Lines Matching full:sc
68 static int rge_reset(struct rge_softc *sc);
69 static void rge_set_phy_power(struct rge_softc *sc, int on);
71 static void rge_mcu_set_version(struct rge_softc *sc, uint64_t mcodever);
72 static void rge_ephy_config_mac_r25(struct rge_softc *sc);
73 static void rge_ephy_config_mac_r25b(struct rge_softc *sc);
74 static void rge_ephy_config_mac_r27(struct rge_softc *sc);
75 static void rge_phy_config_mac_r27(struct rge_softc *sc);
76 static void rge_phy_config_mac_r26(struct rge_softc *sc);
77 static void rge_phy_config_mac_r25(struct rge_softc *sc);
78 static void rge_phy_config_mac_r25b(struct rge_softc *sc);
79 static void rge_phy_config_mac_r25d(struct rge_softc *sc);
80 static void rge_phy_config_mcu(struct rge_softc *sc, uint16_t rcodever);
81 static void rge_hw_init(struct rge_softc *sc);
82 static void rge_disable_phy_ocp_pwrsave(struct rge_softc *sc);
83 static void rge_patch_phy_mcu(struct rge_softc *sc, int set);
84 static void rge_disable_hw_im(struct rge_softc *sc);
85 static void rge_disable_sim_im(struct rge_softc *sc);
86 static void rge_setup_sim_im(struct rge_softc *sc);
87 static void rge_switch_mcu_ram_page(struct rge_softc *sc, int page);
88 static int rge_exit_oob(struct rge_softc *sc);
89 static void rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val);
90 static uint16_t rge_read_ephy(struct rge_softc *sc, uint16_t reg);
91 static uint16_t rge_check_ephy_ext_add(struct rge_softc *sc, uint16_t reg);
92 static void rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val);
95 rge_reset(struct rge_softc *sc) in rge_reset() argument
99 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV | in rge_reset()
104 RGE_SETBIT_1(sc, RGE_PPSW, 0x08); in rge_reset()
106 RGE_SETBIT_1(sc, RGE_CMD, RGE_CMD_STOPREQ); in rge_reset()
107 if (sc->rge_type == MAC_R25) { in rge_reset()
110 if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_STOPREQ)) in rge_reset()
114 RGE_PRINT_ERROR(sc, "failed to stop all requests\n"); in rge_reset()
122 if ((RGE_READ_1(sc, RGE_MCUCMD) & (RGE_MCUCMD_RXFIFO_EMPTY | in rge_reset()
127 if (sc->rge_type != MAC_R25) { in rge_reset()
130 if ((RGE_READ_2(sc, RGE_IM) & 0x0103) == 0x0103) in rge_reset()
135 RGE_WRITE_1(sc, RGE_CMD, in rge_reset()
136 RGE_READ_1(sc, RGE_CMD) & (RGE_CMD_TXENB | RGE_CMD_RXENB)); in rge_reset()
139 RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_RESET); in rge_reset()
143 if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_RESET)) in rge_reset()
147 RGE_PRINT_ERROR(sc, "reset never completed!\n"); in rge_reset()
160 rge_chipinit(struct rge_softc *sc) in rge_chipinit() argument
164 RGE_ASSERT_LOCKED(sc); in rge_chipinit()
166 if ((error = rge_exit_oob(sc)) != 0) in rge_chipinit()
168 rge_set_phy_power(sc, 1); in rge_chipinit()
169 rge_hw_init(sc); in rge_chipinit()
170 rge_hw_reset(sc); in rge_chipinit()
176 rge_set_phy_power(struct rge_softc *sc, int on) in rge_set_phy_power() argument
181 RGE_SETBIT_1(sc, RGE_PMCH, 0xc0); in rge_set_phy_power()
183 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN); in rge_set_phy_power()
186 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 3) in rge_set_phy_power()
191 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN); in rge_set_phy_power()
192 RGE_CLRBIT_1(sc, RGE_PMCH, 0x80); in rge_set_phy_power()
193 RGE_CLRBIT_1(sc, RGE_PPSW, 0x40); in rge_set_phy_power()
198 rge_mac_config_mcu(struct rge_softc *sc, enum rge_mac_type type) in rge_mac_config_mcu() argument
206 rge_switch_mcu_ram_page(sc, npages); in rge_mac_config_mcu()
209 rge_write_mac_ocp(sc, in rge_mac_config_mcu()
213 rge_write_mac_ocp(sc, in rge_mac_config_mcu()
217 rge_write_mac_ocp(sc, in rge_mac_config_mcu()
222 rge_write_mac_ocp(sc, 0xf9f8, 0x6486); in rge_mac_config_mcu()
223 rge_write_mac_ocp(sc, 0xf9fa, 0x0b15); in rge_mac_config_mcu()
224 rge_write_mac_ocp(sc, 0xf9fc, 0x090e); in rge_mac_config_mcu()
225 rge_write_mac_ocp(sc, 0xf9fe, 0x1139); in rge_mac_config_mcu()
228 rge_write_mac_ocp(sc, 0xfc26, 0x8000); in rge_mac_config_mcu()
229 rge_write_mac_ocp(sc, 0xfc2a, 0x0540); in rge_mac_config_mcu()
230 rge_write_mac_ocp(sc, 0xfc2e, 0x0a06); in rge_mac_config_mcu()
231 rge_write_mac_ocp(sc, 0xfc30, 0x0eb8); in rge_mac_config_mcu()
232 rge_write_mac_ocp(sc, 0xfc32, 0x3a5c); in rge_mac_config_mcu()
233 rge_write_mac_ocp(sc, 0xfc34, 0x10a8); in rge_mac_config_mcu()
234 rge_write_mac_ocp(sc, 0xfc40, 0x0d54); in rge_mac_config_mcu()
235 rge_write_mac_ocp(sc, 0xfc42, 0x0e24); in rge_mac_config_mcu()
236 rge_write_mac_ocp(sc, 0xfc48, 0x307a); in rge_mac_config_mcu()
238 rge_switch_mcu_ram_page(sc, 0); in rge_mac_config_mcu()
240 rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg, in rge_mac_config_mcu()
245 rge_switch_mcu_ram_page(sc, npages); in rge_mac_config_mcu()
247 rge_write_mac_ocp(sc, 0xf800, in rge_mac_config_mcu()
249 rge_write_mac_ocp(sc, 0xf802, in rge_mac_config_mcu()
251 rge_write_mac_ocp(sc, 0xf804, in rge_mac_config_mcu()
253 rge_write_mac_ocp(sc, 0xf806, in rge_mac_config_mcu()
255 rge_write_mac_ocp(sc, 0xf808, in rge_mac_config_mcu()
257 rge_write_mac_ocp(sc, 0xf80a, in rge_mac_config_mcu()
259 rge_write_mac_ocp(sc, 0xf80c, in rge_mac_config_mcu()
261 rge_write_mac_ocp(sc, 0xf80e, in rge_mac_config_mcu()
263 rge_write_mac_ocp(sc, 0xf810, in rge_mac_config_mcu()
267 rge_write_mac_ocp(sc, reg, 0); in rge_mac_config_mcu()
269 rge_write_mac_ocp(sc, 0xf9f8, in rge_mac_config_mcu()
271 rge_write_mac_ocp(sc, 0xf9fa, in rge_mac_config_mcu()
273 rge_write_mac_ocp(sc, 0xf9fc, in rge_mac_config_mcu()
275 rge_write_mac_ocp(sc, 0xf9fe, in rge_mac_config_mcu()
278 rge_write_mac_ocp(sc, 0xfc26, 0x8000); in rge_mac_config_mcu()
279 rge_write_mac_ocp(sc, 0xfc28, 0x14a2); in rge_mac_config_mcu()
280 rge_write_mac_ocp(sc, 0xfc48, 0x0001); in rge_mac_config_mcu()
283 if (sc->rge_mcodever != mcodever) { in rge_mac_config_mcu()
285 rge_switch_mcu_ram_page(sc, 0); in rge_mac_config_mcu()
287 rge_write_mac_ocp(sc, rtl8127_mac_bps[i].reg, in rge_mac_config_mcu()
290 rge_switch_mcu_ram_page(sc, 1); in rge_mac_config_mcu()
292 rge_write_mac_ocp(sc, rtl8127_mac_bps[i].reg, in rge_mac_config_mcu()
295 rge_write_mac_ocp(sc, 0xfc26, 0x8000); in rge_mac_config_mcu()
296 rge_write_mac_ocp(sc, 0xfc28, 0x1520); in rge_mac_config_mcu()
297 rge_write_mac_ocp(sc, 0xfc2a, 0x41e0); in rge_mac_config_mcu()
298 rge_write_mac_ocp(sc, 0xfc2c, 0x508c); in rge_mac_config_mcu()
299 rge_write_mac_ocp(sc, 0xfc2e, 0x50f6); in rge_mac_config_mcu()
300 rge_write_mac_ocp(sc, 0xfc30, 0x34fa); in rge_mac_config_mcu()
301 rge_write_mac_ocp(sc, 0xfc32, 0x0166); in rge_mac_config_mcu()
302 rge_write_mac_ocp(sc, 0xfc34, 0x1a6a); in rge_mac_config_mcu()
303 rge_write_mac_ocp(sc, 0xfc36, 0x1a2c); in rge_mac_config_mcu()
304 rge_write_mac_ocp(sc, 0xfc48, 0x00ff); in rge_mac_config_mcu()
307 rge_mcu_set_version(sc, mcodever); in rge_mac_config_mcu()
326 rge_mcu_set_version(struct rge_softc *sc, uint64_t mcodever) in rge_mcu_set_version() argument
331 rge_switch_mcu_ram_page(sc, 2); in rge_mcu_set_version()
334 rge_write_mac_ocp(sc, 0xf9f8 + 6 - i, (uint16_t)mcodever); in rge_mcu_set_version()
339 rge_switch_mcu_ram_page(sc, 0); in rge_mcu_set_version()
343 rge_ephy_config(struct rge_softc *sc) in rge_ephy_config() argument
345 switch (sc->rge_type) { in rge_ephy_config()
347 rge_ephy_config_mac_r25(sc); in rge_ephy_config()
350 rge_ephy_config_mac_r25b(sc); in rge_ephy_config()
353 rge_ephy_config_mac_r27(sc); in rge_ephy_config()
361 rge_ephy_config_mac_r25(struct rge_softc *sc) in rge_ephy_config_mac_r25() argument
367 rge_write_ephy(sc, mac_r25_ephy[i].reg, mac_r25_ephy[i].val); in rge_ephy_config_mac_r25()
369 val = rge_read_ephy(sc, 0x002a) & ~0x7000; in rge_ephy_config_mac_r25()
370 rge_write_ephy(sc, 0x002a, val | 0x3000); in rge_ephy_config_mac_r25()
371 RGE_EPHY_CLRBIT(sc, 0x0019, 0x0040); in rge_ephy_config_mac_r25()
372 RGE_EPHY_SETBIT(sc, 0x001b, 0x0e00); in rge_ephy_config_mac_r25()
373 RGE_EPHY_CLRBIT(sc, 0x001b, 0x7000); in rge_ephy_config_mac_r25()
374 rge_write_ephy(sc, 0x0002, 0x6042); in rge_ephy_config_mac_r25()
375 rge_write_ephy(sc, 0x0006, 0x0014); in rge_ephy_config_mac_r25()
376 val = rge_read_ephy(sc, 0x006a) & ~0x7000; in rge_ephy_config_mac_r25()
377 rge_write_ephy(sc, 0x006a, val | 0x3000); in rge_ephy_config_mac_r25()
378 RGE_EPHY_CLRBIT(sc, 0x0059, 0x0040); in rge_ephy_config_mac_r25()
379 RGE_EPHY_SETBIT(sc, 0x005b, 0x0e00); in rge_ephy_config_mac_r25()
380 RGE_EPHY_CLRBIT(sc, 0x005b, 0x7000); in rge_ephy_config_mac_r25()
381 rge_write_ephy(sc, 0x0042, 0x6042); in rge_ephy_config_mac_r25()
382 rge_write_ephy(sc, 0x0046, 0x0014); in rge_ephy_config_mac_r25()
386 rge_ephy_config_mac_r25b(struct rge_softc *sc) in rge_ephy_config_mac_r25b() argument
391 rge_write_ephy(sc, mac_r25b_ephy[i].reg, mac_r25b_ephy[i].val); in rge_ephy_config_mac_r25b()
395 rge_ephy_config_mac_r27(struct rge_softc *sc) in rge_ephy_config_mac_r27() argument
400 rge_r27_write_ephy(sc, mac_r27_ephy[i].reg, in rge_ephy_config_mac_r27()
404 rge_write_ephy(sc, RGE_EPHYAR_EXT_ADDR, 0); in rge_ephy_config_mac_r27()
408 rge_phy_config(struct rge_softc *sc) in rge_phy_config() argument
413 rge_ephy_config(sc); in rge_phy_config()
416 rge_write_phy(sc, 0, MII_ANAR, in rge_phy_config()
417 rge_read_phy(sc, 0, MII_ANAR) & in rge_phy_config()
419 rge_write_phy(sc, 0, MII_100T2CR, in rge_phy_config()
420 rge_read_phy(sc, 0, MII_100T2CR) & in rge_phy_config()
422 switch (sc->rge_type) { in rge_phy_config()
433 RGE_PHY_CLRBIT(sc, 0xa5d4, val); in rge_phy_config()
434 rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | in rge_phy_config()
437 if (!(rge_read_phy(sc, 0, MII_BMCR) & BMCR_RESET)) in rge_phy_config()
442 RGE_PRINT_ERROR(sc, "PHY reset failed\n"); in rge_phy_config()
447 rge_write_phy_ocp(sc, 0xa436, 0x801e); in rge_phy_config()
448 sc->rge_rcodever = rge_read_phy_ocp(sc, 0xa438); in rge_phy_config()
450 switch (sc->rge_type) { in rge_phy_config()
452 rge_phy_config_mac_r25(sc); in rge_phy_config()
455 rge_phy_config_mac_r25b(sc); in rge_phy_config()
458 rge_phy_config_mac_r25d(sc); in rge_phy_config()
461 rge_phy_config_mac_r26(sc); in rge_phy_config()
464 rge_phy_config_mac_r27(sc); in rge_phy_config()
470 RGE_PHY_CLRBIT(sc, 0xa5b4, 0x8000); in rge_phy_config()
473 RGE_MAC_CLRBIT(sc, 0xe040, 0x0003); in rge_phy_config()
474 if (sc->rge_type == MAC_R25) { in rge_phy_config()
475 RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006); in rge_phy_config()
476 RGE_PHY_CLRBIT(sc, 0xa432, 0x0010); in rge_phy_config()
477 } else if (sc->rge_type == MAC_R25B || sc->rge_type == MAC_R25D) in rge_phy_config()
478 RGE_PHY_SETBIT(sc, 0xa432, 0x0010); in rge_phy_config()
480 RGE_PHY_CLRBIT(sc, 0xa5d0, (sc->rge_type == MAC_R27) ? 0x000e : 0x0006); in rge_phy_config()
481 RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001); in rge_phy_config()
482 if (sc->rge_type == MAC_R26 || sc->rge_type == MAC_R27) in rge_phy_config()
483 RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0002); in rge_phy_config()
484 RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010); in rge_phy_config()
485 RGE_PHY_CLRBIT(sc, 0xa428, 0x0080); in rge_phy_config()
486 RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200); in rge_phy_config()
489 RGE_MAC_CLRBIT(sc, 0xe052, 0x0001); in rge_phy_config()
490 RGE_PHY_CLRBIT(sc, 0xa442, 0x3000); in rge_phy_config()
491 RGE_PHY_CLRBIT(sc, 0xa430, 0x8000); in rge_phy_config()
497 rge_phy_config_mac_r27(struct rge_softc *sc) in rge_phy_config_mac_r27() argument
514 rge_phy_config_mcu(sc, RGE_MAC_R27_RCODE_VER); in rge_phy_config_mac_r27()
516 rge_write_phy_ocp(sc, 0xa4d2, 0x0000); in rge_phy_config_mac_r27()
517 rge_read_phy_ocp(sc, 0xa4d4); in rge_phy_config_mac_r27()
519 RGE_PHY_CLRBIT(sc, 0xa442, 0x0800); in rge_phy_config_mac_r27()
520 rge_write_phy_ocp(sc, 0xa436, 0x8415); in rge_phy_config_mac_r27()
521 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
522 rge_write_phy_ocp(sc, 0xa438, val | 0x9300); in rge_phy_config_mac_r27()
523 rge_write_phy_ocp(sc, 0xa436, 0x81a3); in rge_phy_config_mac_r27()
524 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
525 rge_write_phy_ocp(sc, 0xa438, val | 0x0f00); in rge_phy_config_mac_r27()
526 rge_write_phy_ocp(sc, 0xa436, 0x81ae); in rge_phy_config_mac_r27()
527 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
528 rge_write_phy_ocp(sc, 0xa438, val | 0x0f00); in rge_phy_config_mac_r27()
529 rge_write_phy_ocp(sc, 0xa436, 0x81b9); in rge_phy_config_mac_r27()
530 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
531 rge_write_phy_ocp(sc, 0xa438, val | 0xb900); in rge_phy_config_mac_r27()
532 rge_write_phy_ocp(sc, 0xb87c, 0x83b0); in rge_phy_config_mac_r27()
533 RGE_PHY_CLRBIT(sc,0xb87e, 0x0e00); in rge_phy_config_mac_r27()
534 rge_write_phy_ocp(sc, 0xb87c, 0x83c5); in rge_phy_config_mac_r27()
535 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00); in rge_phy_config_mac_r27()
536 rge_write_phy_ocp(sc, 0xb87c, 0x83da); in rge_phy_config_mac_r27()
537 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00); in rge_phy_config_mac_r27()
538 rge_write_phy_ocp(sc, 0xb87c, 0x83ef); in rge_phy_config_mac_r27()
539 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00); in rge_phy_config_mac_r27()
540 val = rge_read_phy_ocp(sc, 0xbf38) & ~0x01f0; in rge_phy_config_mac_r27()
541 rge_write_phy_ocp(sc, 0xbf38, val | 0x0160); in rge_phy_config_mac_r27()
542 val = rge_read_phy_ocp(sc, 0xbf3a) & ~0x001f; in rge_phy_config_mac_r27()
543 rge_write_phy_ocp(sc, 0xbf3a, val | 0x0014); in rge_phy_config_mac_r27()
544 RGE_PHY_CLRBIT(sc, 0xbf28, 0x6000); in rge_phy_config_mac_r27()
545 RGE_PHY_CLRBIT(sc, 0xbf2c, 0xc000); in rge_phy_config_mac_r27()
546 val = rge_read_phy_ocp(sc, 0xbf28) & ~0x1fff; in rge_phy_config_mac_r27()
547 rge_write_phy_ocp(sc, 0xbf28, val | 0x0187); in rge_phy_config_mac_r27()
548 val = rge_read_phy_ocp(sc, 0xbf2a) & ~0x003f; in rge_phy_config_mac_r27()
549 rge_write_phy_ocp(sc, 0xbf2a, val | 0x0003); in rge_phy_config_mac_r27()
550 rge_write_phy_ocp(sc, 0xa436, 0x8173); in rge_phy_config_mac_r27()
551 rge_write_phy_ocp(sc, 0xa438, 0x8620); in rge_phy_config_mac_r27()
552 rge_write_phy_ocp(sc, 0xa436, 0x8175); in rge_phy_config_mac_r27()
553 rge_write_phy_ocp(sc, 0xa438, 0x8671); in rge_phy_config_mac_r27()
554 rge_write_phy_ocp(sc, 0xa436, 0x817c); in rge_phy_config_mac_r27()
555 RGE_PHY_SETBIT(sc, 0xa438, 0x2000); in rge_phy_config_mac_r27()
556 rge_write_phy_ocp(sc, 0xa436, 0x8187); in rge_phy_config_mac_r27()
557 RGE_PHY_SETBIT(sc, 0xa438, 0x2000); in rge_phy_config_mac_r27()
558 rge_write_phy_ocp(sc, 0xA436, 0x8192); in rge_phy_config_mac_r27()
559 RGE_PHY_SETBIT(sc, 0xA438, 0x2000); in rge_phy_config_mac_r27()
560 rge_write_phy_ocp(sc, 0xA436, 0x819D); in rge_phy_config_mac_r27()
561 RGE_PHY_SETBIT(sc, 0xA438, 0x2000); in rge_phy_config_mac_r27()
562 rge_write_phy_ocp(sc, 0xA436, 0x81A8); in rge_phy_config_mac_r27()
563 RGE_PHY_CLRBIT(sc, 0xA438, 0x2000); in rge_phy_config_mac_r27()
564 rge_write_phy_ocp(sc, 0xA436, 0x81B3); in rge_phy_config_mac_r27()
565 RGE_PHY_CLRBIT(sc, 0xA438, 0x2000); in rge_phy_config_mac_r27()
566 rge_write_phy_ocp(sc, 0xA436, 0x81BE); in rge_phy_config_mac_r27()
567 RGE_PHY_SETBIT(sc, 0xA438, 0x2000); in rge_phy_config_mac_r27()
568 rge_write_phy_ocp(sc, 0xa436, 0x817d); in rge_phy_config_mac_r27()
569 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
570 rge_write_phy_ocp(sc, 0xa438, val | 0xa600); in rge_phy_config_mac_r27()
571 rge_write_phy_ocp(sc, 0xa436, 0x8188); in rge_phy_config_mac_r27()
572 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
573 rge_write_phy_ocp(sc, 0xa438, val | 0xa600); in rge_phy_config_mac_r27()
574 rge_write_phy_ocp(sc, 0xa436, 0x8193); in rge_phy_config_mac_r27()
575 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
576 rge_write_phy_ocp(sc, 0xa438, val | 0xa600); in rge_phy_config_mac_r27()
577 rge_write_phy_ocp(sc, 0xa436, 0x819e); in rge_phy_config_mac_r27()
578 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
579 rge_write_phy_ocp(sc, 0xa438, val | 0xa600); in rge_phy_config_mac_r27()
580 rge_write_phy_ocp(sc, 0xa436, 0x81a9); in rge_phy_config_mac_r27()
581 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
582 rge_write_phy_ocp(sc, 0xa438, val | 0x1400); in rge_phy_config_mac_r27()
583 rge_write_phy_ocp(sc, 0xa436, 0x81b4); in rge_phy_config_mac_r27()
584 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
585 rge_write_phy_ocp(sc, 0xa438, val | 0x1400); in rge_phy_config_mac_r27()
586 rge_write_phy_ocp(sc, 0xa436, 0x81bf); in rge_phy_config_mac_r27()
587 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
588 rge_write_phy_ocp(sc, 0xa438, val | 0xa600); in rge_phy_config_mac_r27()
589 RGE_PHY_CLRBIT(sc, 0xaeaa, 0x0028); in rge_phy_config_mac_r27()
590 rge_write_phy_ocp(sc, 0xb87c, 0x84f0); in rge_phy_config_mac_r27()
591 rge_write_phy_ocp(sc, 0xb87e, 0x201c); in rge_phy_config_mac_r27()
592 rge_write_phy_ocp(sc, 0xb87c, 0x84f2); in rge_phy_config_mac_r27()
593 rge_write_phy_ocp(sc, 0xb87e, 0x3117); in rge_phy_config_mac_r27()
594 rge_write_phy_ocp(sc, 0xaec6, 0x0000); in rge_phy_config_mac_r27()
595 rge_write_phy_ocp(sc, 0xae20, 0xffff); in rge_phy_config_mac_r27()
596 rge_write_phy_ocp(sc, 0xaece, 0xffff); in rge_phy_config_mac_r27()
597 rge_write_phy_ocp(sc, 0xaed2, 0xffff); in rge_phy_config_mac_r27()
598 rge_write_phy_ocp(sc, 0xaec8, 0x0000); in rge_phy_config_mac_r27()
599 RGE_PHY_CLRBIT(sc, 0xaed0, 0x0001); in rge_phy_config_mac_r27()
600 rge_write_phy_ocp(sc, 0xadb8, 0x0150); in rge_phy_config_mac_r27()
601 rge_write_phy_ocp(sc, 0xb87c, 0x8197); in rge_phy_config_mac_r27()
602 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
603 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000); in rge_phy_config_mac_r27()
604 rge_write_phy_ocp(sc, 0xb87c, 0x8231); in rge_phy_config_mac_r27()
605 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
606 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000); in rge_phy_config_mac_r27()
607 rge_write_phy_ocp(sc, 0xb87c, 0x82cb); in rge_phy_config_mac_r27()
608 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
609 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000); in rge_phy_config_mac_r27()
610 rge_write_phy_ocp(sc, 0xb87c, 0x82cd); in rge_phy_config_mac_r27()
611 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
612 rge_write_phy_ocp(sc, 0xb87e, val | 0x5700); in rge_phy_config_mac_r27()
613 rge_write_phy_ocp(sc, 0xb87c, 0x8233); in rge_phy_config_mac_r27()
614 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
615 rge_write_phy_ocp(sc, 0xb87e, val | 0x5700); in rge_phy_config_mac_r27()
616 rge_write_phy_ocp(sc, 0xb87c, 0x8199); in rge_phy_config_mac_r27()
617 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
618 rge_write_phy_ocp(sc, 0xb87e, val | 0x5700); in rge_phy_config_mac_r27()
620 rge_write_phy_ocp(sc, 0xb87c, mac_cfg_value[i]); in rge_phy_config_mac_r27()
621 rge_write_phy_ocp(sc, 0xb87e, mac_cfg_value[i + 1]); in rge_phy_config_mac_r27()
623 rge_write_phy_ocp(sc, 0xb87c, 0x84f7); in rge_phy_config_mac_r27()
624 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
625 rge_write_phy_ocp(sc, 0xb87e, val | 0x2800); in rge_phy_config_mac_r27()
626 RGE_PHY_SETBIT(sc, 0xaec2, 0x1000); in rge_phy_config_mac_r27()
627 rge_write_phy_ocp(sc, 0xb87c, 0x81b3); in rge_phy_config_mac_r27()
628 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
629 rge_write_phy_ocp(sc, 0xb87e, val | 0xad00); in rge_phy_config_mac_r27()
630 rge_write_phy_ocp(sc, 0xb87c, 0x824d); in rge_phy_config_mac_r27()
631 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
632 rge_write_phy_ocp(sc, 0xb87e, val | 0xad00); in rge_phy_config_mac_r27()
633 rge_write_phy_ocp(sc, 0xb87c, 0x82e7); in rge_phy_config_mac_r27()
634 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
635 rge_write_phy_ocp(sc, 0xb87e, val | 0xad00); in rge_phy_config_mac_r27()
636 val = rge_read_phy_ocp(sc, 0xae4e) & ~0x000f; in rge_phy_config_mac_r27()
637 rge_write_phy_ocp(sc, 0xae4e, val | 0x0001); in rge_phy_config_mac_r27()
638 rge_write_phy_ocp(sc, 0xb87c, 0x82ce); in rge_phy_config_mac_r27()
639 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xf000; in rge_phy_config_mac_r27()
640 rge_write_phy_ocp(sc, 0xb87e, val | 0x4000); in rge_phy_config_mac_r27()
641 rge_write_phy_ocp(sc, 0xb87c, 0x84ac); in rge_phy_config_mac_r27()
642 rge_write_phy_ocp(sc, 0xb87e, 0x0000); in rge_phy_config_mac_r27()
643 rge_write_phy_ocp(sc, 0xb87c, 0x84ae); in rge_phy_config_mac_r27()
644 rge_write_phy_ocp(sc, 0xb87e, 0x0000); in rge_phy_config_mac_r27()
645 rge_write_phy_ocp(sc, 0xb87c, 0x84b0); in rge_phy_config_mac_r27()
646 rge_write_phy_ocp(sc, 0xb87e, 0xf818); in rge_phy_config_mac_r27()
647 rge_write_phy_ocp(sc, 0xb87c, 0x84b2); in rge_phy_config_mac_r27()
648 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
649 rge_write_phy_ocp(sc, 0xb87e, val | 0x6000); in rge_phy_config_mac_r27()
650 rge_write_phy_ocp(sc, 0xb87c, 0x8ffc); in rge_phy_config_mac_r27()
651 rge_write_phy_ocp(sc, 0xb87e, 0x6008); in rge_phy_config_mac_r27()
652 rge_write_phy_ocp(sc, 0xb87c, 0x8ffe); in rge_phy_config_mac_r27()
653 rge_write_phy_ocp(sc, 0xb87e, 0xf450); in rge_phy_config_mac_r27()
654 rge_write_phy_ocp(sc, 0xb87c, 0x8015); in rge_phy_config_mac_r27()
655 RGE_PHY_SETBIT(sc, 0xb87e, 0x0200); in rge_phy_config_mac_r27()
656 rge_write_phy_ocp(sc, 0xb87c, 0x8016); in rge_phy_config_mac_r27()
657 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0800); in rge_phy_config_mac_r27()
658 rge_write_phy_ocp(sc, 0xb87c, 0x8fe6); in rge_phy_config_mac_r27()
659 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
660 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); in rge_phy_config_mac_r27()
661 rge_write_phy_ocp(sc, 0xb87c, 0x8fe4); in rge_phy_config_mac_r27()
662 rge_write_phy_ocp(sc, 0xb87e, 0x2114); in rge_phy_config_mac_r27()
663 rge_write_phy_ocp(sc, 0xb87c, 0x8647); in rge_phy_config_mac_r27()
664 rge_write_phy_ocp(sc, 0xb87e, 0xa7B1); in rge_phy_config_mac_r27()
665 rge_write_phy_ocp(sc, 0xb87c, 0x8649); in rge_phy_config_mac_r27()
666 rge_write_phy_ocp(sc, 0xb87e, 0xbbca); in rge_phy_config_mac_r27()
667 rge_write_phy_ocp(sc, 0xb87c, 0x864b); in rge_phy_config_mac_r27()
668 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
669 rge_write_phy_ocp(sc, 0xb87e, val | 0xdc00); in rge_phy_config_mac_r27()
670 rge_write_phy_ocp(sc, 0xb87c, 0x8154); in rge_phy_config_mac_r27()
671 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xc000; in rge_phy_config_mac_r27()
672 rge_write_phy_ocp(sc, 0xb87e, val | 0x4000); in rge_phy_config_mac_r27()
673 rge_write_phy_ocp(sc, 0xb87c, 0x8158); in rge_phy_config_mac_r27()
674 RGE_PHY_CLRBIT(sc, 0xb87e, 0xc000); in rge_phy_config_mac_r27()
675 rge_write_phy_ocp(sc, 0xb87c, 0x826c); in rge_phy_config_mac_r27()
676 rge_write_phy_ocp(sc, 0xb87e, 0xffff); in rge_phy_config_mac_r27()
677 rge_write_phy_ocp(sc, 0xb87c, 0x826e); in rge_phy_config_mac_r27()
678 rge_write_phy_ocp(sc, 0xb87e, 0xffff); in rge_phy_config_mac_r27()
679 rge_write_phy_ocp(sc, 0xb87c, 0x8872); in rge_phy_config_mac_r27()
680 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
681 rge_write_phy_ocp(sc, 0xb87e, val | 0x0e00); in rge_phy_config_mac_r27()
682 rge_write_phy_ocp(sc, 0xa436, 0x8012); in rge_phy_config_mac_r27()
683 RGE_PHY_SETBIT(sc, 0xa438, 0x0800); in rge_phy_config_mac_r27()
684 rge_write_phy_ocp(sc, 0xa436, 0x8012); in rge_phy_config_mac_r27()
685 RGE_PHY_SETBIT(sc, 0xa438, 0x4000); in rge_phy_config_mac_r27()
686 RGE_PHY_SETBIT(sc, 0xb576, 0x0001); in rge_phy_config_mac_r27()
687 rge_write_phy_ocp(sc, 0xa436, 0x834a); in rge_phy_config_mac_r27()
688 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
689 rge_write_phy_ocp(sc, 0xa438, val | 0x0700); in rge_phy_config_mac_r27()
690 rge_write_phy_ocp(sc, 0xb87c, 0x8217); in rge_phy_config_mac_r27()
691 val = rge_read_phy_ocp(sc, 0xb87e) & ~0x3f00; in rge_phy_config_mac_r27()
692 rge_write_phy_ocp(sc, 0xb87e, val | 0x2a00); in rge_phy_config_mac_r27()
693 rge_write_phy_ocp(sc, 0xa436, 0x81b1); in rge_phy_config_mac_r27()
694 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
695 rge_write_phy_ocp(sc, 0xa438, val | 0x0b00); in rge_phy_config_mac_r27()
696 rge_write_phy_ocp(sc, 0xb87c, 0x8fed); in rge_phy_config_mac_r27()
697 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
698 rge_write_phy_ocp(sc, 0xb87e, val | 0x4e00); in rge_phy_config_mac_r27()
699 rge_write_phy_ocp(sc, 0xb87c, 0x88ac); in rge_phy_config_mac_r27()
700 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
701 rge_write_phy_ocp(sc, 0xb87e, val | 0x2300); in rge_phy_config_mac_r27()
702 RGE_PHY_SETBIT(sc, 0xbf0c, 0x3800); in rge_phy_config_mac_r27()
703 rge_write_phy_ocp(sc, 0xb87c, 0x88de); in rge_phy_config_mac_r27()
704 RGE_PHY_CLRBIT(sc, 0xb87e, 0xFF00); in rge_phy_config_mac_r27()
705 rge_write_phy_ocp(sc, 0xb87c, 0x80B4); in rge_phy_config_mac_r27()
706 rge_write_phy_ocp(sc, 0xb87e, 0x5195); in rge_phy_config_mac_r27()
707 rge_write_phy_ocp(sc, 0xa436, 0x8370); in rge_phy_config_mac_r27()
708 rge_write_phy_ocp(sc, 0xa438, 0x8671); in rge_phy_config_mac_r27()
709 rge_write_phy_ocp(sc, 0xa436, 0x8372); in rge_phy_config_mac_r27()
710 rge_write_phy_ocp(sc, 0xa438, 0x86c8); in rge_phy_config_mac_r27()
711 rge_write_phy_ocp(sc, 0xa436, 0x8401); in rge_phy_config_mac_r27()
712 rge_write_phy_ocp(sc, 0xa438, 0x86c8); in rge_phy_config_mac_r27()
713 rge_write_phy_ocp(sc, 0xa436, 0x8403); in rge_phy_config_mac_r27()
714 rge_write_phy_ocp(sc, 0xa438, 0x86da); in rge_phy_config_mac_r27()
715 rge_write_phy_ocp(sc, 0xa436, 0x8406); in rge_phy_config_mac_r27()
716 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; in rge_phy_config_mac_r27()
717 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); in rge_phy_config_mac_r27()
718 rge_write_phy_ocp(sc, 0xa436, 0x8408); in rge_phy_config_mac_r27()
719 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; in rge_phy_config_mac_r27()
720 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); in rge_phy_config_mac_r27()
721 rge_write_phy_ocp(sc, 0xa436, 0x840a); in rge_phy_config_mac_r27()
722 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; in rge_phy_config_mac_r27()
723 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); in rge_phy_config_mac_r27()
724 rge_write_phy_ocp(sc, 0xa436, 0x840c); in rge_phy_config_mac_r27()
725 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; in rge_phy_config_mac_r27()
726 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); in rge_phy_config_mac_r27()
727 rge_write_phy_ocp(sc, 0xa436, 0x840e); in rge_phy_config_mac_r27()
728 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; in rge_phy_config_mac_r27()
729 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); in rge_phy_config_mac_r27()
730 rge_write_phy_ocp(sc, 0xa436, 0x8410); in rge_phy_config_mac_r27()
731 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; in rge_phy_config_mac_r27()
732 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); in rge_phy_config_mac_r27()
733 rge_write_phy_ocp(sc, 0xa436, 0x8412); in rge_phy_config_mac_r27()
734 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; in rge_phy_config_mac_r27()
735 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); in rge_phy_config_mac_r27()
736 rge_write_phy_ocp(sc, 0xa436, 0x8414); in rge_phy_config_mac_r27()
737 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; in rge_phy_config_mac_r27()
738 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); in rge_phy_config_mac_r27()
739 rge_write_phy_ocp(sc, 0xa436, 0x8416); in rge_phy_config_mac_r27()
740 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; in rge_phy_config_mac_r27()
741 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); in rge_phy_config_mac_r27()
742 rge_write_phy_ocp(sc, 0xa436, 0x82bd); in rge_phy_config_mac_r27()
743 rge_write_phy_ocp(sc, 0xa438, 0x1f40); in rge_phy_config_mac_r27()
744 val = rge_read_phy_ocp(sc, 0xbfb4) & ~0x07ff; in rge_phy_config_mac_r27()
745 rge_write_phy_ocp(sc, 0xbfb4, val | 0x0328); in rge_phy_config_mac_r27()
746 rge_write_phy_ocp(sc, 0xbfb6, 0x3e14); in rge_phy_config_mac_r27()
747 rge_write_phy_ocp(sc, 0xa436, 0x81c4); in rge_phy_config_mac_r27()
749 rge_write_phy_ocp(sc, 0xa438, mac_cfg_a438_value[i]); in rge_phy_config_mac_r27()
751 rge_write_phy_ocp(sc, 0xb87c, mac_cfg2_value[i]); in rge_phy_config_mac_r27()
752 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_value[i + 1]); in rge_phy_config_mac_r27()
754 rge_write_phy_ocp(sc, 0xb87c, 0x88d5); in rge_phy_config_mac_r27()
755 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r27()
756 rge_write_phy_ocp(sc, 0xb87e, val | 0x0200); in rge_phy_config_mac_r27()
757 rge_write_phy_ocp(sc, 0xa436, 0x84bb); in rge_phy_config_mac_r27()
758 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
759 rge_write_phy_ocp(sc, 0xa438, val | 0x0a00); in rge_phy_config_mac_r27()
760 rge_write_phy_ocp(sc, 0xa436, 0x84c0); in rge_phy_config_mac_r27()
761 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r27()
762 rge_write_phy_ocp(sc, 0xa438, val | 0x1600); in rge_phy_config_mac_r27()
763 RGE_PHY_SETBIT(sc, 0xa430, 0x0003); in rge_phy_config_mac_r27()
767 rge_phy_config_mac_r26(struct rge_softc *sc) in rge_phy_config_mac_r26() argument
784 rge_phy_config_mcu(sc, RGE_MAC_R26_RCODE_VER); in rge_phy_config_mac_r26()
786 RGE_PHY_SETBIT(sc, 0xa442, 0x0800); in rge_phy_config_mac_r26()
787 rge_write_phy_ocp(sc, 0xa436, 0x80bf); in rge_phy_config_mac_r26()
788 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r26()
789 rge_write_phy_ocp(sc, 0xa438, val | 0xed00); in rge_phy_config_mac_r26()
790 rge_write_phy_ocp(sc, 0xa436, 0x80cd); in rge_phy_config_mac_r26()
791 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r26()
792 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); in rge_phy_config_mac_r26()
793 rge_write_phy_ocp(sc, 0xa436, 0x80d1); in rge_phy_config_mac_r26()
794 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r26()
795 rge_write_phy_ocp(sc, 0xa438, val | 0xc800); in rge_phy_config_mac_r26()
796 rge_write_phy_ocp(sc, 0xa436, 0x80d4); in rge_phy_config_mac_r26()
797 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r26()
798 rge_write_phy_ocp(sc, 0xa438, val | 0xc800); in rge_phy_config_mac_r26()
799 rge_write_phy_ocp(sc, 0xa436, 0x80e1); in rge_phy_config_mac_r26()
800 rge_write_phy_ocp(sc, 0xa438, 0x10cc); in rge_phy_config_mac_r26()
801 rge_write_phy_ocp(sc, 0xa436, 0x80e5); in rge_phy_config_mac_r26()
802 rge_write_phy_ocp(sc, 0xa438, 0x4f0c); in rge_phy_config_mac_r26()
803 rge_write_phy_ocp(sc, 0xa436, 0x8387); in rge_phy_config_mac_r26()
804 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r26()
805 rge_write_phy_ocp(sc, 0xa438, val | 0x4700); in rge_phy_config_mac_r26()
806 val = rge_read_phy_ocp(sc, 0xa80c) & ~0x00c0; in rge_phy_config_mac_r26()
807 rge_write_phy_ocp(sc, 0xa80c, val | 0x0080); in rge_phy_config_mac_r26()
808 RGE_PHY_CLRBIT(sc, 0xac90, 0x0010); in rge_phy_config_mac_r26()
809 RGE_PHY_CLRBIT(sc, 0xad2c, 0x8000); in rge_phy_config_mac_r26()
810 rge_write_phy_ocp(sc, 0xb87c, 0x8321); in rge_phy_config_mac_r26()
811 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
812 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); in rge_phy_config_mac_r26()
813 RGE_PHY_SETBIT(sc, 0xacf8, 0x000c); in rge_phy_config_mac_r26()
814 rge_write_phy_ocp(sc, 0xa436, 0x8183); in rge_phy_config_mac_r26()
815 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r26()
816 rge_write_phy_ocp(sc, 0xa438, val | 0x5900); in rge_phy_config_mac_r26()
817 RGE_PHY_SETBIT(sc, 0xad94, 0x0020); in rge_phy_config_mac_r26()
818 RGE_PHY_CLRBIT(sc, 0xa654, 0x0800); in rge_phy_config_mac_r26()
819 RGE_PHY_SETBIT(sc, 0xb648, 0x4000); in rge_phy_config_mac_r26()
820 rge_write_phy_ocp(sc, 0xb87c, 0x839e); in rge_phy_config_mac_r26()
821 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
822 rge_write_phy_ocp(sc, 0xb87e, val | 0x2f00); in rge_phy_config_mac_r26()
823 rge_write_phy_ocp(sc, 0xb87c, 0x83f2); in rge_phy_config_mac_r26()
824 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
825 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); in rge_phy_config_mac_r26()
826 RGE_PHY_SETBIT(sc, 0xada0, 0x0002); in rge_phy_config_mac_r26()
827 rge_write_phy_ocp(sc, 0xb87c, 0x80f3); in rge_phy_config_mac_r26()
828 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
829 rge_write_phy_ocp(sc, 0xb87e, val | 0x9900); in rge_phy_config_mac_r26()
830 rge_write_phy_ocp(sc, 0xb87c, 0x8126); in rge_phy_config_mac_r26()
831 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
832 rge_write_phy_ocp(sc, 0xb87e, val | 0xc100); in rge_phy_config_mac_r26()
833 rge_write_phy_ocp(sc, 0xb87c, 0x893a); in rge_phy_config_mac_r26()
834 rge_write_phy_ocp(sc, 0xb87e, 0x8080); in rge_phy_config_mac_r26()
835 rge_write_phy_ocp(sc, 0xb87c, 0x8647); in rge_phy_config_mac_r26()
836 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
837 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600); in rge_phy_config_mac_r26()
838 rge_write_phy_ocp(sc, 0xb87c, 0x862c); in rge_phy_config_mac_r26()
839 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
840 rge_write_phy_ocp(sc, 0xb87e, val | 0x1200); in rge_phy_config_mac_r26()
841 rge_write_phy_ocp(sc, 0xb87c, 0x864a); in rge_phy_config_mac_r26()
842 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
843 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600); in rge_phy_config_mac_r26()
844 rge_write_phy_ocp(sc, 0xb87c, 0x80a0); in rge_phy_config_mac_r26()
845 rge_write_phy_ocp(sc, 0xb87e, 0xbcbc); in rge_phy_config_mac_r26()
846 rge_write_phy_ocp(sc, 0xb87c, 0x805e); in rge_phy_config_mac_r26()
847 rge_write_phy_ocp(sc, 0xb87e, 0xbcbc); in rge_phy_config_mac_r26()
848 rge_write_phy_ocp(sc, 0xb87c, 0x8056); in rge_phy_config_mac_r26()
849 rge_write_phy_ocp(sc, 0xb87e, 0x3077); in rge_phy_config_mac_r26()
850 rge_write_phy_ocp(sc, 0xb87c, 0x8058); in rge_phy_config_mac_r26()
851 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
852 rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00); in rge_phy_config_mac_r26()
853 rge_write_phy_ocp(sc, 0xb87c, 0x8098); in rge_phy_config_mac_r26()
854 rge_write_phy_ocp(sc, 0xb87e, 0x3077); in rge_phy_config_mac_r26()
855 rge_write_phy_ocp(sc, 0xb87c, 0x809a); in rge_phy_config_mac_r26()
856 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
857 rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00); in rge_phy_config_mac_r26()
858 rge_write_phy_ocp(sc, 0xb87c, 0x8052); in rge_phy_config_mac_r26()
859 rge_write_phy_ocp(sc, 0xb87e, 0x3733); in rge_phy_config_mac_r26()
860 rge_write_phy_ocp(sc, 0xb87c, 0x8094); in rge_phy_config_mac_r26()
861 rge_write_phy_ocp(sc, 0xb87e, 0x3733); in rge_phy_config_mac_r26()
862 rge_write_phy_ocp(sc, 0xb87c, 0x807f); in rge_phy_config_mac_r26()
863 rge_write_phy_ocp(sc, 0xb87e, 0x7c75); in rge_phy_config_mac_r26()
864 rge_write_phy_ocp(sc, 0xb87c, 0x803d); in rge_phy_config_mac_r26()
865 rge_write_phy_ocp(sc, 0xb87e, 0x7c75); in rge_phy_config_mac_r26()
866 rge_write_phy_ocp(sc, 0xb87c, 0x8036); in rge_phy_config_mac_r26()
867 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
868 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000); in rge_phy_config_mac_r26()
869 rge_write_phy_ocp(sc, 0xb87c, 0x8078); in rge_phy_config_mac_r26()
870 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
871 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000); in rge_phy_config_mac_r26()
872 rge_write_phy_ocp(sc, 0xb87c, 0x8031); in rge_phy_config_mac_r26()
873 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
874 rge_write_phy_ocp(sc, 0xb87e, val | 0x3300); in rge_phy_config_mac_r26()
875 rge_write_phy_ocp(sc, 0xb87c, 0x8073); in rge_phy_config_mac_r26()
876 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
877 rge_write_phy_ocp(sc, 0xb87e, val | 0x3300); in rge_phy_config_mac_r26()
878 val = rge_read_phy_ocp(sc, 0xae06) & ~0xfc00; in rge_phy_config_mac_r26()
879 rge_write_phy_ocp(sc, 0xae06, val | 0x7c00); in rge_phy_config_mac_r26()
880 rge_write_phy_ocp(sc, 0xb87c, 0x89D1); in rge_phy_config_mac_r26()
881 rge_write_phy_ocp(sc, 0xb87e, 0x0004); in rge_phy_config_mac_r26()
882 rge_write_phy_ocp(sc, 0xa436, 0x8fbd); in rge_phy_config_mac_r26()
883 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r26()
884 rge_write_phy_ocp(sc, 0xa438, val | 0x0a00); in rge_phy_config_mac_r26()
885 rge_write_phy_ocp(sc, 0xa436, 0x8fbe); in rge_phy_config_mac_r26()
886 rge_write_phy_ocp(sc, 0xa438, 0x0d09); in rge_phy_config_mac_r26()
887 rge_write_phy_ocp(sc, 0xb87c, 0x89cd); in rge_phy_config_mac_r26()
888 rge_write_phy_ocp(sc, 0xb87e, 0x0f0f); in rge_phy_config_mac_r26()
889 rge_write_phy_ocp(sc, 0xb87c, 0x89cf); in rge_phy_config_mac_r26()
890 rge_write_phy_ocp(sc, 0xb87e, 0x0f0f); in rge_phy_config_mac_r26()
891 rge_write_phy_ocp(sc, 0xb87c, 0x83a4); in rge_phy_config_mac_r26()
892 rge_write_phy_ocp(sc, 0xb87e, 0x6600); in rge_phy_config_mac_r26()
893 rge_write_phy_ocp(sc, 0xb87c, 0x83a6); in rge_phy_config_mac_r26()
894 rge_write_phy_ocp(sc, 0xb87e, 0x6601); in rge_phy_config_mac_r26()
895 rge_write_phy_ocp(sc, 0xb87c, 0x83c0); in rge_phy_config_mac_r26()
896 rge_write_phy_ocp(sc, 0xb87e, 0x6600); in rge_phy_config_mac_r26()
897 rge_write_phy_ocp(sc, 0xb87c, 0x83c2); in rge_phy_config_mac_r26()
898 rge_write_phy_ocp(sc, 0xb87e, 0x6601); in rge_phy_config_mac_r26()
899 rge_write_phy_ocp(sc, 0xb87c, 0x8414); in rge_phy_config_mac_r26()
900 rge_write_phy_ocp(sc, 0xb87e, 0x6600); in rge_phy_config_mac_r26()
901 rge_write_phy_ocp(sc, 0xb87c, 0x8416); in rge_phy_config_mac_r26()
902 rge_write_phy_ocp(sc, 0xb87e, 0x6601); in rge_phy_config_mac_r26()
903 rge_write_phy_ocp(sc, 0xb87c, 0x83f8); in rge_phy_config_mac_r26()
904 rge_write_phy_ocp(sc, 0xb87e, 0x6600); in rge_phy_config_mac_r26()
905 rge_write_phy_ocp(sc, 0xb87c, 0x83fa); in rge_phy_config_mac_r26()
906 rge_write_phy_ocp(sc, 0xb87e, 0x6601); in rge_phy_config_mac_r26()
908 rge_patch_phy_mcu(sc, 1); in rge_phy_config_mac_r26()
909 val = rge_read_phy_ocp(sc, 0xbd96) & ~0x1f00; in rge_phy_config_mac_r26()
910 rge_write_phy_ocp(sc, 0xbd96, val | 0x1000); in rge_phy_config_mac_r26()
911 val = rge_read_phy_ocp(sc, 0xbf1c) & ~0x0007; in rge_phy_config_mac_r26()
912 rge_write_phy_ocp(sc, 0xbf1c, val | 0x0007); in rge_phy_config_mac_r26()
913 RGE_PHY_CLRBIT(sc, 0xbfbe, 0x8000); in rge_phy_config_mac_r26()
914 val = rge_read_phy_ocp(sc, 0xbf40) & ~0x0380; in rge_phy_config_mac_r26()
915 rge_write_phy_ocp(sc, 0xbf40, val | 0x0280); in rge_phy_config_mac_r26()
916 val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0080; in rge_phy_config_mac_r26()
917 rge_write_phy_ocp(sc, 0xbf90, val | 0x0060); in rge_phy_config_mac_r26()
918 val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0010; in rge_phy_config_mac_r26()
919 rge_write_phy_ocp(sc, 0xbf90, val | 0x000c); in rge_phy_config_mac_r26()
920 rge_patch_phy_mcu(sc, 0); in rge_phy_config_mac_r26()
922 rge_write_phy_ocp(sc, 0xa436, 0x843b); in rge_phy_config_mac_r26()
923 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r26()
924 rge_write_phy_ocp(sc, 0xa438, val | 0x2000); in rge_phy_config_mac_r26()
925 rge_write_phy_ocp(sc, 0xa436, 0x843d); in rge_phy_config_mac_r26()
926 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r26()
927 rge_write_phy_ocp(sc, 0xa438, val | 0x2000); in rge_phy_config_mac_r26()
928 RGE_PHY_CLRBIT(sc, 0xb516, 0x007f); in rge_phy_config_mac_r26()
929 RGE_PHY_CLRBIT(sc, 0xbf80, 0x0030); in rge_phy_config_mac_r26()
931 rge_write_phy_ocp(sc, 0xa436, 0x8188); in rge_phy_config_mac_r26()
933 rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]); in rge_phy_config_mac_r26()
935 rge_write_phy_ocp(sc, 0xb87c, 0x8015); in rge_phy_config_mac_r26()
936 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
937 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); in rge_phy_config_mac_r26()
938 rge_write_phy_ocp(sc, 0xb87c, 0x8ffd); in rge_phy_config_mac_r26()
939 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
940 rge_write_phy_ocp(sc, 0xb87e, val | 0); in rge_phy_config_mac_r26()
941 rge_write_phy_ocp(sc, 0xb87c, 0x8fff); in rge_phy_config_mac_r26()
942 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
943 rge_write_phy_ocp(sc, 0xb87e, val | 0x7f00); in rge_phy_config_mac_r26()
944 rge_write_phy_ocp(sc, 0xb87c, 0x8ffb); in rge_phy_config_mac_r26()
945 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
946 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_r26()
947 rge_write_phy_ocp(sc, 0xb87c, 0x8fe9); in rge_phy_config_mac_r26()
948 rge_write_phy_ocp(sc, 0xb87e, 0x0002); in rge_phy_config_mac_r26()
949 rge_write_phy_ocp(sc, 0xb87c, 0x8fef); in rge_phy_config_mac_r26()
950 rge_write_phy_ocp(sc, 0xb87e, 0x00a5); in rge_phy_config_mac_r26()
951 rge_write_phy_ocp(sc, 0xb87c, 0x8ff1); in rge_phy_config_mac_r26()
952 rge_write_phy_ocp(sc, 0xb87e, 0x0106); in rge_phy_config_mac_r26()
953 rge_write_phy_ocp(sc, 0xb87c, 0x8fe1); in rge_phy_config_mac_r26()
954 rge_write_phy_ocp(sc, 0xb87e, 0x0102); in rge_phy_config_mac_r26()
955 rge_write_phy_ocp(sc, 0xb87c, 0x8fe3); in rge_phy_config_mac_r26()
956 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
957 rge_write_phy_ocp(sc, 0xb87e, val | 0x0400); in rge_phy_config_mac_r26()
958 RGE_PHY_SETBIT(sc, 0xa654, 0x0800); in rge_phy_config_mac_r26()
959 RGE_PHY_CLRBIT(sc, 0xa654, 0x0003); in rge_phy_config_mac_r26()
960 rge_write_phy_ocp(sc, 0xac3a, 0x5851); in rge_phy_config_mac_r26()
961 val = rge_read_phy_ocp(sc, 0xac3c) & ~0xd000; in rge_phy_config_mac_r26()
962 rge_write_phy_ocp(sc, 0xac3c, val | 0x2000); in rge_phy_config_mac_r26()
963 val = rge_read_phy_ocp(sc, 0xac42) & ~0x0200; in rge_phy_config_mac_r26()
964 rge_write_phy_ocp(sc, 0xac42, val | 0x01c0); in rge_phy_config_mac_r26()
965 RGE_PHY_CLRBIT(sc, 0xac3e, 0xe000); in rge_phy_config_mac_r26()
966 RGE_PHY_CLRBIT(sc, 0xac42, 0x0038); in rge_phy_config_mac_r26()
967 val = rge_read_phy_ocp(sc, 0xac42) & ~0x0002; in rge_phy_config_mac_r26()
968 rge_write_phy_ocp(sc, 0xac42, val | 0x0005); in rge_phy_config_mac_r26()
969 rge_write_phy_ocp(sc, 0xac1a, 0x00db); in rge_phy_config_mac_r26()
970 rge_write_phy_ocp(sc, 0xade4, 0x01b5); in rge_phy_config_mac_r26()
971 RGE_PHY_CLRBIT(sc, 0xad9c, 0x0c00); in rge_phy_config_mac_r26()
972 rge_write_phy_ocp(sc, 0xb87c, 0x814b); in rge_phy_config_mac_r26()
973 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
974 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); in rge_phy_config_mac_r26()
975 rge_write_phy_ocp(sc, 0xb87c, 0x814d); in rge_phy_config_mac_r26()
976 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
977 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); in rge_phy_config_mac_r26()
978 rge_write_phy_ocp(sc, 0xb87c, 0x814f); in rge_phy_config_mac_r26()
979 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
980 rge_write_phy_ocp(sc, 0xb87e, val | 0x0b00); in rge_phy_config_mac_r26()
981 rge_write_phy_ocp(sc, 0xb87c, 0x8142); in rge_phy_config_mac_r26()
982 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
983 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_r26()
984 rge_write_phy_ocp(sc, 0xb87c, 0x8144); in rge_phy_config_mac_r26()
985 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
986 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_r26()
987 rge_write_phy_ocp(sc, 0xb87c, 0x8150); in rge_phy_config_mac_r26()
988 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
989 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_r26()
990 rge_write_phy_ocp(sc, 0xb87c, 0x8118); in rge_phy_config_mac_r26()
991 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
992 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); in rge_phy_config_mac_r26()
993 rge_write_phy_ocp(sc, 0xb87c, 0x811a); in rge_phy_config_mac_r26()
994 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
995 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); in rge_phy_config_mac_r26()
996 rge_write_phy_ocp(sc, 0xb87c, 0x811c); in rge_phy_config_mac_r26()
997 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
998 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); in rge_phy_config_mac_r26()
999 rge_write_phy_ocp(sc, 0xb87c, 0x810f); in rge_phy_config_mac_r26()
1000 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
1001 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_r26()
1002 rge_write_phy_ocp(sc, 0xb87c, 0x8111); in rge_phy_config_mac_r26()
1003 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
1004 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_r26()
1005 rge_write_phy_ocp(sc, 0xb87c, 0x811d); in rge_phy_config_mac_r26()
1006 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
1007 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_r26()
1008 RGE_PHY_SETBIT(sc, 0xac36, 0x1000); in rge_phy_config_mac_r26()
1009 RGE_PHY_CLRBIT(sc, 0xad1c, 0x0100); in rge_phy_config_mac_r26()
1010 val = rge_read_phy_ocp(sc, 0xade8) & ~0xffc0; in rge_phy_config_mac_r26()
1011 rge_write_phy_ocp(sc, 0xade8, val | 0x1400); in rge_phy_config_mac_r26()
1012 rge_write_phy_ocp(sc, 0xb87c, 0x864b); in rge_phy_config_mac_r26()
1013 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
1014 rge_write_phy_ocp(sc, 0xb87e, val | 0x9d00); in rge_phy_config_mac_r26()
1016 rge_write_phy_ocp(sc, 0xa436, 0x8f97); in rge_phy_config_mac_r26()
1018 rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]); in rge_phy_config_mac_r26()
1020 RGE_PHY_SETBIT(sc, 0xad9c, 0x0020); in rge_phy_config_mac_r26()
1021 rge_write_phy_ocp(sc, 0xb87c, 0x8122); in rge_phy_config_mac_r26()
1022 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
1023 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00); in rge_phy_config_mac_r26()
1025 rge_write_phy_ocp(sc, 0xb87c, 0x82c8); in rge_phy_config_mac_r26()
1027 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]); in rge_phy_config_mac_r26()
1029 rge_write_phy_ocp(sc, 0xb87c, 0x80ef); in rge_phy_config_mac_r26()
1030 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
1031 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00); in rge_phy_config_mac_r26()
1033 rge_write_phy_ocp(sc, 0xb87c, 0x82a0); in rge_phy_config_mac_r26()
1035 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]); in rge_phy_config_mac_r26()
1037 rge_write_phy_ocp(sc, 0xa436, 0x8018); in rge_phy_config_mac_r26()
1038 RGE_PHY_SETBIT(sc, 0xa438, 0x2000); in rge_phy_config_mac_r26()
1039 rge_write_phy_ocp(sc, 0xb87c, 0x8fe4); in rge_phy_config_mac_r26()
1040 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r26()
1041 rge_write_phy_ocp(sc, 0xb87e, val | 0); in rge_phy_config_mac_r26()
1042 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xffc0; in rge_phy_config_mac_r26()
1043 rge_write_phy_ocp(sc, 0xb54c, val | 0x3700); in rge_phy_config_mac_r26()
1047 rge_phy_config_mac_r25(struct rge_softc *sc) in rge_phy_config_mac_r25() argument
1063 rge_phy_config_mcu(sc, RGE_MAC_R25_RCODE_VER); in rge_phy_config_mac_r25()
1065 RGE_PHY_SETBIT(sc, 0xad4e, 0x0010); in rge_phy_config_mac_r25()
1066 val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff; in rge_phy_config_mac_r25()
1067 rge_write_phy_ocp(sc, 0xad16, val | 0x03ff); in rge_phy_config_mac_r25()
1068 val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f; in rge_phy_config_mac_r25()
1069 rge_write_phy_ocp(sc, 0xad32, val | 0x0006); in rge_phy_config_mac_r25()
1070 RGE_PHY_CLRBIT(sc, 0xac08, 0x1000); in rge_phy_config_mac_r25()
1071 RGE_PHY_CLRBIT(sc, 0xac08, 0x0100); in rge_phy_config_mac_r25()
1072 val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003; in rge_phy_config_mac_r25()
1073 rge_write_phy_ocp(sc, 0xacc0, val | 0x0002); in rge_phy_config_mac_r25()
1074 val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0; in rge_phy_config_mac_r25()
1075 rge_write_phy_ocp(sc, 0xad40, val | 0x0040); in rge_phy_config_mac_r25()
1076 val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007; in rge_phy_config_mac_r25()
1077 rge_write_phy_ocp(sc, 0xad40, val | 0x0004); in rge_phy_config_mac_r25()
1078 RGE_PHY_CLRBIT(sc, 0xac14, 0x0080); in rge_phy_config_mac_r25()
1079 RGE_PHY_CLRBIT(sc, 0xac80, 0x0300); in rge_phy_config_mac_r25()
1080 val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007; in rge_phy_config_mac_r25()
1081 rge_write_phy_ocp(sc, 0xac5e, val | 0x0002); in rge_phy_config_mac_r25()
1082 rge_write_phy_ocp(sc, 0xad4c, 0x00a8); in rge_phy_config_mac_r25()
1083 rge_write_phy_ocp(sc, 0xac5c, 0x01ff); in rge_phy_config_mac_r25()
1084 val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0; in rge_phy_config_mac_r25()
1085 rge_write_phy_ocp(sc, 0xac8a, val | 0x0030); in rge_phy_config_mac_r25()
1086 rge_write_phy_ocp(sc, 0xb87c, 0x8157); in rge_phy_config_mac_r25()
1087 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r25()
1088 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); in rge_phy_config_mac_r25()
1089 rge_write_phy_ocp(sc, 0xb87c, 0x8159); in rge_phy_config_mac_r25()
1090 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r25()
1091 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); in rge_phy_config_mac_r25()
1092 rge_write_phy_ocp(sc, 0xb87c, 0x80a2); in rge_phy_config_mac_r25()
1093 rge_write_phy_ocp(sc, 0xb87e, 0x0153); in rge_phy_config_mac_r25()
1094 rge_write_phy_ocp(sc, 0xb87c, 0x809c); in rge_phy_config_mac_r25()
1095 rge_write_phy_ocp(sc, 0xb87e, 0x0153); in rge_phy_config_mac_r25()
1097 rge_write_phy_ocp(sc, 0xa436, 0x81b3); in rge_phy_config_mac_r25()
1099 rge_write_phy_ocp(sc, 0xa438, mac_cfg3_a438_value[i]); in rge_phy_config_mac_r25()
1101 rge_write_phy_ocp(sc, 0xa438, 0); in rge_phy_config_mac_r25()
1102 rge_write_phy_ocp(sc, 0xa436, 0x8257); in rge_phy_config_mac_r25()
1103 rge_write_phy_ocp(sc, 0xa438, 0x020f); in rge_phy_config_mac_r25()
1104 rge_write_phy_ocp(sc, 0xa436, 0x80ea); in rge_phy_config_mac_r25()
1105 rge_write_phy_ocp(sc, 0xa438, 0x7843); in rge_phy_config_mac_r25()
1107 rge_patch_phy_mcu(sc, 1); in rge_phy_config_mac_r25()
1108 RGE_PHY_CLRBIT(sc, 0xb896, 0x0001); in rge_phy_config_mac_r25()
1109 RGE_PHY_CLRBIT(sc, 0xb892, 0xff00); in rge_phy_config_mac_r25()
1111 rge_write_phy_ocp(sc, 0xb88e, mac_cfg3_b88e_value[i]); in rge_phy_config_mac_r25()
1112 rge_write_phy_ocp(sc, 0xb890, mac_cfg3_b88e_value[i + 1]); in rge_phy_config_mac_r25()
1114 RGE_PHY_SETBIT(sc, 0xb896, 0x0001); in rge_phy_config_mac_r25()
1115 rge_patch_phy_mcu(sc, 0); in rge_phy_config_mac_r25()
1117 RGE_PHY_SETBIT(sc, 0xd068, 0x2000); in rge_phy_config_mac_r25()
1118 rge_write_phy_ocp(sc, 0xa436, 0x81a2); in rge_phy_config_mac_r25()
1119 RGE_PHY_SETBIT(sc, 0xa438, 0x0100); in rge_phy_config_mac_r25()
1120 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00; in rge_phy_config_mac_r25()
1121 rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00); in rge_phy_config_mac_r25()
1122 RGE_PHY_CLRBIT(sc, 0xa454, 0x0001); in rge_phy_config_mac_r25()
1123 RGE_PHY_SETBIT(sc, 0xa5d4, 0x0020); in rge_phy_config_mac_r25()
1124 RGE_PHY_CLRBIT(sc, 0xad4e, 0x0010); in rge_phy_config_mac_r25()
1125 RGE_PHY_CLRBIT(sc, 0xa86a, 0x0001); in rge_phy_config_mac_r25()
1126 RGE_PHY_SETBIT(sc, 0xa442, 0x0800); in rge_phy_config_mac_r25()
1127 RGE_PHY_SETBIT(sc, 0xa424, 0x0008); in rge_phy_config_mac_r25()
1131 rge_phy_config_mac_r25b(struct rge_softc *sc) in rge_phy_config_mac_r25b() argument
1136 rge_phy_config_mcu(sc, RGE_MAC_R25B_RCODE_VER); in rge_phy_config_mac_r25b()
1138 RGE_PHY_SETBIT(sc, 0xa442, 0x0800); in rge_phy_config_mac_r25b()
1139 val = rge_read_phy_ocp(sc, 0xac46) & ~0x00f0; in rge_phy_config_mac_r25b()
1140 rge_write_phy_ocp(sc, 0xac46, val | 0x0090); in rge_phy_config_mac_r25b()
1141 val = rge_read_phy_ocp(sc, 0xad30) & ~0x0003; in rge_phy_config_mac_r25b()
1142 rge_write_phy_ocp(sc, 0xad30, val | 0x0001); in rge_phy_config_mac_r25b()
1143 rge_write_phy_ocp(sc, 0xb87c, 0x80f5); in rge_phy_config_mac_r25b()
1144 rge_write_phy_ocp(sc, 0xb87e, 0x760e); in rge_phy_config_mac_r25b()
1145 rge_write_phy_ocp(sc, 0xb87c, 0x8107); in rge_phy_config_mac_r25b()
1146 rge_write_phy_ocp(sc, 0xb87e, 0x360e); in rge_phy_config_mac_r25b()
1147 rge_write_phy_ocp(sc, 0xb87c, 0x8551); in rge_phy_config_mac_r25b()
1148 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r25b()
1149 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); in rge_phy_config_mac_r25b()
1150 val = rge_read_phy_ocp(sc, 0xbf00) & ~0xe000; in rge_phy_config_mac_r25b()
1151 rge_write_phy_ocp(sc, 0xbf00, val | 0xa000); in rge_phy_config_mac_r25b()
1152 val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00; in rge_phy_config_mac_r25b()
1153 rge_write_phy_ocp(sc, 0xbf46, val | 0x0300); in rge_phy_config_mac_r25b()
1155 rge_write_phy_ocp(sc, 0xa436, 0x8044 + i * 6); in rge_phy_config_mac_r25b()
1156 rge_write_phy_ocp(sc, 0xa438, 0x2417); in rge_phy_config_mac_r25b()
1158 RGE_PHY_SETBIT(sc, 0xa4ca, 0x0040); in rge_phy_config_mac_r25b()
1159 val = rge_read_phy_ocp(sc, 0xbf84) & ~0xe000; in rge_phy_config_mac_r25b()
1160 rge_write_phy_ocp(sc, 0xbf84, val | 0xa000); in rge_phy_config_mac_r25b()
1161 rge_write_phy_ocp(sc, 0xa436, 0x8170); in rge_phy_config_mac_r25b()
1162 val = rge_read_phy_ocp(sc, 0xa438) & ~0x2700; in rge_phy_config_mac_r25b()
1163 rge_write_phy_ocp(sc, 0xa438, val | 0xd800); in rge_phy_config_mac_r25b()
1164 RGE_PHY_SETBIT(sc, 0xa424, 0x0008); in rge_phy_config_mac_r25b()
1168 rge_phy_config_mac_r25d(struct rge_softc *sc) in rge_phy_config_mac_r25d() argument
1173 rge_phy_config_mcu(sc, RGE_MAC_R25D_RCODE_VER); in rge_phy_config_mac_r25d()
1175 RGE_PHY_SETBIT(sc, 0xa442, 0x0800); in rge_phy_config_mac_r25d()
1177 rge_patch_phy_mcu(sc, 1); in rge_phy_config_mac_r25d()
1178 RGE_PHY_SETBIT(sc, 0xbf96, 0x8000); in rge_phy_config_mac_r25d()
1179 val = rge_read_phy_ocp(sc, 0xbf94) & ~0x0007; in rge_phy_config_mac_r25d()
1180 rge_write_phy_ocp(sc, 0xbf94, val | 0x0005); in rge_phy_config_mac_r25d()
1181 val = rge_read_phy_ocp(sc, 0xbf8e) & ~0x3c00; in rge_phy_config_mac_r25d()
1182 rge_write_phy_ocp(sc, 0xbf8e, val | 0x2800); in rge_phy_config_mac_r25d()
1183 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; in rge_phy_config_mac_r25d()
1184 rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000); in rge_phy_config_mac_r25d()
1185 RGE_PHY_SETBIT(sc, 0xbcd8, 0xc000); in rge_phy_config_mac_r25d()
1186 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; in rge_phy_config_mac_r25d()
1187 rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000); in rge_phy_config_mac_r25d()
1188 val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f; in rge_phy_config_mac_r25d()
1189 rge_write_phy_ocp(sc, 0xbc80, val | 0x0004); in rge_phy_config_mac_r25d()
1190 RGE_PHY_SETBIT(sc, 0xbc82, 0xe000); in rge_phy_config_mac_r25d()
1191 RGE_PHY_SETBIT(sc, 0xbc82, 0x1c00); in rge_phy_config_mac_r25d()
1192 val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f; in rge_phy_config_mac_r25d()
1193 rge_write_phy_ocp(sc, 0xbc80, val | 0x0005); in rge_phy_config_mac_r25d()
1194 val = rge_read_phy_ocp(sc, 0xbc82) & ~0x00e0; in rge_phy_config_mac_r25d()
1195 rge_write_phy_ocp(sc, 0xbc82, val | 0x0040); in rge_phy_config_mac_r25d()
1196 RGE_PHY_SETBIT(sc, 0xbc82, 0x001c); in rge_phy_config_mac_r25d()
1197 RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000); in rge_phy_config_mac_r25d()
1198 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; in rge_phy_config_mac_r25d()
1199 rge_write_phy_ocp(sc, 0xbcd8, val | 0x8000); in rge_phy_config_mac_r25d()
1200 RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000); in rge_phy_config_mac_r25d()
1201 RGE_PHY_CLRBIT(sc, 0xbd70, 0x0100); in rge_phy_config_mac_r25d()
1202 RGE_PHY_SETBIT(sc, 0xa466, 0x0002); in rge_phy_config_mac_r25d()
1203 rge_write_phy_ocp(sc, 0xa436, 0x836a); in rge_phy_config_mac_r25d()
1204 RGE_PHY_CLRBIT(sc, 0xa438, 0xff00); in rge_phy_config_mac_r25d()
1205 rge_patch_phy_mcu(sc, 0); in rge_phy_config_mac_r25d()
1207 rge_write_phy_ocp(sc, 0xb87c, 0x832c); in rge_phy_config_mac_r25d()
1208 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r25d()
1209 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); in rge_phy_config_mac_r25d()
1210 val = rge_read_phy_ocp(sc, 0xb106) & ~0x0700; in rge_phy_config_mac_r25d()
1211 rge_write_phy_ocp(sc, 0xb106, val | 0x0100); in rge_phy_config_mac_r25d()
1212 val = rge_read_phy_ocp(sc, 0xb206) & ~0x0700; in rge_phy_config_mac_r25d()
1213 rge_write_phy_ocp(sc, 0xb206, val | 0x0200); in rge_phy_config_mac_r25d()
1214 val = rge_read_phy_ocp(sc, 0xb306) & ~0x0700; in rge_phy_config_mac_r25d()
1215 rge_write_phy_ocp(sc, 0xb306, val | 0x0300); in rge_phy_config_mac_r25d()
1216 rge_write_phy_ocp(sc, 0xb87c, 0x80cb); in rge_phy_config_mac_r25d()
1217 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r25d()
1218 rge_write_phy_ocp(sc, 0xb87e, val | 0x0300); in rge_phy_config_mac_r25d()
1219 rge_write_phy_ocp(sc, 0xbcf4, 0x0000); in rge_phy_config_mac_r25d()
1220 rge_write_phy_ocp(sc, 0xbcf6, 0x0000); in rge_phy_config_mac_r25d()
1221 rge_write_phy_ocp(sc, 0xbc12, 0x0000); in rge_phy_config_mac_r25d()
1222 rge_write_phy_ocp(sc, 0xb87c, 0x844d); in rge_phy_config_mac_r25d()
1223 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r25d()
1224 rge_write_phy_ocp(sc, 0xb87e, val | 0x0200); in rge_phy_config_mac_r25d()
1226 rge_write_phy_ocp(sc, 0xb87c, 0x8feb); in rge_phy_config_mac_r25d()
1227 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r25d()
1228 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_r25d()
1229 rge_write_phy_ocp(sc, 0xb87c, 0x8fe9); in rge_phy_config_mac_r25d()
1230 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r25d()
1231 rge_write_phy_ocp(sc, 0xb87e, val | 0x0600); in rge_phy_config_mac_r25d()
1233 val = rge_read_phy_ocp(sc, 0xac7e) & ~0x01fc; in rge_phy_config_mac_r25d()
1234 rge_write_phy_ocp(sc, 0xac7e, val | 0x00B4); in rge_phy_config_mac_r25d()
1235 rge_write_phy_ocp(sc, 0xb87c, 0x8105); in rge_phy_config_mac_r25d()
1236 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r25d()
1237 rge_write_phy_ocp(sc, 0xb87e, val | 0x7a00); in rge_phy_config_mac_r25d()
1238 rge_write_phy_ocp(sc, 0xb87c, 0x8117); in rge_phy_config_mac_r25d()
1239 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r25d()
1240 rge_write_phy_ocp(sc, 0xb87e, val | 0x3a00); in rge_phy_config_mac_r25d()
1241 rge_write_phy_ocp(sc, 0xb87c, 0x8103); in rge_phy_config_mac_r25d()
1242 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r25d()
1243 rge_write_phy_ocp(sc, 0xb87e, val | 0x7400); in rge_phy_config_mac_r25d()
1244 rge_write_phy_ocp(sc, 0xb87c, 0x8115); in rge_phy_config_mac_r25d()
1245 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_r25d()
1246 rge_write_phy_ocp(sc, 0xb87e, val | 0x3400); in rge_phy_config_mac_r25d()
1247 RGE_PHY_CLRBIT(sc, 0xad40, 0x0030); in rge_phy_config_mac_r25d()
1248 val = rge_read_phy_ocp(sc, 0xad66) & ~0x000f; in rge_phy_config_mac_r25d()
1249 rge_write_phy_ocp(sc, 0xad66, val | 0x0007); in rge_phy_config_mac_r25d()
1250 val = rge_read_phy_ocp(sc, 0xad68) & ~0xf000; in rge_phy_config_mac_r25d()
1251 rge_write_phy_ocp(sc, 0xad68, val | 0x8000); in rge_phy_config_mac_r25d()
1252 val = rge_read_phy_ocp(sc, 0xad68) & ~0x0f00; in rge_phy_config_mac_r25d()
1253 rge_write_phy_ocp(sc, 0xad68, val | 0x0500); in rge_phy_config_mac_r25d()
1254 val = rge_read_phy_ocp(sc, 0xad68) & ~0x000f; in rge_phy_config_mac_r25d()
1255 rge_write_phy_ocp(sc, 0xad68, val | 0x0002); in rge_phy_config_mac_r25d()
1256 val = rge_read_phy_ocp(sc, 0xad6a) & ~0xf000; in rge_phy_config_mac_r25d()
1257 rge_write_phy_ocp(sc, 0xad6a, val | 0x7000); in rge_phy_config_mac_r25d()
1258 rge_write_phy_ocp(sc, 0xac50, 0x01e8); in rge_phy_config_mac_r25d()
1259 rge_write_phy_ocp(sc, 0xa436, 0x81fa); in rge_phy_config_mac_r25d()
1260 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1261 rge_write_phy_ocp(sc, 0xa438, val | 0x5400); in rge_phy_config_mac_r25d()
1262 val = rge_read_phy_ocp(sc, 0xa864) & ~0x00f0; in rge_phy_config_mac_r25d()
1263 rge_write_phy_ocp(sc, 0xa864, val | 0x00c0); in rge_phy_config_mac_r25d()
1264 val = rge_read_phy_ocp(sc, 0xa42c) & ~0x00ff; in rge_phy_config_mac_r25d()
1265 rge_write_phy_ocp(sc, 0xa42c, val | 0x0002); in rge_phy_config_mac_r25d()
1266 rge_write_phy_ocp(sc, 0xa436, 0x80e1); in rge_phy_config_mac_r25d()
1267 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1268 rge_write_phy_ocp(sc, 0xa438, val | 0x0f00); in rge_phy_config_mac_r25d()
1269 rge_write_phy_ocp(sc, 0xa436, 0x80de); in rge_phy_config_mac_r25d()
1270 val = rge_read_phy_ocp(sc, 0xa438) & ~0xf000; in rge_phy_config_mac_r25d()
1271 rge_write_phy_ocp(sc, 0xa438, val | 0x0700); in rge_phy_config_mac_r25d()
1272 RGE_PHY_SETBIT(sc, 0xa846, 0x0080); in rge_phy_config_mac_r25d()
1273 rge_write_phy_ocp(sc, 0xa436, 0x80ba); in rge_phy_config_mac_r25d()
1274 rge_write_phy_ocp(sc, 0xa438, 0x8a04); in rge_phy_config_mac_r25d()
1275 rge_write_phy_ocp(sc, 0xa436, 0x80bd); in rge_phy_config_mac_r25d()
1276 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1277 rge_write_phy_ocp(sc, 0xa438, val | 0xca00); in rge_phy_config_mac_r25d()
1278 rge_write_phy_ocp(sc, 0xa436, 0x80b7); in rge_phy_config_mac_r25d()
1279 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1280 rge_write_phy_ocp(sc, 0xa438, val | 0xb300); in rge_phy_config_mac_r25d()
1281 rge_write_phy_ocp(sc, 0xa436, 0x80ce); in rge_phy_config_mac_r25d()
1282 rge_write_phy_ocp(sc, 0xa438, 0x8a04); in rge_phy_config_mac_r25d()
1283 rge_write_phy_ocp(sc, 0xa436, 0x80d1); in rge_phy_config_mac_r25d()
1284 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1285 rge_write_phy_ocp(sc, 0xa438, val | 0xca00); in rge_phy_config_mac_r25d()
1286 rge_write_phy_ocp(sc, 0xa436, 0x80cb); in rge_phy_config_mac_r25d()
1287 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1288 rge_write_phy_ocp(sc, 0xa438, val | 0xbb00); in rge_phy_config_mac_r25d()
1289 rge_write_phy_ocp(sc, 0xa436, 0x80a6); in rge_phy_config_mac_r25d()
1290 rge_write_phy_ocp(sc, 0xa438, 0x4909); in rge_phy_config_mac_r25d()
1291 rge_write_phy_ocp(sc, 0xa436, 0x80a8); in rge_phy_config_mac_r25d()
1292 rge_write_phy_ocp(sc, 0xa438, 0x05b8); in rge_phy_config_mac_r25d()
1293 rge_write_phy_ocp(sc, 0xa436, 0x8200); in rge_phy_config_mac_r25d()
1294 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1295 rge_write_phy_ocp(sc, 0xa438, val | 0x5800); in rge_phy_config_mac_r25d()
1296 rge_write_phy_ocp(sc, 0xa436, 0x8ff1); in rge_phy_config_mac_r25d()
1297 rge_write_phy_ocp(sc, 0xa438, 0x7078); in rge_phy_config_mac_r25d()
1298 rge_write_phy_ocp(sc, 0xa436, 0x8ff3); in rge_phy_config_mac_r25d()
1299 rge_write_phy_ocp(sc, 0xa438, 0x5d78); in rge_phy_config_mac_r25d()
1300 rge_write_phy_ocp(sc, 0xa436, 0x8ff5); in rge_phy_config_mac_r25d()
1301 rge_write_phy_ocp(sc, 0xa438, 0x7862); in rge_phy_config_mac_r25d()
1302 rge_write_phy_ocp(sc, 0xa436, 0x8ff7); in rge_phy_config_mac_r25d()
1303 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1304 rge_write_phy_ocp(sc, 0xa438, val | 0x1400); in rge_phy_config_mac_r25d()
1306 rge_write_phy_ocp(sc, 0xa436, 0x814c); in rge_phy_config_mac_r25d()
1307 rge_write_phy_ocp(sc, 0xa438, 0x8455); in rge_phy_config_mac_r25d()
1308 rge_write_phy_ocp(sc, 0xa436, 0x814e); in rge_phy_config_mac_r25d()
1309 rge_write_phy_ocp(sc, 0xa438, 0x84a6); in rge_phy_config_mac_r25d()
1310 rge_write_phy_ocp(sc, 0xa436, 0x8163); in rge_phy_config_mac_r25d()
1311 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1312 rge_write_phy_ocp(sc, 0xa438, val | 0x0600); in rge_phy_config_mac_r25d()
1313 rge_write_phy_ocp(sc, 0xa436, 0x816a); in rge_phy_config_mac_r25d()
1314 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1315 rge_write_phy_ocp(sc, 0xa438, val | 0x0500); in rge_phy_config_mac_r25d()
1316 rge_write_phy_ocp(sc, 0xa436, 0x8171); in rge_phy_config_mac_r25d()
1317 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1318 rge_write_phy_ocp(sc, 0xa438, val | 0x1f00); in rge_phy_config_mac_r25d()
1320 val = rge_read_phy_ocp(sc, 0xbc3a) & ~0x000f; in rge_phy_config_mac_r25d()
1321 rge_write_phy_ocp(sc, 0xbc3a, val | 0x0006); in rge_phy_config_mac_r25d()
1323 rge_write_phy_ocp(sc, 0xa436, 0x8064 + i * 3); in rge_phy_config_mac_r25d()
1324 RGE_PHY_CLRBIT(sc, 0xa438, 0x0700); in rge_phy_config_mac_r25d()
1326 val = rge_read_phy_ocp(sc, 0xbfa0) & ~0xff70; in rge_phy_config_mac_r25d()
1327 rge_write_phy_ocp(sc, 0xbfa0, val | 0x5500); in rge_phy_config_mac_r25d()
1328 rge_write_phy_ocp(sc, 0xbfa2, 0x9d00); in rge_phy_config_mac_r25d()
1329 rge_write_phy_ocp(sc, 0xa436, 0x8165); in rge_phy_config_mac_r25d()
1330 val = rge_read_phy_ocp(sc, 0xa438) & ~0x0700; in rge_phy_config_mac_r25d()
1331 rge_write_phy_ocp(sc, 0xa438, val | 0x0200); in rge_phy_config_mac_r25d()
1333 rge_write_phy_ocp(sc, 0xa436, 0x8019); in rge_phy_config_mac_r25d()
1334 RGE_PHY_SETBIT(sc, 0xa438, 0x0100); in rge_phy_config_mac_r25d()
1335 rge_write_phy_ocp(sc, 0xa436, 0x8fe3); in rge_phy_config_mac_r25d()
1336 rge_write_phy_ocp(sc, 0xa438, 0x0005); in rge_phy_config_mac_r25d()
1337 rge_write_phy_ocp(sc, 0xa438, 0x0000); in rge_phy_config_mac_r25d()
1338 rge_write_phy_ocp(sc, 0xa438, 0x00ed); in rge_phy_config_mac_r25d()
1339 rge_write_phy_ocp(sc, 0xa438, 0x0502); in rge_phy_config_mac_r25d()
1340 rge_write_phy_ocp(sc, 0xa438, 0x0b00); in rge_phy_config_mac_r25d()
1341 rge_write_phy_ocp(sc, 0xa438, 0xd401); in rge_phy_config_mac_r25d()
1342 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1343 rge_write_phy_ocp(sc, 0xa438, val | 0x2900); in rge_phy_config_mac_r25d()
1345 rge_write_phy_ocp(sc, 0xa436, 0x8018); in rge_phy_config_mac_r25d()
1346 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1347 rge_write_phy_ocp(sc, 0xa438, val | 0x1700); in rge_phy_config_mac_r25d()
1349 rge_write_phy_ocp(sc, 0xa436, 0x815b); in rge_phy_config_mac_r25d()
1350 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_r25d()
1351 rge_write_phy_ocp(sc, 0xa438, val | 0x1700); in rge_phy_config_mac_r25d()
1353 RGE_PHY_CLRBIT(sc, 0xa4e0, 0x8000); in rge_phy_config_mac_r25d()
1354 RGE_PHY_CLRBIT(sc, 0xa5d4, 0x0020); in rge_phy_config_mac_r25d()
1355 RGE_PHY_CLRBIT(sc, 0xa654, 0x0800); in rge_phy_config_mac_r25d()
1356 RGE_PHY_SETBIT(sc, 0xa430, 0x1001); in rge_phy_config_mac_r25d()
1357 RGE_PHY_SETBIT(sc, 0xa442, 0x0080); in rge_phy_config_mac_r25d()
1361 rge_phy_config_mcu(struct rge_softc *sc, uint16_t rcodever) in rge_phy_config_mcu() argument
1363 if (sc->rge_rcodever != rcodever) { in rge_phy_config_mcu()
1366 rge_patch_phy_mcu(sc, 1); in rge_phy_config_mcu()
1368 if (sc->rge_type == MAC_R25) { in rge_phy_config_mcu()
1369 rge_write_phy_ocp(sc, 0xa436, 0x8024); in rge_phy_config_mcu()
1370 rge_write_phy_ocp(sc, 0xa438, 0x8601); in rge_phy_config_mcu()
1371 rge_write_phy_ocp(sc, 0xa436, 0xb82e); in rge_phy_config_mcu()
1372 rge_write_phy_ocp(sc, 0xa438, 0x0001); in rge_phy_config_mcu()
1374 RGE_PHY_SETBIT(sc, 0xb820, 0x0080); in rge_phy_config_mcu()
1377 rge_write_phy_ocp(sc, in rge_phy_config_mcu()
1380 RGE_PHY_CLRBIT(sc, 0xb820, 0x0080); in rge_phy_config_mcu()
1382 rge_write_phy_ocp(sc, 0xa436, 0); in rge_phy_config_mcu()
1383 rge_write_phy_ocp(sc, 0xa438, 0); in rge_phy_config_mcu()
1384 RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001); in rge_phy_config_mcu()
1385 rge_write_phy_ocp(sc, 0xa436, 0x8024); in rge_phy_config_mcu()
1386 rge_write_phy_ocp(sc, 0xa438, 0); in rge_phy_config_mcu()
1387 } else if (sc->rge_type == MAC_R25B) { in rge_phy_config_mcu()
1389 rge_write_phy_ocp(sc, in rge_phy_config_mcu()
1391 } else if (sc->rge_type == MAC_R25D) { in rge_phy_config_mcu()
1393 rge_write_phy_ocp(sc, in rge_phy_config_mcu()
1395 rge_patch_phy_mcu(sc, 0); in rge_phy_config_mcu()
1397 rge_patch_phy_mcu(sc, 1); in rge_phy_config_mcu()
1399 rge_write_phy_ocp(sc, in rge_phy_config_mcu()
1401 rge_patch_phy_mcu(sc, 0); in rge_phy_config_mcu()
1403 rge_patch_phy_mcu(sc, 1); in rge_phy_config_mcu()
1405 rge_write_phy_ocp(sc, in rge_phy_config_mcu()
1407 } else if (sc->rge_type == MAC_R26) { in rge_phy_config_mcu()
1409 rge_write_phy_ocp(sc, in rge_phy_config_mcu()
1411 } else if (sc->rge_type == MAC_R27) { in rge_phy_config_mcu()
1413 rge_write_phy_ocp(sc, in rge_phy_config_mcu()
1415 rge_patch_phy_mcu(sc, 0); in rge_phy_config_mcu()
1417 rge_patch_phy_mcu(sc, 1); in rge_phy_config_mcu()
1419 rge_write_phy_ocp(sc, in rge_phy_config_mcu()
1423 rge_patch_phy_mcu(sc, 0); in rge_phy_config_mcu()
1426 rge_write_phy_ocp(sc, 0xa436, 0x801e); in rge_phy_config_mcu()
1427 rge_write_phy_ocp(sc, 0xa438, rcodever); in rge_phy_config_mcu()
1432 rge_set_macaddr(struct rge_softc *sc, const uint8_t *addr) in rge_set_macaddr() argument
1434 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); in rge_set_macaddr()
1435 RGE_WRITE_4(sc, RGE_MAC0, in rge_set_macaddr()
1437 RGE_WRITE_4(sc, RGE_MAC4, in rge_set_macaddr()
1439 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); in rge_set_macaddr()
1451 rge_get_macaddr(struct rge_softc *sc, uint8_t *addr) in rge_get_macaddr() argument
1455 RGE_ASSERT_LOCKED(sc); in rge_get_macaddr()
1458 addr[i] = RGE_READ_1(sc, RGE_MAC0 + i); in rge_get_macaddr()
1460 *(uint32_t *)&addr[0] = RGE_READ_4(sc, RGE_ADDR0); in rge_get_macaddr()
1461 *(uint16_t *)&addr[4] = RGE_READ_2(sc, RGE_ADDR1); in rge_get_macaddr()
1463 rge_set_macaddr(sc, addr); in rge_get_macaddr()
1472 rge_hw_init(struct rge_softc *sc) in rge_hw_init() argument
1477 RGE_ASSERT_LOCKED(sc); in rge_hw_init()
1479 rge_disable_aspm_clkreq(sc); in rge_hw_init()
1480 RGE_CLRBIT_1(sc, 0xf1, 0x80); in rge_hw_init()
1483 RGE_MAC_CLRBIT(sc, 0xd40a, 0x0010); in rge_hw_init()
1486 rge_disable_aspm_clkreq(sc); in rge_hw_init()
1487 rge_write_mac_ocp(sc, 0xfc48, 0); in rge_hw_init()
1489 rge_write_mac_ocp(sc, reg, 0); in rge_hw_init()
1491 rge_write_mac_ocp(sc, 0xfc26, 0); in rge_hw_init()
1494 rge_switch_mcu_ram_page(sc, 2); in rge_hw_init()
1495 sc->rge_mcodever = 0; in rge_hw_init()
1497 sc->rge_mcodever <<= 16; in rge_hw_init()
1498 sc->rge_mcodever |= rge_read_mac_ocp(sc, 0xf9f8 + i); in rge_hw_init()
1500 rge_switch_mcu_ram_page(sc, 0); in rge_hw_init()
1502 rge_mac_config_mcu(sc, sc->rge_type); in rge_hw_init()
1505 if (sc->rge_type == MAC_R25) in rge_hw_init()
1506 rge_disable_phy_ocp_pwrsave(sc); in rge_hw_init()
1509 rge_write_csi(sc, 0x108, in rge_hw_init()
1510 rge_read_csi(sc, 0x108) | 0x00100000); in rge_hw_init()
1514 rge_hw_reset(struct rge_softc *sc) in rge_hw_reset() argument
1517 RGE_WRITE_4(sc, RGE_IMR, 0); in rge_hw_reset()
1518 RGE_WRITE_4(sc, RGE_ISR, RGE_READ_4(sc, RGE_ISR)); in rge_hw_reset()
1521 RGE_WRITE_4(sc, RGE_TIMERINT0, 0); in rge_hw_reset()
1522 RGE_WRITE_4(sc, RGE_TIMERINT1, 0); in rge_hw_reset()
1523 RGE_WRITE_4(sc, RGE_TIMERINT2, 0); in rge_hw_reset()
1524 RGE_WRITE_4(sc, RGE_TIMERINT3, 0); in rge_hw_reset()
1526 rge_reset(sc); in rge_hw_reset()
1530 rge_disable_phy_ocp_pwrsave(struct rge_softc *sc) in rge_disable_phy_ocp_pwrsave() argument
1532 if (rge_read_phy_ocp(sc, 0xc416) != 0x0500) { in rge_disable_phy_ocp_pwrsave()
1533 rge_patch_phy_mcu(sc, 1); in rge_disable_phy_ocp_pwrsave()
1534 rge_write_phy_ocp(sc, 0xc416, 0); in rge_disable_phy_ocp_pwrsave()
1535 rge_write_phy_ocp(sc, 0xc416, 0x0500); in rge_disable_phy_ocp_pwrsave()
1536 rge_patch_phy_mcu(sc, 0); in rge_disable_phy_ocp_pwrsave()
1541 rge_patch_phy_mcu(struct rge_softc *sc, int set) in rge_patch_phy_mcu() argument
1546 RGE_PHY_SETBIT(sc, 0xb820, 0x0010); in rge_patch_phy_mcu()
1548 RGE_PHY_CLRBIT(sc, 0xb820, 0x0010); in rge_patch_phy_mcu()
1552 if ((rge_read_phy_ocp(sc, 0xb800) & 0x0040) != 0) in rge_patch_phy_mcu()
1555 if (!(rge_read_phy_ocp(sc, 0xb800) & 0x0040)) in rge_patch_phy_mcu()
1561 RGE_PRINT_ERROR(sc, "timeout waiting to patch phy mcu\n"); in rge_patch_phy_mcu()
1565 rge_config_imtype(struct rge_softc *sc, int imtype) in rge_config_imtype() argument
1569 sc->rge_intrs = RGE_INTRS; in rge_config_imtype()
1572 sc->rge_intrs = RGE_INTRS_TIMER; in rge_config_imtype()
1575 RGE_PRINT_ERROR(sc, "unknown imtype %d", imtype); in rge_config_imtype()
1580 rge_disable_aspm_clkreq(struct rge_softc *sc) in rge_disable_aspm_clkreq() argument
1584 if ((RGE_READ_1(sc, RGE_EECMD) & RGE_EECMD_WRITECFG) == in rge_disable_aspm_clkreq()
1589 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); in rge_disable_aspm_clkreq()
1591 if (sc->rge_type == MAC_R26 || sc->rge_type == MAC_R27) in rge_disable_aspm_clkreq()
1592 RGE_CLRBIT_1(sc, RGE_INT_CFG0, 0x08); in rge_disable_aspm_clkreq()
1594 RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN); in rge_disable_aspm_clkreq()
1595 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS); in rge_disable_aspm_clkreq()
1598 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); in rge_disable_aspm_clkreq()
1602 rge_disable_hw_im(struct rge_softc *sc) in rge_disable_hw_im() argument
1604 RGE_WRITE_2(sc, RGE_IM, 0); in rge_disable_hw_im()
1608 rge_disable_sim_im(struct rge_softc *sc) in rge_disable_sim_im() argument
1610 RGE_WRITE_4(sc, RGE_TIMERINT0, 0); in rge_disable_sim_im()
1611 sc->rge_timerintr = 0; in rge_disable_sim_im()
1615 rge_setup_sim_im(struct rge_softc *sc) in rge_setup_sim_im() argument
1617 RGE_WRITE_4(sc, RGE_TIMERINT0, 0x2600); in rge_setup_sim_im()
1618 RGE_WRITE_4(sc, RGE_TIMERCNT, 1); in rge_setup_sim_im()
1619 sc->rge_timerintr = 1; in rge_setup_sim_im()
1623 rge_setup_intr(struct rge_softc *sc, int imtype) in rge_setup_intr() argument
1625 rge_config_imtype(sc, imtype); in rge_setup_intr()
1628 RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs); in rge_setup_intr()
1632 rge_disable_sim_im(sc); in rge_setup_intr()
1633 rge_disable_hw_im(sc); in rge_setup_intr()
1636 rge_disable_hw_im(sc); in rge_setup_intr()
1637 rge_setup_sim_im(sc); in rge_setup_intr()
1640 RGE_PRINT_ERROR(sc, "unknown imtype %d", imtype); in rge_setup_intr()
1645 rge_switch_mcu_ram_page(struct rge_softc *sc, int page) in rge_switch_mcu_ram_page() argument
1649 val = rge_read_mac_ocp(sc, 0xe446) & ~0x0003; in rge_switch_mcu_ram_page()
1651 rge_write_mac_ocp(sc, 0xe446, val); in rge_switch_mcu_ram_page()
1655 rge_exit_oob(struct rge_softc *sc) in rge_exit_oob() argument
1660 rge_write_mac_ocp(sc, 0xc0bc, 0x00ff); in rge_exit_oob()
1662 if ((error = rge_reset(sc)) != 0) in rge_exit_oob()
1666 RGE_CLRBIT_1(sc, RGE_MCUCMD, RGE_MCUCMD_IS_OOB); in rge_exit_oob()
1668 RGE_MAC_CLRBIT(sc, 0xe8de, 0x4000); in rge_exit_oob()
1672 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200) in rge_exit_oob()
1676 rge_write_mac_ocp(sc, 0xc0aa, 0x07d0); in rge_exit_oob()
1677 rge_write_mac_ocp(sc, 0xc0a6, 0x01b5); in rge_exit_oob()
1678 rge_write_mac_ocp(sc, 0xc01e, 0x5555); in rge_exit_oob()
1682 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200) in rge_exit_oob()
1686 if (rge_read_mac_ocp(sc, 0xd42c) & 0x0100) { in rge_exit_oob()
1688 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 2) in rge_exit_oob()
1692 RGE_MAC_CLRBIT(sc, 0xd42c, 0x0100); in rge_exit_oob()
1693 if (sc->rge_type != MAC_R25) in rge_exit_oob()
1694 RGE_PHY_CLRBIT(sc, 0xa466, 0x0001); in rge_exit_oob()
1695 RGE_PHY_CLRBIT(sc, 0xa468, 0x000a); in rge_exit_oob()
1702 rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val) in rge_write_csi() argument
1706 RGE_WRITE_4(sc, RGE_CSIDR, val); in rge_write_csi()
1707 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) | in rge_write_csi()
1712 if (!(RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY)) in rge_write_csi()
1720 rge_read_csi(struct rge_softc *sc, uint32_t reg) in rge_read_csi() argument
1724 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) | in rge_read_csi()
1729 if (RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY) in rge_read_csi()
1735 return (RGE_READ_4(sc, RGE_CSIDR)); in rge_read_csi()
1739 rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val) in rge_write_mac_ocp() argument
1746 RGE_WRITE_4(sc, RGE_MACOCP, tmp); in rge_write_mac_ocp()
1750 rge_read_mac_ocp(struct rge_softc *sc, uint16_t reg) in rge_read_mac_ocp() argument
1755 RGE_WRITE_4(sc, RGE_MACOCP, val); in rge_read_mac_ocp()
1757 return (RGE_READ_4(sc, RGE_MACOCP) & RGE_MACOCP_DATA_MASK); in rge_read_mac_ocp()
1761 rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val) in rge_write_ephy() argument
1768 RGE_WRITE_4(sc, RGE_EPHYAR, tmp); in rge_write_ephy()
1772 if (!(RGE_READ_4(sc, RGE_EPHYAR) & RGE_EPHYAR_BUSY)) in rge_write_ephy()
1780 rge_read_ephy(struct rge_softc *sc, uint16_t reg) in rge_read_ephy() argument
1786 RGE_WRITE_4(sc, RGE_EPHYAR, val); in rge_read_ephy()
1790 val = RGE_READ_4(sc, RGE_EPHYAR); in rge_read_ephy()
1801 rge_check_ephy_ext_add(struct rge_softc *sc, uint16_t reg) in rge_check_ephy_ext_add() argument
1806 rge_write_ephy(sc, RGE_EPHYAR_EXT_ADDR, val); in rge_check_ephy_ext_add()
1812 rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val) in rge_r27_write_ephy() argument
1814 rge_write_ephy(sc, rge_check_ephy_ext_add(sc, reg), val); in rge_r27_write_ephy()
1818 rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val) in rge_write_phy() argument
1829 rge_write_phy_ocp(sc, phyaddr, val); in rge_write_phy()
1833 rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg) in rge_read_phy() argument
1844 return (rge_read_phy_ocp(sc, phyaddr)); in rge_read_phy()
1848 rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val) in rge_write_phy_ocp() argument
1855 RGE_WRITE_4(sc, RGE_PHYOCP, tmp); in rge_write_phy_ocp()
1859 if (!(RGE_READ_4(sc, RGE_PHYOCP) & RGE_PHYOCP_BUSY)) in rge_write_phy_ocp()
1865 rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg) in rge_read_phy_ocp() argument
1871 RGE_WRITE_4(sc, RGE_PHYOCP, val); in rge_read_phy_ocp()
1875 val = RGE_READ_4(sc, RGE_PHYOCP); in rge_read_phy_ocp()
1884 rge_get_link_status(struct rge_softc *sc) in rge_get_link_status() argument
1886 return ((RGE_READ_2(sc, RGE_PHYSTAT) & RGE_PHYSTAT_LINK) ? 1 : 0); in rge_get_link_status()
1894 struct rge_softc *sc = ifp->if_softc;
1897 if (!(RGE_READ_1(sc, RGE_CFG1) & RGE_CFG1_PM_EN)) {
1899 "cannot do WOL\n", sc->sc_dev.dv_xname);
1905 rge_iff(sc);
1908 RGE_MAC_SETBIT(sc, 0xc0b6, 0x0001);
1910 RGE_MAC_CLRBIT(sc, 0xc0b6, 0x0001);
1912 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
1913 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE | RGE_CFG5_WOL_UCAST |
1915 RGE_CLRBIT_1(sc, RGE_CFG3, RGE_CFG3_WOL_LINK | RGE_CFG3_WOL_MAGIC);
1917 RGE_SETBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE);
1918 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
1924 rge_wol_power(struct rge_softc *sc)
1927 RGE_CLRBIT_1(sc, RGE_PPSW, 0x08);
1930 RGE_SETBIT_1(sc, RGE_CFG1, RGE_CFG1_PM_EN);
1931 RGE_SETBIT_1(sc, RGE_CFG2, RGE_CFG2_PMSTS_EN);