Lines Matching +full:0 +full:x00020002
19 #define RT2560_DEFAULT_RSSI_CORR 0x79
36 #define RT2560_CSR0 0x0000 /* ASIC version number */
37 #define RT2560_CSR1 0x0004 /* System control */
38 #define RT2560_CSR3 0x000c /* STA MAC address 0 */
39 #define RT2560_CSR4 0x0010 /* STA MAC address 1 */
40 #define RT2560_CSR5 0x0014 /* BSSID 0 */
41 #define RT2560_CSR6 0x0018 /* BSSID 1 */
42 #define RT2560_CSR7 0x001c /* Interrupt source */
43 #define RT2560_CSR8 0x0020 /* Interrupt mask */
44 #define RT2560_CSR9 0x0024 /* Maximum frame length */
45 #define RT2560_SECCSR0 0x0028 /* WEP control */
46 #define RT2560_CSR11 0x002c /* Back-off control */
47 #define RT2560_CSR12 0x0030 /* Synchronization configuration 0 */
48 #define RT2560_CSR13 0x0034 /* Synchronization configuration 1 */
49 #define RT2560_CSR14 0x0038 /* Synchronization control */
50 #define RT2560_CSR15 0x003c /* Synchronization status */
51 #define RT2560_CSR16 0x0040 /* TSF timer 0 */
52 #define RT2560_CSR17 0x0044 /* TSF timer 1 */
53 #define RT2560_CSR18 0x0048 /* IFS timer 0 */
54 #define RT2560_CSR19 0x004c /* IFS timer 1 */
55 #define RT2560_CSR20 0x0050 /* WAKEUP timer */
56 #define RT2560_CSR21 0x0054 /* EEPROM control */
57 #define RT2560_CSR22 0x0058 /* CFP control */
58 #define RT2560_TXCSR0 0x0060 /* TX control */
59 #define RT2560_TXCSR1 0x0064 /* TX configuration */
60 #define RT2560_TXCSR2 0x0068 /* TX descriptor configuration */
61 #define RT2560_TXCSR3 0x006c /* TX ring base address */
62 #define RT2560_TXCSR4 0x0070 /* TX ATIM ring base address */
63 #define RT2560_TXCSR5 0x0074 /* TX PRIO ring base address */
64 #define RT2560_TXCSR6 0x0078 /* Beacon base address */
65 #define RT2560_TXCSR7 0x007c /* AutoResponder control */
66 #define RT2560_RXCSR0 0x0080 /* RX control */
67 #define RT2560_RXCSR1 0x0084 /* RX descriptor configuration */
68 #define RT2560_RXCSR2 0x0088 /* RX ring base address */
69 #define RT2560_PCICSR 0x008c /* PCI control */
70 #define RT2560_RXCSR3 0x0090 /* BBP ID 0 */
71 #define RT2560_TXCSR9 0x0094 /* OFDM TX BBP */
72 #define RT2560_ARSP_PLCP_0 0x0098 /* Auto Responder PLCP address */
73 #define RT2560_ARSP_PLCP_1 0x009c /* Auto Responder Basic Rate mask */
74 #define RT2560_CNT0 0x00a0 /* FCS error counter */
75 #define RT2560_CNT1 0x00ac /* PLCP error counter */
76 #define RT2560_CNT2 0x00b0 /* Long error counter */
77 #define RT2560_CNT3 0x00b8 /* CCA false alarm counter */
78 #define RT2560_CNT4 0x00bc /* RX FIFO Overflow counter */
79 #define RT2560_CNT5 0x00c0 /* Tx FIFO Underrun counter */
80 #define RT2560_PWRCSR0 0x00c4 /* Power mode configuration */
81 #define RT2560_PSCSR0 0x00c8 /* Power state transition time */
82 #define RT2560_PSCSR1 0x00cc /* Power state transition time */
83 #define RT2560_PSCSR2 0x00d0 /* Power state transition time */
84 #define RT2560_PSCSR3 0x00d4 /* Power state transition time */
85 #define RT2560_PWRCSR1 0x00d8 /* Manual power control/status */
86 #define RT2560_TIMECSR 0x00dc /* Timer control */
87 #define RT2560_MACCSR0 0x00e0 /* MAC configuration */
88 #define RT2560_MACCSR1 0x00e4 /* MAC configuration */
89 #define RT2560_RALINKCSR 0x00e8 /* Ralink RX auto-reset BBCR */
90 #define RT2560_BCNCSR 0x00ec /* Beacon interval control */
91 #define RT2560_BBPCSR 0x00f0 /* BBP serial control */
92 #define RT2560_RFCSR 0x00f4 /* RF serial control */
93 #define RT2560_LEDCSR 0x00f8 /* LED control */
94 #define RT2560_SECCSR3 0x00fc /* XXX not documented */
95 #define RT2560_DMACSR0 0x0100 /* Current RX ring address */
96 #define RT2560_DMACSR1 0x0104 /* Current Tx ring address */
97 #define RT2560_DMACSR2 0x0104 /* Current Priority ring address */
98 #define RT2560_DMACSR3 0x0104 /* Current ATIM ring address */
99 #define RT2560_TXACKCSR0 0x0110 /* XXX not documented */
100 #define RT2560_GPIOCSR 0x0120 /* */
101 #define RT2560_BBBPPCSR 0x0124 /* BBP Pin Control */
102 #define RT2560_FIFOCSR0 0x0128 /* TX FIFO pointer */
103 #define RT2560_FIFOCSR1 0x012c /* RX FIFO pointer */
104 #define RT2560_BCNOCSR 0x0130 /* Beacon time offset */
105 #define RT2560_RLPWCSR 0x0134 /* RX_PE Low Width */
106 #define RT2560_TESTCSR 0x0138 /* Test Mode Select */
107 #define RT2560_PLCP1MCSR 0x013c /* Signal/Service/Length of ACK @1M */
108 #define RT2560_PLCP2MCSR 0x0140 /* Signal/Service/Length of ACK @2M */
109 #define RT2560_PLCP5p5MCSR 0x0144 /* Signal/Service/Length of ACK @5.5M */
110 #define RT2560_PLCP11MCSR 0x0148 /* Signal/Service/Length of ACK @11M */
111 #define RT2560_ACKPCTCSR 0x014c /* ACK/CTS padload consume time */
112 #define RT2560_ARTCSR1 0x0150 /* ACK/CTS padload consume time */
113 #define RT2560_ARTCSR2 0x0154 /* ACK/CTS padload consume time */
114 #define RT2560_SECCSR1 0x0158 /* WEP control */
115 #define RT2560_BBPCSR1 0x015c /* BBP TX Configuration */
118 #define RT2560_DISABLE_RX (1 << 0)
127 #define RT2560_RESET_ASIC (1 << 0)
132 #define RT2560_ENABLE_TSF (1 << 0)
133 #define RT2560_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1)
148 #define RT2560_KICK_TX (1 << 0)
154 #define RT2560_KICK_DECRYPT (1 << 0)
157 #define RT2560_KICK_ENCRYPT (1 << 0)
160 #define RT2560_BEACON_EXPIRE 0x00000001
161 #define RT2560_WAKEUP_EXPIRE 0x00000002
162 #define RT2560_ATIM_EXPIRE 0x00000004
163 #define RT2560_TX_DONE 0x00000008
164 #define RT2560_ATIM_DONE 0x00000010
165 #define RT2560_PRIO_DONE 0x00000020
166 #define RT2560_RX_DONE 0x00000040
167 #define RT2560_DECRYPTION_DONE 0x00000080
168 #define RT2560_ENCRYPTION_DONE 0x00000100
178 #define RT2560_TX_BUSY (1 << 0)
181 #define RT2560_TX_RESULT_MASK 0x0000001c
182 #define RT2560_TX_SUCCESS (0 << 2)
194 #define RT2560_TX_IFS_MASK 0x00006000
195 #define RT2560_TX_IFS_BACKOFF (0 << 13)
202 #define RT2560_TX_CIPHER_MASK 0xe0000000
203 #define RT2560_TX_CIPHER_NONE (0 << 29)
209 #define RT2560_TX_RETRYCNT(v) (((v) >> 5) & 0x7)
213 #define RT2560_LOGCWMAX(x) (((x) & 0xf) << 12)
214 #define RT2560_LOGCWMIN(x) (((x) & 0xf) << 8)
215 #define RT2560_AIFSN(x) (((x) & 0x3) << 6)
216 #define RT2560_IVOFFSET(x) (((x) & 0x3f))
221 #define RT2560_PLCP_LENGEXT 0x80
234 #define RT2560_RX_BUSY (1 << 0)
241 #define RT2560_RX_CIPHER_MASK 0xe0000000
242 #define RT2560_RX_CIPHER_NONE (0 << 29)
258 #define RAL_RF1 0
263 #define RT2560_RF1_AUTOTUNE 0x08000
264 #define RT2560_RF3_AUTOTUNE 0x00040
271 #define RT2560_RF_2522 0x00
272 #define RT2560_RF_2523 0x01
273 #define RT2560_RF_2524 0x02
274 #define RT2560_RF_2525 0x03
275 #define RT2560_RF_2525E 0x04
276 #define RT2560_RF_2526 0x05
278 #define RT2560_RF_5222 0x10
280 #define RT2560_BBP_VERSION 0
284 #define RT2560_BBP_ANTA 0x00
285 #define RT2560_BBP_DIVERSITY 0x01
286 #define RT2560_BBP_ANTB 0x02
287 #define RT2560_BBP_ANTMASK 0x03
288 #define RT2560_BBP_FLIPIQ 0x04
290 #define RT2560_LED_MODE_DEFAULT 0
295 #define RT2560_JAPAN_FILTER 0x8
319 } while (/* CONSTCOND */0)
325 { RT2560_PSCSR0, 0x00020002 }, \
326 { RT2560_PSCSR1, 0x00000002 }, \
327 { RT2560_PSCSR2, 0x00020002 }, \
328 { RT2560_PSCSR3, 0x00000002 }, \
329 { RT2560_TIMECSR, 0x00003f21 }, \
330 { RT2560_CSR9, 0x00000780 }, \
331 { RT2560_CSR11, 0x07041483 }, \
332 { RT2560_CNT3, 0x00000000 }, \
333 { RT2560_TXCSR1, 0x07614562 }, \
334 { RT2560_ARSP_PLCP_0, 0x8c8d8b8a }, \
335 { RT2560_ACKPCTCSR, 0x7038140a }, \
336 { RT2560_ARTCSR1, 0x21212929 }, \
337 { RT2560_ARTCSR2, 0x1d1d1d1d }, \
338 { RT2560_RXCSR0, 0xffffffff }, \
339 { RT2560_RXCSR3, 0xb3aab3af }, \
340 { RT2560_PCICSR, 0x000003b8 }, \
341 { RT2560_PWRCSR0, 0x3f3b3100 }, \
342 { RT2560_GPIOCSR, 0x0000ff00 }, \
343 { RT2560_TESTCSR, 0x000000f0 }, \
344 { RT2560_PWRCSR1, 0x000001ff }, \
345 { RT2560_MACCSR0, 0x00213223 }, \
346 { RT2560_MACCSR1, 0x00235518 }, \
347 { RT2560_RLPWCSR, 0x00000040 }, \
348 { RT2560_RALINKCSR, 0x9a009a11 }, \
349 { RT2560_CSR7, 0xffffffff }, \
350 { RT2560_BBPCSR1, 0x82188200 }, \
351 { RT2560_TXACKCSR0, 0x00000020 }, \
352 { RT2560_SECCSR3, 0x0000e78f }
358 { 3, 0x02 }, \
359 { 4, 0x19 }, \
360 { 14, 0x1c }, \
361 { 15, 0x30 }, \
362 { 16, 0xac }, \
363 { 17, 0x48 }, \
364 { 18, 0x18 }, \
365 { 19, 0xff }, \
366 { 20, 0x1e }, \
367 { 21, 0x08 }, \
368 { 22, 0x08 }, \
369 { 23, 0x08 }, \
370 { 24, 0x80 }, \
371 { 25, 0x50 }, \
372 { 26, 0x08 }, \
373 { 27, 0x23 }, \
374 { 30, 0x10 }, \
375 { 31, 0x2b }, \
376 { 32, 0xb9 }, \
377 { 34, 0x12 }, \
378 { 35, 0x50 }, \
379 { 39, 0xc4 }, \
380 { 40, 0x02 }, \
381 { 41, 0x60 }, \
382 { 53, 0x10 }, \
383 { 54, 0x18 }, \
384 { 56, 0x08 }, \
385 { 57, 0x10 }, \
386 { 58, 0x08 }, \
387 { 61, 0x60 }, \
388 { 62, 0x10 }, \
389 { 75, 0xff }
397 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, \
398 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e \
403 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \
404 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \
409 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \
410 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \
415 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, \
416 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 \
421 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, \
422 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e \
427 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, \
428 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b \
433 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, \
434 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 \
439 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, \
440 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d \
448 { 1, 0x08808, 0x0044d, 0x00282 }, \
449 { 2, 0x08808, 0x0044e, 0x00282 }, \
450 { 3, 0x08808, 0x0044f, 0x00282 }, \
451 { 4, 0x08808, 0x00460, 0x00282 }, \
452 { 5, 0x08808, 0x00461, 0x00282 }, \
453 { 6, 0x08808, 0x00462, 0x00282 }, \
454 { 7, 0x08808, 0x00463, 0x00282 }, \
455 { 8, 0x08808, 0x00464, 0x00282 }, \
456 { 9, 0x08808, 0x00465, 0x00282 }, \
457 { 10, 0x08808, 0x00466, 0x00282 }, \
458 { 11, 0x08808, 0x00467, 0x00282 }, \
459 { 12, 0x08808, 0x00468, 0x00282 }, \
460 { 13, 0x08808, 0x00469, 0x00282 }, \
461 { 14, 0x08808, 0x0046b, 0x00286 }, \
463 { 36, 0x08804, 0x06225, 0x00287 }, \
464 { 40, 0x08804, 0x06226, 0x00287 }, \
465 { 44, 0x08804, 0x06227, 0x00287 }, \
466 { 48, 0x08804, 0x06228, 0x00287 }, \
467 { 52, 0x08804, 0x06229, 0x00287 }, \
468 { 56, 0x08804, 0x0622a, 0x00287 }, \
469 { 60, 0x08804, 0x0622b, 0x00287 }, \
470 { 64, 0x08804, 0x0622c, 0x00287 }, \
472 { 100, 0x08804, 0x02200, 0x00283 }, \
473 { 104, 0x08804, 0x02201, 0x00283 }, \
474 { 108, 0x08804, 0x02202, 0x00283 }, \
475 { 112, 0x08804, 0x02203, 0x00283 }, \
476 { 116, 0x08804, 0x02204, 0x00283 }, \
477 { 120, 0x08804, 0x02205, 0x00283 }, \
478 { 124, 0x08804, 0x02206, 0x00283 }, \
479 { 128, 0x08804, 0x02207, 0x00283 }, \
480 { 132, 0x08804, 0x02208, 0x00283 }, \
481 { 136, 0x08804, 0x02209, 0x00283 }, \
482 { 140, 0x08804, 0x0220a, 0x00283 }, \
484 { 149, 0x08808, 0x02429, 0x00281 }, \
485 { 153, 0x08808, 0x0242b, 0x00281 }, \
486 { 157, 0x08808, 0x0242d, 0x00281 }, \
487 { 161, 0x08808, 0x0242f, 0x00281 }