Lines Matching +full:0 +full:x1280

39 #define BIT_0                   (0x1 << 0)
40 #define BIT_1                   (0x1 << 1)
41 #define BIT_2                   (0x1 << 2)
42 #define BIT_3                   (0x1 << 3)
43 #define BIT_4                   (0x1 << 4)
44 #define BIT_5                   (0x1 << 5)
45 #define BIT_6                   (0x1 << 6)
46 #define BIT_7                   (0x1 << 7)
47 #define BIT_8                   (0x1 << 8)
48 #define BIT_9                   (0x1 << 9)
49 #define BIT_10                  (0x1 << 10)
50 #define BIT_11                  (0x1 << 11)
51 #define BIT_12                  (0x1 << 12)
52 #define BIT_13                  (0x1 << 13)
53 #define BIT_14                  (0x1 << 14)
54 #define BIT_15                  (0x1 << 15)
55 #define BIT_16                  (0x1 << 16)
56 #define BIT_17                  (0x1 << 17)
57 #define BIT_18                  (0x1 << 18)
58 #define BIT_19                  (0x1 << 19)
59 #define BIT_20                  (0x1 << 20)
60 #define BIT_21                  (0x1 << 21)
61 #define BIT_22                  (0x1 << 22)
62 #define BIT_23                  (0x1 << 23)
63 #define BIT_24                  (0x1 << 24)
64 #define BIT_25                  (0x1 << 25)
65 #define BIT_11                  (0x1 << 11)
66 #define BIT_12                  (0x1 << 12)
67 #define BIT_13                  (0x1 << 13)
68 #define BIT_14                  (0x1 << 14)
69 #define BIT_15                  (0x1 << 15)
70 #define BIT_16                  (0x1 << 16)
71 #define BIT_17                  (0x1 << 17)
72 #define BIT_18                  (0x1 << 18)
73 #define BIT_19                  (0x1 << 19)
74 #define BIT_20                  (0x1 << 20)
75 #define BIT_21                  (0x1 << 21)
76 #define BIT_22                  (0x1 << 22)
77 #define BIT_23                  (0x1 << 23)
78 #define BIT_24                  (0x1 << 24)
79 #define BIT_25                  (0x1 << 25)
80 #define BIT_26                  (0x1 << 26)
81 #define BIT_27                  (0x1 << 27)
82 #define BIT_28                  (0x1 << 28)
83 #define BIT_29                  (0x1 << 29)
84 #define BIT_30                  (0x1 << 30)
85 #define BIT_31                  (0x1 << 31)
94 #define Q81_WRKQ_INDEX_REG			0x00
95 #define		Q81_WRKQ_CONS_INDEX_MASK	0xFFFF0000
96 #define		Q81_WRKQ_PROD_INDEX_MASK	0x0000FFFF
97 #define	Q81_WRKQ_VALID_REG			0x04
104 #define Q81_COMPQ_INDEX_REG			0x00
105 #define		Q81_COMPQ_PROD_INDEX_MASK	0xFFFF0000
106 #define		Q81_COMPQ_CONS_INDEX_MASK	0x0000FFFF
107 #define	Q81_COMPQ_VALID_REG			0x04
109 #define Q81_LRGBQ_INDEX_REG			0x18
110 #define		Q81_LRGBQ_CONS_INDEX_MASK	0xFFFF0000
111 #define		Q81_LRGBQ_PROD_INDEX_MASK	0x0000FFFF
112 #define Q81_SMBQ_INDEX_REG			0x1C
113 #define		Q81_SMBQ_CONS_INDEX_MASK	0xFFFF0000
114 #define		Q81_SMBQ_PROD_INDEX_MASK	0x0000FFFF
120 #define Q81_CTL_PROC_ADDR		0x00 /* R/W  - Y - */
121 #define Q81_CTL_PROC_DATA		0x04 /* R/W  - Y - */
122 #define Q81_CTL_SYSTEM			0x08 /* MWR  - - - */
123 #define Q81_CTL_RESET			0x0C /* MWR  Y - - */
124 #define Q81_CTL_FUNC_SPECIFIC		0x10 /* MWR  Y - - */
125 #define Q81_CTL_HOST_CMD_STATUS		0x14 /* R/W  Y - - */
126 #define Q81_CTL_LED			0x18 /* R/W  Y - Y */
127 #define Q81_CTL_ICB_ACCESS_ADDR_LO	0x20 /* R/W  - Y - */
128 #define Q81_CTL_ICB_ACCESS_ADDR_HI	0x24 /* R/W  - Y - */
129 #define Q81_CTL_CONFIG			0x28 /* MWR  - - - */
130 #define Q81_CTL_STATUS			0x30 /* MWR  Y - - */
131 #define Q81_CTL_INTR_ENABLE		0x34 /* MWR  Y - - */
132 #define Q81_CTL_INTR_MASK		0x38 /* MWR  Y - - */
133 #define Q81_CTL_INTR_STATUS1		0x3C /* RO   Y - - */
134 #define Q81_CTL_INTR_STATUS2		0x40 /* RO   Y - - */
135 #define Q81_CTL_INTR_STATUS3		0x44 /* RO   Y - - */
136 #define Q81_CTL_INTR_STATUS4		0x48 /* RO   Y - - */
137 #define Q81_CTL_REV_ID			0x4C /* RO   - - - */
138 #define Q81_CTL_FATAL_ERR_STATUS	0x54 /* RO   Y - - */
139 #define Q81_CTL_COR_ECC_ERR_COUNTER	0x60 /* RO   Y - - */
140 #define Q81_CTL_SEMAPHORE		0x64 /* MWR  Y - - */
141 #define Q81_CTL_GPIO1			0x68 /* MWR  Y - - */
142 #define Q81_CTL_GPIO2			0x6C /* MWR  Y - - */
143 #define Q81_CTL_GPIO3			0x70 /* MWR  Y - - */
144 #define Q81_CTL_XGMAC_ADDR		0x78 /* R/W  Y Y - */
145 #define Q81_CTL_XGMAC_DATA		0x7C /* R/W  Y Y Y */
146 #define Q81_CTL_NIC_ENH_TX_SCHD		0x80 /* R/W  Y - Y */
147 #define Q81_CTL_CNA_ENH_TX_SCHD		0x84 /* R/W  Y - Y */
148 #define Q81_CTL_FLASH_ADDR		0x88 /* R/W  - Y - */
149 #define Q81_CTL_FLASH_DATA		0x8C /* R/W  - Y - */
150 #define Q81_CTL_STOP_CQ_PROCESSING	0x90 /* MWR  Y - - */
151 #define Q81_CTL_MAC_PROTO_ADDR_INDEX	0xA8 /* R/W  - Y - */
152 #define Q81_CTL_MAC_PROTO_ADDR_DATA	0xAC /* R/W  - Y - */
153 #define Q81_CTL_COS_DEF_CQ1		0xB0 /* R/W  Y - - */
154 #define Q81_CTL_COS_DEF_CQ2		0xB4 /* R/W  Y - - */
155 #define Q81_CTL_ETHERTYPE_SKIP_1	0xB8 /* R/W  Y - - */
156 #define Q81_CTL_ETHERTYPE_SKIP_2	0xBC /* R/W  Y - - */
157 #define Q81_CTL_SPLIT_HDR		0xC0 /* R/W  Y - - */
158 #define Q81_CTL_NIC_PAUSE_THRES		0xC8 /* R/W  Y - Y */
159 #define Q81_CTL_NIC_RCV_CONFIG		0xD4 /* MWR  Y - Y */
160 #define Q81_CTL_COS_TAGS_IN_NIC_FIFO	0xDC /* R/W  Y - Y */
161 #define Q81_CTL_MGMT_RCV_CONFIG		0xE0 /* MWR  Y - Y */
162 #define Q81_CTL_ROUTING_INDEX		0xE4 /* R/W  Y Y - */
163 #define Q81_CTL_ROUTING_DATA		0xE8 /* R/W  Y Y - */
164 #define Q81_CTL_XG_SERDES_ADDR		0xF0 /* R/W  Y Y Y */
165 #define Q81_CTL_XG_SERDES_DATA		0xF4 /* R/W  Y Y Y */
166 #define Q81_CTL_XG_PROBE_MUX_ADDR	0xF8 /* R/W  - Y - */
167 #define Q81_CTL_XG_PROBE_MUX_DATA	0xFC /* R/W  - Y - */
170  * Process Address Register (0x00)
175 #define Q81_CTL_PROC_ADDR_MPI_RISC	(0x00 << 16)
176 #define Q81_CTL_PROC_ADDR_MDE		(0x01 << 16)
177 #define Q81_CTL_PROC_ADDR_REG_BLOCK	(0x02 << 16)
178 #define Q81_CTL_PROC_ADDR_RISC_INT_REG	(0x03 << 16)
181  * System Register (0x08)
192  * Reset Register (0x0C)
199  * Function Specific Control Register (0x10)
208 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_MASK	(0x7 << 8)
209 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_2K	(0x1 << 8)
210 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_4K	(0x2 << 8)
211 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_8K	(0x3 << 8)
212 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_64K	(0x6 << 8)
217 #define Q81_CTL_FUNC_SPECIFIC_DBL_DBRST		(0x00 << 3)
218 #define Q81_CTL_FUNC_SPECIFIC_DBL_MAX_PAYLDSZ	(0x01 << 3)
219 #define Q81_CTL_FUNC_SPECIFIC_DBL_MAX_RDBRSTSZ	(0x02 << 3)
220 #define Q81_CTL_FUNC_SPECIFIC_DBL_128		(0x03 << 3)
221 #define Q81_CTL_FUNC_SPECIFIC_DBRST_256		0x00			
222 #define Q81_CTL_FUNC_SPECIFIC_DBRST_512		0x01			
223 #define Q81_CTL_FUNC_SPECIFIC_DBRST_768		0x02			
224 #define Q81_CTL_FUNC_SPECIFIC_DBRST_1024	0x03			
227  * Host Command/Status Register (0x14)
229 #define Q81_CTL_HCS_CMD_NOP			(0x00 << 28)
230 #define Q81_CTL_HCS_CMD_SET_RISC_RESET		(0x01 << 28)
231 #define Q81_CTL_HCS_CMD_CLR_RISC_RESET		(0x02 << 28)
232 #define Q81_CTL_HCS_CMD_SET_RISC_PAUSE		(0x03 << 28)
233 #define Q81_CTL_HCS_CMD_CLR_RISC_PAUSE		(0x04 << 28)
234 #define Q81_CTL_HCS_CMD_SET_HTR_INTR		(0x05 << 28)
235 #define Q81_CTL_HCS_CMD_CLR_HTR_INTR		(0x06 << 28)
236 #define Q81_CTL_HCS_CMD_SET_PARITY_EN		(0x07 << 28)
237 #define Q81_CTL_HCS_CMD_FORCE_BAD_PARITY	(0x08 << 28)
238 #define Q81_CTL_HCS_CMD_CLR_BAD_PARITY		(0x09 << 28)
239 #define Q81_CTL_HCS_CMD_CLR_RTH_INTR		(0x0A << 28)
245 #define Q81_CTL_HCS_ERR_STATUS_MASK		0x3F
248  * Configuration Register (0x28)
252 #define Q81_CTL_CONFIG_Q_NUM_MASK	(0x7F << Q81_CTL_CONFIG_Q_NUM_SHIFT)
262  * Status Register (0x30)
279  * Interrupt Enable Register (0x34)
285 #define Q81_CTL_INTRE_RTYPE_MASK		(0x3 << 8)
286 #define Q81_CTL_INTRE_RTYPE_ENABLE		(0x1 << 8)
287 #define Q81_CTL_INTRE_RTYPE_DISABLE		(0x2 << 8)
288 #define Q81_CTL_INTRE_RTYPE_SETUP_TO_RD		(0x3 << 8)
289 #define Q81_CTL_INTRE_HOST_INTR_MASK		0x7F
292  * Interrupt Mask Register (0x38)
304  * Interrupt Status 1 Register (0x3C)
306 #define Q81_CTL_INTRS1_COMPQ(i)			(0x1 << i)
309  * Interrupt Status 2 Register (0x40)
311 #define Q81_CTL_INTRS2_COMPQ(i)			(0x1 << i)
314  * Interrupt Status 3 Register (0x44)
316 #define Q81_CTL_INTRS3_COMPQ(i)			(0x1 << i)
319  * Interrupt Status 4 Register (0x48)
321 #define Q81_CTL_INTRS4_COMPQ(i)			(0x1 << i)
324  * Revision ID Register (0x4C)
326 #define Q81_CTL_REV_ID_CHIP_REV_MASK		(0xF << 28)
327 #define Q81_CTL_REV_ID_XGMAC_RCV_MASK		(0xF << 16)
328 #define Q81_CTL_REV_ID_XGMAC_ROLL_MASK		(0xF << 8)
329 #define Q81_CTL_REV_ID_NIC_REV_MASK		(0xF << 4)
330 #define Q81_CTL_REV_ID_NIC_ROLL_MASK		(0xF << 0)
333  * Semaphore Register (0x64)
336 #define Q81_CTL_SEM_MASK_PROC_ADDR_NIC_RCV	0xC0000000
338 #define Q81_CTL_SEM_MASK_RIDX_DATAREG		0x30000000
340 #define Q81_CTL_SEM_MASK_FLASH			0x03000000
342 #define Q81_CTL_SEM_MASK_MAC_SERDES		0x00C00000
344 #define Q81_CTL_SEM_MASK_ICB			0x00300000
346 #define Q81_CTL_SEM_MASK_XGMAC1			0x000C0000
348 #define Q81_CTL_SEM_MASK_XGMAC0			0x00030000
350 #define Q81_CTL_SEM_SET_PROC_ADDR_NIC_RCV	0x4000
351 #define Q81_CTL_SEM_SET_RIDX_DATAREG		0x1000
352 #define Q81_CTL_SEM_SET_FLASH			0x0100
353 #define Q81_CTL_SEM_SET_MAC_SERDES		0x0040
354 #define Q81_CTL_SEM_SET_ICB			0x0010
355 #define Q81_CTL_SEM_SET_XGMAC1			0x0004
356 #define Q81_CTL_SEM_SET_XGMAC0			0x0001
359  * Flash Address Register (0x88)
364 #define Q81_CTL_FLASH_ADDR_MASK			0x7FFFFF
367  * Stop CQ Processing Register (0x90)
371 #define Q81_CTL_STOP_CQ_RQ_STARTQ		(0x1 << 8)
372 #define Q81_CTL_STOP_CQ_RQ_STOPQ		(0x2 << 8)
373 #define Q81_CTL_STOP_CQ_RQ_READ			(0x3 << 8)
374 #define Q81_CTL_STOP_CQ_MASK			0x7F
377  * MAC Protocol Address Index Register (0xA8)
385 #define Q81_CTL_MAC_PROTO_AI_TYPE_MASK		0xF0000
387 #define Q81_CTL_MAC_PROTO_AI_IDX_MASK		0xFFF0
388 #define Q81_CTL_MAC_PROTO_AI_OFF_MASK		0xF
390 #define Q81_CTL_MAC_PROTO_AI_TYPE_CAM_MAC	(0 << 16)
403 #define Q81_CAM_MAC_OFF2_ROUTE_FC		0x00000000
404 #define Q81_CAM_MAC_OFF2_ROUTE_NIC		0x00000001
406 #define Q81_CAM_MAC_OFF2_RV			0x00000010
408 #define Q81_CAM_MAC_OFF2_SH			0x00008000
409 #define Q81_CAM_MAC_OFF2_MHT			0x40000000
410 #define Q81_CAM_MAC_OFF2_VLD			0x80000000
413  * NIC Pause Threshold Register (0xC8)
416 #define Q81_CTL_NIC_PAUSE_THRES_RESUME_SHIFT	0
419  * NIC Receive Configuration Register (0xD4)
423 #define Q81_CTL_NIC_RCVC_DCQ_MASK		0x7F00
427 #define Q81_CTL_NIC_RCVC_VLAN_ALL		(0x0 << 1)
428 #define Q81_CTL_NIC_RCVC_VLAN_ONLY		(0x1 << 1)
429 #define Q81_CTL_NIC_RCVC_VLAN_NON_VLAN		(0x2 << 1)
430 #define Q81_CTL_NIC_RCVC_VLAN_REJECT		(0x3 << 1)
434  * Routing Index Register (0xE4)
441 #define Q81_CTL_RI_DST_RSS			(0x00 << 20)
442 #define Q81_CTL_RI_DST_CAMQ			(0x01 << 20)
443 #define Q81_CTL_RI_DST_COSQ			(0x02 << 20)
444 #define Q81_CTL_RI_DST_DFLTQ			(0x03 << 20)
445 #define Q81_CTL_RI_DST_DESTQ			(0x04 << 20)
446 #define Q81_CTL_RI_DST_DROP			(0x07 << 20)
448 #define Q81_CTL_RI_TYPE_RTMASK			(0x00 << 16)
449 #define Q81_CTL_RI_TYPE_RTINVMASK		(0x01 << 16)
450 #define Q81_CTL_RI_TYPE_NICQMASK		(0x02 << 16)
451 #define Q81_CTL_RI_TYPE_NICQINVMASK		(0x03 << 16)
454 #define Q81_CTL_RI_IDX_ALL_ERROR		(0x00 << 8)
455 #define Q81_CTL_RI_IDX_MAC_ERROR		(0x00 << 8)
456 #define Q81_CTL_RI_IDX_IPCSUM_ERROR		(0x01 << 8)
457 #define Q81_CTL_RI_IDX_TCPCSUM_ERROR		(0x02 << 8)
458 #define Q81_CTL_RI_IDX_BCAST			(0x03 << 8)
459 #define Q81_CTL_RI_IDX_MCAST_MATCH		(0x04 << 8)
460 #define Q81_CTL_RI_IDX_ALLMULTI			(0x05 << 8)
461 #define Q81_CTL_RI_IDX_RSS_MATCH		(0x08 << 8)
462 #define Q81_CTL_RI_IDX_RSS_IPV4			(0x08 << 8)
463 #define Q81_CTL_RI_IDX_RSS_IPV6			(0x09 << 8)
464 #define Q81_CTL_RI_IDX_RSS_TCPV4		(0x0A << 8)
465 #define Q81_CTL_RI_IDX_RSS_TCPV6		(0x0B << 8)
466 #define Q81_CTL_RI_IDX_CAM_HIT			(0x0C << 8)
467 #define Q81_CTL_RI_IDX_PROMISCUOUS		(0x0F << 8)
585 	uint16_t	mask; /* bits 9-0 are valid */
632 #define Q81_IOCB_TX_MAC		0x01
633 #define Q81_IOCB_TX_TSO		0x02
634 #define Q81_IOCB_RX		0x20
635 #define Q81_IOCB_MPI		0x21
636 #define Q81_IOCB_SYS		0x3F
789 #define Q81_SYS_COMPE_LINK_UP		0x00
790 #define Q81_SYS_COMPE_LINK_DOWN		0x01
791 #define Q81_SYS_COMPE_MULTI_CAM_LOOKUP	0x06
792 #define Q81_SYS_COMPE_SOFT_ECC		0x07
793 #define Q81_SYS_COMPE_MPI_FATAL_ERROR	0x08
794 #define Q81_SYS_COMPE_MAC_INTR		0x09
795 #define Q81_SYS_COMPE_GPI0_HTOL		0x10
796 #define Q81_SYS_COMPE_GPI0_LTOH		0x20
797 #define Q81_SYS_COMPE_GPI1_HTOL		0x11
798 #define Q81_SYS_COMPE_GPI1_LTOH		0x21
800 	uint8_t		q_id; /* only bits 0-6 are valid */
820 #define Q81_RX_FLAGS0_MCAST_MASK	(0x03 << 5)
821 #define Q81_RX_FLAGS0_MCAST_NONE	(0x00 << 5)
822 #define Q81_RX_FLAGS0_MCAST_HASH_MATCH	(0x01 << 5)
823 #define Q81_RX_FLAGS0_MCAST_REG_MATCH	(0x02 << 5)
824 #define Q81_RX_FLAGS0_MCAST_PROMISC	(0x03 << 5)
832 #define Q81_RX_FLAGS1_ERR_NONE		(0x00 << 2)
833 #define Q81_RX_FLAGS1_ERR_CODE		(0x01 << 2)
834 #define Q81_RX_FLAGS1_ERR_OSIZE		(0x02 << 2)
835 #define Q81_RX_FLAGS1_ERR_USIZE		(0x04 << 2)
836 #define Q81_RX_FLAGS1_ERR_PREAMBLE	(0x05 << 2)
837 #define Q81_RX_FLAGS1_ERR_FRAMELENGTH	(0x06 << 2)
838 #define Q81_RX_FLAGS1_ERR_CRC		(0x07 << 2)
839 #define Q81_RX_FLAGS1_ERR_MASK		(0x07 << 2)
844 #define Q81_RX_FLAGS1_RSS_NO_MATCH	(0x00 << 8)
845 #define Q81_RX_FLAGS1_RSS_IPV4_MATCH	(0x04 << 8)
846 #define Q81_RX_FLAGS1_RSS_IPV6_MATCH	(0x02 << 8)
847 #define Q81_RX_FLAGS1_RSS_TCPIPV4_MATCH	(0x05 << 8)
848 #define Q81_RX_FLAGS1_RSS_TCPIPV4_MATCH	(0x05 << 8)
849 #define Q81_RX_FLAGS1_RSS_MATCH_MASK	(0x07 << 8)
963 #define Q81_F0_FLASH_OFFSET	0x140200
964 #define Q81_F1_FLASH_OFFSET	0x140600
1008 #define Q81_FUNC0_MBX_IN_REG0	0x1180
1009 #define Q81_FUNC0_MBX_OUT_REG0	0x1190
1011 #define Q81_FUNC1_MBX_IN_REG0	0x1280
1012 #define Q81_FUNC1_MBX_OUT_REG0	0x1290
1014 #define Q81_MBX_NOP		0x0000
1015 #define Q81_MBX_EXEC_FW		0x0002
1016 #define Q81_MBX_REG_TEST	0x0006
1017 #define Q81_MBX_VERIFY_CHKSUM	0x0007
1018 #define Q81_MBX_ABOUT_FW	0x0008
1019 #define Q81_MBX_RISC_MEMCPY	0x000A
1020 #define Q81_MBX_LOAD_RISC_RAM	0x000B
1021 #define Q81_MBX_DUMP_RISC_RAM	0x000C
1022 #define Q81_MBX_WR_RAM_WORD	0x000D
1023 #define Q81_MBX_INIT_RISC_RAM	0x000E
1024 #define Q81_MBX_RD_RAM_WORD	0x000F
1025 #define Q81_MBX_STOP_FW		0x0014
1026 #define Q81_MBX_GEN_SYS_ERR	0x002A
1027 #define Q81_MBX_WR_SFP_PLUS	0x0030
1028 #define Q81_MBX_RD_SFP_PLUS	0x0031
1029 #define Q81_MBX_INIT_FW		0x0060
1030 #define Q81_MBX_GET_IFCB	0x0061
1031 #define Q81_MBX_GET_FW_STATE	0x0069
1032 #define Q81_MBX_IDC_REQ		0x0100
1033 #define Q81_MBX_IDC_ACK		0x0101
1034 #define Q81_MBX_IDC_TIME_EXTEND	0x0102
1035 #define Q81_MBX_WOL_MODE	0x0110
1036 #define Q81_MBX_SET_WOL_FILTER	0x0111
1037 #define Q81_MBX_CLR_WOL_FILTER	0x0112
1038 #define Q81_MBX_SET_WOL_MAGIC	0x0113
1039 #define Q81_MBX_WOL_MODE_IMM	0x0115
1040 #define Q81_MBX_PORT_RESET	0x0120
1041 #define Q81_MBX_SET_PORT_CFG	0x0122
1042 #define Q81_MBX_GET_PORT_CFG	0x0123
1043 #define Q81_MBX_GET_LNK_STATUS	0x0124
1044 #define Q81_MBX_SET_LED_CFG	0x0125
1045 #define Q81_MBX_GET_LED_CFG	0x0126
1046 #define Q81_MBX_SET_DCBX_CTLB	0x0130
1047 #define Q81_MBX_GET_DCBX_CTLB	0x0131
1048 #define Q81_MBX_GET_DCBX_TLV	0x0132
1049 #define Q81_MBX_DIAG_CMDS	0x0150
1050 #define Q81_MBX_SET_MGMT_CTL	0x0160
1051 #define		Q81_MBX_SET_MGMT_CTL_STOP	0x01
1052 #define		Q81_MBX_SET_MGMT_CTL_RESUME	0x02
1053 #define Q81_MBX_GET_MGMT_CTL	0x0161
1054 #define		Q81_MBX_GET_MGMT_CTL_MASK	~0x3
1055 #define		Q81_MBX_GET_MGMT_CTL_FIFO_EMPTY	0x02
1056 #define		Q81_MBX_GET_MGMT_CTL_SET_MGMT	0x01
1058 #define Q81_MBX_CMD_COMPLETE	0x4000
1059 #define Q81_MBX_CMD_INVALID	0x4001
1060 #define Q81_MBX_CMD_TEST_FAILED	0x4003
1061 #define Q81_MBX_CMD_ERROR	0x4005
1062 #define Q81_MBX_CMD_PARAM_ERROR	0x4006