Lines Matching refs:uint32_t

39         uint32_t  entry_type ;
40         uint32_t  first_entry_offset ;
41         uint32_t  size_of_template ;
42         uint32_t  recommended_capture_mask;
44         uint32_t  num_of_entries ;
45         uint32_t  version ;
46         uint32_t  driver_timestamp ;
47         uint32_t  checksum ;
49         uint32_t  driver_capture_mask ;
50         uint32_t  driver_info_word2 ;
51         uint32_t  driver_info_word3 ;
52         uint32_t  driver_info_word4 ;
54         uint32_t  saved_state_array[QL_DBG_STATE_ARRAY_LEN] ;
55         uint32_t  capture_size_array[QL_DBG_CAP_SIZE_ARRAY_LEN] ;
57         uint32_t ocm_window_array[QL_NO_OF_OCM_WINDOWS] ;
146         uint32_t      entry_type ;
147         uint32_t      entry_size ;
148         uint32_t      entry_capture_size ;
156         	uint32_t entry_ctrl_word ;
173     uint32_t entry_data00 ;
174     uint32_t entry_data01 ;
175     uint32_t entry_data02 ;
176     uint32_t entry_data03 ;
178     uint32_t entry_data04 ;
179     uint32_t entry_data05 ;
180     uint32_t entry_data06 ;
181     uint32_t entry_data07 ;
191         uint32_t addr ;
198             uint32_t addr_cntrl  ;
201         uint32_t data_size ;
202         uint32_t op_count;
204     uint32_t    rsvd_2 ;
205     uint32_t    rsvd_3 ;
206     uint32_t    rsvd_4 ;
207     uint32_t    rsvd_5 ;
218         uint32_t tag_reg_addr ;
224             	uint32_t select_addr_cntrl  ;
227         uint32_t data_size ;
228         uint32_t op_count;
230     	uint32_t control_addr ;
237         	uint32_t control_value ;
240     	uint32_t read_addr ;
247             	uint32_t read_addr_cntrl  ;
258         uint32_t rsvd_0 ;
259         uint32_t rsvd_1 ;
261         uint32_t data_size ;
262         uint32_t op_count;
264     uint32_t rsvd_2 ;
265     uint32_t rsvd_3 ;
267     uint32_t read_addr ;
268     uint32_t read_addr_stride ;
279     uint32_t rsvd_0[6] ;
281     uint32_t read_addr ;
282     uint32_t read_data_size ;
293     uint32_t rsvd_0[6] ;
295     uint32_t read_addr ;
296     uint32_t read_data_size ;
307         uint32_t select_addr ;
310             uint32_t rsvd_0 ;
312             uint32_t select_addr_cntrl  ;
315         uint32_t data_size ;
316         uint32_t op_count;
318     uint32_t select_value ;
319     uint32_t select_value_stride ;
321     uint32_t read_addr ;
322     uint32_t rsvd_1 ;
333         uint32_t select_addr_1;
334         uint32_t select_addr_2;
335         uint32_t select_value_1;
336         uint32_t select_value_2;
337         uint32_t select_value_count;
338         uint32_t select_value_mask;
339         uint32_t read_addr;
347                 uint32_t select_addr_value_cntrl;
359         uint32_t select_addr ;
365             uint32_t select_addr_cntrl  ;
368         uint32_t data_size ;
369         uint32_t op_count ;
371     uint32_t rsvd_1 ;
372     uint32_t rsvd_2 ;
374     uint32_t read_addr ;
381             uint32_t read_addr_cntrl  ;
393         uint32_t addr ;
400             uint32_t addr_cntrl  ;
403         uint32_t data_size ;
404         uint32_t op_count;
413         uint32_t control_value ;
416     uint32_t value_1 ;
417     uint32_t value_2 ;
418     uint32_t value_3 ;
428         uint32_t select_addr;
429         uint32_t read_addr;
430         uint32_t select_value;
436                 uint32_t select_value_cntrl;
439         uint32_t poll;
440         uint32_t mask;
442         uint32_t data_size;
443         uint32_t rsvd_0;
454         uint32_t addr_1;
455         uint32_t addr_2;
456         uint32_t value_1;
457         uint32_t value_2;
458         uint32_t poll;
459         uint32_t mask;
460         uint32_t modify_mask;
461         uint32_t data_size;