Lines Matching +full:0 +full:x720

135 #define OC_SKH_DEVICE_PF 0x720
136 #define OC_SKH_DEVICE_VF 0x728
148 #define QLNXR_MAX_SQ_PBL (0x8000) /* 2^15 bytes */
149 #define QLNXR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *)) /* number */
158 #define QLNXR_MAX_RQ_PBL (0x2000) /* 2^13 bytes */
159 #define QLNXR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *)) /* number */
171  * calculation that comes from having a u16 for the number of pages i.e. 0xffff
187 #define QLNXR_ROCE_MAX_CNQ_SIZE          (0x4000) /* 2^16 */
199 #define QLNXR_CQ_MAGIC_NUMBER    (0x11223344)
200 #define QLNXR_QP_MAGIC_NUMBER    (0x77889900)
208 #define QLNXR_MSG_INIT		0x10000,
209 #define QLNXR_MSG_FAIL		0x10000,
210 #define QLNXR_MSG_CQ		0x20000,
211 #define QLNXR_MSG_RQ		0x40000,
212 #define QLNXR_MSG_SQ		0x80000,
214 #define QLNXR_MSG_MR		0x100000,
215 #define QLNXR_MSG_GSI		0x200000,
216 #define QLNXR_MSG_MISC		0x400000,
217 #define QLNXR_MSG_SRQ		0x800000,
218 #define QLNXR_MSG_IWARP		0x1000000,
222 #define QLNXR_ROCE_PKEY_DEFAULT		0xffff
226 #define QLNXR_ENET_STATE_BIT     (0)
296 #define QLNXR_ROCE_DEV_CAP_RNR_NAK_MASK                           0x1
297 #define QLNXR_ROCE_DEV_CAP_RNR_NAK_SHIFT                  0
299 #define QLNXR_ROCE_DEV_CAP_SHUTDOWN_PORT_MASK                     0x1
302 #define QLNXR_ROCE_DEV_CAP_PORT_ACTIVE_EVENT_MASK         0x1
305 #define QLNXR_ROCE_DEV_CAP_PORT_CHANGE_EVENT_MASK         0x1
308 #define QLNXR_ROCE_DEV_CAP_SYS_IMAGE_MASK                 0x1
311 #define QLNXR_ROCE_DEV_CAP_BAD_PKEY_CNT_MASK                      0x1
314 #define QLNXR_ROCE_DEV_CAP_ATOMIC_OP_MASK                 0x1
316 #define QLNXR_ROCE_DEV_CAP_RESIZE_CQ_MASK                 0x1
321 #define QLNXR_ROCE_DEV_CAP_RESIZE_MAX_WR_MASK                     0x1
325 #define QLNXR_ROCE_DEV_CAP_AUTO_PATH_MIG_MASK                     0x1
328 #define QLNXR_ROCE_DEV_CAP_BASE_MEMORY_EXT_MASK                   0x1
330 #define QLNXR_ROCE_DEV_CAP_BASE_QUEUE_EXT_MASK                    0x1
333 #define QLNXR_ROCE_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK             0x1
336 #define QLNXR_ROCE_DEV_CAP_BLOCK_MODE_MASK                        0x1
339 #define QLNXR_ROCE_DEV_CAP_ZBVA_MASK                              0x1
342 #define QLNXR_ROCE_DEV_CAP_LOCAL_INV_FENCE_MASK                   0x1
345 #define QLNXR_ROCE_DEV_CAP_LB_INDICATOR_MASK                      0x1
577         } while (0)
607         QLNXR_QP_ERR_SQ_FULL     = 1 << 0,
804                 return 0;  in qlnxr_qp_has_sq()
812                 return 0;  in qlnxr_qp_has_rq()
820         } while (0)
837         union ib_gid zero_sgid = { { 0 } };  in qlnxr_get_dmac()
841                 memset(mac_addr, 0x00, ETH_ALEN);  in qlnxr_get_dmac()
849         mac_addr[0] = guid[0] ^ 2; /* toggle the local/universal bit to local */  in qlnxr_get_dmac()
858         return 0;  in qlnxr_get_dmac()
866 #define QLNXR_ROCE_PKEY_DEFAULT 0xffff