Lines Matching +full:umac +full:- +full:reset
2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
147 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
185 …2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
189 …20 // This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)
210 …s (de-asserted) regardless of any internal chip logic. Setting this bit has no effect on the INT_S…
250 …n Revision ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
252 …ing Interface. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
254 …t Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
256 …t Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
261 … (0xffffff<<8) // The 24-bit Class Code regist…
281 …multifunction. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
290 …ADER_TYPE_BB (0xff<<16) // The 8-bit Header Type regis…
292 … (0xff<<24) // The 8-bit BIST register is used to initiate and report the results o…
297 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
304 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
306 … (0x3<<1) // BAR0 32-bit or 64-bit. Note: The access attributes of this field a…
308 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
310 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
312 …-bit BAR_1 register programs the base address for the memory space mapped by the card onto the PCI…
315 …icate that BAR_1 may be programmed to map this adapter to anywhere in the 64-bit address space. Pa…
317 … (0x1<<3) // This bit indicates that the area mapped by BAR_1 may be pre-fetched or cached by …
319 …-bit address space that will be card will respond in. These bits may be combined with the bits in …
323 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
325 … (0x3<<1) // BAR1 32-bit or 64-bit. Note: The access attributes of this field a…
327 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
329 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
331 … 0x000014UL //Access:RW DataWidth:0x20 // The 32-bit BAR_2 register pr…
335 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
342 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
344 … (0x3<<1) // BAR2 32-bit or 64-bit. Note: The access attributes of this field a…
346 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
348 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
350 …-bit BAR_3 register programs the 2nd base address for the memory space mapped by the card onto the…
353 …icate that BAR_2 may be programmed to map this adapter to anywhere in the 64-bit address space. Pa…
355 … (0x1<<3) // This bit indicates that the area mapped by BAR_2 may be pre-fetched or cached by …
357 …-bit address space that will be card will respond in. These bits may be combined with the bits in …
361 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
363 … (0x3<<1) // BAR3 32-bit or 64-bit. Note: The access attributes of this field a…
365 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
367 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
369 … 0x00001cUL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register pr…
373 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
380 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
382 … (0x3<<1) // BAR4 32-bit or 64-bit. Note: The access attributes of this field a…
384 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
386 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
388 …-bit BAR_5 register programs the 3rd base address for the memory space mapped by the card onto the…
391 …icate that BAR_3 may be programmed to map this adapter to anywhere in the 64-bit address space. Pa…
393 … (0x1<<3) // This bit indicates that the area mapped by BAR_3 may be pre-fetched or cached by …
395 …-bit address space that will be card will respond in. These bits may be combined with the bits in …
399 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
401 … (0x3<<1) // BAR5 32-bit or 64-bit. Note: The access attributes of this field a…
403 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
405 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
407 … 0x000024UL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register pr…
412 … (0xffff<<0) // Subsystem vendor ID. Assigned by PCI-SIG, writable through…
414 … (0xffff<<16) // Subsystem ID. Assigned by PCI-SIG, writable through…
417 …tem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
419 …tem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
422 …VENDOR_ID_BB (0xffff<<0) // The 16-bit Subsystem Vendor …
424 …D_BB (0xffff<<16) // The 16-bit Subsystem ID regi…
432 …<<0) // Expansion ROM Enable. Note: The access attributes of this field are as follows: - Dbi: R
434 …Expansion ROM Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W
436 … 0x000030UL //Access:RW DataWidth:0x20 // The 32-bit Expansion ROM BAR…
449 …ity Structure. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
452 …-bit Capabilities Pointer register specifies an offset in the PCI address space of a linked list o…
466 …egister Field. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
469 …_INT_LINE_BB (0xff<<0) // The 8-bit Interrupt Line re…
471 …_INT_PIN_BB (0xff<<8) // The 8-bit Interrupt Pin reg…
499 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
501 … Spec Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
505 … Return to D0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
507 …alization Bit. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
509 … Requirements. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
511 …State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
513 …State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
515 …reset value PME_SUPPORT_n && {sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1}, where PME_SUPP…
520 … (0x1<<3) // No soft reset, writable through …
537 …owever, the read-back value is the actual power state, not the write value. Note: The access attr…
539 … (0x1<<3) // No soft Reset. Note: The access attributes of this field are a…
556 … (0xff<<0) // The 8-bit Power Management …
558 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
568 …a specific initialization (DSI) sequence following a transition to the D0 un-initialized state. Th…
591 …hen device transitions from D3 to D0, device does not perform an internal reset. This bit can be p…
595 …(0x1<<8) // This bit enables the device to transmit PME messages. On HARD reset, this bit resets t…
601 …erted low. This bit is cleared by writing a 1 in this bit position. At power-up, the chip must cle…
605 …from one of eight values by the DATA_SEL bits of the PM_CSR register. The reset value of all 9 of …
610 … Next Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
614 …ssage Capable. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
618 … (0x1<<23) // MSI 64-bit Address Capable. Note: The access attributes of this fiel…
623 … (0xff<<0) // The 8-bit VPD Capability ID…
625 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
629 …// This value is the 32-bit word address of the VPD value being accessed in the vpd_data register.…
631 …bit is used to control passing of data between the vpd_data register and Non-Volatile memory. To r…
634 …essage Lower Address Field. Note: The access attributes of this field are as follows: - Dbi: R/W
638 …-bit MSI Message, this field contains Data. For 64-bit it contains lower 16 bits of the Upper Addr…
640 …is reserved. For 64-bit it contains upper 16 bits of the Upper Address. Note: The access attribut…
643 … (0xff<<0) // The 8-bit MSI Capability ID…
645 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
658 …-bit MSI Message, this field contains Data. For 32-bit, it contains the lower Mask Bits if PVM is …
660 …-bit MSI Message, this field contains Data. For 32-bit, it contains the upper Mask Bits if PVM is …
676 … (0xff<<8) // Next capability pointer. Points to the MSI-X Capabilities by def…
689 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
695 …emented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
697 …essage Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
712 … (0x1<<15) // Role-based error reporting…
718 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV c…
721 …ize Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
723 …ons Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
725 …eld Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
727 …table latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
729 …table latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
731 … (0x1<<15) // Role-based Error Reporting Implemented. Note: The access attributes of th…
737 …(0x1<<28) // Function Level Reset Capability (endpoints only). Note: The access attributes of th…
762 … (0x1<<15) // Initiate function level reset. [I_FLR] must no…
764 …if we receive any of the errors in PCIEEP_COR_ERR_STAT, for example a replay-timer timeout. Also,…
770 …ests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message shoul…
779 …S_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting…
789 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
791 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
795 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
799 …LR_K2 (0x1<<15) // Initiate Function Level Reset (for endpoints).
803 …_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
816 …reset value of this field is determined by the value read from PEM()_CFG[LANES]. This field is w…
837 …In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The …
839 …In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The …
841 …ment) Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
843 …- CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1…
845 …- CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1…
847 …er Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
855 …ty Compliance. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
857 …/ Port Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
899 …d Completion Boundary (RCB). Note: The access attributes of this field are as follows: - Dbi: R/W
901 …_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_EN…
903 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
909 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
911 …e Autonomous Width Disable. Note: The access attributes of this field are as follows: - Dbi: R/W
913 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
915 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
923 …figuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
925 …Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
929 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
931 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
942 … (0x1<<7) // 32-bit AtomicOp supporte…
944 … (0x1<<8) // 64-bit AtomicOp supporte…
946 … (0x1<<9) // 128-bit AtomicOp supporte…
948 … (0x1<<10) // No RO-enabled PR-PR passing. (Thi…
956 …SUPP_E5 (0x1<<16) // 10-bit tag completer sup…
958 …SUPP_E5 (0x1<<17) // 10-bit tag requestor sup…
964 … (0x1<<21) // End-end TLP prefix suppor…
966 … (0x3<<22) // Max end-end TLP prefixes. 0x…
983 …R2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
1010 …EN_E5 (0x1<<12) // 10-bit tag requester ena…
1014 … (0x1<<15) // End-end TLP prefix blocki…
1017 …/ Completion Timeout Value. Note: The access attributes of this field are as follows: - Dbi: R/W
1049 …DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1052 …reset value of this field is controlled by the value read from PEM()_CFG[MD]. _ MD is 0x0, reset…
1054 …y setting this bit to one in both components on a link and then initiating a hot reset on the link.
1056 …he application must disable hardware from changing the link speed for device-specific reasons othe…
1060 …-deemphasized voltage level at the transmitter pins: 0x0 = 800-1200 mV for full swing 400-600 mV …
1066 …ntry occurred due to the TX compliance receive bit being one. 0x0 = -6 dB. 0x1 = -3.5 dB. When…
1068 …ting at 5 GT/s speed, this bit reflects the level of deemphasis. 0 = -6 dB. 1 = -3.5 dB. The v…
1091 …K_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the conten…
1095 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1097 …EMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
1101 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1103 … transmission. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1105 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
1107 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
1126 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
1128 …f<<16) // System sw reads this field to determine the MSI-X table size N, which is encoded as N-1 …
1137 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X table into memory s…
1142 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X PBA into memory spa…
1157 …-X vector is used for the interrupt message generated in association with any of the status bits o…
1160 …MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
1164 … (0x7ff<<16) // MSI-X table size encoded as (table size - 1)…
1166 …ctors associated with the function are masked, regardless of their respective per-vector mask bits.
1168 … (0x1<<31) // MSI-X enable. If MSI-X is enabled,…
1170 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
1171 …TRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
1173 … (0xff<<8) // MSI-X Next Capability Pointer. Note: The access attributes of this f…
1175 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
1177 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
1179 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
1205 … (0x7<<0) // MSI-X table BAR indicator register (BIR). Indicates which BAR is u…
1207 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
1209 … 0x0000b4UL //Access:RW DataWidth:0x20 // MSI-X Table Offset and BI…
1210 … (0x7<<0) // MSI-X Table Bar Indicator Register Field. Note: The access attributes of …
1212 … (0x1fffffff<<3) // MSI-X Table Offset. Note: The access attributes of this field …
1217 …L_ERR_REPORT_EN_BB (0x1<<1) // Non-Fatal Error Reporting…
1237 …reset. This bit is writeable only if flr_supported bit in private device_capability register is se…
1241 …TAL_ERR_DET_BB (0x1<<17) // Non-Fatal Error Detected.…
1249 … (0x1<<21) // This is bit is read back a 1, whenever a non-posted request initia…
1252 … (0x7<<0) // MSI-X PBA BAR indicator register (BIR). Indicates which BAR is us…
1254 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
1256 … 0x0000b8UL //Access:RW DataWidth:0x20 // MSI-X PBA Offset and BIR …
1257 … (0x7<<0) // MSI-X PBA BIR. Note: The access attributes of this field are…
1259 … (0x1fffffff<<3) // MSI-X PBA Offset. Note: The access attributes of this field a…
1317 … (0x1<<28) // Slot Clock configuration. This bit is read-only by host, but rea…
1355 …xt Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1357 …0x7fff<<16) // VPD Address. Note: The access attributes of this field are as follows: - Dbi: R/W
1359 … (0x1<<31) // VPD Flag. Note: The access attributes of this field are as follows: - Dbi: R/W
1404 … all 0's to allow compliance with PCIE spec 1.1. To enable this register, reset comply_pcie_1_1 bi…
1411 …6) // When link is operating at Gen2 rates, this bit selects the level of de-emphasis. Path= i_cfg…
1425 … (0x1<<17) // Equalization Complete - when set, this indic…
1427 … (0x1<<18) // Equalization Phase 1 Successful - when set, this indic…
1429 … (0x1<<19) // Equalization Phase 2 Successful - when set, this indic…
1431 … (0x1<<20) // Equalization Phase 3 Successful - when set, this indic…
1451 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1453 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1455 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1597 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1603 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1605 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1686 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1692 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1694 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1751 …ATAL_ERR_STATUS_K2 (0x1<<13) // Advisory Non-Fatal Error Status.
1802 …ERR_MASK_K2 (0x1<<13) // Advisory Non-Fatal Error Mask. N…
1858 … (0x1f<<0) // First Error Pointer - These bits correspon…
1972 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1974 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1976 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1982 …nded VC Count. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1990 …on Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1999 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
2021 …// Reject Snoop Transactions. Note: The access attributes of this field are as follows: - Dbi: R
2023 … (0x3f<<16) // Maximum Time Slots-1 supported. Note: The access attributes of this field ar…
2077 … 0x000160UL //Access:R DataWidth:0x20 // The read-back value of this re…
2096 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2098 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2100 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2124 … 0x000174UL //Access:RW DataWidth:0x20 // The read-back value of this re…
2141 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2143 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2145 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2176 … 0x000180UL //Access:R DataWidth:0x20 // The read-only value of this re…
2201 … Allocated PB. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2203 … 0x000184UL //Access:R DataWidth:0x20 // The read-only value of this re…
2204 … (0xffff<<0) // VSEC ID. This field is a vendor-defined ID number tha…
2206 … (0xf<<16) // VSEC Rev. This field is a vendor-defined version numbe…
2208 …uding the PCI Express Enhanced Capability header, the Vendor-Specific header, and the Vendor-Speci…
2228 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2230 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2232 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2234 …/ If bit 0 of the EXT_CAP_ENA for EP or bit 0 of RC_EXT_CAP_ENA for RC is reset to '0', reading th…
2328 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2330 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2332 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2357 …0) // Perform Equalization. Note: The access attributes of this field are as follows: - Dbi: R/W
2359 …n Request Interrupt Enable. Note: The access attributes of this field are as follows: - Dbi: R/W
2382 …tter Preset 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2384 …Preset Hint 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2386 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2388 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2390 …tter Preset 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2392 …Preset Hint 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2394 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2396 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2405 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2406 …itter Preset2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2408 … Preset Hint2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2410 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2412 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2414 …itter Preset3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2416 … Preset Hint3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2418 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2420 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2423 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2424 …itter Preset4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2426 … Preset Hint4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2428 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2430 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2432 …itter Preset5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2434 … Preset Hint5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2436 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2438 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2441 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2442 …itter Preset6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2444 … Preset Hint6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2446 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2448 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2450 …itter Preset7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2452 … Preset Hint7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2454 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2456 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2458 …-only value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP, By default,…
2477 …g with Max snoop latency scale field, this register specifies the maximum no-snoop latency that a …
2483 …ith Max No snoop latency scale field, this register specifies the maximum no-snoop latency that a …
2490 … 0x0001b8UL //Access:RW DataWidth:0x20 // SR-IOV Capability Header…
2491 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2493 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2495 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2497 … 0x0001b8UL //Access:R DataWidth:0x20 // The read-only value of this re…
2507 … 0x0001bcUL //Access:RW DataWidth:0x20 // SR-IOV Capability Regist…
2510 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2528 … 0x0001c0UL //Access:RW DataWidth:0x20 // SR-IOV Control and Statu…
2537 …access attributes of this field are as follows: - Dbi: R/W but read-value is not always same as w…
2539 … 0x0001c0UL //Access:R DataWidth:0x20 // The read-only value of this re…
2547 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2549 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2575 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2576 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: STATUS_CONTROL_…
2613 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register" det…
2615 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register". de…
2640 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2692 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2693 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2695 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2697 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2717 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2718 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2720 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2722 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2742 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2743 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2745 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2747 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2749 …-bit VF_BAR0 register programs the base address for the memory space mapped by the VFs belonging t…
2752 …ate that VF_BAR0 may be programmed to map this adapter to anywhere in the 64-bit address space. Bi…
2754 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR0 may be pre-fetched or cached by …
2758 …-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR…
2777 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2778 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2780 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2782 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2784 … 0x0001e8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR1 register …
2802 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2803 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2805 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2807 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2809 …-bit VF_BAR2 register programs the base address for the memory space mapped by the VFs belonging t…
2812 …ate that VF_BAR2 may be programmed to map this adapter to anywhere in the 64-bit address space(reg…
2814 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR2 may be pre-fetched or cached by …
2818 …-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR…
2837 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2838 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2840 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2842 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2844 … 0x0001f0UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR3 register …
2867 …-bit VF_BAR4 register programs the base address for the memory space mapped by the VFs belonging t…
2870 …ate that VF_BAR4 may be programmed to map this adapter to anywhere in the 64-bit address space(reg…
2872 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR4 may be pre-fetched or cached by …
2876 …-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR…
2896 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2898 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2900 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2902 … 0x0001f8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR5 register …
2923 …ode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2925 …ode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2927 …ter Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2929 …ocation Bit 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2931 …ocation Bit 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2933 …ST Table Size. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2953 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
2957 … 0x000200UL //Access:R DataWidth:0x20 // The read-only value of this re…
2982 … 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
2984 … 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
3049 … 0x000210UL //Access:R DataWidth:0x20 // The read-only value of this re…
3127 … 0x000220UL //Access:R DataWidth:0x20 // The read-only value of this re…
3139 …5 (0x1<<2) // VF 10-bit tag requester sup…
3179 … (0x1<<4) // ARI capable hierarchy. 0 = All PFs have non-ARI capable hierarchy…
3181 …5 (0x1<<5) // VF 10-bit Tag Requester Ena…
3197 … (0xffff<<16) // Total VFs. Read-only copy of PCIEEP_S…
3204 … 0x000230UL //Access:R DataWidth:0x20 // The read-only value of this re…
3212 …Reset values: _ PF0: 0x1. There are two first VF offset registers; one for each ARI ca…
3214 …Reset values: _ ARI: 0x1. _ non-ARI: 0x1. There are two VF stride registers; one…
3231 …ware reads this field to determine the STTable Size N, whihc is encoded as N-1. So a returned valu…
3245 …-only value of this register is controlled by setting bit 2 of the EXT2_CAP_ENA for EP, By default…
3255 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3274 … (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
3307 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3324 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3356 … (0x7ff<<16) // ST table size (limited by MSI-X table size).
3369 …d Capacity ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3371 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3373 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3375 … 0x000288UL //Access:RW DataWidth:0x20 // LTR Max Snoop and No-Snoop Latency Registe…
3380 …T_K2 (0x3ff<<16) // Max No-Snoop Latency Value.
3382 …LAT_SCALE_K2 (0x7<<26) // Max No-Snoop Latency Scale.
3384 … 0x00028cUL //Access:RW DataWidth:0x20 // Vendor-Specific Extended Cap…
3385 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3387 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3389 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3391 … 0x000290UL //Access:R DataWidth:0x20 // Vendor-Specific Header.
3398 …- Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register det…
3399 …ear' code. The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11:…
3401 …ays '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no…
3403 …alue of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT…
3405 …a returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - ..…
3407 …- 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the Group For e…
3409 …s the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTRO…
3410 …idth:0x20 // Time-based Analysis Control. Used for controlling the measurement of RX/TX data thr…
3411 … (0x1<<0) // Timer Start. - 0: Start/Restart - 1: Stop Th…
3413 …-based Duration Select. Selects the duration of time-based analysis. When "manual control" is sele…
3415 …-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_…
3417 …ataWidth:0x20 // Time-based Analysis Data. Contains the measurement results of RX/TX data throug…
3418 …- 0: CRC Error: EINJ0_CRC_REG - 1: Sequence Number Error: EINJ1_SEQNUM_REG - 2: DLLP Error: EINJ…
3433 …- LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link …
3434 …have been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE…
3436 …- 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b:…
3438 …- ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 409…
3439 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE …
3441 …nce number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - …
3443 …-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. …
3445 …- If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the trans…
3446 … being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABL…
3448 … inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block …
3450 …- If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeo…
3451 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE …
3453 …- Mask K symbol. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set)…
3455 … - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Po…
3456 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE …
3458 …-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Po…
3462 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is repr…
3464 … - For Duplicate TLP, the core initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These …
3465 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE …
3467 …Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as N…
3533 … (0x3ff<<16) // Max no-snoop latency value.
3535 … (0x7<<26) // Max no-snoop latency scale.
3546 … 0x000300UL //Access:R DataWidth:0x20 // The read-only value of this re…
3554 …PCIPM_SUP_E5 (0x1<<0) // PCI-PM L12 supported.
3556 …PCIPM_SUP_E5 (0x1<<1) // PCI-PM L11 supported.
3577 …1_2_PCIPM_EN_E5 (0x1<<0) // PCI-PM L12 enable.
3579 …1_1_PCIPM_EN_E5 (0x1<<1) // PCI-PM L11 enable.
3589 …s. 0x2 = 1024 ns. 0x3 = 32,768 ns. 0x4 = 1,048,575 ns. 0x5 = 33,554,432 ns. 0x6-7 = Reserved.
3681 …remote device when all of the following conditions are true. - Using 128b/130b encoding - Inject…
3682 …are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE …
3684 …ror Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EI…
3686 …e TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Pref…
3736 …ter data returned in the PCIEEP_RAS_EC_DATA[EV_CNTR_DATA]. 0x0-0x7 = Lane number. 0x8-0xF = Res…
3778 …-based duration select. Selects the duration of time-based analysis. 0x0 = Manual control. Ana…
3780 …EL_E5 (0xff<<24) // Time-based report select. …
3801 …uring LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. -…
3805 …-reset exit. The core selects the greater value between this register and the value defined by the…
3807 …m receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - …
3812 …rts transitioning to Recovery State. This request does not cause a speed change or re-equalization.
3824 … // Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the…
3825 …er for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 …
3840 …- 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When …
3848 …-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negoti…
3851 …- 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDL…
3853 …- 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 08h: L1 - 09h: L1_BLOCK_…
3855 … Re-send flag. When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host soft…
3879 … (0x3<<24) // DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 1…
3888 …-FC DLLP. 0x3 = New TLP's ECRC error injection. 0x4 = TLP's FCRC error injection (128b/130b). 0…
3890 …LP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL…
3891 …ort-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data …
3893 …IT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CRE…
3895 …iewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 d…
3897 …TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_D…
3899 …TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value …
3901 …YPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value …
3908 …-assigned sequence numbers. This value is represented by two's complement. 0x0FFF = +4095. 0x0…
3911 …- 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: T…
3923 …ng - Mask K symbol. 0x0 = Reserved. 0x1 = COM/PAD(TS1 Order Set). 0x2 = COM/PAD(TS2 Order Set)…
3928 …-FC type. Selects the credit type. 0x0 = Posted TLP header credit value control. 0x1 = Non-Pos…
3932 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. The value is rep…
3934 …ng the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ…
3935 …-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] view…
3937 …the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/…
3939 …al Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11:…
3951 … (0x3f<<0) // Force Local Transmitter Pre-cursor. Indicates th…
3955 … (0x3f<<12) // Force Local Transmitter Post-Cursor. Indicates th…
3961 …fficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CUR…
3969 … (0x3f<<0) // Force Remote Transmitter Pre-Cursor. Indicates th…
3973 … (0x3f<<12) // Force Remote Transmitter Post-Cursor. Indicates th…
3975 …ficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CU…
3979 …ed unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_…
3982 …nformation. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x…
3994 …_K2 (0x3f<<0) // EQ Local Pre-Cursor. Indicates Lo…
3998 …K2 (0x3f<<12) // EQ Local Post-Cursor. Indicates Lo…
4006 …_K2 (0x3f<<0) // EQ Remote Pre-Cursor. Indicates Re…
4010 …K2 (0x3f<<12) // EQ Remote Post-Cursor. Indicates Re…
4023 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4025 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4027 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4039 …for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. …
4055 …mpletion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. …
4068 … 0x000398UL //Access:RW DataWidth:0x20 // Corrected error (1-bit ECC) counter sele…
4071 …) // Enable correctable errors counters. - 1: counters increment when the core detects a correcta…
4073 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4078 … 0x00039cUL //Access:R DataWidth:0x20 // Corrected error (1-bit ECC) counter data…
4081 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4086 … 0x0003a0UL //Access:RW DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) c…
4089 … Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correct…
4091 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4100 …ors into. 0x0 = TLP header. 0x1 = TLP prefix 1st 4-DWORDs. 0x2 = TLP prefix 2nd 4-DWORDs. 0x3…
4102 … 0x0003a4UL //Access:R DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) c…
4105 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4109 …he following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection mod…
4112 … (0x3<<4) // Error injection type: - 0: none - 1: 1-bit - 2: 2-bit
4114 … (0xff<<8) // Error injection count. - 0: errors are inserted in every TLP until you clear ERR…
4119 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4123 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4128 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4132 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4136 …_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are for…
4146 …-reset exit. The core selects the greater value between this register and the value defined by the…
4148 …ing EIOS to, RXELECIDLE assertion at the PHY 0x0 = 40ns. 0x1 = 160ns. 0x2 = 320ns. 0x3 - 640ns.
4168 …cUL //Access:R DataWidth:0x20 // RAM Address where a corrected error (1-bit ECC) has been det…
4169 … (0x7ffffff<<0) // RAM Address where a corrected error (1-bit ECC) has been det…
4171 … (0xf<<28) // RAM index where a corrected error (1-bit ECC) has been det…
4173 … //Access:R DataWidth:0x20 // RAM Address where an uncorrected error (2-bit ECC) has been det…
4174 … (0x7ffffff<<0) // RAM Address where an uncorrected error (2-bit ECC) has been det…
4176 … (0xf<<28) // RAM index where an uncorrected error (2-bit ECC) has been det…
4179 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4181 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4183 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4186 … silicon debug status register of Layer1-PerLane. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. 0x7 …
4201 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4203 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4205 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4207 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4210 …-STP/SDP/IDL token was received and it was not in TLP/DLLP reception. 0x02 = When current token w…
4218 …ualization_done_8GT_data_rate. 0x7 = equalization_done_16GT_data_rate. 0x8-0xF = idle_to_rlock_t…
4223 …s Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT
4225 …s Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT
4228 … 0x17 = L0S_BLOCK_TLP. 0x18 = WAIT_LAST_PMDLLP. 0x19 = WAIT_DSTATE_UPDATE. 0x20-0x1F = Reserved.
4230 …S_L23RDY_WAIT4ALIVE. 0x0F = S_L23RDY_WAIT4IDLE. 0x10 = S_WAIT_LAST_PMDLLP. 0x10-0x1F = Reserved.
4232 …_Status bit. If host software does not clear PME_Status bit for 100ms (+50%/-5%), the DUT resends …
4239 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4241 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4243 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4257 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4259 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4261 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4264 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields determi…
4266 …ith the [CREDIT_SEL_VC], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields determi…
4268 …] viewport-select fields determines that data that is returned by the [CREDIT_DATA0] and [CREDIT_D…
4270 …CREDIT_SEL_VC], [CREDIT_SEL_CREDIT_TYPE], and [CREDIT_SEL_TLP_TYPE] viewport-select fields determi…
4272 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = …
4274 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = …
4277 … (0x1<<0) // PTM Requester Auto Update Enabled - When enabled PTM Req…
4279 … (0x1<<1) // PTM Requester Start Update - When set the PTM Req…
4281 …K2 (0x1<<2) // PTM Fast Timers - Debug mode for PTM T…
4283 … (0xff<<8) // PTM Requester Long Timer - Determines the perio…
4286 …ion request rules. 0x0E = Invalid TLP type. 0x0F = Completion rules. 0x10-0x7E = Reserved. 0x7…
4291 … (0x1<<0) // PTM Requester Context Valid - Indicate that the Ti…
4293 … (0x1<<1) // PTM Requester Manual Update Allowed - Indicates whether or…
4298 …-lane silicon debug EQ status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] view…
4300 …ct. Setting this field in conjunction with [EQ_LANE_SEL] determines the per-lane silicon debug EQ…
4330 … (0x3f<<0) // Force remote transmitter pre-cursor as selected by…
4381 …ster of the PCI configuration space. This value is sticky and only reset by HARD Reset. Default is…
4383 … of bar_1 as a 32-bit address. The value of this bit maps directly to bit 2 of bar_1. This value i…
4385 … (0x1<<5) // This bit will force the PCI bus to re-try all cycles to the…
4387 … (0x1<<6) // This bit will force the PCI bus to re-try all cycles to the…
4389 …ce PCI reset that a configuration cycle hass been done by the PCI block. This may be used by firmw…
4391 …en this value is non-zero, the Expansion ROM attention must be handled by an internal processor to…
4393 …16) // This bit when set is reflected in bit 3 of bar_1 and indicates that the BAR is pre-fetchable
4399 …reset only reset by HARD Reset such that it can be used to detect initial power up if a non-zero v…
4401 … (0xff<<8) // This value is reset only by REG_HARD_R…
4407 …uration space still control the output normally. This value is sticky and only reset by HARD Reset.
4409 …te of the PME_STATUS bit in configuration space. This value is sticky and only reset by HARD Reset.
4411 …te of the PME_ENABLE bit in configuration space. This value is sticky and only reset by HARD Reset.
4423 …er is 0. This is the power consumed in D0 state. This value is sticky and only reset by HARD Reset.
4425 …er is 1. This is the power consumed in D1 state. This value is sticky and only reset by HARD Reset.
4427 …er is 2. This is the power consumed in D2 state. This value is sticky and only reset by HARD Reset.
4429 …er is 3. This is the power consumed in D3 state. This value is sticky and only reset by HARD Reset.
4433 … is 4. This is the power dissipated in D0 state. This value is sticky and only reset by HARD Reset.
4435 … is 5. This is the power dissipated in D1 state. This value is sticky and only reset by HARD Reset.
4437 … is 6. This is the power dissipated in D2 state. This value is sticky and only reset by HARD Reset.
4439 … is 7. This is the power dissipated in D3 state. This value is sticky and only reset by HARD Reset.
4450 …ster of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits…
4452 …ster of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits…
4454 …ster of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits…
4456 …ster of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits…
4460 …ster of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits…
4462 …ster of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits…
4472 … (0xfff<<0) // PTM Requester TX Latency - Requester Transmit p…
4504 … (0xfff<<0) // PTM Requester RX Latency - Requester Receive pa…
4511 …). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved.
4516 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4518 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4520 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4525 …ot supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved.
4530 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4532 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4534 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4536 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4538 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4540 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4542 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4544 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4546 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4548 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4550 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4552 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4554 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4556 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4558 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4560 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4562 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4564 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4566 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4568 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4578 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4587 …) // BAR Size. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4599 …). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved.
4607 … (0x3<<4) // Error injection type. 0x0 = None. 0x1 = 1-bit. 0x2 = 2-bit. 0x3 = Re…
4609 … 0x0 = errors are injected in every TLP until [ERR_INJ_EN] is cleared. 0x1 - 0xFF = number of err…
4614 …ult value is the Broadcom vendor ID. This value is sticky and only reset by HARD Reset. The defaul…
4616 …ardware default value is the Broadcom vendor ID. This value is sticky and only reset by HARD Reset.
4619 …ot supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved.
4623 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4628 …stem_vendor_id value in the configuration space. This value is sticky and only reset by HARD Reset.
4630 …id value in the configuration space. This value is sticky and only reset by HARD Reset. The defaul…
4633 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4637 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4642 …-bit Class Code register identifies the generic function of the device. All of the legal values ar…
4652 …s the MSI capability and Bit3 is MSIX capability This value is sticky and only reset by HARD Reset.
4656 …register in the PCI Configuration address space. This value is sticky and only reset by HARD Reset.
4660 …lways be equal or less than what was advertised. This value is sticky and only reset by HARD Reset.
4662 …ation space. The default is 0, which is one MSI. This value is sticky and only reset by HARD Reset.
4672 …n the D1_SUPPORT bit in the configuration space. This value is sticky and only reset by HARD Reset.
4674 …n the D2_SUPPORT bit in the configuration space. This value is sticky and only reset by HARD Reset.
4676 …in the PME_IN_D0 bit in the configuration space. This value is sticky and only reset by HARD Reset.
4678 …in the PME_IN_D1 bit in the configuration space. This value is sticky and only reset by HARD Reset.
4680 …in the PME_IN_D2 bit in the configuration space. This value is sticky and only reset by HARD Reset.
4682 …he PME_IN_D3_HOT bit in the configuration space. This value is sticky and only reset by HARD Reset.
4686 … (0x1<<9) // This indicates function does not perform an internal reset when transitioning…
4703 …of the bist register in the configuration space. This value is sticky and only reset by HARD Reset.
4724 … (0x7fffff<<0) // Only bit 0 is currently defined - remote scaled flow c…
4771 … common logic in case of multi function devices. This value is sticky and only reset by HARD Reset.
4818 …orted resource sizes. PEM advertises the maximum allowable BAR size (512 GB - 0xF_FFFF) when the f…
4835 …ters located at 10h in configuration space is used to map the function's MSI-X table into memory s…
4837 … one of the functions Base address registers to point to the base of the MSI-X table. Value is con…
4847 …ters located at 10h in configuration space is used to map the function's MSI-X PBA into memory spa…
4849 … one of the functions Base address registers to point to the base of the MSI-X PBA Value is contro…
4859 …-zero values indicate some software-defined post-firmware loaded state information or failure code…
4916 …ster of the PCI configuration space. This value is sticky and only reset by HARD Reset. Default is…
4918 … of bar_3 as a 32-bit address. The value of this bit maps directly to bit 2 of bar_3. This value i…
4920 …<5) // This bit when set is reflected in bit 3 of bar_3 and indicates that the BAR is pre-fetchable
4925 … Timeout Ranges Supported. Controls value in same field in the config space 0xF- Ranges A,B,C and D
4949 …ster of the PCI configuration space. This value is sticky and only reset by HARD Reset. This regis…
4951 … of bar_5 as a 32-bit address. The value of this bit maps directly to bit 2 of bar_5. This value i…
4953 …it when set is reflected in bit 3 of bar_5 and indicates that the BAR is pre-fetchable. This regis…
4988 …e pwr_bdgt_data_sel register (0x154) value is 0. This value is sticky and only reset by HARD Reset.
4993 …e pwr_bdgt_data_sel register (0x154) value is 1. This value is sticky and only reset by HARD Reset.
4998 …e pwr_bdgt_data_sel register (0x154) value is 2. This value is sticky and only reset by HARD Reset.
5003 …e pwr_bdgt_data_sel register (0x154) value is 3. This value is sticky and only reset by HARD Reset.
5008 …e pwr_bdgt_data_sel register (0x154) value is 4. This value is sticky and only reset by HARD Reset.
5013 …e pwr_bdgt_data_sel register (0x154) value is 5. This value is sticky and only reset by HARD Reset.
5018 …e pwr_bdgt_data_sel register (0x154) value is 6. This value is sticky and only reset by HARD Reset.
5023 …e pwr_bdgt_data_sel register (0x154) value is 7. This value is sticky and only reset by HARD Reset.
5035 …e pwr_bdgt_data_sel register (0x154) value is 7. This value is sticky and only reset by HARD Reset.
5052 … (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
5080 …trol the size of the user BAR1 area. This value is sticky and only reset by HARD Reset. This regis…
5092 …trol the size of the user BAR1 area. This value is sticky and only reset by HARD Reset. This regis…
5116 … is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. Al…
5158 …ster. This field indicates device ID for all VFs associated with this PF. Reset value is based on …
5163 … VF BAR0 as a 64-bit address. The value of this bit maps directly to bit 2 of VF BAR0. This value …
5165 … when set is reflected in bit 3 of VF BAR0 and indicates that the BAR is pre-fetchable. This regis…
5171 … VF BAR2 as a 64-bit address. The value of this bit maps directly to bit 2 of VF BAR2. This value …
5173 … when set is reflected in bit 3 of VF BAR2 and indicates that the BAR is pre-fetchable. This regis…
5185 …. Bit 0 enables the MSIX capability. This value is sticky and only reset by HARD Reset. Value affe…
5192 …bility structure of PF configuration space is used to map the function's MSI-X table into memory s…
5194 … one of the functions Base address registers to point to the base of the MSI-X table . All the VF'…
5197 …capability structure in PF configuration space is used to map the VF's's MSI-X PBA into memory spa…
5199 …ress contained by one of the functions Base address registers to point to the base of the MSI-X PBA
5209 … VF BAR4 as a 64-bit address. The value of this bit maps directly to bit 2 of VF BAR4. This value …
5211 … when set is reflected in bit 3 of VF BAR4 and indicates that the BAR is pre-fetchable. This regis…
5235 … is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. Al…
5244 …it reaches this limit. This value is set correctly by the hardware out of reset or when the negoti…
5246 … replay timer expires. This value is set correctly by the hardware out of reset or when the negoti…
5249 …reset, the core updates the default according to the Negotiated Link Width, Max_Payload_Size, and …
5251 …reset, the core updates the default according to the Negotiated Link Width, Max_Payload_Size, and …
5267 … (0xff<<0) // Link Number. Not used for endpoint. Not used for M-PCIe. Note: This reg…
5271 …- Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the core to t…
5275 …many clock cycles for the associated completion of a CfgWr to D-state register to go low-power. Th…
5290 … 0x00070cUL //Access:RW DataWidth:0x20 // Ack Frequency and L0-L1 ASPM Control Regis…
5291 …- 0: Indicates that this Ack frequency control feature is turned off. The core schedules a low-pri…
5293 …-sets that a component can request is 255. The core does not support a value of zero; a value of z…
5295 …-sets that a component can request is 255. This field is only writable (sticky) when all of the fo…
5297 … - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us…
5299 … Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 …
5301 … (0x1<<30) // ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has …
5308 …->1 transition, the PCIe core sends TS ordered sets with the loopback bit set to cause the link pa…
5310 … (0x1<<3) // Reset assert. Triggers a recovery and forces the LTSSM to…
5335 … the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register fie…
5339 …-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during C…
5341 … (0x1<<3) // Reset Assert. Triggers a recovery and forces the LTSSM to…
5347 …-outs and to link up faster. The scaling factor is selected in FAST_LINK_SCALING_FACTOR(default : …
5351 …". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supp…
5370 … (0xf<<27) // Set the implementation-specific number of la…
5372 … (0x1<<31) // Disable lane-to-lane deskew. Disables the internal lane-t…
5381 … (0x1<<31) // Disable Lane-to-Lane Deskew. Causes the core to disable the intern…
5384 … (0xff<<0) // Max number of functions supported. Used for SR-IOV.
5397 …-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in inc…
5403 …- 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Fa…
5451 …- 0: For RADM RC filter to not allow CFG transaction being received - 1: For RADM RC filter to al…
5492 … 0x000734UL //Access:R DataWidth:0x20 // Transmit Non-Posted FC Credit Stat…
5493 … (0xfff<<0) // Transmit Non-Posted Data FC Credits. The non-poste…
5495 … (0xff<<12) // Transmit Non-Posted Header FC Credits. The non-post…
5547 …xff<<0) // WRR Weight for VC0. Note: The access attributes of this field are as follows: - Dbi: R
5549 …xff<<8) // WRR Weight for VC1. Note: The access attributes of this field are as follows: - Dbi: R
5551 …ff<<16) // WRR Weight for VC2. Note: The access attributes of this field are as follows: - Dbi: R
5553 …ff<<24) // WRR Weight for VC3. Note: The access attributes of this field are as follows: - Dbi: R
5565 …xff<<0) // WRR Weight for VC4. Note: The access attributes of this field are as follows: - Dbi: R
5567 …xff<<8) // WRR Weight for VC5. Note: The access attributes of this field are as follows: - Dbi: R
5569 …ff<<16) // WRR Weight for VC6. Note: The access attributes of this field are as follows: - Dbi: R
5571 …ff<<24) // WRR Weight for VC7. Note: The access attributes of this field are as follows: - Dbi: R
5580 …-buffer configuration, writable through PEM()_CFG_WR. However, the application must not change thi…
5588 …he TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration,…
5590 …ines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration,…
5592 … 0x000748UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Posted Rec…
5593 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5595 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5603 …ly in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ord…
5605 …eues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs …
5614 …-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at a time: _ Bit 2…
5616 … (0x3<<24) // VC0 scale non-posted header credits.
5618 … (0x3<<26) // VC0 scale non-posted data credits.
5622 … 0x00074cUL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Non-Posted Receive…
5623 …-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segm…
5625 …-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the …
5640 …-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at a time: _ Bit 2…
5648 … 0x000750UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Completion…
5649 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5651 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5682 … (0x1<<12) // This bit if set will force DUT to not reset its RID after an F…
5700 … (0x1<<21) // When set, it enables WAKE generation in any L-state, when PME_EN bi…
5704 … (0x1<<23) // When set, TL does not get reset on DLPDOWN and Pci…
5706 … (0x1<<24) // When set, it prevents PM from re-entering L1 when programmed to non-D0 p…
5714 … mode, when set, it enables pcie_scnd_rst_b to be asserted when Secondary reset bit in BridgeContr…
5759 … and not wait for LTR message to be sent first even though device state may have changed to non-D0.
5845 …0x1 = 1 lane. 0x2 = 2 lanes. 0x3 = 3 lanes. _ ... 0x10 = 16 lanes. 0x11-0x1F = Reserved. Wh…
5847 …e0 to physical lane 7. 0x4 = Connect logical Lane0 to physical lane 15. 0x5 - 0x7 = Reserved.
5857 … (0x1<<20) // Set the deemphasis level for upstream ports. 0 = -6 dB. 1 = -3.5 dB.
5862 …his field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as…
5864 …- 0x01: 1 lane - 0x02: 2 lanes - 0x03: 3 lanes - .. When you have unused lanes in your system, …
5866 …- 3'b000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8…
5868 …his field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as…
5870 …- Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deas…
5872 …ld. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe. Note: The …
5874 …his field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as…
5876 …-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at…
5878 …core by just detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Id…
5885 …t. When this bit is set, PH credits are not released by IP if FIFO at the DL-TL boundary reaches a…
5887 … (0x1<<3) // Indicates no non-posted credit is avai…
5897 … (0x1<<16) // This bit when set prevents DUT from entering L1 due to being in non-d0 state.
5899 … (0x7fff<<17) // Programmable delay to prevent link from re-entering L1, when lin…
5904 … (0xffff<<0) // For ECO/CTRL bits are reset o hard_reset
5906 … (0xffff<<16) // For ECO/Control bits are reset on perst_b
6359 …will keep the Serdes MDIO regs in reset till PERST_N is released. Default behavior is to release S…
6361 … when cleared will keep the micro in reset till PERST_N is released. Default behavior is to releas…
6363 … (0x1<<2) // This bit when set will reset the Serdes registe…
6365 … will allow bit 2 value to propogate to Serdes. This bit acts as the mux sel for a soft MDIO reset.
6367 … (0x1<<4) // This bit when set will reset the micro, provide…
6369 … set will allow bit 4 value to propogate to uc reset. This bit acts as the mux sel for a soft micr…
6641 …gating feature when there is no receive traffic, receive queues and pre/post-queue pipelines are e…
6707 … (0x1<<0) // Gen3 receiver impedance ZRX-DC not compliant.
6713 … (0x1<<10) // Equalization EIEOS count reset disable. Disable requesting reset o…
6715 … (0x1<<11) // Equalization redo disable. Disable requesting reset of EIEOS count dur…
6735 …-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is us…
6736 …-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defin…
6740 …Gen4 data rate. Note: The access attributes of this field are as follows: - Dbi: see description…
6742 … (0x1<<10) // Equalization EIEOS Count Reset Disable. Disable requesting reset o…
6746 …-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the…
6748 …- 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. - 1: mac_phy_rxeq…
6845 … with a data payload of 0xFFFFFFFF. When the MSB of a PF's HIDE_PFn is non-zero, the PF is consi…
6911 … (0xf<<0) // Feedback mode. 0 = Direction of change. 1 = Figure of merit. 2-15 = Reserved.
6925 … (0x1<<26) // Request core to send back-to-back EIEOS in Recove…
6927 …or Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP). M-PCIe doesn't have Con…
6928 … (0xf<<0) // Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserv…
6930 …- 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found then: …
6932 …Eval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settin…
6934 …- 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: P…
6936 …ter, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include…
6940 … core to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping …
6947 … (0xf<<10) // Convergence window aperture for C-1. Precursor coeffici…
6956 …TA_K2 (0xf<<10) // Convergence Window Aperture for C-1. Pre-cursor coefficient…
6958 …K2 (0xf<<14) // Convergence Window Aperture for C+1. Post-cursor coefficients m…
6961 …-Posted passing posted ordering rule control. Determines if a NP can pass halted P queue. 0x0 = …
6963 …lted P queue. 0x0 = CPL can not pass P (recommended). 0x1 = CPL can pass P. 0x2-0xFF = Reserved.
6966 …<0) // Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue…
6968 … Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1…
6971 … (0xffff<<0) // Loopback rxvalid (lane enable - 1 bit per lane).
6984 … (0x1<<31) // PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This reg…
6989 …error reporting). A completion with UR status will be generated for non-posted requests. 0x1…
6991 …e suppresses error logging, error message generation, and CPL generation (for non-posted requests).
6999 … 0x0008bcUL //Access:RW DataWidth:0x20 // DBI Read-Only Write Enable Reg…
7000 …he local application through the DBI. For more details, see "Writing to Read-Only Registers." Not…
7005 …e or autonomous width downsizing in the configuration state. The core self-clears this field whe…
7009 … 0x0008c0UL //Access:RW DataWidth:0x20 // UpConfigure Multi-lane Control Register…
7010 …- 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration s…
7012 …- If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CO…
7014 …n Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This reg…
7017 …RxStandby/RxStandbyStatus handshake. 0x0 = Rx EIOS and subsequent T TX-IDLE-MIN. 0x1 = Rate …
7026 …- [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfig…
7028 …- 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Core wai…
7033 …This is a one-shot bit. Writing a one triggers the deletion of the target completion LUT entry tha…
7035 …lication completions (on XALI0/1/2) corresponding to previously received non-posted requests from …
7038 …mpletion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register fie…
7096 … (0xff<<24) // Non-Posted Data credits a…
7105 …BB (0xf<<28) // Non-Posted Data credits a…
7114 … (0xff<<24) // Non-Posted Data credits c…
7123 …BB (0xf<<28) // Non-Posted Data credits c…
7134 … (0x1<<16) // Available Non-posted credit for tar…
7137 …B (0xff<<0) // Non-Posted header credits…
7139 …B (0xff<<8) // Non-Posted data credits a…
7146 … (0xf<<0) // Target Non-Posted request State …
7157 … 0x0009a0UL //Access:R DataWidth:0x20 // Different Reset Related Debug Sign…
7182 …non-posted data credits since the last request for immediate update that are needed to force an im…
7184 … (0xff<<12) // The number of accumulated non-posted header credits…
7186 …-posted credits are flagged for immediate update. When clear, the credits may or not be updated un…
7188 …the forced update if there are outstanding non-posted credits to update. The resolution on the tim…
7190 …-posted credit updates are forwarded to the DLL as immediate updates after a given number of micro…
7199 … update if there are outstanding posted credits to update. The resolution on the timer is +/- 1 us.
7201 …w) elapses since the last update. This is typically used with non-immediate (threshold-based) upda…
7228 … field when set will prevent hardware from generating attention when PTM req- response handshake h…
7232 … (0x1<<30) // This field when set inidcates that the PTM req-response handshake in…
7234 … (0x1<<31) // This field when set inidcates that the PTM req-response handshake co…
7244 …reset to '0', the counting stops and software can read the results. This bit is automatically clea…
7248 …r the reg_ttx_tlp_stat_en bit to stop the operation. When it is set to a non-zero value, hardware …
7277 …reset to '0', the counting stops and software can read the results. This bit is automatically clea…
7281 …r the reg_trx_tlp_stat_en bit to stop the operation. When it is set to a non-zero value, hardware …
7323 …<<0) // Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7325 …<10) // Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7327 …/ Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7329 …) // No Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7331 …) // No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7333 …o Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7336 … This value is used to provide a 1 us reference for counting time during low-power states with aux…
7339 …-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are…
7389 …RETRIG_CNT_BB (0xff<<0) // When non-zero, indicates the m…
7403 …buffer is filled, the trig_addr field is used to determine the amount of pre-trigger data collected
7424 …- mask bits [319:0] for 0to1 trigger0 Register 10 :: IND_PCIE_DBG_TRIG0_1TO0_MASK - mask bits [319…
7455 …- no FIFO selected to read by user if 001 - PL/DL FIFO is selected to read by user if 010 - TLDA…
7459 … (0x7<<12) // 000 - generic lane is selected 001 - predefined lane 1 010 - predefine…
7490 …nterface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
7496 … (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read fr…
7498 … (0x7f<<15) // The number of pre-trigger samples to ke…
7523 …-- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 risi…
7525 … 0x000c50UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the FIFO
7526 … 0x000c54UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the FIFO
7527 … 0x000c58UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the FIFO
7528 … 0x000c5cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the FIFO
7540 …nterface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
7546 … (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read fr…
7548 … (0x7f<<15) // The number of pre-trigger samples to ke…
7573 …-- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 risi…
7575 …000c70UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the second …
7576 …x000c74UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the second …
7577 …x000c78UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the second …
7578 …0x000c7cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the second …
7612 …ET_BB (0x1<<28) // PHY: Disable Hot Reset.
7625 …// When this bit is set, the software value will be used for UpdateFC Latency of Non-Posted credit.
7627 … (0x1<<10) // DL: When this bit is set to '1', Replay Timer will not be reset if a NAK is receiv…
7633 … (0x1<<14) // This initiates Link re-training by directing…
7664 …1<<17) // DL: Enable Non-Posted Latency Timer. If this timer reaches MAX_ACK_LAT_TIMER value, DL w…
7678 … (0xfff<<0) // DL: Non-Posted Data for INITFC
7700 … (0xffff<<16) // Reserved - always write 0
7703 …s selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calculated value is s…
7705 …he replay timeout in symbol time. This delay is only applied to the hardware-calculated replay tim…
7707 …_BB (0x7ff<<21) // Reserved - always write 0
7712 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7717 …s selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calculated value is s…
7719 …he replay timeout in symbol time. This delay is only applied to the hardware-calculated replay tim…
7734 …t from sending more Posted FC updates , potentially stall DMA requests, until the flag de-asserted.
7737 …s selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calculated value is s…
7739 …he replay timeout in symbol time. This delay is only applied to the hardware-calculated replay tim…
7744 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7751 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7781 … (0x1<<6) // Indicate un-decoded condition in de-framing l…
7791 … (0x1<<11) // Set if DL detects impossible condition to de-allocate entries in R…
7801 … (0x1<<16) // Detect DLLP with mismatched CRC-16 on receiving side.
7844 …conditions occurs: - TLP ends in one entry. - The number of valid entries in T2D FIFO is greater t…
7881 …8-bit header information that is sent to TL logic to build a TLP. The header information is passed…
7897 …rates packets to TL logic. After all packets are transferred, this bit is reset to '0' by hardware.
7911 … HW transmits number of TLPs equal to ATE_TLP_CNT (bits[7:0] of ate_tlp_cfg - offset 0x111c). trx_…
7915 …] of ate_tlp_cfg - offset 0x111c). This register value needs to be ignored until user writes '1' t…
7967 … (0x1<<0) // Request a width change (ie -make the link wider, …
7969 … (0x1<<1) // Request a speed change (ie -make the link fast or…
7975 … (0x1<<6) // For multi-lane links on a 2.0 c…
8005 …ate (this propagates to the PCIe Serdes via the TxDeemph signal. 0 == -6 dB, 1 == -3.5 dB (For Gen…
8015 … (0x1<<27) // Disable use of electrical idle in Recovery.Speed - only use inferred el…
8019 … (0x1<<29) // Disable the ability to compensate for lane reversal in multi-lane links.
8026 … (0x1<<0) // Force the PIPE interface to be 16-bit, even in Gen 1 So…
8030 … (0x1<<2) // Enable the PIPE-style powerdown of unused lanes in a multi-…
8032 … (0x1<<3) // Enable the auxilliary powerdown of unused lanes in a multi-lane link.
8034 … (0x1<<4) // Initiate PL changes required for a far-end loopback
8036 …e configuration that cycles through the rates, deemphasis, and presets is reset back to the first …
8068 … (0x1<<29) // Clear the LTSSM histogram. Not self-clearing
8070 … (0x1<<30) // Clear the Gen2 debug histogram. Not self-clearing
8072 … (0x1<<31) // Clear the recovery histogram. Not self-clearing
8081 …erved - only write 0. Spare flops for the PL - train_ctl_in[1:0]. [29] (PL_FIX_19) Enable Phase 3 …
8083 …es elastic buffers will be prevented from adjusting - generating dynamic clock compensation events…
8085 … (0x1<<31) // Reserved - only write 0. Spare flop for the PL - t…
8092 … (0x1<<14) // Enable the "pins" gloopback - assumes an external …
8143 …nimum time to wait in Detect.Quiet (in 32 ns increments) if the state is entered at non-Gen1 speeds
8145 … (0x1<<14) // Allow lanes to be put into P2 state during reset to save power.
8149 … (0x1<<16) // Enable exit from Compliance on 1.1-compliant systems on …
8162 … (0xf<<5) // High 4 bits of the 10 bit-counter of 25 MHz clk…
8168 …erdes device type to minimize the PLL lock time (when set, don't reuse the old value - start over).
8170 … (0x3<<22) // Selects the low-frequency clock used …
8172 … (0x3f<<24) // Low 6 bits of the 10 bit-counter of 25 MHz clk…
8174 … (0x1<<30) // Reserved - only write 0
8181 …B (0x3<<6) // Reserved - only write 0
8183 … at 25 MHz to delay between assertion of reset to the Serdes before deassertion of the Serdes clk …
8185 … (0x3<<14) // Reserved - only write 0
8189 … (0x1<<17) // Use any PhyStatus to indicate the P0->P2 transition. De…
8193 …reset the Serdes clk mux during perstb and keep it asserted while perstb is asserted. Default is t…
8195 … (0xfff<<20) // Reserved - only write 0
8198 … (0xf<<0) // b0000: select pseudo-random value between …
8212 … (0x1fff<<18) // Reserved - always write 0
8233 …1_BB (0xf<<8) // Reserved - only write 0
8254 …_1_BB (0xf<<8) // Reserved - only write 0
8269 … (0x1<<8) // *** Do not modify!! Enable 16-bit data for all rate…
8287 … (0x3<<17) // Reserved - only write 0
8312 … (0x1<<20) // Enable a bad/misplaced End-of-Data-Stream token as a…
8343 … (0x1<<5) // Software sets if it can disable data traffic during re-equalization.
8383 …B (0x1<<28) // Reserved - only write 0
8406 … (0x1<<11) // Enable Gen3 redo deskew on framing/post-deskew alignment issu…
8420 …CK_ALIGN_RCFG_RESET_BB (0x1<<18) // Reset needed flops on bl…
8428 … (0x1<<22) // (PL_FIX_05) Enable preset-coefficient lookup fo…
8447 …C_BB (0x1<<6) // SED read address auto-increment
8468 …ET_LUT_ENTRY_5_TO_0_BB (0x3f<<0) // Pre-cursor for the coeffi…
8472 …_LUT_ENTRY_17_TO_12_BB (0x3f<<12) // Post-cursor for the coeffi…
8480 …y the EP to the Link partner-RC Transmitter in Phase2 EQ programmable preset value advertized by t…
8523 …eemphasis register control programming of coefficients for preset-0(-6dB) and preset-1(-3.5dB) in …
8525 …reset 0 and 1 0: points to the preset 0 coefficients(-6dB) 1: points to the preset 1 coefficients(…
8529 …0) // Gen2 deemphasis register select control bit to change from Preset-1(-3.5dB) to preset-0(-6dB)
8531 …/ Select control bit for the read status of the gen1/2 and gen2 lut entry 18-bit value poining to …
8576 … (0x1<<31) // RX reset EIEOS control bit for TS1(SYM6-Bit…
8581 … (0x3f<<1) // Registered programmed 6-bit FULL SWING value …
8585 … (0x3f<<8) // Registered programmed 6-bit LOW FREQUENCY val…
8611 …<<26) // [DEBUG_BIT]: RC mode : Forces Gen3 equalization for every Speed change over from Gen1-Gen3
8613 … (0x1f<<27) // [DEBUG_BITS]: Equalization static debug 5-bit address control f…
8653 …clear the lpbk_master_ena bit to stop the operation. When it is set to a non-zero value, hardware …
8668 …CURSOR_BB (0x3f<<8) // Loopback Master TS1 Pre-Cursor Coefficient. T…
8672 …URSOR_BB (0x3f<<20) // Loopback Master TS1 Post-cursor Coefficient. T…
8674 … (0x1<<26) // Loopback Master TS1 Selectable De-emphasis. This value …
8679 … used when loopback is in Gen2 rate. Notes that for Gen1 the TX deemphasis is always set to -3.5db.
8684 …are starts controlling LTSSM, it continues to do so until sw_ltssm_ena is reset to '0'. This featu…
8686 …ware is in control, the new state will be applied to LTSSM. This bit is self-cleared, so reading a…
8692 …-level State. This field specifies the state of the sub-level state machine that software wants LT…
8696 … (0x1ff<<20) // Software LTSSM Top-level State. This field specifies the state of th…
8703 …reset to '0', the counting stops and software can read the results. This bit can be automatically …
8707 …clear the pcie_statis_ena bit to stop the operation. When it is set to a non-zero value, hardware …
8737 …llection. When this bit is reset to '0', information is frozen so S/W can read the results. All st…
8775 … (0x7f<<8) // For lane 13 in a multi-lane system: The numb…
8777 … (0x1<<15) // For lane 13 in a multi-lane system: Set by t…
8783 … (0x7f<<24) // For lane 15 in a multi-lane system: The numb…
8785 … (0x1<<31) // For lane 15 in a multi-lane system: Set by t…
8792 … (0x7f<<8) // For lane 9 in a multi-lane system: The numb…
8794 … (0x1<<15) // For lane 9 in a multi-lane system: Set by t…
8800 … (0x7f<<24) // For lane 11 in a multi-lane system: The numb…
8802 … (0x1<<31) // For lane 11 in a multi-lane system: Set by t…
8809 … (0x7f<<8) // For lane 5 in a multi-lane system: The numb…
8811 … (0x1<<15) // For lane 5 in a multi-lane system: Set by t…
8817 … (0x7f<<24) // For lane 7 in a multi-lane system: The numb…
8819 … (0x1<<31) // For lane 7 in a multi-lane system: Set by t…
8826 … (0x7f<<8) // For lane 1 in a multi-lane system: The numb…
8828 … (0x1<<15) // For lane 1 in a multi-lane system: Set by t…
8834 … (0x7f<<24) // For lane 3 in a multi-lane system: The numb…
8836 … (0x1<<31) // For lane 3 in a multi-lane system: Set by t…
8843 … (0x7f<<8) // For lane 13 in a multi-lane system: The numb…
8845 … (0x1<<15) // For lane 13 in a multi-lane system: Set by t…
8851 … (0x7f<<24) // For lane 15 in a multi-lane system: The numb…
8853 … (0x1<<31) // For lane 15 in a multi-lane system: Set by t…
8860 … (0x7f<<8) // For lane 9 in a multi-lane system: The numb…
8862 … (0x1<<15) // For lane 9 in a multi-lane system: Set by t…
8868 … (0x7f<<24) // For lane 11 in a multi-lane system: The numb…
8870 … (0x1<<31) // For lane 11 in a multi-lane system: Set by t…
8877 … (0x7f<<8) // For lane 5 in a multi-lane system: The numb…
8879 … (0x1<<15) // For lane 5 in a multi-lane system: Set by t…
8885 … (0x7f<<24) // For lane 7 in a multi-lane system: The numb…
8887 … (0x1<<31) // For lane 7 in a multi-lane system: Set by t…
8894 … (0x7f<<8) // For lane 1 in a multi-lane system: The numb…
8896 … (0x1<<15) // For lane 1 in a multi-lane system: Set by t…
8902 … (0x7f<<24) // For lane 3 in a multi-lane system: The numb…
8904 … (0x1<<31) // For lane 3 in a multi-lane system: Set by t…
8939 … (0xff<<0) // Gen2 Debug History - current. Changes are…
8957 … (0xff<<0) // Recovery History - current. Changes are…
9015 …) // The current state of the ATE loopback SM tracker: b00011 : IDLE state - not active b00101 : …
9066 … 0x001d38UL //Access:R DataWidth:0x20 // PHY Debug - Polling Compliance s…
9067 … 0x001d3cUL //Access:R DataWidth:0x20 // PHY Debug - Equalization signals
9194 …it conditions to settle b1110 : Unknown state (failure) b1111 : Fundamental reset (perstb) occurred
9248 …0x1<<0) // Instantaneous value of the top-level user_allow_gen3 signal (sync'd to the cfg_clk doma…
9253 … (0xffff<<0) // Vendor ID. For SR-IOV VFs always 0xFFFF.
9255 … (0xffff<<16) // Device ID. For SR-IOV VFs always 0xFFFF.
9258 …ENDOR_ID_K2 (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufact…
9263 …E_E5 (0x1<<0) // VF read-only zero.
9265 …E_E5 (0x1<<1) // VF read-only zero.
9267 …)_PF()_DBG_INFO[P()_BMD_E bit. Transactions are dropped in the Client. Non-posted transactions r…
9281 … (0x1<<9) // Fast back-to-back transaction ena…
9283 …S_E5 (0x1<<10) // VF read-only zero.
9289 … (0x1<<19) // INTx status. Not applicable for SR-IOV. Hardwired to 0.
9295 … (0x1<<23) // Fast back-to-back capable. Not ap…
9312 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9314 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9352 …_ERR_K2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
9359 … (0xff<<8) // Read-only copy of the asso…
9361 … (0xff<<16) // Read-only copy of the asso…
9363 … (0xff<<24) // Read-only copy of the asso…
9375 … (0xff<<0) // Read-only copy of the asso…
9381 … (0x1<<23) // Read-only copy of the asso…
9400 …E_K2 (0x3<<1) // BAR0 32-bit or 64-bit.
9410 …E_K2 (0x3<<1) // BAR1 32-bit or 64-bit.
9420 …E_K2 (0x3<<1) // BAR2 32-bit or 64-bit.
9430 …E_K2 (0x3<<1) // BAR3 32-bit or 64-bit.
9440 …E_K2 (0x3<<1) // BAR4 32-bit or 64-bit.
9450 …E_K2 (0x3<<1) // BAR5 32-bit or 64-bit.
9459 … (0xffff<<0) // Read-only copy of the asso…
9461 … (0xffff<<16) // Read-only copy of the asso…
9464 …tem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9466 …tem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9469 … (0x1<<0) // Read-only copy of the asso…
9471 … (0x1fff<<19) // Read-only copy of the asso…
9480 … (0xff<<0) // VF's read-only zeros.
9482 … (0xff<<8) // VF's read-only zeros.
9484 … (0xff<<16) // VF's read-only zeros.
9486 … (0xff<<24) // VF's read-only zeros.
9496 … (0xff<<8) // Next capability pointer. Points to the MSI-X capabilities by def…
9498 …_E5 (0xf<<16) // Read-only copy of the asso…
9500 … (0xf<<20) // Read-only copy of the asso…
9502 … (0x1<<24) // Read-only copy of the asso…
9504 … (0x1f<<25) // Read-only copy of the asso…
9515 …emented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9522 … (0x7<<0) // Read-only copy of the asso…
9524 … (0x3<<3) // Read-only copy of the asso…
9526 … (0x1<<5) // Read-only copy of the asso…
9528 … (0x7<<6) // Read-only copy of the asso…
9530 … (0x7<<9) // Read-only copy of the asso…
9532 … (0x1<<15) // Read-only copy of the asso…
9538 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV c…
9545 …eld Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9551 …_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2 (0x1<<15) // Role-based Error Reporting…
9557 …_CAP_K2 (0x1<<28) // Function Level Reset Capability (endpoi…
9582 … (0x1<<15) // Initiate function level reset when written to on…
9584 …e receive any of the errors in PCIEEPVF()_COR_ERR_STAT, for example a replay-timer timeout. Also,…
9590 …ests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message shoul…
9592 …D_E5 (0x1<<20) // VF's read-only zeros.
9599 …_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting…
9609 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9611 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9615 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
9619 …IATE_FLR_K2 (0x1<<15) // Initiate Function Level Reset (for endpoints).
9623 …STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
9634 … (0xf<<0) // Read-only copy of the asso…
9636 … (0x3f<<4) // Read-only copy of the asso…
9638 …5 (0x3<<10) // Read-only copy of the asso…
9640 … (0x7<<12) // Read-only copy of the asso…
9642 … (0x7<<15) // Read-only copy of the asso…
9644 … (0x1<<18) // Read-only copy of the asso…
9646 … (0x1<<19) // Read-only copy of the asso…
9648 …5 (0x1<<20) // Read-only copy of the asso…
9650 … (0x1<<21) // Read-only copy of the asso…
9652 … (0x1<<22) // Read-only copy of the asso…
9654 … (0xff<<24) // Read-only copy of the asso…
9657 … (0xf<<0) // Maximum Link Speed. In M-PCIe mode, the reset and dynami…
9659 … (0x3f<<4) // Maximum Link Width. In M-PCIe mode, the reset and dynami…
9663 … following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_CO…
9665 … following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_CO…
9667 …er Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9675 … ASPM Optionality Compliance. Note: The access attributes of this field are as follows: - Dbi: R
9721 …_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_EN…
9723 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
9729 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9733 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9735 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9743 …figuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
9745 …Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9749 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9751 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9762 …2S_E5 (0x1<<7) // 32-bit AtomicOp supporte…
9764 …4S_E5 (0x1<<8) // 64-bit AtomicOp supporte…
9766 …8S_E5 (0x1<<9) // 128-bit AtomicOp supporte…
9768 … (0x1<<10) // No RO-enabled PR-PR passing. (Thi…
9776 …_CPL_SUPP_E5 (0x1<<16) // 10-bit tag completer sup…
9778 …_REQ_SUPP_E5 (0x1<<17) // 10-bit tag requestor sup…
9784 …5 (0x1<<21) // End-end TLP prefix suppor…
9786 … (0x3<<22) // Read-only copy of the asso…
9803 …O_EN_PR2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
9828 …_REQ_EN_E5 (0x1<<12) // 10-bit tag requestor ena…
9832 … (0x1<<15) // Unsupported end-end TLP prefix blocki…
9854 … (0x7f<<1) // Read-only copy of the asso…
9867 …DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9870 …TLS_E5 (0xf<<0) // VF's read-only zeros.
9872 …EC_E5 (0x1<<4) // VF's read-only zeros.
9874 …HASD_E5 (0x1<<5) // VF's read-only zeros.
9876 …SDE_E5 (0x1<<6) // VF's read-only zeros.
9878 …TM_E5 (0x7<<7) // VF's read-only zeros.
9880 …MC_E5 (0x1<<10) // VF's read-only zeros.
9882 …SOS_E5 (0x1<<11) // VF's read-only zeros.
9884 …DE_E5 (0xf<<12) // VF's read-only zeros.
9886 … (0x1<<16) // Read-only copy of the asso…
9909 …ET_LINK_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the conten…
9913 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9915 …SEL_DEEMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
9919 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9921 … transmission. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9923 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
9925 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
9942 …NTRL_MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
9946 … (0x7ff<<16) // MSI-X table size encoded as (table size - 1)…
9948 …ctors associated with the function are masked, regardless of their respective per-vector mask bits.
9950 …X_CAP_CNTRL_MSIXEN_E5 (0x1<<31) // MSI-X enable.
9952 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
9953 …NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
9955 …TRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2 (0xff<<8) // MSI-X Next Capability Poi…
9957 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
9959 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
9961 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
9964 …BIR_E5 (0x7<<0) // Read-only copy of the asso…
9966 … (0x1fffffff<<3) // Read-only copy of the asso…
9968 … 0x0000b4UL //Access:R DataWidth:0x20 // MSI-X Table Offset and BI…
9969 …_PCI_MSIX_BIR_K2 (0x7<<0) // MSI-X Table Bar Indicator…
9971 …_PCI_MSIX_TABLE_OFFSET_K2 (0x1fffffff<<3) // MSI-X Table Offset.
9974 …R_E5 (0x7<<0) // Read-only copy of the asso…
9976 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
9978 … 0x0000b8UL //Access:R DataWidth:0x20 // MSI-X PBA Offset and BIR …
9979 …OFFSET_REG_PCI_MSIX_PBA_K2 (0x7<<0) // MSI-X PBA BIR.
9981 …_PCI_MSIX_PBA_OFFSET_K2 (0x1fffffff<<3) // MSI-X PBA Offset.
9991 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9993 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9995 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10031 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10033 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10035 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10073 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
10083 … 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
10085 … 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
10132 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10134 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10138 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10140 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10154 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10156 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10160 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10162 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10170 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if RO…
10172 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if RO…
10174 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10175 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10177 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10180 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10182 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10185 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10187 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10190 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10192 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10195 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10197 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10200 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10202 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10205 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10207 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10210 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10212 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10227 … 0x000050UL //Access:W DataWidth:0x1 // Reset to error interrupt.
10228 … 0x000054UL //Access:W DataWidth:0x1 // Reset to parity interrup…
10290 …-only access of the GPRE registers. Register can be accessed only when storm is stalled. Address b…
10292 … 0x000480UL //Access:R DataWidth:0x20 // 15-0 STORM0 GPRE0 bits 15:0. 31-16 STOR…
10293 …- misc_local_mux_other_stall, 20 - ram_mux_bkpt_stall, 19 - mux_lock_stall, 18 - pram_mux_pipe_st…
10298 …ether or not the Storm is currently stalled. bit0- STORM A. bit1- STORM B. bit2- Pram Breakpoint. …
10299 …r with any value causes all the internal and external stall sources to be reset, resulting in the …
10303 …R DataWidth:0xf // This register delivers the PRAM address for the low-word instruction that…
10304 … DataWidth:0xf // This register delivers the PRAM address for the high-word instruction that…
10307 …en as a single bit , a value of 2 means that the PortID will be taken as a 2-bit field. A value of…
10308 …fines the offset (in bits) from the lsb of the CID in which to assign to bit-0 of the port ID. I.e…
10309 …dth:0x1 // Defines the Storm register file set that is currently active. 0 - STORM A 1 - STORM B
10310 …- DRA WR STM Core_A, 3:5 - DRA WR STM Core_B, 6:8 - DRA RD STM Core_A, 9:11 - DRA RD STM Core_B, …
10313 …- when set, invert bit on complementary index 4:0. bit 5 - when set, invert bit on index 4:0. …
10315 …th:0x20 // This register delivers the Storm PC for read-only debug access. 15-0 - STORM A. 31-16…
10316 …e access type defined in data_breakpoint_access_set), the STORMs bits 15:0 - IRAM stall start add…
10317 …efined in data_breakpoint_access_set), the STORMs will be stalled. bit15:0 - IRAM stall end addre…
10318 …- stall on read access. bit1 - stall on write access. bit3:2 - stall on write BE (bit2 -to IRAM'…
10319 …er defines the IRAM address for which the data breakpoint stall was set. bits 0:15 - IRAM address.
10323 … indirect registers defines the modulus (roll-over) values for the corresponding real time clocks.…
10326 …-time clock with regard to the associated RTClkTickValue. The Storm decode assignments used for th…
10329 …-time clocks. This value is assigned to the corresponding real-time clock only when the Storm corr…
10332 …-time clock with the value provided by the associated RTClkInitValue register. The Storm decode as…
10335 …direct registers provides read access to the real time clock values. The sub-address for this indi…
10337 … per RTC used to enable each of the ten real-time clocks. The bit index corresponds with the ID of…
10347 …or the most recent RBC read request issued. The valid bit is returned on bit-0 of the data. All ot…
10357 …0x20 // This array of registers returns the 128-bit CAM match vector returned in the most recent…
10360 …-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fas…
10361 …ources for modes 2 and 3 on the fast debug channel: b0-DRA write disable; b1-DRA read disable; b2-…
10362 …able any of the following debug sources for mode-4 on the fast debug channel: b0-store data disabl…
10363 …ces for mode-6 on the fast debug channel: b0-dra_in disable; b1-fin disable; b2-load disable; b3-t…
10364 …0 // Connection id that should compared with cid field of the data (in Dra-In message); Note: ap…
10365 …aWidth:0x8 // Event id that should compared with event id field of the data (in Dra-In message).
10366 …075cUL //Access:RW DataWidth:0x8 // Mask for event id. 1- specified bit is ignored; 0 - speci…
10367 …e event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active stat…
10368 …e event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active stat…
10370 …- Filter off; in that case all data should be transmitted to the DBG block without any filtering i…
10372 …- use the recorded connection id field which arrives from the DBG block (dbg_sem_cid interface) fo…
10378 … (0x3<<5) // Used to define the DRA-In source that should…
10388 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
10402 … (0x3<<2) // Used to define the DRA-In source that should…
10408 … 0x000a44UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10409 … 0x000a44UL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10411 … 0x000a4cUL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10412 … 0x000a4cUL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10413 … 0x000a50UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10414 …- The accumulated number of Storm cycles in which the Storm has been idle due to having no threads…
10415 … 0x000a54UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10416 … 0x000a54UL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10417 … 0x000a58UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10418 … 0x000a5cUL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10419 … 0x000a60UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10420 … 0x000a64UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10425 …- response is ready. It is set when response cycle of 32 bit is ready from VFC block. It is reset …
10429 … 0x000c4cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
10437 …-address. Bits [3:0] of the data bus provide the OpCode for the request where the following numera…
10439 … 0x00a000UL //Access:RW DataWidth:0x20 // Provides a memory-mapped region for VFC…
10458 …r includes bit per ALU vector: 0-4 long vectors; 5-11 short vectors. When it is set then appropria…
10461 …asserted when there is attempt to write to read only register. It will be de-asserted aftre write …
10471 …ycle not equal 64 bit or number of data cycles bigger than 6. It will be de-asserted aftre write …
10473 …asserted when waitp is asserted and output FIFO is also full. It will be de-asserted aftre write …
10475 …asserted when it was address overflow of INFO part of RSS RAM. It will be de-asserted aftre write …
10477 …ted when it was address overflow of KEY LSB part of RSS RAM. It will be de-asserted aftre write …
10479 …erted when it was address overflow of KEY MSB part of RSS RAM. It will be de-asserted aftre write …
10482 …ty interrupt. It may be asserted when it was CAM parity error. It will be de-asserted aftre write …
10484 …pt. It may be asserted when it was parity error inside TT RAM. It will be de-asserted aftre write …
10486 …terrupt. It may be asserted when it was RSS RAM parity error. It will be de-asserted aftre write …
10532 … 0x000038UL //Access:W DataWidth:0x1 // Write to this bit will cause to block reset.
10534 …reset of all CAM rows including valid bit and all bits in a row. Write 0 to it will have no effect…
10536 …reset of all Target tables rows. Write 0 to it will have no effect. Read 1 from this bit means tha…
10538 …reset of all RSS RAM rows. Write 0 to it will have no effect. Read 1 from this bit means that RAM …
10540 …:RW DataWidth:0x1 // REQUIRED -If this bit is set then background mechanism for parity check …
10542 … 0x000048UL //Access:RW DataWidth:0x3 // REQUIRED - 0 - parity is enabled;…
10543 … 0x00004cUL //Access:RW DataWidth:0xa // REQUIRED - 0 - interrupt is enabled;1- interr…
10554 …p was raised to STORM as a result of full input FIFO. This vector will be reset after reading from…
10556 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
10557 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
10795 … 0x002000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
10800 …_E5 (0xff<<0) // 8-bit value from packag…
10802 …E5 (0xff<<8) // 8-bit value from packag…
10808 …ould be set to '1' to enable the MAC transmit path, should be set to '0' (Reset value) to disable …
10810 …hould be set to '1' to enable the MAC receive path, should be set to '0' (Reset value) to disable …
10816 …all frames are received without any MAC address filtering. If set to '0' (Reset value), Unicast fr…
10820 …rame to the user application. If set to '0' (Reset value), the CRC field is stripped from the fram…
10822 …o '1', pause frames are forwarded to the user application. If set to '0' (Reset value), pause fram…
10824 … set to '1', received pause frames are ignored by the MAC. If set to '0' (Reset value), the transm…
10826 …ddress programmed in registers MAC_ADDR_0 and MAC_ADDR_1 . If set to '0' (Reset value), the source…
10828 …oopback. If set to '1', the signal loop_ena is set to '1'. If set to '0' (Reset value), the signal…
10832 … (0x1<<12) // Self-Clearing Software Reset. When written with '1', all Statistics…
10846 …es according to the Priority Flow Control Interface signals. If set to 0 (Reset Value), the Core o…
10860 … (0x1<<26) // Self-Clearing TX FIFO reset command. …
10913 … (0x1<<5) // MDIO transaction preamble disable. Shortens transaction but is non-standard.
10917 …divisor; A value of 5 to 511. The frequency is reg_clk/(2*divisor+1). The reset default is defined…
10924 … (0x1<<14) // If written with 1, a read with address post-increment will be performed. Post-incr…
10929 …-bit data word. When written- Initiates a write transaction to the PHY. The MDIO_COMMAND register …
10931 …PHY device to read from or write to. After writing this register, an address-write transaction wil…
10939 … (0x1<<2) // PHY indicates loss-of-signal. Represents v…
10959 … (0x1<<0) // Credit-based FIFO only: When written with a 1, RX FIFO …
10962 …5 (0xff<<0) // Credit-based FIFO only: Spec…
10970 …C quanta value for that class when a class XOFF is triggered. Each Quanta specifies a 512 bit-time.
11012 … (0x1<<0) // Enable XGMII-64 (4byte alignment)
11016 … (0x1<<5) // Enable 1-step capable datapath…
11019 …/ Configure saturation behavior. When set to 1, the counters saturate at all-1. Otherwise counters…
11021 … (0x1<<1) // Configure clear-on-read behavior. When …
11023 … (0x1<<2) // Clear all counters command (self-clearing). When writt…
11167 …_K2_E5 (0xf<<8) // RS-FEC receive lane lock…
11169 … (0x1<<14) // Indicates, when 1 that the RS-FEC receiver has lock…
11173 …x20 // Counts number of corrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11174 …umber of corrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11176 …h:0x20 // Counts number of corrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11177 … (0xffff<<0) // Counts number of corrected FEC codewords upper 16-bits; None roll-over; Clears …
11179 …0 // Counts number of uncorrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11180 …ber of uncorrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11182 …0x20 // Counts number of uncorrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11183 … (0xffff<<0) // Counts number of uncorrected FEC codewords upper 16-bits; None roll-over; Clears …
11194 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 0; None roll-over whe…
11195 … (corrected) 10-bit symbol errors found in lane 0 for correctable codewords only; Lower 16-bit of …
11197 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11198 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 0; Clears o…
11200 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 1; None roll-over whe…
11201 … (corrected) 10-bit symbol errors found in lane 1 for correctable codewords only; Lower 16-bit of …
11203 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11204 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 1; Clears o…
11206 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 2; None roll-over whe…
11207 … (corrected) 10-bit symbol errors found in lane 2 for correctable codewords only; Lower 16-bit of …
11209 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11210 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 2; Clears o…
11212 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 3; None roll-over whe…
11213 … (corrected) 10-bit symbol errors found in lane 3 for correctable codewords only; Lower 16-bit of …
11215 … DataWidth:0x20 // Upper 16 bit of counter (with above register); Clears on read; None roll-over.
11216 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 3; Clears o…
11218 … 0x000200UL //Access:RW DataWidth:0x20 // Additional control to enable RS-FEC operation.
11230 …_E5 (0x1<<6) // RX datapath (sync) reset occured; Latched h…
11232 …_E5 (0x1<<7) // TX datapath (sync) reset occured; Latched h…
11240 …_EMPTY_K2_E5 (0xf<<12) // Real-time indication from …
11248 …W DataWidth:0x20 // Bits 7:0; Must be written with the 8-bit value of 0x57 to enable RS-FEC tr…
11249 … (0xff<<0) // Bits 7:0; Must be written with 8-bit value 0x57 to enable RS-FEC tra…
11251 … 0x000214UL //Access:RW DataWidth:0x20 // Bits 15:0. One bit per 10-bit Symbol; Each bit …
11252 … (0xffff<<0) // Bits 15:0. One bit per 10-bit Symbol; When a bi…
11254 … 0x000218UL //Access:RW DataWidth:0x20 // Bits 9:0; A 10-bit value which XORed…
11255 …N_TEST_PATTERN_K2_E5 (0x3ff<<0) // A 10-bit value which will …
11265 … (0x1<<8) // Indicate full-duplex operation; alw…
11279 … (0x1<<15) // PCS soft-reset command; self-clearing
11284 … (0x1<<2) // Indicate link status; latch-low
11296 …x20 // Local Device Abilities for Autonegotiation. Contents differs for 1000Base-X or SGMII mode.
11299 … (0x1<<5) // Indicate full-duplex support; SGMII…
11301 … (0x1<<6) // Indicate half-duplex support; SGMII…
11317 …/ Received Abilities during Autonegotiation. Contents differ depending on 1000Base-X or SGMII mode.
11320 … (0x1<<5) // Indicate full-duplex support; SGMII…
11322 … (0x1<<6) // Indicate half-duplex support; SGMII…
11341 … (0x1<<1) // Autoneg page received indication; latch-high
11392 … (0x1<<4) // Set SGMII half-duplex mode when not …
11410 … (0x1<<15) // 1=PCS reset, 0=normal; Self cl…
11436 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
11468 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11470 … (0x1<<1) // When 1, this PCS is 10GBase-X capable.
11472 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11474 … (0x1<<3) // When 1, this PCS is 10GBase-T capable.
11476 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11478 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11495 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11497 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11499 … (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
11502 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11512 … (0xff<<0) // Errored blocks counter; None roll-over.
11514 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11520 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11521 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11523 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11524 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11526 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11527 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11529 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11530 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11532 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11533 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11535 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11536 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11538 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11539 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11541 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11542 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11549 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11551 …ESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enable.
11555 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11556 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11558 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11559 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11561 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11562 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11586 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11587 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11589 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11590 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11592 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11593 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11595 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11596 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11616 …x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
11617 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dis…
11620 …_THRESHOLD_K2_E5 (0xf<<0) // A 4-bit value to define t…
11622 …0010UL //Access:RW DataWidth:0x20 // Vendor Specific Reg; Define Reduced-XLAUI PMA mode using …
11623 …_K2_E5 (0x1<<0) // Enable Reduced-XLAUI PMA mode using …
11668 …2_E5 (0x1<<1) // When 0 PCS 4-lane MLD function is …
11685 … (0x1<<15) // 1=PCS reset, 0=normal; Self cl…
11711 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
11743 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11745 … (0x1<<1) // When 1, this PCS is 10GBase-X capable.
11747 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11749 … (0x1<<3) // When 1, this PCS is 10GBase-T capable.
11751 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11753 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11770 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11772 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11774 … (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
11777 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11787 … (0xff<<0) // Errored blocks counter; None roll-over.
11789 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11795 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11796 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11798 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11799 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11801 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11802 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11804 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11805 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11807 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11808 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11810 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11811 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11813 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11814 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11816 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11817 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11824 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11826 …ESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enable.
11830 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11831 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11833 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11834 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11836 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11837 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11853 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11854 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11856 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11857 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11859 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11860 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11862 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11863 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11871 …x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
11872 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dis…
11875 …_THRESHOLD_K2_E5 (0xf<<0) // A 4-bit value to define t…
11912 …2_E5 (0x1<<1) // When 0 PCS 4-lane MLD function is …
11962 …- off high-impedance 0x1 - CMU 0 0x3 - Lane 0 0x4 - Lane 1 0x5 - Lane 2 0x6 - Lane 3 0x15 - SoC ci…
12362 … (0x1<<0) // PHY error status. 0x0 - no error 0x1 - PHY has an in…
12364 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12365 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12383 … 0x000680UL //Access:RW DataWidth:0x8 // lower 8-bits of the 16-bit digital te…
12384 … 0x000684UL //Access:RW DataWidth:0x8 // higher 8-bits of the 16-bit digital te…
14398 …used in gearbox applications. 0x0 - DIV4 0x1 - DIV8 0x2 - DIV16 0x3 - DIV20 0x4 - DIV32 0x5 - DIV…
14429 …to the half-rate TX clock path to provide visibility at the TX driver output. 0x0 - mission mode …
14431 …CMU macro to all lanes macros. 0x0 - DIV1 0x1 - DIV2 0x2 - DIV4 0x3 - DIV5 0x4 - DIV8 0x5 - DIV10…
14473 … (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indica…
14477 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14478 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14480 … (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro…
14515 … (0x1<<0) // CMU PLL regulator vddha setting. 0x0 - vddha is 1.5V nominal 0x1 - vddha …
14670 … (0x1<<0) // CMU PLL lock detector status. 0x0 - CMU PLL is not locked 0x1 - CMU PL…
14910 … (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indica…
14914 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14915 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14917 … (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro…
14950 … (0x1<<0) // Select the reference clock. 0 - clk_ref 1- clk_pllref
15204 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
15206 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
15208 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
15210 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
15286 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
15290 …K2_E5 (0x1<<5) // Controls tx_en for Far-End-Digital FED loopbac…
15293 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
15336 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
15418 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15419 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15421 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
15488 … 0x0062fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
15490 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
15497 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
15655 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
15658 …1<<0) // Restarts AN that is already in progress or otherwise completed. Reset is triggered by ri…
15673 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
15677 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
15696 … 0x006650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
15697 … 0x006654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
15701 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
15704 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
15720 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
15722 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
15724 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
15726 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
15728 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
15730 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
15732 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
15734 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
15737 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
15739 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
15741 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
15743 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
15746 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
15753 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
15755 …x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
15758 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15760 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
15762 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15764 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
15766 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15768 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15770 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15772 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15825 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
15828 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
15846 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
15848 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
15850 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
15852 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
15854 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
15856 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
15858 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
15860 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
15863 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
15865 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
15867 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
15869 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
15872 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
15879 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
15881 …k partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
15884 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15886 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
15888 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15890 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
15892 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15894 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15896 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15898 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15949 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
15951 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
15953 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
15955 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
15957 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
15959 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
15961 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
15963 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
15966 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
15968 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
15970 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
15972 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
15974 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
15976 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
15978 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
15981 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
15994 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
15996 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
15998 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
16000 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
16002 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
16004 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
16006 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
16008 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
16011 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
16013 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
16015 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
16017 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
16019 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
16021 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
16627 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
16633 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
16744 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
16777 …les updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
16779 …les updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
16781 …bles updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
16783 …bles updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
16785 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16787 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16789 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16791 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
17203 …2_E5 (0x1<<0) // Enables the run-length detection digi…
17205 … 0x007410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
17207 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
17209 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
17380 … 0x00781cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17381 … 0x007820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17416 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
17439 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17440 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17441 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17442 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17444 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
17590 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
17592 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
17665 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
17774 … (0x1<<3) // Synchronous reset for LT Tx block.
17794 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
17806 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
17810 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
17817 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
17821 …E5 (0x3<<4) // Status report field for pre-cursor tap.
17836 … (0x1<<0) // Synchronous reset for LT Rx block.
17864 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
17868 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
17875 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
17879 … (0x3<<4) // Received status report field for pre-cursor tap.
17886 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
17888 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
17890 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
17892 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
17968 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
17972 …K2_E5 (0x1<<5) // Controls tx_en for Far-End-Digital FED loopbac…
17975 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
18018 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
18100 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18101 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18103 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
18170 … 0x0082fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
18172 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
18179 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
18337 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
18340 …1<<0) // Restarts AN that is already in progress or otherwise completed. Reset is triggered by ri…
18355 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
18359 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
18378 … 0x008650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
18379 … 0x008654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
18383 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
18386 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
18402 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
18404 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
18406 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
18408 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
18410 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
18412 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
18414 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
18416 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
18419 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
18421 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
18423 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
18425 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
18428 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
18435 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
18437 …x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
18440 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18442 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
18444 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18446 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
18448 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18450 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18452 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18454 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
18507 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
18510 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
18528 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
18530 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
18532 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
18534 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
18536 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
18538 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
18540 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
18542 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
18545 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
18547 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
18549 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
18551 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
18554 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
18561 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
18563 …k partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
18566 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18568 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
18570 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18572 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
18574 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18576 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18578 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18580 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
18631 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
18633 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
18635 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
18637 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
18639 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
18641 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
18643 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
18645 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
18648 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
18650 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
18652 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
18654 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
18656 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
18658 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
18660 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
18663 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
18676 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
18678 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
18680 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
18682 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
18684 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
18686 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
18688 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
18690 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
18693 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
18695 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
18697 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
18699 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
18701 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
18703 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
19309 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
19315 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
19426 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
19459 …les updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
19461 …les updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
19463 …bles updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
19465 …bles updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
19467 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19469 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19471 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19473 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19885 …2_E5 (0x1<<0) // Enables the run-length detection digi…
19887 … 0x009410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
19889 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
19891 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
20062 … 0x00981cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20063 … 0x009820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20098 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
20121 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20122 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20123 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20124 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20126 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
20272 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
20274 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
20347 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
20456 … (0x1<<3) // Synchronous reset for LT Tx block.
20476 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
20488 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
20492 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
20499 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
20503 …E5 (0x3<<4) // Status report field for pre-cursor tap.
20518 … (0x1<<0) // Synchronous reset for LT Rx block.
20546 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
20550 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
20557 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
20561 … (0x3<<4) // Received status report field for pre-cursor tap.
20568 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
20570 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
20572 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
20574 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
20650 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
20654 …K2_E5 (0x1<<5) // Controls tx_en for Far-End-Digital FED loopbac…
20657 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
20700 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
20782 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20783 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20785 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
20852 … 0x00a2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
20854 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
20861 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
21019 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
21022 …1<<0) // Restarts AN that is already in progress or otherwise completed. Reset is triggered by ri…
21037 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
21041 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
21060 … 0x00a650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
21061 … 0x00a654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
21065 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
21068 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
21084 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
21086 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
21088 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
21090 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
21092 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
21094 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
21096 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
21098 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
21101 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
21103 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
21105 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
21107 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
21110 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
21117 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
21119 …x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
21122 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21124 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
21126 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21128 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
21130 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21132 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
21134 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21136 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
21189 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
21192 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
21210 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
21212 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
21214 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
21216 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
21218 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
21220 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
21222 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
21224 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
21227 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
21229 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
21231 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
21233 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
21236 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
21243 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
21245 …k partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
21248 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21250 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
21252 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21254 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
21256 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21258 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
21260 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21262 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
21313 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
21315 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
21317 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
21319 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
21321 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
21323 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
21325 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
21327 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
21330 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
21332 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
21334 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
21336 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
21338 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
21340 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
21342 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
21345 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
21358 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
21360 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
21362 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
21364 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
21366 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
21368 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
21370 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
21372 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
21375 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
21377 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
21379 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
21381 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
21383 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
21385 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
21991 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
21997 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
22108 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
22141 …les updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
22143 …les updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
22145 …bles updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
22147 …bles updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
22149 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22151 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22153 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22155 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22567 …2_E5 (0x1<<0) // Enables the run-length detection digi…
22569 … 0x00b410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
22571 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
22573 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
22744 … 0x00b81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22745 … 0x00b820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22780 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
22803 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22804 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22805 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22806 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22808 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
22954 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
22956 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
23029 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
23138 … (0x1<<3) // Synchronous reset for LT Tx block.
23158 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
23170 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
23174 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
23181 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
23185 …E5 (0x3<<4) // Status report field for pre-cursor tap.
23200 … (0x1<<0) // Synchronous reset for LT Rx block.
23228 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
23232 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
23239 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
23243 … (0x3<<4) // Received status report field for pre-cursor tap.
23250 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
23252 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
23254 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
23256 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
23332 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
23336 …K2_E5 (0x1<<5) // Controls tx_en for Far-End-Digital FED loopbac…
23339 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
23382 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
23464 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23465 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23467 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
23534 … 0x00c2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
23536 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
23543 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
23701 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
23704 …1<<0) // Restarts AN that is already in progress or otherwise completed. Reset is triggered by ri…
23719 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
23723 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
23742 … 0x00c650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
23743 … 0x00c654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
23747 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
23750 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
23766 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
23768 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
23770 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
23772 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
23774 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
23776 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
23778 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
23780 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
23783 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
23785 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
23787 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
23789 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
23792 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
23799 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
23801 …x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
23804 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23806 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
23808 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23810 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
23812 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23814 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
23816 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23818 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
23871 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
23874 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
23892 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
23894 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
23896 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
23898 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
23900 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
23902 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
23904 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
23906 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
23909 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
23911 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
23913 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
23915 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
23918 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
23925 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
23927 …k partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
23930 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23932 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
23934 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23936 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
23938 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23940 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
23942 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23944 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
23995 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
23997 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
23999 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
24001 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
24003 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
24005 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
24007 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
24009 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
24012 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
24014 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
24016 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
24018 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
24020 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
24022 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
24024 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
24027 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
24040 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
24042 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
24044 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
24046 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
24048 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
24050 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
24052 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
24054 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
24057 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
24059 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
24061 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
24063 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
24065 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
24067 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
24673 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
24679 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
24790 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
24823 …les updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
24825 …les updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
24827 …bles updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
24829 …bles updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
24831 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24833 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24835 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24837 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
25249 …2_E5 (0x1<<0) // Enables the run-length detection digi…
25251 … 0x00d410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
25253 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
25255 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
25426 … 0x00d81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25427 … 0x00d820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25462 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
25485 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25486 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25487 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25488 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25490 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
25636 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
25638 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
25711 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
25820 … (0x1<<3) // Synchronous reset for LT Tx block.
25840 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
25852 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
25856 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
25863 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
25867 …E5 (0x3<<4) // Status report field for pre-cursor tap.
25882 … (0x1<<0) // Synchronous reset for LT Rx block.
25910 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
25914 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
25921 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
25925 … (0x3<<4) // Received status report field for pre-cursor tap.
25937 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
25950 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
25953 …AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
25965 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25966 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25967 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25969 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25971 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
25972 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
25973 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
25974 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
25975 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
25976 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
25977 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
25978 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
25979 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
25980 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
25981 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
25982 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
25983 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
25984 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
25985 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
25986 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
26004 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
26006 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
26008 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
26010 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
26013 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
26015 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
26017 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
26019 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
26022 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26024 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26026 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26028 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26031 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
26033 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
26035 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
26037 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
26040 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
26042 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26044 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
26096 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
26104 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
26138 …2_E5 (0x1<<2) // Override enable for overriding N-div value
26157 …1_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
26207 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
26214 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
26216 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
26229 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
26231 …P_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
26257 …127_CMU_MASTER_CDN_O_K2_E5 (0x1<<0) // Master reset for CMU
26263 …e for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO …
26271 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
26273 …BUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
26287 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
26523 … 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b010 - pma_lX_rxb_iRecovered byte clock 3'b011 - ck_soc1_int…
26525 … (0x1<<3) // Clock divider for TX path branch 1 : 0-No division, 1- Divide by 2
26527 …h branch 2 clock : 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b011 - ck_soc1_int_root 3'b010,3'b100,3'b1…
26529 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
26532 …ck : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b0…
26534 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
26536 …ck : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b0…
26538 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
26541 …- qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmi…
26543 … (0x1<<3) // Clock divider for RX path branch 3 : 0-No division, 1- Divide by 2
26545 …- qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmi…
26547 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
26550 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
26552 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
26555 …0_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
26560 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
26562 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
26567 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
26569 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
26573 …GEN_CDN_O_K2_E5 (0x1<<5) // Bist generator master reset.
26575 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
26577 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
26582 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
26584 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
26586 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26587 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26588 … 0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
26589 … 0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
26590 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
26592 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
26599 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
26619 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
26620 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26621 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26622 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26623 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26631 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
26632 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
26633 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
26634 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
26635 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
26636 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
26637 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
26638 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
26639 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
26640 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
26641 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
26642 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
26643 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
26644 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
26645 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
26646 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
26647 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
26648 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
26649 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
26650 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
26655 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
26657 …E5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
26659 …_K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
26667 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
26712 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
26714 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
26716 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
26720 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26721 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26722 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26724 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26726 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
26776 …_O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
26783 …_O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
26828 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
26830 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
26832 …PMA_LN_EYE_SGN_RST_O_K2_E5 (0x1<<2) // Reset signal for eye ali…
26875 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
26877 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
26894 … 0x0011f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
26962 …_K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
26964 …K2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
27046 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
27048 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
27075 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
27087 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
27359 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
27361 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27363 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27365 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27369 …2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - R…
27372 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27374 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27376 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27378 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27380 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27382 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27387 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27389 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27407 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
27411 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
27457 … (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the…
27462 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
27464 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
27481 …g to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '…
27488 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
27498 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
27501 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
27503 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
27553 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
27554 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
27555 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
27556 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
27557 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
27558 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
27559 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
27560 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
27561 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
27562 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
27563 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
27564 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
27565 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
27566 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
27567 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
27568 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
27571 …nction. Varies depending on function number. Bits 15-7: Address of first command to run Bits: 6-…
27640 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
27641 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
27703 …ST_IDDQ_SD_O_K2_E5 (0x1<<0) // MSM Function RESET state's default va…
27705 …ST_PD_DFE_O_K2_E5 (0x1<<1) // MSM Function RESET state's default va…
27707 …ST_PD_DFE_BIAS_O_K2_E5 (0x1<<2) // MSM Function RESET state's default va…
27709 …ST_PD_LNREG_O_K2_E5 (0x1<<3) // MSM Function RESET state's default va…
27711 …ST_PD_LNREGH_O_K2_E5 (0x1<<4) // MSM Function RESET state's default va…
27713 …ST_PD_P2S_O_K2_E5 (0x1<<5) // MSM Function RESET state's default va…
27715 …ST_PD_RA_O_K2_E5 (0x1<<6) // MSM Function RESET state's default va…
27717 …ST_PD_S2P_O_K2_E5 (0x1<<7) // MSM Function RESET state's default va…
27720 …ST_PD_SLV_BIAS_O_K2_E5 (0x1<<0) // MSM Function RESET state's default va…
27722 …ST_PD_TXDRV_O_K2_E5 (0x1<<1) // MSM Function RESET state's default va…
27724 …ST_PD_TXREG_O_K2_E5 (0x1<<2) // MSM Function RESET state's default va…
27726 …ST_PD_VCO_O_K2_E5 (0x1<<3) // MSM Function RESET state's default va…
27728 …ST_PD_VCO_BUF_O_K2_E5 (0x1<<4) // MSM Function RESET state's default va…
27730 …ST_RESET_CDR_O_K2_E5 (0x1<<5) // MSM Function RESET state's default va…
27732 …ST_RESET_CDR_GCRX_O_K2_E5 (0x1<<6) // MSM Function RESET state's default va…
27734 …ST_RESET_DFE_O_K2_E5 (0x1<<7) // MSM Function RESET state's default va…
27737 …ST_RESET_LNREG_O_K2_E5 (0x1<<0) // MSM Function RESET state's default va…
27739 …ST_RESET_LNREGH_O_K2_E5 (0x1<<1) // MSM Function RESET state's default va…
27741 …ST_RESET_P2S_O_K2_E5 (0x1<<2) // MSM Function RESET state's default va…
27743 …ST_RESET_RA_O_K2_E5 (0x1<<3) // MSM Function RESET state's default va…
27745 …ST_RESET_S2P_O_K2_E5 (0x1<<4) // MSM Function RESET state's default va…
27747 …ST_RESET_VCO_O_K2_E5 (0x1<<5) // MSM Function RESET state's default va…
27749 …ST_TXREG_BLEED_ENA_O_K2_E5 (0x1<<6) // MSM Function RESET state's default va…
27751 …ST_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MSM Function RESET state's default va…
27754 …ST_CDR_EN_O_K2_E5 (0x1<<0) // MSM Function RESET state's default va…
27756 …ST_RXBCLK_EN_O_K2_E5 (0x1<<1) // MSM Function RESET state's default va…
27758 …ST_RX_GATE_EN_O_K2_E5 (0x1<<2) // MSM Function RESET state's default va…
27760 …ST_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MSM Function RESET state's default va…
27978 …_LOW_EN_O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a prog…
27980 …LOW_EN_O_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor down to a prog…
27998 … (0x1<<6) // Set all DFE calibration values to mid-scale instead of usin…
28000 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
28002 …ONT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
28004 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
28005 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
28006 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
28007 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
28008 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
28009 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
28010 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
28014 …ECAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration for { Tap…
28023 …ATE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
28173 …NE_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
28175 …ADAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
28375 …T_IDDQ_SD_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28377 …T_PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28379 …T_PD_DFE_BIAS_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28381 …T_PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28383 …T_PD_LNREGH_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28385 …T_PD_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28387 …T_PD_RA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28389 …T_PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28392 …T_PD_SLV_BIAS_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28394 …T_PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28396 …T_PD_TXREG_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28398 …T_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28400 …T_PD_VCO_BUF_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28402 …T_RESET_CDR_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28404 …T_RESET_CDR_GCRX_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28406 …T_RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28409 …T_RESET_LNREG_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28411 …T_RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28413 …T_RESET_P2S_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28415 …T_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28417 …T_RESET_S2P_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28419 …T_RESET_VCO_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28421 …T_TXREG_BLEED_ENA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28423 …T_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28426 …T_CDR_EN_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28428 …T_RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28430 …T_RX_GATE_EN_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28432 …T_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28435 …_IDDQ_SD_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28437 …_PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28439 …_PD_DFE_BIAS_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28441 …_PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28443 …_PD_LNREGH_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28445 …_PD_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28447 …_PD_RA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28449 …_PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28452 …_PD_SLV_BIAS_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28454 …_PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28456 …_PD_TXREG_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28458 …_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28460 …_PD_VCO_BUF_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28462 …_RESET_CDR_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28464 …_RESET_CDR_GCRX_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28466 …_RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28469 …_RESET_LNREG_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28471 …_RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28473 …_RESET_P2S_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28475 …_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28477 …_RESET_S2P_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28479 …_RESET_VCO_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28481 …_TXREG_BLEED_ENA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28483 …_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28486 …_CDR_EN_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28488 …_RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28490 …_RX_GATE_EN_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28492 …_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28495 …_IDDQ_SD_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28497 …_PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28499 …_PD_DFE_BIAS_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28501 …_PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28503 …_PD_LNREGH_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28505 …_PD_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28507 …_PD_RA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28509 …_PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28512 …_PD_SLV_BIAS_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28514 …_PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28516 …_PD_TXREG_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28518 …_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28520 …_PD_VCO_BUF_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28522 …_RESET_CDR_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28524 …_RESET_CDR_GCRX_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28526 …_RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28529 …_RESET_LNREG_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28531 …_RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28533 …_RESET_P2S_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28535 …_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28537 …_RESET_S2P_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28539 …_RESET_VCO_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28541 …_TXREG_BLEED_ENA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28543 …_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28546 …_CDR_EN_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28548 …_RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28550 …_RX_GATE_EN_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28552 …_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28555 …_IDDQ_SD_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28557 …_PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28559 …_PD_DFE_BIAS_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28561 …_PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28563 …_PD_LNREGH_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28565 …_PD_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28567 …_PD_RA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28569 …_PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28572 …_PD_SLV_BIAS_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28574 …_PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28576 …_PD_TXREG_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28578 …_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28580 …_PD_VCO_BUF_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28582 …_RESET_CDR_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28584 …_RESET_CDR_GCRX_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28586 …_RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28589 …_RESET_LNREG_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28591 …_RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28593 …_RESET_P2S_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28595 …_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28597 …_RESET_S2P_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28599 …_RESET_VCO_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28601 …_TXREG_BLEED_ENA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28603 …_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28606 …_CDR_EN_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28608 …_RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28610 …_RX_GATE_EN_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28612 …_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28615 …T_DELAY_IDDQ_RESET_1_4_0_K2_E5 (0x1f<<0) // MFSM's PMA pd/reset input control sign…
28619 …T_DELAY_IDDQ_RESET_2_4_0_K2_E5 (0x1f<<0) // MFSM's PMA pd/reset input control sign…
28622 …SR_5_X401_L0_MASTER_CDN_O_K2_E5 (0x1<<0) // Lane0 master reset
28624 …SR_5_X401_L1_MASTER_CDN_O_K2_E5 (0x1<<1) // Lane1 master reset
28626 …SR_5_X401_L2_MASTER_CDN_O_K2_E5 (0x1<<2) // Lane2 master reset
28628 …SR_5_X401_L3_MASTER_CDN_O_K2_E5 (0x1<<3) // Lane3 master reset
28637 …E_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
28709 …_0_PD_LNREGH_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28711 …_0_PD_VCO_BUF_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28713 …_0_RESET_CDR_GCRX_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28715 …_0_RX_GATE_EN_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28717 …_0_RESET_LNREG_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28719 …_0_RESET_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28721 …_0_RESET_S2P_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28723 …_0_RESET_CDR_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28726 …_0_RESET_DFE_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28728 …_0_RESET_VCO_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28730 …_0_RESET_RA_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28732 …_0_RESET_LNREGH_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28734 …_0_PD_DFE_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28736 …_0_PD_LNREG_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28738 …_0_PD_P2S_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28740 …_0_PD_RA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28743 …_0_PD_S2P_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28745 …_0_PD_SLV_BIAS_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28747 …_0_PD_TXDRV_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28749 …_0_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28751 …_0_PD_DFE_BIAS_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28753 …_0_IDDQ_SD_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28755 …_0_CDR_EN_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28757 …_0_RXBCLK_EN_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28760 …_0_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28762 …_0_TXREG_BLEED_ENA_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28764 …_0_PD_TXREG_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28766 …_0_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28769 …_1_PD_LNREGH_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28771 …_1_PD_VCO_BUF_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28773 …_1_RESET_CDR_GCRX_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28775 …_1_RX_GATE_EN_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28777 …_1_RESET_LNREG_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28779 …_1_RESET_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28781 …_1_RESET_S2P_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28783 …_1_RESET_CDR_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28786 …_1_RESET_DFE_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28788 …_1_RESET_VCO_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28790 …_1_RESET_RA_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28792 …_1_RESET_LNREGH_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28794 …_1_PD_DFE_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28796 …_1_PD_LNREG_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28798 …_1_PD_P2S_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28800 …_1_PD_RA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28803 …_1_PD_S2P_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28805 …_1_PD_SLV_BIAS_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28807 …_1_PD_TXDRV_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28809 …_1_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28811 …_1_PD_DFE_BIAS_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28813 …_1_IDDQ_SD_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28815 …_1_CDR_EN_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28817 …_1_RESET_TX_CLKDIV_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28820 …_1_RXBCLK_EN_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28822 …_1_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28824 …_1_TXREG_BLEED_ENA_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28826 …_1_PD_TXREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28829 …_2_PD_LNREGH_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28831 …_2_PD_VCO_BUF_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28833 …_2_RESET_CDR_GCRX_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28835 …_2_RX_GATE_EN_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28837 …_2_RESET_LNREG_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28839 …_2_RESET_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28841 …_2_RESET_S2P_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28843 …_2_RESET_TX_CLKDIV_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28846 …_2_RESET_CDR_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28848 …_2_RESET_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28850 …_2_RESET_VCO_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28852 …_2_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28854 …_2_RESET_LNREGH_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28856 …_2_PD_DFE_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28858 …_2_PD_LNREG_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28860 …_2_PD_P2S_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28863 …_2_PD_RA_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28865 …_2_PD_S2P_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28867 …_2_PD_SLV_BIAS_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28869 …_2_PD_TXDRV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28871 …_2_PD_VCO_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
28873 …_2_PD_DFE_BIAS_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
28875 …_2_IDDQ_SD_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
28877 …_2_CDR_EN_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
28880 …_2_RXBCLK_EN_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
28882 …_2_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
28884 …_2_TXREG_BLEED_ENA_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
28886 …_2_PD_TXREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
28888 … 0x002fbcUL //Access:RW DataWidth:0x8 // MFSM's PMA pd/reset input control sign…
28889 … 0x002fc0UL //Access:RW DataWidth:0x8 // MFSM's PMA pd/reset input control sign…
28890 … 0x002fc4UL //Access:RW DataWidth:0x8 // MFSM's PMA pd/reset input control sign…
28891 … 0x002fc8UL //Access:RW DataWidth:0x8 // MFSM's PMA pd/reset input control sign…
28893 …EF_CLK_WAIT_O_K2_E5 (0x7<<0) // MFSM's PMA pd/reset input control sign…
28901 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
28914 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
28917 …_AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
28929 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28930 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28931 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28933 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28935 … 0x003028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
28936 … 0x00302cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
28937 … 0x003030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
28938 … 0x003034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
28939 … 0x003038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
28940 … 0x00303cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
28941 … 0x003040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
28942 … 0x003044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
28943 … 0x003048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
28944 … 0x00304cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
28945 … 0x003050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
28946 … 0x003054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
28947 … 0x003058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
28948 … 0x00305cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
28949 … 0x003060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
28950 … 0x003064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
28968 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
28970 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
28972 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
28974 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
28977 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
28979 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
28981 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
28983 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
28986 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28988 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28990 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28992 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28995 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
28997 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
28999 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
29001 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29004 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29006 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29008 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
29060 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29068 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
29102 …K2_E5 (0x1<<2) // Override enable for overriding N-div value
29121 …01_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29171 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
29178 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29180 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29193 … 0x0031e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29195 …MP_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29221 …X127_CMU_MASTER_CDN_O_K2_E5 (0x1<<0) // Master reset for CMU
29227 …e for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO …
29235 … 0x003210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29237 …TBUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29251 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
29492 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
29505 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
29508 …HB_PMA_CM_DIVNSEL_6_0_O_K2_E5 (0x7f<<0) // CMU N-divider setting
29520 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29521 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29522 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29524 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29526 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
29527 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
29528 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
29529 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
29530 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
29531 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
29532 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
29533 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
29534 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
29535 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
29536 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
29537 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
29538 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
29539 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
29540 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
29541 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
29559 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
29561 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
29563 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
29565 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
29568 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
29570 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
29572 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
29574 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
29577 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29579 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29581 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29583 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29586 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
29588 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
29590 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
29592 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29595 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29597 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29599 …ides for the following functions: [0] - active high, Override Enable [1] - RESET …
29640 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29648 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
29682 …_E5 (0x1<<2) // Override enable for overriding N-div value
29701 …_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29746 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
29753 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29755 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29768 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29770 …_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29796 …27_CMU_MASTER_CDN_O_K2_E5 (0x1<<0) // Master reset for CMU
29802 …e for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO …
29810 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29812 …US_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29878 …A_CM_DIVPSEL_GEN3_O_K2_E5 (0x7f<<0) // CMU P-divider setting in ge…
29906 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
30245 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
30248 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
30250 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
30253 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
30256 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
30258 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
30261 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
30270 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
30272 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
30277 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
30279 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
30283 …EN_CDN_O_K2_E5 (0x1<<5) // Bist generator master reset.
30285 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
30287 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
30292 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
30294 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
30296 … 0x000824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30297 … 0x000828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30298 … 0x00082cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
30299 … 0x000830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
30300 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
30302 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
30309 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
30329 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
30330 … 0x000854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30331 … 0x000858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30332 … 0x00085cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30333 … 0x000860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30341 … 0x000880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
30342 … 0x000884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
30343 … 0x000888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
30344 … 0x00088cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
30345 … 0x000890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
30346 … 0x000894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
30347 … 0x000898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
30348 … 0x00089cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
30349 … 0x0008a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
30350 … 0x0008a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
30351 … 0x0008a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
30352 … 0x0008acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
30353 … 0x0008b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
30354 … 0x0008b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
30355 … 0x0008b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
30356 … 0x0008bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
30357 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
30358 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
30359 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
30360 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
30365 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
30367 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
30369 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
30377 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
30421 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
30423 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
30425 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
30429 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30430 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30431 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30433 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30435 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
30485 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
30492 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
30536 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
30538 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
30540 …MA_LN_EYE_SGN_RST_O_K2_E5 (0x1<<2) // Reset signal for eye ali…
30627 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
30629 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
30646 … 0x0009f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
30714 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
30716 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
30794 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
30800 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
30802 … 0x000a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
30804 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
30806 … 0x000a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
30824 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
30832 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
30834 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
30861 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
30869 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
31139 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
31141 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31143 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31145 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31149 …2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - R…
31152 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31154 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31156 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31158 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31160 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31162 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31167 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31169 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31187 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
31191 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
31232 …BUF_RSTN_O_K2_E5 (0x1<<3) // TX FIFO synchronous reset
31244 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
31284 … (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the…
31289 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
31291 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
31308 …g to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '…
31317 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
31325 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
31328 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
31330 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
31333 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
31336 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
31338 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
31341 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
31350 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
31352 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
31357 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
31359 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
31363 …EN_CDN_O_K2_E5 (0x1<<5) // Bist generator master reset.
31365 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
31367 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
31372 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
31374 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
31376 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31377 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31378 … 0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
31379 … 0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
31380 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
31382 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
31389 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
31409 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
31410 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31411 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31412 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31413 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31421 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
31422 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
31423 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
31424 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
31425 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
31426 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
31427 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
31428 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
31429 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
31430 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
31431 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
31432 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
31433 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
31434 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
31435 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
31436 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
31437 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
31438 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
31439 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
31440 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
31445 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
31447 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
31449 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
31457 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
31501 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
31503 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
31505 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
31509 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31510 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31511 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31513 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31515 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
31565 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
31572 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
31616 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
31618 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
31620 …MA_LN_EYE_SGN_RST_O_K2_E5 (0x1<<2) // Reset signal for eye ali…
31707 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
31709 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
31726 … 0x0011f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
31794 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
31796 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
31874 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
31880 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
31882 … 0x001280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
31884 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
31886 … 0x001288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
31904 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
31912 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
31914 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
31941 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
31949 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
32219 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
32221 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32223 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32225 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32229 …2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - R…
32232 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32234 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32236 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32238 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32240 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32242 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32247 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32249 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32267 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
32271 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
32312 …BUF_RSTN_O_K2_E5 (0x1<<3) // TX FIFO synchronous reset
32324 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
32364 … (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the…
32369 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
32371 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
32388 …g to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '…
32397 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
32405 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
32408 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
32410 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
32413 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
32416 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
32418 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
32421 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
32430 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
32432 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
32437 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
32439 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
32443 …EN_CDN_O_K2_E5 (0x1<<5) // Bist generator master reset.
32445 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
32447 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
32452 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
32454 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
32456 … 0x001824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32457 … 0x001828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32458 … 0x00182cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
32459 … 0x001830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
32460 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
32462 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
32469 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
32489 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
32490 … 0x001854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32491 … 0x001858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32492 … 0x00185cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32493 … 0x001860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32501 … 0x001880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
32502 … 0x001884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
32503 … 0x001888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
32504 … 0x00188cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
32505 … 0x001890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
32506 … 0x001894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
32507 … 0x001898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
32508 … 0x00189cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
32509 … 0x0018a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
32510 … 0x0018a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
32511 … 0x0018a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
32512 … 0x0018acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
32513 … 0x0018b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
32514 … 0x0018b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
32515 … 0x0018b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
32516 … 0x0018bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
32517 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
32518 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
32519 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
32520 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
32525 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
32527 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
32529 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
32537 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
32581 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
32583 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
32585 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
32589 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32590 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32591 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32593 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32595 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
32645 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
32652 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
32696 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
32698 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
32700 …MA_LN_EYE_SGN_RST_O_K2_E5 (0x1<<2) // Reset signal for eye ali…
32787 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
32789 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
32806 … 0x0019f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
32874 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
32876 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
32954 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
32960 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
32962 … 0x001a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
32964 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
32966 … 0x001a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
32984 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
32992 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
32994 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
33021 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
33029 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
33299 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
33301 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33303 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33305 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33309 …2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - R…
33312 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33314 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33316 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33318 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33320 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33322 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33327 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33329 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33347 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
33351 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
33392 …BUF_RSTN_O_K2_E5 (0x1<<3) // TX FIFO synchronous reset
33404 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
33444 … (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the…
33449 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
33451 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
33468 …g to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '…
33477 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
33485 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
33488 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
33490 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
33493 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
33496 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
33498 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
33501 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
33510 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
33512 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
33517 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
33519 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
33523 …EN_CDN_O_K2_E5 (0x1<<5) // Bist generator master reset.
33525 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
33527 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
33532 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
33534 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
33536 … 0x002024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33537 … 0x002028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33538 … 0x00202cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
33539 … 0x002030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
33540 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
33542 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
33549 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
33569 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
33570 … 0x002054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33571 … 0x002058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33572 … 0x00205cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33573 … 0x002060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33581 … 0x002080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
33582 … 0x002084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
33583 … 0x002088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
33584 … 0x00208cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
33585 … 0x002090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
33586 … 0x002094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
33587 … 0x002098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
33588 … 0x00209cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
33589 … 0x0020a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
33590 … 0x0020a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
33591 … 0x0020a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
33592 … 0x0020acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
33593 … 0x0020b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
33594 … 0x0020b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
33595 … 0x0020b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
33596 … 0x0020bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
33597 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
33598 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
33599 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
33600 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
33605 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
33607 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
33609 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
33617 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
33661 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
33663 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
33665 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
33669 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33670 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33671 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33673 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33675 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
33725 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
33732 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
33776 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
33778 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
33780 …MA_LN_EYE_SGN_RST_O_K2_E5 (0x1<<2) // Reset signal for eye ali…
33867 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
33869 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
33886 … 0x0021f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
33954 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
33956 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
34034 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
34040 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
34042 … 0x002280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
34044 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
34046 … 0x002288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
34064 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
34072 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
34074 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
34101 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
34109 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
34379 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
34381 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34383 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34385 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34389 …2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - R…
34392 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34394 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34396 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34398 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34400 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34402 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34407 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34409 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34427 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
34431 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
34472 …BUF_RSTN_O_K2_E5 (0x1<<3) // TX FIFO synchronous reset
34484 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
34524 … (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the…
34529 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
34531 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
34548 …g to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '…
34557 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
34565 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
34568 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
34570 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
34621 … 0x002880UL //Access:RW DataWidth:0x8 // SKP symbol for PCIe Gen3 SKP OS ---8'hAA
34631 … 0x002898UL //Access:RW DataWidth:0x8 // 10-bit align symbol for …
34633 …_S0_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for …
34635 … 0x0028a0UL //Access:RW DataWidth:0x8 // 10-bit align symbol for …
34637 …_S1_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for …
34702 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
34703 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
34704 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
34705 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
34706 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
34707 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
34708 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
34709 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
34710 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
34711 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
34712 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
34713 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
34714 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
34715 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
34716 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
34717 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
34720 …nction. Varies depending on function number. Bits 15-7: Address of first command to run Bits: 6-…
34789 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
34790 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
34852 …T_IDDQ_SD_O_K2_E5 (0x1<<0) // MSM Function RESET state's default va…
34854 …T_PD_DFE_O_K2_E5 (0x1<<1) // MSM Function RESET state's default va…
34856 …T_PD_DFE_BIAS_O_K2_E5 (0x1<<2) // MSM Function RESET state's default va…
34858 …T_PD_LNREG_O_K2_E5 (0x1<<3) // MSM Function RESET state's default va…
34860 …T_PD_LNREGH_O_K2_E5 (0x1<<4) // MSM Function RESET state's default va…
34862 …T_PD_P2S_O_K2_E5 (0x1<<5) // MSM Function RESET state's default va…
34864 …T_PD_RA_O_K2_E5 (0x1<<6) // MSM Function RESET state's default va…
34866 …T_PD_S2P_O_K2_E5 (0x1<<7) // MSM Function RESET state's default va…
34869 …T_PD_SLV_BIAS_O_K2_E5 (0x1<<0) // MSM Function RESET state's default va…
34871 …T_PD_TXDRV_O_K2_E5 (0x1<<1) // MSM Function RESET state's default va…
34873 …T_PD_TXREG_O_K2_E5 (0x1<<2) // MSM Function RESET state's default va…
34875 …T_PD_VCO_O_K2_E5 (0x1<<3) // MSM Function RESET state's default va…
34877 …T_PD_VCO_BUF_O_K2_E5 (0x1<<4) // MSM Function RESET state's default va…
34879 …T_RESET_CDR_O_K2_E5 (0x1<<5) // MSM Function RESET state's default va…
34881 …T_RESET_CDR_GCRX_O_K2_E5 (0x1<<6) // MSM Function RESET state's default va…
34883 …T_RESET_DFE_O_K2_E5 (0x1<<7) // MSM Function RESET state's default va…
34886 …T_RESET_LNREG_O_K2_E5 (0x1<<0) // MSM Function RESET state's default va…
34888 …T_RESET_LNREGH_O_K2_E5 (0x1<<1) // MSM Function RESET state's default va…
34890 …T_RESET_P2S_O_K2_E5 (0x1<<2) // MSM Function RESET state's default va…
34892 …T_RESET_RA_O_K2_E5 (0x1<<3) // MSM Function RESET state's default va…
34894 …T_RESET_S2P_O_K2_E5 (0x1<<4) // MSM Function RESET state's default va…
34896 …T_RESET_VCO_O_K2_E5 (0x1<<5) // MSM Function RESET state's default va…
34898 …T_TXREG_BLEED_ENA_O_K2_E5 (0x1<<6) // MSM Function RESET state's default va…
34900 …T_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MSM Function RESET state's default va…
34903 …T_CDR_EN_O_K2_E5 (0x1<<0) // MSM Function RESET state's default va…
34905 …T_RXBCLK_EN_O_K2_E5 (0x1<<1) // MSM Function RESET state's default va…
34907 …T_RX_GATE_EN_O_K2_E5 (0x1<<2) // MSM Function RESET state's default va…
34909 …T_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MSM Function RESET state's default va…
35260 …LOW_EN_O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a prog…
35262 …OW_EN_O_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor down to a prog…
35280 … (0x1<<6) // Set all DFE calibration values to mid-scale instead of usin…
35282 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
35284 …NT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
35286 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
35287 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
35288 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
35289 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
35290 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
35291 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
35292 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
35296 …CAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration for { Tap…
35305 …TE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
35464 …E_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
35466 …DAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
35475 …2_E5 (0x1f<<0) // Bit 4 - latency check control enable Bit 3:0 - l…
35708 …_IDDQ_SD_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35710 …_PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35712 …_PD_DFE_BIAS_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35714 …_PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35716 …_PD_LNREGH_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
35718 …_PD_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
35720 …_PD_RA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
35722 …_PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
35725 …_PD_SLV_BIAS_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35727 …_PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35729 …_PD_TXREG_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35731 …_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35733 …_PD_VCO_BUF_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
35735 …_RESET_CDR_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
35737 …_RESET_CDR_GCRX_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
35739 …_RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
35742 …_RESET_LNREG_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35744 …_RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35746 …_RESET_P2S_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35748 …_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35750 …_RESET_S2P_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
35752 …_RESET_VCO_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
35754 …_TXREG_BLEED_ENA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
35756 …_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
35759 …_CDR_EN_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35761 …_RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35763 …_RX_GATE_EN_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35765 …_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35768 …IDDQ_SD_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35770 …PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35772 …PD_DFE_BIAS_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35774 …PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35776 …PD_LNREGH_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
35778 …PD_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
35780 …PD_RA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
35782 …PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
35785 …PD_SLV_BIAS_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35787 …PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35789 …PD_TXREG_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35791 …PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35793 …PD_VCO_BUF_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
35795 …RESET_CDR_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
35797 …RESET_CDR_GCRX_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
35799 …RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
35802 …RESET_LNREG_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35804 …RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35806 …RESET_P2S_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35808 …RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35810 …RESET_S2P_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
35812 …RESET_VCO_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
35814 …TXREG_BLEED_ENA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
35816 …TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
35819 …CDR_EN_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35821 …RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35823 …RX_GATE_EN_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35825 …RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35828 …IDDQ_SD_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35830 …PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35832 …PD_DFE_BIAS_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35834 …PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35836 …PD_LNREGH_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
35838 …PD_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
35840 …PD_RA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
35842 …PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
35845 …PD_SLV_BIAS_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35847 …PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35849 …PD_TXREG_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35851 …PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35853 …PD_VCO_BUF_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
35855 …RESET_CDR_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
35857 …RESET_CDR_GCRX_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
35859 …RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
35862 …RESET_LNREG_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35864 …RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35866 …RESET_P2S_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35868 …RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35870 …RESET_S2P_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
35872 …RESET_VCO_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
35874 …TXREG_BLEED_ENA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
35876 …TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
35879 …CDR_EN_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35881 …RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35883 …RX_GATE_EN_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35885 …RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35888 …IDDQ_SD_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35890 …PD_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35892 …PD_DFE_BIAS_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35894 …PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35896 …PD_LNREGH_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
35898 …PD_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
35900 …PD_RA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
35902 …PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
35905 …PD_SLV_BIAS_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35907 …PD_TXDRV_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35909 …PD_TXREG_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35911 …PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35913 …PD_VCO_BUF_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
35915 …RESET_CDR_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
35917 …RESET_CDR_GCRX_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
35919 …RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
35922 …RESET_LNREG_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35924 …RESET_LNREGH_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35926 …RESET_P2S_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35928 …RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35930 …RESET_S2P_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
35932 …RESET_VCO_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
35934 …TXREG_BLEED_ENA_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
35936 …TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
35939 …CDR_EN_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
35941 …RXBCLK_EN_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
35943 …RX_GATE_EN_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
35945 …RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
35948 …_DELAY_IDDQ_RESET_1_4_0_K2_E5 (0x1f<<0) // MFSM's PMA pd/reset input control sign…
35951 …_DELAY_IDDQ_RESET_2_4_0_K2_E5 (0x1f<<0) // MFSM's PMA pd/reset input control sign…
35954 …R_5_X401_L0_MASTER_CDN_O_K2_E5 (0x1<<0) // Lane0 master reset
35956 …R_5_X401_L1_MASTER_CDN_O_K2_E5 (0x1<<1) // Lane1 master reset
35958 …R_5_X401_L2_MASTER_CDN_O_K2_E5 (0x1<<2) // Lane2 master reset
35960 …R_5_X401_L3_MASTER_CDN_O_K2_E5 (0x1<<3) // Lane3 master reset
35973 …_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
36036 …X414_TXPRESET_COEFF_P0CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P0 C-1
36045 …X417_TXPRESET_COEFF_P1CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P1 C-1
36054 …X420_TXPRESET_COEFF_P2CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P2 C-1
36063 …X423_TXPRESET_COEFF_P3CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P3 C-1
36072 …X426_TXPRESET_COEFF_P4CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P4 C-1
36081 …X429_TXPRESET_COEFF_P5CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P5 C-1
36090 …X432_TXPRESET_COEFF_P6CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P6 C-1
36099 …X435_TXPRESET_COEFF_P7CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P7 C-1
36108 …X438_TXPRESET_COEFF_P8CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P8 C-1
36117 …X441_TXPRESET_COEFF_P9CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P9 C-1
36126 …444_TXPRESET_COEFF_P10CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P10 C-1
36169 …0_PD_LNREGH_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
36171 …0_PD_VCO_BUF_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
36173 …0_RESET_CDR_GCRX_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
36175 …0_RX_GATE_EN_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
36177 …0_RESET_LNREG_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
36179 …0_RESET_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
36181 …0_RESET_S2P_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
36183 …0_RESET_CDR_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
36186 …0_RESET_DFE_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
36188 …0_RESET_VCO_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
36190 …0_RESET_RA_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
36192 …0_RESET_LNREGH_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
36194 …0_PD_DFE_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
36196 …0_PD_LNREG_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
36198 …0_PD_P2S_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
36200 …0_PD_RA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
36203 …0_PD_S2P_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
36205 …0_PD_SLV_BIAS_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
36207 …0_PD_TXDRV_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
36209 …0_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
36211 …0_PD_DFE_BIAS_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
36213 …0_IDDQ_SD_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
36215 …0_CDR_EN_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
36217 …0_RXBCLK_EN_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
36220 …0_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
36222 …0_TXREG_BLEED_ENA_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
36224 …0_PD_TXREG_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
36226 …0_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
36229 …1_PD_LNREGH_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
36231 …1_PD_VCO_BUF_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
36233 …1_RESET_CDR_GCRX_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
36235 …1_RX_GATE_EN_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
36237 …1_RESET_LNREG_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
36239 …1_RESET_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
36241 …1_RESET_S2P_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
36243 …1_RESET_CDR_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
36246 …1_RESET_DFE_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
36248 …1_RESET_VCO_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
36250 …1_RESET_RA_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
36252 …1_RESET_LNREGH_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
36254 …1_PD_DFE_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
36256 …1_PD_LNREG_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
36258 …1_PD_P2S_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
36260 …1_PD_RA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
36263 …1_PD_S2P_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
36265 …1_PD_SLV_BIAS_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
36267 …1_PD_TXDRV_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
36269 …1_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
36271 …1_PD_DFE_BIAS_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
36273 …1_IDDQ_SD_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
36275 …1_CDR_EN_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
36277 …1_RESET_TX_CLKDIV_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
36280 …1_RXBCLK_EN_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
36282 …1_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
36284 …1_TXREG_BLEED_ENA_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
36286 …1_PD_TXREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
36289 …2_PD_LNREGH_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
36291 …2_PD_VCO_BUF_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
36293 …2_RESET_CDR_GCRX_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
36295 …2_RX_GATE_EN_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
36297 …2_RESET_LNREG_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
36299 …2_RESET_P2S_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
36301 …2_RESET_S2P_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
36303 …2_RESET_TX_CLKDIV_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
36306 …2_RESET_CDR_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
36308 …2_RESET_DFE_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
36310 …2_RESET_VCO_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
36312 …2_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
36314 …2_RESET_LNREGH_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
36316 …2_PD_DFE_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
36318 …2_PD_LNREG_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
36320 …2_PD_P2S_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
36323 …2_PD_RA_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
36325 …2_PD_S2P_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
36327 …2_PD_SLV_BIAS_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
36329 …2_PD_TXDRV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
36331 …2_PD_VCO_O_K2_E5 (0x1<<4) // MFSM's PMA pd/reset input control sign…
36333 …2_PD_DFE_BIAS_O_K2_E5 (0x1<<5) // MFSM's PMA pd/reset input control sign…
36335 …2_IDDQ_SD_O_K2_E5 (0x1<<6) // MFSM's PMA pd/reset input control sign…
36337 …2_CDR_EN_O_K2_E5 (0x1<<7) // MFSM's PMA pd/reset input control sign…
36340 …2_RXBCLK_EN_O_K2_E5 (0x1<<0) // MFSM's PMA pd/reset input control sign…
36342 …2_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<1) // MFSM's PMA pd/reset input control sign…
36344 …2_TXREG_BLEED_ENA_O_K2_E5 (0x1<<2) // MFSM's PMA pd/reset input control sign…
36346 …2_PD_TXREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/reset input control sign…
36348 … 0x002fbcUL //Access:RW DataWidth:0x8 // MFSM's PMA pd/reset input control sign…
36349 … 0x002fc0UL //Access:RW DataWidth:0x8 // MFSM's PMA pd/reset input control sign…
36350 … 0x002fc4UL //Access:RW DataWidth:0x8 // MFSM's PMA pd/reset input control sign…
36351 … 0x002fc8UL //Access:RW DataWidth:0x8 // MFSM's PMA pd/reset input control sign…
36353 …F_CLK_WAIT_O_K2_E5 (0x7<<0) // MFSM's PMA pd/reset input control sign…
36355 …Reset configuration register. inside order of the bits is: [0] rst_pswrq_auto_mode (0- no auto dea…
36356 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36358 …-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific bloc…
36360 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36362 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36364 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36366 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36422 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36424 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36426 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36427 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36431 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36433 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36435 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36436 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36440 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36442 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36444 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36445 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36449 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36451 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36453 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36454 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36458 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36460 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36462 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36463 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36467 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36469 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36471 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36472 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36476 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36478 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36480 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36481 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36485 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36487 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36489 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36490 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36494 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36496 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36498 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36499 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36503 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36505 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36507 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36508 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36512 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36514 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36516 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36517 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36521 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36523 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36525 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36526 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36530 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36532 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36534 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36535 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36539 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36541 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36543 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36544 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36548 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36550 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36552 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36553 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36557 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36559 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36561 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36562 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36566 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36568 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36570 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36571 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36575 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36577 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36579 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36580 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36584 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36586 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36588 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36589 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36593 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36595 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36597 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36598 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36602 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36604 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36606 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36607 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36611 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36613 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36615 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36616 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36620 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36622 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36624 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36625 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36629 … MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP P…
36631 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36633 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36634 … Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity e…
36635 … 0x0087fcUL //Access:RW DataWidth:0x1 // If set a system kill occurred. Reset on POR reset.
36636 …cess:RW DataWidth:0x1 // The System Kill enable: 0 - none; 1 - hard reset. Reset on POR reset.
36637 …O29; [30] GPIO30; [31] GPIO31; System kill signal (that which causes hard reset) is blocked by aeu…
36638 …] PCIE glue/PXP VPD event #15; System kill signal (that which causes hard reset) is blocked by aeu…
36639 …l attn30; [31] General attn31; System kill signal (that which causes hard reset) is blocked by aeu…
36640 …-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity erro…
36641 …error; [31] TSEM Hw interrupt; System kill signal (that which causes hard reset) is blocked by aeu…
36642 …-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw inte…
36643 …rror; [31] PSWRQ Hw interrupt; System kill signal (that which causes hard reset) is blocked by aeu…
36644 …ertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt; System kill signa…
36645 …reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt…
36655 …n (goes 0); [7] one clears PERST_N de-assertion (goes 1). [8] one clears PCIe link up. [9] one cle…
36657 …ister results with the clear of the latched signals; [0] - clears pglue_misc_vpd_attn[0], [1] - cl…
36659 … 0x00883cUL //Access:RW DataWidth:0x9 // Attention sticky number - latches first attent…
36660 …0x2 // Port mode. 0 - single port; 1 - 2 ports; 2 - 4 ports. 2 is prohibited configuration in 2…
36661 …- Single Port Mode; 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the XMAC_M…
36662 …- Single Port Mode; 01 - Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap …
36663 …- disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port. Port…
36664 …ypassed in latency-critical paths. bit0 - clock mux control (Obsolete), bit1 - BRB/BTB control, bi…
36665 …E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset. [0]- BRB; [1] - BTB…
36667 …- Storms stall is disallowed; AEU unifier bit[7] output to MCP is disabled; 1 - All Storms are for…
36668 …c20UL //Access:RW DataWidth:0x17 // 23 bit GRC address where the scratch-pad of the MCP that i…
36669 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36670 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36671 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36672 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36673 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36674 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36675 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36676 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36688 … 0x008c70UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by hard reset.
36689 … 0x008c74UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by hard reset.
36690 … 0x008c78UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by hard reset.
36691 … 0x008c7cUL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by hard reset.
36692 … 0x008c80UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by core reset.
36693 … 0x008c84UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by core reset.
36694 … 0x008c88UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by core reset.
36695 … 0x008c8cUL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by core reset.
36696 … 0x008c90UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by por reset.
36697 … 0x008c94UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by por reset.
36698 … 0x008c98UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by por reset.
36699 … 0x008c9cUL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by por reset.
36701 …he counter for sw timers1-8. there are 8 addresses in this register. address 0 - timer 1; address …
36703 …Reset configuration register. inside order of the bits is: [0] rst_ncsi_on_core_rst (0- no auto de…
36704 …Reset configuration register. inside order of the bits is: [0] rst_n_reg_hard_misc_rbc_pcie (0 - i…
36705 …reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = th…
36707 …reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the co…
36710 …programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset.
36711 …- source of privilege level, 0 - the source is external pin, 1 - the source are bits[2:1] of this …
36712 … // Privilege level as defined by external pin. 0 - non-secured mode; 1 - secured mode; 2 - full…
36713 …-disable to the NVM block is generated. '0' - PROTECT: This value protects the NVM from any writes…
36714 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36716 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36718 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36720 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36722 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36724 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36726 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36728 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36730 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36732 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36734 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36736 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36738 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36740 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36742 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36744 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36746 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36748 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36750 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36752 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36754 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36756 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36758 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36760 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36762 …reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the co…
36892 …state of the ptw_miscs_pcie_link_up signal which is driven by the PCIE core - a pulse at the begin…
36893 …cie_hot_reset signal which is driven by the PCIE core - a pulse at the beginning of PCIe hot reset.
36894 … DataWidth:0x10 // Accounts for HOT RESET assertion when the chip is in prepared state. Is res…
36895 … DataWidth:0x10 // Accounts for HOT RESET assertion when the chip is in un-prepared state. Is re…
36896 …3d0UL //Access:RW DataWidth:0x10 // Accounts for PCIE LINK UP assertion. Is reset on POR reset.
36897 … when main PLL lock indication is de-asserted when hard reset is de-asserted. Reset to 0 by FW. Is…
36898 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36899 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36900 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36901 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36902 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36903 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36904 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36905 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36906 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36907 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36908 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36909 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36910 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36911 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36912 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36913 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36914 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36915 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36916 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36917 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36918 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36919 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36920 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36921 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36922 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36923 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36924 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36925 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36926 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36927 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36928 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36929 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36930 …ding GPIO bit will turn off it's drivers and become an input. This is the reset state of all GPIO …
36996 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
36997 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
36998 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
36999 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37000 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37001 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37002 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37003 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37004 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37005 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37006 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37007 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37008 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37009 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37010 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37011 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37012 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37013 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37014 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37015 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37016 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37017 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37018 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37019 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37020 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37021 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37022 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37023 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37024 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37025 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37026 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37027 …reset value 0). [2] OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VAL…
37029 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37031 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37033 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37035 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37037 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37039 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37041 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37043 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37046 …-assertion. If == 1, triggers chip core reset. If == 0, doesn't trigger chip core reset. Bit[1]: P…
37047 …Reset on POR reset and PERST# de-assert. Bit[1]: WAKE control � direct MFW control of the WAKE# IO…
37048 …ccess:RW DataWidth:0x1 // When 0, indicated PCIE EP controller is in reset, except for PMC mo…
37049 …9660UL //Access:RW DataWidth:0x1 // When 0, indicated PCIE PHY is in reset Refer to PCIE PHY …
37050 …0x0096b8UL //Access:R DataWidth:0x1 // Chip core_rst_n status. 0 - asserted; 1 - de-asserted.
37053 …ss:RW DataWidth:0x20 // Debug only: spare RW register reset by hard reset. Reset on hard reset.
37054 …ss:RW DataWidth:0x20 // Debug only: spare RW register reset by hard reset. Reset on hard reset.
37055 …ss:RW DataWidth:0x20 // Debug only: spare RW register reset by core reset. Reset on core reset.
37056 …ss:RW DataWidth:0x20 // Debug only: spare RW register reset by core reset. Reset on core reset.
37057 …reset by por reset. bit 0 is used for Vmain state machine system kill reset. If clear will not res…
37058 …cess:RW DataWidth:0x20 // Debug only: spare RW register reset by por reset. Reset on POR reset.
37059 …- Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON. When set to 0 - vTMON is in reset. …
37060 …/ Debug only: spare RW register reset by core reset. Bit[0]: used for VCCMIN control to select 25M…
37061 …- spare RW register reset by por reset; [10:8] : PCIe Device Type: 3'b000 - Endpoint mode; 3'b010 …
37063 … DataWidth:0x2 // 0-bypass the Vmain PORBG. for Vmain POR; if sel=1 the output wil be MISC_REGI…
37064 …- bypass select; Bits[15:1] - bypass value per function (1 - function 1; 2 -function 2; etc.). Whe…
37065 …t indicates that a Vmain powerdown event occurred. Write 0 to clear the event. Reset on hard reset.
37069 … DataWidth:0x1 // NIG debug mux vector control. 0 - NIG0 debug vector is output to IFMUX; 1 -…
37070 …Drives misc_cnig_mux_4port_shared_mdio_en output. Applicable both in 2-port and 4-port mode. TBD: …
37071 …1 // NIG EMAC debug source selector. If 0 - path0 gmii/mii emac debug outputs are selected by N…
37072 …s:R DataWidth:0x2 // SEL_VAUX_B - Control to power switching logic. [0] - output value drive…
37077 …N to override the hardware mode defined defaults. Global register. Reset on Hard reset. TBD: uncon…
37078 …-chip PHY devices and MAC ports to the four MDIO domains. It is only used when MISC_REGISTERS_MDIO…
37079 …is asserted (Hot Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state. Res…
37082 …l reset exactly like a power-up reset. There is not protection for this request and it may cause a…
37083 …reset; the SM affects the controls. Bit 0 - Vmain OTP reset; Bit 1 - isolation_logic_b; Bit 2 - un…
37084 …reset; the SM affects the controls. Bit 0 - Vmain OTP reset; Bit 1 - isolation_logic_b; Bit 2 - up…
37087 …-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bi…
37088 …taWidth:0x1 // [0]clock storm bypass: 0-select Storm SPLL clock; 1-select external clock; Reset…
37089 … remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset.
37090 … remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset.
37091 … remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset.
37092 … 0x009760UL //Access:R DataWidth:0x1 // 0 - VAUX is not present (external pin is 0); 1 …
37093 …-6] RESERVED (FLOAT: these IOs are outputs only). [5-4] CLR: When any of these bits is written as …
37096 … the chip. This value starts at 0x0 for the A0 tape-out and increments by one for each all-layer t…
37097 …f the chip. This value starts at 0x00 for each all-layer tape-out and increments by one for each t…
37100 …nly. The PCI power will always read as '0' in this state; as if the chip is in Out-Of-Box WOL mode.
37102 …09788UL //Access:RW DataWidth:0x10 // Accounts for Hard reset assertion. Is reset on POR reset.
37103 …8cUL //Access:RW DataWidth:0x10 // Accounts for Hard reset de-assertion. Is reset on POR reset.
37104 …09790UL //Access:RW DataWidth:0x10 // Accounts for Core reset assertion. Is reset on POR reset.
37105 …94UL //Access:RW DataWidth:0x10 // Accounts for Core de-reset assertion. Is reset on POR reset.
37106 …98UL //Access:RW DataWidth:0x10 // Accounts for PERST_B reset assertion. Is reset on POR reset.
37107 …L //Access:RW DataWidth:0x10 // Accounts for PERST_B reset de-assertion. Is reset on POR reset.
37108 …10 // Accounts for PCI_RST_N assertion when the chip is in prepared state. Is reset on POR reset.
37109 … // Accounts for PCI_RST_N assertion when the chip is in un-prepared state. Is reset on POR reset.
37110 …7a8UL //Access:RW DataWidth:0x10 // Accounts for PCI_RST_N de-assertion. Is reset on POR reset.
37111 …Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state, hard reset is assert…
37113 …UL //Access:RW DataWidth:0x20 // Eco reserved. Global register. [31:30] - used to programm loo…
37120 …r-ride: When set, over-ride DAC code from AVS monitor with on from this register [20:11] VMgmt DAC…
37121 …- Per-TC packet available status; [10] - STORM FIFO; [9] - BTB SOP FIFO for engine 0; [8] - BTB S…
37122 …- STORM FIFO almost full; [10] - STORM FIFO full; [9] - BTB SOP FIFO full for engine 0; [8] - …
37123 …- Received packet from BTB IF0 of engine 0; [6] - Received packet from BTB IF0 of engine 1; [5] …
37124 …- storm_init_crd: Credits for the output STORM Packet interface. [3:2] - storm_pkt_dst: Select t…
37125 …-full Threshold. [29:25] - Btb_if0_fifo_almfull_thr: Almost-full threshold for BTB main traffic F…
37167 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
37168 … enable. If 0 - the acknowledge input is disregarded; valid is deasserted; full is asserted; all o…
37169 …t;Master) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
37231 … 0x00c400UL //Access:RW DataWidth:0x4 // DMAE- PCI Request Interfac…
37232 …404UL //Access:RW DataWidth:0x1 // Relaxed ordering. 0-strict PCI ordering is used;1-PCI-X re…
37233 … 0x00c408UL //Access:RW DataWidth:0x1 // 0-PCI type cache snoop protection is required;…
37234 …00c40cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 initial value is all zeroes; if 1 - t…
37235 … //Access:RW DataWidth:0x1 // If 0 - the CRC-16 final calculation result isn't byte swapped; …
37236 …0c414UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16c initial value is all zeroes; if 1 - t…
37237 …c418UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 T10 initial value is all zeroes; if 1 -…
37238 …00c41cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-32 initial value is all zeroes; if 1 - t…
37239 … //Access:RW DataWidth:0x1 // If 0 - the CRC-32 final calculation result isn't byte swapped; …
37240 …0c424UL //Access:RW DataWidth:0x1 // If 0 - the CRC-32c initial value is all zeroes; if 1 - t…
37241 …//Access:RW DataWidth:0x1 // If 0 - the CRC-32c final calculation result isn't byte swapped; …
37242 …0x00c42cUL //Access:RW DataWidth:0x1 // If 0 - the final checksum equal 0 won't be changed;if…
37243 …st ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; …
37244 …st ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; …
37245 … 0x00c438UL //Access:RW DataWidth:0x1 // When set discards 1- or 2-Dword PCI transact…
37246 … 0x00c43cUL //Access:RW DataWidth:0x14 // GRC address in case 1- or 2-Dword PCI transact…
37250 …- Bidirectional shared data structure; 01 - Device writes/reads then device reads/writes soon; 10 …
37255 …: 0 - VN Virtualized NIC (Used for VF access); 1 - PDA Physical Device Assignment (Assigned to VM-…
37272 …- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other e…
37273 …- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other e…
37281 …as follows: 0-NONE; 1-DoubleBwTx (DoubleBw the TX side); 2-DoubleBwRx (DoubleBw the RX side); 3-Cr…
37282 …dex for slot 0 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37283 …dex for slot 1 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37284 …dex for slot 2 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37285 …dex for slot 3 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37286 …dex for slot 4 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37287 …dex for slot 5 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37288 …dex for slot 6 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37289 …dex for slot 7 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37290 …dex for slot 8 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37291 …dex for slot 9 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37292 …ex for slot 10 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37293 …ex for slot 11 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37294 …ex for slot 12 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37295 …ex for slot 13 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37296 …ex for slot 14 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37297 …ex for slot 15 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37299 …- 128b STORM (A and B) data is logged 1 - 64b STORM (A and B) data + 4 different (in general case)…
37300 …only: These bits indicate the target of the debug data: 0 - internal buffer; 1 - NIG; 2 - PCI.
37301 …-one shot (newest data is thrown) as follows: (a) When DBG_REGISTERS_DEBUG_TARGET =0 (internal buf…
37319 …ddress that was written to the internal buffer. An exception exists after reset when DBG_REGISTERS…
37322 …when DBG_REGISTERS_DEBUG_TARGET =1 (NIG) and DBG_REGISTERS_FULL_MODE =0 (one-shot); WB Read Only (…
37332 … value of the external PCI buffer size in target_packet_size chunks (The reset value is for 128 M…
37333 …the NIG (The reset value is for 4M chunks of target_packet_size data byte each); Relevant only whe…
37339 …mpletion of all required configuration for the dbg block and shouldn't be reset during all operati…
37340 …- no grants will be made to the storms when the internal buffer is almost full. When the buffer w…
37341 …r should be >= 12. Together with DBG_REG_BUFFER_THR_HIGH provides histerezis-like mechanism to set…
37342 …tes logical/physical address in PCI request as follows: (a) 1 - logical address; (b) 0 - physical…
37343 … to internal buffer to be output to IFMUX interface. 0 - bits[31:0] 1 - bits[63:32] 2:6 - etc. 7 -…
37344 …h:0x9 // Debug only: together with DBG_REG_BUFFER_THR provides histerezis-like mechanism to set…
37345 …on is done as follows: bits 255:0 - data; bits 263:256 - frame; bits 271:264 - valid; bits 303:272…
37349 …tor as follows: (a) 1 - bit is masked. This bit won't be compared with the DBG_REGISTERS_EXPECTED…
37351 … pattern recognition feature is disabled/enabled as follows: (a) 1 - disabled; (b) 0 - enabled;.
37352 …nition feature as follows: (a) 1 - stop debug data storgae when the expected pattern is initially…
37353 …occurence as follows: (a) 1 - enable continuously data storage after/before first occurence of pat…
37354 … // (a) 0 - trigger machine is off (all data will bypass the triggering machine); dbg_sem_trgr_…
37355 …010550UL //Access:RW DataWidth:0x1 // (a) 0 - triggering interleaved messages is disabled. (b…
37356 … to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits…
37357 … to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits…
37358 … to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits…
37359 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37360 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37361 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37374 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37375 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37376 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37377 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37378 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37379 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37380 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37381 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37382 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37383 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37384 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37385 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37386 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37387 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37388 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37389 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37390 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37391 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37392 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37393 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37394 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37395 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37396 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37397 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37446 … 0x0106bcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37447 … 0x0106c0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37448 … 0x0106c4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37449 … 0x0106c8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37450 … 0x0106ccUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37451 … 0x0106d0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37452 … 0x0106d4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37453 … 0x0106d8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37454 … 0x0106dcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37455 … 0x0106e0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37456 … 0x0106e4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37457 … 0x0106e8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37458 … 0x0106ecUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37459 … 0x0106f0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37460 … 0x0106f4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37461 … 0x0106f8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37462 … 0x0106fcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37463 … 0x010700UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37464 … 0x010704UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37465 … 0x010708UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37466 … 0x01070cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37467 … 0x010710UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37468 … 0x010714UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37469 … 0x010718UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37470 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37471 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37472 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37473 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37474 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37475 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37476 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37477 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37478 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37479 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37480 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37481 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37482 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37483 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37484 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37485 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37486 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37487 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37488 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37489 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37490 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37491 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37492 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37493 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37614 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37615 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37616 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37617 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37618 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37619 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37620 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37621 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37622 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37623 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37624 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37625 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37626 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37627 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37628 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37629 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37630 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37631 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37632 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37633 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37634 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37635 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37636 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37637 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37686 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37687 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37688 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37689 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37690 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37691 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37692 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37693 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37694 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37695 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37696 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37697 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37698 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37699 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37700 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37701 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37702 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37703 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37704 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37705 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37706 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37707 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37708 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37709 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37713 … 0x010968UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37714 … 0x01096cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37715 … 0x010970UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37718 …-1:32*trigger_indirect0_offseti[2:0]] in cycle trigger_indirect0_offseti[11:3] from the last messa…
37719 …-1:32*trigger_indirect0_offseti[2:0]] in cycle trigger_indirect0_offseti[11:3] from the last messa…
37720 …-1:32*trigger_indirect0_offseti[2:0]] in cycle trigger_indirect0_offseti[11:3] from the last messa…
37729 …-1:32*trigger_indirect1_offseti[2:0]] in cycle trigger_indirect1_offseti[11:3] from the last messa…
37730 …-1:32*trigger_indirect1_offseti[2:0]] in cycle trigger_indirect1_offseti[11:3] from the last messa…
37731 …-1:32*trigger_indirect1_offseti[2:0]] in cycle trigger_indirect1_offseti[11:3] from the last messa…
37739 …- Filter off; in that case all data should be transmitted to the internal buffer without any filte…
37740 … to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits…
37741 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37742 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37743 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37744 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37753 … 0x010a08UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37754 … 0x010a0cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37755 … 0x010a10UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37756 … 0x010a14UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37761 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37762 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37763 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37764 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37793 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37794 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37795 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37796 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37798 … 0x010a7cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37800 …cess:RW DataWidth:0x8 // The message length-1 of the recorded part size in terms of numbers o…
37801 …nt: (a) 00 - record from time=0; (b) 01 - record rcrd_on_window_pre_num_chunks chunks to internal…
37802 … (a) 0- enable recording data upon triggering event; in that case record for rcrd_on_window_post_…
37805 … 0x010a98UL //Access:RW DataWidth:0x10 // 16-bit opaque FID for pc…
37815 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37816 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37817 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37818 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37819 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37820 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37821 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37822 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37823 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37824 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37825 …- bits[31:0]; [5:3] - bits[63:32]; [8:6] - bits[95:64]; [11:9] - bits[127:96]; [14:12] - bits…
37826 …ll be added to trailer when STORM will be selected: B2:0 - TSEM; B5:3- MSEM; B8:6- USEM; B11:9- XS…
37835 …0x4 // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 M…
37836 … in granularity of chunks. The allowed range is 1-48 that suits to packet size of 256B-12KB. Value…
37840 …mestamp_tick value. It may be reset from RBC or set to any init value. This counter starts to coun…
37844 …tput from DBG to SEM block as result of trigger event: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is …
37845 … // Current state machine status of trigger block in dbg_trigger.v: states 0-2 are functional stat…
37846 …ock in dbg_trigger_state.v: : state 0 - NOT_HNDLR_MSG; state 1- FRST_HNDLR_MSG; state 2- SCND_HNDL…
37849 …- constraint 0 set0; B1 - constraint 1 set0; B2 - constraint 2 set0; B3 - constraint 3 set0; B4 - …
37851 …DataWidth:0x20 // Debug only: These bits represent the total number of 128-bit cycles sent from …
37855 … status in trailer block : 0 - WAIT_FOR_NEW_LINE; 1- END_OF_CHUNK; 2 - SEND_ADDITIONAL_CHUNK; 3 - …
37857 … // Statistics. Match constraint status. B0 - constraint 0; B1 - constraint 1; B2 - constraint …
37863 …1 // When set to 0 - only client which HW ID is defined in DBG_REGISTERS_FILTER_ID_NUM.FILTER_I…
37864 …ccess:RW DataWidth:0x1 // When 0 - SEMI core A is selected for all trigger/filter related act…
37878 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37884 …50Mhz Device will be using 50Mhz crytal, so defaults to a value of 4. Global Register, Reset on POR
37887 …ws it SW to override the setting based on register osc_e28_xcore_bias Global Register, Reset on POR
37888 … 0x02021cUL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
37890 …50Mhz Device will be using 50Mhz crytal, so defaults to a value of 1. Global Register, Reset on POR
37893 …allows it SW to override the setting based on register osc_e28_hipass Global Register, Reset on POR
37895 …0x020224UL //Access:RW DataWidth:0x3 // D2C Bias Current Control Global Register, Reset on POR
37898 … 0x020228UL //Access:RW DataWidth:0x1 // CML Current Control Global Register, Reset on POR
37901 …/ 50ohm Driver Current Control 00 = 5mA 01 = 10mA 10 = 15mA 11 = 20mA Global Register, Reset on POR
37904 … by 2 Selection for pad_op/n_cml output 0=XTAL Freq. 1=XTAL Freq. / 2 Global Register, Reset on POR
37907 …put Voltage Level Control 00 = 1.05V 01 = 1.00V 10 = 0.95V 11 = 0.90V Global Register, Reset on POR
37908 … 0x020238UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
37909 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37910 …:0] depends on i_resetb and i_cmos_en_ch[5:0] 1=o_xtal_ck[5:0] ALL ON Global Register, Reset on POR
37911 … 0x02023cUL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3)…
37912 … 0x02023cUL //Access:RW DataWidth:0x1 // pll reset signal
37913 …_xtal_ck2 Bit[3] = o_xtal_ck3 Bit[4] = o_xtal_ck4 Bit[5] = o_xtal_ck5 Global Register, Reset on POR
37916 …_p/n 0 Bit[1] = o_cml_p/n 1 Bit[2] = o_cml_p/n 2 Bit[3] = o_cml_p/n 3 Global Register, Reset on POR
37919 … (0x1<<0) // 0: pll reset disabled 1: pll reset enabled
37921 … (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of th…
37924 …:0x1 // 50ohm Driver Power Down 0=Driver ENABLED 1=Driver DISABLED Global Register, Reset on POR
37926 … (0x1<<0) // 0: post scaler reset disabled 1: post scaler reset ena…
37928 …(0x1<<4) // 1 : Override the init state machine and control the PLL logic reset using bit[0] of th…
37940 …= PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR
37944 … (0x1<<0) // 1 : Reset the VCO of the PLL. The reset is active high. Global …
37946 … (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of th…
37951 … (0x1<<0) // 1 : Reset the Post Divider of the PLL. The reset is active high. Gl…
37953 … (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of th…
37957 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
37960 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
37963 … // Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset.
37965 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37966 …-divider ratio for channel-0 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 1…
37967 … 0x020268UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
37968 …-divider ratio for channel-1 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 1…
37970 …-divider ratio for channel-2 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 1…
37973 …-divider ratio for channel-3 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 1…
37976 …-divider ratio for channel-4 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 1…
37979 …-divider ratio for channel-5 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 1…
37982 …W DataWidth:0x10 // Number to VCO clock to delay Channel 2 Global register. Reset on POR reset.
37985 …W DataWidth:0x10 // Number to VCO clock to delay Channel 3 Global register. Reset on POR reset.
37986 … 0x020284UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
37987 …W DataWidth:0x10 // Number to VCO clock to delay Channel 4 Global register. Reset on POR reset.
37988 … 0x020288UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3)…
37989 …W DataWidth:0x10 // Number to VCO clock to delay Channel 5 Global register. Reset on POR reset.
37991 … 0x02028cUL //Access:R DataWidth:0x4 // Delay for each channel 2-5 is completed.
37993 … (0x1<<0) // 0: pll reset disabled 1: pll reset enabled
37995 … (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of th…
37997 …L //Access:RW DataWidth:0x6 // Active Low Channel Enable. Global register. Reset on POR reset.
37999 … (0x1<<0) // 0: post scaler reset disabled 1: post scaler reset ena…
38001 …(0x1<<4) // 1 : Override the init state machine and control the PLL logic reset using bit[0] of th…
38003 …reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test …
38006 …reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test …
38008 … DataWidth:0x3 // Loop gain in frequency acquisition mode Global register. Reset on POR reset.
38010 …loop filter integrator path during fine phase acquisition mode Global register. Reset on POR reset.
38012 …rite 15 A default of 5 implies that the PLL sees a value of 3. Global register. Reset on POR reset.
38014 …h:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.
38016 …cUL //Access:R DataWidth:0xc // Status Bits from the PLL Global register. Reset on POR reset.
38018 …= PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR
38019 … 0x0202b4UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
38020 …202b4UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset is Active High
38022 …/Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset is Active High
38024 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38026 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
38028 … // Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset.
38030 …-divider ratio for channel-0 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 1…
38032 …-divider ratio for channel-1 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 1…
38033 … 0x0202d0UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
38034 …L //Access:RW DataWidth:0x6 // Active Low Channel Enable. Global register. Reset on POR reset.
38035 … 0x0202d4UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3)…
38036 …reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test …
38038 …reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test …
38039 … 0x020268UL //Access:RW DataWidth:0x1 // pll reset signal
38040 … 0x0202dcUL //Access:RW DataWidth:0x1 // 0: pll reset disabled 1: pll reset enabled
38041 … DataWidth:0x3 // Loop gain in frequency acquisition mode Global register. Reset on POR reset.
38042 …x0202e0UL //Access:RW DataWidth:0x1 // 0: post scaler reset disabled 1: post scaler reset ena…
38043 …loop filter integrator path during fine phase acquisition mode Global register. Reset on POR reset.
38044 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38045 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38046 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38047 …rite 15 A default of 5 implies that the PLL sees a value of 3. Global register. Reset on POR reset.
38048 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38049 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38050 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38051 …h:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.
38052 …2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is clea…
38053 …2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is clea…
38054 …2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is clea…
38055 …cUL //Access:R DataWidth:0xc // Status Bits from the PLL Global register. Reset on POR reset.
38058 …= PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR
38059 …aWidth:0x1 // reset of sgmii mdio registers. This is an active high reset. The name "rstb" is m…
38060 …aWidth:0x1 // reset of sgmii mdio registers. This is an active high reset. The name "rstb" is m…
38061 …202f4UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset is Active High
38065 …/Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset is Active High
38069 …uS interval. Main Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measuremen…
38073 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38077 …S interval. Storm Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measuremen…
38081 … 0000001111 = not usable 0000010000 = 16 ... 1111111111 = 1023 Global register. Reset on POR reset.
38084 …10uS interval. NW Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measuremen…
38088 …-divider ratio for channel-0 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by …
38089 … 0x0204b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38090 … 0x0202a8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38091 … 0x020308UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38092 …-divider ratio for channel-1 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by …
38093 … 0x0204b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38094 … 0x0202acUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38095 … 0x02030cUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38096 …L //Access:RW DataWidth:0x6 // Active Low Channel Enable. Global register. Reset on POR reset.
38097 … 0x0204bcUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38098 … 0x0202b0UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38099 … 0x020310UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38100 …Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset c…
38101 … 0x0204c0UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38102 … 0x0202b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38103 … 0x020314UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38104 …Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset c…
38105 … 0x0204c4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38106 … 0x0202b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38107 … 0x020318UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38108 …Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset c…
38109 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38110 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38111 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38112 …h:0x3 // Integrator gain control of the PLL digital filter. Global register. Reset on POR reset.
38116 …p filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset.
38117 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38118 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38119 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38120 … DataWidth:0x4 // Control of the non-zero pole in the PLL digital filter. Global register. Res…
38121 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38122 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38123 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38124 …h:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.
38128 …ccess:R DataWidth:0xc // Internal Status Bits of the PLL Global register. Reset on POR reset.
38129 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38130 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38131 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38132 …= PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR
38133 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38134 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38135 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38136 …20334UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset is Active High
38144 …/Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset is Active High
38152 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN go…
38156 … (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# g…
38174 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38204 … 0000001111 = not usable 0000010000 = 16 ... 1111111111 = 1023 Global register. Reset on POR reset.
38212 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN go…
38216 … (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# g…
38234 …-divider ratio for channel-0 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by …
38242 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN go…
38246 … (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# g…
38264 …-divider ratio for channel-1 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by …
38268 …-bit compliance enable pins on the ballout. These bits are used to override the pins if needed. 2'…
38272 …L //Access:RW DataWidth:0x6 // Active Low Channel Enable. Global register. Reset on POR reset.
38273 …ss:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_contro…
38274 …ss:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_contro…
38275 …Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset c…
38278 …Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset c…
38279 …am bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist…
38280 …am bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist…
38281 …Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset c…
38282 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38283 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38284 …h:0x3 // Integrator gain control of the PLL digital filter. Global register. Reset on POR reset.
38285 …- bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - re…
38286 …- bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - re…
38287 …p filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset.
38288 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38289 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38290 … DataWidth:0x4 // Control of the non-zero pole in the PLL digital filter. Global register. Res…
38291 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38292 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38293 …h:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.
38294 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38295 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38296 …ccess:R DataWidth:0xc // Internal Status Bits of the PLL Global register. Reset on POR reset.
38297 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38298 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38300 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38301 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38303 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38304 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38306 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38307 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38309 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38310 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38312 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38313 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38315 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38316 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38318 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38319 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38321 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38322 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38324 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38325 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38327 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38328 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38329 … 0x020398UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38330 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38331 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38332 … 0x02039cUL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38362 … 0x0203c4UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38363 …ess:RW DataWidth:0x6 // Sets the CTL# (# in [0..5]) I/Os of the PADS in non - scan/mbist modes
38365 … 0x0203c8UL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38366 …cess:RW DataWidth:0x2 // Sets the SL# (# in [0..1]) I/Os of the PADS in non - scan/mbist modes
38368 … 0x0203ccUL //Access:R DataWidth:0x8 // PCIe lock signals. 0-unlocked; 1-locked. Global …
38372 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38373 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38377 … (0x1<<0) // 1 : Reset the entire SGMII Core. Global Register, R…
38379 … (0x1<<1) // 1 : Reset the MDIO Registers. Global Register, Res…
38381 … (0x1<<2) // 1 : Resets the PLL and digital logic.. Global Register, Reset on POR
38383 … 0x0203e0UL //Access:RW DataWidth:0x5 // Device Address Global Register, Reset on POR
38384 … 0x0203e4UL //Access:RW DataWidth:0x1 // 0 : CL22 1 : CL45 Global Register, Reset on POR
38385 …UL //Access:RW DataWidth:0x5 // PHY Address for MDIO Transaction Global Register, Reset on POR
38386 …front end and turns off all clocks except refclk. MDIO is operational Global Register, Reset on POR
38387 … powers down analog and turns off all clocks. MDIO is not operational Global Register, Reset on POR
38388 … 0x0203f4UL //Access:RW DataWidth:0x3 // TBD. Global Register, Reset on POR
38390 … (0x1<<0) // Link Status 1: Link has been achieve Global Register, Reset on POR
38392 … (0x1<<1) // Signal Detect Global Register, Reset on POR
38394 … (0x1<<2) // 1: Bit Alignment Done Global Register, Reset on POR
38396 … (0x1<<3) // 1: Symbol Alignment Global Register, Reset on POR
38398 … (0x1<<4) // 1: Speed is 10M Global Register, Reset on POR
38400 … (0x1<<5) // 1: Speed is 100M Global Register, Reset on POR
38402 … (0x1<<6) // 1: Speed is 1G Global Register, Reset on POR
38404 … (0x1<<8) // 1: PLL is locked Global Register, Reset on POR
38406 … (0x1<<12) // 1: Running in SGMII mode. Global Register, Reset on POR
38410 … (0x1<<0) // 1 : Reset the VTMON register…
38414 … Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the value forever. Global register. …
38415 …ss:R DataWidth:0xa // Voltage/Temperature Monitor output.Global register. Reset on POR reset.
38418 … (0x1<<0) // 1 : Reset the VTMON register…
38422 … Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the value forever. Global register. …
38423 …ss:R DataWidth:0xa // Voltage/Temperature Monitor output.Global register. Reset on POR reset.
38424 … Mode 1: Powerdown the RESCAL block Transition from 1->0 to start calibration Global Register, Res…
38425 …ss:RW DataWidth:0x1 // Reset the RESCAL block 0: Normal Operation Mode 1: Reset the RESCAL bl…
38426 …tpulates the pwrdn and reset signals to start its own calibration. 0: Normal Operation Mode 1: FW …
38427 …the rescal block. 0: Normal Operation Mode 1: Restart the calibration Global Register, Reset on POR
38428 …:0x1 // 0: Normal Operation Mode 1: Freeze Internal Digital ciruit Global Register, Reset on POR
38429 …-up time before starting calibration 2'b00: 32 refclk = 1.28us 2'b01: 128 refclk = 5.12us 2'b10: 2…
38431 …ion operation is done. 0: Calibration in progress 1: Calibration Done Global Register, Reset on POR
38433 …a is valid when calib_done is set 0: Data is invalid 1: Data is valid Global Register, Reset on POR
38435 …-chip Sheet Resistance 0000 -24% ~ -21% 0001 -21% ~ -18% 0010 -18% ~ -15% 0011 -15% ~ -12% 0100 -1…
38436 …R DataWidth:0x6 // accumulated comparison for current pon value Global Register, Reset on POR
38437 … DataWidth:0x4 // accumulated comparison for previous pon value Global Register, Reset on POR
38438 … 0x020444UL //Access:R DataWidth:0x1 // RESCAL Comp Value Global Register, Reset on POR
38439 … DataWidth:0xd // default values for the rescal control signals. Global Register, Reset on POR
38440 … status 0: INIT 1: WAIT_PWRUP 2: COMP_ACC 3: WAIT_PON_INC 4: CAL_DONE Global Register, Reset on POR
38441 …tate machine status 0: POR 1: INIT 2: RESET 3: PWRDN 4: CALIB 5: PONVALID 6: RESULT 7: IDLE Global…
38442 …ching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR
38443 … // Reset the Registers in VManagement Switching Regulator 0: Normal Operation Mode 1: Reset the…
38444 … 0x02045cUL //Access:R DataWidth:0x1 // 1: PMU is stable Global Register, Reset on POR
38445 …ching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR
38446 …x1 // Reset the Registers in VMain Switching Regulator 0: Normal Operation Mode 1: Reset the sw…
38447 … 0x020468UL //Access:R DataWidth:0x1 // 1: PMU is stable Global Register, Reset on POR
38448 …ching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR
38449 …1 // Reset the Registers in VAnalog Switching Regulator 0: Normal Operation Mode 1: Reset the s…
38450 … 0x020474UL //Access:R DataWidth:0x1 // 1: PMU is stable Global Register, Reset on POR
38451 …ching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR
38452 …0x1 // Reset the Registers in V1p8 Switching Regulator 0: Normal Operation Mode 1: Reset the sw…
38453 … 0x020480UL //Access:R DataWidth:0x1 // 1: PMU is stable Global Register, Reset on POR
38454 …verall power consumption. 1: Select 1Mhz Clock 0: Select 500Khz Clock Global Register, Reset on POR
38455 …able the phase shift logic betweent the three swreg to start working. Global Register, Reset on POR
38456 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38457 …2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is clea…
38458 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38460 …10uS interval. NW Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measuremen…
38464 … 0x0204e8UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38465 … 0x0204ecUL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38466 … 0x0204f0UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38467 … 0x0204f4UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38468 … 0x0204f8UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38469 … 0x0204fcUL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38470 … 0x020500UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38471 … 0x020504UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38475 …erential oscillator 1= CML reference clock, from the chip pins Global register. Reset on POR reset.
39263 … (0x1<<2) // 0 -> Send all broadcast packets to the appropriate networ…
39265 … (0x1<<3) // 0 -> Send all multicast packets to the appropriate networ…
39267 … (0x1<<4) // 0 -> only MAC address is used for comparison to detect Host2B…
39269 … (0x1<<5) // 0 -> Do not enable source MAC address learning for packets from…
39271 … (0x1<<6) // 0 -> Entries in SA Learning Cache are valid even after they…
39279 … (0x1<<10) // 0 -> Select NCSI RMII interface as the MII port …
39281 … (0x1<<11) // 0 -> Select NCSI RMII interface as the Management Po…
39283 … (0x1<<12) // 1 -> When BMB asserts any full condition, drop all the p…
39285 … (0x1<<13) // 1 -> When this bit is set, all pass through traffic will be directed to hos…
39370 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39372 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39374 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39376 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39378 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39380 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39382 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39384 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39422 … (0x3f<<1) // NCSI block has the capability to remove up-to six TAGs present i…
39424 …-> Use the configuration bit associated with the Inner VLAN tag to decide whether to remove the ta…
39426 …from the packet before sending it out to BMC. it is expected that once a non-zero value is set, al…
39438 …criptor for a BMC to Network packet if there is a VLAN header in the packet and VLAN ID is non-zero
39451 …to '1' causes the hardware arbitration scheme to begin. Any NCSI port can re-start the arbitration.
39457 … (0x1f<<8) // This field is a programmable inter-packet gap for when t…
39465 …mber of Ingress clock cycles that the arbitration master will wait before re-starting the arbitrat…
39470 … (0x1<<0) // Setting this bit will create an asychronous reset to the egress logi…
39472 … (0x1<<1) // Setting this bit will create an asychronous reset to the ingress log…
39484 …started. Setting a value of all 1s in this register will guarantee a store-and-forward operation. …
39507 … 0x050000UL //Access:RW DataWidth:0x1 // Reset the protection ove…
39510 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39511 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39513 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39514 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39516 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39517 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39519 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39525 …masked, access with the PF is not written to the trace FIFO. BB: only bits 0-7 are applicable. The…
39527 …L = 1. Value of all 1s is applicable and represents VF not valid. BB: only bits 0-6 are applicable.
39528 …sked, access with the port is not written to the trace FIFO. BB: only bits 0-1 are applicable. The…
39530 …_OV. Over-ride to VN PROTECTION. Bit [5]: PDA_OV. Over-ride to PDA PROTECTION. Bit [6]: HV_OV. Ove…
39611 …et to '1'; otherwise transmit to PHY is disabled (normal operation); when set to '0' (Reset value).
39613 …et to '1'; otherwise transmit to PHY is disabled (normal operation); when set to '0' (Reset value).
39615 …ed internally are allowed if ignore_tx_pause is not set. When set to '0' (Reset value); the MAC tr…
39617 … (0x1<<1) // Enable/Disable MAC receive path. When set to '0' (Reset value); the MAC re…
39623 …ame before it is transmitted to the user application. If disabled (set to reset value '0'); then n…
39625 …eived frames are transmitted to the user application. If disabled (Set to reset value '0') the CRC…
39627 …) pause frames are forwarded to the user application. If disabled (Set to reset value '0'); pause …
39629 … '1') received pause frames are ignored by the MAC. When disabled (Set to reset value '0') the tra…
39631 … programmed MAC address in registers MAC_0 and MAC_1. If disabled (Set to reset value '0'); the so…
39639 …tware Reset Command. When asserted; the TX and RX are disabled. Config registers are not affected …
39641 …) // Corrupt Tx FCS; on underrun; when set to '1'; No FCS corruption when set to '0' (Reset value).
39643 …1<<15) // Enable GMII/MII loopback when set to '1'; normal operation when set to '0' (Reset value).
39645 …et to '1'; otherwise transmit to PHY is disabled (normal operation); when set to '0' (Reset value).
39653 … (0x1<<22) // Enable Configuration with External Pins. When set to '0' (Reset value) the Core sp…
39655 …0x0001 are accepted and forward to the Client interface. When set to '0' (Reset value); MAC Contro…
39657 … frame's payload length with the Frame Length/Type field; when set to '1'(Reset value); the payloa…
39659 …pback i.e. MAC FIFO side loopback; when set to '1'; normal operation when set to '0' (Reset value).
39667 …-of-band egress flow control is enabled. When this bit is set and input pin ext_tx_flow_control is…
39673 … 0x051014UL //Access:RW DataWidth:0x10 // Defines a 16-Bit maximum frame len…
39674 … 0x051018UL //Access:RW DataWidth:0x10 // 16-Bit value; sets; in i…
39709 …G between Back-to-Back packets. This is the IPG parameter used exclusively in Full-Duplex mode whe…
39710 …dth:0x10 // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
39712 …s idle. The rx_lpi_detect assertion is independent of this configuration. Reset default depends on…
39722 …the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register…
39723 …the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register…
39727 …tate when it receives packet for transmission. The decrement unit is 1 micro-second. This register…
39728 …tate when it receives packet for transmission. The decrement unit is 1 micro-second. This register…
39737 … (0x7f<<16) // Non Back-to-Back Transmit IPG pa…
39739 … (0x7f<<24) // Non Back-to-Back Transmit IPG pa…
39790 …ss:RW DataWidth:0x20 // This register contains the bits [31:0] in the 48-bit MAC address. The…
39792 …L_BB (0x1<<0) // Read-only field assertion …
39794 …TY_BB (0x1<<1) // Read-only field assertion …
39798 …s:RW DataWidth:0x10 // This register contains the bits [47:32] in the 48-bit MAC address. The…
39815 …- skipped (unsupported) 1 - stackvlan (unsupported) 2 - carrerr (on by default) 3 - codeerr (on by…
39817 … 0x051338UL //Access:RW DataWidth:0x8 // probe address bit 7 - U/L bit 6 - GMII/XMGII CLK…
39819 … (0x1<<0) // RXFIFO Underrun occurred. Cleared by only reset.
39821 … (0x1<<1) // RXFIFO Overrun occurred. Cleared by only reset.
39825 … (0x1<<0) // TXFIFO Underrun occurred. Cleared by only reset.
39827 … (0x1<<1) // TXFIFO Overrun occurred. Cleared by only reset.
39830 … (0x1<<0) // Enables the PPP-Tx functionality.
39832 … (0x1<<1) // Enables the PPP-Rx functionality.
40056 … DORQ FIFO. When the occupancy is more than that number, local edpm_en is de-asserted. It is than …
40221 … (0xffff<<4) // Minimum Wake Falling Edge Delay(this reset value is a count v…
40224 … (0xffff<<0) // Minimum Wake Pulse Width (this reset value is a count v…
40226 … (0xffff<<16) // Maximum Wake Pulse Width (this reset value is a count v…
40268 …ataWidth:0x1 // Driven low by your application after cold, warm or hot reset to hold the LTSSM …
40272 … (0x1<<1) // When set to 1, HW delay asserting internal reset to allow FW access…
40342 …MSG_UNLOCK_K2_E5 (0x1<<16) // One-cycle pulse that indi…
40344 …TURNOFF_K2_E5 (0x1<<17) // One-clock-cycle pulse that i…
40349 … to wake up the PMC state machine from a D1, D2 or D3 power state. Upon wake-up, the core sends a …
40368 … (0xffff<<0) // This is the value of the No Soft Reset bit in the Power M…
40415 … 0x054328UL //Access:R DataWidth:0x5 // pm_dev_num[4:0]- Device number
40416 … 0x05432cUL //Access:R DataWidth:0x8 // pm_bus_num[7:0]- Bus Number
40462 …CT_K2_E5 (0x1<<5) // Early Hot Reset detected.
40464 …CT_K2_E5 (0x1<<6) // Hot Reset detected.
40472 … (0x1<<10) // Do not use -- keep mask bit set to…
40478 … (0x1<<13) // Non-Fatal Error Message s…
40484 … (0x1<<16) // Vendor-Defined Message recei…
40532 …ETECT_K2_E5 (0x1<<5) // Early Hot Reset detected.
40534 …ETECT_K2_E5 (0x1<<6) // Hot Reset detected.
40542 … (0x1<<10) // Do not use -- keep mask bit set to…
40548 …E5 (0x1<<13) // Non-Fatal Error Message s…
40554 … (0x1<<16) // Vendor-Defined Message recei…
40567 …DETECT_K2_E5 (0x1<<5) // Early Hot Reset detected.
40569 …DETECT_K2_E5 (0x1<<6) // Hot Reset detected.
40577 … (0x1<<10) // Do not use -- keep mask bit set to…
40583 …_E5 (0x1<<13) // Non-Fatal Error Message s…
40589 … (0x1<<16) // Vendor-Defined Message recei…
40608 …_E5 (0x1<<0) // Power-on reset occurred.
40610 …_2_K2_E5 (0x1<<1) // Wake Ref reset occurred.
40612 …_2_K2_E5 (0x1<<2) // Phy reset occurred.
40614 …_2_K2_E5 (0x1<<3) // Squelch reset occurred.
40616 … (0x1<<4) // Sticky register reset occurred.
40618 … (0x1<<5) // Non-sticky register reset occurred.
40620 …_2_K2_E5 (0x1<<6) // Core reset occurred.
40622 …_2_K2_E5 (0x1<<7) // PIPE reset occurred.
40640 …(0x1<<16) // Soft power-on reset occurred. NOTE: This bit is unreliable for indication of a soft p…
40642 …2_K2_E5 (0x1<<17) // Soft Wake Ref reset occurred.
40644 …2_K2_E5 (0x1<<18) // Soft phy reset occurred.
40646 …2_K2_E5 (0x1<<19) // Soft squelch reset occurred.
40648 … (0x1<<20) // Soft sticky register reset occurred.
40650 … (0x1<<21) // Soft non-sticky register reset occurred.
40652 …2_K2_E5 (0x1<<22) // Soft core reset occurred.
40654 …2_K2_E5 (0x1<<23) // Soft PIPE reset occurred.
40656 … 0x054804UL //Access:RW DataWidth:0x18 // Corresponding bits of Reset Status Register 2 …
40718 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
40719 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
40737 … (0x1<<8) // CFC load request FIFO under-run
40741 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40787 …RR (0x1<<8) // CFC load request FIFO under-run
40791 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40812 …ERR (0x1<<8) // CFC load request FIFO under-run
40816 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40880 …2 // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 me…
40881 …2 // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 me…
40888 … //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS = 1. Reset value = SET_AG_CMD.
40891 … //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS = 2. Reset value = SET_AG_CMD.
40894 … //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS = 3. Reset value = SET_AG_CMD.
40897 … //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS = 4. Reset value = SET_AG_CMD.
40900 … //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS = 5. Reset value = SET_AG_CMD.
40903 … //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS = 6. Reset value = SET_AG_CMD.
40906 … //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS = 7. Reset value = SET_AG_CMD.
40907 … 0x1004f4UL //Access:RW DataWidth:0x2 // AGG command value in PWM non-DPM mode.
40910 …n 2 port mode it is equal to 0 for all PF-s. In 4 port mode, it is equal to 0 for even PF-s and to…
40915 …ccess:RW DataWidth:0x1 // Enable DPM doorbells for all this PF child VF-s. In case not set th…
40929 … 0x100810UL //Access:RW DataWidth:0x1 // If set then CCFC mini-cache is enabled.
40931 …and first DPM doorbell appears it is truncated to one entry and aborted; non-first doorbell is dro…
40932 … doorbell appears it is truncated to one entry and DpmAbort flag is set; non-first doorbell is sil…
40946 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40947 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40948 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40949 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40952 … // Enable bit per each RoCE Opcode 5 LSB-s. N-th bit set means corresponding opcode N is enable…
40953 …Access:RW DataWidth:0x1 // If 0 - the RoCE CRC-32 final calculation result isn't byte swapped…
40969 … 0x100918UL //Access:RW DataWidth:0x2 // TPH Hint value in case of non-inline L2 EDPM.
40970 … 0x10091cUL //Access:RW DataWidth:0x3 // ATC attribute value of non-inline L2 EDPM.
40972 … 0x100924UL //Access:RW DataWidth:0xe // Maximum non-inline L2 EDPM PktSiz…
40973 … 0x100928UL //Access:RW DataWidth:0x8 // The maximum number of WORD-s which the PBF may a…
40980 …DataWidth:0xb // Counter of DORQ FIFO entries used by corresponding PF or any of its child VF-s.
40982 … number of DORQ FIFO entries used by corresponding PF or any of its child VF-s. This is a per PF c…
40992 …de is active and all doorbells are dropped at the entrance to DORQ FIFO. De-asserted when auto_di…
40995 … 0x1009fcUL //Access:R DataWidth:0x20 // Accounts for any non-DPM doorbell or first…
41003 …0 // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_deta…
41004 …-armed by db_drop_details_rel. The following details of the transaction will be recorded: Doorbell…
41005 …7 // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_deta…
41007 …reset on write to db_drop_details_rel. 0 - Size of the data is not equal to 4 or to a multiple of …
41009 …ails of the first aborted doorbell after this register was cleared. It is reset on write to db_abo…
41010 …ails of the first aborted doorbell after this register was cleared. It is reset on write to db_abo…
41011 …ails of the first aborted doorbell after this register was cleared. It is reset on write to db_abo…
41012 …ails of the first aborted doorbell after this register was cleared. It is reset on write to db_abo…
41013 …reset on write to db_abort_details_rel. The following details of the transaction will be recorded:…
41015 …reset on write to db_abort_details_rel. 0 - DPM doorbell and rewind configuration of DPM timer (dp…
41016 … 0x100a50UL //Access:RC DataWidth:0x20 // Truncation counter. It is reset on read.
41017 … 0x100a54UL //Access:RC DataWidth:0x20 // DPM early abort counter. It is reset on read.
41018 …100a58UL //Access:RC DataWidth:0x20 // DPM timer expiration abort counter. It is reset on read.
41019 …Width:0x20 // DPM global condition abort counter for External EDPM doorbell. It is reset on read.
41020 …:0x20 // DPM context check failure abort counter for External EDPM doorbell. It is reset on read.
41021 … first on a CID which already has a DPM entry pending for data) abort counter. It is reset on read.
41022 …20 // DPM Illegal value of DpmSize, WqeSize/PktSize or SgeNum abort counter. It is reset on read.
41023 … //Access:RC DataWidth:0x20 // Number of successfull legacy DPM doorbells. It is reset on read.
41024 …L //Access:RC DataWidth:0x20 // Number of successfull RoCE EDPM doorbells. It is reset on read.
41025 …4UL //Access:RC DataWidth:0x20 // Number of successfull L2 EDPM doorbells. It is reset on read.
41027 … be done at first cycle of first DPM doorbell by the size of DpmSize. No non-first DPM doorbells s…
41029 …selected size can be a number which is a power of 2 which is between 4 to 256. It is reset on read.
41032 …ue of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Re…
41034 …-cache was used. 36 - CDU Validation Error; 35 - CFC Load Cancel; 34 - CFC Load Error; 33 - CFC LC…
41039 …Width:0x1 // comment="Selects IEDPM payload endianity. 0 - little endian (lsB first); 1 - big e…
41053 …- DPM FSM state [194:192] - DbAggValSel [191:190] - DbAggCmd [189:182] - DbAggFlgCmd [181] - IEDPM…
41087 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41088 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41089 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41090 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41091 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41092 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41093 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41094 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41095 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41096 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41097 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41098 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41099 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41100 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41101 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41102 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41364 …Access:RW DataWidth:0x1 // If 0 - the iWARP CRC-32 final calculation result isn't byte swappe…
41365 … // Enable bit per each iWARP Opcode 5 LSB-s. N-th bit set means corresponding opcode N is enable…
41380 …reset on write to db_abort_details_rel. The following details of the transaction will be recorded:…
41381 …f the first aborted IEDPM doorbell after this register was cleared. It is reset on write to db_abo…
41382 …f the first aborted IEDPM doorbell after this register was cleared. It is reset on write to db_abo…
41383 …f the first aborted IEDPM doorbell after this register was cleared. It is reset on write to db_abo…
41384 …f the first aborted IEDPM doorbell after this register was cleared. It is reset on write to db_abo…
41385 …reset on write to db_abort_details_rel. The following details of the transaction will be recorded:…
41387 …reset on write to db_abort_details_rel. 0 - First DPM doorbell does not match DPM global start con…
41388 …-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: IEDPM…
41389 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41390 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41391 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41392 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41394 …reset on write to iedpm_drop_details_rel. 4 - First QWord (offset 0) arives on IEDPM buffer which …
41396 …dth:0x20 // IEDPM global condition abort counter for Internal EDPM doorbell. It is reset on read.
41397 …x20 // IEDPM context check failure abort counter for Internal EDPM doorbell. It is reset on read.
41398 … // IEDPM timer expiration failure abort counter for Internal EDPM doorbell. It is reset on read.
41399 … DataWidth:0x20 // Accounts for number of Internal EDPM doorbells arrived. It is reset on read.
41457 … //Access:RC DataWidth:0x20 // Number of successfull iWARP EDPM doorbells. It is reset on read.
41458 … //Access:RC DataWidth:0x20 // Number of successfull iWARP EDPM doorbells. It is reset on read.
41461 …reset finished the appropriate bit is cleared. Bit 0 - mapping memory; Bit 1 - SB memory (producer…
41463 …// If enabled the IGU forwards write/read requests to the TPH interface. 1 - enabled; 0 - disabled.
41465 …ed the IGU allows to VF to send cleanup commands on the int ack address. 1 - enabled; 0 - disabled.
41467 …the IGU allows bypass mode of the rate limiter when the system is empty. 1 - enabled; 0 - disabled.
41473 … 0x18006cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
41761 …r of MSI/MSIX/ATTN messages sent for the PF: address 0 - number of MSI/MSIX messages; address 1 - …
41771 …Debug: count the number of PXP requests sent on behalf of a specific MSI/MSI-X vector on the SB in…
41785 … 0x180600UL //Access:RW DataWidth:0x14 // IPS statistics - number of messages s…
41787 …- function enable; b1 - MSI/MSIX enable; b2 - INT enable; b3 - attention enable; b4 - single ISR m…
41788 …h:0x9 // d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enabl…
41816 …th:0x1 // PF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41818 …th:0x1 // VF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41829 …idth:0x20 // [15:0] - function number: opaque fid. [28:16] - PXP BAR address; [30:29] - Reserved…
41831 … DataWidth:0x20 // Address 0 - MSI address low (two Lsbit are zero). Address 1 - MSI address hig…
41834 …g is enabled, the match address of the hit response is used to perform a two-cycle …
41836 … read of the entire CAM will be started (or re-started). This will e…
41838 … 0x180864UL //Access:RW DataWidth:0x1 // Enable the RL statistic. 0 - disabled; 1 - enabled.
41868 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41869 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41870 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41871 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41872 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41873 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41874 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41875 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41876 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41877 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41878 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41879 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41880 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41881 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41882 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41883 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41884 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41885 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41886 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41887 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41888 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41889 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41890 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41891 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41892 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41893 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41894 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41895 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41896 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41897 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41899 …UL //Access:RW DataWidth:0x20 // SB interrupt before mask. 0 - prod equal cons. 1 - prod not e…
41901 …UL //Access:RW DataWidth:0x20 // SB interrupt before mask. 0 - prod equal cons. 1 - prod not e…
41902 …UL //Access:RW DataWidth:0x20 // SB interrupt before mask. 0 - prod equal cons. 1 - prod not e…
41903 … 0x180ce0UL //Access:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The b…
41905 … 0x180d00UL //Access:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The b…
41906 … 0x180d04UL //Access:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The b…
41907 … 0x180d20UL //Access:RW DataWidth:0x20 // PBA register. 0 - PBA clear, 1 - PBA set - the appr…
41909 … 0x180d40UL //Access:RW DataWidth:0x20 // PBA register. 0 - PBA clear, 1 - PBA set - the appr…
41910 … 0x180d44UL //Access:RW DataWidth:0x20 // PBA register. 0 - PBA clear, 1 - PBA set - the appr…
41911 …d - sets the max value that the rate_counter can reach; [19:10] tick_interval - define the max int…
41913 …- receives the tick_interval value when reaching zero; or when writing to the tick_interval. The t…
41923 …er - incremented by one when Tick_value reaches zero and decremented whenever a message from that …
41926 …the previous write (or in the reset value) as set. Each write should be followed by a read. For ex…
41927 …Tph field for attention message. Bits 8:0 - steering tag; bits 12:9 - reserved; bits 14:13 - st hi…
41928 …miter group enable status bit for groups 0-31. For each bit: 0 - the rate limiter of the group is …
41929 …iter group enable status bit for groups 32-63. For each bit: 0 - the rate limiter of the group is …
41930 …/ Rate Limiter group credit status bit for groups 0-31. For each bit: 0 - the group has no credit.…
41931 … Rate Limiter group credit status bit for groups 32-63. For each bit: 0 - the group has no credit.…
41932 …imiter group pending status bit for groups 0-31. For each bit: 0 - there are no pending SB in that…
41933 …miter group pending status bit for groups 32-63. For each bit: 0 - there are no pending SB in that…
41934 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port0.
41935 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port1.
41936 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port2.
41937 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port3.
41939 …L //Access:R DataWidth:0x5 // Debug: [4] - attention write done message is pending (0-no pen…
41940 …518UL //Access:RW DataWidth:0x1 // Debug only: 0 - FIFO collects 64 first error messages; 1 -…
41942 …- fid ([8] - if set - PF; else VF, [7:0] - FID). [12:9] - source (values 0-7 according to PXP sour…
41966 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 0; [7:0] = VF number; if PF - [8…
41978 …- MSIX read/write; Bit [1] - PBA read/write; Bit [2] - Producer update (or cleanup command through…
41993 … DataWidth:0x18 // Producers only. Address 0-511 match to the mapping memory. Address 512-227:…
41997 …W DataWidth:0x18 // Consumers only. Address 0-511 match to the mapping memory. Address 512-227…
42001 …- valid. [8:1] - vector number (0-128 for PF; 0-63 for VF). [17:9] - FID (if VF: [17] = 0; [16:9] …
42005 …/ [63:0] - MSIX message address (bit [1:0] are always zero); [95:64] - MSIX message data; [96] - M…
42244 …05 related) When set, bypass can be implemented (i.e. bug not fixed) When reset, bypass cannot be …
42245 … number of outstanding write requests without receiving write done. Values 1-128. Zero is not a va…
42246 …reset the whole memory. When the memory reset finished the appropriate bit will be clear. [0] - PI…
42247 …p on the written SB number. [8:0] - SB absolute index; [9] - Cleanup set/clr (0-clr; 1 - set); [12…
42251 … 0x1c0600UL //Access:RW DataWidth:0x1 // Indicate the size of the CQE. 0 - 32B; 1 - 64B.
42252 …W DataWidth:0x2 // Indicate the size of the AGG unit. 0 - 64B; 1 - 128B; 2 - 256B; 3 - illega…
42253 … 0x1c0608UL //Access:RW DataWidth:0x1 // Flush all command - will flush all the C…
42255 …should keep one of the bits that are set in the previous write (or in the reset value) as set. Eac…
42256 …the previous write (or in the reset value) as set. Each write should be followed by a read. For ex…
42260 … 0x1c0780UL //Access:R DataWidth:0x20 // Rx timers status. 0 - inactive 1 - active.
42262 … 0x1c0800UL //Access:R DataWidth:0x20 // Tx timers status. 0 - inactive 1 - active.
42266 … 0x1c0980UL //Access:R DataWidth:0x1 // Debug: IGU-CAU request interface…
42267 … 0x1c0984UL //Access:R DataWidth:0x1 // Debug: IGU-CAU command interface…
42293 … timer command type. One bit for each timer command type: [0] - rewind; [1] - clear; [2] - rewind …
42311 …- FIFO empty; 1 - FIFO not empty. [0] - PXP command FIFO; [1] - reserved; [2] - timers expiration …
42312 …- error typ (1- read request; 2 - reserved; 3 - sb_index >= CAU_NUM_SB or SB index > CAU_NUM_PI/n…
42313 …- source (0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM)…
42314 … // Debug; [9] if set data valid; [8] previous FSM_sel; [7:4] - previous state; [3:0] - previous…
42315 …: If set a parity occurd and the CAU assert discard flag to the IGU from now on (until hard reset).
42316 …h:0x19 // comment="Debug: [15:0] The PF that caused the error- one bit per PF; [24:16] - SB inde…
42318 …e was writing to agg_units_state_read_en register. (i =0-15). 0 - free; 1 - dirty; 2 - clean; 3 - …
42319 …was writing to agg_units_state_read_en register. (i = 16-31). 0 - free; 1 - dirty; 2 - clean; 3 - …
42320 …was writing to agg_units_state_read_en register. (i = 32-47). 0 - free; 1 - dirty; 2 - clean; 3 - …
42321 …was writing to agg_units_state_read_en register. (i = 48-63). 0 - free; 1 - dirty; 2 - clean; 3 - …
42334 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 1; [7:0] = VF number; if PF - [8…
42346 … (0x7<<0) // Debug: command type for the debug. [0] - PI producer update; [1] - cleanup; [2] - …
42365 … 0x1c0f0cUL //Access:R DataWidth:0x5 // Debug: FSM state for debug.Idle state value are 0-2
42367 … 0x1c2000UL //Access:WB_R DataWidth:0x80 // Debug: Provides read-only access of the CQ…
42369 … 0x1c2200UL //Access:WB_R DataWidth:0x35 // Debug: Provides read-only access of the IG…
42371 … 0x1c2300UL //Access:WB_R DataWidth:0x62 // Debug: Provides read-only access of the PX…
42373 …2400UL //Access:WB_R DataWidth:0x84 // Debug: Provides read-only access of the PXP write-data FI…
42375 … and PI relative number of each aggregation unit. [0] - valid; [9:1] - absolute SB index; [14:10] …
42377 …- next state; [5:4] - timer cmd (0 - None; 1 - Rewind; 2 - Clear; 3 - Rewind to shorter); [6] - SB…
42379 …-2 only); [49:48] TimerRes1 (This value will determine the TX FSM timer resolution in ticks. Valid…
42387 …ry.[15:0] - protocol producer; [22:16] - PiTimeSet (This value determines the TimeSet that the PI …
42394 …- address; [71:64] - valid slots; [84:72] - FID ([13:9] - PF number (in case of VF the parent PF);…
42396 …h:0x18 // The SB timers. For each SB there are two timers: [11:0] - RX timer; [23:12] - TX timer.
42400 … 0x1f0000UL //Access:RW DataWidth:0x1 // Soft reset - reset all FSM.
42401 …UL //Access:W DataWidth:0x1 // Any write to this register triggers MAC-VLAN Cache initializa…
42408 … (0x1<<1) // Load Request Mini-cache validation error
42418 … (0x1<<1) // Load Request Mini-cache validation error
42423 … (0x1<<1) // Load Request Mini-cache validation error
42432 …0168UL //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a PF packet, task-…
42433 …016cUL //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a VF packet, task-…
42434 …0170UL //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a PF packet, task-…
42435 …0174UL //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a VF packet, task-…
42442 … 0x1f0190UL //Access:RW DataWidth:0x1 // Per-PF: If set, override …
42443 … 0x1f0194UL //Access:RW DataWidth:0x20 // Per-opcode requester/resp…
42444 … 0x1f0198UL //Access:RW DataWidth:0x1 // Per-PF: If set, a load re…
42445 … 0x1f019cUL //Access:RW DataWidth:0x1 // If set, CFC load mini-cache is enabled.
42446 … 0x1f01a0UL //Access:RW DataWidth:0x1 // 0-search response initiator type,1-Excha…
42447 … 0x1f01a4UL //Access:RW DataWidth:0x1 // 0-Exchange Context field in the fcoe search req is z…
42803 … 0x1f0400UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42804 … 0x1f0404UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42805 … 0x1f0408UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42806 … 0x1f040cUL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42838 … 0x1f041cUL //Access:RW DataWidth:0x1 // Per-PF: If set, search re…
42839 … 0x1f0420UL //Access:RW DataWidth:0x1 // Per-PF: Enables VF_ID (if…
42840 … 0x1f0424UL //Access:RW DataWidth:0x1 // Per-PF: Enables load requ…
42842 … 0x1f042cUL //Access:RW DataWidth:0x11 // Per-PF: Max value for tem…
42843 … 0x1f0430UL //Access:RW DataWidth:0x11 // Per-PF: Max value for tem…
42844 … 0x1f0434UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow …
42845 … 0x1f0438UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow search for non-IP …
42846 … 0x1f043cUL //Access:RW DataWidth:0x1 // Per-PF: If this field is 1, Over-IPv4-prot…
42888 … // Per-PF: Indicates whether to include the Inner VLAN in the search for each protocol. 0 - TC…
42889 … // Per-PF: Indicates whether to include the Outer TAG in the search for each protocol. 0 - TCP…
42890 …-PF: Indicates whether to include Tenant ID (if it exists) in the search for each encapsulation ty…
42891 …o be 0 if the ID matches the default value. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 …
42895 …nant ID used in the search request if Tenant ID exists in the encapsulated T-tag packet.. A zero i…
42899 …ccess:RW DataWidth:0x20 // If the Tenant ID exists in the encapsulated T-Tag packet and does n…
42900 …ataWidth:0x3 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. The T-tag bit of …
42905 …DataWidth:0x1 // MAC port arbitration guarantees fairness at byte-level (0) or packet-level (1).
42906 … DataWidth:0x1 // Main/LB arbitration guarantees fairness at byte-level (0) or packet-level (1).
42909 … 0x1f0510UL //Access:RW DataWidth:0x8 // Size of inter-packet gap and FCS us…
42910 …ority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 tr…
42911 …ority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 tr…
42912 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
42913 …bits are for priority 8 client. The clients are assigned the IDs corresponding to their TC # (0-8)
42914 …bits are for priority 8 client. The clients are assigned the IDs corresponding to their TC # (0-8)
42915 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
42916 … 0x1f052cUL //Access:RW DataWidth:0x1 // Enables pseudo-random round robin ar…
42919 …0x1f0538UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42922 …0x1f0544UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42925 …0x1f0550UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42928 …0x1f055cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42931 …0x1f0568UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42934 …0x1f0574UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42937 …0x1f0580UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42940 …0x1f058cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42943 …0x1f0598UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42946 …0x1f05a4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42949 …0x1f05b0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42952 …0x1f05bcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42955 …0x1f05c8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42958 …0x1f05d4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42961 …0x1f05e0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42964 …0x1f05ecUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42967 …0x1f05f8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42970 …0x1f0604UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42973 …0x1f0610UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42976 …0x1f061cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42979 …0x1f0628UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42982 …0x1f0634UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42985 …0x1f0640UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42988 …0x1f064cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42991 …0x1f0658UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42994 …0x1f0664UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42995 … 0x1f0700UL //Access:RW DataWidth:0x4 // Per-port: Size of the pro…
43007 …ataWidth:0x6 // Per-port: Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - V…
43010 … 0x1f073cUL //Access:RW DataWidth:0x10 // Per-PF: Base value used i…
43011 … 0x1f0740UL //Access:RW DataWidth:0x10 // Per-PF: Base value used i…
43026 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
43027 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
43028 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
43029 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
43030 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
43031 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
43032 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
43033 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
43034 … 0x1f079cUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43035 … 0x1f07a0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43036 … 0x1f07a4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43037 … 0x1f07a8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43038 … 0x1f07acUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43039 … 0x1f07b0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43040 … 0x1f07b4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43041 … 0x1f07b8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43046 … 0x1f07ccUL //Access:RW DataWidth:0x20 // Per-PF/Per-port: Destination …
43047 … 0x1f07d0UL //Access:RW DataWidth:0x10 // Per-PF/Per-port: Destination …
43048 … 0x1f07d4UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43049 … 0x1f07d8UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43050 … 0x1f07dcUL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43051 … 0x1f07e0UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43052 … 0x1f07e4UL //Access:RW DataWidth:0x2 // Per-PF: Destination IP address match value - …
43053 … 0x1f07e8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43054 … 0x1f07ecUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43055 … 0x1f07f0UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43056 … 0x1f07f4UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43057 … 0x1f07f8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43058 … 0x1f07fcUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43059 … 0x1f0800UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43060 … 0x1f0804UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43061 … 0x1f0808UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43062 … 0x1f080cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43063 … 0x1f0810UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43064 … 0x1f0814UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43065 … 0x1f0818UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43066 … 0x1f081cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43067 … 0x1f0820UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43068 … 0x1f0824UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43069 … 0x1f0828UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43070 … 0x1f082cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43071 … 0x1f0830UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43072 … 0x1f0834UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43073 … 0x1f0838UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43074 … 0x1f083cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43075 … 0x1f0840UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43076 … 0x1f0844UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43077 … 0x1f0848UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43078 … 0x1f084cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43079 … 0x1f0850UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43080 … 0x1f0854UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43081 … 0x1f0858UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43082 … 0x1f085cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43083 … 0x1f0860UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43084 … 0x1f0864UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43088 … 0x1f0874UL //Access:RW DataWidth:0x1 // Per-port: Flag enabling …
43089 … 0x1f0878UL //Access:RW DataWidth:0x1 // Per-port: Flag to compar…
43093 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43098 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43100 …ch in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg;…
43111 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43113 …ch in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg;…
43126 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43139 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43146 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43156 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43157 … 0x1f093cUL //Access:RW DataWidth:0x4 // Connection type for no-match packets.
43158 … 0x1f0940UL //Access:RW DataWidth:0x4 // Per-port: PFID for no-match packet…
43159 … 0x1f0944UL //Access:RW DataWidth:0x1 // Per-PF: If set, the PFID may be overridden for n…
43160 … 0x1f0948UL //Access:RW DataWidth:0x20 // Per-PF: CID for no-match packets.
43161 … 0x1f094cUL //Access:RW DataWidth:0x9 // Per-PF: LCID for no-match packets.
43169 … 0x1f096cUL //Access:RW DataWidth:0x1 // Per-PF: If set, and PF cl…
43170 …sulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN 2 - NGE
43171 …sulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN 2 - NGE
43172 …ulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN, 2 - NGE
43173 …-PF: Indicates whether to include Tenant ID (if it exists) in the MAC VLAN Cache entry for each en…
43174 …-VLAN Cache Flexible Field. If two blocks are used, this block is used for the upper bytes. 14:11…
43175 …the MAC-VLAN Cache Flexible Field. This block is only used if the number of bytes in mac_vlan_fle…
43178 … 0x1f09d0UL //Access:RW DataWidth:0x1 // Per-PF: If set, the SACK …
43179 …-FCoE packets. This allows Over-L2-Raw Part2 to be available on non-RoCE packets. The RoCE specifi…
43180 … 0x1f09d8UL //Access:RW DataWidth:0x20 // Per-PF: Mask used in RDMA…
43189 … 0x1f09fcUL //Access:RW DataWidth:0x1 // Per-PF: Enables SYN cooki…
43190 … 0x1f0a00UL //Access:RW DataWidth:0x1 // Per-PF: If set, enables i…
43191 …1 // Per-PF: If set, 4B for Ethernet CRC is included in Packet Length for Statistics field. For…
43192 …-PF: For each bit set, the length of the corresponding tag in the inner header will be subtracted …
43193 …-PF: For each bit set, the length of the corresponding tag in the first header will be subtracted …
43194 … 0x1f0a10UL //Access:RW DataWidth:0x1 // Per-Port: If set and clas…
43195 … 0x1f0a14UL //Access:RW DataWidth:0x8 // Per-Port: If classificati…
43196 … 0x1f0a18UL //Access:RW DataWidth:0x9 // Per-Port: If classificati…
43197 … 0x1f0a1cUL //Access:RW DataWidth:0x20 // Per-PF: This value is passed to the per-PF …
43198 … 0x1f0a20UL //Access:RW DataWidth:0x2 // Per-Port: This value goes…
43199 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 0. In …
43200 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 0. In 4…
43201 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 1. In …
43202 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 1. In 4…
43203 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 2. In …
43204 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 2. In 4…
43205 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 3. In …
43206 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 3. In 4…
43207 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 4. In …
43208 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 4. In 4…
43209 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 5. In …
43210 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 5. In 4…
43211 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 6. In …
43212 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 6. In 4…
43213 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 7. In …
43214 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 7. In 4…
43215 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 8. In 4…
43216 …0x1f0a68UL //Access:RW DataWidth:0x3 // bit 0 - ignore for VXLAN, bit 1 - ignore for NGE, bit…
43233 …-port): Packet available status of the main and loopback queues of each traffic class, before bein…
43234 …dth:0x18 // Debug only (per-port): STORM backpressure status (blocked priorities) Each set bit r…
43236 …ue of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Re…
43238 …f0b68UL //Access:R DataWidth:0xd // Debug only: In the case of a mini-cache LCID validation…
43266 …kts sent to TCM: Reserved - 127:66, Parsing and Error flags - 65:50, Start block - 49:37, Priority…
43303 … 0x1f0f8cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
43307 …-encasulated packet): 40.Source MAC 39.Destination MAC 38.VLAN (12b) ) � Tag 1 37.Provider VLAN (1…
43309 …reset 1-14 data 14-11 PF ID (3bit BB 4bit K2) 10-7 Tunnel type (4b) 0000-no tunnel 0001-vxlan 0010…
43324 …ld the priority field in the GFT used frame fields inner header 0- use CVLAN priority 1- use SVLAN…
43325 …d the priority field in the GFT used frame fields tunnel header 0- use CVLAN priority 1- use SVLAN…
43326 … 0x1f11bcUL //Access:RW DataWidth:0x1 // Per-PF: Enables gft searc…
43327 … 0x1f11c0UL //Access:RW DataWidth:0x1 // Per-PF: Enables gft search for non-IP pac…
43332 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43481 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43489 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43497 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43505 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43513 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43521 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43529 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43537 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43544 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43551 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43558 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43565 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43572 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43579 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43586 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43593 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43648 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43661 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43674 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43685 … 0x1f169cUL //Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on TCP 4 tuple. 0- p…
43686 … 0x1f16a0UL //Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on UDP 4 tuple. 0- p…
43706 …ataWidth:0x1 // Burst mode enabled. Set this bits to have the main round-robin arbiter stays o…
43713 …rom TX to RX. This loopback is on the line side after clock domain crossing - from the last TX pip…
43715 …om TX to RX. This loopback is on the core side before clock domain crossing - from the first TX pi…
43717 …om RX to TX. This loopback is on the line side before clock domain crossing - from the first RX pi…
43719 …rom RX to TX. This loopback is on the core side after clock domain crossing - from the last RX pip…
43729 … (0x1<<10) // Resets the RS layer functionality - fault handling.
43731 …ide the one column idle/sequence ordered set check before SOP in XGMII mode - effectively supporti…
43735 …cation from software or the link status indication from the strap pin. If reset; it selects the so…
43775 … (0x1<<1) // True to allow any non-Idle character to sta…
43779 …the MAC checks for IEEE Ethernet format premable - K.SOP + 5 '55' premable bytes + 'D5' SFD charac…
43783 …inimum receive packet size is reduced to 18 bytes from the default 33 bytes - Should be used in MA…
43805 …; the TX faults inputs are used to send out fault sequences - else receive faults are used -- used…
43809 …nsmit data is dropped on detection of local fault on the receive side. If reset; transmit data is …
43811 …smit data is dropped on detection of remote fault on the receive side. If reset; transmit data is …
43813 …data is dropped on detection of link interruption on the receive side. If reset; transmit data is …
43815 … (0x1<<7) // If set; the Receive LPause; PFC & LLFC timers are reset whenever the link …
43825 … (0x1<<0) // A rising edge on this register bit (0->1); clears the stick…
43827 … (0x1<<1) // A rising edge on this register bit (0->1); clears the stick…
43829 … (0x1<<2) // A rising edge on this register bit (0->1); clears the stick…
43832 …<<0) // This field is Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
43844 …use_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
43846 …use_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
43848 … (0xffff<<0) // Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
43850 …xffff<<16) // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
43853 … (0x1<<0) // Enable automatic re-send of PFC packet af…
43876 … (0x1<<3) // When set and llfc_in_ipg_only =0; GXPORT operates in cut-through mode.
43931 … (0x1<<0) // A rising edge on this register bit (0->1); clears the stick…
43933 … (0x1<<1) // A rising edge on this register bit (0->1); clears the stick…
43935 … (0x1<<2) // A rising edge on this register bit (0->1); clears the stick…
43937 … (0x1<<3) // A rising edge on this register bit (0->1); clears the stick…
43939 … (0x1<<4) // A rising edge on this register bit (0->1); clears the stick…
43941 … (0x1<<5) // A rising edge on this register bit (0->1); clears the stick…
43943 … (0x1<<6) // A rising edge on this register bit (0->1); clears the stick…
43985 … 0x210130UL //Access:RW DataWidth:0x10 // XMAC IP Version ID - corresponds to RTL/D…
44007 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44019 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44027 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44039 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44047 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44059 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44072 …_BB (0x1<<16) // Reset the Register inter…
44079 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44091 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44101 …1<<0) // This regiseter enables loopback mode (used for debug) 0 - loopback inactive 1 - loopback …
44188 …_BB (0x1<<16) // Reset the Register inter…
44270 …(on + off) for Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field is reset t…
44274 … // Led mode: 0 -> MAC; 1-3 -> PHY1; 4 -> MAC2; 5-7 -> PHY4; 8 -> MAC3; 9 -…
44275 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44276 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44277 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44280 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44283 … corresponding Physical function. 0 -> NW0 connects to PF0 1 -> NW0 connects to PF1 2 -> NW0 co…
44285 … corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connects to PF1 2 -> NW1 co…
44287 … corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1 2 -> NW2 co…
44289 … corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1 2 -> NW3 co…
44292 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44294 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44296 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44298 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44299 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44300 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44301 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44302 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44303 …h:0x1 // When set, PMIF block uses values in following registers to configure NIG - PM interface
44307 …G port is assigned to each PMEG Port. [1:0] -- PMEG Port 0 [3:2] -- PMEG Port 1 [5:4] -- PMEG Port…
44308 …G port is assigned to each PMFC Port. [1:0] -- PMFC Port 0 [3:2] -- PMFC Port 1 [5:4] -- PMFC Port…
44309 …e PMEG Port ID every cycle. Valid values are: 0 -- Only Port 0 is used 1 -- All Ports (0-3) are us…
44310 …e PMFC Port ID every cycle. Valid values are: 0 -- Only Port 0 is used 1 -- All Ports (0-3) are us…
44314 …IFO (bit [4]) and the NIG Tx FIFOs (bits [3:0]). To clear these bits, the NIG block must be reset.
44372 …th:0x1 // PMEG timestamp local counter reset. If = 0, the timers is reset. If = 1, the timer is…
44373 …th:0x1 // PMFC timestamp local counter reset. If = 0, the timers is reset. If = 1, the timer is…
44374 …ports 0,2 and should be used for 100G or 2x50G NW modes. Bit 0 - port0 CRC enable. Bit 1 - port2 C…
44375 …ports 0,2 and should be used for 100G or 2x50G NW modes. Bit 0 - port0 CRC enable. Bit 1 - port2 C…
44376 …pted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - por…
44377 …pted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - por…
44399 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44401 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44403 … (0x1<<7) // End of packet error on M-Storm command interfa…
44405 … (0x1<<8) // End of packet error on U-Storm command interfa…
44445 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44447 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44449 … (0x1<<7) // End of packet error on M-Storm command interfa…
44451 … (0x1<<8) // End of packet error on U-Storm command interfa…
44468 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44470 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44472 … (0x1<<7) // End of packet error on M-Storm command interfa…
44474 … (0x1<<8) // End of packet error on U-Storm command interfa…
44670 … 0x230420UL //Access:RW DataWidth:0x10 // Provides the value of the 16-bit pad that will be …
44673 … Initial credit to be used on the RDIF command interface for regular (non-pass-through) requests. …
44674 …on the RDIF command interface for pass-through requests. This value defines the maximum number of …
44678 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
44679 …th:0x9 // Defines the number of occupied entries required in the PXP read-response FIFO before …
44680 … DataWidth:0x20 // Statistics counter provides a count of the number of M-Storm comands that ha…
44681 … DataWidth:0x20 // Statistics counter provides a count of the number of U-Storm comands that ha…
44710 … 0x232000UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the M-Storm comma…
44712 … 0x232400UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the U-Storm comma…
44714 … 0x232800UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the BR…
44716 … 0x232c00UL //Access:R DataWidth:0x7 // Provides read-only access of the BR…
44718 … 0x233000UL //Access:WB_R DataWidth:0x2c // Provides read-only access of the ta…
44720 … 0x233400UL //Access:R DataWidth:0x11 // Provides read-only access of the pa…
44722 … 0x233600UL //Access:R DataWidth:0xb // Provides read-only access of the PB…
44724 … 0x233800UL //Access:WB_R DataWidth:0x100 // Provides read-only access of the PR…
44726 … 0x233c00UL //Access:R DataWidth:0x8 // Provides read-only access of the PXP write-done re…
44773 … 0x238480UL //Access:RW DataWidth:0x10 // Per-PF Bitmask for inclus…
44774 … 0x238484UL //Access:RW DataWidth:0x8 // Per-StringType Bitmask fo…
44811 … 0x23874cUL //Access:RW DataWidth:0x19 // Reset internal state mac…
45076 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45077 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45078 …0x20 // Debug register. FIFO empty status: {b15:8 - inp_fifo_counter; b7:6- cmd_fifo_couter; b5:…
45079 …ster. State of each state machine {b15:12 - calc_cur_state; b11:8 - main_cur_state;b7:4 - msg_cur_…
45324 … 0x23e000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
45328 … // Driver should write 1 to this register in order to signal the PSWRQ block to issue soft reset.
45331 …x4 // Page size in L2P table for CDU-Task module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-51…
45332 … // Page size in L2P table for CDU module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45333 …4 // Page size in L2P table for TM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45334 …4 // Page size in L2P table for QM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45335 … // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45336 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45337 … // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45338 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45339 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45346 … 0x240048UL //Access:RW DataWidth:0xe // First memory address base for cdu-connection in ILT.
45347 … 0x24004cUL //Access:RW DataWidth:0xe // Last memory address base for cdu-connection in ILT.
45348 … 0x240050UL //Access:RW DataWidth:0xe // First memory address base for cdu-task in ILT.
45349 … 0x240054UL //Access:RW DataWidth:0xe // Last memory address base for cdu-task in ILT.
45387 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45391 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45393 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45395 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45397 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45403 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45405 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45407 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45409 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45411 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45413 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45461 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45465 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45467 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45469 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45471 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45477 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45479 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45481 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45483 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45485 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45487 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45498 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45502 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45504 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45506 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45508 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45514 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45516 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45518 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45520 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45522 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45524 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45634 …W DataWidth:0x3 // Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010:…
45635 …RW DataWidth:0x3 // Max burst size filed for read requests port 0; 000 - 128B; 001:256B; 010:…
45638 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45639 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45653 …DataWidth:0x8 // Initial value of global counter; This value MUST be 256 - sum of all clients t…
46001 … 0x2406a0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ5 Read- currently not used.
46104 … (0xf<<0) // Indicates the number of credits for read sub-requests in th reques…
46106 … (0x1f<<4) // Indicates the number of credits for write sub-requests in th reques…
46111 … 0x240724UL //Access:RW DataWidth:0x5 // Sets which vq head pointer to see out of queues 0-31.
46112 … 0x240728UL //Access:RW DataWidth:0x5 // Sets which vq tail pointer to see out of queues 0-31.
46114 …th:0x1 // When set the new alignment method (E2) will be applied; when reset the original align…
46146 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46147 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46148 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46149 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46150 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46151 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46152 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46153 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46154 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46155 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46156 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46157 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46158 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46159 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46160 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46161 …- SR from the VQ can send ATC lookup request to the ATC (assuming all other conditions are met). W…
46162 …ss:RW DataWidth:0x2 // ATC enable values per PF as follows: b0 - PF enable; b1 - VF enable; P…
46163 …ues of rq_atc_internal_ats_enable as follows: b0 - PF0; b1 - VF0; b2 - PF1; b3 - VF1; b30 - PF15 ;…
46164 …-PGLUE interface for more details). In that case the address will be delivered by the chip (and no…
46165 … 0x2407fcUL //Access:RW DataWidth:0x1 // Global ATC enable bit. when reset all ATC logic is d…
46166 … 0x240800UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46167 … 0x240804UL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i…
46168 … 0x240808UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46169 … 0x24080cUL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i…
46170 … 0x240810UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46171 … // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ…
46175 …- assert ilt fail interrupt (rq_elt_addr) in case working in ilt mode and onchip translation fail …
46177 …: enable reading from the hoq ram; when set hoq rbc read is enabled; when reset hoq rbc read is di…
46178 …FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 d…
46182 … //Access:R DataWidth:0x20 // FOR DBG: bit 0 relaxed ordering; bit 1 no-snoop; bits 5:2 clien…
46183 … 0x240844UL //Access:R DataWidth:0x20 // The total number of WR SR-s that were sent to t…
46184 … 0x240848UL //Access:R DataWidth:0x20 // The total number of RD SR-s that were sent to t…
46185 … 0x24084cUL //Access:R DataWidth:0x20 // The number of PBF RD SR-s that were sent to t…
46186 … 0x240850UL //Access:R DataWidth:0x20 // The number of USDM-DP WR SR-s that were sent …
46187 … 0x240854UL //Access:R DataWidth:0x20 // The number of TREQ SR-s that were sent to t…
46188 … 0x240858UL //Access:R DataWidth:0x20 // The number of ICPL SR-s that were sent to t…
46189 …20 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46190 …9 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46191 …20 // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46192 …c // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46193 …0x20 // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46194 …0xc // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46195 …:0x20 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46196 …:0x9 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46197 … // Counting window mode. 0 - manual window: counting is manually being initiated & stopped by t…
46200 …en working in manual window mode (i.e. Sr_cnt_window_mode = 0). 0 - stop counting. 1 - start count…
46201 … // Write Only register. RBC write command to this reg (any value) will reset the SR counters & …
46202 …global window counter). 0 - start counting upon any first SR that is sent to the PGLUE. 1 - start …
46205 …atus of the SR count mechanism: 0 - idle: ready to start new counting. 1 - ongoing: counting is cu…
46206 … 0x2408a0UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46207 … 0x2408a4UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46208 … 0x2408a8UL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46209 …dth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client …
46210 … 0x2408b0UL //Access:R DataWidth:0x9 // bit 8-0: srid.
46211 … 0x2408b4UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46212 … 0x2408b8UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46213 … 0x2408bcUL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46214 … DataWidth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15…
46215 … 0x2408c4UL //Access:R DataWidth:0xa // b1-0: atc code; b2: wdone type; b4-3: endianity; …
46243 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46244 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46245 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46246 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46247 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46258 …l2p_vf_err or rq_elt_addr interrupt. [12:0] - Length in bytes. [16:13] - PFID. [17] - VF_VALID. …
46259 …:16] client ID. [21] - Error type - 0 - rq_l2p_vf_err; 1 - rq_elt_addr. [22] - w_nr - 0 - read; 1 …
46261 …:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must be big…
46263 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46264 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46265 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46266 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46267 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46268 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46269 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46270 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46271 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46272 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46273 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46274 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46275 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46276 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46277 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46278 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46279 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46280 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46281 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46282 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46283 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46284 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46285 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46286 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46287 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46288 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46289 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46290 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46291 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46294 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46295 … 0x2409c4UL //Access:R DataWidth:0x9 // Debug only: The SR counter - number of unused sub…
46328 …0x240a48UL //Access:R DataWidth:0xa // Debug only: The blocks counter - number of unused blo…
46391 … 0x240b44UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46392 … 0x240b48UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46393 … 0x240b4cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46394 … 0x240b50UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46395 … 0x240b54UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46396 … 0x240b58UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46397 … 0x240b5cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46398 … 0x240b60UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46399 … 0x240b64UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46400 … 0x240b68UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46401 … 0x240b6cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46402 … 0x240b70UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46403 … 0x240b74UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46404 … 0x240b78UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46405 … 0x240b7cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46406 … 0x240b80UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46407 … 0x240b84UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46408 … 0x240b88UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46409 … 0x240b8cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46410 … 0x240b90UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46411 … 0x240b94UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46412 … 0x240b98UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46413 … 0x240b9cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46414 … 0x240ba0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46415 … 0x240ba4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46416 … 0x240ba8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46417 … 0x240bacUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46418 … 0x240bb0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46419 … 0x240bb4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46420 … 0x240bb8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46421 … 0x240bbcUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46422 … 0x240bc0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46430 … 0 - the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW count…
46431 …- the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters…
46432 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46433 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46434 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46435 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46436 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46437 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46438 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46439 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46440 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46441 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46442 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46443 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46444 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46445 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46446 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46447 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46448 …-PGLUE request interface write credit; 0 - no more credit for wr SR-s (i.e. write SR-s cannot be s…
46449 …-PGLUE request interface read credit; 0 - no more credit for rd SR-s (i.e. read SR-s cannot be sen…
46450 …can be a workaround for possible bugs in the byte counters. Id-s are based on wr client id-s (take…
46451 …-1] between qc_cmg_add_2_q (indication that new request is written into hoq0) and cmg_qc_del_head …
46452 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46453 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46454 … 0x240c40UL //Access:R DataWidth:0xe // For debug and Idle-check use. The value …
46456 …ite done for them from the PGLUE). Upon reaching the threshold no more wr SR-s will be sent by the…
46513 … // Page size in L2P table for tgsrc module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
46514 … // Page size in L2P table for RGSRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
46552 …5 // Internal lookup table for logical to physical address translation. Re-instantiated in E4 du…
46772 …- TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM; 5 - PSDM; 6 - QM; 7 - TM; 8 - SRC; 9 - DMAE; 10 - …
46773 …reset towards the client. The clients order is according to the incrementing client IDs of write c…
46948 …- client ID. [7:5] - (sum1[5:3] + 1) or (sum1[5:4] + 1) according to the definition in the spec. […
46951 …9b054UL //Access:R DataWidth:0x8 // Maximum internal PRM fill level since reset in 64B lines.
46953 …9b05cUL //Access:R DataWidth:0x6 // Maximum internal CDU fill level since reset in 64B lines.
46956 …0x29b068UL //Access:RW DataWidth:0x7 // If Number of entries in the PRM-secondary internal fi…
46957 … 0x29b06cUL //Access:R DataWidth:0x7 // Current internal PRM-secondary fill level …
46958 …070UL //Access:R DataWidth:0x7 // Maximum internal PRM-secondary fill level since reset in 6…
46996 … the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the…
47086 … the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the…
47131 … the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the…
47685 …ss:R DataWidth:0x12 // Each bit indicates if full was asserted since reset by the client. The…
47719 …n this VQ in PSWRD. The reset value is the one expected in idle check except for the Timers VQ (VQ…
47725 …ot to override the data. Arrowhead: The reset value of 1 should not be changed. It can cause Xs on…
47727 …-block until end of packet. Note that the override may start a few cycles before or after the last…
47729 …uest with error on receive side: [15:0] - Echo ID. [28:16] - sub-request length minus 1. [29] - fi…
47730 …ils of first request with error on receive side: [4:0] - VQ ID. [9:5] - client ID. [10] - valid - …
47737 … this VQ in PSWRD. The reset value is the one expected in idle check except for the Timers VQ (VQ3…
47764 …han this Number of entries are used in the clock synchronization FIFO; it de-asserts the 'almost f…
47766 …this Number of entries are used in the CDU clock synchronization FIFO; it de-asserts the 'almost f…
47768 …this Number of entries are used in the PBF clock synchronization FIFO; it de-asserts the 'almost f…
47770 …han this Number of entries are used in the clock synchronization FIFO; it de-asserts the 'almost f…
47771 …ataWidth:0x12 // Each bit indicates if 'almost full' was asserted since reset from the FIFO towa…
47772 … 0x29d144UL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since res…
47773 … 0x29d148UL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since res…
47774 … 0x29d14cUL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since res…
47775 … 0x29d150UL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since res…
47776 …d154UL //Access:R DataWidth:0x8 // PBF maximum sync FIFO fill level since reset in 16B lines.
47779 … 0x29d160UL //Access:R DataWidth:0x8 // Per-client maximum sync FIFO fill level since res…
48121 …:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must be big…
48123 … 0x29d46cUL //Access:RW DataWidth:0x1 // Global ATC enable bit. When reset all ATC logic is d…
48124 … 0 - The delivery port continues delivering the next PBF request only if the second delivery port …
48212 …ter-engine indicating if the engine is idle. Idle means the engine is not sending request (and the…
48213 …- pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 P…
48214 … 0x2a0060UL //Access:R DataWidth:0x1 // 1 - An error request is …
48216 …- RSV [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM…
48217 …the format is: [6:0] - length in DWs. The data is written only when the valid bit is reset. and it…
48218 … 0x2a0070UL //Access:R DataWidth:0x1 // 1 - An incorrect access is logged. The valid bit is…
48220 …0x2a0078UL //Access:R DataWidth:0x1 // 1- permission violation data is logged. The valid bit…
48226 …te source that consumed more than its allowed credits. the format is: [3:0] - client (0 TSDM; 1 MS…
48227 …x2a0094UL //Access:R DataWidth:0x1 // 1 - A source credit violation is logged. The valid bit…
48233 … 0x2a00acUL //Access:R DataWidth:0x1 // 1 - PSWHST is in drain m…
48235 …- length in DWs; [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - cli…
48236 … 0x2a00b8UL //Access:R DataWidth:0x1 // 1 - An hst timeout data is logged. The valid bit is…
48238 …interface. PSWHST issues an attention if more credits are consumed. Added in BB-B0 due to pipeline.
48283 …ccess is dropped). The disabled vf registers are valid when it is set and reset when the interrupt…
48287 …ss registers. The incorrect access registers are valid when it is set and reset when the interrupt…
48357 …ccess is dropped). The disabled vf registers are valid when it is set and reset when the interrupt…
48361 …ss registers. The incorrect access registers are valid when it is set and reset when the interrupt…
48394 …ccess is dropped). The disabled vf registers are valid when it is set and reset when the interrupt…
48398 …ss registers. The incorrect access registers are valid when it is set and reset when the interrupt…
48451 …und interrupts memory. E4 entry structure: [15:0] - CompParams. [23:16] - EventID. [24] - T. [28:2…
48490 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48588 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48637 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48783 …- for Atomic Op / MRD handling of NPH credits. 0 - Can send both if there is one NPH credit and th…
48787 … (0x1<<0) // 0 - Debug bus is not output to RBCN_e0. 1 - …
48789 … (0x1<<1) // 0 - Debug bus is not output to RBCN_e1. 1 - …
48806 … (0x1<<9) // This bit give strict priority to read over write on the PGL read-write arbiter.
48809 …was blocked because of bus_master_en was deasserted. Bit 1: Added in BigBear-B0. Indicates that cu…
48810 …was blocked because of bus_master_en was deasserted. Bit 1: Added in BigBear-B0. Indicates that cu…
48819 …ccess:R DataWidth:0x9 // Debug only: Maximal number of used tags at a given time since reset.
48820 …reset. Note that such errors are legitimate. Bit 0 - Target memory read arrived with a correctable…
48835 …UL //Access:RW DataWidth:0x1 // Debug only: 0 - PCIe checksum is generated towards PCIe core.…
48839 …:0x5 // Pseudo VF target mode configuration that controls the size of each pseudo-VF in the BAR.
48841 … to accesss DORQ via BAR0: 0-disable access; 1-enable access if BAR0 size is 128K; 2-enable acces…
48842 … 0x2a84ecUL //Access:RW DataWidth:0x9 // VSC fields: bit 0 - enable VSC; bits 1-8 - VSC reser…
48858 …-PF region. Addresses 0x0 - 0x5c: 12 per-PF PF windows. Each PF window contains two 32-bit values.…
48860 …0x0 - 0x3c8 (0x200 - 0x5c8) - 243 global windows. Each entry is the 12-bit window offset. Address…
48862 …ister on which config space A attention is generated. Note that this register is in 128-byte units.
48863 …ting in address cfg_space_a_address generates an attention. If bit N is set - a CSSNOOP cycle with…
48864 …ister on which config space B attention is generated. Note that this register is in 128-byte units.
48865 …ting in address cfg_space_b_address generates an attention. If bit N is set - a CSSNOOP cycle with…
48866 …that the corresponding PF generates config space A attention. Set by PXP. Reset by MCP writing 1 t…
48867 …est register. Note: register contains bits from both paths. Note: Need to re-read the enabled regi…
48868 …that the corresponding PF generates config space B attention. Set by PXP. Reset by MCP writing 1 t…
48869 …est register. Note: register contains bits from both paths. Note: Need to re-read the enabled regi…
48870 …icates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 t…
48871 …icates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 t…
48872 …icates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 t…
48873 …icates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 t…
48874 …icates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 t…
48875 …icates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 t…
48876 …icates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 t…
48877 …icates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 t…
48878 …icates that the FLR register of the corresponding PF was set. Set by PXP. Reset by MCP writing 1 t…
48891 …ABLED_REQUEST (0x1<<1) // Debug only: When 1 SR-IOV disbaled request …
48893 …of the corresponding PF is written to 0 and was previously 1. Set by PXP. Reset by MCP writing 1 t…
48904 …in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select field…
48905 …in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select field…
48906 …in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select field…
48907 …in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select field…
48908 …in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select field…
48909 …in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select field…
48910 …in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select field…
48911 …in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select field…
48912 …- Shadow bits clear for PFs 0 to 31. MCP writes 1 to a bit in this register in order to reset the…
48922 …th:0x10 // Shadow vf_enable register for all PFs. Each bit indicates if SR-IOV for the correspon…
48926 …- Reserved. Bit 1 - Reserved. Bit 2 - Reserved. Bit 3 - Reserved. Bit 4 - Completion with Configur…
48927 …completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 t…
48928 …completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 t…
48929 …completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 t…
48930 …completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 t…
48931 …completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 t…
48932 …completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 t…
48933 …completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 t…
48934 …completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 t…
48935 …completion with uncorrectable error for the corresponding PF. Set by PXP. Reset by MCP writing 1 t…
48936 …egister. The register is split per path but VFID is global. Each path can reset only the VFs belon…
48937 …egister. The register is split per path but VFID is global. Each path can reset only the VFs belon…
48938 …egister. The register is split per path but VFID is global. Each path can reset only the VFs belon…
48939 …egister. The register is split per path but VFID is global. Each path can reset only the VFs belon…
48940 …egister. The register is split per path but VFID is global. Each path can reset only the VFs belon…
48941 …egister. The register is split per path but VFID is global. Each path can reset only the VFs belon…
48942 …egister. The register is split per path but VFID is global. Each path can reset only the VFs belon…
48943 …egister. The register is split per path but VFID is global. Each path can reset only the VFs belon…
48944 …egister. The register is split per path but PFID is global. Each path can reset only the PFs belon…
48945 …- PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of …
48946 …- PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of …
48949 …ot submitted due to error. [4:0] VQID. [17:5] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. …
48950 …- Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indica…
48953 …QID. [5] TREQ. 1 - Indicates the request is a Translation Request. [18:6] - Length in bytes. [19] …
48954 …- Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indica…
48955 …- PFID. [11:4] - VFID. [12] - VF_VALID. [17:13] - ITAG Index. [21:18] - Error type - [18] - Indic…
48956 …68UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-VF for master and tar…
48957 …6cUL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for master transac…
48958 …70UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target write t…
48959 …74UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target read tr…
48968 …pfid_enable registers for target flow. Bits [15:0] - internal_pfid_enable_target_write; Bits [31:1…
48969 … global view of internal_pfid_enable registers for master flow. Bits [15:0] - internal_pfid_enable…
49000 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49001 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49002 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49003 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49004 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49005 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49006 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49007 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49008 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49009 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49010 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49011 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49012 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49013 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49014 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49015 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49016 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49017 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49018 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49019 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49020 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49021 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49022 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49023 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49024 … 0x2aa318UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49025 … 0x2aa31cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49026 … 0x2aa320UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49027 … 0x2aa324UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49028 … 0x2aa328UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49029 … 0x2aa32cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49030 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49031 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49032 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49033 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49034 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49035 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49036 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49037 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49038 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49039 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49040 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49041 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49042 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49043 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49044 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49045 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49046 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49047 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49048 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49049 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49050 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49051 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49052 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49053 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49054 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49055 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49056 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49057 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49058 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49059 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49060 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49061 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49062 …R0. [12:0] Address in DWs (bits [14:2] of byte address). [14:13] BAR. [22:15] VFID. [26:23] - PFID.
49063 …st with length violation (too many DWs) accessing BAR0. [5:0] - Length in DWs. [6] valid - indica…
49064 …ermission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. [23:16] VFID. [27:24] - PFID. [28…
49065 …- clears INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears TX_ERR_WR_ADD_31_0 T…
49067 … 0x2aa3c4UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates t…
49068 … 0x2aa3c8UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates t…
49069 … 0x2aa3ccUL //Access:RW DataWidth:0x1 // 1 - Do not discard IGU m…
49070 …- Accesses to the first 8KB of IGU in BAR0 (MSIX table and PBA) are not allowed. When this value i…
49071 …pletion is considered erroneous. [3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [17:13] - OTB EntryI…
49072 …- Unsupported Request or Completer Abort on User RX Interface. 1 - Reception of a poisoned TLP on …
49073 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49074 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49075 …- Enable the fix for CQ45220. If a Function receives a Translation Completion with a Translation S…
49076 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49077 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49094 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49096 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49098 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49100 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49102 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49104 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49106 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49108 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49110 …-only register reflects the value of the corresponding 'PF trusted' config bit on the external con…
49113 …. 1 - Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFI…
49114 …- PGLUE will submit the request with TPH info. PXP will take care of aligning it correctly when se…
49115 … address). [13:10] BE first. [17:14] BE last. [21:18] - PFID. [27:22] - Length in DWs. [28] valid …
49116 …- original PFID. [7:4] Pretend PFID. [15:8] Pretend VFID. [16] Pretend vf_valid. [20:17] Pretend r…
49118 …2aa560UL //Access:RW DataWidth:0x1 // 0 - Work with external BAR0 mechanism as defined in E4 …
49125 …57cUL //Access:RW DataWidth:0x1 // FID channel enable configuration per-VF. Controls Target …
49126 …led for that SDM. One bit per SDM. Bit 0 - TSDM. Bit 1 - MSDM. Bit 2 - USDM. Bit 3 - XSDM. Bit 4 -…
49127 …3 // Window size for VF to PF channel. 0 - NA; 1 - 8B; 2 - 16B; 3 - 32B; 4 - 64B; 5 - 128B; 6 -…
49130 … (0x1<<0) // Decision bit for PF master requests when BME is cleared: 0 - block; 1 - discard.
49132 …(0x1<<1) // Decision bit for PF master requests when fid_enable is cleared: 0 - block; 1 - discard.
49134 … (0x1<<2) // Decision bit for PF master requests when was_error is set: 0 - block; 1 - discard.
49136 … (0x1<<3) // Decision bit for VF master requests when BME is cleared: 0 - block; 1 - discard.
49138 …(0x1<<4) // Decision bit for VF master requests when fid_enable is cleared: 0 - block; 1 - discard.
49140 … (0x1<<5) // Decision bit for VF master requests when was_error is set: 0 - block; 1 - discard.
49143 … PF master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set att…
49145 …er requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set att…
49147 …F master requests when was_error is set: 0 - Always set (and log error details); 1 - never set att…
49149 … VF master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set att…
49151 …er requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set att…
49153 …F master requests when was_error is set: 0 - Always set (and log error details); 1 - never set att…
49162 … of '1' instructs PGLUE to use the client ID value in the 'tag' field of non-TPH master write pack…
49163 …RW DataWidth:0x1 // This field is an enable bit for 'detection of out-of-range requests' debu…
49165 … of ) the minimal legal address value. It is used in the 'detection of out-of-range requests' debu…
49167 … of ) the maximal legal address value. It is used in the 'detection of out-of-range requests' debu…
49171 …th illegal address. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49172 …- address was smaller than minimal_address_log; 1 - address was bigger than maximal_address_log. …
49175 …th TPH information. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49176 …nt ID. [6:5] PH. [14:7] Steering Tag. [15] - write_n_read: 0 - read; 1 - write. [16] - last SR. […
49177 …x1 // 0 - never pad write sub-requests with zeros. 1 - Pad write sub-requests with zeros and al…
49178 …/Access:RW DataWidth:0x3 // Cache line size for padding. 0 - 32B. 1 - 64B. 2 - 128B. 3 - 256B.
49179 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49180 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49181 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49182 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49183 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49184 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49185 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49186 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49196 …t error indication. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49197 …[15:0] Request ID. [20:16] client ID. [21] - write_n_read: 0 - read; 1 - write. [22] - last SR. […
49199 …ion dirty bits. Bit 0 is for engine 0 and bit 1 for engine 1. Set by PXP. Reset by MCP writing 1 t…
49201 …UL //Access:R DataWidth:0x10 // MPS attention dirty bit. Set by PXP. Reset by MCP writing 1 t…
49203 …icates that the VPD register of the corresponding PF was set. Set by PXP. Reset by MCP according t…
49233 … 0x2aaf10UL //Access:R DataWidth:0x10 // pm_dstate 47-032
49235 … 0x2aaf60UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 31-0
49236 … 0x2aaf64UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 63 -32
49237 … 0x2aaf68UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 95 - 64
49238 … 0x2aaf6cUL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 127 - 96
49239 … 0x2aaf70UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 159-128
49243 … // Indicates there was an error in MCTP BIt 21-30 Message code Bit 7-22 Vender ID Bit 3-6 TAG…
49244 …dth:0x20 // Indicates there was an error in MCTP Bit 21-30 Length Bit 5-20 PCIE REQ ID Bit 0-4 …
49256 …0x2aafb4UL //Access:RW DataWidth:0x1 // 0 - Don't discard target request with unknown header …
49257 …cess:RW DataWidth:0x1 // 0 - Don't compare the function received in the completion to the ori…
49258 … 0x2aafbcUL //Access:RW DataWidth:0x1 // 0 - Enable b2b pop from sync fifos in pgl_pci_core_r…
49259 … 0x2aafc0UL //Access:RW DataWidth:0x1 // 0 - Don't discard master request during FLR 1 …
49260 … DataWidth:0x4 // 0 - TXCPL sync fifo push overflow 1 - TXR sync fifo push overflow 2 - TXW hea…
49261 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo pop underflow 1 - RX header syn…
49262 …x2aafccUL //Access:R DataWidth:0x12 // 8:0 - RX target read and config sync fifo pop status …
49265 …_MEM_SELF_INIT_START (0x1<<0) // Reset the context memory…
49267 …CONN_MEM_SELF_INIT_START (0x1<<1) // Reset the config conn me…
49269 …TASK_MEM_SELF_INIT_START (0x1<<2) // Reset the config task me…
49271 …N_MEM_SELF_INIT_START (0x1<<3) // Reset the pre scan memor…
49273 …Width:0x1 // When set, the self init for the context memory is done. TBD - need to change to re…
49562 … (0x1<<2) // Context Read with Last indication de-asserted.
49564 … (0x1<<3) // Context Write with Last indication de-asserted.
49608 … (0x1<<2) // Context Read with Last indication de-asserted.
49610 … (0x1<<3) // Context Write with Last indication de-asserted.
49631 … (0x1<<2) // Context Read with Last indication de-asserted.
49633 … (0x1<<3) // Context Write with Last indication de-asserted.
49770 …x2 // Number of timers per connection group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49771 …idth:0x2 // Number of timers per task group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49772 …- the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each gr…
49773 …- the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each gr…
49776 …lock in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49777 …lock in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49778 …ckss in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49779 …eld for writes; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49780 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49781 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49782 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49783 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49784 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49785 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49786 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49787 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49788 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49789 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49790 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49791 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49792 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49793 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49807 …scan is completed or if task scan is completed. The counter wraparound, and is not reset when read.
49858 …the debug_0 registers. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved,…
49859 …tes that the debug_0 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49863 …- SET TIMER, 1 - CLEAR TIMER, 2 - STOP ALL TIMERS, 3 - INIT, 4 - FORCE CLEAR TIMER, 5 - reserved,…
49866 …s:R DataWidth:0x1 // The Leader Type field for the errored command: 0 - connection, 1 - task.
49867 …r the errored command. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved,…
49870 …tes that the debug_1 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49872 …-0: LCID, Bit 9: scan type (0 - connection, 1 - task), Bits 12-10: type (3 LSbits), Bit 13: Load E…
49873 …tes that the debug_2 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49874 …last indication de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 10…
49875 …tes that the debug_3 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49876 …ion de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 11-10: Qward V…
49877 …-0: cmd_handler. Bit 3: reserved. Bits 7-4: writ…
49878 …tes that the debug_4 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49879 … Bits 8-0: function # (0-239 VFs, 240 and above PFs / segments) . Bit 9: type (0 - connecti…
49889 …- number of connections, the value should be multiplies of group_size_resolution_conn register (fo…
49893 …- number of tasks, the value should be multiplies of group_size_resolution_task register (for exam…
49897 …r connections, the last 512 rows contain the scan rate fields for tasks. TBD - describe the fields.
49908 … (0x1<<10) // When set link list ram will be initialized - all LCIDs will be lo…
49912 …TID Lock RAM to be initialized. This cannot be set during normal operation -- the block must be id…
49993 … it updates these fields. [31:28] -- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Request…
49994 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
49995 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
49996 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
50010 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50020 … (0xf<<10) // This register is not used in BB-B0. Reduced width to …
50048 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50049 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50050 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50078 …00UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a …
50079 …04UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a …
50080 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50081 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50086 … (0x1<<10) // This field is not used in BB-B0. When set, this co…
50112 …L //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if les…
50186 … 0x2d0a3cUL //Access:R DataWidth:0xa // {HIT;LCID}. HIT - if set then previous…
50187 …cess:RW DataWidth:0x1 // Added in E4B0. 0 - tid is not included in hash calculation (like in …
50188 …ess:RW DataWidth:0x1 // Added in E4B0. 0 - vlan is not included in hash calculation (like in …
50192 … 0x2d0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CI…
50196 … 0x2d0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the ST…
50207 … 0x2db000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
50224 … (0x1<<10) // When set link list ram will be initialized - all LCIDs will be lo…
50228 …TID Lock RAM to be initialized. This cannot be set during normal operation -- the block must be id…
50336 … it updates these fields. [31:28] -- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Request…
50337 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
50338 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
50339 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
50353 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50363 … (0xf<<10) // This register is not used in BB-B0. Reduced width to …
50391 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50392 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50393 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50421 …00UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a …
50422 …04UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a …
50423 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50424 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50429 … (0x1<<10) // This field is not used in BB-B0. When set, this co…
50455 …L //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if les…
50529 … 0x2e0a3cUL //Access:R DataWidth:0xa // {HIT;LCID}. HIT - if set then previous…
50530 …cess:RW DataWidth:0x1 // Added in E4B0. 0 - tid is not included in hash calculation (like in …
50531 …ess:RW DataWidth:0x1 // Added in E4B0. 0 - vlan is not included in hash calculation (like in …
50535 … 0x2e0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CI…
50539 … 0x2e0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the ST…
50550 … 0x2eb000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
51180 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51181 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51182 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51183 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51184 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51185 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51186 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51187 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51188 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51189 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51190 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51191 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51192 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51193 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51194 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51195 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51196 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51197 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51198 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51199 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51200 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51201 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51202 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51203 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51204 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51205 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51206 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51207 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51208 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51209 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51210 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51211 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51212 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51213 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51214 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51215 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51216 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51217 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51218 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51219 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51220 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51221 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51222 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51223 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51224 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51225 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51226 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51227 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51228 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51229 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51230 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51231 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51232 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51233 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51234 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51235 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51236 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51237 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51238 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51239 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51240 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51241 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51242 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51243 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51244 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51245 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51246 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51254 …L //Access:WB DataWidth:0x36 // Pointer Table Memory for Other queues 63-0; The mapping is as …
51260 … 0x2f1010UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards…
51264 … 0x2f1030UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards…
51265 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51266 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51267 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51268 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51269 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51270 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51271 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51272 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51273 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51274 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51275 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51276 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51277 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51278 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51279 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51280 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51281 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51282 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51283 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51284 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51367 …-b0: rd first bank in page; b3: reserved (zero); b6-b4: wr first bank in page; b7: reserved (zero)…
51368 …al STU within the PXP (there is STU per PF). 0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
51369 …H field used in the PCI request. Per PF value. bits: 8-0 TPH Steering Tag Index; 12-9 reserved; 14…
51375 …- VOQs [0..31] VoqCrdLineFull_msb - VOQs [32..35] Some VOQs are "not used" depending on the…
51376 … to the matched Voq line credit (relevant only for VOQs that are being used - or in other words VO…
51377 …- VOQs [0..31]. VoqCrdByteFull_msb - VOQs [32..35]. Some VOQs are "not used" depending on t…
51378 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51379 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51380 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51381 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51382 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51383 …- VOQs [0..31]. AFullQmBypThrLineVoqMask_msb - VOQs [32..35]. Some VOQs are "not used" depe…
51388 …- resource is required to be more than the almost full threshold. 0 - resource value is do not car…
51389 …credit almost full threshold for the opportunistic credit flow operation. reset value: +2 x TaskLi…
51390 …credit almost full threshold for the opportunistic credit flow operation. reset value: +2 x TaskBy…
51391 …t almost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrd…
51392 …t almost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrd…
51393 …credit almost full threshold for the opportunistic credit flow operation. reset value: +2 x TaskBy…
51394 …credit almost full threshold for the opportunistic credit flow operation. reset value: +2 x TaskBy…
51395 …- resource is required to be more than the almost full threshold. 0 - resource value is do not car…
51398 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51399 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51400 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51401 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51402 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51403 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51404 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51405 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51406 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51407 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51408 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51409 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51410 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51411 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51412 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51413 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51414 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51415 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51416 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51417 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51418 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51419 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51420 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51421 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51422 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51423 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51424 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b01. NOTE: weight update is allowed only to queues w…
51425 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b11. NOTE: weight update is allowed only to queues w…
51436 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51437 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51438 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51439 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51440 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51441 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51442 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51443 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51444 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51445 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51446 …is masked. i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51447 …-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM se…
51462 …0x2f2800UL //Access:R DataWidth:0x1 // The status of the Other PQ-s: bit0 - PQ paused. Shoul…
51466 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51467 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51468 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51469 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51470 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51471 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51472 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51473 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51474 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51475 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51476 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51477 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51478 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51479 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51480 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51481 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51482 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51483 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51484 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51485 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51486 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51487 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51488 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51489 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51490 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51491 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51492 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51493 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51494 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51495 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51496 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51497 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51498 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51499 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51500 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51501 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51502 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51503 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51504 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51505 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51506 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51507 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51508 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51509 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51510 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51511 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51512 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51513 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51514 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51515 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51516 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51517 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51518 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51519 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51520 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51521 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51522 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51523 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51524 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51525 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51526 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51527 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51528 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51529 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51530 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51531 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51532 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51533 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51534 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51535 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51536 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51537 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51538 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51539 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51540 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51541 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51542 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51543 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51544 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51545 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51550 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for selecting a line…
51551 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for enabling dwords …
51552 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for circular right s…
51553 … // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing valid.
51554 … // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing frame.
51555 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 lsb data that…
51556 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 msb data that…
51557 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 frame bits tha…
51558 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 valid bits tha…
51571 …ut period in 25Mhz clock cycles for the global. VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51572 …out period in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51573 … for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. Upon init should be set with value of …
51574 …od counter in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51575 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51576 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51577 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51578 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51579 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51580 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51581 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51582 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51585 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51587 …-init mode. In init mode should be written with the same value of RlGlblUpperBound. Sign: the msb …
51591 …x1 // when 1 - force cam search and update sts_rlglbl_pq_blocked vector even when the rlglblcrd…
51592 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51593 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51594 …o). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51595 …ector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlGlblCrd; b1 …
51596 …ataWidth:0x20 // The RL timeout period in 25Mhz clock cycles for the PF RL-s. NOTE: ck25 domain.…
51597 …:0x20 // The RL timeout period counter in 25Mhz clock cycles for the PF RL-s. Upon init should b…
51601 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51604 …-init mode. In init mode should be written with the same value of RlPfUpperBound. Sign: the msb is…
51608 … the PF RL mechanism per VOQ. RlPfVoqEnable (This one) - VOQs [0..31]. RlPfVoqEnable_msb - …
51609 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51610 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51611 …ero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51612 … vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlPfCrd; b1 …
51616 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51619 …- VOQ0..VOQ15. WfqPfCrd_msb - VOQ16..VOQ35. Should be read only access in non-init mode. In init m…
51624 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51625 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51626 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51627 …vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqPfCrd; b1 …
51629 …0x1 // when 1 - force cam search and update sts_wfqvp_pq_blocked vector even when the wfqvpcrd …
51630 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51631 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51632 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51633 …vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqVpCrd; b1 …
51634 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51635 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51636 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51637 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51638 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51639 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51640 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51641 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51642 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51643 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51644 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51645 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51646 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51647 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51648 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51649 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51650 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51651 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51652 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51653 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51654 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51655 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51656 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51657 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51659 …-idle state, trying to start new TX arbitration depends on the GO mode as follows: 0 - start new T…
51662 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51663 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51664 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51665 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51666 …when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqLineCrd; b1 - Err_…
51667 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51668 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51669 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51670 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51671 …when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqByteCrd; b1 - Err_…
51680 …set the mem is initiazlied. when reset the mem in not initiazlied. There is mask bit per mem, the …
51681 …set the mem is initiazlied. when reset the mem in not initiazlied. There is mask bit per mem, the …
51682 …tialized with all ones. when reset the mem in initialized with all zeroes. There is bit per mem, t…
51683 …tialized with all ones. when reset the mem in initialized with all zeroes. There is bit per mem, t…
51684 …ly being initialized. There is status bit per mem, the following are mems 31-0: b0: qm_mem_bigram_…
51685 …ly being initialized. There is status bit per mem, the following are mems 63-32: b32: qm_mem_cfc_l…
51689 … 0x2f5da8UL //Access:R DataWidth:0x16 // Provides read-only access to the BI…
51936 …th:0x4 // The status of the TX PQ-s: bit0 - PQ global VP/QCN RL block; bit1 - PQ active; bit2 -…
51939 …- PQ valid; bits 8:1 - RL id; bits 17:9 - VP id (value of all ones is reserved for pure-LB VOQ …
51945 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51948 …-init mode. In init mode should be written with the same value of WfqVpUpperBound. Sign: the msb i…
51951 … between VP WFQ counter and its resources as follows: bit 5:0 - Voq id; bit 9:6 - Pf id; Som…
51954 …0UL //Access:WB DataWidth:0x36 // Pointer Table Memory for TX queues 447-0; The mapping is as …
51957 …-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb i…
51958 …-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb i…
51961 …-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM se…
51962 …-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM se…
51964 … // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mo…
51965 … // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mo…
51969 …it and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of …
51970 …it and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of …
51974 … // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mo…
51975 … // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mo…
51979 …0x18 // The init and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16.
51980 …it and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16. Some VOQs are …
51984 …- VOQs [0..31]. AFullQmBypThrLineVoqMask_msb (This one) - VOQs [32..35]. Some VOQs are "not used" …
51985 …F RL mechanism per VOQ. RlPfVoqEnable - VOQs [0..31]. RlPfVoqEnable_msb (This one) …
51986 …- VOQs [0..31]. VoqCrdLineFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51987 …- VOQs [0..31]. VoqCrdByteFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51989 …dth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
52004 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52005 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52007 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52008 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52013 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52014 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52016 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52017 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52021 … 0x3000ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52022 … 0x3000d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52026 …n from their E4 place and used accordingly. When reset E5 functionality i…
52106 …-7). Do not read from address[3:5]=i if debug_error_data_valid[i] isn't set. Bits [2:0] in the add…
52117 …-Initial reference tag Address offset-0 bits [31:0]; Field name-Application tag value Address offs…
52118 …- Has 8 QWORDs per task allocated (All are valid). In RDIF - Has 8 QWORDs per task allocated (QWOR…
52122 …dth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
52138 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52139 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52141 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52142 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52147 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52148 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52150 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52151 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52155 … 0x3100ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52156 … 0x3100d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52158 … 0x3100d8UL //Access:R DataWidth:0x1b // [3:0] - error type ([0] Writ…
52176 …n from their E4 place and used accordingly. When reset E5 functionality i…
52311 …-7). Do not read from address[3:5]=i if debug_error_data_valid[i] isn't set. Bits [2:0] in the add…
52322 …- Has 8 QWORDs per task allocated (All are valid). In RDIF - Has 8 QWORDs per task allocated (QWOR…
52373 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_…
52374 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_…
52389 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52447 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_…
52448 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_…
52463 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52473 …- if this bit is set then initialization of link list; all head; tail and start_en registers will …
52474 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
52475 … BRTB will not be able to get packets from write clients when this bit is reset. If link list was …
54848 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
54849 …-bytes resolution. After this number of bytes will input to BRTB will be sent packet available ind…
54856 …et is released::s/MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_R…
54857 …te more requests till reset in a case of length error other way it will continue to work as usual.…
54858 …- SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for…
54861 …Reset value is right for 128B block size only. It should be twice smaller for 256B block size. Whe…
54864 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54865 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54866 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54867 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54868 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54869 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54870 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54871 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54872 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54873 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54874 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54875 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54876 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54877 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54878 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54879 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54880 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54881 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54882 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54883 …taWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
54884 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54885 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54886 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54887 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54888 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54889 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54890 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54891 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54892 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54893 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54894 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54895 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54896 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54897 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54898 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54899 … not used by the TC. There is configuration for each TC in each main port.Reset value is right for…
54900 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54901 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54902 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54903 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54904 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54905 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54906 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54907 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54908 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54909 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54910 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54911 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54912 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54913 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54914 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54915 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54916 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54917 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54918 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54919 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
54920 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54921 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54922 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54923 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54924 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54925 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54926 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54927 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54928 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54929 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54930 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54931 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54932 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54933 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54934 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54935 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54936 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54937 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54938 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54939 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54940 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54941 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54942 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54943 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54944 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54945 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54946 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54947 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54948 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54949 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54950 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54951 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54952 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54953 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54954 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54955 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54956 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54957 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54958 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54959 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54960 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54961 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54962 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54963 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54964 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54965 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54966 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54967 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54968 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54969 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54970 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54971 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54972 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54973 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54974 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54975 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54976 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54977 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54978 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54979 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54980 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54981 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54982 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54983 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54984 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54985 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54986 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54987 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54988 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54989 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54990 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54991 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54992 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54993 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54994 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54995 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54996 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54997 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54998 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54999 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55000 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55001 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55002 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55003 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55004 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55005 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55006 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55007 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55008 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55009 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55010 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55011 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55012 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55013 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55014 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55015 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55016 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55017 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55018 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55019 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55020 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55021 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55022 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55023 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55024 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55025 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55026 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55027 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55033 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55034 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55035 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55036 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55037 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55038 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55039 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55040 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55041 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55042 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55043 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55044 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55045 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55046 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55047 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55048 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55049 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55050 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55051 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55052 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55053 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55054 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55055 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55056 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55057 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55058 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55059 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55060 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55061 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55062 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55063 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55065 …rted when number of allocated blocks in TC bigger lossless_threshold, if 0 - then full to that TC…
55068 … BRTB above which stop parsing interface is asserted::s/BLK_NUM/4800/g in Reset Value::s/BLK_WDTH/…
55069 …sserted::s/BLK_WDTH_PLUS_7/20/g in Data Width::s/BYTE_CNT_RST/614400/g in Reset Value::/PAUSE_EN/d…
55070 …cycles.B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE_RST/1/g in Reset Value::s/NO_DEAD…
55072 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
55074 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
55076 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
55078 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
55080 … priority then selection between them is done with RR. Possible values are 1-3. Priority 7 is high…
55082 …ten without intra packet dead cycles .B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE_RS…
55083 …enabled for the corresponding client. B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE_RS…
55084 …client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_SOP_PRI_RST/5/g in…
55085 …lient to BIG RAM arbiters. Possible values are 0-7. Priority 7 is highest::s/RC_EOP_PRI_RST/4/g in…
55086 …t group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7/g in…
55087 …cal priority is supported. Possible values are 1-3. Priority 3 is highest::s/RC_MULT_PRI_RST/6/g i…
55094 …ient upper which full outputs to this write client interface.::s/DSCR_FIFO_RST/12/g in Reset Value.
55095 …ient upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.
55097 …hreshold_mac_n is asserted to power management block::s/BLK_NUM/4800/g in Reset Value::s/BLK_WDTH/…
55099 … TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP…
55100 … TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP…
55101 … TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP…
55102 … TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP…
55116 …-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When…
55118 …- IF0, B1- IF1. When bit is set then appropriate interface is enabled. When bit is reset then requ…
55120 …rface. When bit is set then appropriate interface is enabled. When bit is reset then request from …
55122 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
55125 …-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When…
55127 …- IF0, B1- IF1. When bit is set then appropriate interface is enabled.When bit is reset then valid…
55129 …rface. When bit is set then appropriate interface is enabled. When bit is reset then valid to that…
55131 … reset then any pause will never be set. This bit should be set after init procedure. ::s/SHARE_GR…
55133 …reset then empty interface will never be set. This bit should be set after init procedure. ::s/MAX…
55135 …s. When bit is set then packet avalable interface is enabled. When bit is reset then packet avalab…
55137 …aces. When bit is set then stop parsing interface is enabled. When bit is reset then stop parsing …
55139 … When bit is set then power management interface is enabled. When bit is reset then power manage…
55141 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55142 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55143 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55144 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55145 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55146 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55147 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55148 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55149 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55150 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55151 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55152 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55153 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55154 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55155 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55156 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55159 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55160 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55161 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55162 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55163 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55164 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55165 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55166 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55167 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55168 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55169 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55170 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55171 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55172 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55173 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55174 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55175 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55176 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
55209 … Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d…
55210 … Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d…
55211 … Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d…
55212 … Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d…
55241 … Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d…
55242 … Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d…
55243 … Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d…
55244 … Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d…
55291 …te client. It contains: b31 - valid; b30:16 - queue size; b15:0 - queue start pointer::s/SOP_STATU…
55294 …ister for each erad packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelli…
55296 …ister for each read packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelli…
55298 …-port per-TC counters. In BigBear, entries 0-7 are port 0 (main 0) TCs 0-7. Entries 8-16 are port …
55301 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55303 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55305 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55307 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55309 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55311 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55313 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55315 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55325 …total port's used shared area crosses (down) this number, over subscription is reset for this port.
55330 …Access:RW DataWidth:0xe // Link list dual port memory that contains per-block descriptor::s/B…
55331 …Access:RW DataWidth:0xf // Link list dual port memory that contains per-block descriptor::s/B…
55367 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
55368 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
55370 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55371 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55372 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55373 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55374 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55375 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55376 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55377 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55378 …0x4c00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55379 …0x4c00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55380 …0x4c00bcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55381 …0x4c00c0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55383 …:0x8 // Logging register for segment message error: bits 3:0 - header len; bits 7:4 - number of…
55384 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 31:0 of the seg…
55385 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 63:32 of the se…
55386 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 95:64 of the se…
55392 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55401 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55403 … (0x1<<3) // Mini cache error - meaning that A load …
55405 … (0x1<<4) // Mini cache error - meaning that A load …
55427 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55429 … (0x1<<3) // Mini cache error - meaning that A load …
55431 … (0x1<<4) // Mini cache error - meaning that A load …
55440 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55442 … (0x1<<3) // Mini cache error - meaning that A load …
55444 … (0x1<<4) // Mini cache error - meaning that A load …
55521 … 0x4c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55523 … 0x4c0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55528 …reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated…
55530 … (0x1<<2) // defines that only back-to-back aggregation is …
55549 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
55551 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
55553 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
55555 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
55558 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
55560 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
55562 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
55564 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
55567 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
55569 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
55571 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
55573 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
55576 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
55578 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
55580 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
55582 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
55618 … 0x4c0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55619 … 0x4c0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55620 … 0x4c092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55621 … 0x4c0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55622 … 0x4c0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55623 … 0x4c0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55624 … 0x4c093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55625 … 0x4c0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55626 … 0x4c0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55627 … 0x4c0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55628 … 0x4c094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55629 … 0x4c0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55630 … 0x4c0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55631 … 0x4c0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55632 … 0x4c095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55633 … 0x4c0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55634 … 0x4c0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55635 … 0x4c0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55636 … 0x4c096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55637 … 0x4c0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55638 … 0x4c0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55639 … 0x4c0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55640 … 0x4c097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55641 … 0x4c0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55642 … 0x4c0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55643 … 0x4c0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55644 … 0x4c098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55645 … 0x4c0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55646 … 0x4c0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55647 … 0x4c0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55648 … 0x4c099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55649 … 0x4c09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55651 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
55653 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
55655 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
55657 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
55660 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
55662 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
55664 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
55666 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
55669 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
55671 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
55673 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
55675 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
55678 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
55680 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
55682 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
55684 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
55723 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
55725 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
55727 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
55729 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
55731 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
55733 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
55735 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
55737 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
55758 … (0xff<<0) // The value by which to increment the event-ID in case of success…
55760 … (0xff<<8) // The value by which to increment the event-ID in case of success…
55762 … (0xff<<16) // The value by which to increment the event-ID in case of success…
55764 … (0xff<<24) // The value by which to increment the event-ID in case of success…
55767 …2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
55768 …2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
55769 …2 // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
55770 …2 // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
55771 …2 // The weight of queue 2 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
55772 …2 // The weight of queue 3 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
55787 …2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
55788 …2 // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
55813 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
55814 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
55816 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55817 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55818 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55819 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55820 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55821 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55822 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55823 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55824 …0x4c8098UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55825 …0x4c809cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55826 …0x4c80a0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55827 …0x4c80a4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55832 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55841 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55843 … (0x1<<3) // Mini cache error - meaning that A load …
55845 … (0x1<<4) // Mini cache error - meaning that A load …
55867 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55869 … (0x1<<3) // Mini cache error - meaning that A load …
55871 … (0x1<<4) // Mini cache error - meaning that A load …
55880 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55882 … (0x1<<3) // Mini cache error - meaning that A load …
55884 … (0x1<<4) // Mini cache error - meaning that A load …
55902 … 0x4c8400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55904 … 0x4c8800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55925 …the BRB read response buffer. The slot size would be the BRB-response-buffer-size/number-of-slots.…
55928 …data returning from the BRB is swapped. meaning that bytes 0-3 is swapped with bytes 4-7 in …
55929 …30UL //Access:RW DataWidth:0x3 // Max credit number for the BRB request-resonse interface::/M…
55949 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
55950 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
55952 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55953 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55954 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55955 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55956 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55957 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55958 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55959 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55960 …0x4d00acUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55961 …0x4d00b0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55962 …0x4d00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55963 …0x4d00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55968 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55977 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55979 … (0x1<<3) // Mini cache error - meaning that A load …
55981 … (0x1<<4) // Mini cache error - meaning that A load …
56003 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56005 … (0x1<<3) // Mini cache error - meaning that A load …
56007 … (0x1<<4) // Mini cache error - meaning that A load …
56016 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56018 … (0x1<<3) // Mini cache error - meaning that A load …
56020 … (0x1<<4) // Mini cache error - meaning that A load …
56083 … 0x4d0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56085 … 0x4d0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56090 …reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated…
56092 … (0x1<<2) // defines that only back-to-back aggregation is …
56111 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
56113 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
56115 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
56117 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
56120 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
56122 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
56124 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
56126 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
56129 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
56131 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
56133 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
56135 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
56138 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
56140 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
56142 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
56144 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
56180 … 0x4d0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56181 … 0x4d0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56182 … 0x4d092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56183 … 0x4d0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56184 … 0x4d0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56185 … 0x4d0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56186 … 0x4d093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56187 … 0x4d0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56188 … 0x4d0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56189 … 0x4d0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56190 … 0x4d094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56191 … 0x4d0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56192 … 0x4d0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56193 … 0x4d0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56194 … 0x4d095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56195 … 0x4d0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56196 … 0x4d0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56197 … 0x4d0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56198 … 0x4d096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56199 … 0x4d0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56200 … 0x4d0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56201 … 0x4d0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56202 … 0x4d097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56203 … 0x4d0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56204 … 0x4d0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56205 … 0x4d0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56206 … 0x4d098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56207 … 0x4d0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56208 … 0x4d0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56209 … 0x4d0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56210 … 0x4d099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56211 … 0x4d09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56213 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
56215 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
56217 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
56219 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
56222 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
56224 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
56226 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
56228 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
56231 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
56233 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
56235 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
56237 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
56240 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
56242 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
56244 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
56246 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
56285 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
56287 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
56289 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
56291 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
56293 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56295 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56297 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56299 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56320 … (0xff<<0) // The value by which to increment the event-ID in case of success…
56322 … (0xff<<8) // The value by which to increment the event-ID in case of success…
56324 … (0xff<<16) // The value by which to increment the event-ID in case of success…
56326 … (0xff<<24) // The value by which to increment the event-ID in case of success…
56329 …2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
56330 …2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
56331 …2 // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
56332 …2 // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
56333 …2 // The weight of queue 2 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
56334 …2 // The weight of queue 3 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
56349 …2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
56350 …2 // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
56351 …2 // The weight of queue 2 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
56352 …2 // The weight of queue 3 at the WRR arbiteration, in case its bit is reset at scbd_strict_pri…
56353 … 0x4e0014UL //Access:RW DataWidth:0x4 // Log 2 of the BD size in bytes - 2:BD size is 4bytes;…
56355 …0x4e001cUL //Access:RW DataWidth:0x4 // Log 2 of the SGE size in bytes - 2:SGE size is 4bytes…
56389 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
56390 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
56392 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56393 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56394 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56395 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56396 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56397 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56398 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56399 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56400 …0x4e00d0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56401 …0x4e00d4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56402 …0x4e00d8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56403 …0x4e00dcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56408 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
56417 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56419 … (0x1<<3) // Mini cache error - meaning that A load …
56421 … (0x1<<4) // Mini cache error - meaning that A load …
56443 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56445 … (0x1<<3) // Mini cache error - meaning that A load …
56447 … (0x1<<4) // Mini cache error - meaning that A load …
56456 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56458 … (0x1<<3) // Mini cache error - meaning that A load …
56460 … (0x1<<4) // Mini cache error - meaning that A load …
56557 … 0x4e0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56559 … 0x4e0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56561 … 0x4e0c00UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue2 - Debug access::/TMLD_…
56563 … 0x4e1000UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue3 - Debug access::/TMLD_…
56568 …reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated…
56570 … (0x1<<2) // defines that only back-to-back aggregation is …
56589 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
56591 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
56593 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
56595 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
56598 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
56600 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
56602 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
56604 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
56607 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
56609 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
56611 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
56613 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
56616 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
56618 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
56620 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
56622 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
56658 … 0x4e1424UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56659 … 0x4e1428UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56660 … 0x4e142cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56661 … 0x4e1430UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56662 … 0x4e1434UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56663 … 0x4e1438UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56664 … 0x4e143cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56665 … 0x4e1440UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56666 … 0x4e1444UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56667 … 0x4e1448UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56668 … 0x4e144cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56669 … 0x4e1450UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56670 … 0x4e1454UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56671 … 0x4e1458UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56672 … 0x4e145cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56673 … 0x4e1460UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56674 … 0x4e1464UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56675 … 0x4e1468UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56676 … 0x4e146cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56677 … 0x4e1470UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56678 … 0x4e1474UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56679 … 0x4e1478UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56680 … 0x4e147cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56681 … 0x4e1480UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56682 … 0x4e1484UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56683 … 0x4e1488UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56684 … 0x4e148cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56685 … 0x4e1490UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56686 … 0x4e1494UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56687 … 0x4e1498UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56688 … 0x4e149cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56689 … 0x4e14a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56691 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
56693 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
56695 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
56697 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
56700 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
56702 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
56704 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
56706 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
56709 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
56711 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
56713 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
56715 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
56718 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
56720 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
56722 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
56724 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
56763 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
56765 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
56767 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
56769 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
56771 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56773 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56775 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56777 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56798 … (0xff<<0) // The value by which to increment the event-ID in case of success…
56800 … (0xff<<8) // The value by which to increment the event-ID in case of success…
56802 … (0xff<<16) // The value by which to increment the event-ID in case of success…
56804 … (0xff<<24) // The value by which to increment the event-ID in case of success…
56819 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
56823 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
57206 … (0x1<<0) // Error in the pure-loopback SOPQ.
57296 … (0x1<<0) // Error in the pure-loopback SOPQ.
57341 … (0x1<<0) // Error in the pure-loopback SOPQ.
57534 … (0x1<<0) // Error in the pure-loopback SOPQ.
57624 … (0x1<<0) // Error in the pure-loopback SOPQ.
57669 … (0x1<<0) // Error in the pure-loopback SOPQ.
57862 … (0x1<<0) // Error in the pure-loopback SOPQ.
57952 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
57997 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58190 … (0x1<<0) // Error in the pure-loopback SOPQ.
58280 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58325 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
59324 …0x1 // Close-gate function disable bit: 0 - egress drain mode is enabled when close-gate input…
59326 …ccess:RW DataWidth:0x10 // The Ethernet type value for L2 tag 1. The reset value is 9x8100 fo…
59331 … 0x50081cUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59332 … 0x500820UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59333 … 0x500824UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59334 … 0x500828UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59335 … 0x50082cUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59336 … 0x500830UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59338 …RX packets. 0 is for XSTORM; 1 is for YSTORM. This configuration should be static during run-time.
59339 …get the current credit count on the interface. This configuration should be static during run-time.
59343 … (0x1<<8) // T-bit to be used in CM …
59349 …0x1 // Global configuration for selecting whether to drop the per-PF drop and per-VPORT drop pa…
59350 … 0x500848UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59351 … 0x50084cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59352 … 0x500850UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59353 … 0x500854UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59354 … 0x500858UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59355 … 0x50085cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59356 … 0x500860UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59357 … 0x500864UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59358 … 0x500868UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59359 … 0x50086cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59360 … 0x500870UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59361 … 0x500874UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59362 … 0x500878UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59363 … 0x50087cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59364 … 0x500880UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59365 … 0x500884UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59366 … 0x500888UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59367 … 0x50088cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59368 … 0x500890UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59369 … 0x500894UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59370 … 0x500898UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59371 … 0x50089cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59372 … 0x5008a0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59373 … 0x5008a4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59374 … 0x5008a8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59375 … 0x5008acUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59376 … 0x5008b0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59377 … 0x5008b4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59378 … 0x5008b8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59379 … 0x5008bcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59380 … 0x5008c0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59381 … 0x5008c4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59382 … 0x5008c8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59383 … 0x5008ccUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59384 … 0x5008d0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59385 … 0x5008d4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59386 … 0x5008d8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59387 … 0x5008dcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59388 … 0x5008e0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59389 … 0x5008e4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59390 … 0x5008e8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59391 … 0x5008ecUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59392 … 0x5008f0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59393 … 0x5008f4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59394 … 0x5008f8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59395 … 0x5008fcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59396 … 0x500900UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59397 … 0x500904UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59398 … 0x500908UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59399 … 0x50090cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59400 … 0x500910UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59401 … 0x500914UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59402 … 0x500918UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59403 … 0x50091cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59404 … 0x500920UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59405 … 0x500924UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59406 … 0x500928UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59407 … 0x50092cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59408 … 0x500930UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59409 … 0x500934UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59410 … 0x500938UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59411 … 0x50093cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59412 … 0x500940UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59413 … 0x500944UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59414 … 0x500948UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59415 … 0x50094cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59416 … 0x500950UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59417 … 0x500954UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59418 … 0x500958UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59419 … 0x50095cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59420 … 0x500960UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59421 … 0x500964UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59422 … 0x500968UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59423 … 0x50096cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59424 … 0x500970UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59425 … 0x500974UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59426 … 0x500978UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59427 … 0x50097cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59428 … 0x500980UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59429 … 0x500984UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59430 … 0x500988UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59431 … 0x50098cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59432 … 0x500990UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59433 … 0x500994UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59434 … 0x500998UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59435 … 0x50099cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59436 … 0x5009a0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59437 … 0x5009a4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59438 … 0x5009a8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59439 … 0x5009acUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59440 … 0x5009b0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59441 … 0x5009b4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59442 … 0x5009b8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59443 … 0x5009bcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59444 … 0x5009c0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59445 … 0x5009c4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59446 … 0x5009c8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59447 … 0x5009ccUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59448 … 0x5009d0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59449 … 0x5009d4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59450 … 0x5009d8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59451 … 0x5009dcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59452 … 0x5009e0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59453 … 0x5009e4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59454 … 0x5009e8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59455 … 0x5009ecUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59456 … 0x5009f0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59457 … 0x5009f4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59458 … 0x5009f8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59459 … 0x5009fcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59460 … 0x500a00UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59461 … 0x500a04UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59462 … 0x500a08UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59463 … 0x500a0cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59464 … 0x500a10UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59465 … 0x500a14UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59466 … 0x500a18UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59467 … 0x500a1cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59468 … 0x500a20UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59469 … 0x500a24UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59470 … 0x500a28UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59471 … 0x500a2cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59472 … 0x500a30UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59473 … 0x500a34UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59474 … 0x500a38UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59475 … 0x500a3cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59476 … 0x500a40UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59477 … 0x500a44UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59478 … 0x500a48UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59479 … 0x500a4cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59480 … 0x500a50UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59481 … 0x500a54UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59482 … 0x500a58UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59483 … 0x500a5cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59484 … 0x500a60UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59485 … 0x500a64UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59486 … 0x500a68UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59487 … 0x500a6cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59488 … 0x500a70UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59489 … 0x500a74UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59490 … 0x500a78UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59491 … 0x500a7cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59492 … 0x500a80UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59493 … 0x500a84UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59494 … 0x500a88UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59495 … 0x500a8cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59496 … 0x500a90UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59497 … 0x500a94UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59498 … 0x500a98UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59499 … 0x500a9cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59500 … 0x500aa0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59501 … 0x500aa4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59502 … 0x500aa8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59503 … 0x500aacUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59504 … 0x500ab0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59505 … 0x500ab4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59506 … 0x500ab8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59507 … 0x500abcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59508 … 0x500ac0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59509 … 0x500ac4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59510 … 0x500ac8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59511 … 0x500accUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59512 … 0x500ad0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59513 … 0x500ad4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59514 … 0x500ad8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59515 … 0x500adcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59516 … 0x500ae0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59517 … 0x500ae4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59518 … 0x500ae8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59519 … 0x500aecUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59520 … 0x500af0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59521 … 0x500af4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59522 … 0x500af8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59523 … 0x500afcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59524 … 0x500b00UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59525 … 0x500b04UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59526 … 0x500b08UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59527 … 0x500b0cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59528 … 0x500b10UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59529 … 0x500b14UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59530 … 0x500b18UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59531 … 0x500b1cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59532 … 0x500b20UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59533 … 0x500b24UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59534 … 0x500b28UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59535 … 0x500b2cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59536 … 0x500b30UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59537 … 0x500b34UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59538 … 0x500b38UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59539 … 0x500b3cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59540 … 0x500b40UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59541 … 0x500b44UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59542 … 0x500b48UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59543 … 0x500b4cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59544 … 0x500b50UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59545 … 0x500b54UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59546 … 0x500b58UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59547 … 0x500b5cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59548 … 0x500b60UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59549 … 0x500b64UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59550 … 0x500b68UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59551 … 0x500b6cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59552 … 0x500b70UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59553 … 0x500b74UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59554 … 0x500b78UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59555 … 0x500b7cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59556 … 0x500b80UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59557 … 0x500b84UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59558 … 0x500c00UL //Access:RW DataWidth:0x1 // Per-PF drop configuration…
59561 …0cUL //Access:R DataWidth:0x18 // TX SOP descriptor queue empty status - for main traffic que…
59562 …c10UL //Access:R DataWidth:0x18 // TX SOP descriptor queue full status - for main traffic que…
59563 … DataWidth:0x40 // Addresses for TimeSync related registers in the timesync generator sub-module.
59567 …1 // Output enable for the STORM interface. This configuration should be static during run-time.
59580 …00UL //Access:RW DataWidth:0x4 // Size of the proprietary header, in 32-bit words, that is pr…
59586 …-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer tag);…
59587 … 0x50101cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59588 … 0x501020UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59589 …01024UL //Access:RW DataWidth:0x8 // Bit-map indicating which L2 hdrs may appear after L2 tag…
59590 … 0x501028UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59591 … 0x50102cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59592 … 0x501030UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59593 … 0x501034UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59594 …-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer tag);…
59595 … 0x50103cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59596 … 0x501040UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59597 …01044UL //Access:RW DataWidth:0x8 // Bit-map indicating which L2 hdrs may appear after L2 tag…
59598 … 0x501048UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59599 … 0x50104cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59600 … 0x501050UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59601 … 0x501054UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59603 … (0x1<<0) // Enable bit for Ethernet-over-GRE (L2 GRE) encaps…
59605 … (0x1<<1) // Enable bit for IP-over-GRE (IP GRE) encaps…
59612 … 0x501068UL //Access:RW DataWidth:0x10 // FCOE Ethertype - default is 0x8906.
59617 … 0x50107cUL //Access:RW DataWidth:0x8 // IPv4 protocol field for ICMPv4 - defaults to 0x01.
59618 … 0x501080UL //Access:RW DataWidth:0x8 // IPv6 next header field for ICMPv6 - defaults to 0x3A.
59651 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_0: 0 - IPv6; 1-IPv4.
59652 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_1: 0 - IPv6; 1-IPv4.
59653 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_2: 0 - IPv6; 1-IPv4.
59761 … for forwarding packets for each PF to MCP in multifunction mode. This is a per-PF split register.
59863 … forwarding packets for the PF to the host in multifunction mode. This is a per-PF split register.
59889 …for comparison. A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-80-C2-00-00-0F.
60009 … for comparison. A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-80-C2-00-00-0F.
60127 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60147 …- message FIFO empty. Bit 1 - descriptor FIFO empty. Bit 2 - message FIFO has more than 32 entries…
60148 …-to-send data remaining below which ETS arbiter for the LB path should start selecting the next pa…
60150 … 0x501508UL //Access:RW DataWidth:0x1 // Zero-padding enable for LB…
60156 … DataWidth:0x20 // Increment PERIOD for the BRB interface rate limiter - in term of 25MHz clo…
60157 …W DataWidth:0x20 // Increment VALUE for the BRB interface rate limiter - in term of bytes, cy…
60158 … DataWidth:0x20 // Upper bound VALUE for the BRB interface rate limiter - in term of bytes, cy…
60161 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60163 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60166 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60168 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60171 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60173 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60176 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60178 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60181 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60183 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60186 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60188 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60191 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60193 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60196 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60198 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60200 …40UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60201 …44UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60202 …48UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60203 …4cUL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60204 …50UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60205 …54UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60206 …58UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60207 …5cUL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60208 …560UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60209 …564UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60210 …568UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60211 …56cUL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60212 …570UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60213 …574UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60214 …578UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60215 …57cUL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60216 …0UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60217 …4UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60218 …8UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60219 …cUL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60220 …0UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60221 …4UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60222 …8UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60223 …cUL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60232 …lient): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6…
60233 …lient): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6…
60234 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60235 …-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6-TC5 traf…
60237 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
60239 … 0x5015e0UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbitration mo…
60260 …0x501634UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60261 …0x501638UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60262 …0x50163cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60263 …0x501640UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60264 …0x501644UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60265 …0x501648UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60266 …0x50164cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60267 …0x501650UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60268 …0x501654UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60269 …0x501658UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60272 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60293 … 0x501910UL //Access:RW DataWidth:0x1 // Enable for SW-specified packet time…
60297 …-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 0xFF0*:0:0:0:0:0:0:181. …
60298 …-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP …
60299 …-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 0xFF0*:0:0:0:0:0:0:181. …
60300 …-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP …
60301 …s:RW DataWidth:0x11 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60302 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60303 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60304 …s:RW DataWidth:0x11 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60305 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60306 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60307 …s:RW DataWidth:0x13 // Packet TimeSync information that is buffered in 1-deep FIFOs for TX sid…
60308 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
60309 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
60310 …-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp val…
60311 …-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp val…
60312 …e PFID for port 3 is based on the translation table entry 3 of port 3. If reset default values are…
60313 …ased on tag/VLAN/MAC matching. 2: classification based on protocol. 3: dual-stage classification.…
60314 …-stage classification mode; value of 0: AND the hit vectors; value of 1: OR the hit vectors; value…
60315 …Default per-port value to be used when protocol-based classification fails. This is the per-port …
60316 …lt per-port value to be used when outer-tag/inner VLAN/MAC classification fails. This is the per…
60317 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60318 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60319 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60320 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60321 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60322 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60323 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60324 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60325 …-bit field immediately following the Ethertype to be used for each of the outer tag value bit. The…
60330 …-port per-PF register. This register selects the classification type for the tag/VLAN/MAC mode. …
60331 … 0x5019b0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60333 … 0x5019c0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60335 … 0x5019d0UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. Per-function…
60337 … 0x5019e0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60338 …er-port per-PF register. Per-function MAC addresses to be matched with for MAC-address-based clas…
60340 … 0x501a80UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60342 …-port per-PF register. Per-function mode select bit to indicate whether the filter is to be used …
60344 …7 // This is a per-port per-PF register. Per-function select bits for the different protocol t…
60346 … 0x501b40UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60348 …e. 0 selects connection-based classification. 1 selects the PF-based classification. This regist…
60349 …-tuple search for TCP packets. Set this bit to use the TCP 4-tuple (TCP source and destination po…
60350 …-tuple search for UDP packets. Set this bit to use the UDP 4-tuple (UDP source and destination po…
60351 …ed to hash the data string in connection-based engine classification. This register is used only …
60352 …-entry Engine ID lookup table, with 1 bit per entry. Set the bit to 1 to have packets associated …
60354 …ts one of the 24-bit destination QP bits to be used as the engine ID. Valid values are 0-23. Thi…
60355 …-global-PF engine ID to be used in PF-based engine classification. Set the bit to 1 to have packe…
60356 …ss:RW DataWidth:0x3 // Flow control mode. 0 - disable; 1 - PFC; 2 - LLFC; 3 - PPP; 4 - PAUSE…
60357 … 0x501ba4UL //Access:RW DataWidth:0x20 // Eight 4-bit configurations for specifying which TC (…
60359 …ting the packet priority information. Valid values are 2-5 for selecting one of the L2 tags 2-5. …
60361 …(0xf<<3) // Bit offset in the outer tag starting from which to extract the 3-bit packet priority i…
60363 …f<<7) // Bit offset in the selected tag starting from which to extract the 3-bit packet priority i…
60365 …-TC full signals. This register may change during run time. Packet truncation/discarding affects…
60367 … 0x501bb4UL //Access:RW DataWidth:0x8 // Per-TC flow control enabl…
60368 … 0x501bb8UL //Access:RW DataWidth:0x8 // Per-TC flow control enabl…
60369 … 0x501bbcUL //Access:RW DataWidth:0x9 // Per-TC flow control enabl…
60370 …DataWidth:0x1 // Enable bit for the no-drop-hdr-ind field of the LB-only-header. When set, the…
60371 …-drop of LB packets with the no-drop-hdr-ind bit set due to per-TC full backpressure from the BRB.…
60372 …cifies the number of 256-bit cycles, starting from the SOP cycle, of the packet not to be dropped …
60373 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60374 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60375 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60376 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60377 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60378 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60379 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60380 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60381 … 0x501becUL //Access:RW DataWidth:0x10 // Bit-map indicating which …
60382 … 0x501bf0UL //Access:RW DataWidth:0x10 // Bit-map indicating which …
60383 … 0x501bf4UL //Access:RW DataWidth:0x10 // Bit-map indicating which …
60384 … 0x501bf8UL //Access:RW DataWidth:0x10 // Bit-map indicating which …
60385 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60386 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60387 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60388 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60393 …ain mode starts immediately upon assertion and stops at the next packet boundary upon de-assertion.
60394 …rts immediately upon assertion and stops at the next packet boundary upon de-assertion. Note that…
60395 …hen enabled -- draining of the corrresponding TC starts immediately - packet data are dropped and…
60396 …hen enabled -- draining of the corrresponding TC starts immediately - packet data are dropped and…
60436 … // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statist…
60454 …dropped due to buffer full. This is an RF generated RC statistics register - reading this registe…
60455 …uncated due to buffer full. This is an RF generated RC statistics register - reading this registe…
60497 … // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statist…
60498 …the TX packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the MCP/per…
60499 …// Statistic register for the number of TX packets that have the per-PF drop or per-VPORT drop con…
60500 …f the LB packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the per-T…
60501 …-PF drop or per-VPORT drop configuration set while the no-drop-hdr-ind in the packet is cleared. T…
60568 …ets from BMB to be forwarded to the host that got truncated due to BRB LB per-TC full backpressure.
60569 …ckets from BMB to be forwarded to the host that got dropped due to BRB LB per-TC full backpressure.
60570 … 0x501f08UL //Access:RW DataWidth:0x1 // Zero-padding enable for TX…
60576 …-to-transmit data remaining below which ETS arbiter for the transmit path should start selecting …
60584 …ccess:RW DataWidth:0x20 // Increment PERIOD for the global rate limiter - in term of 25MHz clo…
60585 …Access:RW DataWidth:0x20 // Increment VALUE for the global rate limiter - in term of bytes, cy…
60586 …cess:RW DataWidth:0x20 // Upper bound VALUE for the global rate limiter - in term of bytes, cy…
60589 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60590 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60591 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60592 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60594 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
60596 … 0x501f50UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbitration mo…
60622 …0x501fb8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60623 …0x501fbcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60624 …0x501fc0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60625 …0x501fc4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60626 …0x501fc8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60627 …0x501fccUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60628 …0x501fd0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60629 …0x501fd4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60630 …0x501fd8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60631 …0x501fdcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60632 …0x501fe0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60633 …0x501fe4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60871 …erride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bi…
60872 …erride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bi…
60889 …n the BMC-to-host path to BRB. This is also used in the TX management path (when enabled by *tx_m…
60891 … 0x50209cUL //Access:RW DataWidth:0x1 // Host-to-MCP path enable. Se…
60895 … 0x5020acUL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
60900 … 0x5020c0UL //Access:RW DataWidth:0x7 // Almost-full threshold for DO…
60904 …. 0 - send debug traffic through port 0. 1 - send debug traffic through port 1. 2 - send debug tr…
60907 … 0x5020dcUL //Access:RW DataWidth:0x8 // Almost-full threshold for de…
60910 …- the number of valid bytes in the last cycle (0=all bytes are valid); [261]eop - active on the la…
60953 …idth:0x8 // This is a per-port per-PF register. L2 tag removal configuration for ACPI. Bit ma…
60954 … 0x508004UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Pro…
60955 …o enable ACPI pattern matching and TCP SYN matching in multi-function mode even when the per-funct…
60957 … 0x508080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
60959 … 0x508100UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Whe…
60960 … 0x508104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60961 … 0x508108UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60962 … 0x50810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60963 … 0x508110UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60964 … 0x508114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60965 … 0x508118UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60966 … 0x50811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60967 … 0x508120UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60968 … 0x508124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60969 … 0x508128UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60970 … 0x50812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60971 … 0x508130UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60972 … 0x508134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60973 … 0x508138UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60974 … 0x50813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60975 … 0x508140UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60976 … 0x508144UL //Access:RW DataWidth:0x2 // This is a per-port per-PF register. Set…
60977 …-port per-PF register. Enable bits for fields to be compared if IPv6 is present in the packet. B…
60978 …-port per-PF register. Enable bits for fields to be compared if IPv4 is present in the packet. B…
60979 … 0x508150UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60980 … 0x508154UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60981 … 0x508158UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60982 … 0x50815cUL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60983 … 0x508160UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60985 … 0x508170UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60987 … 0x508180UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60988 … 0x508184UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60989 … 0x508188UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Whe…
60990 … 0x508190UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
60992 … 0x508198UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high …
60993 … 0x5081a0UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wa…
60995 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
60996 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
60997 … - the actual length of the 'wake' packet, in bytes. This register is sticky and is cleared by wak…
60998 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
60999 …s:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
61001 …s:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
61019 …ARD � insert timestamp using standard IPv4 Timestamp option. In this mode 32-bit timestamp with se…
61022 …RW DataWidth:0x5 // Global timestamp shift for the free running counter. Legal values are 0-16
61026 …ataWidth:0x15 // RX User protocol Packet information that is buffered in 1-deep FIFOs. Bits [15…
61027 …ataWidth:0x40 // RX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp …
61029 …ataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Source add…
61031 …ataWidth:0x15 // TX User protocol Packet information that is buffered in 1-deep FIFOs. Bits [15…
61032 …ataWidth:0x40 // TX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp …
61034 …ataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Destinatio…
61048 …x5088d8UL //Access:RW DataWidth:0x1 // This is a level indication to reset drift counter's va…
61050 … 0x5088e0UL //Access:RW DataWidth:0x4 // Bits 3:0 are the active-low output enables fo…
61052 …FO data bytes occupancy is higher than this threshold nig_dorq_edpm_en is de-asserted. The value i…
61059 … // This field maps (ipv4_tos >> 2) 6 bits to 6 bits: bits 5:3 - priority bits 2:0 - TC This co…
61065 …ataWidth:0x8 // This is a per-port register L2 tag removal configuration for ACPI. Bit mapped…
61066 … 0x508b14UL //Access:RW DataWidth:0x1 // This is a per-port register. Propr…
61067 … 0x508b18UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61068 … 0x508b1cUL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61069 … 0x508b20UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61070 … 0x508b24UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61071 … 0x508b28UL //Access:RW DataWidth:0x1 // This is a per-port register. Enabl…
61072 … 0x508b2cUL //Access:RW DataWidth:0x1 // This is a per-port register. Enable…
61073 … 0x508b30UL //Access:RW DataWidth:0x1 // This is a per-port register. Perfo…
61074 … 0x508b34UL //Access:RW DataWidth:0x10 // This is a per-port register. Next …
61075 … 0x508b38UL //Access:RW DataWidth:0x10 // This is a per-port register. Destin…
61076 … 0x508b3cUL //Access:RW DataWidth:0x18 // This is a per-port register which d…
61161 …nables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.
61162 …nables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.
61163 …t reisters. This enables credit sharing with one of the BTB TCs. 0: MNG. 1-8: BTB per TC. 9: B…
61192 …ther to use the MPA CRC calculation on one fully contained PDU (legacy mode - 0) or on multiple PD…
61193 …MAC addresses to be matched with for MAC-address-based classification. This register is also used…
61197 …ter is to be used for MAC-addresss based classification or protocol-based classification. Set thi…
61199 …512 select bits for the different protocol types to be evaluated in protocol-based classification …
61203 … llh_pf_cls_func_filter_protocol_type and llh_pf_cls_func_filter_hdr_sel. Reset value is the ident…
61207 … 0x50d400UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
61209 … 0x50d800UL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
61253 …- if this bit is set then initialization of link list; all head; tail and start_en registers will …
61254 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
61255 … BRTB will not be able to get packets from write clients when this bit is reset. If link list was …
63985 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
63986 …-bytes resolution. After this number of bytes will input to BRTB will be sent packet available ind…
63993 …et is released::s/MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_R…
63994 …te more requests till reset in a case of length error other way it will continue to work as usual.…
63995 …- SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for…
63996 …Reset value is right for 128B block size only. It should be twice smaller for 256B block size. Whe…
63997 …taWidth:0xb // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
63998 …taWidth:0xb // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
63999 …taWidth:0xb // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
64000 …taWidth:0xb // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
64001 …taWidth:0xb // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
64002 …taWidth:0xb // The number of blocks guaranteed to each TC in each MAC. Reset value is right for…
64003 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
64004 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
64005 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
64006 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
64007 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
64008 …s not used by the TC. There is configuration for each TC in each LB port. Reset value is right for…
64009 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64010 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64011 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64012 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64013 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64014 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64015 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64016 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64017 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64018 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64019 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64020 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64021 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64022 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64023 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64024 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64025 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64026 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64027 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64033 …ad cycles.TBD ::s/NO_DEAD_CYCLE_RST/1/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2…
64035 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
64037 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
64039 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
64041 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
64043 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
64045 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
64047 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
64049 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
64051 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64053 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64055 …hen packet will be written without intra packet dead cycles .TBD ::s/NO_DEAD_CYCLE_RST/1/g in Reset
64056 … priority mechanism is enabled for the corresponding client. TBD ::s/NO_DEAD_CYCLE_RST/1/g in Reset
64057 …client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_SOP_PRI_RST/5/g in…
64058 …t group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7/g in…
64059 …cal priority is supported. Possible values are 1-3. Priority 3 is highest::s/RC_MULT_PRI_RST/6/g i…
64066 …ient upper which full outputs to this write client interface.::s/DSCR_FIFO_RST/12/g in Reset Value.
64067 …ient upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.
64069 … TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP…
64089 …reset then request from that interface will not be accepted. All bits of this register should be s…
64091 …rface. When bit is set then appropriate interface is enabled. When bit is reset then request from …
64093 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
64096 …reset then valid to that interface will never be asserted. All bits of this register should be set…
64098 …rface. When bit is set then appropriate interface is enabled. When bit is reset then valid to that…
64100 … reset then any pause will never be set. This bit should be set after init procedure. ::s/SHARE_GR…
64102 …s. When bit is set then packet avalable interface is enabled. When bit is reset then packet avalab…
64104 … When bit is set then power management interface is enabled. When bit is reset then power manage…
64106 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64107 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64108 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64109 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64110 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64111 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64112 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64113 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64114 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64115 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64128 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64129 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64130 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64131 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64132 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64133 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64134 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64135 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64136 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64137 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64138 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64139 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64140 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64141 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64142 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64143 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64144 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64145 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64146 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64147 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64148 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64149 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64150 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64151 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64152 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64153 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64154 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64155 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64156 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64157 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64158 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64159 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64160 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
64240 … Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d…
64247 … Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d…
64252 …te client. It contains: b31 - valid; b30:16 - queue size; b15:0 - queue start pointer::s/SOP_STATU…
64254 …s register for each erad packet client interface: TBD. Message spelling (MSB->LSB): rest_size_erro…
64257 …s register for each read packet client interface: TBD. Message spelling (MSB->LSB): opaque[1:0]; r…
64280 …Access:RW DataWidth:0xc // Link list dual port memory that contains per-block descriptor::s/B…
64285 … 0x560000UL //Access:RW DataWidth:0x1 // Initiate the ATC array - reset all the valid bit…
64287 …taWidth:0x20 // Logging register for reuse miss on transpend entry [31:0] - TID of the problemat…
64288 …taWidth:0x1c // Logging register for reuse miss on transpend entry [27:0] - ATC page index of th…
64289 …gister for reuse miss on transpend entry [11:0] - Reuse count of the problematic lookuprequest [23…
64290 …ster for the case of invalidation halt (lkpres of invalidated range) [31:0] - TID of the problemat…
64291 …ster for the case of invalidation halt (lkpres of invalidated range) [27:0] - ATC page index of th…
64292 …ster for the case of invalidation halt (lkpres of invalidated range) [11:0] - Reuse count of the p…
64294 …s of the PXP read requests issued by the PTU logic. [0:8] - ST index; [10:9] - ST hint; [11] - ST …
64301 … 0x560078UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per PF.
64304 … // Bit per PF. Indicates that the marked invalidation is done - when read it is also being reset.
64305 …uests to an address belongs to a range which is currently invalidated; if reset such requests will…
64306 … 0x56008cUL //Access:RW DataWidth:0x1 // When set - the block will halt …
64307 … 0x560090UL //Access:RW DataWidth:0x3 // Max credits of the PBF->PXP interface.
64308 … 0x560094UL //Access:RW DataWidth:0x3 // Max credits of the PRM->PXP interface.
64309 … 0x560098UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64310 … 0x56009cUL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64311 … 0x5600a0UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64320 …00c4UL //Access:RW DataWidth:0x1 // Replacement mode for the ATC. If de-asserted then low pri…
64339 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64373 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64390 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64477 …00UL //Access:RW DataWidth:0x2 // Defines the number of sets - 3 - 512 ;2- 256; 1- 128; 0- 64.
64483 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64484 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64485 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64486 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64487 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64488 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64489 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64490 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64491 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64492 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64493 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64494 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64509 … 0x560480UL //Access:RW DataWidth:0x1 // CheckTags configuration bit - when set the availab…
64510 … 0x560484UL //Access:RW DataWidth:0x8 // TAG threshold - for the checkTags fe…
64523 … 0x5604b8UL //Access:RC DataWidth:0x20 // Number of hits for Main-lookups in the ATC.
64525 … 0x5604c0UL //Access:RC DataWidth:0x20 // Number of treqs issued due to pre-lookup.
64568 …if hash_en is set. selects the CRC as hash function for the GPA table; If reset use xor of the FID…
64569 …rted request [1]; Completer abort/completion timeout [2]; Both R & W bits are reset [3]; Other [4].
64570 …rted request [1]; Completer abort/completion timeout [2]; Both R & W bits are reset [3]; Other [4].
64572 … //Access:R DataWidth:0x20 // Data belongs to an erroneous TCPL: [31:0]-bits [31:0] of the ad…
64573 … //Access:R DataWidth:0x14 // Data belongs to an erroneous TCPL: [19:0]-bits [51:32] of the a…
64578 … 0x560594UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 31-0.
64579 … 0x560598UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 63-32.
64580 … 0x56059cUL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 95-64.
64581 … 0x5605a0UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 127-96.
64582 … 0x5605a4UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 159-128.
64583 … 0x5605a8UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 191-160.
64584 … 0x5605acUL //Access:R DataWidth:0x10 // Indicates the end of FLI flow for PF 15-0.
64585 …b0UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 31-0 accordingly.
64586 …b4UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 63-32 accordingly.
64587 …8UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 95-64 accordingly.
64588 …cUL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 127-96 accordingly.
64589 …L //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 159-128 accordingly.
64590 …UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 191-160 accordingly.
64591 …c8UL //Access:RW DataWidth:0x10 // Clears the FLI done indication for PF bits 15-0 accordingly.
64610 …605e4UL //Access:RW DataWidth:0x8 // Resource Type of the invalidated range - register per PF.
64612 …er for the case of invalidation halt (lkpres of invalidated range) [7:0] - Resource type of the…
64614 …x8 // Logging register for reuse miss on transpend entry bits [35:28] - of the problematic r…
64615 …Width:0x8 // Logging register for reuse miss on transpend entry [7:0] - Resource type of the…
64617 … 0x560600UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per Strom.
64621 … 0x560640UL //Access:RW DataWidth:0x8 // TID of the invalidated range - register per Storm.
64627 …/ Bit per Storm. Indicates that the marked invalidation is done - when read it is also being reset.
64629 …uests to an address belongs to a range which is currently invalidated; if reset such requests will…
64631 …x40 // Access the GPA table way 0; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64633 …x40 // Access the GPA table way 1; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64635 …x40 // Access the GPA table way 2; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64639 …h:0x40 // Access the GPA table way3; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID-…
64641 …- {par - [51]; NS bit - [50]; W bit - [49]; R bit - [48]; U bit - [47]; Priority bit - [46]; PLRU …
64643 … // Access the GPA table way 0; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64645 … // Access the GPA table way 1; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64647 … // Access the GPA table way 2; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64649 … // Access the GPA table way3; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64651 …- { Priority bit - [23]; PLRU - [22]; Err bit - [21]; invpend bit [20]; transpend bit - [19]; vali…
64658 … (0x1<<1) // Enables CDU Inputs -- Must be set for norm…
64660 … (0x1<<2) // Enables CDU Outputs -- Must be set for nor…
64668 … (0x1<<6) // Masks all PCIE Errors for Load transactions. NOTE -- This is not connecte…
64755 …n for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64757 …n for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64759 …n for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64761 …n for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64764 …n for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64766 …n for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64768 …n for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64770 …n for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64773 …n for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64775 …n for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64777 …n for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64779 …n for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64782 …n for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64784 …n for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64786 …n for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64788 …n for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64790 …rols the Full signal to PXP. This register must never be set higher than 8 -- doing so will result…
64791 …ories when past this limit. This register must never be set higher than 13 -- doing so will result…
64872 … (0xfff<<12) // Block waste within a page. this number equals to PageSize-NCIB*ContextSize.
64904 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64910 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64911 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64922 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64923 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64924 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64925 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64926 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64927 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64928 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64929 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64930 …0x5a0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64931 …0x5a0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64932 …0x5a0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64933 …0x5a003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64936 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
64945 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64947 … (0x1<<3) // Mini cache error - meaning that A load …
64949 … (0x1<<4) // Mini cache error - meaning that A load …
64971 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64973 … (0x1<<3) // Mini cache error - meaning that A load …
64975 … (0x1<<4) // Mini cache error - meaning that A load …
64984 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64986 … (0x1<<3) // Mini cache error - meaning that A load …
64988 … (0x1<<4) // Mini cache error - meaning that A load …
65013 … 0x5a0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65018 …reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated…
65020 … (0x1<<2) // defines that only back-to-back aggregation is …
65039 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
65041 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
65043 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
65045 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
65048 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
65050 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
65052 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
65054 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
65057 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
65059 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
65061 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
65063 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
65066 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
65068 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
65070 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
65072 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
65108 … 0x5a0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65109 … 0x5a0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65110 … 0x5a082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65111 … 0x5a0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65112 … 0x5a0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65113 … 0x5a0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65114 … 0x5a083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65115 … 0x5a0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65116 … 0x5a0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65117 … 0x5a0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65118 … 0x5a084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65119 … 0x5a0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65120 … 0x5a0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65121 … 0x5a0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65122 … 0x5a085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65123 … 0x5a0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65124 … 0x5a0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65125 … 0x5a0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65126 … 0x5a086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65127 … 0x5a0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65128 … 0x5a0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65129 … 0x5a0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65130 … 0x5a087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65131 … 0x5a0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65132 … 0x5a0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65133 … 0x5a0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65134 … 0x5a088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65135 … 0x5a0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65136 … 0x5a0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65137 … 0x5a0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65138 … 0x5a089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65139 … 0x5a08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65141 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
65143 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
65145 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
65147 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
65150 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
65152 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
65154 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
65156 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
65159 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
65161 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
65163 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
65165 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
65168 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
65170 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
65172 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
65174 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
65213 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
65215 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
65217 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
65219 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
65221 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65223 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65225 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65227 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65248 … (0xff<<0) // The value by which to increment the event-ID in case of success…
65250 … (0xff<<8) // The value by which to increment the event-ID in case of success…
65252 … (0xff<<16) // The value by which to increment the event-ID in case of success…
65254 … (0xff<<24) // The value by which to increment the event-ID in case of success…
65274 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65275 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65276 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65277 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65278 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65279 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65280 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65281 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65282 …0x5c0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65283 …0x5c0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65284 …0x5c0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65285 …0x5c003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65288 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
65297 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65299 … (0x1<<3) // Mini cache error - meaning that A load …
65301 … (0x1<<4) // Mini cache error - meaning that A load …
65323 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65325 … (0x1<<3) // Mini cache error - meaning that A load …
65327 … (0x1<<4) // Mini cache error - meaning that A load …
65336 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65338 … (0x1<<3) // Mini cache error - meaning that A load …
65340 … (0x1<<4) // Mini cache error - meaning that A load …
65365 … 0x5c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65370 …reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated…
65372 … (0x1<<2) // defines that only back-to-back aggregation is …
65391 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
65393 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
65395 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
65397 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
65400 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
65402 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
65404 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
65406 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
65409 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
65411 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
65413 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
65415 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
65418 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
65420 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
65422 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
65424 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
65460 … 0x5c0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65461 … 0x5c0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65462 … 0x5c082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65463 … 0x5c0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65464 … 0x5c0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65465 … 0x5c0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65466 … 0x5c083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65467 … 0x5c0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65468 … 0x5c0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65469 … 0x5c0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65470 … 0x5c084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65471 … 0x5c0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65472 … 0x5c0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65473 … 0x5c0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65474 … 0x5c085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65475 … 0x5c0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65476 … 0x5c0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65477 … 0x5c0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65478 … 0x5c086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65479 … 0x5c0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65480 … 0x5c0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65481 … 0x5c0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65482 … 0x5c087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65483 … 0x5c0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65484 … 0x5c0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65485 … 0x5c0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65486 … 0x5c088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65487 … 0x5c0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65488 … 0x5c0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65489 … 0x5c0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65490 … 0x5c089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65491 … 0x5c08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65493 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
65495 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
65497 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
65499 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
65502 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
65504 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
65506 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
65508 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
65511 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
65513 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
65515 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
65517 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
65520 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
65522 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
65524 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
65526 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
65565 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
65567 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
65569 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
65571 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
65573 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65575 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65577 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65579 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65600 … (0xff<<0) // The value by which to increment the event-ID in case of success…
65602 … (0xff<<8) // The value by which to increment the event-ID in case of success…
65604 … (0xff<<16) // The value by which to increment the event-ID in case of success…
65606 … (0xff<<24) // The value by which to increment the event-ID in case of success…
65693 …idth:0x8 // This is a per-port per-PF register. L2 tag removal configuration for ACPI. Bit ma…
65695 … 0x608080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
65697 … 0x608100UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
65698 … 0x608104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65699 … 0x608108UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65700 … 0x60810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65701 … 0x608110UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65702 … 0x608114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65703 … 0x608118UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65704 … 0x60811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65705 … 0x608120UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65706 … 0x608124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65707 … 0x608128UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65708 … 0x60812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65709 … 0x608130UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65710 … 0x608134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65711 … 0x608138UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65712 … 0x60813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65713 … 0x608140UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65714 … 0x608144UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Whe…
65715 … 0x608148UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
65717 … 0x608150UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high …
65718 … 0x608160UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wa…
65720 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
65721 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
65722 … - the actual length of the 'wake' packet, in bytes. This register is sticky and is cleared by wak…
65723 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
65725 …election - acpi_default_pf_sel. 2: Select the first of each: 2 ports (quad_port_mode is 0) - use o…
65726 … 0x608198UL //Access:RW DataWidth:0x2 // This is a per-PF register. Set bit…
65727 … 0x60819cUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65728 … 0x6081a0UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65729 … 0x6081a4UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65730 … 0x6081a8UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65731 … 0x6081acUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65732 … 0x6081b0UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65764 …erride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bi…
65765 …erride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bi…
65766 … 0x6101f8UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65767 …ccess:RW DataWidth:0x10 // The Ethernet type value for L2 tag 1. The reset value is 9x8100 fo…
65821 … bit to 1 after finished configuring PCIe Serdes AHB registers to bring Serdes channel out of reset
65823 …this bit to 1 after finished configuring PCIe Serdes AHB registers to bring Serdes CMU out of reset
65882 … (0x1<<0) // Controls por_n_i reset signal into the SerDes. This should be 0 (…
65886 …reset mode for increased power savings. Cannot be asserted on CMU0 in multiple CMU PHYs if there a…
65911 …- rxsig_det_mask_i 16 - rxeii_exit_type_i 15 - rxei_infer_i 14 - bslip_req_i 13 - data_width_i - 0…
65913 … (0x1<<18) // Active low. lane reset signal.
65915 …pcs_sdet 0 - ln1_stat_o[2] (RX Locked indicator) 1 - ln1_astat_o[5] (Raw signal detext indicator)…
65923 …- not used 12 - ln1_ok_o 11 - ln1_runlen_err_o 10:4 - not used 3:2 - ln1_rx_locked_o - bit 3 =rxda…
65925 …(0x3f<<14) // 19 - Raw signal detect - Bit Slip Ack 18 - ln1_bitslip_ack_o - Bit Slip Ack 17 - not…
65968 …-0x1ff. Reserved = 0x200-0x3ff. LANE1 registers = 0x400-0x5ff. Reserved = 0x600-0x7f…
65973 … (0x1<<0) // Asynchronous reset, active high When …
65977 …to set0 1: Using registers belonging to set1 SETS_W-1: Using set of registers belonging to set SET…
65979 …corresponds to FLOW 1 Bit [1] : corresponds to FLOW 2 Any toggle from zero-to-one will generate an…
65984 … (0x3<<1) // It replicates the mode-sel value when voltag…
65986 … (0x7<<3) // It replicates the set-sel value when voltag…
66039 …-> MAC; 1-2 -> PHY1; 3 -> PHY3; 4 -> MAC2; 5-6 -> PHY4; 7 -> PHY6; 8 -> MAC3; …
66040 …08UL //Access:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66041 …0cUL //Access:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66042 …10UL //Access:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66043 …14UL //Access:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66045 … corresponding Physical function. 0 -> NW0 connects to PF0 1 -> NW0 connects to PF1 2 -> NW0 co…
66047 … corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connects to PF1 2 -> NW1 co…
66049 … corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1 2 -> NW2 co…
66051 … corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1 2 -> NW3 co…
66053 …1cUL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66054 …20UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66055 …24UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66056 …28UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66057 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
66071 …Reset. Asynchronous reset input signal. This signal must be asserted for a minimum of 170 ns (see …
66073 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66075 … (0x1<<2) // Power-On-Reset Power Enable. Wh…
66081 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66084 …<0) // 0x0 - Select reference clock from Bump 0x1 - Select inter-macro refrence clock from the lef…
66086 … (0x3<<2) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro ref…
66088 … (0x3<<4) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro re…
66090 …l is used for nws_nwm_sd_energy_detect. 0 - use ~lnX_stat_los_o 1 - use ~lnX_stat_los_deglitch_o (…
66092 … (0x1<<10) // Controls cpu_reset_i reset signal into the Se…
66094 …reset signal into the SerDes. This should be 0 (Reset value) while the SerDes program and data ram…
66096 …x1<<12) // Controls cm0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This …
66098 …x1<<13) // Controls cm1_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This …
66100 …x1<<14) // Controls ln0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This …
66102 …x1<<15) // Controls ln1_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This …
66104 …x1<<16) // Controls ln0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This …
66106 …x1<<17) // Controls ln3_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This …
66108 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66110 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66112 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66114 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66116 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66118 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66121 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66128 … (0x1f<<0) // Sets phy_ctrl_refclk_i used for CMU0 0x09 - refclk is 257.8125Mhz
66130 … Sets phy_ctrl_rate1_i used for CMU0 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66132 … Sets phy_ctrl_rate1_i used for CMU1 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66148 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66150 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66152 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66154 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66157 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66164 … (0x1<<0) // 0x0 - No error 0x1 - Phy has inter…
66166 … (0x1<<1) // 0x1 - Indicates CMU0 PLL h…
66168 … (0x1<<2) // 0x1 - Indicates CMU1 PLL h…
66170 … (0x1<<3) // 0x0 - PHY is not ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. The signal…
66172 … (0x1<<4) // 0x0 - PHY is not ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. The signal…
66174 … (0x1<<5) // 0x0 - PHY is not ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. The signal…
66176 … (0x1<<6) // 0x0 - PHY is not ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. The signal…
66178 … (0x1<<7) // 0x0 - PHY is not ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. The signal…
66180 … (0x1<<8) // 0x0 - PHY is not ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. The signal…
66196 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66198 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66200 … LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instea…
66204 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66207 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66209 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66211 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after reset seq…
66213 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after reset seq…
66215 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66218 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66220 … (0x1<<1) // 0x0 - data on ln0_rxdata_o is invalid. 0x1 - d…
66222 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66224 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. …
66226 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. …
66229 …Reset. Asynchronous reset input signal. This signal must be asserted for a minimum of 170 ns (see …
66231 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66233 … (0x1<<2) // Power-On-Reset Power Enable. Wh…
66239 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66261 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66268 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66270 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66272 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66274 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66276 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66278 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66280 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66282 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66284 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66288 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66294 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66296 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66314 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66316 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66318 … LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instea…
66322 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66325 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66332 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66334 … (0x1<<1) // 0x0 - data on ln1_rxdata_o is invalid. 0x1 - d…
66336 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66338 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. …
66340 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. …
66375 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66377 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66379 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after reset seq…
66381 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after reset seq…
66383 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66386 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66388 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66390 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66392 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66394 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66396 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66398 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66400 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66402 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66406 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66412 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66414 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66419 …Reset. Asynchronous reset input signal. This signal must be asserted for a minimum of 170 ns (see …
66421 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66423 … (0x1<<2) // Power-On-Reset Power Enable. Wh…
66429 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66432 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66434 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66436 … LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instea…
66440 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66443 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66450 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66452 … (0x1<<1) // 0x0 - data on ln2_rxdata_o is invalid. 0x1 - d…
66454 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66456 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. …
66458 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. …
66493 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66500 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66502 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66504 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66506 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66508 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66510 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66512 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66514 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66516 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66520 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66526 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66528 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66546 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66548 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66550 … LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instea…
66554 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66557 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66559 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66561 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after reset seq…
66563 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after reset seq…
66565 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66568 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66570 … (0x1<<1) // 0x0 - data on ln3_rxdata_o is invalid. 0x1 - d…
66572 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66574 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. …
66576 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. …
66579 …Reset. Asynchronous reset input signal. This signal must be asserted for a minimum of 170 ns (see …
66581 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66583 … (0x1<<2) // Power-On-Reset Power Enable. Wh…
66589 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66611 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66618 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66620 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66622 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66624 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66626 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66628 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66630 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66632 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66634 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66638 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66644 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66646 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66664 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66684 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66686 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66688 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after reset seq…
66690 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after reset seq…
66692 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66697 …-bit alignment adjustment. This signal must maintain a level for a minimum of one C16 cycle to be …
66712 …-bit alignment adjustment. This signal must maintain a level for a minimum of one C16 cycle to be …
66727 …-bit alignment adjustment. This signal must maintain a level for a minimum of one C16 cycle to be …
66742 …-bit alignment adjustment. This signal must maintain a level for a minimum of one C16 cycle to be …
66757 …. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient up…
66771 …the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 N…
66777 … follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Re…
66781 …. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient up…
66795 …the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 N…
66801 … follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Re…
66805 …. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient up…
66819 …the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 N…
66825 … follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Re…
66829 …. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient up…
66843 …the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 N…
66849 … follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Re…
67211 …10 // PHY instance0 = 0x000-0x1fff. PHY instance1 = 0x2000-0x3fff. PHY instance2 = 0x4000-0x5fff…
67213 …-0x7ff. CMU0 registers = 0x0800-0x0bff. CMU1 registers = 0x0c00-0x0fff. Reserved = …
67359 …-called Peer Delay value that can be added to the correction field for all 1-step updates Refer to…
67360 …-called Peer Delay value that can be added to the correction field for all 1-step updates Refer to…
67361 …-called Peer Delay value that can be added to the correction field for all 1-step updates Refer to…
67362 …-called Peer Delay value that can be added to the correction field for all 1-step updates Refer to…
67364 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67380 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67396 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67412 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67440 … (0x1<<1) // Auto-Negotiation status. Set to '1' when the Auto…
67444 … (0x1<<3) // Auto-Negotiation status. Set to '1' when the Auto…
67448 … (0x1<<5) // Auto-Negotiation status. Set to '1' when the Auto…
67452 … (0x1<<7) // Auto-Negotiation status. Set to '1' when the Auto…
67470 … 0x800058UL //Access:RW DataWidth:0x1 // Controls the fast-wake mode for the LPI…
67522 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67531 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67540 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67549 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67554 …(1) the block synchronization state machines could successfully lock onto 66-bit block boundaries …
67558 …-lock or align-done status, depending on current mode, and a cleared hi-ber status. The signal sta…
67568 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67570 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67572 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67574 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67576 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67578 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67580 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67582 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67584 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67586 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67588 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67590 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67592 …ets). The time for idle counter is defined as "REGISTER VAL"x100nsec. The reset value for this cou…
67593 …ets). The time for idle counter is defined as "REGISTER VAL"x100nsec. The reset value for this cou…
67594 …ets). The time for idle counter is defined as "REGISTER VAL"x100nsec. The reset value for this cou…
67595 …ets). The time for idle counter is defined as "REGISTER VAL"x100nsec. The reset value for this cou…
67806 …to the credit registers (except the port credits). Should be set and then reset after the configur…
68448 …0400UL //Access:RW DataWidth:0x3 // PXP read request interface initial credit - transoriented.
68449 … 0xd80404UL //Access:RW DataWidth:0x6 // TDIF pass-through command inter…
68450 … 0xd80408UL //Access:RW DataWidth:0x6 // TDIF non_pass-through command inter…
68452 …10UL //Access:RW DataWidth:0x2 // PXP internal write interface initial credit - transoriented.
68453 … 0xd80414UL //Access:RW DataWidth:0x3 // TM interface initial credit - transoriented.
68482 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
68483 …-port: Bit-map indicating which L2 hdrs may appear after the LLC header on this port. This applie…
68484 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
68485 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
68486 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
68487 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
68488 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
68489 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
68490 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
68491 … 0xd804d4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68492 … 0xd804d8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68493 … 0xd804dcUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68494 … 0xd804e0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68495 … 0xd804e4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68496 … 0xd804e8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68497 … 0xd804ecUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68498 … 0xd804f0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68499 … 0xd804f4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68511 … 0xd80524UL //Access:RW DataWidth:0x1 // Per-port: Flag to compar…
68544 …used only if sal_flex_upper_bytes is not 0, and number of bytes selected = 8 - sal_flex_upper_bytes
68550 …/Access:RW DataWidth:0x20 // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in …
68551 …/Access:RW DataWidth:0x20 // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in …
68641 …/ The regular inband TAG order. Reset value is in the order from left to right: tag0; tag1; tag2; …
68642 …//Access:RW DataWidth:0x4 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. T…
68663 …DataWidth:0xb // Number of shared BTB 256 byte blocks which can be used by all TC-s in the port.
68667 …-priority w/ anti-starvation arbiter is a RR arbiter. A value of all ones means no RR slots; i.e. …
68668 …W DataWidth:0x8 // L2 EDPM threshold in 256 byte blocks. Only if all TC-s have allocated bloc…
68669 …s:RW DataWidth:0xb // CPMU threshold in 256 byte blocks. Only if all TC-s in port N have allo…
68670 … DataWidth:0xb // RDMA EDPM threshold in 256 byte blocks. Only if all TC-s have allocated bloc…
68681 … 0xd80628UL //Access:RW DataWidth:0x2 // Update mode for the RESET flag
68710 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 0. Reset upon init.
68721 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 0. Reset upon init.
68722 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 0. Reset upon init.
68728 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 1. Reset upon init.
68739 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 1. Reset upon init.
68740 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 1. Reset upon init.
68746 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 2. Reset upon init.
68757 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 2. Reset upon init.
68758 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 2. Reset upon init.
68764 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 3. Reset upon init.
68775 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 3. Reset upon init.
68776 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 3. Reset upon init.
68782 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 4. Reset upon init.
68793 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 4. Reset upon init.
68794 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 4. Reset upon init.
68800 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 5. Reset upon init.
68811 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 5. Reset upon init.
68812 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 5. Reset upon init.
68818 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 6. Reset upon init.
68829 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 6. Reset upon init.
68830 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 6. Reset upon init.
68836 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 7. Reset upon init.
68847 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 7. Reset upon init.
68848 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 7. Reset upon init.
68854 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 8. Reset upon init.
68865 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 8. Reset upon init.
68866 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 8. Reset upon init.
68872 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 9. Reset upon init.
68883 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 9. Reset upon init.
68884 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 9. Reset upon init.
68890 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 10. Reset upon init.
68901 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 10. Reset upon init.
68902 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 10. Reset upon init.
68908 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 11. Reset upon init.
68919 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 11. Reset upon init.
68920 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 11. Reset upon init.
68926 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 12. Reset upon init.
68937 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 12. Reset upon init.
68938 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 12. Reset upon init.
68944 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 13. Reset upon init.
68955 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 13. Reset upon init.
68956 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 13. Reset upon init.
68962 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 14. Reset upon init.
68973 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 14. Reset upon init.
68974 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 14. Reset upon init.
68980 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 15. Reset upon init.
68991 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 15. Reset upon init.
68992 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 15. Reset upon init.
68998 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 16. Reset upon init.
69009 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 16. Reset upon init.
69010 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 16. Reset upon init.
69016 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 17. Reset upon init.
69027 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 17. Reset upon init.
69028 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 17. Reset upon init.
69034 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 18. Reset upon init.
69045 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 18. Reset upon init.
69046 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 18. Reset upon init.
69052 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 19. Reset upon init.
69063 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 19. Reset upon init.
69064 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 19. Reset upon init.
69070 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 20. Reset upon init.
69081 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 20. Reset upon init.
69082 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 20. Reset upon init.
69088 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 21. Reset upon init.
69099 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 21. Reset upon init.
69100 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 21. Reset upon init.
69106 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 22. Reset upon init.
69117 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 22. Reset upon init.
69118 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 22. Reset upon init.
69124 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 23. Reset upon init.
69135 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 23. Reset upon init.
69136 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 23. Reset upon init.
69142 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 24. Reset upon init.
69153 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 24. Reset upon init.
69154 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 24. Reset upon init.
69160 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 25. Reset upon init.
69171 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 25. Reset upon init.
69172 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 25. Reset upon init.
69178 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 26. Reset upon init.
69189 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 26. Reset upon init.
69190 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 26. Reset upon init.
69196 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 27. Reset upon init.
69207 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 27. Reset upon init.
69208 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 27. Reset upon init.
69214 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 28. Reset upon init.
69225 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 28. Reset upon init.
69226 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 28. Reset upon init.
69232 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 29. Reset upon init.
69243 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 29. Reset upon init.
69244 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 29. Reset upon init.
69250 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 30. Reset upon init.
69261 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 30. Reset upon init.
69262 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 30. Reset upon init.
69268 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 31. Reset upon init.
69279 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 31. Reset upon init.
69280 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 31. Reset upon init.
69286 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 32. Reset upon init.
69297 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 32. Reset upon init.
69298 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 32. Reset upon init.
69304 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 33. Reset upon init.
69315 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 33. Reset upon init.
69316 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 33. Reset upon init.
69322 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 34. Reset upon init.
69333 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 34. Reset upon init.
69334 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 34. Reset upon init.
69340 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 35. Reset upon init.
69351 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 35. Reset upon init.
69352 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 35. Reset upon init.
69491 … 0xda2000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
69631 … 0xda6000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
69635 …- if this bit is set then initialization of link list; all head; tail and start_en registers will …
69636 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
69637 … BRTB will not be able to get packets from write clients when this bit is reset. If link list was …
71021 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
71022 …-bytes resolution. After this number of bytes will input to BRTB will be sent packet available ind…
71029 …et is released::s/MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_R…
71030 …te more requests till reset in a case of length error other way it will continue to work as usual.…
71031 …a Width::/ALM_FULL_EN/d in Existance. Value for 40G mode (reset value, both BB and K2): 2880 - (34…
71032 …-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 ::s/NO_DEAD_CYCLE_RST/1/g in …
71034 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
71036 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
71038 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
71040 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
71042 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
71044 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
71046 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
71048 …alues are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g …
71050 …ra packet dead cycles .B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 ::s/…
71051 … corresponding client. B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 ::s/…
71052 …client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_SOP_PRI_RST/5/g in…
71053 …t group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7/g in…
71054 …cal priority is supported. Possible values are 1-3. Priority 3 is highest::s/RC_MULT_PRI_RST/6/g i…
71061 …ient upper which full outputs to this write client interface.::s/DSCR_FIFO_RST/12/g in Reset Value.
71062 …ient upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.
71077 …-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropr…
71079 …rface. When bit is set then appropriate interface is enabled. When bit is reset then request from …
71081 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
71084 …-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropr…
71086 …rface. When bit is set then appropriate interface is enabled. When bit is reset then valid to that…
71088 …faces. When bit is set then almost full interface is enabled. When bit is reset then almost full w…
71090 …s. When bit is set then packet avalable interface is enabled. When bit is reset then packet avalab…
71092 …nterfaces. When bit is set then release interface is enabled. When bit is reset then release inter…
71097 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
71101 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71102 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71103 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71104 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71105 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71106 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71107 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71108 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71109 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71110 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71111 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71112 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71113 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71114 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71115 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71116 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71117 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71118 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71119 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71120 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71121 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71122 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71123 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71124 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71125 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71126 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71127 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
71136 …f the packet arrived it can be sent to the read client. This is because (375-425)/425 is less then…
71141 …te client. It contains: b31 - valid; b30:16 - queue size; b15:0 - queue start pointer::s/SOP_STATU…
71144 … erad packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1.…
71148 … read packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1.…
71155 …Access:RW DataWidth:0xc // Link list dual port memory that contains per-block descriptor::s/B…
71156 …Access:RW DataWidth:0xd // Link list dual port memory that contains per-block descriptor::s/B…
71163 …les MCP's GRC Master interface. This bit should cleared by the driver when the MCP reset completes.
71190 … (0x1<<31) // When set this bit validates bits 10-0 of this register.
71199 … 0xe00094UL //Access:RW DataWidth:0x20 // Doorbell to reset the watchog timer.
71213 …ill send it back to the driver using driver status block. Cleared when the watchdog timer is reset.
71215 … (0x1<<30) // When set this bit enables the watchdog timer to reset the MCP instead of…
71219 …provide timeout period scaling in case where core/cpu clocks are slowed down. Reset value is 500ms.
71220 …ide timeout period scaling in case where core/cpu clocks are slowed down. Reset value is 2 seconds.
71229 … odd PCIE functions. Since the value is different for both functions, the reset value is shown as …
71232 …-bit words) of the mailbox within the MCP scratchpad. There are two reset values. Register that co…
71236 … (0xfff<<20) // Mailbox size in 32-bit words. Default ma…
71239 …-bit words) of the mailbox within the MCP scratchpad. There are two reset values. Register that co…
71243 … (0xfff<<20) // Mailbox size in 32-bit words. Default ma…
71248 …river to alert the MCP. Changing this register updates the corresponding per-PF bit in the MCP Doo…
71266 …taWidth:0x20 // Port mode for GRC Master transactions 0: 1-port mode, 1: 2-port mode, 2: 4-port …
71268 …W DataWidth:0x20 // EPIO mask for signal transitioning from high to low. 1 -> MASK the event
71269 …W DataWidth:0x20 // EPIO mask for signal transitioning from low to high. 1 -> MASK the event
71274 …// When this bit is written to a 1, the processor will reset as if from power-up state. All "Reset…
71278 …erences the first 256 bytes of memory space (page 0). This bit is cleared by an interrupt or reset.
71280 …erences the first 256 bytes of memory space (page 0). This bit is cleared by an interrupt or reset.
71290 …reset. If the processor does not have a ROM, then this bit will reset to set so that no code is ex…
71339 …t into the equation for generation the TX Processor Attention output. The reset value of 1 masks a…
71366 …-2 are implemented. '1's written to bits 1-0 are ignored. If the processor has a ROM, then the res…
71373 … (0x1<<0) // Reset: 1 When this bit i…
71377 … (0x3fffffff<<2) // This field sets the 32-bit word on which the…
71380 … (0x7ff<<0) // 11 bit set-1 debug visibility ve…
71384 … (0xf<<12) // 4 bit select for the peek value of the set-1 debug visibility ve…
71386 … (0x7ff<<16) // 11 bit set-2 debug visibility ve…
71390 … (0xf<<28) // 4 bit select for the peek value of the set-2 debug visibility ve…
71399 …/ While the processor is halted, the general purpose processor registers (r0-r31) can be read and …
71402 … (0xffff<<0) // This value is used to specify the bit at the auto-polled address that i…
71404 …xffff<<16) // This value is used to define the register address in MDIO auto-poll transactions. Fo…
71407 …-B0, on the first read of this register when the START_BUSY bit returns to '0', this value, in the…
71417 …ust be read as a '0' before setting to prevent un-predictable results. On chip versions before Tet…
71420 …by the MDIO interface if auto-polling is enabled. The value of this bit is reflected by in the mai…
71427 … (0x1<<1) // If this bit is set, the 32-bit pre-amble will not be generated during au…
71431 … (0x1<<4) // This bit enables auto-polling. When auto-polling is o…
71453 … COMMAND register. This bit must be set to proper value before the link auto-polling function is e…
71476 …arpCore SERDES microcontroller program memory interfaces. This register auto-increments after each…
71521 … 2 PCIE SERDES microcontroller program memory interfaces. This register auto-increments after each…
71542 …address offset for the AVS RBUS program memory interface. This register auto-increments after each…
71547 … (0x1f<<0) // Number of bytes to be transfered in Read or Write operation. Valid lengths are 0-16.
71561 … (0x1<<30) // Setting this bit will synchronously reset the entire IMC Blo…
71570 …ice ID of the Slave Device. This is a 7-bit field as defined by the I2C spec, but can be written h…
71600 … (0x1<<1) // This bit indicates that in In-Use Error has occured…
71620 … (0x7f<<0) // This is the length of the VDM packet, in 32-bit DWords. 0x0 is an…
71698 …/Access:R DataWidth:0x20 // Reading this register will give the next 32-bits of the current H…
71707 … 0xe06240UL //Access:R DataWidth:0x20 // 32-bit Packet Data.
71709 … (0x7f<<0) // 7-bit Length from VDM H…
71712 … (0xffff<<0) // 16-bit PCI Requester ID …
71715 … (0xffff<<0) // 16-bit Vendor ID from VD…
71718 … (0xffff<<0) // 16-bit FID from VDM Head…
71720 … 0xe06254UL //Access:R DataWidth:0x20 // 32-bit Vendor Defined DW…
71730 … (0xff<<16) // This is the 8-bit Tag from VDM Head…
71734 … (0x1<<0) // If this bit is cleared then the look-up is bypassed and th…
71884 …of the Expansion ROM Engine Baddr register used in the cache fetch logic. Reset value points to En…
71889 …of the Expansion ROM Engine Gaddr register used in the cache fetch logic. Reset value points to En…
71894 …of the Expansion ROM Engine Caddr register used in the cache fetch logic. Reset value points to En…
71899 …of the Expansion ROM Engine Cdata register used in the cache fetch logic. Reset value points to En…
71904 …s of the Expansion ROM Engine Cfg register used in the cache fetch logic. Reset value points to En…
71906 …//Access:RW DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction hi…
71907 …//Access:RW DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction mi…
71933 … (0x1<<0) // When set, the entire NVM state machine is reset. This bit is self …
71953 …en_cmd to flash device through SPI interface to set Flash device to be write-enabled. Used for the…
71955 …di_cmd to flash device through SPI interface to set Flash device to be write-disabled. Used for th…
71965 …it is set, the 256B page mode is disabled for the next operation. It is self-clearing when both th…
71972 …/ 24 bit address value used in read, write and erase operations. When in bit-bang mode, the bottom…
71980 … (0x1<<2) // Enable pass-thru mode to the byte…
71982 … (0x1<<3) // Enable bit-bang mode to control …
71984 … This is automatically interpreted by hardware. This value is self-configured on reset based on th…
72011 …lock erase command. "ready" status will be polled for after this command. Reset value is 0x20h if …
72013 …the first clock and from the last clock to the CSB deassertion. commands. Reset value is 0x1e in L…
72015 … to poll the "ready" status of the flash part after many of the commands. Reset value is 0x9Fh if …
72017 …er command. This command is used to read the ID register from ST devices. Reset value depends on s…
72022 … two bits base on the value of A1 and A0 assigned to this SEEPROM device. Reset value is 0x10 if f…
72026 … two bits base on the value of A1 and A0 assigned to this SEEPROM device. Reset value is 0xFF if f…
72069 …rface state machine through SPI interface To flash device, and make the flash device write-enabled.
72071 …face state machine through SPI interface To flash device, and make the flash device write-disabled.
72082 … by FLSH hardware. It is only used by software. This value is self-configured on reset based on th…
72084 … (0x1<<3) // This bit is self-configured on reset based on th…
72086 …it when MODE_256 is not set with Atmel devices. This value is self-configured on reset based on th…
72088 …this defaults to 1. For ST, this defaults to 0. This value is self-configured on reset based on th…
72090 …ld be cleared when using the 0x68 read command. This value is self-configured on reset based on th…
72102 …ng f(SCLK) = f(core_clk)/(2*(SPI_SLOW_CLK_DIV +1)). [Ex: SPI_SLOW_CLK_DIV=0 -> f(SCLK) = f(core…
72104 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72106 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72108 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72110 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72112 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72114 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72116 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72118 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72120 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72122 … 0xe06430UL //Access:RW DataWidth:0x20 // NVM re-configuration registe…
72125 … by software to numerically encode how the FLSH has been reconfigured. On reset, this register is …
72129 … (0x1<<31) // This bit is 0 on reset. After software fi…
72167 …AR area, it will place the offset from the BAR value in this register and re-try the PCI bus to ma…
72310 … bit is '1', the SMBUS block is placed into bit-bang mode. SMBUS interface pins are controlled usi…
72314 … (0x1<<31) // When this bit is set it will reset SMBUS block to its…
72377 … (0x1<<28) // When the SMBUS interface is configured for bit-bang mode, this bit c…
72381 … (0x1<<30) // When the SM Bus interface is configured for bit-bang mode, this bit c…
72402 … number of bytes that SMBUS block should read from the slave in Block Write - Block Read Process C…
72416 … has no effect. This bit must be read as a '0' before setting it to prevent un-predictable results.
72431 …as no effect. This bit must be read as a '0' before setting it to prevent un-predictable results. …
72512 … (0x1<<31) // 0 - Byte other then last in an WMBUS transaction …
72684 … processor. This can be modified at any time and may be used for processor-to-processor communicat…
72700 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
72702 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
72704 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
72706 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
72750 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
72800 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Asy…
72815 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
72865 … (0x1<<29) // Last-cycle indication not …
72941 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
72991 …E5 (0x1<<29) // Last-cycle indication not …
73004 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73054 …_E5 (0x1<<29) // Last-cycle indication not …
73100 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
73101 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
73102 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
73104 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
73107 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
73127 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
73204 … 0xf82000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73206 … 0xf82400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
73208 … 0xf82800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
73210 … 0xf82c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
73212 … 0xf83000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
73214 … 0xf83400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
73216 … 0xf83800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
73218 … 0xf83c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
73220 … 0xf84000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
73241 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
73243 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
73245 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
73247 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73291 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
73341 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Asy…
73356 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73406 … (0x1<<29) // Last-cycle indication not …
73482 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73532 …E5 (0x1<<29) // Last-cycle indication not …
73545 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73595 …_E5 (0x1<<29) // Last-cycle indication not …
73637 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
73638 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
73639 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
73641 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
73644 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
73665 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
73742 … 0xf92000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73744 … 0xf92400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
73746 … 0xf92800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
73748 … 0xf92c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
73750 … 0xf93000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
73752 … 0xf93400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
73754 … 0xf93800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
73756 … 0xf93c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
73758 … 0xf94000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
73779 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
73781 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
73783 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
73785 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73829 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
73879 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Asy…
73894 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73944 … (0x1<<29) // Last-cycle indication not …
74020 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74070 …E5 (0x1<<29) // Last-cycle indication not …
74083 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74133 …_E5 (0x1<<29) // Last-cycle indication not …
74199 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
74200 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
74201 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
74203 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
74206 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
74227 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
74304 … 0xfa2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74306 … 0xfa2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
74308 … 0xfa2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
74310 … 0xfa2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
74312 … 0xfa3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
74314 … 0xfa3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
74316 … 0xfa3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
74318 … 0xfa3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
74320 … 0xfa4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
74341 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
74343 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
74345 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
74347 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74391 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
74441 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Asy…
74456 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74506 … (0x1<<29) // Last-cycle indication not …
74582 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74632 …E5 (0x1<<29) // Last-cycle indication not …
74645 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74695 …_E5 (0x1<<29) // Last-cycle indication not …
74741 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
74742 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
74743 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
74745 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
74748 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
74768 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
74845 … 0xfb2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74847 … 0xfb2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
74849 … 0xfb2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
74851 … 0xfb2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
74853 … 0xfb3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
74855 … 0xfb3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
74857 … 0xfb3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
74859 … 0xfb3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
74861 … 0xfb4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
74882 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
74884 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
74886 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
74888 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74932 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
74982 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Asy…
74997 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75047 … (0x1<<29) // Last-cycle indication not …
75123 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75173 …E5 (0x1<<29) // Last-cycle indication not …
75186 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75236 …_E5 (0x1<<29) // Last-cycle indication not …
75310 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
75311 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
75312 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
75314 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
75317 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
75339 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
75416 … 0xfc2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75418 … 0xfc2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
75420 … 0xfc2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
75422 … 0xfc2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
75424 … 0xfc3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
75426 … 0xfc3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
75428 … 0xfc3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
75430 … 0xfc3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
75432 … 0xfc4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
75453 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
75455 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
75457 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
75459 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
75503 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
75553 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Asy…
75568 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75618 … (0x1<<29) // Last-cycle indication not …
75694 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75744 …E5 (0x1<<29) // Last-cycle indication not …
75757 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75807 …_E5 (0x1<<29) // Last-cycle indication not …
75853 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
75854 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
75855 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
75857 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
75860 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
75881 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
75958 … 0xfd2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75960 … 0xfd2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
75962 … 0xfd2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
75964 … 0xfd2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
75966 … 0xfd3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
75968 … 0xfd3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
75970 … 0xfd3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
75972 … 0xfd3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
75974 … 0xfd4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
75982 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
76026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76027 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76029 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76031 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76033 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76035 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76037 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76039 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76041 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76042 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76043 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76044 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76045 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76046 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76047 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76048 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76049 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76050 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76051 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76052 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76053 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76054 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76055 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76056 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76057 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76058 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76059 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76060 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76061 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76062 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76063 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76064 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76065 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76066 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76067 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76068 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76069 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76070 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76071 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76073 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76074 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76262 … (0x1<<19) // In-process Table overflo…
76364 … (0x1<<19) // In-process Table overflo…
76415 … (0x1<<19) // In-process Table overflo…
76781 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
76783 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76784 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76785 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76786 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76787 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76788 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76789 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76790 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76791 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76792 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76793 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76794 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76795 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76796 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76797 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76798 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76799 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76800 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76801 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76802 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76803 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76804 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76805 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76806 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76807 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76808 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76810 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76812 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76814 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76816 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76817 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76818 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76819 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76820 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76821 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76822 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76823 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76824 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76825 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76826 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76827 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76828 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76829 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76830 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76831 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76832 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76833 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76834 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76835 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76836 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76849 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76850 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76851 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76852 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76853 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76854 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76855 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
76856 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76857 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76858 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76859 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76860 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76861 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76862 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76863 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76864 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76865 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76866 … 0x1000680UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
76868 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
76879 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
76880 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
76881 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
76883 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
76888 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76889 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76890 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76891 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
76895 …00075cUL //Access:RC DataWidth:0x4 // Xx Connection Bypass Table sticky status. Reset on read.
76905 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76906 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76907 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76908 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76909 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76910 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76911 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76912 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76913 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76914 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76915 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76916 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76917 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76918 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76919 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76920 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76921 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76922 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76923 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76924 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76925 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76926 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76927 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76928 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76942 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
76943 … 0x1000904UL //Access:RW DataWidth:0xa // [9]: PQ Type (0-Other PQ; 1-TX PQ); if bit[…
76944 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
76945 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
76946 … 0x1000a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
76947 … 0x1000a10UL //Access:R DataWidth:0x1 // In-process Table almost …
76969 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
76970 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
76971 …th:0x5 // QM output initial credit (XCM TX queues). Max credit available - 16.Write writes the …
76972 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
77008 …tive counter overflow/uder-run. Is reset on read. [0] - If set, there was under-run; [1] - If set,…
77025 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
77028 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
77030 …ess:R DataWidth:0x20 // Debug read from XSEM Input stage buffer with 32-bits granularity. Rea…
77032 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
77034 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
77036 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
77038 …ess:R DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Rea…
77040 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
77042 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
77043 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
77044 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
77050 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
77053 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
77247 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77248 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77249 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77250 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77251 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77252 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77253 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77254 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77255 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77256 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77257 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77258 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77259 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77260 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77261 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77262 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77273 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
77283 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
77284 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
77286 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
77288 …alue. [28:20] PQ number. [29:29] Reserved. [31:30] Command type: 0 - SET; 1 - DEC; 2 - INC; The ad…
77291 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
77333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77334 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77336 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77338 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77492 … (0x1<<14) // In-process Table overflo…
77586 … (0x1<<14) // In-process Table overflo…
77633 … (0x1<<14) // In-process Table overflo…
78022 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
78072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78073 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78074 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78075 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78076 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78077 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78078 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78079 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78080 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78081 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78091 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78092 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78093 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78094 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78095 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78096 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78097 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
78098 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78099 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78100 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78101 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78102 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78103 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78104 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78105 … 0x1080664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
78107 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78108 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78121 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
78122 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
78123 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
78125 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
78130 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78131 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78132 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78133 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
78137 …08075cUL //Access:RC DataWidth:0x4 // Xx Connection Bypass Table sticky status. Reset on read.
78140 … 0x1080768UL //Access:RC DataWidth:0x7 // Xx Task Bypass Table sticky status. Reset on read.
78150 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78151 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78152 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78153 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78154 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78155 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78156 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78157 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78158 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78159 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78160 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78161 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78162 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78163 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78164 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78165 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78166 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78167 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78168 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78169 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78170 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78171 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78172 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78173 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78213 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
78214 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
78219 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78220 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78221 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78222 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78223 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78224 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78225 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78226 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78227 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78228 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78229 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78230 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78231 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78232 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78233 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78242 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
78243 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
78244 … 0x1080a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
78245 … 0x1080a10UL //Access:R DataWidth:0x1 // In-process Table almost …
78269 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
78270 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
78271 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
78272 …1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the i…
78273 …th:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the i…
78312 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
78314 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
78316 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
78318 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
78320 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
78321 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
78322 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
78323 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
78324 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
78333 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
78336 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
78516 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
78517 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
78519 …ess:R DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Rea…
78520 …ess:R DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Rea…
78525 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
78526 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
78529 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78535 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
78536 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
78539 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
78658 …K2 (0x1<<10) // In-process Table overflo…
78660 … (0x1<<8) // In-process Table overflo…
78764 …BB_K2 (0x1<<10) // In-process Table overflo…
78766 …_E5 (0x1<<8) // In-process Table overflo…
78817 …_BB_K2 (0x1<<10) // In-process Table overflo…
78819 …L_E5 (0x1<<8) // In-process Table overflo…
78998 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
79003 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79004 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79005 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79006 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79007 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79008 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79009 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
79010 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79011 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79012 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79013 … 0x110063cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
79015 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
79025 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
79026 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
79027 … DataWidth:0x2 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
79029 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
79034 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79035 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79036 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79037 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
79052 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
79053 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
79054 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
79055 … 0x1100a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
79056 … 0x1100a10UL //Access:R DataWidth:0x1 // In-process Table almost …
79060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
79076 …ess:R DataWidth:0x20 // Debug read from PSEM Input stage buffer with 32-bits granularity. Rea…
79079 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
79081 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
79082 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
79085 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
79087 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
79123 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
79124 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
79131 …ess:R DataWidth:0x20 // Debug read from YPLD Input stage buffer with 32-bits granularity. Rea…
79133 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
79135 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
79177 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79178 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79179 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79180 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79182 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79184 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79186 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79187 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79188 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79189 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79190 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79191 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79192 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79193 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79194 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79195 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79196 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79197 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79198 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79199 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79399 … (0x1<<21) // In-process Table overflo…
79537 … (0x1<<21) // In-process Table overflo…
79606 … (0x1<<21) // In-process Table overflo…
79982 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
80024 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80025 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80027 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80029 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80031 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80033 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80035 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80037 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80039 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80041 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80042 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80043 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80053 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80054 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80055 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80056 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80057 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80058 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80059 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
80060 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80061 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80062 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80063 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80064 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80065 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80066 … 0x1180664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
80068 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80069 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80082 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
80083 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
80084 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
80086 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
80091 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80092 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80093 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80094 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
80098 …18075cUL //Access:RC DataWidth:0x4 // Xx Connection Bypass Table sticky status. Reset on read.
80101 … 0x1180768UL //Access:RC DataWidth:0x7 // Xx Task Bypass Table sticky status. Reset on read.
80111 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80112 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80113 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80114 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80115 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80116 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80117 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80118 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80119 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80120 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80121 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80122 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80123 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80124 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80125 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80126 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80127 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80128 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80129 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80130 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80131 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80132 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80133 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80134 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80174 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
80175 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
80180 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80182 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80184 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80194 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
80195 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
80196 … 0x1180a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
80197 … 0x1180a10UL //Access:R DataWidth:0x1 // In-process Table almost …
80223 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
80224 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
80225 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
80226 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
80264 …ess:R DataWidth:0x20 // Debug read from TSEM Input stage buffer with 32-bits granularity. Rea…
80267 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
80269 …cess:R DataWidth:0x20 // Debug read from PRS Input stage buffer with 32-bits granularity. Rea…
80271 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
80273 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
80275 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
80276 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
80277 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
80278 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
80279 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
80288 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
80291 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
80495 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
80496 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
80503 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
80510 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
80520 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
80521 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
80528 …ess:R DataWidth:0x20 // Debug read from PTLD Input stage buffer with 32-bits granularity. Rea…
80530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80535 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80536 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80537 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80538 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80539 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80540 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80541 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80542 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80543 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80544 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80545 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80546 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
80549 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
80591 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80592 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80593 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80594 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80595 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80596 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80848 … (0x1<<15) // In-process Table overflo…
80954 … (0x1<<15) // In-process Table overflo…
81007 … (0x1<<15) // In-process Table overflo…
81283 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
81333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81334 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81336 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81338 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81339 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81340 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81341 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81342 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81352 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81353 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81354 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81355 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81356 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81357 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81358 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
81359 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81360 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81361 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81362 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81363 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81364 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81365 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81366 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81367 … 0x120066cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
81369 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81370 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81383 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
81384 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
81385 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
81387 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
81392 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81393 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81394 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81395 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
81399 …20075cUL //Access:RC DataWidth:0x4 // Xx Connection Bypass Table sticky status. Reset on read.
81402 … 0x1200768UL //Access:RC DataWidth:0x7 // Xx Task Bypass Table sticky status. Reset on read.
81412 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81413 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81414 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81415 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81416 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81417 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81418 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81419 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81420 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81421 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81422 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81423 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81424 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81425 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81426 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81427 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81428 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81429 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81430 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81431 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81432 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81433 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81434 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81435 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81475 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
81476 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
81481 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81482 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81483 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81484 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81485 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81486 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81487 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81488 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81497 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
81498 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
81499 … 0x1200a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
81500 … 0x1200a10UL //Access:R DataWidth:0x1 // In-process Table almost …
81524 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
81525 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
81526 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
81527 …1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the i…
81528 …th:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the i…
81568 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
81571 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
81573 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
81575 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
81577 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
81579 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
81580 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
81581 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
81582 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
81583 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
81592 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
81595 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
81765 …ess:R DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Rea…
81766 …ess:R DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Rea…
81774 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
81781 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
81793 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
81794 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
81804 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
81805 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
81808 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81810 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81812 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81814 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81816 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
81817 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
81820 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
81866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81867 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81868 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81869 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81870 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81871 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81872 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81873 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81874 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81875 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81876 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81877 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81878 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81879 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81880 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81881 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82121 …K2 (0x1<<18) // In-process Table overflo…
82123 … (0x1<<19) // In-process Table overflo…
82359 …BB_K2 (0x1<<18) // In-process Table overflo…
82361 …E5 (0x1<<19) // In-process Table overflo…
82478 …_BB_K2 (0x1<<18) // In-process Table overflo…
82480 …_E5 (0x1<<19) // In-process Table overflo…
82808 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
82850 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82851 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82852 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82853 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82854 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82855 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82856 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82857 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82858 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82859 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82860 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82861 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82862 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82863 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82864 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82865 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82867 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82882 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82883 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82884 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82885 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82886 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82887 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82888 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
82889 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82890 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82891 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82892 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82893 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82894 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82895 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82896 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82897 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82898 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82899 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82900 … 0x1280684UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
82902 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82903 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82916 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
82917 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
82918 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
82920 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
82925 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82926 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82927 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82928 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
82932 …28075cUL //Access:RC DataWidth:0x4 // Xx Connection Bypass Table sticky status. Reset on read.
82935 … 0x1280768UL //Access:RC DataWidth:0x7 // Xx Task Bypass Table sticky status. Reset on read.
82945 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82946 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82947 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82948 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82949 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82950 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82951 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82952 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82953 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82954 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82955 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82956 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82957 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82958 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82959 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82960 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82961 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82962 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82963 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82964 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82965 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82966 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82967 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82968 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
83008 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
83009 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
83014 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83015 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83016 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83017 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83018 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83019 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83020 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83021 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83022 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83031 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
83032 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
83033 … 0x1280a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
83034 … 0x1280a10UL //Access:R DataWidth:0x1 // In-process Table almost …
83060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
83061 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
83062 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
83063 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
83124 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
83127 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
83129 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
83131 …ess:R DataWidth:0x20 // Debug read from RDIF Input stage buffer with 32-bits granularity. Rea…
83133 …ess:R DataWidth:0x20 // Debug read from TDIF Input stage buffer with 32-bits granularity. Rea…
83135 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
83137 …ess:R DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Rea…
83139 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
83141 …ess:R DataWidth:0x20 // Debug read from YULD Input stage buffer with 32-bits granularity. Rea…
83143 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
83144 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
83145 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
83146 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
83147 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
83156 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
83159 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
83353 …ess:R DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Rea…
83354 …ess:R DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Rea…
83363 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
83365 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83366 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83367 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83368 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83369 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83370 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83371 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83372 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83373 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83374 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83375 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83376 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
83424 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
83435 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
83438 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
83440 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
83442 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
83444 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
83446 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
83449 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
83451 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
83453 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
83455 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83458 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
83460 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
83462 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
83464 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83494 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83522 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83570 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83732 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83760 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83808 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83851 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83879 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83927 … (0x1<<11) // Signals an unknown address in the fast-memory window.
84038 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84040 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84044 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84054 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84220 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84222 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84226 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84236 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84311 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84313 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84317 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84327 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84356 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84358 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84482 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84484 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84545 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84547 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84628 … 0x1400408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
84629 … 0x140040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
84630 … 0x1400420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
84633 … 0x1400440UL //Access:R DataWidth:0x10 // This read-only register provide…
84640 …UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be acti…
84641 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
84642 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
84643 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
84647 … 0x1400600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
84649 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
84650 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
84656 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
84659 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84660 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84662 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
84664 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
84667 …0x1400b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
84674 …1400b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
84675 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
84677 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
84681 … 0x1400d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
84683 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
84685 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
84686 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
84696 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
84701 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
84714 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
84717 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
84720 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
84721 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
84733 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
84738 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
84749 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
84751 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
84756 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
84772 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
84782 … 0x1408000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
84788 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
84793 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84794 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84847 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
84858 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
84861 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
84863 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
84865 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
84867 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
84869 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
84872 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
84874 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
84876 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
84878 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84881 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
84883 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
84885 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
84887 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84917 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
84945 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84993 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85155 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85183 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85231 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85274 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85302 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85350 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85461 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85463 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85467 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85477 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85643 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85645 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85649 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85659 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85734 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85736 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85740 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85750 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85779 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85781 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85905 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85907 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85968 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85970 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
86051 … 0x1500408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
86052 … 0x150040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
86053 … 0x1500420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
86056 … 0x1500440UL //Access:R DataWidth:0x10 // This read-only register provide…
86063 …UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be acti…
86064 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
86065 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
86066 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
86070 … 0x1500600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
86072 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
86073 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
86079 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
86082 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86083 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86085 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
86087 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
86090 …0x1500b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
86097 …1500b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
86098 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
86100 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
86104 … 0x1500d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
86106 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
86108 …L //Access:RW DataWidth:0xe // Provides access to the thread ordering queue pop-enable vector.
86109 … //Access:RW DataWidth:0xe // Provides access to the thread ordering queue wake-enable vector.
86119 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
86124 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
86137 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
86140 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
86143 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
86144 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
86156 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
86161 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
86172 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
86174 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
86179 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
86195 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
86205 … 0x1508000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the ex…
86211 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
86216 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86217 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86271 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
86282 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
86285 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
86287 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
86289 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
86291 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
86293 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
86296 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
86298 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
86300 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
86302 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86305 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
86307 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
86309 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
86311 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86341 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86369 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86417 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86579 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86607 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86655 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86698 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86726 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86774 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86885 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
86887 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
86891 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86901 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87067 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
87069 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
87073 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87083 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87158 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
87160 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
87164 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87174 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87203 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87205 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87329 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87331 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87392 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87394 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87473 … 0x1600408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
87474 … 0x160040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
87475 … 0x1600420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
87478 … 0x1600440UL //Access:R DataWidth:0x10 // This read-only register provide…
87485 …UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be acti…
87486 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
87487 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
87488 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
87492 … 0x1600600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
87493 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
87494 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
87500 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
87503 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87504 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87506 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
87508 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
87511 …0x1600b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
87518 …1600b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
87519 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
87521 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
87525 … 0x1600d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
87527 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
87529 …L //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue pop-enable vector.
87530 … //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue wake-enable vector.
87540 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
87545 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
87557 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
87560 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
87563 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
87564 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
87575 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
87580 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
87591 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
87593 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
87598 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
87614 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
87624 … 0x1608000UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the ex…
87630 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
87635 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87636 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87690 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
87701 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
87704 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
87706 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
87708 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
87710 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
87712 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
87715 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
87717 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
87719 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
87721 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87724 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
87726 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
87728 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
87730 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87760 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
87788 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87836 … (0x1<<11) // Signals an unknown address in the fast-memory window.
87998 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88026 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88074 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88117 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88145 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88193 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88304 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88306 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88310 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88320 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88486 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88488 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88492 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88502 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88577 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88579 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88583 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88593 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88622 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88624 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88748 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88750 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88811 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88813 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88892 … 0x1700408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
88893 … 0x170040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
88894 … 0x1700420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
88897 … 0x1700440UL //Access:R DataWidth:0x10 // This read-only register provide…
88904 …UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be acti…
88905 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
88906 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
88907 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
88911 … 0x1700600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
88912 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
88913 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
88919 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
88922 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88923 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88925 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
88927 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
88930 …0x1700b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
88937 …1700b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
88938 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
88940 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
88944 … 0x1700d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
88946 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
88948 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
88949 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
88959 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
88964 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
88976 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
88979 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
88982 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
88983 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
88994 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
88999 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
89010 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
89012 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
89017 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
89033 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
89043 … 0x1708000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
89049 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
89054 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89055 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89108 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
89119 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
89122 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
89124 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
89126 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
89128 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
89130 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
89133 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
89135 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
89137 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
89139 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89142 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
89144 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
89146 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
89148 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89178 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89206 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89254 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89416 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89444 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89492 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89535 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89563 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89611 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89722 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89724 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89728 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89738 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
89904 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89906 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89910 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89920 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
89995 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89997 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
90001 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90011 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
90040 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90042 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90166 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90168 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90229 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90231 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90374 … 0x1800408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
90375 … 0x180040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
90376 … 0x1800420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
90379 … 0x1800440UL //Access:R DataWidth:0x10 // This read-only register provide…
90386 …UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be acti…
90387 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
90388 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
90389 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
90393 … 0x1800600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
90394 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
90395 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
90401 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
90404 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90405 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90407 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
90409 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
90412 …0x1800b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
90419 …1800b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
90420 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
90422 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
90426 … 0x1800d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
90428 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
90430 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
90431 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
90441 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
90446 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
90458 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
90461 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
90464 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
90465 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
90476 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
90481 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
90492 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
90494 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
90499 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
90515 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
90525 … 0x1808000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
90531 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
90536 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90537 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90591 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
90602 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
90605 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
90607 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
90609 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
90611 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
90613 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
90616 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
90618 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
90620 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
90622 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90625 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
90627 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
90629 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
90631 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90661 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90689 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90737 … (0x1<<11) // Signals an unknown address in the fast-memory window.
90899 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90927 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90975 … (0x1<<11) // Signals an unknown address in the fast-memory window.
91018 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
91046 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91094 … (0x1<<11) // Signals an unknown address in the fast-memory window.
91205 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91207 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91211 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91221 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91387 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91389 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91393 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91403 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91478 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91480 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91484 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91494 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91523 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91525 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91649 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91651 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91712 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91714 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91793 … 0x1900408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
91794 … 0x190040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
91795 … 0x1900420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
91798 … 0x1900440UL //Access:R DataWidth:0x10 // This read-only register provide…
91805 …UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be acti…
91806 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
91807 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
91808 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
91812 … 0x1900600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
91813 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
91814 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
91820 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
91823 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91824 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91826 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
91828 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
91831 …0x1900b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
91838 …1900b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
91839 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
91841 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
91845 … 0x1900d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
91847 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
91849 …L //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue pop-enable vector.
91850 … //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue wake-enable vector.
91860 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
91865 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
91877 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
91880 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
91883 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
91884 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
91895 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
91900 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
91911 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
91913 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
91918 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
91934 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
91944 … 0x1908000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the ex…
91950 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
91955 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
91956 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…