Lines Matching +full:set +full:- +full:io +full:- +full:isolation
2 * Copyright (c) 2017-2018 Cavium, Inc.
38 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
40 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
83 …l not be loaded, EEPROM load will stop, and the FastLinkEnable bit will be set in the PCIEEP_PORT_…
85 …ly set to the appropriate chip number, from the FUS_FUSE_NUM_E::CHIP_TYPE() fuses, and as enumerat…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
102 …e. If the PF or any of its VFs try to master the bus when this bit is not set, the request is dis…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …IO Access Response. You cannot write to this register if your configuration has no IO bars; that…
147 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
185 …2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
189 …20 // This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)
190 …s not support I/O space access because it is zero and can not be modified. IO transactions targeti…
194 … device. When low, it disables an Endpoint function from issuing memory or IO requests. Also disab…
202 …his bit is cleared , the master data parity error status bit will never be set. Path = i_cfg_func.…
206 … (0x1<<8) // When set, this bit enables t…
210 …set, function is not permitted to generate IntX interrupt messages (de-asserted) regardless of any…
226 …set by a requester if the parity error enable bit is set in its command register and either of the…
230 … (0x1<<27) // This bit is set when a function act…
232 … (0x1<<28) // This bit is set when a requester re…
234 … (0x1<<29) // This bit is set when a requester re…
236 …0) // This bit is set when a function sends an ERR_FATAL or ERR_NONFATAL message and the SERR enab…
238 … (0x1<<31) // When this bit is set, it indicates that …
250 …n Revision ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
252 …ing Interface. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
254 …t Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
256 …t Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
261 … (0xffffff<<8) // The 24-bit Class Code regist…
281 …multifunction. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
290 …ADER_TYPE_BB (0xff<<16) // The 8-bit Header Type regis…
292 … (0xff<<24) // The 8-bit BIST register is used to initiate and report the results o…
297 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
304 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
306 … (0x3<<1) // BAR0 32-bit or 64-bit. Note: The access attributes of this field a…
308 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
310 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
312 …-bit BAR_1 register programs the base address for the memory space mapped by the card onto the PCI…
315 …icate that BAR_1 may be programmed to map this adapter to anywhere in the 64-bit address space. Pa…
317 … (0x1<<3) // This bit indicates that the area mapped by BAR_1 may be pre-fetched or cached by …
319 … (0xfffffff<<4) // These bits set the address within a 32-bit addr…
323 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
325 … (0x3<<1) // BAR1 32-bit or 64-bit. Note: The access attributes of this field a…
327 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
329 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
331 … 0x000014UL //Access:RW DataWidth:0x20 // The 32-bit BAR_2 register pr…
335 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
342 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
344 … (0x3<<1) // BAR2 32-bit or 64-bit. Note: The access attributes of this field a…
346 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
348 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
350 …-bit BAR_3 register programs the 2nd base address for the memory space mapped by the card onto the…
353 …icate that BAR_2 may be programmed to map this adapter to anywhere in the 64-bit address space. Pa…
355 … (0x1<<3) // This bit indicates that the area mapped by BAR_2 may be pre-fetched or cached by …
357 … (0xfffffff<<4) // These bits set the address within a 32-bit addr…
361 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
363 … (0x3<<1) // BAR3 32-bit or 64-bit. Note: The access attributes of this field a…
365 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
367 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
369 … 0x00001cUL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register pr…
373 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
380 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
382 … (0x3<<1) // BAR4 32-bit or 64-bit. Note: The access attributes of this field a…
384 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
386 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
388 …-bit BAR_5 register programs the 3rd base address for the memory space mapped by the card onto the…
391 …icate that BAR_3 may be programmed to map this adapter to anywhere in the 64-bit address space. Pa…
393 … (0x1<<3) // This bit indicates that the area mapped by BAR_3 may be pre-fetched or cached by …
395 … (0xfffffff<<4) // These bits set the address within a 32-bit addr…
399 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
401 … (0x3<<1) // BAR5 32-bit or 64-bit. Note: The access attributes of this field a…
403 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
405 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
407 … 0x000024UL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register pr…
412 … (0xffff<<0) // Subsystem vendor ID. Assigned by PCI-SIG, writable through…
414 … (0xffff<<16) // Subsystem ID. Assigned by PCI-SIG, writable through…
417 …tem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
419 …tem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
422 …VENDOR_ID_BB (0xffff<<0) // The 16-bit Subsystem Vendor …
424 …D_BB (0xffff<<16) // The 16-bit Subsystem ID regi…
432 …<<0) // Expansion ROM Enable. Note: The access attributes of this field are as follows: - Dbi: R
434 …Expansion ROM Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W
436 … 0x000030UL //Access:RW DataWidth:0x20 // The 32-bit Expansion ROM BAR…
437 … (0x1<<0) // This bit indicates that the Expansion ROM BAR is valid when set to one. If it is ze…
449 …ity Structure. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
452 …-bit Capabilities Pointer register specifies an offset in the PCI address space of a linked list o…
466 …egister Field. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
469 … (0xff<<0) // The 8-bit Interrupt Line register is used to communicate interrupt line routing…
471 …_INT_PIN_BB (0xff<<8) // The 8-bit Interrupt Pin reg…
494 …set, PME Messages can be generated from D0. _ Bit 12: If set, PME Messages can be generated from…
499 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
501 … Spec Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
505 … Return to D0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
507 …alization Bit. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
509 … Requirements. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
511 …State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
513 …State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
515 …tion parameter. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
537 …owever, the read-back value is the actual power state, not the write value. Note: The access attr…
539 …No soft Reset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
556 … (0xff<<0) // The 8-bit Power Management Capability ID is set …
558 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
568 …a specific initialization (DSI) sequence following a transition to the D0 un-initialized state. Th…
587 … (0x3<<0) // These bits may be used by the system to set the power state. Th…
601 …set when a PME is asserted from the MAC or RX Parser blocks, regardless of the state of the PME_EN…
610 … Next Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
614 …ssage Capable. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
618 … (0x1<<23) // MSI 64-bit Address Capable. Note: The access attributes of this fiel…
623 … (0xff<<0) // The 8-bit VPD Capability ID is set to 3 t…
625 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
629 …// This value is the 32-bit word address of the VPD value being accessed in the vpd_data register.…
631 …bit is used to control passing of data between the vpd_data register and Non-Volatile memory. To r…
634 …essage Lower Address Field. Note: The access attributes of this field are as follows: - Dbi: R/W
638 …-bit MSI Message, this field contains Data. For 64-bit it contains lower 16 bits of the Upper Addr…
640 …is reserved. For 64-bit it contains upper 16 bits of the Upper Address. Note: The access attribut…
643 … (0xff<<0) // The 8-bit MSI Capability ID is set to 5 t…
645 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
647 … (0x1<<16) // When this bit is set, the chip will gene…
658 …-bit MSI Message, this field contains Data. For 32-bit, it contains the lower Mask Bits if PVM is …
660 …-bit MSI Message, this field contains Data. For 32-bit, it contains the upper Mask Bits if PVM is …
676 … (0xff<<8) // Next capability pointer. Points to the MSI-X Capabilities by def…
689 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
695 …emented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
697 …essage Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
712 … (0x1<<15) // Role-based error reporting…
718 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core.
721 …ize Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
723 …ons Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
725 …eld Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
727 …table latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
729 …table latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
731 … (0x1<<15) // Role-based Error Reporting Implemented. Note: The access attributes of th…
737 …dpoints only). Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
750 …Larger sizes are not supported by CNXXXX. DPI_SLI_PRT()_CFG[MPS] must be set to the same value a…
752 … (0x1<<8) // Extended tag field enable. Set this bit to enable …
754 … (0x1<<9) // Phantom function enable. This bit should never be set; CNXXXX requests ne…
760 …s. 0x4 = 2048 bytes. 0x5 = 4096 bytes. DPI_SLI_PRT()_CFG[MRRS] must be set and properly must n…
764 …set if we receive any of the errors in PCIEEP_COR_ERR_STAT, for example a replay-timer timeout. A…
766 …ce control register. This field is set if we receive any of the errors in PCIEEP_UCOR_ERR_MSK that…
768 …ce control register. This field is set if we receive any of the errors in PCIEEP_UCOR_ERR_MSK that…
770 …ests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message shoul…
772 … (0x1<<20) // AUX power detected. Set to one if AUX power…
774 … (0x1<<21) // Transaction pending. Set to 1 when nonposted requests are not yet complete…
779 …S_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting…
789 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
791 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
795 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
803 …_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
826 … (0x1<<19) // Surprise down error reporting capable. Set to 0 for endpoint d…
830 … (0x1<<21) // Link bandwidth notification capability. Set to 0 for endpoint d…
837 …In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The …
839 …In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The …
841 …ment) Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
843 …- CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1…
845 …- CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1…
847 …er Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
855 …ty Compliance. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
857 …/ Port Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
884 … (0x3f<<20) // Negotiated link width. Set automatically by ha…
899 …d Completion Boundary (RCB). Note: The access attributes of this field are as follows: - Dbi: R/W
901 …_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_EN…
903 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
909 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
911 …e Autonomous Width Disable. Note: The access attributes of this field are as follows: - Dbi: R/W
913 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
915 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
923 …figuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
925 …Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
929 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
931 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
942 … (0x1<<7) // 32-bit AtomicOp supporte…
944 … (0x1<<8) // 64-bit AtomicOp supporte…
946 … (0x1<<9) // 128-bit AtomicOp supporte…
948 … (0x1<<10) // No RO-enabled PR-PR passing. (Thi…
956 …SUPP_E5 (0x1<<16) // 10-bit tag completer sup…
958 …SUPP_E5 (0x1<<17) // 10-bit tag requestor sup…
964 … (0x1<<21) // End-end TLP prefix suppor…
966 … (0x3<<22) // Max end-end TLP prefixes. 0x…
983 …R2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
1010 …EN_E5 (0x1<<12) // 10-bit tag requester ena…
1014 … (0x1<<15) // End-end TLP prefix blocki…
1017 …/ Completion Timeout Value. Note: The access attributes of this field are as follows: - Dbi: R/W
1049 …DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1052 …s undefined. For both upstream and downstream ports, this field is used to set the target complian…
1056 …he application must disable hardware from changing the link speed for device-specific reasons othe…
1060 …-deemphasized voltage level at the transmitter pins: 0x0 = 800-1200 mV for full swing 400-600 mV …
1062 … (0x1<<10) // Enter modified compliance. When this bit is set to one, the device …
1064 … (0x1<<11) // Compliance SOS. When set to one, the LTSSM i…
1066 …ntry occurred due to the TX compliance receive bit being one. 0x0 = -6 dB. 0x1 = -3.5 dB. When…
1068 …ting at 5 GT/s speed, this bit reflects the level of deemphasis. 0 = -6 dB. 1 = -3.5 dB. The v…
1091 …K_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the conten…
1095 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1097 …EMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
1101 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1103 … transmission. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1105 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
1107 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
1126 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
1128 …f<<16) // System sw reads this field to determine the MSI-X table size N, which is encoded as N-1 …
1137 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X table into memory s…
1142 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X PBA into memory spa…
1157 …-X vector is used for the interrupt message generated in association with any of the status bits o…
1160 …MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
1164 …-X table size encoded as (table size - 1). Writable through PEM()_CFG_WR. This field is writable…
1166 …ctors associated with the function are masked, regardless of their respective per-vector mask bits.
1168 … (0x1<<31) // MSI-X enable. If MSI-X is enabled,…
1170 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
1171 …TRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
1173 … (0xff<<8) // MSI-X Next Capability Pointer. Note: The access attributes of this f…
1175 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
1177 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
1179 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
1198 …upper limit on power supplied by slot. It is set by the Set_Slot_Power_Limit Message. This field i…
1200 …e used for the Slot Power Limit Value. It is set by the Set_Slot_Power_Limit Message. This field i…
1202 …capability is advertized when flr_supported bit in private device_capability register space is set.
1205 … (0x7<<0) // MSI-X table BAR indicator register (BIR). Indicates which BAR is u…
1207 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
1209 … 0x0000b4UL //Access:RW DataWidth:0x20 // MSI-X Table Offset and BI…
1210 … (0x7<<0) // MSI-X Table Bar Indicator Register Field. Note: The access attributes of …
1212 … (0x1fffffff<<3) // MSI-X Table Offset. Note: The access attributes of this field …
1217 …L_ERR_REPORT_EN_BB (0x1<<1) // Non-Fatal Error Reporting…
1227 … (0x1<<8) // Extended Tag Field Enable. This capability when set allows DUT to gener…
1231 … (0x1<<10) // This bit when set enables device to d…
1233 …able No Snoop. When this bit is set to 1, PCIE initiates a read request with the No Snoop bit in t…
1237 …iteable only if flr_supported bit in private device_capability register is set. A write of 1 to th…
1241 …TAL_ERR_DET_BB (0x1<<17) // Non-Fatal Error Detected.…
1249 … (0x1<<21) // This is bit is read back a 1, whenever a non-posted request initia…
1252 … (0x7<<0) // MSI-X PBA BAR indicator register (BIR). Indicates which BAR is us…
1254 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
1256 … 0x0000b8UL //Access:RW DataWidth:0x20 // MSI-X PBA Offset and BIR …
1257 … (0x7<<0) // MSI-X PBA BIR. Note: The access attributes of this field are…
1259 … (0x1fffffff<<3) // MSI-X PBA Offset. Note: The access attributes of this field a…
1274 … (0x1<<19) // Surprise Down Error Reporting Capable: RC: this bit must be set if the component su…
1295 … logic is resolved to 1 only if all functions (when enabled) have this bit set. For ARI devices, o…
1297 …set forces the transmission of 4096 FTS ordered sets in the L0s state followed by a single SKP ord…
1299 …e Clock Power Management: RC: N/A and hardwired to 0. EP: When this bit is set, the device is perm…
1301 … (0x1<<9) // Hardware Autonomous Width Disable: When Set, this bit disables …
1303 …t Enable: when Set, this bit enables the generation of an interrupt to indicate that the Link Band…
1305 …t Enable: When Set, this bit enables the generation of an interrupt to indicate that the Link Auto…
1317 … (0x1<<28) // Slot Clock configuration. This bit is read-only by host, but rea…
1355 …xt Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1357 …0x7fff<<16) // VPD Address. Note: The access attributes of this field are as follows: - Dbi: R/W
1359 … (0x1<<31) // VPD Flag. Note: The access attributes of this field are as follows: - Dbi: R/W
1368 …er space. This field will read 1, when bit 5 of ext_cap_ena field in private register space is set.
1385 … (0x1<<6) // Atomic requester Enable. When this bit is set, function and assoc…
1389 …d bit of private device_capability_2 register is set. When this bit is set, function is permitted …
1391 …d bit of private device_capability_2 register is set. When this bit is set, function is permitted …
1393 …is writeable, when bit 5 of ext_cap_ena field in private register space is set. This bit is RW onl…
1397 …is writeable, when bit 5 of ext_cap_ena field in private register space is set. This bit is RW onl…
1411 …e level of de-emphasis. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Value used by logic is resolve…
1425 … (0x1<<17) // Equalization Complete - when set, this indicates …
1427 … (0x1<<18) // Equalization Phase 1 Successful - when set, this indicates …
1429 … (0x1<<19) // Equalization Phase 2 Successful - when set, this indicates …
1431 … (0x1<<20) // Equalization Phase 3 Successful - when set, this indicates …
1433 …EST_BB (0x1<<21) // This bit is set by hardware to requ…
1451 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1453 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1455 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1518 …re sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it de…
1550 … (0x1<<5) // Surprise down error mask. Set to 0 for endpoint d…
1597 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1603 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1605 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1637 … (0x1<<5) // Surprise down error severity. Set to 1 for endpoint d…
1686 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1692 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1694 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1751 …ATAL_ERR_STATUS_K2 (0x1<<13) // Advisory Non-Fatal Error Status.
1772 … (0x1<<13) // Advisory Non fatal Error Status. Only set if role_based_err_r…
1802 …ERR_MASK_K2 (0x1<<13) // Advisory Non-Fatal Error Mask. N…
1858 … (0x1f<<0) // First Error Pointer - These bits correspon…
1972 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1974 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1976 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1982 …nded VC Count. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1990 …on Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1999 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
2021 …// Reject Snoop Transactions. Note: The access attributes of this field are as follows: - Dbi: R
2023 … (0x3f<<16) // Maximum Time Slots-1 supported. Note: The access attributes of this field ar…
2057 …set indicates that the power budget for the device is included within the system power budget. Rep…
2077 … 0x000160UL //Access:R DataWidth:0x20 // The read-back value of this re…
2096 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2098 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2100 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2124 … 0x000174UL //Access:RW DataWidth:0x20 // The read-back value of this re…
2127 …ld is valid for all devices. Note: Bit 0 of this field is read only. It is set to 1 for the defaul…
2141 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2143 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2145 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2176 … 0x000180UL //Access:R DataWidth:0x20 // The read-only value of this re…
2201 … Allocated PB. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2203 … 0x000184UL //Access:R DataWidth:0x20 // The read-only value of this re…
2204 … (0xffff<<0) // VSEC ID. This field is a vendor-defined ID number tha…
2206 … (0xf<<16) // VSEC Rev. This field is a vendor-defined version numbe…
2208 …uding the PCI Express Enhanced Capability header, the Vendor-Specific header, and the Vendor-Speci…
2228 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2230 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2232 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2235 …ress and alignment of the BAR0 for each VF. This field may only have 1 bit set.This field is ignor…
2288 …ress and alignment of the BAR2 for each VF. This field may only have 1 bit set.This field is ignor…
2328 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2330 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2332 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2335 …ress and alignment of the BAR4 for each VF. This field may only have 1 bit set.This field is ignor…
2357 …0) // Perform Equalization. Note: The access attributes of this field are as follows: - Dbi: R/W
2359 …n Request Interrupt Enable. Note: The access attributes of this field are as follows: - Dbi: R/W
2382 …tter Preset 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2384 …Preset Hint 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2386 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2388 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2390 …tter Preset 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2392 …Preset Hint 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2394 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2396 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2405 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2406 …itter Preset2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2408 … Preset Hint2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2410 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2412 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2414 …itter Preset3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2416 … Preset Hint3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2418 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2420 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2423 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2424 …itter Preset4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2426 … Preset Hint4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2428 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2430 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2432 …itter Preset5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2434 … Preset Hint5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2436 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2438 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2441 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2442 …itter Preset6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2444 … Preset Hint6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2446 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2448 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2450 …itter Preset7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2452 … Preset Hint7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2454 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2456 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2458 …-only value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP, By default,…
2477 …, this register specifies the maximum no-snoop latency that a device is premitted to request. Soft…
2483 …, this register specifies the maximum no-snoop latency that a device is premitted to request. Soft…
2490 … 0x0001b8UL //Access:RW DataWidth:0x20 // SR-IOV Capability Header…
2491 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2493 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2495 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2497 … 0x0001b8UL //Access:R DataWidth:0x20 // The read-only value of this re…
2507 … 0x0001bcUL //Access:RW DataWidth:0x20 // SR-IOV Capability Regist…
2510 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2528 … 0x0001c0UL //Access:RW DataWidth:0x20 // SR-IOV Control and Statu…
2537 …access attributes of this field are as follows: - Dbi: R/W but read-value is not always same as w…
2539 … 0x0001c0UL //Access:R DataWidth:0x20 // The read-only value of this re…
2547 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2549 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2554 … (0x1<<1) // This field is only present in PF0. This bet when set indicates that the …
2575 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2576 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: STATUS_CONTROL_…
2587 … (0x1<<3) // When set, memory space is en…
2589 …_BB (0x1<<4) // When set, the device is perm…
2613 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register" det…
2615 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register". de…
2640 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2692 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2693 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2695 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2697 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2717 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2718 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2720 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2722 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2742 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2743 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2745 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2747 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2749 …-bit VF_BAR0 register programs the base address for the memory space mapped by the VFs belonging t…
2752 …ate that VF_BAR0 may be programmed to map this adapter to anywhere in the 64-bit address space. Bi…
2754 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR0 may be pre-fetched or cached by …
2758 … (0xfffff<<12) // These bits set the address within a 32-bit addr…
2777 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2778 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2780 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2782 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2784 … 0x0001e8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR1 register …
2802 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2803 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2805 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2807 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2809 …-bit VF_BAR2 register programs the base address for the memory space mapped by the VFs belonging t…
2812 …ate that VF_BAR2 may be programmed to map this adapter to anywhere in the 64-bit address space(reg…
2814 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR2 may be pre-fetched or cached by …
2818 … (0xfffff<<12) // These bits set the address within a 32-bit addr…
2837 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2838 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2840 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2842 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2844 … 0x0001f0UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR3 register …
2867 …-bit VF_BAR4 register programs the base address for the memory space mapped by the VFs belonging t…
2870 …ate that VF_BAR4 may be programmed to map this adapter to anywhere in the 64-bit address space(reg…
2872 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR4 may be pre-fetched or cached by …
2876 … (0xfffff<<12) // These bits set the address within a 32-bit addr…
2896 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2898 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2900 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2902 … 0x0001f8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR5 register …
2923 …ode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2925 …ode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2927 …ter Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2929 …ocation Bit 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2931 …ocation Bit 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2933 …ST Table Size. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2953 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
2957 … 0x000200UL //Access:R DataWidth:0x20 // The read-only value of this re…
2982 … 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
2984 … 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
3007 … (0x1<<0) // When Set, Function is permit…
3009 … (0x1<<1) // If Set, device is the PTM …
3049 … 0x000210UL //Access:R DataWidth:0x20 // The read-only value of this re…
3076 … (0x1<<5) // This bit when set indicates Untransla…
3084 … (0x1<<31) // When set, function is enable…
3127 … 0x000220UL //Access:R DataWidth:0x20 // The read-only value of this re…
3139 …5 (0x1<<2) // VF 10-bit tag requester sup…
3146 … (0x1<<4) // when Set, it indicates funct…
3148 … (0x1<<5) // when Set, it indicates funct…
3150 … (0x1<<6) // when Set, it indicates funct…
3152 … (0x1<<7) // when Set, it indicates funct…
3154 …B (0x1<<8) // when Set, it indicates funct…
3156 …B (0x1<<9) // when Set, it indicates funct…
3158 … (0x1<<10) // when Set, it indicates funct…
3160 …B (0x1<<11) // when Set, it indicates funct…
3162 …B (0x1<<12) // when Set, it indicates funct…
3164 …B (0x1<<13) // when Set, it indicates funct…
3166 … (0x1<<14) // when Set, it indicates funct…
3179 … (0x1<<4) // ARI capable hierarchy. 0 = All PFs have non-ARI capable hierarchy…
3181 …5 (0x1<<5) // VF 10-bit Tag Requester Ena…
3197 … (0xffff<<16) // Total VFs. Read-only copy of PCIEEP_S…
3204 … 0x000230UL //Access:R DataWidth:0x20 // The read-only value of this re…
3212 …-ARI capable hierarchies. The PCIEEP_SRIOV_CTL[ACH] determines which one is being used for SR-IOV…
3214 …-ARI: 0x1. There are two VF stride registers; one for each ARI capable and non-ARI capable…
3219 …R_MODE_SUPPORTED_BB (0x1<<1) // If Set function supports I…
3221 …DE_SUPPORTED_BB (0x1<<2) // If Set function supports d…
3225 …TPH_REQ_SUPP_BB (0x1<<8) // If Set function is capable…
3231 …ware reads this field to determine the STTable Size N, whihc is encoded as N-1. So a returned valu…
3245 …-only value of this register is controlled by setting bit 2 of the EXT2_CAP_ENA for EP, By default…
3255 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3274 … (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
3286 …LE_BB (0x1<<0) // When set, PM L1.2 is enabled.
3288 …LE_BB (0x1<<1) // When set, PM L1.1 is enabled.
3290 …ABLE_BB (0x1<<2) // When set, ASPM L1.2 is enabl…
3292 …ABLE_BB (0x1<<3) // When set, ASPM L1.1 is enabl…
3307 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3324 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3356 … (0x7ff<<16) // ST table size (limited by MSI-X table size).
3369 …d Capacity ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3371 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3373 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3375 … 0x000288UL //Access:RW DataWidth:0x20 // LTR Max Snoop and No-Snoop Latency Registe…
3380 …T_K2 (0x3ff<<16) // Max No-Snoop Latency Value.
3382 …LAT_SCALE_K2 (0x7<<26) // Max No-Snoop Latency Scale.
3384 … 0x00028cUL //Access:RW DataWidth:0x20 // Vendor-Specific Extended Cap…
3385 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3387 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3389 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3391 … 0x000290UL //Access:R DataWidth:0x20 // Vendor-Specific Header.
3398 …- Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register det…
3399 …ear' code. The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11:…
3401 …ays '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no…
3403 …alue of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT…
3405 …a returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - ..…
3407 …- 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the Group For e…
3409 …s the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTRO…
3410 …idth:0x20 // Time-based Analysis Control. Used for controlling the measurement of RX/TX data thr…
3411 … (0x1<<0) // Timer Start. - 0: Start/Restart - 1: Stop Th…
3413 …-based Duration Select. Selects the duration of time-based analysis. When "manual control" is sele…
3415 …-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_…
3417 …ataWidth:0x20 // Time-based Analysis Data. Contains the measurement results of RX/TX data throug…
3418 …- 0: CRC Error: EINJ0_CRC_REG - 1: Sequence Number Error: EINJ1_SEQNUM_REG - 2: DLLP Error: EINJ…
3431 …t. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_…
3433 …- LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link …
3434 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG r…
3436 …- 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b:…
3438 …- ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 409…
3439 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG r…
3441 …nce number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - …
3443 …-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. …
3445 …- If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the trans…
3446 …- If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_R…
3448 … inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block …
3450 …- If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeo…
3451 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG r…
3453 …- Mask K symbol. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set)…
3455 … - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Po…
3456 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG r…
3458 …-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Po…
3462 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is repr…
3464 … - For Duplicate TLP, the core initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These …
3465 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG r…
3467 …Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as N…
3533 … (0x3ff<<16) // Max no-snoop latency value.
3535 … (0x7<<26) // Max no-snoop latency scale.
3546 … 0x000300UL //Access:R DataWidth:0x20 // The read-only value of this re…
3554 …PCIPM_SUP_E5 (0x1<<0) // PCI-PM L12 supported.
3556 …PCIPM_SUP_E5 (0x1<<1) // PCI-PM L11 supported.
3577 …1_2_PCIPM_EN_E5 (0x1<<0) // PCI-PM L12 enable.
3579 …1_1_PCIPM_EN_E5 (0x1<<1) // PCI-PM L11 enable.
3589 …s. 0x2 = 1024 ns. 0x3 = 32,768 ns. 0x4 = 1,048,575 ns. 0x5 = 33,554,432 ns. 0x6-7 = Reserved.
3681 …remote device when all of the following conditions are true. - Using 128b/130b encoding - Inject…
3682 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG r…
3684 …ror Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EI…
3686 …e TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Pref…
3736 …ter data returned in the PCIEEP_RAS_EC_DATA[EV_CNTR_DATA]. 0x0-0x7 = Lane number. 0x8-0xF = Res…
3778 …-based duration select. Selects the duration of time-based analysis. 0x0 = Manual control. Ana…
3780 …EL_E5 (0xff<<24) // Time-based report select. …
3801 …s set, the core ignores receiver detection from PHY during LTSSM Detect state and uses this value …
3803 … (0x1<<16) // Force Detect Lane Enable. When this bit is set, the core ignores r…
3805 …-reset exit. The core selects the greater value between this register and the value defined by the…
3807 …should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the …
3812 …n this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This requ…
3814 … (0x1<<2) // Force LinkDown. When this bit is set and the core detect…
3816 … (0x1<<8) // Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in…
3818 … (0x1<<9) // Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in…
3820 … (0x1<<10) // Detect Loopback Slave To Exit. When this bit is set and the LTSSM is in…
3824 … // Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the…
3825 …er for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 …
3840 …- 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When …
3848 …-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negoti…
3851 …- 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDL…
3853 …- 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 08h: L1 - 09h: L1_BLOCK_…
3855 … Re-send flag. When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host soft…
3879 … (0x3<<24) // DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 1…
3886 …ns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ0_EN] is set, errors are inserte…
3888 …-FC DLLP. 0x3 = New TLP's ECRC error injection. 0x4 = TLP's FCRC error injection (128b/130b). 0…
3890 …LP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL…
3891 …ort-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data …
3893 …IT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CRE…
3895 …iewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 d…
3897 …TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_D…
3899 …TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value …
3901 …YPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value …
3904 …ns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ1_EN] is set, errors are inserte…
3908 …-assigned sequence numbers. This value is represented by two's complement. 0x0FFF = +4095. 0x0…
3911 …- 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: T…
3916 …ns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ2_EN] is set, errors are inserte…
3921 …ns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ3_EN] is set, errors are inserte…
3923 …- Mask K symbol. 0x0 = Reserved. 0x1 = COM/PAD(TS1 Order Set). 0x2 = COM/PAD(TS2 Order Set). …
3926 …ns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ4_EN] is set, errors are inserte…
3928 …-FC type. Selects the credit type. 0x0 = Posted TLP header credit value control. 0x1 = Non-Pos…
3932 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. The value is rep…
3934 …ng the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ…
3935 …-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] view…
3937 …the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/…
3939 …al Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11:…
3946 …ns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ5_EN] is set, errors are inserte…
3951 … (0x3f<<0) // Force Local Transmitter Pre-cursor. Indicates th…
3955 … (0x3f<<12) // Force Local Transmitter Post-Cursor. Indicates th…
3957 …lue of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of received or set value. Note: This …
3961 …fficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CUR…
3969 … (0x3f<<0) // Force Remote Transmitter Pre-Cursor. Indicates th…
3973 … (0x3f<<12) // Force Remote Transmitter Post-Cursor. Indicates th…
3975 …ficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CU…
3979 …ed unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_…
3982 …nformation. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x…
3994 …_K2 (0x3f<<0) // EQ Local Pre-Cursor. Indicates Lo…
3998 …K2 (0x3f<<12) // EQ Local Post-Cursor. Indicates Lo…
4006 …_K2 (0x3f<<0) // EQ Remote Pre-Cursor. Indicates Re…
4010 …K2 (0x3f<<12) // EQ Remote Post-Cursor. Indicates Re…
4023 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4025 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4027 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4039 …for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. …
4055 …mpletion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. …
4068 … 0x000398UL //Access:RW DataWidth:0x20 // Corrected error (1-bit ECC) counter sele…
4071 …) // Enable correctable errors counters. - 1: counters increment when the core detects a correcta…
4073 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4078 … 0x00039cUL //Access:R DataWidth:0x20 // Corrected error (1-bit ECC) counter data…
4081 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4083 … (0xff<<24) // Counter selection. Returns the value set in the CORR_COUNTER…
4086 … 0x0003a0UL //Access:RW DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) c…
4089 … Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correct…
4091 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4096 …ns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ6_EN] is set, errors are inserte…
4100 …ors into. 0x0 = TLP header. 0x1 = TLP prefix 1st 4-DWORDs. 0x2 = TLP prefix 2nd 4-DWORDs. 0x3…
4102 … 0x0003a4UL //Access:R DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) c…
4105 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4107 … (0xff<<24) // Counter selection. Returns the value set in the UNCORR_COUNT…
4109 …he following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection mod…
4110 … (0x1<<0) // Error injection global enable. When set enables the error i…
4112 … (0x3<<4) // Error injection type: - 0: none - 1: 1-bit - 2: 2-bit
4114 … (0xff<<8) // Error injection count. - 0: errors are inserted in every TLP until you clear ERR…
4119 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4123 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4128 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4132 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4136 …_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are for…
4142 … (0xffff<<0) // Force detect lane. When set, the core ignores r…
4144 … (0x1<<16) // Force detect lane enable. When this bit is set, the core ignores r…
4146 …-reset exit. The core selects the greater value between this register and the value defined by the…
4148 …ould set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PH…
4154 … (0x1<<0) // Hold and release LTSSM. For as long as this is set, the core stays in …
4156 … (0x1<<1) // Recovery request. When this bit is set in L0 or L0s, the L…
4158 … (0x1<<2) // Force link down. When this bit is set and the core detect…
4160 … (0x1<<8) // Direct Recovery.Idle to configuration. When this bit is set and the LTSSM is in…
4162 … (0x1<<9) // Direct Polling.Compliance to detect. When this bit is set and the LTSSM is in…
4164 … (0x1<<10) // Direct loopback slave to exit. When set and the LTSSM is in…
4168 …cUL //Access:R DataWidth:0x20 // RAM Address where a corrected error (1-bit ECC) has been det…
4169 … (0x7ffffff<<0) // RAM Address where a corrected error (1-bit ECC) has been det…
4171 … (0xf<<28) // RAM index where a corrected error (1-bit ECC) has been det…
4173 … //Access:R DataWidth:0x20 // RAM Address where an uncorrected error (2-bit ECC) has been det…
4174 … (0x7ffffff<<0) // RAM Address where an uncorrected error (2-bit ECC) has been det…
4176 … (0xf<<28) // RAM index where an uncorrected error (2-bit ECC) has been det…
4179 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4181 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4183 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4186 … silicon debug status register of Layer1-PerLane. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. 0x7 …
4201 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4203 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4205 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4207 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4210 …-STP/SDP/IDL token was received and it was not in TLP/DLLP reception. 0x02 = When current token w…
4218 …Set to one if both ports advertised the UpConfigure capability in the last Config.Complete. 0x4 =…
4221 … (0x1<<0) // PTM Enable. When set, this function is p…
4223 …set this Time Source is the PTM Root. For a description of this standard PCIe register, see the PC…
4225 …s Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT
4228 … 0x17 = L0S_BLOCK_TLP. 0x18 = WAIT_LAST_PMDLLP. 0x19 = WAIT_DSTATE_UPDATE. 0x20-0x1F = Reserved.
4230 …S_L23RDY_WAIT4ALIVE. 0x0F = S_L23RDY_WAIT4IDLE. 0x10 = S_WAIT_LAST_PMDLLP. 0x10-0x1F = Reserved.
4232 …_Status bit. If host software does not clear PME_Status bit for 100ms (+50%/-5%), the DUT resends …
4239 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4241 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4243 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4257 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4259 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4261 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4264 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields determi…
4266 …ith the [CREDIT_SEL_VC], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields determi…
4268 …] viewport-select fields determines that data that is returned by the [CREDIT_DATA0] and [CREDIT_D…
4270 …CREDIT_SEL_VC], [CREDIT_SEL_CREDIT_TYPE], and [CREDIT_SEL_TLP_TYPE] viewport-select fields determi…
4272 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = …
4274 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = …
4277 … (0x1<<0) // PTM Requester Auto Update Enabled - When enabled PTM Req…
4279 … (0x1<<1) // PTM Requester Start Update - When set the PTM Requeste…
4281 …K2 (0x1<<2) // PTM Fast Timers - Debug mode for PTM T…
4283 …- Determines the period between each auto update PTM Dialogue in miliseconds. Update period is the…
4286 …ion request rules. 0x0E = Invalid TLP type. 0x0F = Completion rules. 0x10-0x7E = Reserved. 0x7…
4291 … (0x1<<0) // PTM Requester Context Valid - Indicate that the Ti…
4293 … (0x1<<1) // PTM Requester Manual Update Allowed - Indicates whether or…
4298 …-lane silicon debug EQ status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] view…
4300 …ct. Setting this field in conjunction with [EQ_LANE_SEL] determines the per-lane silicon debug EQ…
4302 …his field is used when the ltssm is in Recovery.EQ2/3. When this field is set, the value of the E…
4318 …PresetHint value of EQ slave (DSP in EQ Phase2/USP in EQ Phase3), instead of received or set value.
4330 … (0x3f<<0) // Force remote transmitter pre-cursor as selected by…
4383 …bar_1 as a 32-bit address. The value of this bit maps directly to bit 2 of bar_1. This value is st…
4385 …/ This bit will force the PCI bus to re-try all cycles to the current Expansion ROM BAR area. When…
4387 …-try all cycles to the configuration space until it is cleared. This is used to block the host fro…
4389 … (0x1<<7) // This bit will be set the first time sinc…
4391 …en this value is non-zero, the Expansion ROM attention must be handled by an internal processor to…
4393 … (0x1<<16) // This bit when set is reflected in bit 3 of bar_1 and indicates that th…
4399 …t by HARD Reset such that it can be used to detect initial power up if a non-zero value is written…
4472 … (0xfff<<0) // PTM Requester TX Latency - Requester Transmit p…
4504 … (0xfff<<0) // PTM Requester RX Latency - Requester Receive pa…
4511 …). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved.
4516 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4518 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4520 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4525 …ot supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved.
4527 … (0xff<<24) // Counter selection. Returns the value set in PCIEEP_RASDP_CE_…
4530 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4532 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4534 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4536 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4538 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4540 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4542 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4544 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4546 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4548 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4550 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4552 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4554 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4556 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4558 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4560 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4562 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4564 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4566 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4568 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4571 …This bit will be set if there is a pending request for action by the firmware to handle a Vital Pr…
4578 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4587 …) // BAR Size. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4594 …set, then the host has requested the data in the vpd_data register to be passed to the NVM interfa…
4599 …). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved.
4601 … (0xff<<24) // Counter selection. Returns the value set in PCIEEP_RASDP_UCE…
4603 …set, this word should be read and written to the NVM interface. After the NVM interface write is c…
4605 … (0x1<<0) // Error injection global enable. When set, enables the error …
4607 … (0x3<<4) // Error injection type. 0x0 = None. 0x1 = 1-bit. 0x2 = 2-bit. 0x3 = Re…
4609 … 0x0 = errors are injected in every TLP until [ERR_INJ_EN] is cleared. 0x1 - 0xFF = number of err…
4619 …ot supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved.
4623 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4633 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4637 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4642 …the read value of the class_code register of the configuration space. The 24-bit Class Code regist…
4647 …DE_EN_E5 (0x1<<0) // Set this bit to enable …
4649 …NK_DN_EN_E5 (0x1<<1) // Set this bit to enable …
4664 …ogramming of the MSI Enable bit in PCI configuration space. If this bit is set, it means that the …
4669 …DE_CLR_E5 (0x1<<0) // Set this bit to take th…
4724 … (0x7fffff<<0) // Only bit 0 is currently defined - remote scaled flow c…
4748 … (0x1<<0) // PTM enable. When set, this function is p…
4750 … (0x1<<1) // PTM root select. When set this time source is…
4762 … 0x000468UL //Access:RW DataWidth:0x20 // Each pending bit that is set , the function has …
4778 … (0x1<<1) // PTM requester start update. When set the PTM Requester w…
4782 …egister value +1 milisecond. For the Switch product this value must not be set larger than 0x9 for…
4818 …orted resource sizes. PEM advertises the maximum allowable BAR size (512 GB - 0xF_FFFF) when the f…
4835 …ters located at 10h in configuration space is used to map the function's MSI-X table into memory s…
4837 … one of the functions Base address registers to point to the base of the MSI-X table. Value is con…
4847 …ters located at 10h in configuration space is used to map the function's MSI-X PBA into memory spa…
4849 … one of the functions Base address registers to point to the base of the MSI-X PBA Value is contro…
4859 …-zero values indicate some software-defined post-firmware loaded state information or failure code…
4864 … (0x1<<5) // This bit when set, hides any PCIE spe…
4866 … (0x1<<6) // This bit when set, sets the ASPM optionality bit in the Link cap register. This bit…
4890 …leared automatically after 55 ms if auto_clear bit in private reg space is set. This bit also exis…
4894 …set), this register will read a value of 1, indicating that all the VFs that belong to this PF sho…
4918 … (0x1<<4) // This bit enables the advertisement of bar_3 as a 32-bit address. The valu…
4920 … (0x1<<5) // This bit when set is reflected in bit 3 of bar_3 and indicates that th…
4925 … Timeout Ranges Supported. Controls value in same field in the config space 0xF- Ranges A,B,C and D
4931 …bit is valid only if IDO_Enabled is defined in version.v. When this bit is set, IDO feature is mad…
4935 …d to set this value to 2 or 3(also supported using Messages) This bit is valid only if PCIE_OBFF_S…
4944 …IVE_CAP_BB (0x1<<0) // RC only. If set, indicates dl_activ…
4946 …SLOT_CLK_CONFIG_BB (0x1<<1) // If set, indicates device u…
4951 … (0x1<<4) // This bit enables the advertisement of bar_5 as a 32-bit address. The valu…
4953 … (0x1<<5) // This bit when set is reflected in bit 3 of bar_5 and indicates that th…
4964 … (0x1f<<3) // If it is set, indicates RC suppo…
5030 …l extended capability is in 29:26 in dev_ser_num_cap_id register. The next set of capabilities are…
5052 … (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
5084 … (0x1<<7) // Enable User Defined Mem area in RC mode. If this bit is set, then memory transa…
5096 … (0x1<<7) // Enable User Defined Mem area in RC mode. If this bit is set, then memory transa…
5112 …UPP_BB (0x1<<0) // when Set, it indicates funct…
5114 …BB (0x1<<1) // When Set, it indicates funct…
5116 … is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. Al…
5123 …BILITY_BB (0x1<<4) // when Set, it indicates funct…
5125 …BILITY_BB (0x1<<5) // when Set, it indicates funct…
5127 …BILITY_BB (0x1<<6) // when Set, it indicates funct…
5129 …BILITY_BB (0x1<<7) // when Set, it indicates funct…
5131 …ABILITY_BB (0x1<<8) // when Set, it indicates funct…
5133 …ABILITY_BB (0x1<<9) // when Set, it indicates funct…
5135 …BILITY_BB (0x1<<10) // when Set, it indicates funct…
5137 …ABILITY_BB (0x1<<11) // when Set, it indicates funct…
5139 …ABILITY_BB (0x1<<12) // when Set, it indicates funct…
5141 …ABILITY_BB (0x1<<13) // when Set, it indicates funct…
5143 …ILITY_BB (0x1<<14) // when Set, it indicates funct…
5163 … (0x1<<4) // This bit enables the advertisement of VF BAR0 as a 64-bit address. The valu…
5165 … (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR0 and indicates that t…
5171 … (0x1<<12) // This bit enables the advertisement of VF BAR2 as a 64-bit address. The valu…
5173 … (0x1<<13) // This bit when set is reflected in bit 3 of VF BAR2 and indicates that t…
5183 …age sizes. This PF supports a page size of 2^n+12 if bit n is set. For eg, if bit 0 is set, PF sup…
5192 …bility structure of PF configuration space is used to map the function's MSI-X table into memory s…
5194 … one of the functions Base address registers to point to the base of the MSI-X table . All the VF'…
5197 …capability structure in PF configuration space is used to map the VF's's MSI-X PBA into memory spa…
5199 …ress contained by one of the functions Base address registers to point to the base of the MSI-X PBA
5209 … (0x1<<4) // This bit enables the advertisement of VF BAR4 as a 64-bit address. The valu…
5211 … (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR4 and indicates that t…
5226 …ls the corresponding value in the ATS capability register. This field qhen Set, indicates the Untr…
5231 …DE_SUPP_BB (0x1<<0) // when Set, it indicates funct…
5233 …ODE_BB (0x1<<1) // When Set, it indicates funct…
5235 … is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. Al…
5241 … (0x1<<31) // This field when set enables TPH capabil…
5244 …he ACK/NAK latency timer expires when it reaches this limit. This value is set correctly by the ha…
5246 …ay upon reception of a NAK or when the replay timer expires. This value is set correctly by the ha…
5249 …-7, 3-8, and 3-9 of the PCIe 3.0 specification. The limit must reflect the round trip latency from…
5251 …-4, 3-5, and 3-6 of the PCIe 3.0 specification. If there is a change in the payload size or link s…
5262 …nk state that the PCI Express bus is forced to when bit 15 (force link) is set. State encoding: 0x…
5264 …to SKP OS to do deskew for SRIS instead of using received SKP OS if DO_DESKEW_FOR_SRIS is set to 1.
5267 … (0xff<<0) // Link Number. Not used for endpoint. Not used for M-PCIe. Note: This reg…
5269 …ink Command. The link command that the core is forced to transmit when you set FORCE_EN bit (Force…
5271 …- Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the core to t…
5273 …// Forced LTSSM State. The LTSSM state that the core is forced to when you set the FORCE_EN bit (F…
5275 …many clock cycles for the associated completion of a CfgWr to D-state register to go low-power. Th…
5288 …even when link partner did not go to L0s (receive is not in L0s). When not set, core goes to ASPM …
5290 … 0x00070cUL //Access:RW DataWidth:0x20 // Ack Frequency and L0-L1 ASPM Control Regis…
5291 …- 0: Indicates that this Ack frequency control feature is turned off. The core schedules a low-pri…
5293 …-sets that a component can request is 255. The core does not support a value of zero; a value of z…
5295 …-sets that a component can request is 255. This field is only writable (sticky) when all of the fo…
5297 … - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us…
5299 … Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 …
5301 … (0x1<<30) // ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has …
5308 …iate loopback mode as a master. On a 0->1 transition, the PCIe core sends TS ordered sets with the…
5316 … (0x1<<6) // Link disable. Internally reserved field, do not set.
5318 …EPROM load, the first word loaded is 0xFFFFFFFF, the EEPROM load is terminated and this bit is set.
5322 …set as follows: 0x1 = x1. 0x3 = x2. 0x7 = x4. 0xF = x8. 0x1F = x16. 0x3F = x32 (not supported…
5326 … (0x1<<24) // Beacon enable. Internally reserved field, do not set.
5328 … (0x1<<25) // Corrupt LCRC enable. Internally reserved field, do not set.
5330 … (0x1<<26) // Extended synch. Internally reserved field, do not set.
5332 … (0x1<<27) // Transmit lane reversible enable. Internally reserved field, do not set.
5335 … the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register fie…
5339 …-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during C…
5347 …-outs and to link up faster. The scaling factor is selected in FAST_LINK_SCALING_FACTOR(default : …
5351 …". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supp…
5370 … (0xf<<27) // Set the implementation-specific n…
5372 … (0x1<<31) // Disable lane-to-lane deskew. Disables the internal lane-t…
5381 … (0x1<<31) // Disable Lane-to-Lane Deskew. Causes the core to disable the intern…
5384 … (0xff<<0) // Max number of functions supported. Used for SR-IOV.
5392 …actor. Sets the scaling factor of LTSSM timer when PCIEEP_PORT_CTL[FLM] is set. 0x0 = Scaling fac…
5397 …-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in inc…
5403 …set to 1b. - 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2…
5451 …- 0: For RADM RC filter to not allow CFG transaction being received - 1: For RADM RC filter to al…
5492 … 0x000734UL //Access:R DataWidth:0x20 // Transmit Non-Posted FC Credit Stat…
5493 … (0xfff<<0) // Transmit Non-Posted Data FC Credits. The non-poste…
5495 … (0xff<<12) // Transmit Non-Posted Header FC Credits. The non-post…
5522 … (0x1fff<<16) // FC latency timer override value. When you set PCIEEP_QUEUE_STATUS…
5524 … (0x1<<31) // FC latency timer override enable. When this bit is set, the value in PCIEE…
5533 … (0x1fff<<16) // FC Latency Timer Override Value. When you set the "FC Latency Tim…
5535 … (0x1<<31) // FC Latency Timer Override Enable. When this bit is set, the value from the…
5547 …xff<<0) // WRR Weight for VC0. Note: The access attributes of this field are as follows: - Dbi: R
5549 …xff<<8) // WRR Weight for VC1. Note: The access attributes of this field are as follows: - Dbi: R
5551 …ff<<16) // WRR Weight for VC2. Note: The access attributes of this field are as follows: - Dbi: R
5553 …ff<<24) // WRR Weight for VC3. Note: The access attributes of this field are as follows: - Dbi: R
5565 …xff<<0) // WRR Weight for VC4. Note: The access attributes of this field are as follows: - Dbi: R
5567 …xff<<8) // WRR Weight for VC5. Note: The access attributes of this field are as follows: - Dbi: R
5569 …ff<<16) // WRR Weight for VC6. Note: The access attributes of this field are as follows: - Dbi: R
5571 …ff<<24) // WRR Weight for VC7. Note: The access attributes of this field are as follows: - Dbi: R
5580 …-buffer configuration, writable through PEM()_CFG_WR. However, the application must not change thi…
5588 …he TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration,…
5590 …ines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration,…
5592 … 0x000748UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Posted Rec…
5593 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5595 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5603 …ly in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ord…
5605 …eues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs …
5614 …-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at a time: _ Bit 2…
5616 … (0x3<<24) // VC0 scale non-posted header credits.
5618 … (0x3<<26) // VC0 scale non-posted data credits.
5622 … 0x00074cUL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Non-Posted Receive…
5623 …-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segm…
5625 …-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the …
5640 …-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at a time: _ Bit 2…
5648 … 0x000750UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Completion…
5649 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5651 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5660 …set the TL TX does not send out pending requests if PM requests to block TLPS. By default TL will …
5662 … (0x1<<1) // Target mem Rd should not be greater than 1 DW if set.
5664 … (0x1<<2) // Target mem Rd should not be greater than 3 DW if set.
5666 … (0x1<<3) // Target mem Wr should not be greater than 1 DW if set.
5668 … (0x1<<4) // Target Expansion ROM should not be greater than 3 DW if set.
5670 … (0x1<<5) // Target mem Rd should not be greater than 16 DW if set .
5672 … (0x1<<6) // Target mem Rd should not be greater than 4 DW if set .
5674 … (0x1<<7) // Target mem Wr should not be greater than 4 DW if set .
5676 … (0x1<<8) // Target mem Wr should not be greater than 32 DW if set .
5678 … (0x1<<9) // Target mem Rd should not be greater than 32 DW if set .
5682 … (0x1<<12) // This bit if set will force DUT to n…
5684 …ER_55MS_BB (0x1<<13) // If set, DUT will automatic…
5686 …T_FLR_BB (0x1<<14) // If set, DUT will automatic…
5688 …B (0x1<<15) // If set, completions receiv…
5690 … (0x1<<16) // If set, this causes func0 …
5694 …B (0x1<<18) // when set, forces MSI_En to l…
5696 … (0x1<<19) // When set Beacon is enabled f…
5698 … (0x1<<20) // When set, Beacon generation …
5700 … (0x1<<21) // When set, it enables WAKE generation in any L-state, when PME_…
5704 …_BB (0x1<<23) // When set, TL does not get re…
5706 … (0x1<<24) // When set, it prevents PM from re-entering L1 when programm…
5714 …28) // In RC mode, when set, it enables pcie_scnd_rst_b to be asserted when Secondary reset bit in…
5716 … (0x1<<29) // In RC mode, when set, it forces pcie_scn…
5759 …) // When set, hardware will return completions and not wait for LTR message to be sent first even…
5777 … programmed in 'h840. This state has highest priority and when this bit is set, no other LTR messa…
5780 … (0x1<<0) // Poisoned Error Status Status Mask, if set, does not generate …
5782 … (0x1<<1) // Flow Control Protocol Error Status Status Mask, if set, does not generate …
5784 … (0x1<<2) // Completer Timeout Status Status Mask, if set, does not generate …
5786 … (0x1<<3) // Received UR Status, Status Mask, if set, does not generate …
5788 … (0x1<<4) // Unexpected Completion Status Status Mask, if set, does not generate …
5790 … (0x1<<5) // Receiver Overflow Status Status Mask, if set, does not generate …
5792 … (0x1<<6) // Malformed TLP Status Status Mask, if set, does not generate …
5794 … (0x1<<7) // ECRC Error TLP Status Status Mask, if set, does not generate …
5796 … (0x1<<8) // Unsupported Request Error Status Mask, if set, does not generate …
5798 … (0x1<<9) // Received target Abort Error Status Mask, if set, does not generate …
5800 … (0x1<<10) // Poisoned Error Status Status Mask for Function1, if set, does not generate …
5802 …1<<11) // Flow Control Protocol Error Status Status Mask for Function1, if set, does not generate …
5804 … (0x1<<12) // Completer Timeout Status Status Mask for Function1, if set, does not generate …
5806 … (0x1<<13) // Received UR Status, Status Mask for Function1, if set, does not generate …
5808 … (0x1<<14) // Unexpected Completion Status Status Mask for Function1, if set, does not generate …
5810 … (0x1<<15) // Receiver Overflow Status Status Mask for Function1, if set, does not generate …
5812 … (0x1<<16) // Malformed TLP Status Status Mask for Function1, if set, does not generate …
5814 … (0x1<<17) // ECRC Error TLP Status Status Mask for Function1, if set, does not generate …
5816 … (0x1<<18) // Unsupported Request Error Status Mask for Function1, if set, does not generate …
5818 … (0x1<<19) // Received target Abort Error Status Mask for Function1, if set, does not generate …
5820 … (0x1<<20) // rtag_val_unexp_attn Mask. If set, does not generate …
5822 … (0x1<<21) // tx_tag_in_use_attn Mask. If set, does not generate …
5824 … (0x1<<22) // DL Error Status Mask. If set, does not generate …
5826 … (0x1<<23) // PHY Error Status Mask. If set, does not generate …
5830 …RR_ATTN_MASK_BB (0x1<<25) // If set, TX reports user in…
5843 …PHY's ability to recover synchronization after a low power state. Do not set [N_FTS] to zero; do…
5845 …0x1 = 1 lane. 0x2 = 2 lanes. 0x3 = 3 lanes. _ ... 0x10 = 16 lanes. 0x11-0x1F = Reserved. Wh…
5847 …e0 to physical lane 7. 0x4 = Connect logical Lane0 to physical lane 15. 0x5 - 0x7 = Reserved.
5853 …cates the voltage level that the PHY should drive. When set to one, indicates low swing. When set …
5855 … (0x1<<19) // Config TX compliance receive bit. When set to one, signals LTS…
5857 … (0x1<<20) // Set the deemphasis level for upstream ports. 0 = -6 …
5862 …set N_FTS to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0…
5864 …- 0x01: 1 lane - 0x02: 2 lanes - 0x03: 3 lanes - .. When you have unused lanes in your system, …
5866 …- 3'b000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8…
5868 …set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature…
5870 …- Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deas…
5872 …ld. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe. Note: The …
5874 …set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal …
5876 …set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link o…
5878 …core by just detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Id…
5885 …asing of Posted header credit. When this bit is set, PH credits are not released by IP if FIFO at …
5887 … (0x1<<3) // Indicates no non-posted credit is available to user when bit is…
5891 … (0x1<<5) // When set , disables entry into L1, due to function being in D0unin…
5897 … (0x1<<16) // This bit when set prevents DUT from entering L1 due to being in…
5899 … (0x7fff<<17) // Programmable delay to prevent link from re-entering L1, when lin…
5911 … (0x1<<0) // This bit is set when h/w detects Poisoned Error Status . If…
5913 … (0x1<<1) // This bit is set when h/w detects Flow Control Protocol Error Statu…
5915 … (0x1<<2) // This bit is set when h/w detects Completer Timeout Status . I…
5917 … (0x1<<3) // This bit is set when h/w detects Receive UR Status. If se…
5919 … (0x1<<4) // This bit is set when h/w detects Unexpected Completion Status .…
5921 … (0x1<<5) // This bit is set when h/w detects Receiver Overflow Status . I…
5923 … (0x1<<6) // This bit is set when h/w detects Malformed TLP Status . If …
5925 … (0x1<<7) // This bit is set when h/w detects ECRC Error TLP Status , If…
5927 … (0x1<<8) // This bit is set when h/w detects Unsupported Request Error Status…
5931 … (0x1<<10) // This bit is set when h/w detects Poisoned Error Status in function…
5933 … (0x1<<11) // This bit is set when h/w detects Flow Control Protocol Error Status in f…
5935 … (0x1<<12) // This bit is set when h/w detects Completer Timeout Status in functi…
5937 … (0x1<<13) // This bits is set when h/w detects Receive UR Status in function 1…
5939 … (0x1<<14) // This bit is set when h/w detects Unexpected Completion Status in func…
5941 … (0x1<<15) // This bit is set when h/w detects Receiver Overflow Status in functi…
5943 … (0x1<<16) // This bit is set when h/w detects Malformed TLP Status in function…
5945 … (0x1<<17) // This bit is set when h/w detects ECRC Error TLP Status in function…
5947 … (0x1<<18) // This bit is set when h/w detects Unsupported Request Error Status in fu…
6069 … (0x1<<0) // Poisoned Error Status Status Mask, if set, does not generate …
6071 … (0x1<<1) // Flow Control Protocol Error Status Status Mask, if set, does not generate …
6073 … (0x1<<2) // Completer Timeout Status Status Mask, if set, does not generate …
6075 … (0x1<<3) // Received UR Status, Status Mask, if set, does not generate …
6077 … (0x1<<4) // Unexpected Completion Status Status Mask, if set, does not generate …
6079 … (0x1<<5) // Receiver Overflow Status Status Mask, if set, does not generate …
6081 … (0x1<<6) // Malformed TLP Status Status Mask, if set, does not generate …
6083 … (0x1<<7) // ECRC Error TLP Status Status Mask, if set, does not generate …
6085 … (0x1<<8) // Unsupported Request Error Status Mask, if set, does not generate …
6087 … (0x1<<9) // Received target Abort Error Status Mask, if set, does not generate …
6089 … (0x1<<10) // Poisoned Error Status Status Mask for Function3, if set, does not generate …
6091 …1<<11) // Flow Control Protocol Error Status Status Mask for Function3, if set, does not generate …
6093 … (0x1<<12) // Completer Timeout Status Status Mask for Function3, if set, does not generate …
6095 … (0x1<<13) // Received UR Status, Status Mask for Function3, if set, does not generate …
6097 … (0x1<<14) // Unexpected Completion Status Status Mask for Function3, if set, does not generate …
6099 … (0x1<<15) // Receiver Overflow Status Status Mask for Function3, if set, does not generate …
6101 … (0x1<<16) // Malformed TLP Status Status Mask for Function3, if set, does not generate …
6103 … (0x1<<17) // ECRC Error TLP Status Status Mask for Function3, if set, does not generate …
6105 … (0x1<<18) // Unsupported Request Error Status Mask for Function3, if set, does not generate …
6107 … (0x1<<19) // Received target Abort Error Status Mask for Function3, if set, does not generate …
6109 … (0x1<<20) // Poisoned Error Status Status Mask for Function4, if set, does not generate …
6111 …1<<21) // Flow Control Protocol Error Status Status Mask for Function4, if set, does not generate …
6113 … (0x1<<22) // Completer Timeout Status Status Mask for Function4, if set, does not generate …
6115 … (0x1<<23) // Received UR Status, Status Mask for Function4, if set, does not generate …
6117 … (0x1<<24) // Unexpected Completion Status Status Mask for Function4, if set, does not generate …
6119 … (0x1<<25) // Receiver Overflow Status Status Mask for Function4, if set, does not generate …
6121 … (0x1<<26) // Malformed TLP Status Status Mask for Function4, if set, does not generate …
6123 … (0x1<<27) // ECRC Error TLP Status Status Mask for Function4, if set, does not generate …
6125 … (0x1<<28) // Unsupported Request Error Status Mask for Function4, if set, does not generate …
6127 … (0x1<<29) // Received target Abort Error Status Mask for Function4, if set, does not generate …
6132 … (0x1<<0) // This bit is set when h/w detects Poisoned Error Status for Functio…
6134 … (0x1<<1) // This bit is set when h/w detects Flow Control Protocol Error Status for F…
6136 … (0x1<<2) // This bit is set when h/w detects Completer Timeout Status for Functi…
6138 … (0x1<<3) // This bit is set when h/w detects Receive UR Status in Function 2…
6140 … (0x1<<4) // This bit is set when h/w detects Unexpected Completion Status for Func…
6142 … (0x1<<5) // This bit is set when h/w detects Receiver Overflow Status for Functi…
6144 … (0x1<<6) // This bit is set when h/w detects Malformed TLP Status for Function…
6146 … (0x1<<7) // This bit is set when h/w detects ECRC Error TLP Status for Functio…
6148 … (0x1<<8) // This bit is set when h/w detects Unsupported Request Error Status for Fu…
6152 … (0x1<<10) // This bit is set when h/w detects Poisoned Error Status in function…
6154 … (0x1<<11) // This bit is set when h/w detects Flow Control Protocol Error Status in f…
6156 … (0x1<<12) // This bit is set when h/w detects Completer Timeout Status in functi…
6158 … (0x1<<13) // This bit is set when h/w detects Receive UR Status in function 3…
6160 … (0x1<<14) // This bit is set when h/w detects Unexpected Completion Status in func…
6162 … (0x1<<15) // This bit is set when h/w detects Receiver Overflow Status in functi…
6164 … (0x1<<16) // s bit is set when h/w detects Malformed TLP Status Status in funct…
6166 … (0x1<<17) // This bit is set when h/w detects ECRC Error TLP Status in function…
6168 … (0x1<<18) // This bit is set when h/w detects Unsupported Request Error Status in fu…
6172 … (0x1<<20) // This bit is set when h/w detects Poisoned Error Status Status in func…
6174 … (0x1<<21) // This bit is set when h/w detects Flow Control Protocol Error Status in f…
6176 … (0x1<<22) // This bit is set when h/w detects Completer Timeout Status in functi…
6178 … (0x1<<23) // This bit is set when h/w detects Receive UR Statusin function 4…
6180 … (0x1<<24) // This bit is set when h/w detects Unexpected Completion Status in func…
6182 … (0x1<<25) // This bit is set when h/w detects Receiver Overflow Status in functi…
6184 … (0x1<<26) // This bit is set when h/w detects Malformed TLP Status in function…
6186 … (0x1<<27) // This bit is set when h/w detects ECRC Error TLP Status in function…
6188 … (0x1<<28) // This bit is set when h/w detects Unsupported Request Error Status in fu…
6195 … (0x1<<0) // Poisoned Error Status Status Mask. If set, does not generate …
6197 … (0x1<<1) // Flow Control Protocol Error Status Status Mask. If set, does not generate …
6199 … (0x1<<2) // Completer Timeout Status Status Mask. If set, does not generate …
6201 … (0x1<<3) // Received UR Status, Status Mask. If set, does not generate …
6203 … (0x1<<4) // Unexpected Completion Status Status Mask. If set, does not generate …
6205 … (0x1<<5) // Receiver Overflow Status Status Mask. If set, does not generate …
6207 … (0x1<<6) // Malformed TLP Status Status Mask. If set, does not generate …
6209 … (0x1<<7) // ECRC Error TLP Status Status Mask. If set, does not generate …
6211 … (0x1<<8) // Unsupported Request Error Status Mask. If set, does not generate …
6213 … (0x1<<9) // Received target Abort Error Status Mask. If set, does not generate …
6215 … (0x1<<10) // Poisoned Error Status Status Mask for Function6. if set, does not generate …
6217 …1<<11) // Flow Control Protocol Error Status Status Mask for Function6. if set, does not generate …
6219 … (0x1<<12) // Completer Timeout Status Status Mask for Function6. if set, does not generate …
6221 … (0x1<<13) // Received UR Status, Status Mask for Function6. if set, does not generate …
6223 … (0x1<<14) // Unexpected Completion Status Status Mask for Function6. if set, does not generate …
6225 … (0x1<<15) // Receiver Overflow Status Status Mask for Function6. if set, does not generate …
6227 … (0x1<<16) // Malformed TLP Status Status Mask for Function6. if set, does not generate …
6229 … (0x1<<17) // ECRC Error TLP Status Status Mask for Function6. if set, does not generate …
6231 … (0x1<<18) // Unsupported Request Error Status Mask for Function6. if set, does not generate …
6233 … (0x1<<19) // Received target Abort Error Status Mask for Function6. if set, does not generate …
6235 … (0x1<<20) // Poisoned Error Status Status Mask for Function7. if set, does not generate …
6237 …1<<21) // Flow Control Protocol Error Status Status Mask for Function7. if set, does not generate …
6239 … (0x1<<22) // Completer Timeout Status Status Mask for Function7. if set, does not generate …
6241 … (0x1<<23) // Received UR Status, Status Mask for Function7. if set, does not generate …
6243 … (0x1<<24) // Unexpected Completion Status Status Mask for Function7. if set, does not generate …
6245 … (0x1<<25) // Receiver Overflow Status Status Mask for Function7, if set, does not generate …
6247 … (0x1<<26) // Malformed TLP Status Status Mask for Function7. if set, does not generate …
6249 … (0x1<<27) // ECRC Error TLP Status Status Mask for Function7. if set, does not generate …
6251 … (0x1<<28) // Unsupported Request Error Status Mask for Function7. if set, does not generate …
6253 … (0x1<<29) // Received target Abort Error Status Mask for Function7. if set, does not generate …
6258 … (0x1<<0) // Poisoned Error Status detected for Function 5. If set, hw generates pcie_…
6260 …(0x1<<1) // Flow Control Protocol Error Status detected for Function 5, if set, generate pcie_err_…
6262 … (0x1<<2) // Completer Timeout Status detected for Function 5. If set, hw generates pcie_…
6264 … (0x1<<3) // Receive UR Status detectedfor Function 5. If set, generate pcie_err_…
6266 … (0x1<<4) // Unexpected Completion Status detected for Function 5, if set, generate pcie_err_…
6268 … (0x1<<5) // Receiver Overflow Status detected for Function 5. If set, hw generates pcie_…
6270 … (0x1<<6) // Malformed TLP Status detected for Function 5. If set, hw generates pcie_…
6272 … (0x1<<7) // ECRC Error TLP Status detected for Function 5. If set, hw generates pcie_…
6274 … (0x1<<8) // Unsupported Request Error Status detected for Function 5. If set, hw generates pcie_…
6278 … (0x1<<10) // Poisoned Error Status detected in function 6. If set, hw generates pcie_…
6280 …(0x1<<11) // Flow Control Protocol Error Status detected in function 6, if set, generate pcie_err_…
6282 … (0x1<<12) // Completer Timeout Status detected in function 6. If set, hw generates pcie_…
6284 … (0x1<<13) // Receive UR Status detectedin function 6. If set, generate pcie_err_…
6286 … (0x1<<14) // Unexpected Completion Status detected in function 6, if set, generate pcie_err_…
6288 … (0x1<<15) // Receiver Overflow Status detected in function 6. If set, hw generates pcie_…
6290 … (0x1<<16) // Malformed TLP Status detected in function 6. If set, hw generates pcie_…
6292 … (0x1<<17) // ECRC Error TLP Status detected in function 6. If set, hw generates pcie_…
6294 … (0x1<<18) // Unsupported Request Error Status detected in function6. If set, hw generates pcie_…
6298 … (0x1<<20) // Poisoned Error Status detected in function 7. If set, hw generates pcie_…
6300 …(0x1<<21) // Flow Control Protocol Error Status detected in function 7, if set, generate pcie_err_…
6302 … (0x1<<22) // Completer Timeout Status detected in function 7. If set, hw generates pcie_…
6304 … (0x1<<23) // Receive UR Status detectedin function 7. If set, generate pcie_err_…
6306 … (0x1<<24) // Unexpected Completion Status detected in function 7, if set, generate pcie_err_…
6308 … (0x1<<25) // Receiver Overflow Status detected in function 7. If set, hw generates pcie_…
6310 … (0x1<<26) // Malformed TLP Status detected in function 7. If set, hw generates pcie_…
6312 … (0x1<<27) // ECRC Error TLP Status detected in function 7. If set, hw generates pcie_…
6314 … (0x1<<28) // Unsupported Request Error Status detected in function7. If set, hw generates pcie_…
6363 … (0x1<<2) // This bit when set will reset the Serdes register space, provided bit 3…
6365 … (0x1<<3) // Tthis bit when set will allow bit 2 va…
6367 … (0x1<<4) // This bit when set will reset the micro, provided bit 5 is also…
6369 … (0x1<<5) // For gen3 serdes, this bit when set will allow bit 4 va…
6389 …HIDDEN_BB (0x1<<0) // Set if func1 is hidden …
6391 …HIDDEN_BB (0x1<<1) // Set if func2 is hidden …
6393 …HIDDEN_BB (0x1<<2) // Set if func3 is hidden …
6395 …HIDDEN_BB (0x1<<3) // Set if func4 is hidden …
6397 …HIDDEN_BB (0x1<<4) // Set if func5 is hidden …
6399 …HIDDEN_BB (0x1<<5) // Set if func6 is hidden …
6401 …HIDDEN_BB (0x1<<6) // Set if func7 is hidden …
6403 …HIDDEN_BB (0x1<<7) // Set if func8 is hidden …
6405 …HIDDEN_BB (0x1<<8) // Set if func9 is hidden …
6407 …_HIDDEN_BB (0x1<<9) // Set if func10 is hidden…
6409 …HIDDEN_BB (0x1<<10) // Set if func11 is hidden…
6411 …HIDDEN_BB (0x1<<11) // Set if func12 is hidden…
6413 …HIDDEN_BB (0x1<<12) // Set if func13 is hidden…
6415 …HIDDEN_BB (0x1<<13) // Set if func14 is hidden…
6417 …HIDDEN_BB (0x1<<14) // Set if func15 is hidden…
6452 … (0x1<<0) // Poisoned Error Status Status Mask for Function8. If set, does not generate …
6454 …x1<<1) // Flow Control Protocol Error Status Status Mask for Function8. If set, does not generate …
6456 … (0x1<<2) // Completer Timeout Status Status Mask for Function8. If set, does not generate …
6458 … (0x1<<3) // Received UR Status, Status Mask for Function8. If set, does not generate …
6460 … (0x1<<4) // Unexpected Completion Status Status Mask for Function8. If set, does not generate …
6462 … (0x1<<5) // Receiver Overflow Status Status Mask for Function8. If set, does not generate …
6464 … (0x1<<6) // Malformed TLP Status Status Mask for Function8. If set, does not generate …
6466 … (0x1<<7) // ECRC Error TLP Status Status Mask for Function8. If set, does not generate …
6468 … (0x1<<8) // Unsupported Request Error Status Mask for Function8. If set, does not generate …
6470 … (0x1<<9) // Received target Abort Error Status Mask for Function8. If set, does not generate …
6472 … (0x1<<10) // Poisoned Error Status Status Mask for Function9. If set, does not generate …
6474 …1<<11) // Flow Control Protocol Error Status Status Mask for Function9. If set, does not generate …
6476 … (0x1<<12) // Completer Timeout Status Status Mask for Function9. If set, does not generate …
6478 … (0x1<<13) // Received UR Status, Status Mask for Function9. If set, does not generate …
6480 … (0x1<<14) // Unexpected Completion Status Status Mask for Function9. If set, does not generate …
6482 … (0x1<<15) // Receiver Overflow Status Status Mask for Function9. If set, does not generate …
6484 … (0x1<<16) // Malformed TLP Status Status Mask for Function9. If set, does not generate …
6486 … (0x1<<17) // ECRC Error TLP Status Status Mask for Function9. If set, does not generate …
6488 … (0x1<<18) // Unsupported Request Error Status Mask for Function9. If set, does not generate …
6490 … (0x1<<19) // Received target Abort Error Status Mask for Function9. If set, does not generate …
6492 … (0x1<<20) // Poisoned Error Status Status Mask for Function10. If set, does not generate …
6494 …<<21) // Flow Control Protocol Error Status Status Mask for Function10. If set, does not generate …
6496 … (0x1<<22) // Completer Timeout Status Status Mask for Function10. If set, does not generate …
6498 … (0x1<<23) // Received UR Status, Status Mask for Function10. If set, does not generate …
6500 … (0x1<<24) // Unexpected Completion Status Status Mask for Function10. If set, does not generate …
6502 … (0x1<<25) // Receiver Overflow Status Status Mask for Function10. If set, does not generate …
6504 … (0x1<<26) // Malformed TLP Status Status Mask for Function10. If set, does not generate …
6506 … (0x1<<27) // ECRC Error TLP Status Status Mask for Function10. If set, does not generate …
6508 … (0x1<<28) // Unsupported Request Error Status Mask for Function10. If set, does not generate …
6510 … (0x1<<29) // Received target Abort Error Status Mask for Function10. If set, does not generate …
6515 … (0x1<<0) // Poisoned Error Status detected for Function 8. If set, hw generates pcie_…
6517 …(0x1<<1) // Flow Control Protocol Error Status detected for Function 8, if set, generate pcie_err_…
6519 … (0x1<<2) // Completer Timeout Status detected for Function 8. If set, hw generates pcie_…
6521 … (0x1<<3) // Receive UR Status detectedfor Function 8. If set, generate pcie_err_…
6523 … (0x1<<4) // Unexpected Completion Status detected for Function 8, if set, generate pcie_err_…
6525 … (0x1<<5) // Receiver Overflow Status detected for Function 8. If set, hw generates pcie_…
6527 … (0x1<<6) // Malformed TLP Status detected for Function 8. If set, hw generates pcie_…
6529 … (0x1<<7) // ECRC Error TLP Status detected for Function 8. If set, hw generates pcie_…
6531 … (0x1<<8) // Unsupported Request Error Status detected for Function 8. If set, hw generates pcie_…
6535 … (0x1<<10) // Poisoned Error Status detected in function 9. If set, hw generates pcie_…
6537 …(0x1<<11) // Flow Control Protocol Error Status detected in function 9, if set, generate pcie_err_…
6539 … (0x1<<12) // Completer Timeout Status detected in function 9. If set, hw generates pcie_…
6541 … (0x1<<13) // Receive UR Status detectedin function 9. If set, generate pcie_err_…
6543 … (0x1<<14) // Unexpected Completion Status detected in function 9, if set, generate pcie_err_…
6545 … (0x1<<15) // Receiver Overflow Status detected in function 9. If set, hw generates pcie_…
6547 … (0x1<<16) // Malformed TLP Status detected in function 9. If set, hw generates pcie_…
6549 … (0x1<<17) // ECRC Error TLP Status detected in function 9. If set, hw generates pcie_…
6551 … (0x1<<18) // Unsupported Request Error Status detected in function9. If set, hw generates pcie_…
6555 … (0x1<<20) // Poisoned Error Status detected in function 10. If set, hw generates pcie_…
6557 …0x1<<21) // Flow Control Protocol Error Status detected in function 10, if set, generate pcie_err_…
6559 … (0x1<<22) // Completer Timeout Status detected in function 10. If set, hw generates pcie_…
6561 … (0x1<<23) // Receive UR Status detectedin function 10. If set, generate pcie_err_…
6563 … (0x1<<24) // Unexpected Completion Status detected in function 10, if set, generate pcie_err_…
6565 … (0x1<<25) // Receiver Overflow Status detected in function 10. If set, hw generates pcie_…
6567 … (0x1<<26) // Malformed TLP Status detected in function 10. If set, hw generates pcie_…
6569 … (0x1<<27) // ECRC Error TLP Status detected in function 10. If set, hw generates pcie_…
6571 … (0x1<<28) // Unsupported Request Error Status detected in function10. If set, hw generates pcie_…
6578 … (0x1<<0) // Poisoned Error Status Status Mask for Function11. If set, hw does not genera…
6580 …1<<1) // Flow Control Protocol Error Status Status Mask for Function11. If set, hw does not genera…
6582 … (0x1<<2) // Completer Timeout Status Status Mask for Function11. If set, hw does not genera…
6584 … (0x1<<3) // Received UR Status, Status Mask for Function11. If set, hw does not genera…
6586 … (0x1<<4) // Unexpected Completion Status Status Mask for Function11. If set, hw does not genera…
6588 … (0x1<<5) // Receiver Overflow Status Status Mask for Function11. If set, hw does not genera…
6590 … (0x1<<6) // Malformed TLP Status Status Mask for Function11. If set, hw does not genera…
6592 … (0x1<<7) // ECRC Error TLP Status Status Mask for Function11. If set, hw does not genera…
6594 … (0x1<<8) // Unsupported Request Error Status Mask for Function11. If set, hw does not genera…
6596 … (0x1<<9) // Received target Abort Error Status Mask for Function11. If set, hw does not genera…
6598 … (0x1<<10) // Poisoned Error Status Status Mask for Function12. If set, hw does not genera…
6600 …<<11) // Flow Control Protocol Error Status Status Mask for Function12. If set, hw does not genera…
6602 … (0x1<<12) // Completer Timeout Status Status Mask for Function12. If set, hw does not genera…
6604 … (0x1<<13) // Received UR Status, Status Mask for Function12. If set, hw does not genera…
6606 … (0x1<<14) // Unexpected Completion Status Status Mask for Function12. If set, hw does not genera…
6608 … (0x1<<15) // Receiver Overflow Status Status Mask for Function12. If set, hw does not genera…
6610 … (0x1<<16) // Malformed TLP Status Status Mask for Function12. If set, hw does not genera…
6612 … (0x1<<17) // ECRC Error TLP Status Status Mask for Function12. If set, hw does not genera…
6614 … (0x1<<18) // Unsupported Request Error Status Mask for Function12. If set, hw does not genera…
6616 … (0x1<<19) // Received target Abort Error Status Mask for Function12. If set, hw does not genera…
6618 … (0x1<<20) // Poisoned Error Status Status Mask for Function13. If set, hw does not genera…
6620 …<<21) // Flow Control Protocol Error Status Status Mask for Function13. If set, hw does not genera…
6622 … (0x1<<22) // Completer Timeout Status Status Mask for Function13. If set, hw does not genera…
6624 … (0x1<<23) // Received UR Status, Status Mask for Function13. If set, hw does not genera…
6626 … (0x1<<24) // Unexpected Completion Status Status Mask for Function13. If set, hw does not genera…
6628 … (0x1<<25) // Receiver Overflow Status Status Mask for Function13. If set, hw does not genera…
6630 … (0x1<<26) // Malformed TLP Status Status Mask for Function13. If set, hw does not genera…
6632 … (0x1<<27) // ECRC Error TLP Status Status Mask for Function13. If set, hw does not genera…
6634 … (0x1<<28) // Unsupported Request Error Status Mask for Function13. If set, hw does not genera…
6636 … (0x1<<29) // Received target Abort Error Status Mask for Function13. If set, hw does not genera…
6641 …gating feature when there is no receive traffic, receive queues and pre/post-queue pipelines are e…
6644 … (0x1<<0) // Poisoned Error Status detected for Function 11. If set, hw generates pcie_…
6646 …0x1<<1) // Flow Control Protocol Error Status detected for Function 11. If set, hw generates pcie_…
6648 … (0x1<<2) // Completer Timeout Status detected for Function 11. If set, hw generates pcie_…
6650 … (0x1<<3) // Receive UR Status detectedfor Function 11. If set, hw generates pcie_…
6652 … (0x1<<4) // Unexpected Completion Status detected for Function 11. If set, hw generates, gene…
6654 … (0x1<<5) // Receiver Overflow Status detected for Function 11. If set, hw generates pcie_…
6656 … (0x1<<6) // Malformed TLP Status detected for Function 11. If set, hw generates pcie_…
6658 … (0x1<<7) // ECRC Error TLP Status detected for Function 11. If set, hw generates pcie_…
6660 … (0x1<<8) // Unsupported Request Error Status detected for Function 11. If set, hw generates pcie_…
6664 … (0x1<<10) // Poisoned Error Status detected in function 12. If set, hw generates pcie_…
6666 …0x1<<11) // Flow Control Protocol Error Status detected in function 12. If set, hw generates pcie_…
6668 … (0x1<<12) // Completer Timeout Status detected in function 12. If set, hw generates pcie_…
6670 … (0x1<<13) // Receive UR Status detectedin function 12. If set, hw generates pcie_…
6672 … (0x1<<14) // Unexpected Completion Status detected in function 12. If set, hw generates pcie_…
6674 … (0x1<<15) // Receiver Overflow Status detected in function 12. If set, hw generates pcie_…
6676 … (0x1<<16) // Malformed TLP Status detected in function 12. If set, hw generates pcie_…
6678 … (0x1<<17) // ECRC Error TLP Status detected in function 12. If set, hw generates pcie_…
6680 … (0x1<<18) // Unsupported Request Error Status detected in function12. If set, hw generates pcie_…
6684 … (0x1<<20) // Poisoned Error Status detected in function 13. If set, hw generates pcie_…
6686 …0x1<<21) // Flow Control Protocol Error Status detected in function 13. If set, hw generates pcie_…
6688 … (0x1<<22) // Completer Timeout Status detected in function 13. If set, hw generates pcie_…
6690 … (0x1<<23) // Receive UR Status detectedin function 13. If set, hw generates pcie_…
6692 … (0x1<<24) // Unexpected Completion Status detected in function 13. If set, hw generates pcie_…
6694 … (0x1<<25) // Receiver Overflow Status detected in function 13. If set, hw generates pcie_…
6696 … (0x1<<26) // Malformed TLP Status detected in function 13. If set, hw generates pcie_…
6698 … (0x1<<27) // ECRC Error TLP Status detected in function 13. If set, hw generates pcie_…
6700 … (0x1<<28) // Unsupported Request Error Status detected in function13. If set, hw generates pcie_…
6707 … (0x1<<0) // Gen3 receiver impedance ZRX-DC not compliant.
6729 …and it means USP can set DSP TxPreset value in Gen4 Data Rate. If this register set to 0, USP send…
6735 …-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is us…
6736 …-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defin…
6740 …Gen4 data rate. Note: The access attributes of this field are as follows: - Dbi: see description…
6746 …set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 …
6748 …set to '1', the core as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation an…
6759 … (0x1<<0) // Poisoned Error Status Status Mask for Function14. If set, does not generate …
6761 …1<<1) // Flow Control Protocol Error Status Status Mask for Function14. If set, does not generate …
6763 … (0x1<<2) // Completer Timeout Status Status Mask for Function14. If set, does not generate …
6765 … (0x1<<3) // Received UR Status, Status Mask for Function14. If set, does not generate …
6767 … (0x1<<4) // Unexpected Completion Status Status Mask for Function14. If set, does not generate …
6769 … (0x1<<5) // Receiver Overflow Status Status Mask for Function14. If set, does not generate …
6771 … (0x1<<6) // Malformed TLP Status Status Mask for Function14. If set, does not generate …
6773 … (0x1<<7) // ECRC Error TLP Status Status Mask for Function14. If set, does not generate …
6775 … (0x1<<8) // Unsupported Request Error Status Mask for Function14. If set, does not generate …
6777 … (0x1<<9) // Received target Abort Error Status Mask for Function14. If set, does not generate …
6779 … (0x1<<10) // Poisoned Error Status Status Mask for Function15. If set, does not generate …
6781 …<<11) // Flow Control Protocol Error Status Status Mask for Function15. If set, does not generate …
6783 … (0x1<<12) // Completer Timeout Status Status Mask for Function15. If set, does not generate …
6785 … (0x1<<13) // Received UR Status, Status Mask for Function15. If set, does not generate …
6787 … (0x1<<14) // Unexpected Completion Status Status Mask for Function15. If set, does not generate …
6789 … (0x1<<15) // Receiver Overflow Status Status Mask for Function15. If set, does not generate …
6791 … (0x1<<16) // Malformed TLP Status Status Mask for Function15. If set, does not generate …
6793 … (0x1<<17) // ECRC Error TLP Status Status Mask for Function15. If set, does not generate …
6795 … (0x1<<18) // Unsupported Request Error Status Mask for Function15. If set, does not generate …
6797 … (0x1<<19) // Received target Abort Error Status Mask for Function15. If set, does not generate …
6802 … (0x1<<0) // Poisoned Error Status detected for Function 14. If set, hw generates pcie_…
6804 …0x1<<1) // Flow Control Protocol Error Status detected for Function 14. If set, hw generates pcie_…
6806 … (0x1<<2) // Completer Timeout Status detected for Function 14. If set, hw generates pcie_…
6808 … (0x1<<3) // Receive UR Status detectedfor Function 14. If set, hw generates pcie_…
6810 … (0x1<<4) // Unexpected Completion Status detected for Function 14. If set, hw generates pcie_…
6812 … (0x1<<5) // Receiver Overflow Status detected for Function 14. If set, hw generates pcie_…
6814 … (0x1<<6) // Malformed TLP Status detected for Function 14. If set, hw generates pcie_…
6816 … (0x1<<7) // ECRC Error TLP Status detected for Function 14. If set, hw generates pcie_…
6818 … (0x1<<8) // Unsupported Request Error Status detected for Function 14. If set, hw generates pcie_…
6822 … (0x1<<10) // Poisoned Error Status detected in function 15. If set, hw generates pcie_…
6824 …0x1<<11) // Flow Control Protocol Error Status detected in function 15. If set, hw generates pcie_…
6826 … (0x1<<12) // Completer Timeout Status detected in function 15. If set, hw generates pcie_…
6828 … (0x1<<13) // Receive UR Status detectedin function 15. If set, hw generates pcie_…
6830 … (0x1<<14) // Unexpected Completion Status detected in function 15. If set, hw geneartes pcie_…
6832 … (0x1<<15) // Receiver Overflow Status detected in function 15. If set, hw generates pcie_…
6834 … (0x1<<16) // Malformed TLP Status detected in function 15. If set, hw generates pcie_…
6836 … (0x1<<17) // ECRC Error TLP Status detected in function 15. If set, hw generates pcie_…
6838 … (0x1<<18) // Unsupported Request Error Status detected in function15. If set, hw generates pcie_…
6845 … with a data payload of 0xFFFFFFFF. When the MSB of a PF's HIDE_PFn is non-zero, the PF is consi…
6877 …hiding of implemented physical functions. To enable this feature, you must set the CX_HIDE_PF_EN h…
6911 … (0xf<<0) // Feedback mode. 0 = Direction of change. 1 = Figure of merit. 2-15 = Reserved.
6913 …ase 3 successful status bit is not set in the link status register. * Equalization phase 3 comple…
6925 … (0x1<<26) // Request core to send back-to-back EIEOS in Recove…
6927 …or Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP). M-PCIe doesn't have Con…
6928 … (0xf<<0) // Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserv…
6930 …- 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found then: …
6932 …Eval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settin…
6934 …- 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: P…
6936 …ter, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include…
6940 … core to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping …
6947 … (0xf<<10) // Convergence window aperture for C-1. Precursor coeffici…
6951 …qualization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feedback Mode i…
6954 …Allowed range: 0,1,2,..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0, EQ Master is …
6956 …TA_K2 (0xf<<10) // Convergence Window Aperture for C-1. Pre-cursor coefficient…
6958 …K2 (0xf<<14) // Convergence Window Aperture for C+1. Post-cursor coefficients m…
6961 …-Posted passing posted ordering rule control. Determines if a NP can pass halted P queue. 0x0 = …
6963 …lted P queue. 0x0 = CPL can not pass P (recommended). 0x1 = CPL can pass P. 0x2-0xFF = Reserved.
6966 …<0) // Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue…
6968 … Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1…
6971 … (0xffff<<0) // Loopback rxvalid (lane enable - 1 bit per lane).
6984 … (0x1<<31) // PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This reg…
6987 … (0x1<<0) // Write to RO registers using DBI. When you set this bit, then some…
6989 …IO or MEM request with UR/CA/CRS is sent to be the controller. 0x0 = The controller drops all inc…
6991 … (when [DEF_TARGET] is set). When set, the core suppresses error logging, error message generati…
6999 … 0x0008bcUL //Access:RW DataWidth:0x20 // DBI Read-Only Write Enable Reg…
7000 …u set this field to "1", then some RO and HwInit bits are writable from the local application thro…
7005 …set. If PCIEEP_RAS_EINJ_CTL6PE[LTSSM_VAR] is set and PCIEEP_LINK_CTL2[HASD] is zero, the core st…
7009 … 0x0008c0UL //Access:RW DataWidth:0x20 // UpConfigure Multi-lane Control Register…
7010 …- 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration s…
7012 …set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE b…
7014 …n Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This reg…
7017 …RxStandby/RxStandbyStatus handshake. 0x0 = Rx EIOS and subsequent T TX-IDLE-MIN. 0x1 = Rate …
7026 …- [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfig…
7028 …- 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Core wai…
7033 …This is a one-shot bit. Writing a one triggers the deletion of the target completion LUT entry tha…
7035 …lication completions (on XALI0/1/2) corresponding to previously received non-posted requests from …
7038 …mpletion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register fie…
7096 … (0xff<<24) // Non-Posted Data credits a…
7105 …BB (0xf<<28) // Non-Posted Data credits a…
7114 … (0xff<<24) // Non-Posted Data credits c…
7123 …BB (0xf<<28) // Non-Posted Data credits c…
7134 … (0x1<<16) // Available Non-posted credit for tar…
7137 …B (0xff<<0) // Non-Posted header credits…
7139 …B (0xff<<8) // Non-Posted data credits a…
7146 … (0xf<<0) // Target Non-Posted request State …
7175 …set enables the DUT to assume that VFs are residing on a bus number that is different than the one…
7177 … bit when set, prevents DUT from automatically setting VF offset to be greater than 256(when vf_ne…
7179 … (0x1<<2) // This bit when set, enables DUT to aut…
7182 …non-posted data credits since the last request for immediate update that are needed to force an im…
7184 … (0xff<<12) // The number of accumulated non-posted header credits…
7186 …set, released non-posted credits are flagged for immediate update. When clear, the credits may or …
7188 …the forced update if there are outstanding non-posted credits to update. The resolution on the tim…
7190 …set, outstanding non-posted credit updates are forwarded to the DLL as immediate updates after a g…
7197 …MMEDIATE_BB (0x1<<20) // When set, released posted cr…
7199 … update if there are outstanding posted credits to update. The resolution on the timer is +/- 1 us.
7201 …set, outstanding posted credit updates are forwarded to the DLL as immediate updates after a given…
7204 … (0xf<<0) // Each bit, when set, indicates that the…
7206 …B (0x3ff<<4) // Each bit, when set, indicates that the…
7208 …SK_BB (0x3<<14) // Each bit, when set, indicates that the…
7210 …_BB (0xf<<16) // Each bit, when set, indicates that the…
7212 …_BB (0xf<<20) // Each bit, when set, indicates that the…
7216 …SK_BB (0x1f<<26) // Each bit, when set, indicates that the…
7223 … (0x1<<16) // VDM is enabled when this bit is set. PCIe will pass VDM…
7226 … (0x1<<0) // This bit when set, forces hardware to…
7228 … (0x1<<1) // This field when set will prevent hardware from generating attention wh…
7232 … (0x1<<30) // This field when set inidcates that the PTM req-respon…
7234 …/ This field when set inidcates that the PTM req-response handshake completed successfully. This f…
7244 …cleared after the specified time if reg_ttx_tlp_stat_len is non-zero. All statistic read-back regi…
7248 …roseconds. When it is set to '0', software has to clear the reg_ttx_tlp_stat_en bit to stop the op…
7251 …he TLP type that hardware can detect. Bit[7] is enable bit. If this bit is set to 1, then hardware…
7253 …e TLP type that hardware can detect. Bit[15] is enable bit. If this bit is set to 1, then hardware…
7255 …e TLP type that hardware can detect. Bit[23] is enable bit. If this bit is set to 1, then hardware…
7257 …e TLP type that hardware can detect. Bit[31] is enable bit. If this bit is set to 1, then hardware…
7260 …t_tlp_type_0. Bits[7:0] are the mask bits. Default value is 0. If a bit is set to 1 then correspon…
7264 …_tlp_type_1. Bits[14:8] are the mask bits. Default value is 0. If a bit is set to 1 then correspon…
7268 …tlp_type_2. Bits[22:16] are the mask bits. Default value is 0. If a bit is set to 1 then correspon…
7272 …tlp_type_3. Bits[30:24] are the mask bits. Default value is 0. If a bit is set to 1 then correspon…
7277 …cleared after the specified time if reg_trx_tlp_stat_len is non-zero. All statistic read-back regi…
7281 …roseconds. When it is set to '0', software has to clear the reg_trx_tlp_stat_en bit to stop the op…
7284 …he TLP type that hardware can detect. Bit[7] is enable bit. If this bit is set to 1, then hardware…
7286 …e TLP type that hardware can detect. Bit[15] is enable bit. If this bit is set to 1, then hardware…
7288 …e TLP type that hardware can detect. Bit[23] is enable bit. If this bit is set to 1, then hardware…
7290 …e TLP type that hardware can detect. Bit[31] is enable bit. If this bit is set to 1, then hardware…
7293 …t_tlp_type_0. Bits[7:0] are the mask bits. Default value is 0. If a bit is set to 1 then correspon…
7297 …_tlp_type_1. Bits[14:8] are the mask bits. Default value is 0. If a bit is set to 1 then correspon…
7301 …tlp_type_2. Bits[22:16] are the mask bits. Default value is 0. If a bit is set to 1 then correspon…
7305 …tlp_type_3. Bits[30:24] are the mask bits. Default value is 0. If a bit is set to 1 then correspon…
7323 …<<0) // Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7325 …<10) // Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7327 …/ Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7329 …) // No Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7331 …) // No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7333 …o Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7336 … This value is used to provide a 1 us reference for counting time during low-power states with aux…
7339 …-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are…
7389 …RETRIG_CNT_BB (0xff<<0) // When non-zero, indicates the m…
7391 … When cleared, indicates that the DBG FIFO is read by user interface. When set, indicates that the…
7403 …buffer is filled, the trig_addr field is used to determine the amount of pre-trigger data collected
7407 … (0x1<<31) // When set by write, activates the DBG FIFO logic. To retrigger, this mu…
7412 … (0x1<<9) // When set, the indirect write address register is incremented on writes and…
7416 …RADDR_AUTOINC_BB (0x1<<19) // When set, the indirect read …
7418 …NO_RADDR_BB (0x1<<20) // When set, the indirect write…
7424 …- mask bits [319:0] for 0to1 trigger0 Register 10 :: IND_PCIE_DBG_TRIG0_1TO0_MASK - mask bits [319…
7438 …CTRL_ATTN_BB (0x1<<24) // When set, asserts attn signa…
7440 …SOFT_RST_25_BB (0x1<<25) // When set, resets user side i…
7442 …SOFT_RST_26_BB (0x1<<26) // When set, resets user side i…
7444 …SOFT_RST_27_BB (0x1<<27) // When set, resets user side i…
7446 …FIFO_CTL_28_BB (0x1<<28) // When set, clears the debug f…
7448 …FIFO_CTL_29_BB (0x1<<29) // When set, activates debug fi…
7450 …FIFO_CTL_30_BB (0x1<<30) // When set, resets notrig_cnt …
7452 …FIFO_CTL_31_BB (0x1<<31) // When set, dbg_fifo_triggered…
7455 …- no FIFO selected to read by user if 001 - PL/DL FIFO is selected to read by user if 010 - TLDA…
7459 … (0x7<<12) // 000 - generic lane is selected 001 - predefined lane 1 010 - predefine…
7479 …igger and status shown in this register. If both of the above two bits are set, the results are un…
7482 …_DWSEL_BB (0x1<<7) // When set, indicates that the…
7484 …OINC_BB (0x1<<8) // When set and in local mode, …
7486 …S_BB (0x1<<9) // When set, the FIFOs are link…
7488 …B (0x1<<10) // When set, the FIFOs are link…
7490 …set, all pretrigger data is considered valid and will be present on the interface. Note that there…
7494 …G_BB (0x1<<13) // When set after FIFO has trig…
7496 … (0x1<<14) // When set, indicates that the FIFO is operating in local…
7498 … (0x7f<<15) // The number of pre-trigger samples to ke…
7502 …G_FULL_BB (0x1<<29) // Set if pretrigger data …
7506 … (0x1<<31) // When set by write, activates the TLDA logic. To retrigger, this must…
7511 … (0x1<<8) // When set, the indirect write address register is incremented on writes and…
7515 …DR_AUTOINC_BB (0x1<<17) // When set, the indirect read …
7517 …RD_ADDR_BB (0x1<<18) // When set, the indirect write…
7523 …-- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 risi…
7525 … 0x000c50UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the FIFO
7526 … 0x000c54UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the FIFO
7527 … 0x000c58UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the FIFO
7528 … 0x000c5cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the FIFO
7532 …_DWSEL_BB (0x1<<7) // When set, indicates that the…
7534 …OINC_BB (0x1<<8) // When set and in local mode, …
7536 …S_BB (0x1<<9) // When set, this indicates the…
7538 …B (0x1<<10) // When set, this indicates the…
7540 …set, all pretrigger data is considered valid and will be present on the interface. Note that there…
7544 …G_BB (0x1<<13) // When set after FIFO has trig…
7546 … (0x1<<14) // When set, indicates that the FIFO is operating in local…
7548 … (0x7f<<15) // The number of pre-trigger samples to ke…
7552 …G_FULL_BB (0x1<<29) // Set if pretrigger data …
7556 … (0x1<<31) // When set by write, activates the TLDA logic. To retrigger, this must…
7561 … (0x1<<8) // When set, the indirect write address register is incremented on writes and…
7565 …DR_AUTOINC_BB (0x1<<17) // When set, the indirect read …
7567 …RD_ADDR_BB (0x1<<18) // When set, the indirect write…
7573 …-- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 risi…
7575 …000c70UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the second …
7576 …x000c74UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the second …
7577 …x000c78UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the second …
7578 …0x000c7cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the second …
7592 …F_BB (0x1<<6) // DL: If set, REPLAY EMPTY will …
7598 …edit Update. If this bit is set to '1', DL will not automatically generate UpdateFC every 30us (or…
7602 … (0x1<<13) // DL: Force L0 to L1. When this bit is set to '1', DL will sen…
7606 … (0x1<<23) // PHY: Force Receiver Detect All. When this bit is set to '1', internal Re…
7610 … (0x1<<27) // DL: Force L0 to L2. When this bit is set to '1', DL will sen…
7616 …(0x1<<31) // PHY: Direct Recovery to Configuration State. When this bit is set to '1', LTSSM is di…
7621 … (0x1<<7) // When this bit is set, the software value…
7625 … (0x1<<9) // When this bit is set, the software value will be used for UpdateFC Late…
7627 … (0x1<<10) // DL: When this bit is set to '1', Replay Time…
7633 … (0x1<<14) // This initiates Link re-training by directing…
7641 … (0x1<<30) // Internal ASPM L1 Enable. When this bit is set to '1', hardware au…
7643 …set to '1', user can directly control when to enter ASPM L1 using signal user_l1_enter. Actual L1 …
7646 …) // PHY: Select SKP OS interval. This field selects the interval for SKP ordered set transmitting.
7648 … (0x1<<2) // PHY: Disable SKP OS. When this bit is set to '1', periodic SK…
7650 …ER_BB (0x1<<3) // DL: If set, it will enable ACK…
7652 …_BB (0x1<<4) // If set, override hardwired…
7654 …R_SEL_BB (0x1<<5) // If set, override hardwired…
7664 …1<<17) // DL: Enable Non-Posted Latency Timer. If this timer reaches MAX_ACK_LAT_TIMER value, DL w…
7678 … (0xfff<<0) // DL: Non-Posted Data for INITFC
7687 … (0x1<<8) // This bit is set to '1' if IP is con…
7700 … (0xffff<<16) // Reserved - always write 0
7703 …symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calc…
7705 …he replay timeout in symbol time. This delay is only applied to the hardware-calculated replay tim…
7707 …_BB (0x7ff<<21) // Reserved - always write 0
7712 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7717 …symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calc…
7719 …he replay timeout in symbol time. This delay is only applied to the hardware-calculated replay tim…
7728 … DL: If set and DL has detected checksum error earlier, DL will nullify all subsequence memory wri…
7730 …set DL will nullify the first packet with bad checksum. Subsequent MWR packets will get nullified …
7734 …t from sending more Posted FC updates , potentially stall DMA requests, until the flag de-asserted.
7737 …symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calc…
7739 …he replay timeout in symbol time. This delay is only applied to the hardware-calculated replay tim…
7744 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7751 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7766 …1) // Enable GRC to control the driving of the debug bus. When this bit is set, it provides the ca…
7773 …_ERROR_BB (0x1<<2) // Set if DLP2TLP buffer d…
7775 …_PARITY_ERROR_BB (0x1<<3) // Set if Replay Address b…
7777 …_PARITY_ERROR_BB (0x1<<4) // Set if Replay Wrapper h…
7781 … (0x1<<6) // Indicate un-decoded condition in de-framing l…
7791 … (0x1<<11) // Set if DL detects impossible condition to de…
7793 …VERRUN_BB (0x1<<12) // Set if Replay buffer is…
7795 …OLL_OVER_BB (0x1<<13) // Set if number of Replay…
7797 …BB (0x1<<14) // Set if Replay Timer exp…
7799 … (0x1<<15) // DL TX Underrun. This bit is set to '1' if underrun …
7801 … (0x1<<16) // Detect DLLP with mismatched CRC-16 on receiving side.
7807 … (0x1<<19) // This signal is set to '1' when the TLP…
7809 …RITY_ERROR_BB (0x1<<20) // Set if TLP2DLP Buf has …
7812 …NS_BB (0x1fffff<<0) // If set mask out DL attenti…
7819 … (0x1<<10) // If set, indicates Replay b…
7823 … (0x1<<13) // If set, indicates link is …
7825 … (0x1<<14) // If set, signal DL finishes…
7827 … (0x1<<15) // If set, DL is doing VC0 FC…
7844 …set to '1' to enable the T2D FIFO threshold feature. Depending on TL, DL bus width and clock relat…
7853 … When bit replayfifo_testsize_sel is set to '1', this value is used as the Replay FIFO size. This …
7855 …Size. When bit d2tfifo_testsize_sel is set to '1', this value is used as the D2T FIFO size. This v…
7859 … (0x1<<30) // Replay FIFO Test Size Select. When this bit is set to '1', the value i…
7861 … (0x1<<31) // D2T FIFO Test Size Select. When this bit is set to '1', the value i…
7881 …8-bit header information that is sent to TL logic to build a TLP. The header information is passed…
7886 …P Count. Specify the number of TLP's to be transferred. When ate_tlp_go is set to '1', the value i…
7888 … (0x1<<8) // ATE TLP Nullify. When this bit is set to '1', an internal…
7897 … (0x1<<0) // ATE TLP Go bit. When this bit is set to '1', the TX User…
7911 … HW transmits number of TLPs equal to ATE_TLP_CNT (bits[7:0] of ate_tlp_cfg - offset 0x111c). trx_…
7915 …] of ate_tlp_cfg - offset 0x111c). This register value needs to be ignored until user writes '1' t…
7924 …T_BB (0x7<<18) // Offset into each set of 4 lanes
7935 …n the read has completed, this bit will read as '0'. If both bit 31 and 30 set at the same time th…
7937 … the write has completed, this bit will read as '0'. If both bit 31 and 30 set at the same time th…
7967 … (0x1<<0) // Request a width change (ie -make the link wider, …
7969 … (0x1<<1) // Request a speed change (ie -make the link fast or…
7975 … (0x1<<6) // For multi-lane links on a 2.0 c…
7993 …OL_BB (0x1<<16) // If set, all symbols of the…
7995 …RR_BB (0x1<<17) // If set, both error symbols…
7997 …Pattern in Polling.Compliance if the Enter Compliance bit of the Link Control 2 register is not set
8001 …ve. This also causes the Compliance Receive bit in the outgoing TS1s to be set in Polling.Active. …
8003 …r the Selectable Deemphasis bit set in TS1s in Polling.Active, Loopback, Recovery, and some Config…
8005 … of the local deemphasis set in the Detect state (this propagates to the PCIe Serdes via the TxDee…
8007 …/ The value for the Autonomous Change bit set in TS1s in the Configuration state when PhyLinkUp is…
8015 … (0x1<<27) // Disable use of electrical idle in Recovery.Speed - only use inferred el…
8019 … (0x1<<29) // Disable the ability to compensate for lane reversal in multi-lane links.
8023 … (0x1<<31) // Enable gen2 features when in 1.1 compliance mode (register 0x4d0, bit 5 is set)
8026 … (0x1<<0) // Force the PIPE interface to be 16-bit, even in Gen 1 So…
8030 … (0x1<<2) // Enable the PIPE-style powerdown of unused lanes in a multi-…
8032 … (0x1<<3) // Enable the auxilliary powerdown of unused lanes in a multi-lane link.
8034 … (0x1<<4) // Initiate PL changes required for a far-end loopback
8036 …DETECT_RST_BB (0x1<<5) // If set, when Detect is ent…
8038 …KEW_BUFS_BB (0x1<<6) // When set, clear the statis d…
8040 … (0x1f<<7) // Tuning field to set the delay in clocks…
8052 … (0x1<<18) // Declare an inferred electrical idel in L0 if no Skip Ordered Set (SOS) is received i…
8054 …s register. In that case, not receiving both an UpdateFC or a Skip Ordered Set within the 128 us i…
8068 … (0x1<<29) // Clear the LTSSM histogram. Not self-clearing
8070 … (0x1<<30) // Clear the Gen2 debug histogram. Not self-clearing
8072 … (0x1<<31) // Clear the recovery histogram. Not self-clearing
8081 …erved - only write 0. Spare flops for the PL - train_ctl_in[1:0]. [29] (PL_FIX_19) Enable Phase 3 …
8083 … (0x1<<30) // When set, the Serdes elastic buffers will be prevented from adjusting - generating …
8085 … (0x1<<31) // Reserved - only write 0. Spare flop for the PL - t…
8092 … (0x1<<14) // Enable the "pins" gloopback - assumes an external …
8121 … (0x1<<0) // For RC only. Select the value to use for the deemphasis set during Recovery fro…
8143 …set, disables the delay between the assertion of electrical idle to the power state change to P2. …
8149 … (0x1<<16) // Enable exit from Compliance on 1.1-compliant systems on …
8162 …-counter of 25 MHz clks for the minimum time to spend waiting for the reference clock buffers in t…
8168 …x1<<21) // When set, disables the control of the Serdes device type to minimize the PLL lock time …
8170 … (0x3<<22) // Selects the low-frequency clock used …
8172 …-counter of 25 MHz clks for the minimum time to spend waiting for the reference clock buffers in t…
8174 … (0x1<<30) // Reserved - only write 0
8176 …KREQ_BB (0x1<<31) // When set, disables entry to …
8181 …B (0x3<<6) // Reserved - only write 0
8185 … (0x3<<14) // Reserved - only write 0
8189 … (0x1<<17) // Use any PhyStatus to indicate the P0->P2 transition. De…
8195 … (0xfff<<20) // Reserved - only write 0
8198 … (0xf<<0) // b0000: select pseudo-random value between …
8204 …le data on the lane rom below b10 : corrupt the last symbol of the ordered set on the lane from be…
8206 …(0x3<<14) // b11 : Reserved b10 : DLLP error b01 : TLP error b00 : Ordered set error for TX or Ser…
8208 … (0x1<<16) // Inject transmit DLLP/TLP error or ordered set error.
8212 … (0x1fff<<18) // Reserved - always write 0
8214 …ult in the link being declared unusable since data alignment is lost. When set, the legacy behavio…
8217 …_BB (0x1<<0) // If set, either an elastic …
8219 …RR_BB (0x1<<1) // If set, a disparity error …
8221 …BB (0x1<<2) // If set, an 8b10b decode er…
8223 …W_BB (0x1<<3) // If set, the link needed to…
8225 …B (0x1<<4) // If set, the link needed to…
8233 …1_BB (0xf<<8) // Reserved - only write 0
8238 …IC_ERR_BB (0x1<<0) // If set, masks ELASTIC_ERR …
8240 …RITY_ERR_BB (0x1<<1) // If set, masks DISPARITY_ER…
8242 …E_ERR_BB (0x1<<2) // If set, masks DECODE_ERR f…
8244 …IS_SKEW_BB (0x1<<3) // If set, masks LINK_IS_SKEW…
8246 …_ERR_BB (0x1<<4) // If set, masks TRAIN_ERR fr…
8248 …AIN_ERROR_BB (0x1<<5) // If set, masks L0S_MAIN_ERR…
8250 …IN_REQ_BB (0x1<<6) // If set, masks RETRAIN_REQ …
8252 …R_STATUS_BB (0x1<<7) // If set, masks Clock Compen…
8254 …_1_BB (0xf<<8) // Reserved - only write 0
8269 … (0x1<<8) // *** Do not modify!! Enable 16-bit data for all rate…
8281 …) // Clear the block aligner debug information frozen on an aligner error. Set, then clear immedia…
8287 … (0x3<<17) // Reserved - only write 0
8312 … (0x1<<20) // Enable a bad/misplaced End-of-Data-Stream token as a…
8343 … (0x1<<5) // Software sets if it can disable data traffic during re-equalization.
8375 …ved TS1 if the EC field is set to 2'b10 or 2'b11 depending on whether Slave is an RC or EP respect…
8383 …B (0x1<<28) // Reserved - only write 0
8406 … (0x1<<11) // Enable Gen3 redo deskew on framing/post-deskew alignment issu…
8418 … (0x1<<17) // Select between requiring all EQ TS2s or any EQ TS2 to set start_eq_w_preset
8428 … (0x1<<22) // (PL_FIX_05) Enable preset-coefficient lookup fo…
8447 …C_BB (0x1<<6) // SED read address auto-increment
8468 …NTRY_5_TO_0_BB (0x3f<<0) // Pre-cursor for the coefficient set
8470 …TRY_11_TO_6_BB (0x3f<<6) // Main cursor for the coefficient set
8472 …RY_17_TO_12_BB (0x3f<<12) // Post-cursor for the coefficient set
8480 …y the EP to the Link partner-RC Transmitter in Phase2 EQ programmable preset value advertized by t…
8523 …eemphasis register control programming of coefficients for preset-0(-6dB) and preset-1(-3.5dB) in …
8525 …reset 0 and 1 0: points to the preset 0 coefficients(-6dB) 1: points to the preset 1 coefficients(…
8529 …0) // Gen2 deemphasis register select control bit to change from Preset-1(-3.5dB) to preset-0(-6dB)
8531 …/ Select control bit for the read status of the gen1/2 and gen2 lut entry 18-bit value poining to …
8576 … (0x1<<31) // RX reset EIEOS control bit for TS1(SYM6-Bit2) in Recovery.Equ…
8581 … (0x3f<<1) // Registered programmed 6-bit FULL SWING value …
8585 … (0x3f<<8) // Registered programmed 6-bit LOW FREQUENCY val…
8611 …<<26) // [DEBUG_BIT]: RC mode : Forces Gen3 equalization for every Speed change over from Gen1-Gen3
8613 … (0x1f<<27) // [DEBUG_BITS]: Equalization static debug 5-bit address control f…
8616 … (0x1<<0) // Enable Illegal Ordered Set After EDS Error. When this bit is set …
8618 … (0x1<<1) // Enable Ordered Set After SDS Error. When this bit is set …
8620 … (0x1<<2) // Enable Ordered Set with No EDS Error. When this bit is set…
8622 … (0x1<<3) // Enable Bad Framing CRC Error. When this bit is set to '1', report Gen3…
8624 … (0x1<<4) // Enable Bad Framing Parity Error. When this bit is set to '1', report Gen3…
8626 … (0x1<<5) // Enable Bad EDB Error. When this bit is set to '1', report Gen3…
8628 … (0x1<<6) // Enable Bad Framing Symbol Error. When this bit is set to '1', report Gen3…
8630 … (0x1<<7) // Enable Data After EDS Error. When this bit is set to '1', report Gen3…
8633 …'1' enables the master loopback operation. Normally, if lpbk_master_len is set to '0', software ha…
8635 … (0x1<<1) // Loopback Master Entry State. If this bit is set to '1', loopback is…
8637 … (0x1<<2) // Loopback Master Set Compliance Receive. If this bit is set to '1', the Compliance R…
8639 … (0x1<<3) // Loopback Master Automatically Set Compliance Receive. If this bit is set …
8641 …ce Setting. When loopback is entered from Recov.Idle state and this bit is set to '1', hardware ap…
8643 … (0x1<<5) // Loopback Master Skip Ordered Set. When this bit is set, SKP OS …
8645 … Set. PCIE Spec requires that in Gen3 loopback master inserts two SKIP ordered sets for each SKIP …
8653 …illiseconds. When it is set to '0', software has to clear the lpbk_master_ena bit to stop the oper…
8656 … Timeout. While in Loopback.Entry state, if Compliance Receive bit was not set in transmitting TS1…
8661 …Idle and bit lpbk_master_frc_setting is set to '1'. If data rate is Gen3, Loopback Master will aut…
8668 …CURSOR_BB (0x3f<<8) // Loopback Master TS1 Pre-Cursor Coefficient. T…
8672 …URSOR_BB (0x3f<<20) // Loopback Master TS1 Post-cursor Coefficient. T…
8674 … (0x1<<26) // Loopback Master TS1 Selectable De-emphasis. This value …
8676 …hanged to a new speed. 2. Entered from Recovery.Idle and bit lpbk_master_frc_setting is set to '1'.
8679 … used when loopback is in Gen2 rate. Notes that for Gen1 the TX deemphasis is always set to -3.5db.
8684 … (0x1<<1) // Software LTSSM Delay Start. When this bit is set together with sw_lt…
8686 …ware is in control, the new state will be applied to LTSSM. This bit is self-cleared, so reading a…
8688 … (0x1<<3) // LTSSM Timeout Disable. When this bit is set to '1', all LTSSM t…
8692 …-level State. This field specifies the state of the sub-level state machine that software wants LT…
8696 … (0x1ff<<20) // Software LTSSM Top-level State. This field specifies the state of th…
8700 … enable that is set to '1' only when S/W is actually in control of the LTSSM. If sw_ltssm_dlystart…
8703 …ally cleared after the specified time if pcie_statis_len is non-zero. All statistic read-back regi…
8707 …icroseconds. When it is set to '0', software has to clear the pcie_statis_ena bit to stop the oper…
8717 …cess:R DataWidth:0x20 // PCIE TX Ordered Set Statistic Low 32 bits. This is the number of ord…
8719 … (0xff<<0) // PCIE TX Ordered Set Statistic High 8 bits. This is the number of ord…
8729 …cess:R DataWidth:0x20 // PCIE RX Ordered Set Statistic Low 32 bits. This is the number of ord…
8731 … (0xff<<0) // PCIE RX Ordered Set Statistic High 8 bits. This is the number of ord…
8739 … (0x1<<1) // LTSSM Statistic Auto Increment. When this bit is set to '1', hardware au…
8773 …B (0x1<<7) // For lane 12: Set by the link partner…
8775 … (0x7f<<8) // For lane 13 in a multi-lane system: The numb…
8777 … (0x1<<15) // For lane 13 in a multi-lane system: Set by the link …
8781 … (0x1<<23) // For lane 14: Set by the link partner…
8783 … (0x7f<<24) // For lane 15 in a multi-lane system: The numb…
8785 … (0x1<<31) // For lane 15 in a multi-lane system: Set by the link …
8790 … (0x1<<7) // For lane 8: Set by the link partner…
8792 … (0x7f<<8) // For lane 9 in a multi-lane system: The numb…
8794 … (0x1<<15) // For lane 9 in a multi-lane system: Set by the link …
8798 … (0x1<<23) // For lane 10: Set by the link partner…
8800 … (0x7f<<24) // For lane 11 in a multi-lane system: The numb…
8802 … (0x1<<31) // For lane 11 in a multi-lane system: Set by the link …
8807 … (0x1<<7) // For lane 4: Set by the link partner…
8809 … (0x7f<<8) // For lane 5 in a multi-lane system: The numb…
8811 … (0x1<<15) // For lane 5 in a multi-lane system: Set by the link …
8815 … (0x1<<23) // For lane 6: Set by the link partner…
8817 … (0x7f<<24) // For lane 7 in a multi-lane system: The numb…
8819 … (0x1<<31) // For lane 7 in a multi-lane system: Set by the link …
8824 … (0x1<<7) // For lane 0: Set by the link partner…
8826 … (0x7f<<8) // For lane 1 in a multi-lane system: The numb…
8828 … (0x1<<15) // For lane 1 in a multi-lane system: Set by the link …
8832 … (0x1<<23) // For lane 2: Set by the link partner…
8834 … (0x7f<<24) // For lane 3 in a multi-lane system: The numb…
8836 … (0x1<<31) // For lane 3 in a multi-lane system: Set by the link …
8841 …K_12_BB (0x1<<7) // For lane 12: Set by the local receiv…
8843 … (0x7f<<8) // For lane 13 in a multi-lane system: The numb…
8845 … (0x1<<15) // For lane 13 in a multi-lane system: Set by the local…
8849 …_14_BB (0x1<<23) // For lane 14: Set by the local receiv…
8851 … (0x7f<<24) // For lane 15 in a multi-lane system: The numb…
8853 … (0x1<<31) // For lane 15 in a multi-lane system: Set by the local…
8858 …K_8_BB (0x1<<7) // For lane 8: Set by the local receiv…
8860 … (0x7f<<8) // For lane 9 in a multi-lane system: The numb…
8862 … (0x1<<15) // For lane 9 in a multi-lane system: Set by the local…
8866 …10_BB (0x1<<23) // For lane 10: Set by the local receiv…
8868 … (0x7f<<24) // For lane 11 in a multi-lane system: The numb…
8870 … (0x1<<31) // For lane 11 in a multi-lane system: Set by the local…
8875 …_4_BB (0x1<<7) // For lane 4: Set by the local receiv…
8877 … (0x7f<<8) // For lane 5 in a multi-lane system: The numb…
8879 … (0x1<<15) // For lane 5 in a multi-lane system: Set by the local…
8883 …6_BB (0x1<<23) // For lane 6: Set by the local receiv…
8885 … (0x7f<<24) // For lane 7 in a multi-lane system: The numb…
8887 … (0x1<<31) // For lane 7 in a multi-lane system: Set by the local…
8892 …_0_BB (0x1<<7) // For lane 0: Set by the local receiv…
8894 … (0x7f<<8) // For lane 1 in a multi-lane system: The numb…
8896 … (0x1<<15) // For lane 1 in a multi-lane system: Set by the local…
8900 …2_BB (0x1<<23) // For lane 2: Set by the local receiv…
8902 … (0x7f<<24) // For lane 3 in a multi-lane system: The numb…
8904 … (0x1<<31) // For lane 3 in a multi-lane system: Set by the local…
8939 … (0xff<<0) // Gen2 Debug History - current. Changes are…
8957 … (0xff<<0) // Recovery History - current. Changes are…
9015 …) // The current state of the ATE loopback SM tracker: b00011 : IDLE state - not active b00101 : …
9036 …REDSET_AFTER_SDS_BB (0x1<<6) // An ordered set occurred after an S…
9040 …REDSET_NO_EDS_BB (0x1<<8) // An ordered set occurred in the dat…
9042 …ETS_BB (0x1<<9) // Ordered set follows SKP ordered set after E…
9062 … (0x1<<19) // This bit is set to '1' when the ordered set follo…
9066 … 0x001d38UL //Access:R DataWidth:0x20 // PHY Debug - Polling Compliance s…
9067 … 0x001d3cUL //Access:R DataWidth:0x20 // PHY Debug - Equalization signals
9248 … (0x1<<0) // Instantaneous value of the top-level user_allow_gen3…
9253 … (0xffff<<0) // Vendor ID. For SR-IOV VFs always 0xFFFF.
9255 … (0xffff<<16) // Device ID. For SR-IOV VFs always 0xFFFF.
9258 …ENDOR_ID_K2 (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufact…
9263 …E_E5 (0x1<<0) // VF read-only zero.
9265 …E_E5 (0x1<<1) // VF read-only zero.
9267 …set, the request is discarded. A interrupt will be generated setting the SPEM()_PF()_DBG_INFO[P()_…
9281 … (0x1<<9) // Fast back-to-back transaction ena…
9283 …S_E5 (0x1<<10) // VF read-only zero.
9289 … (0x1<<19) // INTx status. Not applicable for SR-IOV. Hardwired to 0.
9295 … (0x1<<23) // Fast back-to-back capable. Not ap…
9312 …IO Access Response. You cannot write to this register if your configuration has no IO bars; that…
9314 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9352 …_ERR_K2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
9359 … (0xff<<8) // Read-only copy of the asso…
9361 … (0xff<<16) // Read-only copy of the asso…
9363 … (0xff<<24) // Read-only copy of the asso…
9375 … (0xff<<0) // Read-only copy of the asso…
9381 … (0x1<<23) // Read-only copy of the asso…
9400 …E_K2 (0x3<<1) // BAR0 32-bit or 64-bit.
9410 …E_K2 (0x3<<1) // BAR1 32-bit or 64-bit.
9420 …E_K2 (0x3<<1) // BAR2 32-bit or 64-bit.
9430 …E_K2 (0x3<<1) // BAR3 32-bit or 64-bit.
9440 …E_K2 (0x3<<1) // BAR4 32-bit or 64-bit.
9450 …E_K2 (0x3<<1) // BAR5 32-bit or 64-bit.
9459 … (0xffff<<0) // Read-only copy of the asso…
9461 … (0xffff<<16) // Read-only copy of the asso…
9464 …tem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9466 …tem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9469 … (0x1<<0) // Read-only copy of the asso…
9471 … (0x1fff<<19) // Read-only copy of the asso…
9480 … (0xff<<0) // VF's read-only zeros.
9482 … (0xff<<8) // VF's read-only zeros.
9484 … (0xff<<16) // VF's read-only zeros.
9486 … (0xff<<24) // VF's read-only zeros.
9496 … (0xff<<8) // Next capability pointer. Points to the MSI-X capabilities by def…
9498 …_E5 (0xf<<16) // Read-only copy of the asso…
9500 … (0xf<<20) // Read-only copy of the asso…
9502 … (0x1<<24) // Read-only copy of the asso…
9504 … (0x1f<<25) // Read-only copy of the asso…
9515 …emented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9522 … (0x7<<0) // Read-only copy of the asso…
9524 … (0x3<<3) // Read-only copy of the asso…
9526 … (0x1<<5) // Read-only copy of the asso…
9528 … (0x7<<6) // Read-only copy of the asso…
9530 … (0x7<<9) // Read-only copy of the asso…
9532 … (0x1<<15) // Read-only copy of the asso…
9538 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core.
9545 …eld Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9551 …_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2 (0x1<<15) // Role-based Error Reporting…
9584 …set if we receive any of the errors in PCIEEPVF()_COR_ERR_STAT, for example a replay-timer timeout…
9586 … control register. This field is set if we receive any of the errors in PCIEEPVF()_UCOR_ERR_MSK th…
9588 … control register. This field is set if we receive any of the errors in PCIEEPVF()_UCOR_ERR_MSK th…
9590 …ests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message shoul…
9592 …D_E5 (0x1<<20) // VF's read-only zeros.
9594 … (0x1<<21) // Transaction pending. Set to 1 when nonposted requests are not yet complete…
9599 …_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting…
9609 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9611 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9615 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
9623 …STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
9634 … (0xf<<0) // Read-only copy of the asso…
9636 … (0x3f<<4) // Read-only copy of the asso…
9638 …5 (0x3<<10) // Read-only copy of the asso…
9640 … (0x7<<12) // Read-only copy of the asso…
9642 … (0x7<<15) // Read-only copy of the asso…
9644 … (0x1<<18) // Read-only copy of the asso…
9646 … (0x1<<19) // Read-only copy of the asso…
9648 …5 (0x1<<20) // Read-only copy of the asso…
9650 … (0x1<<21) // Read-only copy of the asso…
9652 … (0x1<<22) // Read-only copy of the asso…
9654 … (0xff<<24) // Read-only copy of the asso…
9657 …D_K2 (0xf<<0) // Maximum Link Speed. In M-PCIe mode, the reset …
9659 …_K2 (0x3f<<4) // Maximum Link Width. In M-PCIe mode, the reset …
9663 …- CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1…
9665 …- CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1…
9667 …er Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9675 … ASPM Optionality Compliance. Note: The access attributes of this field are as follows: - Dbi: R
9704 … (0x3f<<20) // Negotiated link width. Set automatically by ha…
9721 …_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_EN…
9723 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
9729 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9733 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9735 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9743 …figuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
9745 …Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9749 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9751 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9762 …-bit AtomicOp supported. Note that inbound AtomicOps targeting BAR0 are not supported and are dro…
9764 …-bit AtomicOp supported. Note that inbound AtomicOps targeting BAR0 are not supported and are dro…
9766 …-bit AtomicOp supported. Note that inbound AtomicOps targeting BAR0 are not supported and are dro…
9768 … (0x1<<10) // No RO-enabled PR-PR passing. (Thi…
9776 …_CPL_SUPP_E5 (0x1<<16) // 10-bit tag completer sup…
9778 …_REQ_SUPP_E5 (0x1<<17) // 10-bit tag requestor sup…
9784 …5 (0x1<<21) // End-end TLP prefix suppor…
9786 … (0x3<<22) // Read-only copy of the asso…
9803 …O_EN_PR2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
9828 …_REQ_EN_E5 (0x1<<12) // 10-bit tag requestor ena…
9832 … (0x1<<15) // Unsupported end-end TLP prefix blocki…
9854 … (0x7f<<1) // Read-only copy of the asso…
9867 …DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9870 …TLS_E5 (0xf<<0) // VF's read-only zeros.
9872 …EC_E5 (0x1<<4) // VF's read-only zeros.
9874 …HASD_E5 (0x1<<5) // VF's read-only zeros.
9876 …SDE_E5 (0x1<<6) // VF's read-only zeros.
9878 …TM_E5 (0x7<<7) // VF's read-only zeros.
9880 …MC_E5 (0x1<<10) // VF's read-only zeros.
9882 …SOS_E5 (0x1<<11) // VF's read-only zeros.
9884 …DE_E5 (0xf<<12) // VF's read-only zeros.
9886 … (0x1<<16) // Read-only copy of the asso…
9909 …ET_LINK_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the conten…
9913 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9915 …SEL_DEEMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
9919 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9921 … transmission. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9923 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
9925 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
9942 …NTRL_MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
9946 …7ff<<16) // MSI-X table size encoded as (table size - 1). This field is writable through PEM()_C…
9948 …ctors associated with the function are masked, regardless of their respective per-vector mask bits.
9950 …X_CAP_CNTRL_MSIXEN_E5 (0x1<<31) // MSI-X enable.
9952 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
9953 …NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
9955 …TRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2 (0xff<<8) // MSI-X Next Capability Poi…
9957 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
9959 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
9961 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
9964 …BIR_E5 (0x7<<0) // Read-only copy of the asso…
9966 … (0x1fffffff<<3) // Read-only copy of the asso…
9968 … 0x0000b4UL //Access:R DataWidth:0x20 // MSI-X Table Offset and BI…
9969 …_PCI_MSIX_BIR_K2 (0x7<<0) // MSI-X Table Bar Indicator…
9971 …_PCI_MSIX_TABLE_OFFSET_K2 (0x1fffffff<<3) // MSI-X Table Offset.
9974 …R_E5 (0x7<<0) // Read-only copy of the asso…
9976 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
9978 … 0x0000b8UL //Access:R DataWidth:0x20 // MSI-X PBA Offset and BIR …
9979 …OFFSET_REG_PCI_MSIX_PBA_K2 (0x7<<0) // MSI-X PBA BIR.
9981 …_PCI_MSIX_PBA_OFFSET_K2 (0x1fffffff<<3) // MSI-X PBA Offset.
9991 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9993 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9995 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10031 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10033 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10035 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10073 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
10083 … 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
10085 … 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
10132 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10134 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10138 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10140 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10154 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10156 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10160 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10162 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10170 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if RO…
10172 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if RO…
10174 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10175 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10177 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10180 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10182 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10185 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10187 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10190 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10192 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10195 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10197 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10200 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10202 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10205 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10207 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10210 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10212 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10219 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
10230 … (0x1<<0) // This bit masks, when set, the Parity bit: SE…
10232 … (0x1<<1) // This bit masks, when set, the Parity bit: SE…
10234 … (0x1<<2) // This bit masks, when set, the Parity bit: SE…
10236 … (0x1<<3) // This bit masks, when set, the Parity bit: SE…
10238 … (0x1<<4) // This bit masks, when set, the Parity bit: SE…
10240 … (0x1<<5) // This bit masks, when set, the Parity bit: SE…
10242 … (0x1<<6) // This bit masks, when set, the Parity bit: SE…
10244 … (0x1<<7) // This bit masks, when set, the Parity bit: SE…
10246 … (0x1<<0) // This bit masks, when set, the Parity bit: SE…
10248 … (0x1<<1) // This bit masks, when set, the Parity bit: SE…
10250 … (0x1<<2) // This bit masks, when set, the Parity bit: SE…
10252 … (0x1<<3) // This bit masks, when set, the Parity bit: SE…
10254 … (0x1<<4) // This bit masks, when set, the Parity bit: SE…
10256 … (0x1<<5) // This bit masks, when set, the Parity bit: SE…
10258 … (0x1<<6) // This bit masks, when set, the Parity bit: SE…
10290 …-only access of the GPRE registers. Register can be accessed only when storm is stalled. Address b…
10292 … 0x000480UL //Access:R DataWidth:0x20 // 15-0 STORM0 GPRE0 bits 15:0. 31-16 STOR…
10293 …- misc_local_mux_other_stall, 20 - ram_mux_bkpt_stall, 19 - mux_lock_stall, 18 - pram_mux_pipe_st…
10298 …ether or not the Storm is currently stalled. bit0- STORM A. bit1- STORM B. bit2- Pram Breakpoint. …
10303 …R DataWidth:0xf // This register delivers the PRAM address for the low-word instruction that…
10304 … DataWidth:0xf // This register delivers the PRAM address for the high-word instruction that…
10307 …en as a single bit , a value of 2 means that the PortID will be taken as a 2-bit field. A value of…
10308 … of the CID in which to assign to bit-0 of the port ID. I.e. if port_id_wdth is set to 0x1 and por…
10309 … DataWidth:0x1 // Defines the Storm register file set that is currently active. 0 - STORM A 1 …
10310 …- DRA WR STM Core_A, 3:5 - DRA WR STM Core_B, 6:8 - DRA RD STM Core_A, 9:11 - DRA RD STM Core_B, …
10313 …set bit in the data field will result in a corresponding bit inversion in the written data while E…
10315 …th:0x20 // This register delivers the Storm PC for read-only debug access. 15-0 - STORM A. 31-16…
10316 …e access type defined in data_breakpoint_access_set), the STORMs bits 15:0 - IRAM stall start add…
10317 …efined in data_breakpoint_access_set), the STORMs will be stalled. bit15:0 - IRAM stall end addre…
10318 …- stall on read access. bit1 - stall on write access. bit3:2 - stall on write BE (bit2 -to IRAM'…
10319 …er defines the IRAM address for which the data breakpoint stall was set. bits 0:15 - IRAM address.
10323 … indirect registers defines the modulus (roll-over) values for the corresponding real time clocks.…
10326 …-time clock with regard to the associated RTClkTickValue. The Storm decode assignments used for th…
10329 …-time clocks. This value is assigned to the corresponding real-time clock only when the Storm corr…
10332 …-time clock with the value provided by the associated RTClkInitValue register. The Storm decode as…
10335 …direct registers provides read access to the real time clock values. The sub-address for this indi…
10337 … per RTC used to enable each of the ten real-time clocks. The bit index corresponds with the ID of…
10347 …or the most recent RBC read request issued. The valid bit is returned on bit-0 of the data. All ot…
10352 … (0x1<<1) // When set, this bit enables h…
10354 …N (0x1<<2) // When set, this bit enables m…
10356 …aWidth:0x1 // This register is set after the CAM initialization is started (by writing to cam_i…
10357 …0x20 // This array of registers returns the 128-bit CAM match vector returned in the most recent…
10360 …-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fas…
10361 …ources for modes 2 and 3 on the fast debug channel: b0-DRA write disable; b1-DRA read disable; b2-…
10362 …able any of the following debug sources for mode-4 on the fast debug channel: b0-store data disabl…
10363 …ces for mode-6 on the fast debug channel: b0-dra_in disable; b1-fin disable; b2-load disable; b3-t…
10364 …0 // Connection id that should compared with cid field of the data (in Dra-In message); Note: ap…
10365 …aWidth:0x8 // Event id that should compared with event id field of the data (in Dra-In message).
10366 …075cUL //Access:RW DataWidth:0x8 // Mask for event id. 1- specified bit is ignored; 0 - speci…
10367 …e event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active stat…
10368 …e event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active stat…
10370 …- Filter off; in that case all data should be transmitted to the DBG block without any filtering i…
10372 …- use the recorded connection id field which arrives from the DBG block (dbg_sem_cid interface) fo…
10374 … (0x1<<3) // Used to enable CID/TID filter for recording handlers, when set.
10376 … (0x1<<4) // Used to enable Event ID filter for recording handlers, when set.
10378 … (0x3<<5) // Used to define the DRA-In source that should…
10380 … (0x1<<7) // Used to enable DRA source filter for recording handlers, when set.
10382 …iltering based on a range of event IDs rather than "match" filtering. When set, the event ID range…
10384 … (0x1<<9) // Used to enable the debug store address filter for fast debug, when set.
10386 …es that transmit store transactions. For all the bits of the mask that are set, then only if the c…
10387 …nsmit store transactions. For all the bits of dbg_store_addr_mask that are set, then only if the c…
10388 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
10398 … (0x1<<0) // Used to enable CID/TID filter for Storm active statistics counter, when set.
10400 … (0x1<<1) // Used to enable Event ID filter for Storm active statistics counter, when set.
10402 … (0x3<<2) // Used to define the DRA-In source that should…
10404 … (0x1<<4) // Used to enable DRA source filter for Storm active statistics counter, when set.
10406 …iltering based on a range of event IDs rather than "match" filtering. When set, the event ID range…
10408 … 0x000a44UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10409 … 0x000a44UL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10411 … 0x000a4cUL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10412 … 0x000a4cUL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10413 … 0x000a50UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10414 …- The accumulated number of Storm cycles in which the Storm has been idle due to having no threads…
10415 … 0x000a54UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10416 … 0x000a54UL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10417 … 0x000a58UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10418 … 0x000a5cUL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10419 … 0x000a60UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10420 … 0x000a64UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10425 …- response is ready. It is set when response cycle of 32 bit is ready from VFC block. It is reset …
10426 …L //Access:RW DataWidth:0x1 // Used to enable/disable BIST mode. When set, BIST testing will …
10429 … 0x000c4cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
10437 …-address. Bits [3:0] of the data bus provide the OpCode for the request where the following numera…
10439 … 0x00a000UL //Access:RW DataWidth:0x20 // Provides a memory-mapped region for VFC…
10445 …//Access:RW DataWidth:0x20 // Provides a RD access for all monitor block, {CNT_VAL,CNT_ID,SET}.
10458 … bit per ALU vector: 0-4 long vectors; 5-11 short vectors. When it is set then appropriate vector …
10459 …DSt vector for analyze operation. If it is set to 1, then row from target table will be rwitten. I…
10461 …asserted when there is attempt to write to read only register. It will be de-asserted aftre write …
10471 …ycle not equal 64 bit or number of data cycles bigger than 6. It will be de-asserted aftre write …
10473 …asserted when waitp is asserted and output FIFO is also full. It will be de-asserted aftre write …
10475 …asserted when it was address overflow of INFO part of RSS RAM. It will be de-asserted aftre write …
10477 …ted when it was address overflow of KEY LSB part of RSS RAM. It will be de-asserted aftre write …
10479 …erted when it was address overflow of KEY MSB part of RSS RAM. It will be de-asserted aftre write …
10482 …ty interrupt. It may be asserted when it was CAM parity error. It will be de-asserted aftre write …
10484 …pt. It may be asserted when it was parity error inside TT RAM. It will be de-asserted aftre write …
10486 …terrupt. It may be asserted when it was RSS RAM parity error. It will be de-asserted aftre write …
10540 …:RW DataWidth:0x1 // REQUIRED -If this bit is set then background mechanism for parity check …
10542 … 0x000048UL //Access:RW DataWidth:0x3 // REQUIRED - 0 - parity is enabled;…
10543 … 0x00004cUL //Access:RW DataWidth:0xa // REQUIRED - 0 - interrupt is enabled;1- interr…
10553 … 0x000074UL //Access:RW DataWidth:0x1 // When set then it disables se…
10556 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
10557 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
10573 … (0x3<<18) // This field is set to 0.
10602 …8UL //Access:RW DataWidth:0x1 // If this bit set to 0 then allows to work with 160 clients. I…
10607 … (0x1<<0) // This bit masks, when set, the Parity bit: VF…
10609 … (0x1<<1) // This bit masks, when set, the Parity bit: VF…
10611 … (0x1<<2) // This bit masks, when set, the Parity bit: VF…
10613 … (0x1<<5) // This bit masks, when set, the Parity bit: VF…
10615 … (0x1<<3) // This bit masks, when set, the Parity bit: VF…
10617 … (0x1<<4) // This bit masks, when set, the Parity bit: VF…
10619 … (0x1<<0) // This bit masks, when set, the Parity bit: VF…
10621 … (0x1<<1) // This bit masks, when set, the Parity bit: VF…
10623 … (0x1<<2) // This bit masks, when set, the Parity bit: VF…
10625 … (0x1<<3) // This bit masks, when set, the Parity bit: VF…
10627 … (0x1<<4) // This bit masks, when set, the Parity bit: VF…
10629 … (0x1<<2) // This bit masks, when set, the Parity bit: VF…
10641 …_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
10643 …_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for mem…
10645 …_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
10647 …_I_ECC_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
10679 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
10681 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
10683 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
10685 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
10687 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
10689 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
10691 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
10693 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
10695 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
10736 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
10757 …ived on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
10795 … 0x002000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
10800 …_E5 (0xff<<0) // 8-bit value from packag…
10802 …E5 (0xff<<8) // 8-bit value from packag…
10808 …(0x1<<0) // MAC Transmit Path Enable. Should be set to '1' to enable the MAC transmit path, should…
10810 … (0x1<<1) // MAC Receive Path Enable. Should be set to '1' to enable the MAC receive path, should …
10816 … Enable MAC Promiscuous Operation. If set to '1', all frames are received without any MAC address …
10820 …set to '1', the CRC field of received frames is forwarded with the frame to the user application. …
10822 … // Terminate / Forward Pause Frames. If set to '1', pause frames are forwarded to the user applic…
10824 …) // Ignore received Pause frame quanta. If set to '1', received pause frames are ignored by the M…
10826 …Set Source MAC Address on Transmit. If set to '1', the MAC overwrites the source MAC address recei…
10828 …Y Interface loopback. If set to '1', the signal loop_ena is set to '1'. If set to '0' (Reset value…
10832 …5 (0x1<<12) // Self-Clearing Software Res…
10834 …<13) // Enable Reception of all Control Frames. If set to '1', all control frames are accepted. If…
10840 … (0x1<<16) // Force Idle Generation. If set to '1', the MAC per…
10846 …e enable. If set to 1, the Core generates and processes PFC control frames according to the Priori…
10860 …_K2_E5 (0x1<<26) // Self-Clearing TX FIFO rese…
10862 …set to '0' (default), the MAC automatically inserts remote faults and idles in egress direction on…
10879 …mit statistics use if it should be different from receive statistics. When set to 0 the FRM_LENGTH…
10907 … (0x1<<0) // MDIO busy. If set, a MDIO transaction…
10909 … (0x1<<1) // MDIO read error. If set, the last read tran…
10913 … (0x1<<5) // MDIO transaction preamble disable. Shortens transaction but is non-standard.
10924 … (0x1<<14) // If written with 1, a read with address post-increment will be performed. Post-incr…
10929 …-bit data word. When written- Initiates a write transaction to the PHY. The MDIO_COMMAND register …
10931 …om or write to. After writing this register, an address-write transaction will be initiated to set…
10935 … (0x1<<0) // Local Fault Status. Set to '1' when the MAC…
10937 … (0x1<<1) // Remote Fault Status. Set to '1' when the MAC…
10939 … (0x1<<2) // PHY indicates loss-of-signal. Represents v…
10954 … octets in steps of 4 (XGMII) or 8 (XLGMII). Minimum 8. Value 12 should be set for compliant opera…
10956 …r PCS inserted markers. Depending on PCS type a value of 16383 (40G) or 20479 (25/50G) must be set.
10959 …E5 (0x1<<0) // Credit-based FIFO only: When…
10962 …5 (0xff<<0) // Credit-based FIFO only: Spec…
10970 …C quanta value for that class when a class XOFF is triggered. Each Quanta specifies a 512 bit-time.
11012 … (0x1<<0) // Enable XGMII-64 (4byte alignment)
11016 … (0x1<<5) // Enable 1-step capable datapath…
11019 … (0x1<<0) // Configure saturation behavior. When set to 1, the counters saturate at all-1.…
11021 …-on-read behavior. When set to 1, the counters are cleared (set to STATN_CLEARVALUE) after having …
11023 …<<2) // Clear all counters command (self-clearing). When written with 1 all counters (tx and rx) a…
11123 … 0x000380UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11125 … 0x000388UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11127 … 0x000390UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11129 … 0x000398UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11131 … 0x0003a0UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11133 … 0x0003a8UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11135 … 0x0003b0UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11137 … 0x0003b8UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11139 … 0x0003c0UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11141 … 0x0003c8UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11143 … 0x0003d0UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11145 … 0x0003d8UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11147 … 0x0003e0UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11149 … 0x0003e8UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11151 … 0x0003f0UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11153 … 0x0003f8UL //Access:R DataWidth:0x20 // Set of 8 objects record…
11167 …_K2_E5 (0xf<<8) // RS-FEC receive lane lock…
11169 … (0x1<<14) // Indicates, when 1 that the RS-FEC receiver has lock…
11173 …x20 // Counts number of corrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11174 …umber of corrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11176 …h:0x20 // Counts number of corrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11177 … (0xffff<<0) // Counts number of corrected FEC codewords upper 16-bits; None roll-over; Clears …
11179 …0 // Counts number of uncorrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11180 …ber of uncorrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11182 …0x20 // Counts number of uncorrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11183 … (0xffff<<0) // Counts number of uncorrected FEC codewords upper 16-bits; None roll-over; Clears …
11194 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 0; None roll-over whe…
11195 … (corrected) 10-bit symbol errors found in lane 0 for correctable codewords only; Lower 16-bit of …
11197 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11198 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 0; Clears o…
11200 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 1; None roll-over whe…
11201 … (corrected) 10-bit symbol errors found in lane 1 for correctable codewords only; Lower 16-bit of …
11203 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11204 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 1; Clears o…
11206 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 2; None roll-over whe…
11207 … (corrected) 10-bit symbol errors found in lane 2 for correctable codewords only; Lower 16-bit of …
11209 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11210 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 2; Clears o…
11212 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 3; None roll-over whe…
11213 … (corrected) 10-bit symbol errors found in lane 3 for correctable codewords only; Lower 16-bit of …
11215 … DataWidth:0x20 // Upper 16 bit of counter (with above register); Clears on read; None roll-over.
11216 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 3; Clears o…
11218 … 0x000200UL //Access:RW DataWidth:0x20 // Additional control to enable RS-FEC operation.
11240 …_EMPTY_K2_E5 (0xf<<12) // Real-time indication from …
11248 …W DataWidth:0x20 // Bits 7:0; Must be written with the 8-bit value of 0x57 to enable RS-FEC tr…
11249 … (0xff<<0) // Bits 7:0; Must be written with 8-bit value 0x57 to enable RS-FEC tra…
11251 … 0x000214UL //Access:RW DataWidth:0x20 // Bits 15:0. One bit per 10-bit Symbol; Each bit …
11252 … (0xffff<<0) // Bits 15:0. One bit per 10-bit Symbol; When a bi…
11254 … 0x000218UL //Access:RW DataWidth:0x20 // Bits 9:0; A 10-bit value which XORed…
11255 …N_TEST_PATTERN_K2_E5 (0x3ff<<0) // A 10-bit value which will …
11257 …E_K2_E5 (0x1<<10) // If the bit is set the 10B symbol is r…
11265 … (0x1<<8) // Indicate full-duplex operation; alw…
11269 … (0x1<<10) // Set PCS isolate mode; C…
11279 … (0x1<<15) // PCS soft-reset command; self-clearing
11284 … (0x1<<2) // Indicate link status; latch-low
11296 …x20 // Local Device Abilities for Autonegotiation. Contents differs for 1000Base-X or SGMII mode.
11297 … (0x1f<<0) // reserved; SGMII:=set to 1 to indicate SG…
11299 … (0x1<<5) // Indicate full-duplex support; SGMII…
11301 … (0x1<<6) // Indicate half-duplex support; SGMII…
11317 …/ Received Abilities during Autonegotiation. Contents differ depending on 1000Base-X or SGMII mode.
11320 … (0x1<<5) // Indicate full-duplex support; SGMII…
11322 … (0x1<<6) // Indicate half-duplex support; SGMII…
11341 … (0x1<<1) // Autoneg page received indication; latch-high
11388 … (0x1<<1) // Use the SGMII autonegotiation results to set SGMII speed
11390 …_E5 (0x3<<2) // Set SGMII speed when no…
11392 … (0x1<<4) // Set SGMII half-duplex mode wh…
11413 …ABILITY_K2_E5 (0x1<<1) // Set to 1 to indicate th…
11436 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
11468 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11470 … (0x1<<1) // When 1, this PCS is 10GBase-X capable.
11472 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11474 … (0x1<<3) // When 1, this PCS is 10GBase-T capable.
11476 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11478 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11495 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11497 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11499 … (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
11502 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11512 … (0xff<<0) // Errored blocks counter; None roll-over.
11514 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11520 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11521 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11523 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11524 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11526 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11527 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11529 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11530 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11532 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11533 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11535 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11536 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11538 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11539 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11541 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11542 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11549 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11551 …ESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enable.
11553 … (0x1<<7) // Select Random Idle test pattern (40G); Overrides bits 1:0 when set.
11555 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11556 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11558 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11559 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11561 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11562 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11586 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11587 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11589 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11590 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11592 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11593 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11595 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11596 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11616 … DataWidth:0x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance …
11617 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dis…
11620 …_THRESHOLD_K2_E5 (0xf<<0) // A 4-bit value to define t…
11622 …0010UL //Access:RW DataWidth:0x20 // Vendor Specific Reg; Define Reduced-XLAUI PMA mode using …
11623 …_K2_E5 (0x1<<0) // Enable Reduced-XLAUI PMA mode using …
11627 …IG_TX_MAP_LANE0_K2_E5 (0xf<<4) // Set VL (0..3) to transm…
11629 …IG_TX_MAP_LANE1_K2_E5 (0xf<<8) // Set VL (0..3) to transm…
11668 …2_E5 (0x1<<1) // When 0 PCS 4-lane MLD function is …
11688 …ABILITY_K2_E5 (0x1<<1) // Set to 1 to indicate th…
11711 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
11743 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11745 … (0x1<<1) // When 1, this PCS is 10GBase-X capable.
11747 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11749 … (0x1<<3) // When 1, this PCS is 10GBase-T capable.
11751 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11753 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11770 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11772 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11774 … (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
11777 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11787 … (0xff<<0) // Errored blocks counter; None roll-over.
11789 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11795 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11796 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11798 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11799 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11801 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11802 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11804 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11805 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11807 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11808 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11810 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11811 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11813 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11814 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11816 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11817 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11824 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11826 …ESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enable.
11828 … (0x1<<7) // Select Random Idle test pattern (40G); Overrides bits 1:0 when set.
11830 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11831 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11833 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11834 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11836 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11837 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11853 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11854 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11856 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11857 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11859 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11860 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11862 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11863 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11871 … DataWidth:0x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance …
11872 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dis…
11875 …_THRESHOLD_K2_E5 (0xf<<0) // A 4-bit value to define t…
11912 …2_E5 (0x1<<1) // When 0 PCS 4-lane MLD function is …
11962 …- off high-impedance 0x1 - CMU 0 0x3 - Lane 0 0x4 - Lane 1 0x5 - Lane 2 0x6 - Lane 3 0x15 - SoC ci…
12362 … (0x1<<0) // PHY error status. 0x0 - no error 0x1 - PHY has an in…
12364 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12365 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12383 … 0x000680UL //Access:RW DataWidth:0x8 // lower 8-bits of the 16-bit digital te…
12384 … 0x000684UL //Access:RW DataWidth:0x8 // higher 8-bits of the 16-bit digital te…
12393 … (0x1<<0) // Set if running a 1b simulation. Firmware may check this field to discover …
12400 …ster writes to the command register. Upon a write to this register, CMD_FLAG is set automatically.
12402 …<<0) // Indicates the presence of a new command to the PHY firmware. It is set automatically when …
12412 …ter writes to the Response register. Upon a write to this register, RSP_FLAG is set automatically.
12414 …<0) // Indicates the presence of a new Response to the PHY firmware. It is set automatically when …
14398 …used in gearbox applications. 0x0 - DIV4 0x1 - DIV8 0x2 - DIV16 0x3 - DIV20 0x4 - DIV32 0x5 - DIV…
14429 …to the half-rate TX clock path to provide visibility at the TX driver output. 0x0 - mission mode …
14431 …CMU macro to all lanes macros. 0x0 - DIV1 0x1 - DIV2 0x2 - DIV4 0x3 - DIV5 0x4 - DIV8 0x5 - DIV10…
14473 … (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indica…
14477 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14478 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14480 … (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro…
14515 … (0x1<<0) // CMU PLL regulator vddha setting. 0x0 - vddha is 1.5V nominal 0x1 - vddha …
14670 … (0x1<<0) // CMU PLL lock detector status. 0x0 - CMU PLL is not locked 0x1 - CMU PL…
14910 … (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indica…
14914 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14915 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14917 … (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro…
14950 … (0x1<<0) // Select the reference clock. 0 - clk_ref 1- clk_pllref
15204 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
15206 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
15208 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
15210 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
15286 …must also be set. 0 : TX data from customer logics 1: RX data for Far-End-Digital FED loopback 2: …
15290 …<5) // Controls tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be …
15293 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
15336 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
15418 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15419 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15421 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
15488 … 0x0062fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
15490 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
15497 …t, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_…
15500 …means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
15655 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
15673 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
15677 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
15696 … 0x006650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
15697 … 0x006654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
15701 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
15704 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
15720 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
15722 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
15724 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
15726 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
15728 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
15730 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
15732 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
15734 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
15737 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
15739 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
15741 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
15743 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
15746 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
15753 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
15755 …x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
15758 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15760 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
15762 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15764 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
15766 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15768 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15770 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15772 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15825 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
15828 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
15846 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
15848 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
15850 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
15852 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
15854 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
15856 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
15858 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
15860 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
15863 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
15865 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
15867 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
15869 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
15872 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
15879 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
15881 …k partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
15884 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15886 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
15888 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15890 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
15892 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15894 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15896 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15898 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15949 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
15951 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
15953 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
15955 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
15957 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
15959 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
15961 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
15963 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
15966 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
15968 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
15970 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
15972 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
15974 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
15976 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
15978 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
15981 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
15994 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
15996 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
15998 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
16000 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
16002 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
16004 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
16006 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
16008 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
16011 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
16013 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
16015 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
16017 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
16019 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
16021 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
16621 … (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until…
16624 …ATUS0_ACK_K2_E5 (0x1<<0) // Set to 1 by firmware wh…
16627 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
16633 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
16742 …execution. It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
16744 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
16748 …L0_DRIVE_BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when changi…
16768 … (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a comman…
16777 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
16779 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
16781 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
16783 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
16785 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16787 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16789 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16791 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16794 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
16796 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16799 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
16801 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16804 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
16806 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16809 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
16811 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16834 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
16836 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16839 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
16841 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16844 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
16846 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16849 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
16851 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
17203 …2_E5 (0x1<<0) // Enables the run-length detection digi…
17205 … 0x007410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
17207 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
17209 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
17380 … 0x00781cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17381 … 0x007820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17387 …Access:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp…
17416 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
17439 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17440 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17441 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17442 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17444 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
17446 …Access:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp…
17571 … (0x3<<0) // How many times to repeat CTLE adaptation sequence for initial adaptation set 0
17573 … (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
17590 …set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alo…
17592 …set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alo…
17599 … (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
17601 … (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
17603 … (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
17605 … (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
17616 … (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0…
17618 … (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0…
17628 … (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
17630 … (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
17665 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
17772 …/ Output corresponding to link training signal detect variable. Should be set when link training …
17776 …coded as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width Should be set to 500ns for 802.3 …
17778 …been trained and are ready. This is an 802.3 defined variable. Should be set between 100 and 300…
17794 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
17796 …x_ready variable. After this is asserted the corresponding frame status report field should be set.
17801 …/Access:RW DataWidth:0x8 // Initial PRBS LFSR seed. This needs to be set according to the re…
17806 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
17810 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
17817 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
17821 …E5 (0x3<<4) // Status report field for pre-cursor tap.
17823 …<6) // Status report field to indicate local receiver is ready. Should be set based on LTSM outpu…
17838 … (0x1<<1) // This is the 802.3 defined training variable. It should be set according to corres…
17864 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
17868 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
17875 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
17879 … (0x3<<4) // Received status report field for pre-cursor tap.
17886 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
17888 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
17890 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
17892 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
17968 …must also be set. 0 : TX data from customer logics 1: RX data for Far-End-Digital FED loopback 2: …
17972 …<5) // Controls tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be …
17975 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
18018 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
18100 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18101 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18103 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
18170 … 0x0082fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
18172 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
18179 …t, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_…
18182 …means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
18337 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
18355 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
18359 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
18378 … 0x008650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
18379 … 0x008654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
18383 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
18386 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
18402 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
18404 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
18406 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
18408 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
18410 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
18412 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
18414 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
18416 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
18419 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
18421 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
18423 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
18425 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
18428 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
18435 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
18437 …x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
18440 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18442 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
18444 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18446 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
18448 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18450 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18452 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18454 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
18507 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
18510 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
18528 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
18530 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
18532 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
18534 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
18536 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
18538 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
18540 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
18542 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
18545 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
18547 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
18549 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
18551 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
18554 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
18561 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
18563 …k partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
18566 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18568 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
18570 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18572 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
18574 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18576 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18578 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18580 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
18631 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
18633 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
18635 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
18637 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
18639 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
18641 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
18643 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
18645 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
18648 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
18650 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
18652 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
18654 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
18656 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
18658 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
18660 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
18663 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
18676 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
18678 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
18680 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
18682 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
18684 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
18686 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
18688 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
18690 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
18693 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
18695 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
18697 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
18699 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
18701 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
18703 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
19303 … (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until…
19306 …ATUS0_ACK_K2_E5 (0x1<<0) // Set to 1 by firmware wh…
19309 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
19315 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
19424 …execution. It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
19426 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
19430 …L0_DRIVE_BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when changi…
19450 … (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a comman…
19459 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
19461 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
19463 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
19465 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
19467 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19469 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19471 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19473 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19476 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
19478 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
19481 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
19483 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
19486 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
19488 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
19491 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
19493 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
19516 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
19518 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
19521 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
19523 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
19526 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
19528 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
19531 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
19533 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
19885 …2_E5 (0x1<<0) // Enables the run-length detection digi…
19887 … 0x009410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
19889 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
19891 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
20062 … 0x00981cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20063 … 0x009820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20069 …Access:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp…
20098 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
20121 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20122 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20123 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20124 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20126 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
20128 …Access:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp…
20253 … (0x3<<0) // How many times to repeat CTLE adaptation sequence for initial adaptation set 0
20255 … (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
20272 …set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alo…
20274 …set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alo…
20281 … (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
20283 … (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
20285 … (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
20287 … (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
20298 … (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0…
20300 … (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0…
20310 … (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
20312 … (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
20347 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
20454 …/ Output corresponding to link training signal detect variable. Should be set when link training …
20458 …coded as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width Should be set to 500ns for 802.3 …
20460 …been trained and are ready. This is an 802.3 defined variable. Should be set between 100 and 300…
20476 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
20478 …x_ready variable. After this is asserted the corresponding frame status report field should be set.
20483 …/Access:RW DataWidth:0x8 // Initial PRBS LFSR seed. This needs to be set according to the re…
20488 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
20492 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
20499 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
20503 …E5 (0x3<<4) // Status report field for pre-cursor tap.
20505 …<6) // Status report field to indicate local receiver is ready. Should be set based on LTSM outpu…
20520 … (0x1<<1) // This is the 802.3 defined training variable. It should be set according to corres…
20546 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
20550 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
20557 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
20561 … (0x3<<4) // Received status report field for pre-cursor tap.
20568 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
20570 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
20572 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
20574 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
20650 …must also be set. 0 : TX data from customer logics 1: RX data for Far-End-Digital FED loopback 2: …
20654 …<5) // Controls tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be …
20657 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
20700 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
20782 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20783 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20785 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
20852 … 0x00a2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
20854 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
20861 …t, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_…
20864 …means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
21019 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
21037 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
21041 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
21060 … 0x00a650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
21061 … 0x00a654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
21065 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
21068 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
21084 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
21086 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
21088 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
21090 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
21092 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
21094 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
21096 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
21098 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
21101 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
21103 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
21105 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
21107 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
21110 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
21117 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
21119 …x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
21122 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21124 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
21126 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21128 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
21130 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21132 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
21134 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21136 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
21189 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
21192 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
21210 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
21212 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
21214 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
21216 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
21218 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
21220 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
21222 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
21224 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
21227 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
21229 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
21231 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
21233 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
21236 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
21243 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
21245 …k partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
21248 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21250 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
21252 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21254 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
21256 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21258 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
21260 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21262 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
21313 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
21315 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
21317 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
21319 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
21321 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
21323 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
21325 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
21327 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
21330 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
21332 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
21334 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
21336 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
21338 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
21340 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
21342 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
21345 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
21358 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
21360 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
21362 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
21364 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
21366 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
21368 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
21370 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
21372 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
21375 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
21377 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
21379 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
21381 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
21383 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
21385 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
21985 … (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until…
21988 …ATUS0_ACK_K2_E5 (0x1<<0) // Set to 1 by firmware wh…
21991 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
21997 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
22106 …execution. It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
22108 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
22112 …L0_DRIVE_BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when changi…
22132 … (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a comman…
22141 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
22143 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
22145 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
22147 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
22149 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22151 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22153 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22155 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22158 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
22160 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
22163 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
22165 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
22168 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
22170 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
22173 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
22175 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
22198 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
22200 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
22203 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
22205 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
22208 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
22210 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
22213 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
22215 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
22567 …2_E5 (0x1<<0) // Enables the run-length detection digi…
22569 … 0x00b410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
22571 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
22573 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
22744 … 0x00b81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22745 … 0x00b820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22751 …Access:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp…
22780 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
22803 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22804 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22805 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22806 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22808 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
22810 …Access:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp…
22935 … (0x3<<0) // How many times to repeat CTLE adaptation sequence for initial adaptation set 0
22937 … (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
22954 …set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alo…
22956 …set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alo…
22963 … (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
22965 … (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
22967 … (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
22969 … (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
22980 … (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0…
22982 … (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0…
22992 … (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
22994 … (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
23029 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
23136 …/ Output corresponding to link training signal detect variable. Should be set when link training …
23140 …coded as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width Should be set to 500ns for 802.3 …
23142 …been trained and are ready. This is an 802.3 defined variable. Should be set between 100 and 300…
23158 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
23160 …x_ready variable. After this is asserted the corresponding frame status report field should be set.
23165 …/Access:RW DataWidth:0x8 // Initial PRBS LFSR seed. This needs to be set according to the re…
23170 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
23174 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
23181 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
23185 …E5 (0x3<<4) // Status report field for pre-cursor tap.
23187 …<6) // Status report field to indicate local receiver is ready. Should be set based on LTSM outpu…
23202 … (0x1<<1) // This is the 802.3 defined training variable. It should be set according to corres…
23228 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
23232 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
23239 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
23243 … (0x3<<4) // Received status report field for pre-cursor tap.
23250 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
23252 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
23254 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
23256 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
23332 …must also be set. 0 : TX data from customer logics 1: RX data for Far-End-Digital FED loopback 2: …
23336 …<5) // Controls tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be …
23339 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
23382 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
23464 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23465 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23467 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
23534 … 0x00c2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
23536 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
23543 …t, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_…
23546 …means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
23701 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
23719 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
23723 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
23742 … 0x00c650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
23743 … 0x00c654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
23747 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
23750 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
23766 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
23768 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
23770 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
23772 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
23774 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
23776 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
23778 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
23780 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
23783 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
23785 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
23787 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
23789 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
23792 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
23799 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
23801 …x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
23804 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23806 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
23808 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23810 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
23812 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23814 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
23816 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23818 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
23871 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
23874 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
23892 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
23894 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
23896 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
23898 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
23900 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
23902 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
23904 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
23906 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
23909 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
23911 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
23913 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
23915 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
23918 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
23925 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
23927 …k partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
23930 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23932 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
23934 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23936 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
23938 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23940 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
23942 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23944 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
23995 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
23997 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
23999 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
24001 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
24003 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
24005 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
24007 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
24009 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
24012 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
24014 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
24016 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
24018 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
24020 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
24022 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
24024 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
24027 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
24040 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
24042 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
24044 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
24046 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
24048 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
24050 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
24052 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
24054 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
24057 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
24059 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
24061 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
24063 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
24065 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
24067 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
24667 … (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until…
24670 …ATUS0_ACK_K2_E5 (0x1<<0) // Set to 1 by firmware wh…
24673 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
24679 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
24788 …execution. It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
24790 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
24794 …L0_DRIVE_BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when changi…
24814 … (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a comman…
24823 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
24825 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
24827 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
24829 …n FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields ta…
24831 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24833 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24835 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24837 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24840 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
24842 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
24845 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
24847 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
24850 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
24852 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
24855 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
24857 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
24880 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
24882 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
24885 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
24887 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
24890 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
24892 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
24895 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
24897 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
25249 …2_E5 (0x1<<0) // Enables the run-length detection digi…
25251 … 0x00d410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
25253 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
25255 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
25426 … 0x00d81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25427 … 0x00d820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25433 …Access:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp…
25462 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
25485 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25486 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25487 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25488 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25490 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
25492 …Access:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp…
25617 … (0x3<<0) // How many times to repeat CTLE adaptation sequence for initial adaptation set 0
25619 … (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
25636 …set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alo…
25638 …set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alo…
25645 … (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
25647 … (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
25649 … (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
25651 … (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
25662 … (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0…
25664 … (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0…
25674 … (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
25676 … (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
25711 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
25818 …/ Output corresponding to link training signal detect variable. Should be set when link training …
25822 …coded as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width Should be set to 500ns for 802.3 …
25824 …been trained and are ready. This is an 802.3 defined variable. Should be set between 100 and 300…
25840 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
25842 …x_ready variable. After this is asserted the corresponding frame status report field should be set.
25847 …/Access:RW DataWidth:0x8 // Initial PRBS LFSR seed. This needs to be set according to the re…
25852 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
25856 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
25863 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
25867 …E5 (0x3<<4) // Status report field for pre-cursor tap.
25869 …<6) // Status report field to indicate local receiver is ready. Should be set based on LTSM outpu…
25884 … (0x1<<1) // This is the 802.3 defined training variable. It should be set according to corres…
25910 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
25914 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
25921 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
25925 … (0x3<<4) // Received status report field for pre-cursor tap.
25937 … (0x7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Ena…
25950 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
25953 …AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
25965 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25966 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25967 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25969 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25971 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
25972 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
25973 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
25974 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
25975 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
25976 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
25977 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
25978 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
25979 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
25980 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
25981 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
25982 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
25983 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
25984 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
25985 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
25986 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
26004 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
26006 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
26008 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
26010 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26013 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
26015 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26017 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26019 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
26022 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26024 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26026 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26028 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26031 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
26033 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26035 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26037 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
26040 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
26042 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26044 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26096 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
26104 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
26138 …2_E5 (0x1<<2) // Override enable for overriding N-div value
26157 …1_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
26175 …E5 (0x1<<0) // Override for primary IO: refclk_oe_l_i Enabl…
26177 …5 (0x1<<1) // "Override for primary IO: refclk_oe_r_i Enabl…
26179 … (0x1<<2) // "Override for primary IO: rxclk_oe_l_i Enable…
26181 …5 (0x1<<3) // Override for primary IO: rxclk_oe_l_i Enable…
26185 …2_E5 (0x1<<6) // Override for primary IO: refclk_qfwd_l_i Ena…
26187 …2_E5 (0x1<<7) // Override for primary IO: refclk_qfwd_r_i Ena…
26207 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
26214 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
26216 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
26229 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
26231 …P_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
26252 …_K2_E5 (0x1<<0) // Debug feature, when set forces circuit RX t…
26263 …r following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO [0] …
26271 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
26273 …BUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
26285 … 0x000264UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
26286 … 0x000268UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
26287 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
26523 … 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b010 - pma_lX_rxb_iRecovered byte clock 3'b011 - ck_soc1_int…
26525 … (0x1<<3) // Clock divider for TX path branch 1 : 0-No division, 1- Divide by 2
26527 …h branch 2 clock : 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b011 - ck_soc1_int_root 3'b010,3'b100,3'b1…
26529 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
26532 …ck : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b0…
26534 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
26536 …ck : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b0…
26538 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
26541 …- qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmi…
26543 … (0x1<<3) // Clock divider for RX path branch 3 : 0-No division, 1- Divide by 2
26545 …- qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmi…
26547 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
26550 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
26552 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
26555 …0_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
26560 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
26562 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
26567 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
26569 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
26575 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
26577 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
26582 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
26584 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
26586 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26587 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26588 … 0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
26589 … 0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
26590 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
26592 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
26599 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
26619 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
26620 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26621 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26622 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26623 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26631 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
26632 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
26633 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
26634 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
26635 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
26636 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
26637 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
26638 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
26639 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
26640 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
26641 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
26642 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
26643 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
26644 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
26645 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
26646 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
26647 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
26648 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
26649 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
26650 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
26655 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
26657 …E5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
26659 …_K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
26667 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
26712 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
26714 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
26716 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
26720 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26721 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26722 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26724 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26726 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
26776 …_O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
26783 …_O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
26828 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
26830 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
26846 …5 (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative…
26875 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
26877 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
26881 …OVR_K2_E5 (0x1<<7) // Debug feature, when set forces circuit to b…
26894 … 0x0011f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
26962 …_K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
26964 …K2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
27046 …s set to 0 8-bit or 10-bit mode. 2'b11: the …
27048 … set to 0 10-bit or 20-bit mode. 2'b11: the m…
27050 … 3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1…
27075 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
27087 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
27359 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
27361 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27363 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27365 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27369 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
27372 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27374 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27376 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27378 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27380 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27382 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27387 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27389 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27407 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
27411 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
27462 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
27464 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
27481 …14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in…
27488 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
27498 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
27501 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
27503 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
27553 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
27554 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
27555 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
27556 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
27557 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
27558 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
27559 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
27560 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
27561 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
27562 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
27563 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
27564 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
27565 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
27566 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
27567 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
27568 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
27571 …nction. Varies depending on function number. Bits 15-7: Address of first command to run Bits: 6-…
27640 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
27641 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
27978 …_LOW_EN_O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a prog…
27980 …LOW_EN_O_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor down to a prog…
27998 …R_DFE_O_K2_E5 (0x1<<6) // Set all DFE calibration values to mid-sca…
28000 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
28002 …ONT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
28004 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
28005 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
28006 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
28007 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
28008 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
28009 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
28010 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
28014 …ECAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration for { Tap…
28023 …ATE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
28173 …NE_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
28175 …ADAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
28637 …E_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
28901 … (0x7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Ena…
28914 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
28917 …_AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
28929 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28930 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28931 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28933 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28935 … 0x003028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
28936 … 0x00302cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
28937 … 0x003030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
28938 … 0x003034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
28939 … 0x003038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
28940 … 0x00303cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
28941 … 0x003040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
28942 … 0x003044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
28943 … 0x003048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
28944 … 0x00304cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
28945 … 0x003050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
28946 … 0x003054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
28947 … 0x003058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
28948 … 0x00305cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
28949 … 0x003060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
28950 … 0x003064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
28968 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
28970 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
28972 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
28974 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28977 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
28979 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28981 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28983 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
28986 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28988 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28990 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28992 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28995 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
28997 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28999 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29001 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29004 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29006 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29008 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29060 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29068 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
29102 …K2_E5 (0x1<<2) // Override enable for overriding N-div value
29121 …01_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29139 …_E5 (0x1<<0) // Override for primary IO: refclk_oe_l_i Enabl…
29141 …E5 (0x1<<1) // "Override for primary IO: refclk_oe_r_i Enabl…
29143 …5 (0x1<<2) // "Override for primary IO: rxclk_oe_l_i Enable…
29145 …E5 (0x1<<3) // Override for primary IO: rxclk_oe_l_i Enable…
29149 …K2_E5 (0x1<<6) // Override for primary IO: refclk_qfwd_l_i Ena…
29151 …K2_E5 (0x1<<7) // Override for primary IO: refclk_qfwd_r_i Ena…
29171 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
29178 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29180 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29193 … 0x0031e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29195 …MP_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29216 …R_K2_E5 (0x1<<0) // Debug feature, when set forces circuit RX t…
29227 …r following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO [0] …
29235 … 0x003210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29237 …TBUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29249 … 0x003264UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
29250 … 0x003268UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
29251 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
29492 … (0x7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Ena…
29505 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
29508 …HB_PMA_CM_DIVNSEL_6_0_O_K2_E5 (0x7f<<0) // CMU N-divider setting
29520 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29521 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29522 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29524 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29526 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
29527 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
29528 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
29529 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
29530 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
29531 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
29532 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
29533 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
29534 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
29535 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
29536 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
29537 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
29538 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
29539 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
29540 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
29541 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
29559 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
29561 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
29563 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
29565 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29568 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
29570 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29572 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29574 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
29577 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29579 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29581 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29583 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29586 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
29588 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29590 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29592 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29595 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29597 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29599 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29640 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29648 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
29682 …_E5 (0x1<<2) // Override enable for overriding N-div value
29701 …_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29714 …5 (0x1<<0) // Override for primary IO: refclk_oe_l_i Enabl…
29716 … (0x1<<1) // "Override for primary IO: refclk_oe_r_i Enabl…
29718 … (0x1<<2) // "Override for primary IO: rxclk_oe_l_i Enable…
29720 … (0x1<<3) // Override for primary IO: rxclk_oe_l_i Enable…
29724 …_E5 (0x1<<6) // Override for primary IO: refclk_qfwd_l_i Ena…
29726 …_E5 (0x1<<7) // Override for primary IO: refclk_qfwd_r_i Ena…
29746 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
29753 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29755 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29768 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29770 …_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29791 …K2_E5 (0x1<<0) // Debug feature, when set forces circuit RX t…
29802 …r following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO [0] …
29810 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29812 …US_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29878 …A_CM_DIVPSEL_GEN3_O_K2_E5 (0x7f<<0) // CMU P-divider setting in ge…
29904 … 0x000264UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
29905 … 0x000268UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
29906 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
30245 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
30248 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
30250 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
30253 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
30256 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
30258 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
30261 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
30270 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
30272 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
30277 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
30279 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
30285 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
30287 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
30292 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
30294 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
30296 … 0x000824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30297 … 0x000828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30298 … 0x00082cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
30299 … 0x000830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
30300 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
30302 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
30309 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
30329 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
30330 … 0x000854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30331 … 0x000858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30332 … 0x00085cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30333 … 0x000860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30341 … 0x000880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
30342 … 0x000884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
30343 … 0x000888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
30344 … 0x00088cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
30345 … 0x000890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
30346 … 0x000894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
30347 … 0x000898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
30348 … 0x00089cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
30349 … 0x0008a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
30350 … 0x0008a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
30351 … 0x0008a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
30352 … 0x0008acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
30353 … 0x0008b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
30354 … 0x0008b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
30355 … 0x0008b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
30356 … 0x0008bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
30357 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
30358 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
30359 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
30360 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
30365 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
30367 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
30369 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
30377 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
30421 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
30423 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
30425 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
30429 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30430 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30431 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30433 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30435 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
30485 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
30492 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
30536 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
30538 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
30554 … (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative…
30627 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
30629 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
30633 …VR_K2_E5 (0x1<<7) // Debug feature, when set forces circuit to b…
30646 … 0x0009f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
30714 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
30716 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
30794 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
30800 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
30802 … 0x000a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
30804 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
30806 … 0x000a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
30824 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
30832 …s set to 0 8-bit or 10-bit mode. 2'b11: the …
30834 … set to 0 10-bit or 20-bit mode. 2'b11: the m…
30836 … 3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1…
30861 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
30869 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
31139 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
31141 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31143 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31145 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31149 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
31152 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31154 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31156 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31158 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31160 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31162 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31167 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31169 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31187 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
31191 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
31244 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
31289 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
31291 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
31308 …14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in…
31317 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
31325 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
31328 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
31330 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
31333 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
31336 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
31338 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
31341 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
31350 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
31352 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
31357 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
31359 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
31365 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
31367 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
31372 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
31374 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
31376 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31377 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31378 … 0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
31379 … 0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
31380 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
31382 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
31389 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
31409 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
31410 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31411 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31412 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31413 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31421 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
31422 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
31423 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
31424 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
31425 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
31426 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
31427 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
31428 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
31429 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
31430 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
31431 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
31432 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
31433 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
31434 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
31435 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
31436 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
31437 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
31438 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
31439 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
31440 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
31445 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
31447 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
31449 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
31457 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
31501 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
31503 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
31505 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
31509 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31510 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31511 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31513 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31515 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
31565 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
31572 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
31616 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
31618 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
31634 … (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative…
31707 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
31709 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
31713 …VR_K2_E5 (0x1<<7) // Debug feature, when set forces circuit to b…
31726 … 0x0011f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
31794 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
31796 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
31874 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
31880 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
31882 … 0x001280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
31884 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
31886 … 0x001288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
31904 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
31912 …s set to 0 8-bit or 10-bit mode. 2'b11: the …
31914 … set to 0 10-bit or 20-bit mode. 2'b11: the m…
31916 … 3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1…
31941 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
31949 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
32219 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
32221 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32223 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32225 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32229 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
32232 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32234 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32236 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32238 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32240 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32242 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32247 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32249 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32267 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
32271 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
32324 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
32369 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
32371 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
32388 …14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in…
32397 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
32405 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
32408 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
32410 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
32413 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
32416 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
32418 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
32421 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
32430 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
32432 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
32437 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
32439 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
32445 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
32447 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
32452 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
32454 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
32456 … 0x001824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32457 … 0x001828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32458 … 0x00182cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
32459 … 0x001830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
32460 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
32462 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
32469 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
32489 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
32490 … 0x001854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32491 … 0x001858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32492 … 0x00185cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32493 … 0x001860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32501 … 0x001880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
32502 … 0x001884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
32503 … 0x001888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
32504 … 0x00188cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
32505 … 0x001890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
32506 … 0x001894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
32507 … 0x001898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
32508 … 0x00189cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
32509 … 0x0018a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
32510 … 0x0018a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
32511 … 0x0018a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
32512 … 0x0018acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
32513 … 0x0018b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
32514 … 0x0018b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
32515 … 0x0018b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
32516 … 0x0018bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
32517 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
32518 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
32519 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
32520 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
32525 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
32527 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
32529 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
32537 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
32581 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
32583 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
32585 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
32589 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32590 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32591 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32593 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32595 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
32645 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
32652 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
32696 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
32698 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
32714 … (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative…
32787 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
32789 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
32793 …VR_K2_E5 (0x1<<7) // Debug feature, when set forces circuit to b…
32806 … 0x0019f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
32874 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
32876 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
32954 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
32960 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
32962 … 0x001a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
32964 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
32966 … 0x001a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
32984 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
32992 …s set to 0 8-bit or 10-bit mode. 2'b11: the …
32994 … set to 0 10-bit or 20-bit mode. 2'b11: the m…
32996 … 3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1…
33021 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
33029 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
33299 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
33301 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33303 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33305 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33309 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
33312 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33314 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33316 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33318 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33320 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33322 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33327 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33329 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33347 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
33351 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
33404 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
33449 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
33451 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
33468 …14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in…
33477 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
33485 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
33488 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
33490 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
33493 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
33496 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
33498 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
33501 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
33510 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
33512 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
33517 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
33519 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
33525 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
33527 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
33532 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
33534 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
33536 … 0x002024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33537 … 0x002028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33538 … 0x00202cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
33539 … 0x002030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
33540 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
33542 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
33549 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
33569 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
33570 … 0x002054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33571 … 0x002058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33572 … 0x00205cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33573 … 0x002060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33581 … 0x002080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
33582 … 0x002084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
33583 … 0x002088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
33584 … 0x00208cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
33585 … 0x002090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
33586 … 0x002094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
33587 … 0x002098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
33588 … 0x00209cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
33589 … 0x0020a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
33590 … 0x0020a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
33591 … 0x0020a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
33592 … 0x0020acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
33593 … 0x0020b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
33594 … 0x0020b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
33595 … 0x0020b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
33596 … 0x0020bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
33597 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
33598 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
33599 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
33600 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
33605 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
33607 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
33609 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
33617 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
33661 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
33663 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
33665 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
33669 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33670 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33671 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33673 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33675 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
33725 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
33732 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
33776 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
33778 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
33794 … (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative…
33867 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
33869 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
33873 …VR_K2_E5 (0x1<<7) // Debug feature, when set forces circuit to b…
33886 … 0x0021f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
33954 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
33956 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
34034 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
34040 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
34042 … 0x002280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
34044 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
34046 … 0x002288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
34064 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
34072 …s set to 0 8-bit or 10-bit mode. 2'b11: the …
34074 … set to 0 10-bit or 20-bit mode. 2'b11: the m…
34076 … 3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1…
34101 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
34109 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
34379 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
34381 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34383 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34385 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34389 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
34392 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34394 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34396 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34398 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34400 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34402 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34407 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34409 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34427 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
34431 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
34484 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
34529 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
34531 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
34548 …14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in…
34557 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
34565 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
34568 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
34570 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
34621 … 0x002880UL //Access:RW DataWidth:0x8 // SKP symbol for PCIe Gen3 SKP OS ---8'hAA
34631 … 0x002898UL //Access:RW DataWidth:0x8 // 10-bit align symbol for …
34633 …_S0_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for …
34635 … 0x0028a0UL //Access:RW DataWidth:0x8 // 10-bit align symbol for …
34637 …_S1_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for …
34702 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
34703 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
34704 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
34705 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
34706 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
34707 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
34708 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
34709 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
34710 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
34711 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
34712 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
34713 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
34714 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
34715 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
34716 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
34717 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
34720 …nction. Varies depending on function number. Bits 15-7: Address of first command to run Bits: 6-…
34789 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
34790 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
35203 …E1_TX_SLEW_SLD3F_2_0_K2_E5 (0x7<<2) // TX enable fastest slew rate set to 1.
35205 …E2_TX_SLEW_SLD3F_2_0_K2_E5 (0x7<<5) // TX enable fastest slew rate set to 1.
35208 …E3_TX_SLEW_SLD3F_2_0_K2_E5 (0x7<<0) // TX enable fastest slew rate set to 1.
35260 …LOW_EN_O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a prog…
35262 …OW_EN_O_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor down to a prog…
35280 …_DFE_O_K2_E5 (0x1<<6) // Set all DFE calibration values to mid-sca…
35282 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
35284 …NT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
35286 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
35287 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
35288 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
35289 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
35290 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
35291 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
35292 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
35296 …CAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration for { Tap…
35305 …TE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
35464 …E_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
35466 …DAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
35475 …2_E5 (0x1f<<0) // Bit 4 - latency check control enable Bit 3:0 - l…
35973 …_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
36036 …X414_TXPRESET_COEFF_P0CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P0 C-1
36045 …X417_TXPRESET_COEFF_P1CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P1 C-1
36054 …X420_TXPRESET_COEFF_P2CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P2 C-1
36063 …X423_TXPRESET_COEFF_P3CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P3 C-1
36072 …X426_TXPRESET_COEFF_P4CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P4 C-1
36081 …X429_TXPRESET_COEFF_P5CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P5 C-1
36090 …X432_TXPRESET_COEFF_P6CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P6 C-1
36099 …X435_TXPRESET_COEFF_P7CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P7 C-1
36108 …X438_TXPRESET_COEFF_P8CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P8 C-1
36117 …X441_TXPRESET_COEFF_P9CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P9 C-1
36126 …444_TXPRESET_COEFF_P10CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P10 C-1
36355 …- no auto deassertion; 1 - auto deassertion); [1] rst_pswrd_auto_mode (0- no auto deassertion; 1 -…
36356 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36358 …-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific bloc…
36360 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36362 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36364 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36366 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36372 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
36380 … 0x008400UL //Access:RW DataWidth:0x1 // Set/clr general attention 0; this will set/…
36381 … 0x008404UL //Access:RW DataWidth:0x1 // Set/clr general attention 1; this will set…
36382 … 0x008408UL //Access:RW DataWidth:0x1 // Set/clr general attention 2; this will set…
36383 … 0x00840cUL //Access:RW DataWidth:0x1 // Set/clr general attention 3; this will set…
36384 … 0x008410UL //Access:RW DataWidth:0x1 // Set/clr general attention 4; this will set/…
36385 … 0x008414UL //Access:RW DataWidth:0x1 // Set/clr general attention 5; this will set/…
36386 … 0x008418UL //Access:RW DataWidth:0x1 // Set/clr general attention 6; this will set/…
36387 … 0x00841cUL //Access:RW DataWidth:0x1 // Set/clr general attention 7; this will set/…
36388 … 0x008420UL //Access:RW DataWidth:0x1 // Set/clr general attention 8; this will set/…
36389 … 0x008424UL //Access:RW DataWidth:0x1 // Set/clr general attention 9; this will set/…
36390 … 0x008428UL //Access:RW DataWidth:0x1 // Set/clr general attention 10; this will set…
36391 … 0x00842cUL //Access:RW DataWidth:0x1 // Set/clr general attention 11; this will set…
36392 … 0x008430UL //Access:RW DataWidth:0x1 // Set/clr general attention 12; this will set…
36393 … 0x008434UL //Access:RW DataWidth:0x1 // Set/clr general attention 13; this will set…
36394 … 0x008438UL //Access:RW DataWidth:0x1 // Set/clr general attention 14; this will set…
36395 … 0x00843cUL //Access:RW DataWidth:0x1 // Set/clr general attention 15; this will set…
36396 … 0x008440UL //Access:RW DataWidth:0x1 // Set/clr general attention 16; this will set…
36397 … 0x008444UL //Access:RW DataWidth:0x1 // Set/clr general attention 17; this will set…
36398 … 0x008448UL //Access:RW DataWidth:0x1 // Set/clr general attention 18; this will set…
36399 … 0x00844cUL //Access:RW DataWidth:0x1 // Set/clr general attention 19; this will set…
36400 … 0x008450UL //Access:RW DataWidth:0x1 // Set/clr general attention 20; this will set…
36401 … 0x008454UL //Access:RW DataWidth:0x1 // Set/clr general attention 21; this will set…
36402 … 0x008458UL //Access:RW DataWidth:0x1 // Set/clr general attention 22; this will set…
36403 … 0x00845cUL //Access:RW DataWidth:0x1 // Set/clr general attention 23; this will set…
36404 … 0x008460UL //Access:RW DataWidth:0x1 // Set/clr general attention 24; this will set…
36405 … 0x008464UL //Access:RW DataWidth:0x1 // Set/clr general attention 25; this will set…
36406 … 0x008468UL //Access:RW DataWidth:0x1 // Set/clr general attention 26; this will set…
36407 … 0x00846cUL //Access:RW DataWidth:0x1 // Set/clr general attention 27; this will set…
36408 … 0x008470UL //Access:RW DataWidth:0x1 // Set/clr general attention 28; this will set…
36409 … 0x008474UL //Access:RW DataWidth:0x1 // Set/clr general attention 29; this will set…
36410 … 0x008478UL //Access:RW DataWidth:0x1 // Set/clr general attention 30; this will set…
36411 … 0x00847cUL //Access:RW DataWidth:0x1 // Set/clr general attention 31; this will set…
36412 … 0x008480UL //Access:RW DataWidth:0x1 // Set/clr general attention 32; this will set…
36413 … 0x008484UL //Access:RW DataWidth:0x1 // Set/clr general attention 33; this will set…
36414 … 0x008488UL //Access:RW DataWidth:0x1 // Set/clr general attention 34; this will set…
36415 … 0x00848cUL //Access:RW DataWidth:0x1 // Set/clr general attention 35; this will set…
36422 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36424 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36426 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36431 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36433 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36435 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36440 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36442 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36444 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36449 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36451 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36453 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36458 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36460 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36462 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36467 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36469 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36471 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36476 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36478 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36480 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36485 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36487 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36489 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36494 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36496 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36498 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36503 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36505 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36507 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36512 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36514 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36516 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36521 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36523 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36525 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36530 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36532 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36534 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36539 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36541 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36543 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36548 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36550 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36552 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36557 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36559 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36561 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36566 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36568 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36570 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36575 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36577 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36579 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36584 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36586 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36588 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36593 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36595 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36597 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36602 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36604 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36606 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36611 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36613 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36615 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36620 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36622 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36624 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36629 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36631 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36633 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36635 … 0x0087fcUL //Access:RW DataWidth:0x1 // If set a system kill occur…
36636 …0x008800UL //Access:RW DataWidth:0x1 // The System Kill enable: 0 - none; 1 - hard reset. Res…
36637 …ster while this register isn't conditoned by it. This means that status is set with no respect to …
36638 …ster while this register isn't conditoned by it. This means that status is set with no respect to …
36639 …ster while this register isn't conditoned by it. This means that status is set with no respect to …
36640 …-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity erro…
36641 …ster while this register isn't conditoned by it. This means that status is set with no respect to …
36642 …-24] Rsvd; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw inte…
36643 …ster while this register isn't conditoned by it. This means that status is set with no respect to …
36644 …-assertion; [30] WOL Parity error; [31] WOL Hw interrupt; System kill signal (that which causes ha…
36645 …ster while this register isn't conditoned by it. This means that status is set with no respect to …
36655 …m_attn; [6] one clears PERST_N assertion (goes 0); [7] one clears PERST_N de-assertion (goes 1). […
36657 …ister results with the clear of the latched signals; [0] - clears pglue_misc_vpd_attn[0], [1] - cl…
36659 … 0x00883cUL //Access:RW DataWidth:0x9 // Attention sticky number - latches first attent…
36660 … 0x008c00UL //Access:RW DataWidth:0x2 // Port mode. 0 - single port; 1 - 2 ports; 2 - 4 por…
36661 … Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 1x …
36662 …s is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 10 - Tri Port…
36663 …- disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port. Port…
36664 …IFOs should be bypassed in latency-critical paths. bit0 - clock mux control (Obsolete), bit1 - BRB…
36665 …ammed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset. [0]…
36667 …- Storms stall is disallowed; AEU unifier bit[7] output to MCP is disabled; 1 - All Storms are for…
36668 …c20UL //Access:RW DataWidth:0x17 // 23 bit GRC address where the scratch-pad of the MCP that i…
36669 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36670 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36671 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36672 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36673 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36674 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36675 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36676 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36677 …ounter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_1 [1] ) is set.
36678 …unter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_2.SW_TIMER_CFG_2 [1] ) is set.
36679 …unter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_3.SW_TIMER_CFG_3 [1] ) is set.
36680 …unter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_4.SW_TIMER_CFG_4 [1] ) is set.
36681 …unter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_5 [1] ) is set.
36682 …unter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_6 [1] ) is set.
36683 …ounter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_7 [1] ) is set.
36684 …ounter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_8 [1] ) is set.
36685 …_7.SW_TIMER_CFG_7 [2]; MISC_REGISTERS_SW_TIMER_CFG_8.SW_TIMER_CFG_8 [2] is set). [0] timer1; [1] t…
36701 …he counter for sw timers1-8. there are 8 addresses in this register. address 0 - timer 1; address …
36703 …- no auto deassertion; 1 - auto deassertion); [1] rst_umac_on_core_rst (0- no auto deassertion; 1 …
36704 …- is not reset on hard reset; 1 - is reset on hard reset); [1] rst_n_hard_misc_rbc_pcie (0 - is no…
36705 …set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a…
36707 …set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a…
36709 … main clock frequency (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G mode. …
36710 …med to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50…
36711 …- source of privilege level, 0 - the source is external pin, 1 - the source are bits[2:1] of this …
36712 … // Privilege level as defined by external pin. 0 - non-secured mode; 1 - secured mode; 2 - full…
36713 …-disable to the NVM block is generated. '0' - PROTECT: This value protects the NVM from any writes…
36714 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36716 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36718 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36720 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36722 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36724 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36726 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36728 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36730 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36732 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36734 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36736 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36738 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36740 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36742 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36744 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36746 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
36748 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
36750 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
36752 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
36754 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
36756 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
36758 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
36760 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
36762 …set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a…
36768 … 0x009170UL //Access:RW DataWidth:0x1 // When set enables the deglitc…
36777 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
36779 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
36781 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
36821 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
36823 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
36825 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
36827 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
36829 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
36831 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
36833 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
36835 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
36837 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
36839 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
36841 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
36890 … (0x1<<0) // This bit masks, when set, the Parity bit: MI…
36892 …state of the ptw_miscs_pcie_link_up signal which is driven by the PCIE core - a pulse at the begin…
36893 …ate of the ptw_miscs_pcie_hot_reset signal which is driven by the PCIE core - a pulse at the begin…
36895 … DataWidth:0x10 // Accounts for HOT RESET assertion when the chip is in un-prepared state. Is re…
36897 …4UL //Access:RW DataWidth:0x1 // Set to 1 when main PLL lock indication is de-asserted when h…
36898 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36899 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36900 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36901 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36902 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36903 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36904 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36905 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36906 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36907 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36908 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36909 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36910 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36911 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36912 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36913 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36914 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36915 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36916 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36917 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36918 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36919 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36920 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36921 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36922 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36923 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36924 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36925 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36926 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36927 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36928 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36929 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36931 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36932 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36933 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36934 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36935 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36936 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36937 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36938 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36939 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36940 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36941 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36942 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36943 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36944 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36945 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36946 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36947 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36948 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36949 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36950 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36951 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36952 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36953 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36954 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36955 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36956 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36957 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36958 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36959 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36960 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36961 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36962 …SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will driv…
36963 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36964 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36965 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36966 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36967 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36968 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36969 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36970 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36971 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36972 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36973 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36974 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36975 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36976 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36977 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36978 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36979 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36980 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36981 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36982 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36983 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36984 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36985 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36986 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36987 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36988 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36989 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36990 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36991 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36992 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36993 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36994 …SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive …
36996 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
36997 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
36998 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
36999 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37000 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37001 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37002 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37003 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37004 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37005 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37006 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37007 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37008 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37009 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37010 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37011 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37012 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37013 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37014 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37015 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37016 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37017 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37018 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37019 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37020 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37021 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37022 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37023 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37024 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37025 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37026 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37027 …set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'…
37029 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
37031 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
37033 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
37035 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
37037 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
37039 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
37041 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
37043 …set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear bot…
37045 …to BSC_SDA0 IO. 01: connect SDA interface to BSC_SDA1 IO. 10: connect SDA interface to BSC_SDA2 IO…
37046 …IO de-assertion. If == 1, triggers chip core reset. If == 0, doesn't trigger chip core reset. Bit[…
37047 …Set to 1 to enable use of NIC magic packet detection to assert WAKE OOB. Reset on POR reset and PE…
37050 …0x0096b8UL //Access:R DataWidth:0x1 // Chip core_rst_n status. 0 - asserted; 1 - de-asserted.
37051 …ISTERS_LINK_HOLDOFF_REQ.LINK_HOLDOFF_REQ is set, this register should be polled till one of the fi…
37052 …set this bit; and then check the MISC_REGISTERS_LINK_HOLDOFF_STATUS.LINK_HOLDOFF_STATUS register. …
37057 … reset. If clear will not reset all the Vmain sm (backward compatible); if set will reset all the …
37059 …set to make use of that. Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When…
37061 …- spare RW register reset by por reset; [10:8] : PCIe Device Type: 3'b000 - Endpoint mode; 3'b010 …
37062 … 0x0096e8UL //Access:R DataWidth:0x1 // The isolation between Vaux and…
37063 … DataWidth:0x2 // 0-bypass the Vmain PORBG. for Vmain POR; if sel=1 the output wil be MISC_REGI…
37064 …// Bypass to the FUNC_HIDE pin. Bit 0 - bypass select; Bits[15:1] - bypass value per function (1 -…
37066 … 0x0096f8UL //Access:RW DataWidth:0x1 // When set enables the deglitc…
37067 … 0x0096fcUL //Access:RC DataWidth:0x1 // If set indicate that the p…
37069 … DataWidth:0x1 // NIG debug mux vector control. 0 - NIG0 debug vector is output to IFMUX; 1 -…
37070 …set this will allow any of the four emacs MDIO masters to initiate MDIO transactions to access XGX…
37071 …1 // NIG EMAC debug source selector. If 0 - path0 gmii/mii emac debug outputs are selected by N…
37072 …s:R DataWidth:0x2 // SEL_VAUX_B - Control to power switching logic. [0] - output value drive…
37073 …bit. PCIE DIS. Has same functionality as the external IO PCIE_DIS: Internal PCIE DIS = external IO…
37074 …th:0x1 // When set to 1, HiGig is supported on 40G and the nw mac clock frequency is higher tha…
37075 …s mapped to path 1. This is the same mapping E2 and E3 have. If the bit is set then those PFs are …
37076 … 0x009720UL //Access:RW DataWidth:0x1 // This bit will be set by the MCP when the…
37078 …-chip PHY devices and MAC ports to the four MDIO domains. It is only used when MISC_REGISTERS_MDIO…
37079 … DataWidth:0x1 // Set to 1 when pcie_hot_reset is asserted (Hot Reset / SBR / Link Down / Link…
37080 … 0x009730UL //Access:R DataWidth:0x5 // OTP IO 5 msb.
37082 …it as a '1' will cause the chip to do an internal reset exactly like a power-up reset. There is no…
37083 …set; the compatible bit in the MISC_REGISTERS_MAIN_SEQ_BYP_VAL.MAIN_SEQ_BYP_VAL affects the contro…
37084 …set; when reset; the SM affects the controls. Bit 0 - Vmain OTP reset; Bit 1 - isolation_logic_b; …
37087 …-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bi…
37088 …0UL //Access:RW DataWidth:0x1 // [0]clock storm bypass: 0-select Storm SPLL clock; 1-select e…
37089 …//Access:RW DataWidth:0x1 // Set by the MCP to remember if one or more of the drivers is/are …
37090 …//Access:RW DataWidth:0x1 // Set by the MCP to remember if one or more of the drivers is/are …
37091 …Access:RW DataWidth:0x1 // Set by the Driver to remember if one or more of the drivers is/are…
37092 … 0x009760UL //Access:R DataWidth:0x1 // 0 - VAUX is not present (external pin is 0); 1 …
37093 …IO: when pulsed low enables supply from VAUX. VAUX DISABLE Chip IO: when pulsed low disables suppl…
37096 … the chip. This value starts at 0x0 for the A0 tape-out and increments by one for each all-layer t…
37097 …f the chip. This value starts at 0x00 for each all-layer tape-out and increments by one for each t…
37099 …that the link is down and PCIE is prepared for operation off of VAUX. TBD: set to 0 in NM. Reserve…
37100 …nly. The PCI power will always read as '0' in this state; as if the chip is in Out-Of-Box WOL mode.
37103 … 0x00978cUL //Access:RW DataWidth:0x10 // Accounts for Hard reset de-assertion. Is reset o…
37105 … 0x009794UL //Access:RW DataWidth:0x10 // Accounts for Core de-reset assertion. Is r…
37107 … 0x00979cUL //Access:RW DataWidth:0x10 // Accounts for PERST_B reset de-assertion. Is reset o…
37109 … DataWidth:0x10 // Accounts for PCI_RST_N assertion when the chip is in un-prepared state. Is re…
37110 … 0x0097a8UL //Access:RW DataWidth:0x10 // Accounts for PCI_RST_N de-assertion. Is reset o…
37111 …-prepared state, hard reset is asserted. When =0, when ptw_miscs_pcie_hot_reset is asserted (Hot R…
37113 …UL //Access:RW DataWidth:0x20 // Eco reserved. Global register. [31:30] - used to programm loo…
37120 …r-ride: When set, over-ride DAC code from AVS monitor with on from this register [20:11] VMgmt DAC…
37121 …- Per-TC packet available status; [10] - STORM FIFO; [9] - BTB SOP FIFO for engine 0; [8] - BTB S…
37122 …- STORM FIFO almost full; [10] - STORM FIFO full; [9] - BTB SOP FIFO full for engine 0; [8] - …
37123 …- Received packet from BTB IF0 of engine 0; [6] - Received packet from BTB IF0 of engine 1; [5] …
37124 …- storm_init_crd: Credits for the output STORM Packet interface. [3:2] - storm_pkt_dst: Select t…
37125 …-full Threshold. [29:25] - Btb_if0_fifo_almfull_thr: Almost-full threshold for BTB main traffic F…
37143 … (0x1<<0) // When this bit is set, the UART timing wi…
37145 … (0x1<<1) // When this bit is set, the debug state ma…
37147 … (0x1<<2) // When this bit is set, all line feeds sha…
37150 … (0xffff<<0) // These bits set the number of core_…
37152 … (0xffff<<16) // These bits set the number of core_…
37154 …this register was received in error. This bit is valid only if rx_valid is set in the status regis…
37157 … (0xff<<0) // Set the VF for which th…
37159 … (0xff<<8) // Set the Port for which …
37161 … (0x1<<16) // The vfid_value bits are valid only if this bit is set. If this bit is cle…
37163 … (0x1<<20) // Set the path ID if the …
37167 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
37168 … enable. If 0 - the acknowledge input is disregarded; valid is deasserted; full is asserted; all o…
37169 …t;Master) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
37209 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
37211 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
37224 … (0x1<<0) // This bit masks, when set, the Parity bit: DM…
37226 … (0x1<<1) // This bit masks, when set, the Parity bit: DM…
37228 … (0x1<<2) // This bit masks, when set, the Parity bit: DM…
37231 … 0x00c400UL //Access:RW DataWidth:0x4 // DMAE- PCI Request Interfac…
37232 …404UL //Access:RW DataWidth:0x1 // Relaxed ordering. 0-strict PCI ordering is used;1-PCI-X re…
37233 … 0x00c408UL //Access:RW DataWidth:0x1 // 0-PCI type cache snoop protection is required;…
37234 …00c40cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 initial value is all zeroes; if 1 - t…
37235 … //Access:RW DataWidth:0x1 // If 0 - the CRC-16 final calculation result isn't byte swapped; …
37236 …0c414UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16c initial value is all zeroes; if 1 - t…
37237 …c418UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 T10 initial value is all zeroes; if 1 -…
37238 …00c41cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-32 initial value is all zeroes; if 1 - t…
37239 … //Access:RW DataWidth:0x1 // If 0 - the CRC-32 final calculation result isn't byte swapped; …
37240 …0c424UL //Access:RW DataWidth:0x1 // If 0 - the CRC-32c initial value is all zeroes; if 1 - t…
37241 …//Access:RW DataWidth:0x1 // If 0 - the CRC-32c final calculation result isn't byte swapped; …
37242 …0x00c42cUL //Access:RW DataWidth:0x1 // If 0 - the final checksum equal 0 won't be changed;if…
37243 …st ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; …
37244 …st ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; …
37245 … 0x00c438UL //Access:RW DataWidth:0x1 // When set discards 1- or 2-Dword PCI t…
37246 …h:0x14 // GRC address in case 1- or 2-Dword PCI transaction is discardd due to PCI error and dma…
37248 …ering Tag Index (value of 0x1FF means no steering tag in which case steering tag will be set to 0).
37250 …- Bidirectional shared data structure; 01 - Device writes/reads then device reads/writes soon; 10 …
37255 …: 0 - VN Virtualized NIC (Used for VF access); 1 - PDA Physical Device Assignment (Assigned to VM-…
37272 …- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other e…
37273 …- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other e…
37281 …as follows: 0-NONE; 1-DoubleBwTx (DoubleBw the TX side); 2-DoubleBwRx (DoubleBw the RX side); 3-Cr…
37282 …dex for slot 0 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37283 …dex for slot 1 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37284 …dex for slot 2 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37285 …dex for slot 3 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37286 …dex for slot 4 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37287 …dex for slot 5 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37288 …dex for slot 6 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37289 …dex for slot 7 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37290 …dex for slot 8 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37291 …dex for slot 9 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37292 …ex for slot 10 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37293 …ex for slot 11 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37294 …ex for slot 12 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37295 …ex for slot 13 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37296 …ex for slot 14 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37297 …ex for slot 15 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37299 …- 128b STORM (A and B) data is logged 1 - 64b STORM (A and B) data + 4 different (in general case)…
37300 …only: These bits indicate the target of the debug data: 0 - internal buffer; 1 - NIG; 2 - PCI.
37301 …-one shot (newest data is thrown) as follows: (a) When DBG_REGISTERS_DEBUG_TARGET =0 (internal buf…
37306 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
37315 … (0x1<<0) // This bit masks, when set, the Parity bit: DB…
37322 …when DBG_REGISTERS_DEBUG_TARGET =1 (NIG) and DBG_REGISTERS_FULL_MODE =0 (one-shot); WB Read Only (…
37333 …rget_packet_size data byte each); Relevant only when debug_target=1 (NIG) & full_mode=0 (one-shot).
37339 …nly: This bit enables the operation of the debug block; This bit should be set upon completion of …
37340 …- no grants will be made to the storms when the internal buffer is almost full. When the buffer w…
37341 … >= 12. Together with DBG_REG_BUFFER_THR_HIGH provides histerezis-like mechanism to set SEMI grant.
37342 …tes logical/physical address in PCI request as follows: (a) 1 - logical address; (b) 0 - physical…
37343 … to internal buffer to be output to IFMUX interface. 0 - bits[31:0] 1 - bits[63:32] 2:6 - etc. 7 -…
37344 … Debug only: together with DBG_REG_BUFFER_THR provides histerezis-like mechanism to set SEMI grant…
37345 …on is done as follows: bits 255:0 - data; bits 263:256 - frame; bits 271:264 - valid; bits 303:272…
37347 …nd filter_enable>0.NOTE: In order to take into consideration the SOP value set trigger_enable=1 an…
37349 …tor as follows: (a) 1 - bit is masked. This bit won't be compared with the DBG_REGISTERS_EXPECTED…
37351 … pattern recognition feature is disabled/enabled as follows: (a) 1 - disabled; (b) 0 - enabled;.
37352 …nition feature as follows: (a) 1 - stop debug data storgae when the expected pattern is initially…
37353 …occurence as follows: (a) 1 - enable continuously data storage after/before first occurence of pat…
37354 … // (a) 0 - trigger machine is off (all data will bypass the triggering machine); dbg_sem_trgr_…
37355 …- triggering interleaved messages is disabled. (b) 1 - triggering interleaved messages is enabled;…
37356 …[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be trigge…
37357 …[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be trigge…
37358 …[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be trigge…
37359 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37360 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37361 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37362 … // Next state in the fsm triggering machine if the referred constraints set in the specified st…
37363 … // Next state in the fsm triggering machine if the referred constraints set in the specified st…
37364 … // Next state in the fsm triggering machine if the referred constraints set in the specified st…
37365 … // Next state in the fsm triggering machine if the referred constraints set in the specified st…
37366 … // Next state in the fsm triggering machine if the referred constraints set in the specified st…
37367 … // Next state in the fsm triggering machine if the referred constraints set in the specified st…
37368 …ess:RW DataWidth:0x10 // Number of times that the referred constraints set should be met prior…
37369 …ess:RW DataWidth:0x10 // Number of times that the referred constraints set should be met prior…
37370 …ess:RW DataWidth:0x10 // Number of times that the referred constraints set should be met prior…
37371 …ess:RW DataWidth:0x10 // Number of times that the referred constraints set should be met prior…
37372 …ess:RW DataWidth:0x10 // Number of times that the referred constraints set should be met prior…
37373 …ess:RW DataWidth:0x10 // Number of times that the referred constraints set should be met prior…
37374 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37375 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37376 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37377 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37378 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37379 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37380 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37381 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37382 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37383 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37384 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37385 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37386 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37387 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37388 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37389 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37390 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37391 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37392 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37393 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37394 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37395 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37396 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37397 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37446 … 0x0106bcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37447 … 0x0106c0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37448 … 0x0106c4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37449 … 0x0106c8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37450 … 0x0106ccUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37451 … 0x0106d0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37452 … 0x0106d4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37453 … 0x0106d8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37454 … 0x0106dcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37455 … 0x0106e0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37456 … 0x0106e4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37457 … 0x0106e8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37458 … 0x0106ecUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37459 … 0x0106f0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37460 … 0x0106f4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37461 … 0x0106f8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37462 … 0x0106fcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37463 … 0x010700UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37464 … 0x010704UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37465 … 0x010708UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37466 … 0x01070cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37467 … 0x010710UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37468 … 0x010714UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37469 … 0x010718UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37470 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37471 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37472 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37473 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37474 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37475 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37476 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37477 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37478 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37479 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37480 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37481 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37482 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37483 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37484 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37485 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37486 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37487 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37488 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37489 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37490 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37491 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37492 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37493 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37614 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37615 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37616 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37617 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37618 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37619 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37620 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37621 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37622 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37623 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37624 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37625 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37626 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37627 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37628 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37629 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37630 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37631 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37632 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37633 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37634 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37635 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37636 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37637 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37686 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37687 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37688 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37689 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37690 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37691 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37692 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37693 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37694 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37695 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37696 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37697 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37698 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37699 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37700 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37701 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37702 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37703 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37704 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37705 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37706 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37707 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37708 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37709 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37713 … 0x010968UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37714 … 0x01096cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37715 … 0x010970UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37717 … 0x010978UL //Access:RW DataWidth:0x3 // If set then record data in…
37718 …set of constraints appear more than once (trigger_state_set_counti >1) then data[32*(trigger_indir…
37719 …set of constraints appear more than once (trigger_state_set_counti >1) then data[32*(trigger_indir…
37720 …set of constraints appear more than once (trigger_state_set_counti >1) then data[32*(trigger_indir…
37724 … 0x010994UL //Access:RW DataWidth:0x20 // If set then the relevant b…
37725 … 0x010998UL //Access:RW DataWidth:0x20 // If set then the relevant b…
37726 … 0x01099cUL //Access:RW DataWidth:0x20 // If set then the relevant b…
37728 … 0x0109a4UL //Access:RW DataWidth:0x3 // If set then record data in…
37729 …set of constraints appear more than once (trigger_state_set_counti >1) then data[32*(trigger_indir…
37730 …set of constraints appear more than once (trigger_state_set_counti >1) then data[32*(trigger_indir…
37731 …set of constraints appear more than once (trigger_state_set_counti >1) then data[32*(trigger_indir…
37735 … 0x0109c0UL //Access:RW DataWidth:0x20 // If set then the relevant b…
37736 … 0x0109c4UL //Access:RW DataWidth:0x20 // If set then the relevant b…
37737 … 0x0109c8UL //Access:RW DataWidth:0x20 // If set then the relevant b…
37739 …- Filter off; in that case all data should be transmitted to the internal buffer without any filte…
37740 …[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be trigge…
37741 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37742 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37743 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37744 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37753 … 0x010a08UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37754 … 0x010a0cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37755 … 0x010a10UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37756 … 0x010a14UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37761 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37762 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37763 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37764 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37793 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37794 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37795 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37796 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37798 … 0x010a7cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37799 … 0x010a80UL //Access:RW DataWidth:0x1 // When set that enables of par…
37800 …cess:RW DataWidth:0x8 // The message length-1 of the recorded part size in terms of numbers o…
37801 …nt: (a) 00 - record from time=0; (b) 01 - record rcrd_on_window_pre_num_chunks chunks to internal…
37802 … (a) 0- enable recording data upon triggering event; in that case record for rcrd_on_window_post_…
37805 … 0x010a98UL //Access:RW DataWidth:0x10 // 16-bit opaque FID for pc…
37815 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37816 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37817 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37818 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37819 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37820 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37821 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37822 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37823 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37824 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37825 …- bits[31:0]; [5:3] - bits[63:32]; [8:6] - bits[95:64]; [11:9] - bits[127:96]; [14:12] - bits…
37826 …ll be added to trailer when STORM will be selected: B2:0 - TSEM; B5:3- MSEM; B8:6- USEM; B11:9- XS…
37835 …0x4 // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 M…
37836 … in granularity of chunks. The allowed range is 1-48 that suits to packet size of 256B-12KB. Value…
37840 …hen tick counter reaches timestamp_tick value. It may be reset from RBC or set to any init value. …
37842 …set and frame[1] is set or bit[1] is set and frame[2] is set or bit[2] is set and frame[3] is set …
37843 …set and valid[1] is set or bit[1] is set and valid[2] is set or bit[2] is set and valid[3] is set …
37844 …ble per SEM block. When set enable stall output from DBG to SEM block as result of trigger event: …
37845 … // Current state machine status of trigger block in dbg_trigger.v: states 0-2 are functional stat…
37846 …ock in dbg_trigger_state.v: : state 0 - NOT_HNDLR_MSG; state 1- FRST_HNDLR_MSG; state 2- SCND_HNDL…
37847 … 0x010b68UL //Access:R DataWidth:0x10 // Counter for number of times set 0 appeared in curre…
37848 … 0x010b6cUL //Access:R DataWidth:0x10 // Counter for number of times set 1 appeared in curre…
37849 …- constraint 0 set0; B1 - constraint 1 set0; B2 - constraint 2 set0; B3 - constraint 3 set0; B4 - …
37851 …DataWidth:0x20 // Debug only: These bits represent the total number of 128-bit cycles sent from …
37855 … status in trailer block : 0 - WAIT_FOR_NEW_LINE; 1- END_OF_CHUNK; 2 - SEND_ADDITIONAL_CHUNK; 3 - …
37857 … // Statistics. Match constraint status. B0 - constraint 0; B1 - constraint 1; B2 - constraint …
37863 …th:0x1 // When set to 0 - only client which HW ID is defined in DBG_REGISTERS_FILTER_ID_NUM.FIL…
37864 …ccess:RW DataWidth:0x1 // When 0 - SEMI core A is selected for all trigger/filter related act…
37873 …set to Low and high again for the next command execution to start; [5:1]: Command: 0: Read; 1: OTP…
37876 …set when PROG ENABLE sequence is issued correctly; [3]: fdone: This signal is set when fout bits a…
37878 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37888 … 0x02021cUL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
37897 … 0x020228UL //Access:RW DataWidth:0x1 // Used for debug, will be set when pll_lock_detec…
37899 …L ref clock termination (default) 1: enable HCSL ref clock termination when pll_ref_oct is set to 1
37908 … 0x020238UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
37909 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37911 … 0x02023cUL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3)…
37949 … 0x020254UL //Access:RW DataWidth:0x1 // Used for debug, will be set when pll_lock_detec…
37957 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
37960 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
37965 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37966 … 0x020264UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
37967 … 0x020268UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
37968 … 0x020268UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
37970 … 0x02026cUL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-2 000000…
37973 … 0x020270UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-3 000000…
37976 … 0x020274UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-4 000000…
37977 …L ref clock termination (default) 1: enable HCSL ref clock termination when pll_ref_oct is set to 1
37979 … 0x020278UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-5 000000…
37984 … 0x020280UL //Access:RW DataWidth:0x1 // Used for debug, will be set when pll_lock_detec…
37986 … 0x020284UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
37988 … 0x020288UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3)…
37991 … 0x02028cUL //Access:R DataWidth:0x4 // Delay for each channel 2-5 is completed.
38003 …Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (def…
38006 …Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (def…
38019 … 0x0202b4UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
38024 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38026 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
38027 …L ref clock termination (default) 1: enable HCSL ref clock termination when pll_ref_oct is set to 1
38030 … 0x0202c8UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38032 … 0x0202ccUL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38033 … 0x0202d0UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
38035 … 0x0202d4UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3)…
38036 …Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (def…
38038 …Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (def…
38044 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38045 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38046 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38048 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38049 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38050 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38052 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38053 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38054 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38073 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38088 … 0x020304UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38089 … 0x0204b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38090 … 0x0202a8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38091 … 0x020308UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38092 … 0x020308UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38093 … 0x0204b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38094 … 0x0202acUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38095 … 0x02030cUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38097 … 0x0204bcUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38098 … 0x0202b0UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38099 … 0x020310UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38100 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38101 … 0x0204c0UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38102 … 0x0202b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38103 … 0x020314UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38104 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38105 … 0x0204c4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38106 … 0x0202b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38107 … 0x020318UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38108 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38109 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38110 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38111 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38117 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38118 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38119 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38120 … 0x020324UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL …
38121 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38122 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38123 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38129 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38130 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38131 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38133 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38134 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38135 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38152 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN go…
38156 … (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# g…
38174 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38178 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
38180 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
38182 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
38184 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
38186 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
38188 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
38190 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
38192 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
38194 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
38196 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
38198 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
38200 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
38202 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
38212 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN go…
38216 … (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# g…
38234 … 0x020344UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38242 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN go…
38246 … (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# g…
38264 … 0x020348UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38268 …set the compliance enable for JTAG pins. the JTAG interface is shared by four masters and there is…
38270 … (0x1<<4) // Set this bit to overrid…
38273 …ss:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_contro…
38274 …ss:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_contro…
38275 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38278 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38279 …am bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist…
38280 …am bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist…
38281 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38282 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38283 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38285 …- bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - re…
38286 …- bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - re…
38288 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38289 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38290 … 0x020364UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL …
38291 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38292 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38294 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38295 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38297 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38298 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38300 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38301 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38303 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38304 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38306 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38307 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38309 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38310 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38312 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38313 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38315 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38316 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38318 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38319 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38321 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38322 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38324 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38325 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38327 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38328 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38329 … 0x020398UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38330 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38331 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38332 … 0x02039cUL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38362 … 0x0203c4UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38363 …ess:RW DataWidth:0x6 // Sets the CTL# (# in [0..5]) I/Os of the PADS in non - scan/mbist modes
38365 … 0x0203c8UL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38366 …cess:RW DataWidth:0x2 // Sets the SL# (# in [0..1]) I/Os of the PADS in non - scan/mbist modes
38368 … 0x0203ccUL //Access:R DataWidth:0x8 // PCIe lock signals. 0-unlocked; 1-locked. Global …
38372 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38373 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38414 …//Access:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the…
38422 …//Access:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the…
38424 …cal 0: Normal Operation Mode 1: Powerdown the RESCAL block Transition from 1->0 to start calibrati…
38429 …-up time before starting calibration 2'b00: 32 refclk = 1.28us 2'b01: 128 refclk = 5.12us 2'b10: 2…
38433 … (0x1<<1) // Indicates if the pon data is valid when calib_done is set 0: Data is invalid …
38435 … On-chip Sheet Resistance 0000 -24% ~ -21% 0001 -21% ~ -18% 0010 -18% ~ -15% 0011 -15% ~ -12% 0100…
38456 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38457 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38458 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38464 … 0x0204e8UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38465 … 0x0204ecUL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38466 … 0x0204f0UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38467 … 0x0204f4UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38468 … 0x0204f8UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38469 … 0x0204fcUL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38470 … 0x020500UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38471 … 0x020504UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38473 … (0x1<<0) // This bit masks, when set, the Parity bit: IP…
38534 …m control, the control set logic is not conditioned with VOQ empty. 1 : For the FSM that drives st…
38536 …set logic is not conditioned with VOQ empty / Interrupt Deasserted / No Pending Interrupt. 1 : For…
38543 …nding VOQ is not empty and the system in the "OBFF" state. If a bit is not set and the correspondi…
38544 …nding VOQ is not empty and the system in the "OBFF" state. If a bit is not set and the correspondi…
38545 …nding VOQ is not empty and the system in the "IDLE" state. If a bit is not set and the correspondi…
38546 …nding VOQ is not empty and the system in the "IDLE" state. If a bit is not set and the correspondi…
38740 …e of 375Mhz, the effective frequency will be 25Mhz. A value >= 2 should be set when using this fea…
38741 …e of 375Mhz, the effective frequency will be 25Mhz. A value >= 2 should be set when using this fea…
38742 …e of 375Mhz, the effective frequency will be 25Mhz. A value >= 2 should be set when using this fea…
38743 …e of 375Mhz, the effective frequency will be 25Mhz. A value >= 2 should be set when using this fea…
39236 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
39251 … (0x1<<0) // This bit masks, when set, the Parity bit: NC…
39253 … (0x1<<1) // This bit masks, when set, the Parity bit: NC…
39255 … (0x1<<2) // This bit masks, when set, the Parity bit: NC…
39263 … (0x1<<2) // 0 -> Send all broadcast packets to the appropriate networ…
39265 … (0x1<<3) // 0 -> Send all multicast packets to the appropriate networ…
39267 … (0x1<<4) // 0 -> only MAC address is used for comparison to detect Host2B…
39269 … (0x1<<5) // 0 -> Do not enable source MAC address learning for packets from…
39271 … (0x1<<6) // 0 -> Entries in SA Learning Cache are valid even after they…
39275 … result in XOFF to be sent out to BMC. Clearing this register after it was set to '1' will cause a…
39279 … (0x1<<10) // 0 -> Select NCSI RMII interface as the MII port …
39281 … (0x1<<11) // 0 -> Select NCSI RMII interface as the Management Po…
39283 … (0x1<<12) // 1 -> When BMB asserts any full condition, drop all the p…
39285 … (0x1<<13) // 1 -> When this bit is set, all pass through traffic will be directed to host, if H…
39287 … 0x040204UL //Access:RW DataWidth:0x1 // When set, this bit indicates…
39289 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39290 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39291 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39292 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39305 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39306 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39307 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39308 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39309 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39310 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39311 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39312 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39313 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39314 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39315 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39316 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39317 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39318 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39319 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39320 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39369 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39370 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39371 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39372 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39373 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39374 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39375 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39376 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39377 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39378 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39379 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39380 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39381 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39382 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39383 …rite MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
39384 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39385 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39386 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39387 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39388 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39389 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39390 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39391 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39392 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39393 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39394 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39395 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39396 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39397 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39398 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39399 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39400 …g cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows…
39418 … 0x040410UL //Access:RW DataWidth:0x1 // When this bit is set, all the entries in…
39422 …-to six TAGs present in a packet. This field sets which of the TAGs need to be removed. This field…
39424 …-> Use the configuration bit associated with the Inner VLAN tag to decide whether to remove the ta…
39426 …packet before sending it out to BMC. it is expected that once a non-zero value is set, all packets…
39434 … (0x1<<0) // Tells HW to set the INS_PROP_HEADER…
39436 … (0x1<<1) // Tells HW to set the INS_OUTER_TAG f…
39438 …HW to set the OVRRIDE_INNER_VLAN flag in the SOP descriptor for a BMC to Network packet if there i…
39440 …o set the OVRRIDE_INNER_VLAN flag in the SOP descriptor for a BMC to Network packet if there is a …
39442 … (0x1<<4) // Tells HW to set the OVRRIDE_PRIORIT…
39445 … (0x7<<0) // This field is used to set the ID of the curre…
39449 … causes the hardware arbitration scheme to be disabled. This bit should be set when there is only …
39451 …to '1' causes the hardware arbitration scheme to begin. Any NCSI port can re-start the arbitration.
39453 …ve the firmware running to be automatically bypassed. Firmware should also set this bit when there…
39457 … (0x1f<<8) // This field is a programmable inter-packet gap for when t…
39465 …mber of Ingress clock cycles that the arbitration master will wait before re-starting the arbitrat…
39484 …started. Setting a value of all 1s in this register will guarantee a store-and-forward operation. …
39499 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
39507 …RW DataWidth:0x1 // Reset the protection override window memory. When set to 1, protection ov…
39510 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39511 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39513 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39514 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39515 …dth:0x1c // Holds the data regarding the last access that caused path isolation interrupt. Bits …
39516 …isolation interrupt. Bits [3:0]: PF. Bits [11:4]: VF. Bit [13:12]: Port. Bits [15:14]: Privilege.…
39517 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39519 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39523 …set by the slave block that the access was targeted for. Bit [4]: slave block privilege (protectio…
39525 …masked, access with the PF is not written to the trace FIFO. BB: only bits 0-7 are applicable. The…
39527 …L = 1. Value of all 1s is applicable and represents VF not valid. BB: only bits 0-6 are applicable.
39528 …sked, access with the port is not written to the trace FIFO. BB: only bits 0-1 are applicable. The…
39530 …_OV. Over-ride to VN PROTECTION. Bit [5]: PDA_OV. Over-ride to PDA PROTECTION. Bit [6]: HV_OV. Ove…
39552 …ERROR (0x1<<3) // Path Isolation error.
39557 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
39559 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
39561 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
39563 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
39565 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
39574 …ON_ERROR (0x1<<3) // Path Isolation error.
39585 …ION_ERROR (0x1<<3) // Path Isolation error.
39590 … (0x1<<0) // This bit masks, when set, the Parity bit: GR…
39592 … (0x1<<1) // This bit masks, when set, the Parity bit: GR…
39605 … (0x7<<2) // Set MAC speed. used to set the core…
39611 …HY while in MAC local loopback; when set to '1'; otherwise transmit to PHY is disabled (normal ope…
39613 …set, frames received by the PHY are transmitted. Received packet by the PHY are Transmitted by the…
39615 … allowed if ignore_tx_pause is not set. When set to '0' (Reset value); the MAC transmit function i…
39617 …// Enable/Disable MAC receive path. When set to '0' (Reset value); the MAC receive function is dis…
39619 …<2) // Set MAC speed. Ignored when the register bit ENA_EXT_CONFIG is set to '1'. When the Registe…
39621 … (0x1<<4) // Enable/Disable MAC promiscuous operation. When asserted (Set to '1'); all frames…
39623 … If enabled (Set to '1'); then padding is removed from the received frame before it is transmitted…
39625 …lication. If disabled (Set to reset value '0') the CRC field is stripped from the frame. Note: If …
39627 …e/Forward Pause Frames. If enabled (Set to '1') pause frames are forwarded to the user application…
39629 …gnore Pause Frame Quanta. If enabled (Set to '1') received pause frames are ignored by the MAC. Wh…
39631 …Set MAC address on transmit. If enabled (Set to '1') the MAC overwrites the source MAC address wit…
39633 …set to '1'; enables half duplex mode; when set to '0'; the MAC operates in full duplex mode. Ignor…
39637 …set; enables Rx FIFO overflow logic. In this case; the RXFIFO_STAT[1] register bit is not operatio…
39639 …X are disabled. Config registers are not affected by sw reset. Write a 0 to de-assert the sw reset.
39641 … (0x1<<14) // Corrupt Tx FCS; on underrun; when set to '1'; No FCS corruption when set to…
39643 … (0x1<<15) // Enable GMII/MII loopback when set to '1'; normal operation when set to…
39645 …HY while in MAC local loopback; when set to '1'; otherwise transmit to PHY is disabled (normal ope…
39647 …set; enables the SW programmed Tx pause capability config bits to overwrite the auto negotiated Tx…
39649 …set; enables the SW programmed Rx pause capability config bits to overwrite the auto negotiated Rx…
39653 …rnal Pins. When set to '0' (Reset value) the Core speed and Mode is programmed with the register b…
39655 …e Enable. When set to '1'; MAC Control frames with any Opcode other than 0x0001 are accepted and f…
39657 … Length Check Disable. When set to '0'; the Core checks the frame's payload length with the Frame …
39659 …// Enable Line Loopback i.e. MAC FIFO side loopback; when set to '1'; normal operation when set to…
39661 …set to '1'; any frame received with an error is discarded in the Core and not forwarded to the Cli…
39665 … // Ignores the back pressure signaling from the system and hence no Tx pause generation; when set.
39667 …set then out-of-band egress flow control is enabled. When this bit is set and input pin ext_tx_flo…
39669 … (0x1<<30) // When set; disable runt filte…
39673 … 0x051014UL //Access:RW DataWidth:0x10 // Defines a 16-Bit maximum frame len…
39674 … 0x051018UL //Access:RW DataWidth:0x10 // 16-Bit value; sets; in i…
39675 …of the EFM preamble between 5 and 15 Bytes. When set to 0; 1; 2; 3 or 4; the Preamble EFM length i…
39689 … (0x1<<5) // Link Status Indication. Set to '0'; when link_status input is low. Se…
39704 …If clear; then subtract the scale_value from the received pause quanta. If set; then add the scale…
39706 …<17) // If set; then receive pause quanta is ignored and a fixed quanta value programmed in SCALE_…
39708 … 0x051054UL //Access:RW DataWidth:0x3 // Set the transmit preamb…
39709 …tween Back-to-Back packets. This is the IPG parameter used exclusively in Full-Duplex mode when tw…
39710 …dth:0x10 // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
39712 … (0x1<<3) // If set; the TX LPI policy …
39714 …i_rx_detect is set whenever the LPI_IDLES are being received on the RX line and Unimac Rx FIFO is …
39718 … (0x1<<6) // When this bit is set and link is establi…
39720 … (0x1<<7) // When set to 1; enables LP_IDLE Prediction. When se…
39722 …the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register…
39723 …the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register…
39725 … 0x051078UL //Access:RW DataWidth:0x1 // Debug status; set if MAC receives an …
39727 …tate when it receives packet for transmission. The decrement unit is 1 micro-second. This register…
39728 …tate when it receives packet for transmission. The decrement unit is 1 micro-second. This register…
39737 … (0x7f<<16) // Non Back-to-Back Transmit IPG pa…
39739 … (0x7f<<24) // Non Back-to-Back Transmit IPG pa…
39757 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
39759 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
39782 … (0x1<<0) // Set the bit 0 (Tx_Launch_en) logic 0; if the tx_launch function is…
39786 …If CRC corruption feature in enabled (TX_CRC_CORUPT_EN set); then in case where this bit when set;…
39790 …ss:RW DataWidth:0x20 // This register contains the bits [31:0] in the 48-bit MAC address. The…
39792 …L_BB (0x1<<0) // Read-only field assertion …
39794 …TY_BB (0x1<<1) // Read-only field assertion …
39798 …s:RW DataWidth:0x10 // This register contains the bits [47:32] in the 48-bit MAC address. The…
39801 … (0xffff<<0) // If set and a Pause frame i…
39803 …5 (0x1<<17) // If set and a Pause frame i…
39807 …Pause time is defined by rf_omac_time_nresume. If rf_omac_time_nresume is set, the chip should co…
39809 …set in a Per Priority Pause frame. Bit 2 is priority 0 and so on. The value of the Pause time is…
39815 …- skipped (unsupported) 1 - stackvlan (unsupported) 2 - carrerr (on by default) 3 - codeerr (on by…
39816 …1 // Flush enable bit to drop out all packets in Tx FIFO without egressing any packets when set.
39817 … 0x051338UL //Access:RW DataWidth:0x8 // probe address bit 7 - U/L bit 6 - GMII/XMGII CLK…
39830 … (0x1<<0) // Enables the PPP-Tx functionality.
39832 … (0x1<<1) // Enables the PPP-Rx functionality.
39836 … (0x1<<4) // When set; MAC pass PFC frame…
39838 …; PFC counters is in full function. Note: it is programming requirement to set this bit when PFC f…
39846 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
39850 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
39852 … (0x1<<1) // This bit masks, when set, the Parity bit: MC…
39854 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
39856 … (0x1<<3) // This bit masks, when set, the Parity bit: MC…
39858 … (0x1<<4) // This bit masks, when set, the Parity bit: MC…
39860 … (0x1<<5) // This bit masks, when set, the Parity bit: MC…
39862 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
39864 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
39866 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
39868 … (0x1<<9) // This bit masks, when set, the Parity bit: MC…
39870 … (0x1<<10) // This bit masks, when set, the Parity bit: MC…
39872 … (0x1<<11) // This bit masks, when set, the Parity bit: MC…
39874 … (0x1<<12) // This bit masks, when set, the Parity bit: MC…
39876 … (0x1<<13) // This bit masks, when set, the Parity bit: MC…
39878 … (0x1<<14) // This bit masks, when set, the Parity bit: MC…
39880 … (0x1<<15) // This bit masks, when set, the Parity bit: MC…
39882 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
39884 … (0x1<<16) // This bit masks, when set, the Parity bit: MC…
39886 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
39888 … (0x1<<1) // This bit masks, when set, the Parity bit: MC…
39890 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
39892 … (0x1<<3) // This bit masks, when set, the Parity bit: MC…
39894 … (0x1<<4) // This bit masks, when set, the Parity bit: MC…
39896 … (0x1<<5) // This bit masks, when set, the Parity bit: MC…
39898 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
39900 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
39902 … (0x1<<9) // This bit masks, when set, the Parity bit: MC…
39904 … (0x1<<11) // This bit masks, when set, the Parity bit: MC…
39954 …5_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
39956 …9_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for mem…
39958 …3_I_ECC_0_PRTY_E5 (0x1<<2) // Set parity only for mem…
39960 …3_I_ECC_1_PRTY_E5 (0x1<<3) // Set parity only for mem…
39962 …3_I_ECC_2_PRTY_E5 (0x1<<4) // Set parity only for mem…
39964 …3_I_ECC_3_PRTY_E5 (0x1<<5) // Set parity only for mem…
39966 …4_I_ECC_0_PRTY_E5 (0x1<<6) // Set parity only for mem…
39968 …4_I_ECC_1_PRTY_E5 (0x1<<7) // Set parity only for mem…
39970 …4_I_ECC_2_PRTY_E5 (0x1<<8) // Set parity only for mem…
39972 …4_I_ECC_3_PRTY_E5 (0x1<<9) // Set parity only for mem…
39974 …1_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
39976 …6_I_ECC_0_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
39978 …6_I_ECC_1_PRTY_BB_K2 (0x1<<2) // Set parity only for mem…
39980 …6_I_ECC_2_PRTY_BB_K2 (0x1<<3) // Set parity only for mem…
39982 …6_I_ECC_3_PRTY_BB_K2 (0x1<<4) // Set parity only for mem…
39984 …7_I_ECC_PRTY_BB_K2 (0x1<<5) // Set parity only for mem…
40032 … (0x1<<0) // This bit masks, when set, the Parity bit: OP…
40034 … (0x1<<1) // This bit masks, when set, the Parity bit: OP…
40036 … (0x1<<2) // This bit masks, when set, the Parity bit: OP…
40038 … (0x1<<3) // This bit masks, when set, the Parity bit: OP…
40040 … (0x1<<4) // This bit masks, when set, the Parity bit: OP…
40042 … (0x1<<5) // This bit masks, when set, the Parity bit: OP…
40044 … (0x1<<6) // This bit masks, when set, the Parity bit: OP…
40046 … (0x1<<7) // This bit masks, when set, the Parity bit: OP…
40048 … (0x1<<8) // This bit masks, when set, the Parity bit: OP…
40050 … (0x1<<9) // This bit masks, when set, the Parity bit: OP…
40052 … (0x1<<10) // This bit masks, when set, the Parity bit: OP…
40056 … DORQ FIFO. When the occupancy is more than that number, local edpm_en is de-asserted. It is than …
40058 … (0x1<<0) // This bit masks, when set, the Parity bit: OP…
40061 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
40063 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
40065 … (0x1<<1) // This bit masks, when set, the Parity bit: PC…
40067 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
40069 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
40071 … (0x1<<3) // This bit masks, when set, the Parity bit: PC…
40073 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
40075 … (0x1<<16) // This bit masks, when set, the Parity bit: PC…
40077 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
40079 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
40081 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
40083 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
40085 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
40087 … (0x1<<1) // This bit masks, when set, the Parity bit: PC…
40089 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
40091 … (0x1<<3) // This bit masks, when set, the Parity bit: PC…
40093 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
40095 … (0x1<<8) // This bit masks, when set, the Parity bit: PC…
40097 … (0x1<<9) // This bit masks, when set, the Parity bit: PC…
40099 … (0x1<<10) // This bit masks, when set, the Parity bit: PC…
40101 … (0x1<<11) // This bit masks, when set, the Parity bit: PC…
40103 … (0x1<<12) // This bit masks, when set, the Parity bit: PC…
40105 … (0x1<<13) // This bit masks, when set, the Parity bit: PC…
40107 … (0x1<<14) // This bit masks, when set, the Parity bit: PC…
40109 … (0x1<<15) // This bit masks, when set, the Parity bit: PC…
40129 …3_I_ECC_PRTY_BB (0x1<<4) // Set parity only for mem…
40131 …3_I_ECC_PRTY_K2_E5 (0x1<<0) // Set parity only for mem…
40133 …4_I_ECC_PRTY_K2_E5 (0x1<<1) // Set parity only for mem…
40135 …1_I_ECC_PRTY_BB (0x1<<0) // Set parity only for mem…
40137 …5_I_ECC_PRTY_BB (0x1<<1) // Set parity only for mem…
40139 …0_I_ECC_PRTY_BB (0x1<<2) // Set parity only for mem…
40141 …9_I_ECC_PRTY_BB (0x1<<3) // Set parity only for mem…
40143 …7_I_ECC_PRTY_BB (0x1<<5) // Set parity only for mem…
40165 …_ENTER (0x1<<2) // Set to enter L1 state.
40167 …REQ (0x1<<3) // Set to request entry to…
40169 …ER_SEND_LTR1 (0x1<<4) // Set to send LTR1.
40171 …ODE_BB (0x1<<0) // Set to enter Root Contr…
40173 …OW_GEN3_BB (0x1<<1) // Set to allow Gen3 mode.
40215 … (0x1<<1) // This bit is set by firmware when ho…
40217 … (0x1<<2) // Set to 1 to indicate that the pcore WakeIn input is active high. Thi…
40219 …TIVEFORCING_K2_E5 (0x1<<3) // Set to 1 to prevent inc…
40270 …OVR_K2_E5 (0x1<<0) // When set to 0, HWInit contro…
40272 …AY_ENABLE_K2_E5 (0x1<<1) // When set to 1, HW delay asse…
40342 …MSG_UNLOCK_K2_E5 (0x1<<16) // One-cycle pulse that indi…
40344 …TURNOFF_K2_E5 (0x1<<17) // One-clock-cycle pulse that i…
40349 … to wake up the PMC state machine from a D1, D2 or D3 power state. Upon wake-up, the core sends a …
40377 …dth:0x2 // Controls the start/end of time based analysis. You must only set the pins to the req…
40415 … 0x054328UL //Access:R DataWidth:0x5 // pm_dev_num[4:0]- Device number
40416 … 0x05432cUL //Access:R DataWidth:0x8 // pm_bus_num[7:0]- Bus Number
40450 … 0x0543b4UL //Access:RC DataWidth:0x1 // Is set to 1 if at least 1 …
40472 … (0x1<<10) // Do not use -- keep mask bit set to 1.
40478 … (0x1<<13) // Non-Fatal Error Message s…
40484 … (0x1<<16) // Vendor-Defined Message recei…
40487 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
40489 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
40491 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
40493 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
40495 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
40497 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
40499 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
40501 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
40503 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
40505 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
40507 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
40509 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
40511 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
40513 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
40515 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
40517 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
40519 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
40542 … (0x1<<10) // Do not use -- keep mask bit set to 1.
40548 …E5 (0x1<<13) // Non-Fatal Error Message s…
40554 … (0x1<<16) // Vendor-Defined Message recei…
40577 … (0x1<<10) // Do not use -- keep mask bit set to 1.
40583 …_E5 (0x1<<13) // Non-Fatal Error Message s…
40589 … (0x1<<16) // Vendor-Defined Message recei…
40592 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
40594 … (0x1<<1) // This bit masks, when set, the Parity bit: PC…
40596 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
40608 …_E5 (0x1<<0) // Power-on reset occurred.
40618 …_2_K2_E5 (0x1<<5) // Non-sticky register reset…
40640 …(0x1<<16) // Soft power-on reset occurred. NOTE: This bit is unreliable for indication of a soft p…
40650 …2_K2_E5 (0x1<<21) // Soft non-sticky register reset…
40658 … (0x1<<3) // This bit masks, when set, the Parity bit: PX…
40660 … (0x1<<0) // This bit masks, when set, the Parity bit: PX…
40662 … (0x1<<1) // This bit masks, when set, the Parity bit: PX…
40664 … (0x1<<13) // This bit masks, when set, the Parity bit: PX…
40666 … (0x1<<2) // This bit masks, when set, the Parity bit: PX…
40668 … (0x1<<4) // This bit masks, when set, the Parity bit: PX…
40670 … (0x1<<3) // This bit masks, when set, the Parity bit: PX…
40672 … (0x1<<4) // This bit masks, when set, the Parity bit: PX…
40674 … (0x1<<5) // This bit masks, when set, the Parity bit: PX…
40676 … (0x1<<6) // This bit masks, when set, the Parity bit: PX…
40678 … (0x1<<7) // This bit masks, when set, the Parity bit: PX…
40680 … (0x1<<2) // This bit masks, when set, the Parity bit: PX…
40682 … (0x1<<8) // This bit masks, when set, the Parity bit: PX…
40684 … (0x1<<8) // This bit masks, when set, the Parity bit: PX…
40686 … (0x1<<9) // This bit masks, when set, the Parity bit: PX…
40688 … (0x1<<10) // This bit masks, when set, the Parity bit: PX…
40690 … (0x1<<11) // This bit masks, when set, the Parity bit: PX…
40692 … (0x1<<12) // This bit masks, when set, the Parity bit: PX…
40694 … (0x1<<13) // This bit masks, when set, the Parity bit: PX…
40696 … (0x1<<14) // This bit masks, when set, the Parity bit: PX…
40698 … (0x1<<15) // This bit masks, when set, the Parity bit: PX…
40700 … (0x1<<16) // This bit masks, when set, the Parity bit: PX…
40702 … (0x1<<17) // This bit masks, when set, the Parity bit: PX…
40704 … (0x1<<18) // This bit masks, when set, the Parity bit: PX…
40706 … (0x1<<19) // This bit masks, when set, the Parity bit: PX…
40708 … (0x1<<0) // This bit masks, when set, the Parity bit: PX…
40710 … (0x1<<20) // This bit masks, when set, the Parity bit: PX…
40712 … (0x1<<9) // This bit masks, when set, the Parity bit: PX…
40714 … (0x1<<21) // This bit masks, when set, the Parity bit: PX…
40718 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
40719 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
40737 … (0x1<<8) // CFC load request FIFO under-run
40741 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40746 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
40748 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
40750 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
40752 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
40754 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
40756 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
40758 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
40760 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
40762 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
40764 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
40766 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
40768 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
40787 …RR (0x1<<8) // CFC load request FIFO under-run
40791 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40812 …ERR (0x1<<8) // CFC load request FIFO under-run
40816 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40821 … (0x1<<0) // This bit masks, when set, the Parity bit: DO…
40824 … (0x1<<0) // This bit masks, when set, the Parity bit: DO…
40826 … (0x1<<1) // This bit masks, when set, the Parity bit: DO…
40828 … (0x1<<2) // This bit masks, when set, the Parity bit: DO…
40830 … (0x1<<1) // This bit masks, when set, the Parity bit: DO…
40832 … (0x1<<3) // This bit masks, when set, the Parity bit: DO…
40834 … (0x1<<4) // This bit masks, when set, the Parity bit: DO…
40836 … (0x1<<5) // This bit masks, when set, the Parity bit: DO…
40838 … (0x1<<6) // This bit masks, when set, the Parity bit: DO…
40840 … (0x1<<7) // This bit masks, when set, the Parity bit: DO…
40842 … (0x1<<2) // This bit masks, when set, the Parity bit: DO…
40844 … (0x1<<8) // This bit masks, when set, the Parity bit: DO…
40846 … (0x1<<3) // This bit masks, when set, the Parity bit: DO…
40848 … (0x1<<9) // This bit masks, when set, the Parity bit: DO…
40850 … (0x1<<4) // This bit masks, when set, the Parity bit: DO…
40852 … (0x1<<10) // This bit masks, when set, the Parity bit: DO…
40854 … (0x1<<5) // This bit masks, when set, the Parity bit: DO…
40856 … (0x1<<11) // This bit masks, when set, the Parity bit: DO…
40859 … 0x100214UL //Access:RW DataWidth:0x1 // Set parity only for mem…
40880 …2 // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 me…
40881 …2 // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 me…
40907 … 0x1004f4UL //Access:RW DataWidth:0x2 // AGG command value in PWM non-DPM mode.
40910 …n 2 port mode it is equal to 0 for all PF-s. In 4 port mode, it is equal to 0 for even PF-s and to…
40911 …eup indication on all ports. This is a per PF per configuration. Should be set in case of coupled …
40912 …/Access:RW DataWidth:0x1 // Enable doorbells for this PF. In case not set the doorbell is sil…
40913 …/Access:RW DataWidth:0x1 // Enable doorbells for this VF. In case not set the doorbell is sil…
40914 …ess:RW DataWidth:0x1 // Enable DPM doorbells for this PF. In case not set the DPM doorbell is…
40915 … DataWidth:0x1 // Enable DPM doorbells for all this PF child VF-s. In case not set the DPM doo…
40929 … 0x100810UL //Access:RW DataWidth:0x1 // If set then CCFC mini-cache is ena…
40931 …and first DPM doorbell appears it is truncated to one entry and aborted; non-first doorbell is dro…
40932 … DPM doorbell appears it is truncated to one entry and DpmAbort flag is set; non-first doorbell is…
40933 … 0x100824UL //Access:RW DataWidth:0x1 // If set, then XCM bypass en…
40934 … 0x100828UL //Access:RW DataWidth:0x1 // If set, then QM bypass ena…
40935 … 0x10082cUL //Access:RW DataWidth:0x1 // If set, then PBF bypass en…
40936 … 0x100830UL //Access:RW DataWidth:0x1 // If set, then QM bypass ena…
40942 …th:0x10 // Tag 1 Ethertype used for packet generation in RoCE EDPM mode. Default is set to SVLAN.
40943 …th:0x10 // Tag 2 Ethertype used for packet generation in RoCE EDPM mode. Default is set to CVLAN.
40944 …dth:0x10 // Tag 3 Ethertype used for packet generation in RoCE EDPM mode. Default is set to TTAG.
40945 …Width:0x10 // Tag 4 Ethertype used for packet generation in RoCE EDPM mode. Default is set to CN.
40946 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40947 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40948 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40949 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40952 …ccess:RW DataWidth:0x20 // Enable bit per each RoCE Opcode 5 LSB-s. N-th bit set means corresp…
40953 …Access:RW DataWidth:0x1 // If 0 - the RoCE CRC-32 final calculation result isn't byte swapped…
40969 … 0x100918UL //Access:RW DataWidth:0x2 // TPH Hint value in case of non-inline L2 EDPM.
40970 … 0x10091cUL //Access:RW DataWidth:0x3 // ATC attribute value of non-inline L2 EDPM.
40972 … 0x100924UL //Access:RW DataWidth:0xe // Maximum non-inline L2 EDPM PktSiz…
40973 … 0x100928UL //Access:RW DataWidth:0x8 // The maximum number of WORD-s which the PBF may a…
40974 … 0x10092cUL //Access:RW DataWidth:0x1 // Set to 1 if IP over NGE…
40975 … 0x100930UL //Access:RW DataWidth:0x1 // Set to 1 if Ethernet ov…
40980 …DataWidth:0xb // Counter of DORQ FIFO entries used by corresponding PF or any of its child VF-s.
40982 … number of DORQ FIFO entries used by corresponding PF or any of its child VF-s. This is a per PF c…
40984 … 0x1009d0UL //Access:RW DataWidth:0x1 // If set, PF doorbell with c…
40985 … 0x1009d4UL //Access:RW DataWidth:0x1 // If set, VF doorbell with c…
40987 …orbell drop reason. If a bit is set (1), then corresponding drop reason will cause attention be se…
40988 …set, DORQ enters freeze mode on the first doorbell drop due to DORQ FIFO overflow. The freeze mode…
40989 … 0x1009e4UL //Access:R DataWidth:0x1 // When set, auto freeze is act…
40990 … 0x1009e8UL //Access:W DataWidth:0x1 // Release the freeze mode set by auto_freeze_en. …
40991 …set, DORQ enters auto drop mode on the first doorbell drop due to DORQ FIFO overflow. In this mode…
40992 … DataWidth:0x1 // When set, auto discard mode is active and all doorbells are dropped at the …
40995 … 0x1009fcUL //Access:R DataWidth:0x20 // Accounts for any non-DPM doorbell or first…
41003 …0 // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_deta…
41004 …-armed by db_drop_details_rel. The following details of the transaction will be recorded: Doorbell…
41005 …7 // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_deta…
41007 …- Size of the data is not equal to 4 or to a multiple of 8 bytes; 1 - 2 LSB-s of the address are n…
41013 …- DPM doorbell and rewind configuration of DPM timer (dpm_timeout) is 0; 1 - PF DPM doorbell and i…
41015 …- DPM doorbell and rewind configuration of DPM timer (dpm_timeout) is 0; 1 - First DPM doorbell an…
41027 … be done at first cycle of first DPM doorbell by the size of DpmSize. No non-first DPM doorbells s…
41032 …ue of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Re…
41034 …-cache was used. 36 - CDU Validation Error; 35 - CFC Load Cancel; 34 - CFC Load Error; 33 - CFC LC…
41039 …Width:0x1 // comment="Selects IEDPM payload endianity. 0 - little endian (lsB first); 1 - big e…
41053 …- DPM FSM state [194:192] - DbAggValSel [191:190] - DbAggCmd [189:182] - DbAggFlgCmd [181] - IEDPM…
41087 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41088 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41089 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41090 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41091 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41092 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41093 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41094 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41095 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41096 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41097 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41098 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41099 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41100 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41101 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41102 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41360 … 0x102b6cUL //Access:RW DataWidth:0x20 // Used to set TCP RTC. Debug only.
41361 … 0x102b70UL //Access:RW DataWidth:0x1 // When set enables RTC increme…
41364 …Access:RW DataWidth:0x1 // If 0 - the iWARP CRC-32 final calculation result isn't byte swappe…
41365 …cess:RW DataWidth:0x20 // Enable bit per each iWARP Opcode 5 LSB-s. N-th bit set means corresp…
41374 …ataWidth:0x4 // Enable special flag indications to affect RDMA RoCE EDPM. Enables when set to 1.
41375 …taWidth:0x4 // Enable special flag indications to affect RDMA iWARP EDPM. Enables when set to 1.
41376 …:RW DataWidth:0x4 // Enable special flag indications to affect L2 EDPM. Enables when set to 1.
41380 …the transaction will be recorded: Doorbell DPM type. 0 - Legacy 1 - RDMA 2 - L2 Inline 3 - L2 Non-…
41385 …- First DPM doorbell does not match DPM global start conditions at CFC load response for Internal …
41387 …- First DPM doorbell does not match DPM global start conditions at CFC load response for Internal …
41388 …-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: IEDPM…
41389 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41390 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41391 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41392 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41394 …- First QWord (offset 0) arives on IEDPM buffer which is not free; 3 - Non-first QWord (offset oth…
41395 …orbell drop reason. If a bit is set (1), then corresponding drop reason will cause attention be se…
41400 … //Access:RW DataWidth:0x1 // The value of UpdPstormEventId flag in PBF command should be set.
41461 …- mapping memory; Bit 1 - SB memory (producer and consumer); Bit 2 - SB interrupt before mask and …
41463 …// If enabled the IGU forwards write/read requests to the TPH interface. 1 - enabled; 0 - disabled.
41465 …ed the IGU allows to VF to send cleanup commands on the int ack address. 1 - enabled; 0 - disabled.
41467 …the IGU allows bypass mode of the rate limiter when the system is empty. 1 - enabled; 0 - disabled.
41470 …L //Access:RW DataWidth:0x1 // Used to enable/disable BIST mode. When set, BIST testing will …
41473 … 0x18006cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
41486 … (0x1<<4) // VFID bit is set and the command is to attention bit set…
41501 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
41503 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
41505 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
41507 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
41509 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
41511 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
41513 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
41515 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
41517 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
41519 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
41521 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
41532 … (0x1<<4) // VFID bit is set and the command is to attention bit set…
41555 … (0x1<<4) // VFID bit is set and the command is to attention bit set…
41570 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41573 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41575 … (0x1<<6) // This bit masks, when set, the Parity bit: IG…
41577 … (0x1<<1) // This bit masks, when set, the Parity bit: IG…
41579 … (0x1<<7) // This bit masks, when set, the Parity bit: IG…
41581 … (0x1<<2) // This bit masks, when set, the Parity bit: IG…
41583 … (0x1<<8) // This bit masks, when set, the Parity bit: IG…
41585 … (0x1<<3) // This bit masks, when set, the Parity bit: IG…
41587 … (0x1<<9) // This bit masks, when set, the Parity bit: IG…
41589 … (0x1<<4) // This bit masks, when set, the Parity bit: IG…
41591 … (0x1<<10) // This bit masks, when set, the Parity bit: IG…
41593 … (0x1<<5) // This bit masks, when set, the Parity bit: IG…
41595 … (0x1<<11) // This bit masks, when set, the Parity bit: IG…
41597 … (0x1<<6) // This bit masks, when set, the Parity bit: IG…
41599 … (0x1<<7) // This bit masks, when set, the Parity bit: IG…
41601 … (0x1<<13) // This bit masks, when set, the Parity bit: IG…
41603 … (0x1<<8) // This bit masks, when set, the Parity bit: IG…
41605 … (0x1<<19) // This bit masks, when set, the Parity bit: IG…
41607 … (0x1<<9) // This bit masks, when set, the Parity bit: IG…
41609 … (0x1<<19) // This bit masks, when set, the Parity bit: IG…
41611 … (0x1<<10) // This bit masks, when set, the Parity bit: IG…
41613 … (0x1<<11) // This bit masks, when set, the Parity bit: IG…
41615 … (0x1<<12) // This bit masks, when set, the Parity bit: IG…
41617 … (0x1<<13) // This bit masks, when set, the Parity bit: IG…
41619 … (0x1<<14) // This bit masks, when set, the Parity bit: IG…
41621 … (0x1<<15) // This bit masks, when set, the Parity bit: IG…
41623 … (0x1<<26) // This bit masks, when set, the Parity bit: IG…
41625 … (0x1<<22) // This bit masks, when set, the Parity bit: IG…
41627 … (0x1<<16) // This bit masks, when set, the Parity bit: IG…
41629 … (0x1<<27) // This bit masks, when set, the Parity bit: IG…
41631 … (0x1<<23) // This bit masks, when set, the Parity bit: IG…
41633 … (0x1<<17) // This bit masks, when set, the Parity bit: IG…
41635 … (0x1<<28) // This bit masks, when set, the Parity bit: IG…
41637 … (0x1<<24) // This bit masks, when set, the Parity bit: IG…
41639 … (0x1<<18) // This bit masks, when set, the Parity bit: IG…
41641 … (0x1<<26) // This bit masks, when set, the Parity bit: IG…
41643 … (0x1<<19) // This bit masks, when set, the Parity bit: IG…
41645 … (0x1<<20) // This bit masks, when set, the Parity bit: IG…
41647 … (0x1<<21) // This bit masks, when set, the Parity bit: IG…
41649 … (0x1<<22) // This bit masks, when set, the Parity bit: IG…
41651 … (0x1<<23) // This bit masks, when set, the Parity bit: IG…
41653 … (0x1<<24) // This bit masks, when set, the Parity bit: IG…
41655 … (0x1<<3) // This bit masks, when set, the Parity bit: IG…
41657 … (0x1<<4) // This bit masks, when set, the Parity bit: IG…
41659 … (0x1<<25) // This bit masks, when set, the Parity bit: IG…
41661 … (0x1<<4) // This bit masks, when set, the Parity bit: IG…
41663 … (0x1<<5) // This bit masks, when set, the Parity bit: IG…
41665 … (0x1<<26) // This bit masks, when set, the Parity bit: IG…
41667 … (0x1<<5) // This bit masks, when set, the Parity bit: IG…
41669 … (0x1<<27) // This bit masks, when set, the Parity bit: IG…
41671 … (0x1<<28) // This bit masks, when set, the Parity bit: IG…
41673 … (0x1<<29) // This bit masks, when set, the Parity bit: IG…
41675 … (0x1<<30) // This bit masks, when set, the Parity bit: IG…
41677 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41679 … (0x1<<1) // This bit masks, when set, the Parity bit: IG…
41681 … (0x1<<1) // This bit masks, when set, the Parity bit: IG…
41683 … (0x1<<2) // This bit masks, when set, the Parity bit: IG…
41685 … (0x1<<2) // This bit masks, when set, the Parity bit: IG…
41687 … (0x1<<3) // This bit masks, when set, the Parity bit: IG…
41689 … (0x1<<7) // This bit masks, when set, the Parity bit: IG…
41691 … (0x1<<9) // This bit masks, when set, the Parity bit: IG…
41693 … (0x1<<8) // This bit masks, when set, the Parity bit: IG…
41695 … (0x1<<10) // This bit masks, when set, the Parity bit: IG…
41697 … (0x1<<11) // This bit masks, when set, the Parity bit: IG…
41699 … (0x1<<12) // This bit masks, when set, the Parity bit: IG…
41701 … (0x1<<14) // This bit masks, when set, the Parity bit: IG…
41703 … (0x1<<15) // This bit masks, when set, the Parity bit: IG…
41705 … (0x1<<14) // This bit masks, when set, the Parity bit: IG…
41707 … (0x1<<16) // This bit masks, when set, the Parity bit: IG…
41709 … (0x1<<15) // This bit masks, when set, the Parity bit: IG…
41711 … (0x1<<17) // This bit masks, when set, the Parity bit: IG…
41713 … (0x1<<18) // This bit masks, when set, the Parity bit: IG…
41715 … (0x1<<20) // This bit masks, when set, the Parity bit: IG…
41717 … (0x1<<21) // This bit masks, when set, the Parity bit: IG…
41719 … (0x1<<29) // This bit masks, when set, the Parity bit: IG…
41721 … (0x1<<25) // This bit masks, when set, the Parity bit: IG…
41723 … (0x1<<30) // This bit masks, when set, the Parity bit: IG…
41725 … (0x1<<27) // This bit masks, when set, the Parity bit: IG…
41727 … (0x1<<12) // This bit masks, when set, the Parity bit: IG…
41729 … (0x1<<16) // This bit masks, when set, the Parity bit: IG…
41731 … (0x1<<17) // This bit masks, when set, the Parity bit: IG…
41733 … (0x1<<18) // This bit masks, when set, the Parity bit: IG…
41735 … (0x1<<22) // This bit masks, when set, the Parity bit: IG…
41737 … (0x1<<23) // This bit masks, when set, the Parity bit: IG…
41739 … (0x1<<24) // This bit masks, when set, the Parity bit: IG…
41741 … (0x1<<25) // This bit masks, when set, the Parity bit: IG…
41745 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41747 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41752 … 0x180224UL //Access:RW DataWidth:0x1 // Set parity only for mem…
41753 … 0x180214UL //Access:RW DataWidth:0x1 // Set parity only for mem…
41754 … 0x180224UL //Access:RW DataWidth:0x1 // Set parity only for mem…
41761 …r of MSI/MSIX/ATTN messages sent for the PF: address 0 - number of MSI/MSIX messages; address 1 - …
41769 …_NUM_MASK_EN (0x1<<9) // Debug: if set the counter is acti…
41771 …Debug: count the number of PXP requests sent on behalf of a specific MSI/MSI-X vector on the SB in…
41775 …SB_NUM_MASK_EN (0x1<<9) // Debug: if set the counter is acti…
41781 …SB_NUM_MASK_EN (0x1<<9) // Debug: if set th counter is activ…
41785 … 0x180600UL //Access:RW DataWidth:0x14 // IPS statistics - number of messages s…
41787 …- function enable; b1 - MSI/MSIX enable; b2 - INT enable; b3 - attention enable; b4 - single ISR m…
41788 …h:0x9 // d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enabl…
41816 …th:0x1 // PF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41818 …th:0x1 // VF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41822 …tion signals leading edge. attn bit condition monitoring; each bit that is set will lock a change …
41823 …ion signals trailing edge. attn bit condition monitoring; each bit that is set will lock a change …
41826 …n vector is 12 bit. If the bit is set to 1, the corresponding bit in the attention vector is enabl…
41827 …set will be masked in the mask bit register). If address = SIMD with mask 32MSB: this register wil…
41828 …r (one in each bit means the appropriate SB is asserted. Every bit that is set will be masked in t…
41829 …- function number: opaque fid. [28:16] - PXP BAR address; [30:29] - Reserved; [31] command type - …
41831 … DataWidth:0x20 // Address 0 - MSI address low (two Lsbit are zero). Address 1 - MSI address hig…
41834 …g is enabled, the match address of the hit response is used to perform a two-cycle …
41836 … read of the entire CAM will be started (or re-started). This will e…
41838 … 0x180864UL //Access:RW DataWidth:0x1 // Enable the RL statistic. 0 - disabled; 1 - enabled.
41844 …MSIX message was sent and write done was not received yet). 0 = clear; 1 = set. The array size is …
41848 … Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in these regist…
41852 …/ Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this regist…
41856 …/ Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this regist…
41860 …/ Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this regist…
41864 …/ Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this regist…
41868 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41869 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41870 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41871 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41872 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41873 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41874 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41875 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41876 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41877 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41878 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41879 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41880 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41881 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41882 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41883 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41884 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41885 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41886 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41887 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41888 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41889 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41890 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41891 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41892 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41893 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41894 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41895 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41896 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41897 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41898 …he appropriate vector in the MSIX table (write zero to all fields except the mask bit that is set).
41899 …UL //Access:RW DataWidth:0x20 // SB interrupt before mask. 0 - prod equal cons. 1 - prod not e…
41901 …UL //Access:RW DataWidth:0x20 // SB interrupt before mask. 0 - prod equal cons. 1 - prod not e…
41902 …UL //Access:RW DataWidth:0x20 // SB interrupt before mask. 0 - prod equal cons. 1 - prod not e…
41903 … 0x180ce0UL //Access:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The b…
41905 … 0x180d00UL //Access:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The b…
41906 … 0x180d04UL //Access:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The b…
41907 …s:RW DataWidth:0x20 // PBA register. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message…
41909 …s:RW DataWidth:0x20 // PBA register. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message…
41910 …s:RW DataWidth:0x20 // PBA register. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message…
41911 …d - sets the max value that the rate_counter can reach; [19:10] tick_interval - define the max int…
41913 …- receives the tick_interval value when reaching zero; or when writing to the tick_interval. The t…
41923 …er - incremented by one when Tick_value reaches zero and decremented whenever a message from that …
41926 …ion and it should keep one of the bits that are set in the previous write (or in the reset value) …
41927 …Tph field for attention message. Bits 8:0 - steering tag; bits 12:9 - reserved; bits 14:13 - st hi…
41928 …miter group enable status bit for groups 0-31. For each bit: 0 - the rate limiter of the group is …
41929 …iter group enable status bit for groups 32-63. For each bit: 0 - the rate limiter of the group is …
41930 …/ Rate Limiter group credit status bit for groups 0-31. For each bit: 0 - the group has no credit.…
41931 … Rate Limiter group credit status bit for groups 32-63. For each bit: 0 - the group has no credit.…
41932 …imiter group pending status bit for groups 0-31. For each bit: 0 - there are no pending SB in that…
41933 …miter group pending status bit for groups 32-63. For each bit: 0 - there are no pending SB in that…
41934 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port0.
41935 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port1.
41936 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port2.
41937 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port3.
41939 …L //Access:R DataWidth:0x5 // Debug: [4] - attention write done message is pending (0-no pen…
41940 …518UL //Access:RW DataWidth:0x1 // Debug only: 0 - FIFO collects 64 first error messages; 1 -…
41942 …set it will collect the data that match to the value in the mask_* register. Masking can be done a…
41958 … (0x1<<9) // Debug: if set the debug informati…
41963 … (0x1<<9) // Debug: if set the debug informati…
41966 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 0; [7:0] = VF number; if PF - [8…
41968 … (0x1<<9) // Debug: if set the debug informati…
41970 …ug information is collected for FID equal to debug_record_mask_fid_num. if set the debug informati…
41975 … (0x1<<4) // Debug: if set the debug informati…
41978 …- MSIX read/write; Bit [1] - PBA read/write; Bit [2] - Producer update (or cleanup command through…
41980 … (0x1<<6) // Debug: if set the debug informati…
41993 … DataWidth:0x18 // Producers only. Address 0-511 match to the mapping memory. Address 512-227:…
41997 …W DataWidth:0x18 // Consumers only. Address 0-511 match to the mapping memory. Address 512-227…
42001 …- valid. [8:1] - vector number (0-128 for PF; 0-63 for VF). [17:9] - FID (if VF: [17] = 0; [16:9] …
42005 …- MSIX message address (bit [1:0] are always zero); [95:64] - MSIX message data; [96] - MSIX mask …
42079 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
42081 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
42083 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
42085 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
42087 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
42089 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
42091 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
42093 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
42095 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
42097 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
42099 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
42102 … (0x1<<1) // This bit masks, when set, the Parity bit: CA…
42104 … (0x1<<0) // This bit masks, when set, the Parity bit: CA…
42106 … (0x1<<2) // This bit masks, when set, the Parity bit: CA…
42108 … (0x1<<1) // This bit masks, when set, the Parity bit: CA…
42110 … (0x1<<3) // This bit masks, when set, the Parity bit: CA…
42112 … (0x1<<2) // This bit masks, when set, the Parity bit: CA…
42114 … (0x1<<4) // This bit masks, when set, the Parity bit: CA…
42116 … (0x1<<3) // This bit masks, when set, the Parity bit: CA…
42118 … (0x1<<3) // This bit masks, when set, the Parity bit: CA…
42120 … (0x1<<5) // This bit masks, when set, the Parity bit: CA…
42122 … (0x1<<4) // This bit masks, when set, the Parity bit: CA…
42124 … (0x1<<5) // This bit masks, when set, the Parity bit: CA…
42126 … (0x1<<4) // This bit masks, when set, the Parity bit: CA…
42128 … (0x1<<6) // This bit masks, when set, the Parity bit: CA…
42130 … (0x1<<5) // This bit masks, when set, the Parity bit: CA…
42132 … (0x1<<7) // This bit masks, when set, the Parity bit: CA…
42134 … (0x1<<10) // This bit masks, when set, the Parity bit: CA…
42136 … (0x1<<11) // This bit masks, when set, the Parity bit: CA…
42138 … (0x1<<8) // This bit masks, when set, the Parity bit: CA…
42140 … (0x1<<11) // This bit masks, when set, the Parity bit: CA…
42142 … (0x1<<12) // This bit masks, when set, the Parity bit: CA…
42144 … (0x1<<9) // This bit masks, when set, the Parity bit: CA…
42146 … (0x1<<0) // This bit masks, when set, the Parity bit: CA…
42148 … (0x1<<6) // This bit masks, when set, the Parity bit: CA…
42150 … (0x1<<8) // This bit masks, when set, the Parity bit: CA…
42152 … (0x1<<7) // This bit masks, when set, the Parity bit: CA…
42154 … (0x1<<9) // This bit masks, when set, the Parity bit: CA…
42156 … (0x1<<8) // This bit masks, when set, the Parity bit: CA…
42158 … (0x1<<10) // This bit masks, when set, the Parity bit: CA…
42160 … (0x1<<9) // This bit masks, when set, the Parity bit: CA…
42162 … (0x1<<12) // This bit masks, when set, the Parity bit: CA…
42184 …_I_ECC_0_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
42186 …_I_ECC_0_PRTY_E5 (0x1<<0) // Set parity only for mem…
42188 …_I_ECC_1_PRTY_BB_K2 (0x1<<2) // Set parity only for mem…
42190 …_I_ECC_1_PRTY_E5 (0x1<<1) // Set parity only for mem…
42192 …_I_ECC_PRTY_K2 (0x1<<3) // Set parity only for mem…
42194 …_I_ECC_PRTY_E5 (0x1<<2) // Set parity only for mem…
42196 …_I_ECC_PRTY_K2 (0x1<<4) // Set parity only for mem…
42198 …_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for mem…
42200 …_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
42244 …N+2/N+1 as part of sb_dma message of command N (Cont00065605 related) When set, bypass can be impl…
42245 … number of outstanding write requests without receiving write done. Values 1-128. Zero is not a va…
42246 …appropriate bit will be clear. [0] - PI memory; [1] - SB var memory; [2]- SB address memory; [3] -…
42247 …p on the written SB number. [8:0] - SB absolute index; [9] - Cleanup set/clr (0-clr; 1 - set); [12…
42251 … 0x1c0600UL //Access:RW DataWidth:0x1 // Indicate the size of the CQE. 0 - 32B; 1 - 64B.
42252 …W DataWidth:0x2 // Indicate the size of the AGG unit. 0 - 64B; 1 - 128B; 2 - 256B; 3 - illega…
42253 … 0x1c0608UL //Access:RW DataWidth:0x1 // Flush all command - will flush all the C…
42255 …ion and it should keep one of the bits that are set in the previous write (or in the reset value) …
42256 …ion and it should keep one of the bits that are set in the previous write (or in the reset value) …
42260 … 0x1c0780UL //Access:R DataWidth:0x20 // Rx timers status. 0 - inactive 1 - active.
42262 … 0x1c0800UL //Access:R DataWidth:0x20 // Tx timers status. 0 - inactive 1 - active.
42266 … 0x1c0980UL //Access:R DataWidth:0x1 // Debug: IGU-CAU request interface…
42267 … 0x1c0984UL //Access:R DataWidth:0x1 // Debug: IGU-CAU command interface…
42293 … type. One bit for each timer command type: [0] - rewind; [1] - clear; [2] - rewind to shorter. Wh…
42311 …- FIFO empty; 1 - FIFO not empty. [0] - PXP command FIFO; [1] - reserved; [2] - timers expiration …
42312 …- error typ (1- read request; 2 - reserved; 3 - sb_index >= CAU_NUM_SB or SB index > CAU_NUM_PI/n…
42313 …- source (0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM)…
42314 …ss:R DataWidth:0xa // Debug; [9] if set data valid; [8] previous FSM_sel; [7:4] - previous s…
42315 … 0x1c0c90UL //Access:R DataWidth:0x1 // Debug: If set a parity occurd and…
42316 …h:0x19 // comment="Debug: [15:0] The PF that caused the error- one bit per PF; [24:16] - SB inde…
42318 …e was writing to agg_units_state_read_en register. (i =0-15). 0 - free; 1 - dirty; 2 - clean; 3 - …
42319 …was writing to agg_units_state_read_en register. (i = 16-31). 0 - free; 1 - dirty; 2 - clean; 3 - …
42320 …was writing to agg_units_state_read_en register. (i = 32-47). 0 - free; 1 - dirty; 2 - clean; 3 - …
42321 …was writing to agg_units_state_read_en register. (i = 48-63). 0 - free; 1 - dirty; 2 - clean; 3 - …
42326 … (0x1<<9) // Debug: if set the debug informati…
42331 … (0x1<<9) // Debug: if set the debug informati…
42334 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 1; [7:0] = VF number; if PF - [8…
42336 … (0x1<<9) // Debug: if set the debug informati…
42338 …formation will be collected for FID equal to debug_record_mask_fid_num. if set he debug informatio…
42343 … (0x1<<4) // Debug: if set the debug informati…
42346 … (0x7<<0) // Debug: command type for the debug. [0] - PI producer update; [1] - cleanup; [2] - …
42348 … (0x1<<3) // Debug: if set the debug informati…
42365 … 0x1c0f0cUL //Access:R DataWidth:0x5 // Debug: FSM state for debug.Idle state value are 0-2
42367 … 0x1c2000UL //Access:WB_R DataWidth:0x80 // Debug: Provides read-only access of the CQ…
42369 … 0x1c2200UL //Access:WB_R DataWidth:0x35 // Debug: Provides read-only access of the IG…
42371 … 0x1c2300UL //Access:WB_R DataWidth:0x62 // Debug: Provides read-only access of the PX…
42373 …2400UL //Access:WB_R DataWidth:0x84 // Debug: Provides read-only access of the PXP write-data FI…
42375 … and PI relative number of each aggregation unit. [0] - valid; [9:1] - absolute SB index; [14:10] …
42377 …- next state; [5:4] - timer cmd (0 - None; 1 - Rewind; 2 - Clear; 3 - Rewind to shorter); [6] - SB…
42379 …-2 only); [49:48] TimerRes1 (This value will determine the TX FSM timer resolution in ticks. Valid…
42387 …ry.[15:0] - protocol producer; [22:16] - PiTimeSet (This value determines the TimeSet that the PI …
42394 …- address; [71:64] - valid slots; [84:72] - FID ([13:9] - PF number (in case of VF the parent PF);…
42396 …h:0x18 // The SB timers. For each SB there are two timers: [11:0] - RX timer; [23:12] - TX timer.
42400 … 0x1f0000UL //Access:RW DataWidth:0x1 // Soft reset - reset all FSM.
42401 …UL //Access:W DataWidth:0x1 // Any write to this register triggers MAC-VLAN Cache initializa…
42402 … 0x1f0008UL //Access:R DataWidth:0x1 // Set when the cache init…
42403 … 0x1f000cUL //Access:RW DataWidth:0x1 // When set to 1 the cam hit pa…
42404 … 0x1f0010UL //Access:RW DataWidth:0x1 // When set to 1 the cam miss p…
42408 … (0x1<<1) // Load Request Mini-cache validation error
42411 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
42413 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
42418 … (0x1<<1) // Load Request Mini-cache validation error
42423 … (0x1<<1) // Load Request Mini-cache validation error
42426 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42428 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
42432 … //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a PF packet, task-id-not…
42433 … //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a VF packet, task-id-not…
42434 … //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a PF packet, task-id-not…
42435 … //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a VF packet, task-id-not…
42442 … 0x1f0190UL //Access:RW DataWidth:0x1 // Per-PF: If set, override of th…
42443 … 0x1f0194UL //Access:RW DataWidth:0x20 // Per-opcode requester/resp…
42444 … 0x1f0198UL //Access:RW DataWidth:0x1 // Per-PF: If set, a load request…
42445 … 0x1f019cUL //Access:RW DataWidth:0x1 // If set, CFC load mini-cache is ena…
42446 … 0x1f01a0UL //Access:RW DataWidth:0x1 // 0-search response initiator type,1-Excha…
42447 … 0x1f01a4UL //Access:RW DataWidth:0x1 // 0-Exchange Context field in the fcoe search req is z…
42450 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42452 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42454 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
42456 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
42458 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42460 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
42462 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42464 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
42466 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
42468 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
42470 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
42472 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
42474 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
42476 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
42478 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
42480 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
42482 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
42484 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
42486 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
42488 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
42490 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
42492 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
42494 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
42496 … (0x1<<30) // This bit masks, when set, the Parity bit: PR…
42498 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
42500 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
42502 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
42504 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
42506 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
42508 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
42510 … (0x1<<26) // This bit masks, when set, the Parity bit: PR…
42512 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
42514 … (0x1<<27) // This bit masks, when set, the Parity bit: PR…
42516 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
42518 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
42520 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
42522 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
42524 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
42526 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
42528 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42530 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
42532 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42534 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
42536 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
42538 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
42540 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
42542 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
42544 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
42546 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42548 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
42550 … (0x1<<25) // This bit masks, when set, the Parity bit: PR…
42552 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
42554 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
42556 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
42558 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
42560 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
42562 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
42564 … (0x1<<29) // This bit masks, when set, the Parity bit: PR…
42566 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
42568 … (0x1<<30) // This bit masks, when set, the Parity bit: PR…
42570 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
42572 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
42574 … (0x1<<24) // This bit masks, when set, the Parity bit: PR…
42576 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
42578 … (0x1<<28) // This bit masks, when set, the Parity bit: PR…
42580 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
42582 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
42584 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
42586 … (0x1<<24) // This bit masks, when set, the Parity bit: PR…
42588 … (0x1<<25) // This bit masks, when set, the Parity bit: PR…
42590 … (0x1<<26) // This bit masks, when set, the Parity bit: PR…
42592 … (0x1<<27) // This bit masks, when set, the Parity bit: PR…
42594 … (0x1<<28) // This bit masks, when set, the Parity bit: PR…
42596 … (0x1<<29) // This bit masks, when set, the Parity bit: PR…
42598 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42600 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
42602 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42604 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
42606 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
42608 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
42610 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
42612 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
42614 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
42616 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
42618 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
42658 …_I_ECC_PRTY_K2 (0x1<<4) // Set parity only for mem…
42660 …_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
42662 …_I_ECC_PRTY_K2 (0x1<<5) // Set parity only for mem…
42664 …_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for mem…
42666 …_I_ECC_PRTY_E5 (0x1<<2) // Set parity only for mem…
42668 …_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for mem…
42670 …_I_ECC_PRTY_E5 (0x1<<4) // Set parity only for mem…
42672 …_I_ECC_PRTY_K2 (0x1<<0) // Set parity only for mem…
42674 …_I_ECC_PRTY_K2 (0x1<<1) // Set parity only for mem…
42676 …_I_ECC_PRTY_K2 (0x1<<2) // Set parity only for mem…
42678 …_I_ECC_PRTY_K2 (0x1<<3) // Set parity only for mem…
42680 …_I_ECC_PRTY_K2 (0x1<<6) // Set parity only for mem…
42682 …_I_ECC_PRTY_K2 (0x1<<7) // Set parity only for mem…
42684 …_I_ECC_PRTY_BB (0x1<<0) // Set parity only for mem…
42686 …_I_ECC_PRTY_BB (0x1<<1) // Set parity only for mem…
42688 …_I_ECC_PRTY_BB (0x1<<2) // Set parity only for mem…
42690 …_I_ECC_PRTY_BB (0x1<<3) // Set parity only for mem…
42693 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42695 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
42697 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42699 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
42701 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42703 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
42705 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
42707 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
42709 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
42711 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
42713 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
42715 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
42717 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
42719 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
42721 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
42723 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
42725 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
42727 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
42729 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
42731 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
42733 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
42735 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
42737 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
42739 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
42741 … (0x1<<24) // This bit masks, when set, the Parity bit: PR…
42743 … (0x1<<25) // This bit masks, when set, the Parity bit: PR…
42745 … (0x1<<26) // This bit masks, when set, the Parity bit: PR…
42747 … (0x1<<27) // This bit masks, when set, the Parity bit: PR…
42749 … (0x1<<28) // This bit masks, when set, the Parity bit: PR…
42751 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
42753 … (0x1<<29) // This bit masks, when set, the Parity bit: PR…
42755 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42757 … (0x1<<30) // This bit masks, when set, the Parity bit: PR…
42759 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42761 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
42763 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42803 … 0x1f0400UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42804 … 0x1f0404UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42805 … 0x1f0408UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42806 … 0x1f040cUL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42838 … 0x1f041cUL //Access:RW DataWidth:0x1 // Per-PF: If set, search request…
42839 … 0x1f0420UL //Access:RW DataWidth:0x1 // Per-PF: Enables VF_ID (if…
42840 … 0x1f0424UL //Access:RW DataWidth:0x1 // Per-PF: Enables load requ…
42842 … 0x1f042cUL //Access:RW DataWidth:0x11 // Per-PF: Max value for tem…
42843 … 0x1f0430UL //Access:RW DataWidth:0x11 // Per-PF: Max value for tem…
42844 … 0x1f0434UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow …
42845 …ss:RW DataWidth:0x1 // Per-PF: Enables openflow search for non-IP packets. Only valid if sear…
42846 … 0x1f043cUL //Access:RW DataWidth:0x1 // Per-PF: If this field is 1, Over-IPv4-prot…
42888 …-PF: Indicates whether to include the Inner VLAN in the search for each protocol. 0 - TCP, 1 - UDP…
42889 …-PF: Indicates whether to include the Outer TAG in the search for each protocol. 0 - TCP, 1 - UDP,…
42890 …-PF: Indicates whether to include Tenant ID (if it exists) in the search for each encapsulation ty…
42891 …o be 0 if the ID matches the default value. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 …
42895 …nant ID used in the search request if Tenant ID exists in the encapsulated T-tag packet.. A zero i…
42896 …capsulated Ethernet over GRE packet and does not match this value the Tenant ID exists bit is set.
42897 …the encapsulated IP over GRE packet and does not match this value the Tenant ID exists bit is set.
42898 …sts in the encapsulated VXLAN packet and does not match this value the Tenant ID exists bit is set.
42899 …e Tenant ID exists in the encapsulated T-Tag packet and does not match this value the Tenant ID ex…
42900 …ataWidth:0x3 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. The T-tag bit of …
42903 …s in the encapsulated ETH NGE packet and does not match this value the Tenant ID exists bit is set.
42904 …ts in the encapsulated IP NGE packet and does not match this value the Tenant ID exists bit is set.
42905 …DataWidth:0x1 // MAC port arbitration guarantees fairness at byte-level (0) or packet-level (1).
42906 … DataWidth:0x1 // Main/LB arbitration guarantees fairness at byte-level (0) or packet-level (1).
42909 … 0x1f0510UL //Access:RW DataWidth:0x8 // Size of inter-packet gap and FCS us…
42910 …-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 traffic; 6-TC6 tra…
42911 …ority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 tr…
42912 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
42913 …bits are for priority 8 client. The clients are assigned the IDs corresponding to their TC # (0-8)
42914 …bits are for priority 8 client. The clients are assigned the IDs corresponding to their TC # (0-8)
42915 …Set these bits to have the round-robin arbiter stays on the winning input instead of moving to the…
42916 … 0x1f052cUL //Access:RW DataWidth:0x1 // Enables pseudo-random round robin ar…
42919 …0x1f0538UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42922 …0x1f0544UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42925 …0x1f0550UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42928 …0x1f055cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42931 …0x1f0568UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42934 …0x1f0574UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42937 …0x1f0580UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42940 …0x1f058cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42943 …0x1f0598UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42946 …0x1f05a4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42949 …0x1f05b0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42952 …0x1f05bcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42955 …0x1f05c8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42958 …0x1f05d4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42961 …0x1f05e0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42964 …0x1f05ecUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42967 …0x1f05f8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42970 …0x1f0604UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42973 …0x1f0610UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42976 …0x1f061cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42979 …0x1f0628UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42982 …0x1f0634UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42985 …0x1f0640UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42988 …0x1f064cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42991 …0x1f0658UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42994 …0x1f0664UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42995 … 0x1f0700UL //Access:RW DataWidth:0x4 // Per-port: Size of the pro…
43005 …in the IPv4 Protocol and IPv6 Next Header fields. Matching can only occur when sctp_enable is set.
43006 …used to designate ICMP in the IPv4 Protocol field. Matching can only occur when icmp_enable is set.
43007 …ataWidth:0x6 // Per-port: Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - V…
43010 … 0x1f073cUL //Access:RW DataWidth:0x10 // Per-PF: Base value used i…
43011 … 0x1f0740UL //Access:RW DataWidth:0x10 // Per-PF: Base value used i…
43026 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
43027 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
43028 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
43029 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
43030 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
43031 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
43032 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
43033 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
43034 … 0x1f079cUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43035 … 0x1f07a0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43036 … 0x1f07a4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43037 … 0x1f07a8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43038 … 0x1f07acUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43039 … 0x1f07b0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43040 … 0x1f07b4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43041 … 0x1f07b8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43046 … 0x1f07ccUL //Access:RW DataWidth:0x20 // Per-PF/Per-port: Destination …
43047 … 0x1f07d0UL //Access:RW DataWidth:0x10 // Per-PF/Per-port: Destination …
43048 … 0x1f07d4UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43049 … 0x1f07d8UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43050 … 0x1f07dcUL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43051 … 0x1f07e0UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43052 … 0x1f07e4UL //Access:RW DataWidth:0x2 // Per-PF: Destination IP address match value - …
43053 … 0x1f07e8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43054 … 0x1f07ecUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43055 … 0x1f07f0UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43056 … 0x1f07f4UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43057 … 0x1f07f8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43058 … 0x1f07fcUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43059 … 0x1f0800UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43060 … 0x1f0804UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43061 … 0x1f0808UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43062 … 0x1f080cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43063 … 0x1f0810UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43064 … 0x1f0814UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43065 … 0x1f0818UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43066 … 0x1f081cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43067 … 0x1f0820UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43068 … 0x1f0824UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43069 … 0x1f0828UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43070 … 0x1f082cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43071 … 0x1f0830UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43072 … 0x1f0834UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43073 … 0x1f0838UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43074 … 0x1f083cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43075 … 0x1f0840UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43076 … 0x1f0844UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43077 … 0x1f0848UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43078 … 0x1f084cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43079 … 0x1f0850UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43080 … 0x1f0854UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43081 … 0x1f0858UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43082 … 0x1f085cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43083 … 0x1f0860UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43084 … 0x1f0864UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43088 … 0x1f0874UL //Access:RW DataWidth:0x1 // Per-port: Flag enabling …
43089 … 0x1f0878UL //Access:RW DataWidth:0x1 // Per-port: Flag to compar…
43093 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43098 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43100 …ch in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg;…
43111 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43113 …ch in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg;…
43126 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43139 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43146 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43156 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43157 … 0x1f093cUL //Access:RW DataWidth:0x4 // Connection type for no-match packets.
43158 … 0x1f0940UL //Access:RW DataWidth:0x4 // Per-port: PFID for no-match packet…
43159 … 0x1f0944UL //Access:RW DataWidth:0x1 // Per-PF: If set, the PFID may be overridden for n…
43160 … 0x1f0948UL //Access:RW DataWidth:0x20 // Per-PF: CID for no-match packets.
43161 … 0x1f094cUL //Access:RW DataWidth:0x9 // Per-PF: LCID for no-match packets.
43169 … 0x1f096cUL //Access:RW DataWidth:0x1 // Per-PF: If set, and PF classif…
43170 …sulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN 2 - NGE
43171 …sulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN 2 - NGE
43172 …ulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN, 2 - NGE
43173 …-PF: Indicates whether to include Tenant ID (if it exists) in the MAC VLAN Cache entry for each en…
43174 …-VLAN Cache Flexible Field. If two blocks are used, this block is used for the upper bytes. 14:11…
43175 …the MAC-VLAN Cache Flexible Field. This block is only used if the number of bytes in mac_vlan_fle…
43178 … 0x1f09d0UL //Access:RW DataWidth:0x1 // Per-PF: If set, the SACK block…
43179 …set, RoCE building block data is FIFOed on all non-FCoE packets. This allows Over-L2-Raw Part2 to …
43180 … 0x1f09d8UL //Access:RW DataWidth:0x20 // Per-PF: Mask used in RDMA…
43189 … 0x1f09fcUL //Access:RW DataWidth:0x1 // Per-PF: Enables SYN cooki…
43190 … 0x1f0a00UL //Access:RW DataWidth:0x1 // Per-PF: If set, enables iWarp.
43191 …1 // Per-PF: If set, 4B for Ethernet CRC is included in Packet Length for Statistics field. For…
43192 …-PF: For each bit set, the length of the corresponding tag in the inner header will be subtracted …
43193 …-PF: For each bit set, the length of the corresponding tag in the first header will be subtracted …
43194 … 0x1f0a10UL //Access:RW DataWidth:0x1 // Per-Port: If set and classifica…
43195 … 0x1f0a14UL //Access:RW DataWidth:0x8 // Per-Port: If classification failed, for each bit …
43196 … 0x1f0a18UL //Access:RW DataWidth:0x9 // Per-Port: If classification failed, for each bit …
43197 … 0x1f0a1cUL //Access:RW DataWidth:0x20 // Per-PF: This value is passed to the per-PF …
43198 … 0x1f0a20UL //Access:RW DataWidth:0x2 // Per-Port: This value goes…
43199 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 0. In …
43200 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 0. In 4…
43201 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 1. In …
43202 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 1. In 4…
43203 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 2. In …
43204 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 2. In 4…
43205 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 3. In …
43206 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 3. In 4…
43207 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 4. In …
43208 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 4. In 4…
43209 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 5. In …
43210 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 5. In 4…
43211 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 6. In …
43212 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 6. In 4…
43213 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 7. In …
43214 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 7. In 4…
43215 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 8. In 4…
43216 …0x1f0a68UL //Access:RW DataWidth:0x3 // bit 0 - ignore for VXLAN, bit 1 - ignore for NGE, bit…
43233 …-port): Packet available status of the main and loopback queues of each traffic class, before bein…
43234 …dth:0x18 // Debug only (per-port): STORM backpressure status (blocked priorities) Each set bit r…
43236 …ue of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Re…
43238 …f0b68UL //Access:R DataWidth:0xd // Debug only: In the case of a mini-cache LCID validation…
43266 …kts sent to TCM: Reserved - 127:66, Parsing and Error flags - 65:50, Start block - 49:37, Priority…
43300 …L //Access:RW DataWidth:0x1 // Used to enable/disable BIST mode. When set, BIST testing will …
43303 … 0x1f0f8cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
43307 …set the values of the GFT profile mask ram. line #31 must be configured before enabling the GFT si…
43309 …set the values of the GFT profile cam: 0 �valid, zero at reset 1-14 data 14-11 PF ID (3bit BB 4bit…
43324 …ld the priority field in the GFT used frame fields inner header 0- use CVLAN priority 1- use SVLAN…
43325 …d the priority field in the GFT used frame fields tunnel header 0- use CVLAN priority 1- use SVLAN…
43326 … 0x1f11bcUL //Access:RW DataWidth:0x1 // Per-PF: Enables gft searc…
43327 …/Access:RW DataWidth:0x1 // Per-PF: Enables gft search for non-IP packets. Only valid if sear…
43328 … equal to this value, use the CM_HDR_GFT intead of CM_HDR_EVENT_ID_X in the CM header. is also set.
43332 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43336 … 0x1f11ccUL //Access:RW DataWidth:0x1 // When set to 1 the gft cam hi…
43337 … 0x1f11d0UL //Access:RW DataWidth:0x1 // When set to 1 the gft cam mi…
43340 …s_ipv4_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
43341 …s_ipv6_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
43342 …s_ipv4_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
43481 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43489 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43497 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43505 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43513 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43521 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43529 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43537 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43544 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43551 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43558 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43565 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43572 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43579 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43586 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43593 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43597 … list of building blocks in TSTORM message for connection type 0. Unused blocks must be set to 0xf.
43598 …ed list of building blocks in PTLD message for connection type 0. Unused blocks must be set to 0xf.
43599 … list of building blocks in TSTORM message for connection type 0. Unused blocks must be set to 0xf.
43600 …ed list of building blocks in PTLD message for connection type 0. Unused blocks must be set to 0xf.
43601 … list of building blocks in TSTORM message for connection type 1. Unused blocks must be set to 0xf.
43602 …ed list of building blocks in PTLD message for connection type 1. Unused blocks must be set to 0xf.
43603 … list of building blocks in TSTORM message for connection type 1. Unused blocks must be set to 0xf.
43604 …ed list of building blocks in PTLD message for connection type 1. Unused blocks must be set to 0xf.
43605 … list of building blocks in TSTORM message for connection type 2. Unused blocks must be set to 0xf.
43606 …ed list of building blocks in PTLD message for connection type 2. Unused blocks must be set to 0xf.
43607 … list of building blocks in TSTORM message for connection type 2. Unused blocks must be set to 0xf.
43608 …ed list of building blocks in PTLD message for connection type 2. Unused blocks must be set to 0xf.
43609 … list of building blocks in TSTORM message for connection type 3. Unused blocks must be set to 0xf.
43610 …ed list of building blocks in PTLD message for connection type 3. Unused blocks must be set to 0xf.
43611 … list of building blocks in TSTORM message for connection type 3. Unused blocks must be set to 0xf.
43612 …ed list of building blocks in PTLD message for connection type 3. Unused blocks must be set to 0xf.
43613 … list of building blocks in TSTORM message for connection type 4. Unused blocks must be set to 0xf.
43614 …ed list of building blocks in PTLD message for connection type 4. Unused blocks must be set to 0xf.
43615 … list of building blocks in TSTORM message for connection type 4. Unused blocks must be set to 0xf.
43616 …ed list of building blocks in PTLD message for connection type 4. Unused blocks must be set to 0xf.
43617 … list of building blocks in TSTORM message for connection type 5. Unused blocks must be set to 0xf.
43618 …ed list of building blocks in PTLD message for connection type 5. Unused blocks must be set to 0xf.
43619 … list of building blocks in TSTORM message for connection type 5. Unused blocks must be set to 0xf.
43620 …ed list of building blocks in PTLD message for connection type 5. Unused blocks must be set to 0xf.
43621 … list of building blocks in TSTORM message for connection type 6. Unused blocks must be set to 0xf.
43622 …ed list of building blocks in PTLD message for connection type 6. Unused blocks must be set to 0xf.
43623 … list of building blocks in TSTORM message for connection type 6. Unused blocks must be set to 0xf.
43624 …ed list of building blocks in PTLD message for connection type 6. Unused blocks must be set to 0xf.
43625 … list of building blocks in TSTORM message for connection type 7. Unused blocks must be set to 0xf.
43626 …ed list of building blocks in PTLD message for connection type 7. Unused blocks must be set to 0xf.
43627 … list of building blocks in TSTORM message for connection type 7. Unused blocks must be set to 0xf.
43628 …ed list of building blocks in PTLD message for connection type 7. Unused blocks must be set to 0xf.
43629 …ed list of building blocks in PTLD message for connection type 8. Unused blocks must be set to 0xf.
43630 …ed list of building blocks in PTLD message for connection type 8. Unused blocks must be set to 0xf.
43631 …ed list of building blocks in PTLD message for connection type 9. Unused blocks must be set to 0xf.
43632 …ed list of building blocks in PTLD message for connection type 9. Unused blocks must be set to 0xf.
43633 …d list of building blocks in PTLD message for connection type 10. Unused blocks must be set to 0xf.
43634 …d list of building blocks in PTLD message for connection type 10. Unused blocks must be set to 0xf.
43635 …d list of building blocks in PTLD message for connection type 11. Unused blocks must be set to 0xf.
43636 …d list of building blocks in PTLD message for connection type 11. Unused blocks must be set to 0xf.
43637 …d list of building blocks in PTLD message for connection type 12. Unused blocks must be set to 0xf.
43638 …d list of building blocks in PTLD message for connection type 12. Unused blocks must be set to 0xf.
43639 …d list of building blocks in PTLD message for connection type 13. Unused blocks must be set to 0xf.
43640 …d list of building blocks in PTLD message for connection type 13. Unused blocks must be set to 0xf.
43641 …d list of building blocks in PTLD message for connection type 14. Unused blocks must be set to 0xf.
43642 …d list of building blocks in PTLD message for connection type 14. Unused blocks must be set to 0xf.
43643 …d list of building blocks in PTLD message for connection type 15. Unused blocks must be set to 0xf.
43644 …d list of building blocks in PTLD message for connection type 15. Unused blocks must be set to 0xf.
43648 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43661 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43674 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43685 … 0x1f169cUL //Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on TCP 4 tuple. 0- p…
43686 … 0x1f16a0UL //Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on UDP 4 tuple. 0- p…
43706 …UL //Access:RW DataWidth:0x1 // Burst mode enabled. Set this bits to have the main round-rob…
43707 … 0x1f16f4UL //Access:RW DataWidth:0x1 // enable event_id to be set as ipv6_ext_event_id
43713 …rom TX to RX. This loopback is on the line side after clock domain crossing - from the last TX pip…
43715 …om TX to RX. This loopback is on the core side before clock domain crossing - from the first TX pi…
43717 …om RX to TX. This loopback is on the line side before clock domain crossing - from the first RX pi…
43719 …rom RX to TX. This loopback is on the core side after clock domain crossing - from the last RX pip…
43725 … (0x1<<8) // If set; during either of t…
43727 … (0x1<<9) // If set; during either of t…
43729 … (0x1<<10) // Resets the RS layer functionality - fault handling.
43731 … (0x1<<11) // If set; this will override the one column idle/sequence ordered set check…
43733 … (0x1<<12) // Link status indication from Software. If set; indicates that lin…
43740 … (0x1<<3) // If set; exclude the SOP by…
43775 … (0x1<<1) // True to allow any non-Idle character to sta…
43779 … (0x1<<3) // If set; the MAC checks for IEEE Ethernet format premable - K.SOP + 5 '55' prema…
43783 … (0x1<<11) // If set; the minimum receive packet size is reduced to 18 bytes from …
43785 …LE_BB (0x1<<12) // If set; the MAC parses the…
43805 … (0x1<<2) // If set; the TX faults inputs are used to send out fault sequences - else …
43809 …CAL_FAULT_BB (0x1<<4) // If set; the transmit data …
43811 …MOTE_FAULT_BB (0x1<<5) // If set; the transmit data …
43813 …NK_INTERRUPT_BB (0x1<<6) // If set; the transmit data …
43815 …_TIMERS_ON_LINK_DOWN_BB (0x1<<7) // If set; the Receive LPause…
43825 … (0x1<<0) // A rising edge on this register bit (0->1); clears the stick…
43827 … (0x1<<1) // A rising edge on this register bit (0->1); clears the stick…
43829 … (0x1<<2) // A rising edge on this register bit (0->1); clears the stick…
43832 …<<0) // This field is Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
43834 …BB (0x1<<16) // If set; enables the pause …
43842 …LINE_SIDE_BB (0x1<<20) // If set; the recive pause i…
43844 …use_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
43846 …use_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
43848 … (0xffff<<0) // Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
43850 …xffff<<16) // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
43853 … (0x1<<0) // Enable automatic re-send of PFC packet af…
43857 … (0x1<<2) // Set to pass RX PFC fram…
43859 … (0x1<<3) // Set to enable increment…
43874 … (0x1<<2) // When set; LLFC is inserted o…
43876 … (0x1<<3) // When set and llfc_in_ipg_only =0; GXPORT operates in …
43878 … (0x1<<4) // This bit if set to 1; disables the …
43880 … (0x1<<5) // When set; LLFC crc calculati…
43905 … (0x1<<2) // The crc check for HCFC messages is ignored if this bit is set.
43907 … (0x1<<3) // When set; HCFC CRC calculati…
43928 …dicates the link status used by XMAC EEE. This is continuously updated. If set; indicates that lin…
43931 … (0x1<<0) // A rising edge on this register bit (0->1); clears the stick…
43933 … (0x1<<1) // A rising edge on this register bit (0->1); clears the stick…
43935 … (0x1<<2) // A rising edge on this register bit (0->1); clears the stick…
43937 … (0x1<<3) // A rising edge on this register bit (0->1); clears the stick…
43939 … (0x1<<4) // A rising edge on this register bit (0->1); clears the stick…
43941 … (0x1<<5) // A rising edge on this register bit (0->1); clears the stick…
43943 … (0x1<<6) // A rising edge on this register bit (0->1); clears the stick…
43955 …XOFF_BB (0x1<<1) // If set; EEE FSM can go to …
43957 …FF_BB (0x1<<2) // If set; EEE FSM can go to …
43959 …ACTIVE_BB (0x1<<3) // If set; EEE FSM can go to …
43967 …transitioning to ACTIVE state. This is in terms of micro seconds. Default value is set to 1 second.
43971 … (0x1<<16) // When set to 1; enables LP_IDLE Prediction. When se…
43973 … (0x1<<17) // When set to 1; GMII interfac…
43976 …H_EN_BB (0x1<<0) // If set; each data frame is…
43980 … (0x1<<2) // In CRC corruption mode; if this bit is set; replaces computed …
43985 … 0x210130UL //Access:RW DataWidth:0x10 // XMAC IP Version ID - corresponds to RTL/D…
44007 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44017 …ata path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX data…
44019 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44027 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44037 …ata path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX data…
44039 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44047 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44057 …ata path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX data…
44059 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44079 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44089 …ata path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX data…
44091 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44101 …1<<0) // This regiseter enables loopback mode (used for debug) 0 - loopback inactive 1 - loopback …
44107 … (0x1<<0) // Set to 1 for masking in…
44109 … (0x1<<1) // Set to 1 for masking cr…
44111 … (0x1<<2) // Set to 1 for masking de…
44113 …K2_E5 (0x1<<3) // Set to 1 for masking fi…
44115 … (0x1<<4) // Set to 1 for masking re…
44117 …E5 (0x1<<5) // Set to 1 for masking vl…
44119 …ASMIT_K2_E5 (0x1<<6) // Set to 1 for masking vl…
44121 …AN_K2_E5 (0x1<<7) // Set to 1 for masking vl…
44153 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
44155 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
44157 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
44159 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
44161 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
44163 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
44165 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
44167 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
44169 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
44171 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
44173 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
44175 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
44250 … 0x218228UL //Access:RW DataWidth:0x1 // This register is used to set the value of NWM lp…
44255 … (0x1<<1) // This bit masks, when set, the Parity bit: CN…
44257 … (0x1<<0) // This bit masks, when set, the Parity bit: CN…
44262 …B (0x1<<0) // If set overrides hardware …
44264 …<<4) // If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LE…
44266 … (0x1<<8) // Port0: If set along with the LED_…
44268 … (0x1<<12) // This bit is set to enable the use o…
44270 …nk cycle (on + off) for Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field i…
44274 … // Led mode: 0 -> MAC; 1-3 -> PHY1; 4 -> MAC2; 5-7 -> PHY4; 8 -> MAC3; 9 -…
44275 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44276 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44277 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44280 …-> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused Th…
44283 … corresponding Physical function. 0 -> NW0 connects to PF0 1 -> NW0 connects to PF1 2 -> NW0 co…
44285 … corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connects to PF1 2 -> NW1 co…
44287 … corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1 2 -> NW2 co…
44289 … corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1 2 -> NW3 co…
44292 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44294 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44296 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44298 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44299 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44300 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44301 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44302 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44303 …UL //Access:RW DataWidth:0x1 // When set, PMIF block uses values in following registers to co…
44304 … 0x21827cUL //Access:RW DataWidth:0x4 // These bits are used to set which NIG Ports are…
44307 …G port is assigned to each PMEG Port. [1:0] -- PMEG Port 0 [3:2] -- PMEG Port 1 [5:4] -- PMEG Port…
44308 …G port is assigned to each PMFC Port. [1:0] -- PMFC Port 0 [3:2] -- PMFC Port 1 [5:4] -- PMFC Port…
44309 …set the number of active ports on PMEG. The value in this register is added to the PMEG Port ID ev…
44310 …set the number of active ports on PMFC. The value in this register is added to the PMFC Port ID ev…
44368 … 0x218320UL //Access:RW DataWidth:0x1 // This register is used to set the value of cnig_p…
44369 … 0x218324UL //Access:RW DataWidth:0x1 // This register is used to set the value of cnig_p…
44370 … 0x218328UL //Access:RW DataWidth:0x1 // This register is used to set the value of PMFC l…
44371 … 0x21832cUL //Access:RW DataWidth:0x1 // This register is used to set the value of PMEG l…
44374 …ports 0,2 and should be used for 100G or 2x50G NW modes. Bit 0 - port0 CRC enable. Bit 1 - port2 C…
44375 …ports 0,2 and should be used for 100G or 2x50G NW modes. Bit 0 - port0 CRC enable. Bit 1 - port2 C…
44376 …pted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - por…
44377 …pted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - por…
44399 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44401 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44403 … (0x1<<7) // End of packet error on M-Storm command interfa…
44405 … (0x1<<8) // End of packet error on U-Storm command interfa…
44408 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
44410 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
44412 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
44414 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
44416 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
44418 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
44420 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
44422 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
44424 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
44426 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
44428 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
44445 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44447 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44449 … (0x1<<7) // End of packet error on M-Storm command interfa…
44451 … (0x1<<8) // End of packet error on U-Storm command interfa…
44468 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44470 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44472 … (0x1<<7) // End of packet error on M-Storm command interfa…
44474 … (0x1<<8) // End of packet error on U-Storm command interfa…
44477 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
44480 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
44482 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
44484 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
44486 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
44488 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
44490 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
44492 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
44494 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
44496 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
44498 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
44500 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
44502 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
44504 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
44506 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
44508 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
44510 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
44512 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
44514 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
44516 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
44518 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
44520 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
44522 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
44524 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
44526 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
44528 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
44530 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
44532 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
44534 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
44536 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
44538 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
44540 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
44542 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
44544 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
44546 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
44548 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
44550 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
44552 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
44554 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
44556 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
44558 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
44560 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
44562 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
44564 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
44566 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
44568 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
44570 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
44572 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
44574 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
44576 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
44578 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
44580 … (0x1<<24) // This bit masks, when set, the Parity bit: PR…
44582 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
44584 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
44586 … (0x1<<25) // This bit masks, when set, the Parity bit: PR…
44588 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
44590 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
44592 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
44594 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
44596 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
44598 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
44600 … (0x1<<3) // This bit masks, when set, the Parity bit: PR…
44602 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
44630 …_I_ECC_PRTY_K2_E5 (0x1<<0) // Set parity only for mem…
44632 …_I_ECC_PRTY_BB (0x1<<0) // Set parity only for mem…
44634 …_I_ECC_PRTY_K2_E5 (0x1<<1) // Set parity only for mem…
44636 …_I_ECC_PRTY_BB (0x1<<1) // Set parity only for mem…
44638 …_I_ECC_PRTY_K2_E5 (0x1<<2) // Set parity only for mem…
44640 …_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for mem…
44642 …_I_ECC_PRTY_K2 (0x1<<3) // Set parity only for mem…
44644 …_I_ECC_PRTY_BB (0x1<<2) // Set parity only for mem…
44646 …_I_ECC_PRTY_BB (0x1<<3) // Set parity only for mem…
44670 … 0x230420UL //Access:RW DataWidth:0x10 // Provides the value of the 16-bit pad that will be …
44671 … 0x230424UL //Access:RW DataWidth:0x1 // When set, this bit enables t…
44673 … Initial credit to be used on the RDIF command interface for regular (non-pass-through) requests. …
44674 …on the RDIF command interface for pass-through requests. This value defines the maximum number of …
44678 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
44679 …th:0x9 // Defines the number of occupied entries required in the PXP read-response FIFO before …
44680 … DataWidth:0x20 // Statistics counter provides a count of the number of M-Storm comands that ha…
44681 … DataWidth:0x20 // Statistics counter provides a count of the number of U-Storm comands that ha…
44710 … 0x232000UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the M-Storm comma…
44712 … 0x232400UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the U-Storm comma…
44714 … 0x232800UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the BR…
44716 … 0x232c00UL //Access:R DataWidth:0x7 // Provides read-only access of the BR…
44718 … 0x233000UL //Access:WB_R DataWidth:0x2c // Provides read-only access of the ta…
44720 … 0x233400UL //Access:R DataWidth:0x11 // Provides read-only access of the pa…
44722 … 0x233600UL //Access:R DataWidth:0xb // Provides read-only access of the PB…
44724 … 0x233800UL //Access:WB_R DataWidth:0x100 // Provides read-only access of the PR…
44726 … 0x233c00UL //Access:R DataWidth:0x8 // Provides read-only access of the PXP write-done re…
44742 … (0x1<<19) // If set; same search shortc…
44744 … (0x1<<20) // If set; search return no m…
44760 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
44773 … 0x238480UL //Access:RW DataWidth:0x10 // Per-PF Bitmask for inclus…
44774 … 0x238484UL //Access:RW DataWidth:0x8 // Per-StringType Bitmask fo…
44775 …1 // IF Stats Enable Bit. IF Stat Counters only count when this bit is set. This bit is cl…
44812 …his register will initialize all rows of RSS memory to zeros.It will be be set to 0 when init will…
44813 … 0x238808UL //Access:R DataWidth:0x1 // This register will be set when init procedure…
44873 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
44875 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
44877 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
44879 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
44881 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
44883 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
44885 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
44887 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
44889 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
44891 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
44893 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
44895 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
44897 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
44899 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
44901 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
44903 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
44905 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
44907 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
44909 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
44911 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
44913 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
44915 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
45008 … (0x1<<0) // This bit masks, when set, the Parity bit: RS…
45010 … (0x1<<1) // This bit masks, when set, the Parity bit: RS…
45012 … (0x1<<2) // This bit masks, when set, the Parity bit: RS…
45014 … (0x1<<3) // This bit masks, when set, the Parity bit: RS…
45016 … (0x1<<4) // This bit masks, when set, the Parity bit: RS…
45018 … (0x1<<5) // This bit masks, when set, the Parity bit: RS…
45020 … (0x1<<0) // This bit masks, when set, the Parity bit: RS…
45022 … (0x1<<1) // This bit masks, when set, the Parity bit: RS…
45024 … (0x1<<2) // This bit masks, when set, the Parity bit: RS…
45026 … (0x1<<3) // This bit masks, when set, the Parity bit: RS…
45042 …_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
45044 …_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for mem…
45046 …_I_ECC_PRTY_E5 (0x1<<2) // Set parity only for mem…
45048 …_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for mem…
45050 …_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
45052 …_I_ECC_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
45076 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45077 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45078 …0x20 // Debug register. FIFO empty status: {b15:8 - inp_fifo_counter; b7:6- cmd_fifo_couter; b5:…
45079 …ster. State of each state machine {b15:12 - calc_cur_state; b11:8 - main_cur_state;b7:4 - msg_cur_…
45208 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
45210 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
45212 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
45214 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
45216 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
45218 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
45220 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
45222 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
45224 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
45265 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
45286 …ived on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
45324 … 0x23e000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
45331 …x4 // Page size in L2P table for CDU-Task module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-51…
45332 … // Page size in L2P table for CDU module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45333 …4 // Page size in L2P table for TM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45334 …4 // Page size in L2P table for QM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45335 … // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45336 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45337 … // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45338 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45339 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45346 … 0x240048UL //Access:RW DataWidth:0xe // First memory address base for cdu-connection in ILT.
45347 … 0x24004cUL //Access:RW DataWidth:0xe // Last memory address base for cdu-connection in ILT.
45348 … 0x240050UL //Access:RW DataWidth:0xe // First memory address base for cdu-task in ILT.
45349 … 0x240054UL //Access:RW DataWidth:0xe // Last memory address base for cdu-task in ILT.
45387 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45391 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45393 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45395 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45397 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45403 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45405 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45407 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45409 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45411 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45413 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45422 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
45424 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
45426 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
45428 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
45430 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
45432 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
45434 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
45436 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
45438 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
45440 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
45442 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
45444 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
45446 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
45448 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
45450 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
45452 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
45454 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
45456 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
45461 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45465 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45467 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45469 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45471 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45477 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45479 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45481 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45483 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45485 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45487 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45498 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45502 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45504 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45506 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45508 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45514 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45516 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45518 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45520 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45522 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45524 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45533 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
45535 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
45537 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
45539 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
45541 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
45543 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
45545 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
45547 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
45549 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
45551 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
45553 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
45555 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
45557 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
45559 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
45561 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
45563 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
45565 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
45567 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
45569 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
45571 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
45573 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
45575 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
45600 …001_I_ECC_PRTY_BB (0x1<<1) // Set parity only for mem…
45602 …001_I_ECC_PRTY_K2 (0x1<<2) // Set parity only for mem…
45604 …001_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
45606 …002_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for mem…
45608 …003_I_ECC_PRTY_E5 (0x1<<2) // Set parity only for mem…
45610 …004_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
45612 …005_I_ECC_PRTY_K2 (0x1<<1) // Set parity only for mem…
45634 …W DataWidth:0x3 // Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010:…
45635 …RW DataWidth:0x3 // Max burst size filed for read requests port 0; 000 - 128B; 001:256B; 010:…
45638 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45639 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45653 …DataWidth:0x8 // Initial value of global counter; This value MUST be 256 - sum of all clients t…
46001 … 0x2406a0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ5 Read- currently not used.
46104 … (0xf<<0) // Indicates the number of credits for read sub-requests in th reques…
46106 … (0x1f<<4) // Indicates the number of credits for write sub-requests in th reques…
46111 … 0x240724UL //Access:RW DataWidth:0x5 // Sets which vq head pointer to see out of queues 0-31.
46112 … 0x240728UL //Access:RW DataWidth:0x5 // Sets which vq tail pointer to see out of queues 0-31.
46114 … 0x240730UL //Access:RW DataWidth:0x1 // When set the new alignment m…
46146 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46147 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46148 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46149 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46150 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46151 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46152 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46153 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46154 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46155 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46156 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46157 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46158 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46159 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46160 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46161 …set - SR from the VQ can send ATC lookup request to the ATC (assuming all other conditions are met…
46162 …ss:RW DataWidth:0x2 // ATC enable values per PF as follows: b0 - PF enable; b1 - VF enable; P…
46163 …ues of rq_atc_internal_ats_enable as follows: b0 - PF0; b1 - VF0; b2 - PF1; b3 - VF1; b30 - PF15 ;…
46164 …set means that SR of the matched VQ will be always sent to the GLUE with the at_valid=1 indication…
46166 … 0x240800UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46167 … 0x240804UL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i…
46168 … 0x240808UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46169 … 0x24080cUL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i…
46170 … 0x240810UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46171 … // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ…
46175 …set - assert ilt fail interrupt (rq_elt_addr) in case working in ilt mode and onchip translation f…
46176 …vqid; in order to read from the hoq ram the read enable register should be set as well (rq_hoq_ram…
46177 …ss:RW DataWidth:0x1 // FOR DBG: enable reading from the hoq ram; when set hoq rbc read is ena…
46178 …/ FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1…
46182 … //Access:R DataWidth:0x20 // FOR DBG: bit 0 relaxed ordering; bit 1 no-snoop; bits 5:2 clien…
46183 … 0x240844UL //Access:R DataWidth:0x20 // The total number of WR SR-s that were sent to t…
46184 … 0x240848UL //Access:R DataWidth:0x20 // The total number of RD SR-s that were sent to t…
46185 … 0x24084cUL //Access:R DataWidth:0x20 // The number of PBF RD SR-s that were sent to t…
46186 … 0x240850UL //Access:R DataWidth:0x20 // The number of USDM-DP WR SR-s that were sent …
46187 … 0x240854UL //Access:R DataWidth:0x20 // The number of TREQ SR-s that were sent to t…
46188 … 0x240858UL //Access:R DataWidth:0x20 // The number of ICPL SR-s that were sent to t…
46189 …20 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46190 …9 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46191 …20 // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46192 …c // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46193 …0x20 // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46194 …0xc // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46195 …:0x20 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46196 …:0x9 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46197 … // Counting window mode. 0 - manual window: counting is manually being initiated & stopped by t…
46200 …en working in manual window mode (i.e. Sr_cnt_window_mode = 0). 0 - stop counting. 1 - start count…
46202 …global window counter). 0 - start counting upon any first SR that is sent to the PGLUE. 1 - start …
46205 …atus of the SR count mechanism: 0 - idle: ready to start new counting. 1 - ongoing: counting is cu…
46206 … 0x2408a0UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46207 … 0x2408a4UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46208 … 0x2408a8UL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46209 …dth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client …
46210 … 0x2408b0UL //Access:R DataWidth:0x9 // bit 8-0: srid.
46211 … 0x2408b4UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46212 … 0x2408b8UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46213 … 0x2408bcUL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46214 … DataWidth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15…
46215 … 0x2408c4UL //Access:R DataWidth:0xa // b1-0: atc code; b2: wdone type; b4-3: endianity; …
46243 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46244 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46245 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46246 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46247 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46255 … 0x240924UL //Access:RW DataWidth:0x2 // In case this register is set, requests belongs t…
46258 …l2p_vf_err or rq_elt_addr interrupt. [12:0] - Length in bytes. [16:13] - PFID. [17] - VF_VALID. …
46259 …:16] client ID. [21] - Error type - 0 - rq_l2p_vf_err; 1 - rq_elt_addr. [22] - w_nr - 0 - read; 1 …
46261 …:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must be big…
46263 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46264 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46265 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46266 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46267 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46268 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46269 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46270 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46271 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46272 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46273 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46274 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46275 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46276 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46277 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46278 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46279 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46280 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46281 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46282 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46283 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46284 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46285 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46286 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46287 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46288 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46289 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46290 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46291 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46294 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46295 … 0x2409c4UL //Access:R DataWidth:0x9 // Debug only: The SR counter - number of unused sub…
46328 …0x240a48UL //Access:R DataWidth:0xa // Debug only: The blocks counter - number of unused blo…
46391 … 0x240b44UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46392 … 0x240b48UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46393 … 0x240b4cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46394 … 0x240b50UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46395 … 0x240b54UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46396 … 0x240b58UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46397 … 0x240b5cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46398 … 0x240b60UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46399 … 0x240b64UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46400 … 0x240b68UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46401 … 0x240b6cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46402 … 0x240b70UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46403 … 0x240b74UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46404 … 0x240b78UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46405 … 0x240b7cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46406 … 0x240b80UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46407 … 0x240b84UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46408 … 0x240b88UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46409 … 0x240b8cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46410 … 0x240b90UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46411 … 0x240b94UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46412 … 0x240b98UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46413 … 0x240b9cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46414 … 0x240ba0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46415 … 0x240ba4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46416 … 0x240ba8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46417 … 0x240bacUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46418 … 0x240bb0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46419 … 0x240bb4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46420 … 0x240bb8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46421 … 0x240bbcUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46422 … 0x240bc0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46430 … 0 - the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW count…
46431 …- the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters…
46432 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46433 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46434 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46435 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46436 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46437 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46438 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46439 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46440 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46441 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46442 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46443 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46444 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46445 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46446 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46447 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46448 …-PGLUE request interface write credit; 0 - no more credit for wr SR-s (i.e. write SR-s cannot be s…
46449 …-PGLUE request interface read credit; 0 - no more credit for rd SR-s (i.e. read SR-s cannot be sen…
46450 …set it will only enable to submit a write request when eop arrived. This can be a workaround for p…
46451 …-1] between qc_cmg_add_2_q (indication that new request is written into hoq0) and cmg_qc_del_head …
46452 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46453 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46454 … 0x240c40UL //Access:R DataWidth:0xe // For debug and Idle-check use. The value …
46456 …ite done for them from the PGLUE). Upon reaching the threshold no more wr SR-s will be sent by the…
46491 … 0x240cd4UL //Access:RW DataWidth:0x9 // If bit is set, client can push re…
46492 … 0x240cd8UL //Access:RW DataWidth:0x9 // If bit is set, client can push re…
46493 … 0x240cdcUL //Access:RW DataWidth:0x9 // If bit is set, client can push re…
46494 … 0x240ce0UL //Access:RW DataWidth:0x9 // If bit is set, client can push re…
46495 … 0x240ce4UL //Access:RW DataWidth:0x9 // If bit is set, client can push re…
46496 … 0x240ce8UL //Access:RW DataWidth:0x9 // If bit is set, client can push re…
46497 … 0x240cecUL //Access:RW DataWidth:0x7 // If bit is set, client can push re…
46513 … // Page size in L2P table for tgsrc module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
46514 … // Page size in L2P table for RGSRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
46552 …5 // Internal lookup table for logical to physical address translation. Re-instantiated in E4 du…
46614 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
46616 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
46618 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
46620 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
46622 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
46624 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
46626 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
46628 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
46630 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
46632 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
46634 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
46636 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
46638 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
46640 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
46642 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
46644 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
46646 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
46648 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
46650 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
46652 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
46654 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
46656 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
46658 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
46755 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
46772 …- TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM; 5 - PSDM; 6 - QM; 7 - TM; 8 - SRC; 9 - DMAE; 10 - …
46773 …- TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM; 5 - PSDM; 6 - QM; 7 - TM; 8 - SRC; 9 - DMAE; 10 - …
46827 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
46829 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
46831 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
46833 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
46835 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
46837 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
46839 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
46841 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
46843 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
46845 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
46847 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
46849 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
46851 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
46853 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
46855 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
46857 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
46859 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
46861 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
46863 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
46944 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
46948 …- client ID. [7:5] - (sum1[5:3] + 1) or (sum1[5:4] + 1) according to the definition in the spec. […
46956 …0x29b068UL //Access:RW DataWidth:0x7 // If Number of entries in the PRM-secondary internal fi…
46957 … 0x29b06cUL //Access:R DataWidth:0x7 // Current internal PRM-secondary fill level …
46958 … 0x29b070UL //Access:R DataWidth:0x7 // Maximum internal PRM-secondary fill level …
46996 … the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the…
47005 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
47007 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
47009 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
47011 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
47013 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
47015 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
47017 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
47019 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
47021 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
47023 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
47025 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
47027 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
47029 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
47031 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
47033 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
47035 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
47037 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
47039 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
47041 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
47043 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
47045 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
47047 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
47086 … the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the…
47131 … the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the…
47140 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47143 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47145 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47147 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47149 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47151 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47153 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47155 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47157 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47159 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47161 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47163 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47165 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47167 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47169 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47171 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47173 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47175 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47177 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47179 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47181 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47183 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47185 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47187 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47189 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47191 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47193 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47195 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47197 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47199 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47201 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47203 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47205 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47207 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47209 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47211 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47213 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47215 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47217 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47219 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47221 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47223 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47225 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47227 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47229 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47231 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47233 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47235 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47237 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47239 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47241 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47243 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47245 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47247 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47249 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47251 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47253 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47255 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47257 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47259 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47261 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47263 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47266 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47268 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47270 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47272 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47274 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47276 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47278 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47280 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47282 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47284 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47286 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47288 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47290 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47292 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47294 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47296 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47298 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47300 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47302 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47304 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47306 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47308 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47310 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47312 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47314 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47316 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47318 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47320 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47322 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47324 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47326 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47328 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47330 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47332 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47334 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47336 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47338 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47340 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47342 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47344 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47346 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47348 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47350 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47352 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47354 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47356 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47358 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47360 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47362 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47364 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47366 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47368 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47370 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47372 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47374 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47376 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47378 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47380 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47382 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47384 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47386 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47388 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47391 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47393 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47395 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47397 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47399 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47401 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47403 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47405 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47407 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47409 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47411 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47413 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47415 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47417 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47419 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47421 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47423 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47425 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47427 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47429 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47431 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47433 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47435 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47437 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47439 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47441 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47443 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47445 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47447 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47449 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47451 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47453 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47455 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47457 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47459 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47461 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47463 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47465 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47467 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47469 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47471 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47473 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47475 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47477 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47479 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47481 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47483 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47485 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47487 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47489 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47491 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47493 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47495 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47497 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47499 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47501 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47503 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47505 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47507 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47509 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47511 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47513 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47516 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47518 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47520 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47522 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47524 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47526 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47528 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47530 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47532 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47534 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47536 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47538 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47540 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47542 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47544 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47546 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47548 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47550 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47552 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47554 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47556 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47558 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47560 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47562 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47564 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47566 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47568 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47570 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47572 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47574 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47576 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47578 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47580 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47582 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47584 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47586 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47588 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47590 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47592 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47594 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47596 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47598 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47600 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47602 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47604 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47606 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47608 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47610 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47612 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47614 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47616 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47619 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47621 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47623 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47625 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47627 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47629 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47631 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47633 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47635 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47637 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47639 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47641 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47643 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47658 …008_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
47660 …009_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for mem…
47662 …_ECC_PARITY_ONLY_0_BB_K2 (0x1<<0) // Set parity only for mem…
47694 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
47696 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
47698 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
47715 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47719 …ue is the one expected in idle check except for the Timers VQ (VQ3). This register is for VQs 0-23.
47725 …a. Arrowhead: The reset value of 1 should not be changed. It can cause Xs on the outputs - CQ79817.
47727 …-block until end of packet. Note that the override may start a few cycles before or after the last…
47729 …uest with error on receive side: [15:0] - Echo ID. [28:16] - sub-request length minus 1. [29] - fi…
47730 …ils of first request with error on receive side: [4:0] - VQ ID. [9:5] - client ID. [10] - valid - …
47737 …e is the one expected in idle check except for the Timers VQ (VQ3). This register is for VQs 24-31.
47764 …han this Number of entries are used in the clock synchronization FIFO; it de-asserts the 'almost f…
47766 …this Number of entries are used in the CDU clock synchronization FIFO; it de-asserts the 'almost f…
47768 …this Number of entries are used in the PBF clock synchronization FIFO; it de-asserts the 'almost f…
47770 …han this Number of entries are used in the clock synchronization FIFO; it de-asserts the 'almost f…
47772 … 0x29d144UL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47773 … 0x29d148UL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47774 … 0x29d14cUL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47775 … 0x29d150UL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47779 … 0x29d160UL //Access:R DataWidth:0x8 // Per-client maximum sync F…
47792 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
47794 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
47796 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
47798 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
47800 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
47825 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47828 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47830 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47832 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47834 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47836 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47838 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47840 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47842 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47844 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47846 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47848 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47850 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47852 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47854 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47856 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47858 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47860 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47862 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47864 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47866 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47868 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47870 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47872 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47874 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47876 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47878 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47880 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47882 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47884 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47886 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47888 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47890 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47892 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47894 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47896 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47898 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47900 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47902 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47904 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47906 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47908 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47910 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47912 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47914 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47916 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47918 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47920 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47922 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47924 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47926 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47928 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47930 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47932 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47934 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47936 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47938 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47940 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47942 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47944 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47946 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47948 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47951 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47953 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47955 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47957 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47959 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
47961 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47963 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47965 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
48025 …020_I_ECC_PRTY_BB_K2 (0x1<<3) // Set parity only for mem…
48027 …020_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
48029 …021_I_ECC_PRTY_BB_K2 (0x1<<4) // Set parity only for mem…
48031 …021_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for mem…
48033 …022_I_ECC_PRTY_BB_K2 (0x1<<5) // Set parity only for mem…
48035 …022_I_ECC_PRTY_E5 (0x1<<2) // Set parity only for mem…
48037 …023_I_ECC_PRTY_BB_K2 (0x1<<6) // Set parity only for mem…
48039 …023_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for mem…
48041 …024_I_ECC_PRTY_BB_K2 (0x1<<7) // Set parity only for mem…
48043 …024_I_ECC_PRTY_E5 (0x1<<4) // Set parity only for mem…
48045 …025_I_ECC_PRTY_BB_K2 (0x1<<8) // Set parity only for mem…
48047 …025_I_ECC_PRTY_E5 (0x1<<5) // Set parity only for mem…
48049 …026_I_ECC_PRTY_E5 (0x1<<6) // Set parity only for mem…
48051 …027_I_ECC_PRTY_E5 (0x1<<7) // Set parity only for mem…
48053 …028_I_ECC_PRTY_E5 (0x1<<8) // Set parity only for mem…
48055 …018_I_ECC_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
48057 …018_I_ECC_PRTY_E5 (0x1<<9) // Set parity only for mem…
48059 …01_I_ECC_PRTY_E5 (0x1<<10) // Set parity only for mem…
48061 …017_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
48063 …019_I_ECC_PRTY_BB_K2 (0x1<<2) // Set parity only for mem…
48065 …015_I_ECC_PRTY_BB_K2 (0x1<<9) // Set parity only for mem…
48121 …:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must be big…
48124 … 0 - The delivery port continues delivering the next PBF request only if the second delivery port …
48169 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
48171 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
48173 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
48175 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
48177 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
48202 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
48212 …ter-engine indicating if the engine is idle. Idle means the engine is not sending request (and the…
48213 …- pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 P…
48214 … 0x2a0060UL //Access:R DataWidth:0x1 // 1 - An error request is …
48216 …- RSV [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM…
48217 …idth:0x7 // The data of the first incorrect access. the format is: [6:0] - length in DWs. The d…
48218 … 0x2a0070UL //Access:R DataWidth:0x1 // 1 - An incorrect access …
48220 … 0x2a0078UL //Access:R DataWidth:0x1 // 1- permission violation…
48226 …te source that consumed more than its allowed credits. the format is: [3:0] - client (0 TSDM; 1 MS…
48227 … 0x2a0094UL //Access:R DataWidth:0x1 // 1 - A source credit viol…
48233 … 0x2a00acUL //Access:R DataWidth:0x1 // 1 - PSWHST is in drain m…
48235 …- length in DWs; [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - cli…
48236 … 0x2a00b8UL //Access:R DataWidth:0x1 // 1 - An hst timeout data …
48238 …interface. PSWHST issues an attention if more credits are consumed. Added in BB-B0 due to pipeline.
48283 …ATC (so access is dropped). The disabled vf registers are valid when it is set and reset when the …
48287 …rect access registers. The incorrect access registers are valid when it is set and reset when the …
48302 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
48304 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
48306 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
48308 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
48310 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
48312 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
48314 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
48316 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
48318 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
48320 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
48322 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
48324 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
48326 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
48328 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
48330 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
48332 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
48334 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
48336 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
48357 …ATC (so access is dropped). The disabled vf registers are valid when it is set and reset when the …
48361 …rect access registers. The incorrect access registers are valid when it is set and reset when the …
48394 …ATC (so access is dropped). The disabled vf registers are valid when it is set and reset when the …
48398 …rect access registers. The incorrect access registers are valid when it is set and reset when the …
48413 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
48416 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
48418 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
48420 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
48422 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
48424 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
48426 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
48428 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
48430 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
48432 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
48434 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
48436 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
48438 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
48440 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
48442 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
48444 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
48446 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
48448 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
48451 …und interrupts memory. E4 entry structure: [15:0] - CompParams. [23:16] - EventID. [24] - T. [28:2…
48490 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48513 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
48515 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
48517 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
48519 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
48521 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
48523 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
48525 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
48527 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
48529 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
48531 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
48533 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
48535 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
48537 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
48539 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
48541 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
48543 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
48545 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
48547 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
48549 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
48551 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
48553 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
48555 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
48557 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
48559 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
48588 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48637 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48660 … (0x1<<0) // This bit masks, when set, the Parity bit: PG…
48663 … (0x1<<0) // This bit masks, when set, the Parity bit: PG…
48665 … (0x1<<4) // This bit masks, when set, the Parity bit: PG…
48667 … (0x1<<1) // This bit masks, when set, the Parity bit: PG…
48669 … (0x1<<2) // This bit masks, when set, the Parity bit: PG…
48671 … (0x1<<3) // This bit masks, when set, the Parity bit: PG…
48673 … (0x1<<5) // This bit masks, when set, the Parity bit: PG…
48675 … (0x1<<4) // This bit masks, when set, the Parity bit: PG…
48677 … (0x1<<5) // This bit masks, when set, the Parity bit: PG…
48679 … (0x1<<6) // This bit masks, when set, the Parity bit: PG…
48681 … (0x1<<7) // This bit masks, when set, the Parity bit: PG…
48683 … (0x1<<8) // This bit masks, when set, the Parity bit: PG…
48685 … (0x1<<10) // This bit masks, when set, the Parity bit: PG…
48687 … (0x1<<9) // This bit masks, when set, the Parity bit: PG…
48689 … (0x1<<11) // This bit masks, when set, the Parity bit: PG…
48691 … (0x1<<10) // This bit masks, when set, the Parity bit: PG…
48693 … (0x1<<6) // This bit masks, when set, the Parity bit: PG…
48695 … (0x1<<11) // This bit masks, when set, the Parity bit: PG…
48697 … (0x1<<12) // This bit masks, when set, the Parity bit: PG…
48699 … (0x1<<13) // This bit masks, when set, the Parity bit: PG…
48701 … (0x1<<7) // This bit masks, when set, the Parity bit: PG…
48703 … (0x1<<14) // This bit masks, when set, the Parity bit: PG…
48705 … (0x1<<8) // This bit masks, when set, the Parity bit: PG…
48707 … (0x1<<15) // This bit masks, when set, the Parity bit: PG…
48709 … (0x1<<9) // This bit masks, when set, the Parity bit: PG…
48711 … (0x1<<16) // This bit masks, when set, the Parity bit: PG…
48713 … (0x1<<0) // This bit masks, when set, the Parity bit: PG…
48715 … (0x1<<17) // This bit masks, when set, the Parity bit: PG…
48717 … (0x1<<18) // This bit masks, when set, the Parity bit: PG…
48719 … (0x1<<19) // This bit masks, when set, the Parity bit: PG…
48721 … (0x1<<20) // This bit masks, when set, the Parity bit: PG…
48723 … (0x1<<21) // This bit masks, when set, the Parity bit: PG…
48725 … (0x1<<22) // This bit masks, when set, the Parity bit: PG…
48727 … (0x1<<1) // This bit masks, when set, the Parity bit: PG…
48729 … (0x1<<23) // This bit masks, when set, the Parity bit: PG…
48731 … (0x1<<12) // This bit masks, when set, the Parity bit: PG…
48733 … (0x1<<24) // This bit masks, when set, the Parity bit: PG…
48735 … (0x1<<13) // This bit masks, when set, the Parity bit: PG…
48737 … (0x1<<25) // This bit masks, when set, the Parity bit: PG…
48739 … (0x1<<14) // This bit masks, when set, the Parity bit: PG…
48741 … (0x1<<26) // This bit masks, when set, the Parity bit: PG…
48743 … (0x1<<15) // This bit masks, when set, the Parity bit: PG…
48745 … (0x1<<27) // This bit masks, when set, the Parity bit: PG…
48747 … (0x1<<16) // This bit masks, when set, the Parity bit: PG…
48749 … (0x1<<28) // This bit masks, when set, the Parity bit: PG…
48751 … (0x1<<17) // This bit masks, when set, the Parity bit: PG…
48753 … (0x1<<29) // This bit masks, when set, the Parity bit: PG…
48755 … (0x1<<18) // This bit masks, when set, the Parity bit: PG…
48757 … (0x1<<30) // This bit masks, when set, the Parity bit: PG…
48759 … (0x1<<19) // This bit masks, when set, the Parity bit: PG…
48761 … (0x1<<20) // This bit masks, when set, the Parity bit: PG…
48763 … (0x1<<21) // This bit masks, when set, the Parity bit: PG…
48766 … (0x1<<0) // This bit masks, when set, the Parity bit: PG…
48768 … (0x1<<1) // This bit masks, when set, the Parity bit: PG…
48770 … (0x1<<2) // This bit masks, when set, the Parity bit: PG…
48783 …- for Atomic Op / MRD handling of NPH credits. 0 - Can send both if there is one NPH credit and th…
48787 … (0x1<<0) // 0 - Debug bus is not output to RBCN_e0. 1 - …
48789 … (0x1<<1) // 0 - Debug bus is not output to RBCN_e1. 1 - …
48806 … (0x1<<9) // This bit give strict priority to read over write on the PGL read-write arbiter.
48809 …was blocked because of bus_master_en was deasserted. Bit 1: Added in BigBear-B0. Indicates that cu…
48810 …was blocked because of bus_master_en was deasserted. Bit 1: Added in BigBear-B0. Indicates that cu…
48820 …- Target memory read arrived with a correctable error. Bit 1 - Target memory read arrived with an …
48835 …UL //Access:RW DataWidth:0x1 // Debug only: 0 - PCIe checksum is generated towards PCIe core.…
48839 …:0x5 // Pseudo VF target mode configuration that controls the size of each pseudo-VF in the BAR.
48841 … to accesss DORQ via BAR0: 0-disable access; 1-enable access if BAR0 size is 128K; 2-enable acces…
48842 … 0x2a84ecUL //Access:RW DataWidth:0x9 // VSC fields: bit 0 - enable VSC; bits 1-8 - VSC reser…
48858 …-PF region. Addresses 0x0 - 0x5c: 12 per-PF PF windows. Each PF window contains two 32-bit values.…
48860 …region. 0x0 - 0x3c8 (0x200 - 0x5c8) - 243 global windows. Each entry is the 12-bit window offset.…
48862 …ister on which config space A attention is generated. Note that this register is in 128-byte units.
48863 …arting in address cfg_space_a_address generates an attention. If bit N is set - a CSSNOOP cycle wi…
48864 …ister on which config space B attention is generated. Note that this register is in 128-byte units.
48865 …arting in address cfg_space_b_address generates an attention. If bit N is set - a CSSNOOP cycle wi…
48866 …it indicates that the corresponding PF generates config space A attention. Set by PXP. Reset by MC…
48867 …est register. Note: register contains bits from both paths. Note: Need to re-read the enabled regi…
48868 …it indicates that the corresponding PF generates config space B attention. Set by PXP. Reset by MC…
48869 …est register. Note: register contains bits from both paths. Note: Need to re-read the enabled regi…
48870 …1. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by …
48871 …3. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by …
48872 …5. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by …
48873 …7. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by …
48874 …9. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by …
48875 …1. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by …
48876 …3. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by …
48877 …5. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by …
48878 …s. Each bit indicates that the FLR register of the corresponding PF was set. Set by PXP. Reset by …
48891 …ABLED_REQUEST (0x1<<1) // Debug only: When 1 SR-IOV disbaled request …
48893 …ble register of the corresponding PF is written to 0 and was previously 1. Set by PXP. Reset by MC…
48904 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48905 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48906 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48907 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48908 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48909 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48910 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48911 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48912 …- Shadow bits clear for PFs 0 to 31. MCP writes 1 to a bit in this register in order to reset the…
48922 …th:0x10 // Shadow vf_enable register for all PFs. Each bit indicates if SR-IOV for the correspon…
48924 … bit for the corresponding PF is set. [31:16] : Each bit indicates if IDO_CPL_ENABLE bit for the c…
48926 …- Reserved. Bit 1 - Reserved. Bit 2 - Reserved. Bit 3 - Reserved. Bit 4 - Completion with Configur…
48927 … there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MC…
48928 … there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MC…
48929 … there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MC…
48930 … there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MC…
48931 … there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MC…
48932 … there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MC…
48933 … there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MC…
48934 … there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MC…
48935 … there was a completion with uncorrectable error for the corresponding PF. Set by PXP. Reset by MC…
48945 …- PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of …
48946 …- PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of …
48949 …ot submitted due to error. [4:0] VQID. [17:5] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. …
48950 …- Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indica…
48953 …QID. [5] TREQ. 1 - Indicates the request is a Translation Request. [18:6] - Length in bytes. [19] …
48954 …- Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indica…
48955 …- PFID. [11:4] - VFID. [12] - VF_VALID. [17:13] - ITAG Index. [21:18] - Error type - [18] - Indic…
48956 …68UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-VF for master and tar…
48957 …6cUL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for master transac…
48958 …70UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target write t…
48959 …74UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target read tr…
48968 …pfid_enable registers for target flow. Bits [15:0] - internal_pfid_enable_target_write; Bits [31:1…
48969 … global view of internal_pfid_enable registers for master flow. Bits [15:0] - internal_pfid_enable…
49000 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49001 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49002 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49003 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49004 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49005 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49006 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49007 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49008 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49009 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49010 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49011 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49012 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49013 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49014 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49015 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49016 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49017 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49018 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49019 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49020 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49021 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49022 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49023 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49024 … 0x2aa318UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49025 … 0x2aa31cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49026 … 0x2aa320UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49027 … 0x2aa324UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49028 … 0x2aa328UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49029 … 0x2aa32cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49030 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49031 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49032 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49033 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49034 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49035 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49036 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49037 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49038 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49039 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49040 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49041 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49042 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49043 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49044 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49045 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49046 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49047 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49048 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49049 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49050 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49051 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49052 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49053 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49054 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49055 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49056 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49057 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49058 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49059 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49060 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49061 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49062 …R0. [12:0] Address in DWs (bits [14:2] of byte address). [14:13] BAR. [22:15] VFID. [26:23] - PFID.
49063 …st with length violation (too many DWs) accessing BAR0. [5:0] - Length in DWs. [6] valid - indica…
49064 …ermission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. [23:16] VFID. [27:24] - PFID. [28…
49065 …- clears INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears TX_ERR_WR_ADD_31_0 T…
49066 … //Access:RW DataWidth:0x20 // Each bit when set indicates that IDO bit towards PGLUE should b…
49067 …3c4UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates that IDO bit towards PGLUE shou…
49068 …3c8UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates that IDO bit towards PGLUE shou…
49069 …ess:RW DataWidth:0x1 // 1 - Do not discard IGU master transactions for PF when the correspond…
49070 …- Accesses to the first 8KB of IGU in BAR0 (MSIX table and PBA) are not allowed. When this value i…
49071 …pletion is considered erroneous. [3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [17:13] - OTB EntryI…
49072 …set. 0 - Unsupported Request or Completer Abort on User RX Interface. 1 - Reception of a poisoned …
49073 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49074 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49075 …- Enable the fix for CQ45220. If a Function receives a Translation Completion with a Translation S…
49076 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49077 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49094 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49096 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49098 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49100 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49102 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49104 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49106 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49108 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49110 …-only register reflects the value of the corresponding 'PF trusted' config bit on the external con…
49113 …. 1 - Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFI…
49114 …- PGLUE will submit the request with TPH info. PXP will take care of aligning it correctly when se…
49115 … address). [13:10] BE first. [17:14] BE last. [21:18] - PFID. [27:22] - Length in DWs. [28] valid …
49116 …- original PFID. [7:4] Pretend PFID. [15:8] Pretend VFID. [16] Pretend vf_valid. [20:17] Pretend r…
49118 …2aa560UL //Access:RW DataWidth:0x1 // 0 - Work with external BAR0 mechanism as defined in E4 …
49125 …57cUL //Access:RW DataWidth:0x1 // FID channel enable configuration per-VF. Controls Target …
49126 …led for that SDM. One bit per SDM. Bit 0 - TSDM. Bit 1 - MSDM. Bit 2 - USDM. Bit 3 - XSDM. Bit 4 -…
49127 …3 // Window size for VF to PF channel. 0 - NA; 1 - 8B; 2 - 16B; 3 - 32B; 4 - 64B; 5 - 128B; 6 -…
49130 … (0x1<<0) // Decision bit for PF master requests when BME is cleared: 0 - block; 1 - discard.
49132 …(0x1<<1) // Decision bit for PF master requests when fid_enable is cleared: 0 - block; 1 - discard.
49134 … (0x1<<2) // Decision bit for PF master requests when was_error is set: 0 - block; 1 - discard.
49136 … (0x1<<3) // Decision bit for VF master requests when BME is cleared: 0 - block; 1 - discard.
49138 …(0x1<<4) // Decision bit for VF master requests when fid_enable is cleared: 0 - block; 1 - discard.
49140 … (0x1<<5) // Decision bit for VF master requests when was_error is set: 0 - block; 1 - discard.
49143 …F master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set atten…
49145 … requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set atten…
49147 … PF master requests when was_error is set: 0 - Always set (and log error details); 1 - never set a…
49149 …F master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set atten…
49151 … requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set atten…
49153 … VF master requests when was_error is set: 0 - Always set (and log error details); 1 - never set a…
49155 … 0x2aa594UL //Access:RW DataWidth:0x1 // When this bit is set and attntion settin…
49156 … 0x2aa598UL //Access:RW DataWidth:0x1 // When this bit is set and attntion settin…
49162 … of '1' instructs PGLUE to use the client ID value in the 'tag' field of non-TPH master write pack…
49163 …RW DataWidth:0x1 // This field is an enable bit for 'detection of out-of-range requests' debu…
49165 … of ) the minimal legal address value. It is used in the 'detection of out-of-range requests' debu…
49167 … of ) the maximal legal address value. It is used in the 'detection of out-of-range requests' debu…
49171 …th illegal address. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49172 …- address was smaller than minimal_address_log; 1 - address was bigger than maximal_address_log. …
49175 …th TPH information. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49176 …nt ID. [6:5] PH. [14:7] Steering Tag. [15] - write_n_read: 0 - read; 1 - write. [16] - last SR. […
49177 …x1 // 0 - never pad write sub-requests with zeros. 1 - Pad write sub-requests with zeros and al…
49178 …/Access:RW DataWidth:0x3 // Cache line size for padding. 0 - 32B. 1 - 64B. 2 - 128B. 3 - 256B.
49179 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49180 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49181 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49182 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49183 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49184 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49185 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49186 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49196 …t error indication. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49197 …[15:0] Request ID. [20:16] client ID. [21] - write_n_read: 0 - read; 1 - write. [22] - last SR. […
49199 …on ROM attention dirty bits. Bit 0 is for engine 0 and bit 1 for engine 1. Set by PXP. Reset by MC…
49201 … 0x2aae90UL //Access:R DataWidth:0x10 // MPS attention dirty bit. Set by PXP. Reset by MC…
49203 …s. Each bit indicates that the VPD register of the corresponding PF was set. Set by PXP. Reset by …
49208 …ess:RW DataWidth:0x1 // Value of 1 indicates that was_error should be set when BME or fid_ena…
49216 … 0x2aaeccUL //Access:R DataWidth:0x5 // PBUS DEV NUM set for MCTP check
49222 …transition IT's checken bit for perfomance improvement If this register is set then b2b transfer w…
49224 …0x2aaeecUL //Access:W DataWidth:0x10 // mrrs attn clear set register if these bits set, then …
49233 … 0x2aaf10UL //Access:R DataWidth:0x10 // pm_dstate 47-032
49235 … 0x2aaf60UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 31-0
49236 … 0x2aaf64UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 63 -32
49237 … 0x2aaf68UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 95 - 64
49238 … 0x2aaf6cUL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 127 - 96
49239 … 0x2aaf70UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 159-128
49243 … // Indicates there was an error in MCTP BIt 21-30 Message code Bit 7-22 Vender ID Bit 3-6 TAG…
49244 …dth:0x20 // Indicates there was an error in MCTP Bit 21-30 Length Bit 5-20 PCIE REQ ID Bit 0-4 …
49256 …0x2aafb4UL //Access:RW DataWidth:0x1 // 0 - Don't discard target request with unknown header …
49257 …cess:RW DataWidth:0x1 // 0 - Don't compare the function received in the completion to the ori…
49258 … 0x2aafbcUL //Access:RW DataWidth:0x1 // 0 - Enable b2b pop from sync fifos in pgl_pci_core_r…
49259 … 0x2aafc0UL //Access:RW DataWidth:0x1 // 0 - Don't discard master request during FLR 1 …
49260 … DataWidth:0x4 // 0 - TXCPL sync fifo push overflow 1 - TXR sync fifo push overflow 2 - TXW hea…
49261 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo pop underflow 1 - RX header syn…
49262 …x2aafccUL //Access:R DataWidth:0x12 // 8:0 - RX target read and config sync fifo pop status …
49265 … (0x1<<0) // Reset the context memory. When set, the context memory…
49267 … (0x1<<1) // Reset the config conn memory. When set, the config conn me…
49269 … (0x1<<2) // Reset the config task memory. When set, the config task me…
49271 … (0x1<<3) // Reset the pre scan memory. When set, the pre scan memor…
49273 …2c0004UL //Access:R DataWidth:0x1 // When set, the self init for the context memory is done.…
49274 … 0x2c0008UL //Access:R DataWidth:0x1 // When set, the self init for …
49275 … 0x2c000cUL //Access:R DataWidth:0x1 // When set, the self init for …
49276 … 0x2c0010UL //Access:R DataWidth:0x1 // When set, the self init for …
49277 … 0x2c0014UL //Access:RW DataWidth:0x1 // When set init the PXP READ D…
49278 … 0x2c0018UL //Access:RW DataWidth:0x1 // When set init the PXP READ C…
49279 … 0x2c001cUL //Access:RW DataWidth:0x1 // When set init the CFC LOAD C…
49280 … 0x2c0020UL //Access:RW DataWidth:0x1 // When set init the CFC LOAD E…
49281 … 0x2c0024UL //Access:RW DataWidth:0x1 // When set init the CLIENT OUT…
49282 … 0x2c0028UL //Access:RW DataWidth:0x1 // When set init the CLIENT IN …
49283 … 0x2c002cUL //Access:RW DataWidth:0x1 // When set init the CLIENT IN …
49284 … 0x2c0030UL //Access:RW DataWidth:0x1 // When set init the CLIENT IN …
49285 … 0x2c0034UL //Access:RW DataWidth:0x1 // When set init the CLIENT IN …
49286 … 0x2c0038UL //Access:RW DataWidth:0x1 // When set init the EXPIRATION…
49287 … 0x2c003cUL //Access:RW DataWidth:0x1 // When set init the AC COMMAND…
49346 … (0x1<<24) // SET/CLEAR/FORCE CLEAR c…
49348 … (0x1<<25) // SET/CLEAR/FORCE CLEAR c…
49363 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
49365 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
49367 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
49369 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
49371 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
49373 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
49375 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
49377 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
49379 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
49381 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
49383 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
49385 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
49387 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
49389 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
49391 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
49393 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
49395 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
49397 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
49399 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
49401 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
49403 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
49405 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
49407 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
49409 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
49411 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
49413 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
49415 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
49417 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
49419 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
49421 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
49423 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
49425 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
49476 …D_0 (0x1<<24) // SET/CLEAR/FORCE CLEAR c…
49478 …D_1 (0x1<<25) // SET/CLEAR/FORCE CLEAR c…
49541 …ID_0 (0x1<<24) // SET/CLEAR/FORCE CLEAR c…
49543 …ID_1 (0x1<<25) // SET/CLEAR/FORCE CLEAR c…
49562 … (0x1<<2) // Context Read with Last indication de-asserted.
49564 … (0x1<<3) // Context Write with Last indication de-asserted.
49581 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
49583 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
49585 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
49587 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
49589 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
49591 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
49593 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
49595 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
49597 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
49599 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
49601 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
49608 … (0x1<<2) // Context Read with Last indication de-asserted.
49610 … (0x1<<3) // Context Write with Last indication de-asserted.
49631 … (0x1<<2) // Context Read with Last indication de-asserted.
49633 … (0x1<<3) // Context Write with Last indication de-asserted.
49650 … (0x1<<0) // This bit masks, when set, the Parity bit: TM…
49652 … (0x1<<9) // This bit masks, when set, the Parity bit: TM…
49654 … (0x1<<1) // This bit masks, when set, the Parity bit: TM…
49656 … (0x1<<11) // This bit masks, when set, the Parity bit: TM…
49658 … (0x1<<2) // This bit masks, when set, the Parity bit: TM…
49660 … (0x1<<4) // This bit masks, when set, the Parity bit: TM…
49662 … (0x1<<3) // This bit masks, when set, the Parity bit: TM…
49664 … (0x1<<12) // This bit masks, when set, the Parity bit: TM…
49666 … (0x1<<4) // This bit masks, when set, the Parity bit: TM…
49668 … (0x1<<13) // This bit masks, when set, the Parity bit: TM…
49670 … (0x1<<5) // This bit masks, when set, the Parity bit: TM…
49672 … (0x1<<6) // This bit masks, when set, the Parity bit: TM…
49674 … (0x1<<7) // This bit masks, when set, the Parity bit: TM…
49676 … (0x1<<5) // This bit masks, when set, the Parity bit: TM…
49678 … (0x1<<8) // This bit masks, when set, the Parity bit: TM…
49680 … (0x1<<10) // This bit masks, when set, the Parity bit: TM…
49682 … (0x1<<9) // This bit masks, when set, the Parity bit: TM…
49684 … (0x1<<8) // This bit masks, when set, the Parity bit: TM…
49686 … (0x1<<10) // This bit masks, when set, the Parity bit: TM…
49688 … (0x1<<15) // This bit masks, when set, the Parity bit: TM…
49690 … (0x1<<11) // This bit masks, when set, the Parity bit: TM…
49692 … (0x1<<16) // This bit masks, when set, the Parity bit: TM…
49694 … (0x1<<12) // This bit masks, when set, the Parity bit: TM…
49696 … (0x1<<13) // This bit masks, when set, the Parity bit: TM…
49698 … (0x1<<6) // This bit masks, when set, the Parity bit: TM…
49700 … (0x1<<14) // This bit masks, when set, the Parity bit: TM…
49702 … (0x1<<0) // This bit masks, when set, the Parity bit: TM…
49704 … (0x1<<1) // This bit masks, when set, the Parity bit: TM…
49706 … (0x1<<2) // This bit masks, when set, the Parity bit: TM…
49708 … (0x1<<3) // This bit masks, when set, the Parity bit: TM…
49710 … (0x1<<14) // This bit masks, when set, the Parity bit: TM…
49722 …_PARITY_ONLY_0_E5 (0x1<<0) // Set parity only for mem…
49724 …I_ECC_0_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
49726 …I_ECC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
49728 …I_ECC_PRTY_BB_K2 (0x1<<2) // Set parity only for mem…
49756 … 0x2c044cUL //Access:RW DataWidth:0x1 // When set, enable the tick_ti…
49758 … 0x2c0454UL //Access:RW DataWidth:0x1 // When set, enable the connect…
49760 … 0x2c045cUL //Access:RW DataWidth:0x1 // When set, enable the tasks s…
49770 …x2 // Number of timers per connection group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49771 …idth:0x2 // Number of timers per task group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49772 …- the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each gr…
49773 …- the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each gr…
49774 …taWidth:0x1 // When set, the pre scan memory is bypassed. This configuration is applicable only…
49776 …lock in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49777 …lock in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49778 …ckss in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49779 …eld for writes; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49780 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49781 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49782 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49783 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49784 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49785 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49786 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49787 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49788 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49789 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49790 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49791 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49792 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49793 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49809 … 0x2c0608UL //Access:R DataWidth:0x20 // Number of SET commands received o…
49814 … 0x2c061cUL //Access:R DataWidth:0x20 // Number of SET commands received o…
49819 … 0x2c0630UL //Access:R DataWidth:0x20 // Number of SET commands received o…
49824 … 0x2c0644UL //Access:R DataWidth:0x20 // Number of SET commands received o…
49831 …ss:RC DataWidth:0x20 // Number of commands (write requests) sent to host (set, clear, stop all)
49841 … 0x2c070cUL //Access:R DataWidth:0x1 // When set indicates that the …
49843 … 0x2c0714UL //Access:R DataWidth:0x1 // When set indicates that the …
49854 …SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical client i…
49858 …the debug_0 registers. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved,…
49859 …tes that the debug_0 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49863 …- SET TIMER, 1 - CLEAR TIMER, 2 - STOP ALL TIMERS, 3 - INIT, 4 - FORCE CLEAR TIMER, 5 - reserved,…
49866 …s:R DataWidth:0x1 // The Leader Type field for the errored command: 0 - connection, 1 - task.
49867 …r the errored command. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved,…
49869 …SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical client i…
49870 …tes that the debug_1 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49872 …-0: LCID, Bit 9: scan type (0 - connection, 1 - task), Bits 12-10: type (3 LSbits), Bit 13: Load E…
49873 …tes that the debug_2 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49874 …last indication de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 10…
49875 …tes that the debug_3 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49876 …ion de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 11-10: Qward V…
49877 …-0: cmd_handler. Bit 3: reserved. Bits 7-4: writ…
49878 …tes that the debug_4 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49879 … Bits 8-0: function # (0-239 VFs, 240 and above PFs / segments) . Bit 9: type (0 - connecti…
49889 …- number of connections, the value should be multiplies of group_size_resolution_conn register (fo…
49893 …- number of tasks, the value should be multiplies of group_size_resolution_task register (for exam…
49897 …r connections, the last 512 rows contain the scan rate fields for tasks. TBD - describe the fields.
49904 …/ When set activity counter ram will be initialized to zeros. when this operation is completed CFC…
49908 …set link list ram will be initialized - all LCIDs will be located in the empty link list. when thi…
49910 …11) // When set the CFC CAMs will be initialized to zeros. When this operation completes CFC_REGIS…
49912 …set during normal operation -- the block must be idle or the request will be ignored. When this op…
49924 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
49926 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
49939 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
49941 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
49943 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
49945 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
49947 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
49949 … (0x1<<3) // This bit masks, when set, the Parity bit: TC…
49957 …3_I_ECC1_PRTY_E5 (0x1<<0) // Set parity only for mem…
49959 …3_I_ECC2_PRTY_E5 (0x1<<1) // Set parity only for mem…
49990 …0x11 // CFC error vector. when the CFC detects an internal error it will set one of these bits. …
49991 …ng. if a bit in this field is set then the corresponding bit in CFC_REGISTERS_CFC_ERROR_VECTOR.ERR…
49993 …-- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Not…
49994 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
49995 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
49996 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
49998 … (0x1<<0) // When set CFC arbiter1 will w…
50000 … (0x1<<1) // When set load context arbite…
50002 … (0x1<<2) // When set CFC arbiter2 will w…
50004 … (0x1<<3) // When set CFC arbiter3 will w…
50006 … (0x1<<4) // When set activity counter de…
50008 … (0x1<<5) // When set activity counter in…
50010 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50020 … (0xf<<10) // This register is not used in BB-B0. Reduced width to …
50048 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50049 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50050 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50055 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
50057 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
50059 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
50061 … (0x1<<3) // This bit masks, when set, the Parity bit: TC…
50063 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
50065 … (0x1<<5) // This bit masks, when set, the Parity bit: TC…
50078 …// This bit when clear will cause a load-cancel response to a load request for PF and set an execu…
50079 …// This bit when clear will cause a load-cancel response to a load request for VF and set an execu…
50080 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50081 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50086 … (0x1<<10) // This field is not used in BB-B0. When set, this configur…
50092 … (0x1<<9) // When set to 1 the search str…
50094 … (0x1<<10) // When set to 1 the cid cam is…
50096 … (0x1<<11) // New Load On Error. if this bit is set and there is a load…
50098 … (0x1<<12) // When set to 1 the string cam…
50100 … (0x1<<13) // When set to 1 the string cam…
50102 … (0x1<<14) // When set to 1 the cid cam hi…
50104 … (0x1<<15) // When set to 1 the cid cam mi…
50106 … 0x2d0740UL //Access:RW DataWidth:0x6 // Set the initial credit …
50109 … 0x2d0780UL //Access:RW DataWidth:0x5 // Set the initial credit …
50110 … 0x2d0784UL //Access:RW DataWidth:0x7 // Set the initial credit …
50111 … 0x2d0788UL //Access:RW DataWidth:0x7 // Set the initial credit …
50112 … 0x2d078cUL //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-b…
50116 … (0x3<<0) // This register is used to set the usage policy fo…
50118 … (0x3<<2) // This register is used to set the usage policy fo…
50122 … 0x2d080cUL //Access:RW DataWidth:0x9 // The size of the empty Link List is set accordingly.
50123 …ataWidth:0x5 // When the sum of number of elements in empty list and in IO list is bigger than …
50139 …Timer in each Generator. At this time, the output of the Generator will be set to the value of the…
50143 …ting Waveform Generator #0. The Waveform will always output this value when the Restart bit is set.
50152 …ting Waveform Generator #1. The Waveform will always output this value when the Restart bit is set.
50161 …ting Waveform Generator #2. The Waveform will always output this value when the Restart bit is set.
50169 …CH_CACHING (0x1<<0) // When set, the String CAM wil…
50171 …HING (0x1<<1) // When set, the String CAM wil…
50174 … 0x2d0a0cUL //Access:RW DataWidth:0x1 // When this bit is set writing to the ccam…
50185 … 0x2d0a38UL //Access:RW DataWidth:0x1 // When this bit is set writing to the scam…
50186 … 0x2d0a3cUL //Access:R DataWidth:0xa // {HIT;LCID}. HIT - if set then previous CAM…
50187 …cess:RW DataWidth:0x1 // Added in E4B0. 0 - tid is not included in hash calculation (like in …
50188 …ess:RW DataWidth:0x1 // Added in E4B0. 0 - vlan is not included in hash calculation (like in …
50189 … DataWidth:0x1 // Used to enable/disable BIST mode on the CID CAM. When set, BIST testing will …
50192 … 0x2d0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CI…
50193 …taWidth:0x1 // Used to enable/disable BIST mode on the STRING CAM. When set, BIST testing will …
50196 … 0x2d0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the ST…
50207 … 0x2db000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
50220 …/ When set activity counter ram will be initialized to zeros. when this operation is completed CFC…
50224 …set link list ram will be initialized - all LCIDs will be located in the empty link list. when thi…
50226 …11) // When set the CFC CAMs will be initialized to zeros. When this operation completes CFC_REGIS…
50228 …set during normal operation -- the block must be idle or the request will be ignored. When this op…
50240 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
50242 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
50255 … (0x1<<0) // This bit masks, when set, the Parity bit: CC…
50257 … (0x1<<1) // This bit masks, when set, the Parity bit: CC…
50259 … (0x1<<0) // This bit masks, when set, the Parity bit: CC…
50261 … (0x1<<2) // This bit masks, when set, the Parity bit: CC…
50263 … (0x1<<3) // This bit masks, when set, the Parity bit: CC…
50265 … (0x1<<4) // This bit masks, when set, the Parity bit: CC…
50267 … (0x1<<5) // This bit masks, when set, the Parity bit: CC…
50269 … (0x1<<1) // This bit masks, when set, the Parity bit: CC…
50285 …5_I_ECC1_PRTY_E5 (0x1<<0) // Set parity only for mem…
50287 …5_I_ECC2_PRTY_E5 (0x1<<1) // Set parity only for mem…
50289 …1_I_ECC_PRTY_E5 (0x1<<2) // Set parity only for mem…
50291 …3_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for mem…
50293 …4_I_ECC_PRTY_E5 (0x1<<4) // Set parity only for mem…
50295 …CC_PARITY_ONLY_0_BB_K2 (0x1<<0) // Set parity only for mem…
50333 …0x11 // CFC error vector. when the CFC detects an internal error it will set one of these bits. …
50334 …ng. if a bit in this field is set then the corresponding bit in CFC_REGISTERS_CFC_ERROR_VECTOR.ERR…
50336 …-- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Not…
50337 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
50338 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
50339 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
50341 … (0x1<<0) // When set CFC arbiter1 will w…
50343 … (0x1<<1) // When set load context arbite…
50345 … (0x1<<2) // When set CFC arbiter2 will w…
50347 … (0x1<<3) // When set CFC arbiter3 will w…
50349 … (0x1<<4) // When set activity counter de…
50351 … (0x1<<5) // When set activity counter in…
50353 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50363 … (0xf<<10) // This register is not used in BB-B0. Reduced width to …
50391 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50392 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50393 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50398 … (0x1<<0) // This bit masks, when set, the Parity bit: CC…
50400 … (0x1<<1) // This bit masks, when set, the Parity bit: CC…
50402 … (0x1<<2) // This bit masks, when set, the Parity bit: CC…
50404 … (0x1<<3) // This bit masks, when set, the Parity bit: CC…
50406 … (0x1<<4) // This bit masks, when set, the Parity bit: CC…
50408 … (0x1<<5) // This bit masks, when set, the Parity bit: CC…
50421 …// This bit when clear will cause a load-cancel response to a load request for PF and set an execu…
50422 …// This bit when clear will cause a load-cancel response to a load request for VF and set an execu…
50423 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50424 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50429 … (0x1<<10) // This field is not used in BB-B0. When set, this configur…
50435 … (0x1<<9) // When set to 1 the search str…
50437 … (0x1<<10) // When set to 1 the cid cam is…
50439 … (0x1<<11) // New Load On Error. if this bit is set and there is a load…
50441 … (0x1<<12) // When set to 1 the string cam…
50443 … (0x1<<13) // When set to 1 the string cam…
50445 … (0x1<<14) // When set to 1 the cid cam hi…
50447 … (0x1<<15) // When set to 1 the cid cam mi…
50449 … 0x2e0740UL //Access:RW DataWidth:0x6 // Set the initial credit …
50452 … 0x2e0780UL //Access:RW DataWidth:0x7 // Set the initial credit …
50453 … 0x2e0784UL //Access:RW DataWidth:0x7 // Set the initial credit …
50454 … 0x2e0788UL //Access:RW DataWidth:0x7 // Set the initial credit …
50455 … 0x2e078cUL //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-b…
50459 … (0x3<<0) // This register is used to set the usage policy fo…
50461 … (0x3<<2) // This register is used to set the usage policy fo…
50465 … 0x2e080cUL //Access:RW DataWidth:0x9 // The size of the empty Link List is set accordingly.
50466 …ataWidth:0x5 // When the sum of number of elements in empty list and in IO list is bigger than …
50482 …Timer in each Generator. At this time, the output of the Generator will be set to the value of the…
50486 …ting Waveform Generator #0. The Waveform will always output this value when the Restart bit is set.
50495 …ting Waveform Generator #1. The Waveform will always output this value when the Restart bit is set.
50504 …ting Waveform Generator #2. The Waveform will always output this value when the Restart bit is set.
50512 …CH_CACHING (0x1<<0) // When set, the String CAM wil…
50514 …HING (0x1<<1) // When set, the String CAM wil…
50517 … 0x2e0a0cUL //Access:RW DataWidth:0x1 // When this bit is set writing to the ccam…
50528 … 0x2e0a38UL //Access:RW DataWidth:0x1 // When this bit is set writing to the scam…
50529 … 0x2e0a3cUL //Access:R DataWidth:0xa // {HIT;LCID}. HIT - if set then previous CAM…
50530 …cess:RW DataWidth:0x1 // Added in E4B0. 0 - tid is not included in hash calculation (like in …
50531 …ess:RW DataWidth:0x1 // Added in E4B0. 0 - vlan is not included in hash calculation (like in …
50532 … DataWidth:0x1 // Used to enable/disable BIST mode on the CID CAM. When set, BIST testing will …
50535 … 0x2e0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CI…
50536 …taWidth:0x1 // Used to enable/disable BIST mode on the STRING CAM. When set, BIST testing will …
50539 … 0x2e0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the ST…
50550 … 0x2eb000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
50609 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
50611 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
50613 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
50615 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
50617 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
50619 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
50621 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
50623 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
50625 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
50627 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
50629 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
50631 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
50633 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
50635 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
50637 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
50639 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
50641 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
50643 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
50645 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
50647 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
50649 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
50651 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
50744 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50746 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
50748 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50750 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
50752 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50754 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50756 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50758 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50760 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50762 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50764 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50767 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50769 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
50771 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50773 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
50775 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50777 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50779 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50781 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50783 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50785 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50787 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50789 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50791 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50793 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
50795 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
50797 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
50799 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
50801 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
50803 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50805 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
50807 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
50809 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
50811 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
50813 … (0x1<<19) // This bit masks, when set, the Parity bit: QM…
50815 … (0x1<<20) // This bit masks, when set, the Parity bit: QM…
50817 … (0x1<<21) // This bit masks, when set, the Parity bit: QM…
50819 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
50821 … (0x1<<22) // This bit masks, when set, the Parity bit: QM…
50823 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
50825 … (0x1<<23) // This bit masks, when set, the Parity bit: QM…
50827 … (0x1<<24) // This bit masks, when set, the Parity bit: QM…
50829 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
50831 … (0x1<<25) // This bit masks, when set, the Parity bit: QM…
50833 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
50835 … (0x1<<26) // This bit masks, when set, the Parity bit: QM…
50837 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
50839 … (0x1<<27) // This bit masks, when set, the Parity bit: QM…
50841 … (0x1<<19) // This bit masks, when set, the Parity bit: QM…
50843 … (0x1<<28) // This bit masks, when set, the Parity bit: QM…
50845 … (0x1<<21) // This bit masks, when set, the Parity bit: QM…
50847 … (0x1<<29) // This bit masks, when set, the Parity bit: QM…
50849 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
50851 … (0x1<<30) // This bit masks, when set, the Parity bit: QM…
50853 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50855 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
50857 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50859 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
50861 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50863 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50865 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50867 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50869 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
50871 … (0x1<<20) // This bit masks, when set, the Parity bit: QM…
50873 … (0x1<<22) // This bit masks, when set, the Parity bit: QM…
50875 … (0x1<<23) // This bit masks, when set, the Parity bit: QM…
50877 … (0x1<<24) // This bit masks, when set, the Parity bit: QM…
50879 … (0x1<<25) // This bit masks, when set, the Parity bit: QM…
50881 … (0x1<<26) // This bit masks, when set, the Parity bit: QM…
50883 … (0x1<<27) // This bit masks, when set, the Parity bit: QM…
50885 … (0x1<<28) // This bit masks, when set, the Parity bit: QM…
50887 … (0x1<<29) // This bit masks, when set, the Parity bit: QM…
50889 … (0x1<<30) // This bit masks, when set, the Parity bit: QM…
50892 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50894 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
50896 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50898 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
50900 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
50902 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
50904 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50906 … (0x1<<21) // This bit masks, when set, the Parity bit: QM…
50908 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50910 … (0x1<<20) // This bit masks, when set, the Parity bit: QM…
50912 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50914 … (0x1<<19) // This bit masks, when set, the Parity bit: QM…
50916 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50918 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
50920 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50922 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50924 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50926 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50928 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50930 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
50932 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50934 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
50936 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50938 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
50940 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
50942 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
50944 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
50946 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
50948 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
50950 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
50952 … (0x1<<19) // This bit masks, when set, the Parity bit: QM…
50954 … (0x1<<20) // This bit masks, when set, the Parity bit: QM…
50956 … (0x1<<21) // This bit masks, when set, the Parity bit: QM…
50958 … (0x1<<22) // This bit masks, when set, the Parity bit: QM…
50960 … (0x1<<23) // This bit masks, when set, the Parity bit: QM…
50962 … (0x1<<24) // This bit masks, when set, the Parity bit: QM…
50964 … (0x1<<25) // This bit masks, when set, the Parity bit: QM…
50966 … (0x1<<26) // This bit masks, when set, the Parity bit: QM…
50968 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
50970 … (0x1<<27) // This bit masks, when set, the Parity bit: QM…
50972 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
50974 … (0x1<<28) // This bit masks, when set, the Parity bit: QM…
50976 … (0x1<<29) // This bit masks, when set, the Parity bit: QM…
50978 … (0x1<<30) // This bit masks, when set, the Parity bit: QM…
50980 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
50982 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50984 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50986 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50988 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50990 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50992 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
50994 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
50996 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
50998 … (0x1<<22) // This bit masks, when set, the Parity bit: QM…
51000 … (0x1<<23) // This bit masks, when set, the Parity bit: QM…
51002 … (0x1<<24) // This bit masks, when set, the Parity bit: QM…
51004 … (0x1<<25) // This bit masks, when set, the Parity bit: QM…
51006 … (0x1<<26) // This bit masks, when set, the Parity bit: QM…
51008 … (0x1<<27) // This bit masks, when set, the Parity bit: QM…
51010 … (0x1<<28) // This bit masks, when set, the Parity bit: QM…
51012 … (0x1<<29) // This bit masks, when set, the Parity bit: QM…
51014 … (0x1<<30) // This bit masks, when set, the Parity bit: QM…
51017 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
51019 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
51021 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
51023 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
51025 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
51027 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
51029 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
51031 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
51033 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
51035 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
51037 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
51039 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
51041 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
51043 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
51045 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
51047 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
51049 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
51051 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
51053 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
51055 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
51057 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
51059 … (0x1<<3) // This bit masks, when set, the Parity bit: QM…
51061 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
51063 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
51065 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
51067 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
51069 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
51071 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
51073 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
51075 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
51077 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
51079 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
51081 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
51083 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
51085 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
51087 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
51089 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
51091 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
51093 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
51095 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
51097 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
51099 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
51101 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
51125 …I_ECC_0_PRTY_E5 (0x1<<0) // Set parity only for mem…
51127 …I_ECC_1_PRTY_E5 (0x1<<1) // Set parity only for mem…
51129 …I_ECC_0_PRTY_E5 (0x1<<2) // Set parity only for mem…
51131 …I_ECC_1_PRTY_E5 (0x1<<3) // Set parity only for mem…
51133 …I_ECC_PRTY_E5 (0x1<<4) // Set parity only for mem…
51135 …I_ECC_0_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
51137 …I_ECC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
51139 …I_ECC_0_PRTY_BB_K2 (0x1<<2) // Set parity only for mem…
51141 …I_ECC_1_PRTY_BB_K2 (0x1<<3) // Set parity only for mem…
51143 …I_ECC_PRTY_BB_K2 (0x1<<4) // Set parity only for mem…
51180 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51181 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51182 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51183 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51184 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51185 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51186 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51187 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51188 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51189 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51190 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51191 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51192 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51193 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51194 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51195 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51196 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51197 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51198 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51199 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51200 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51201 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51202 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51203 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51204 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51205 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51206 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51207 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51208 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51209 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51210 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51211 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51212 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51213 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51214 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51215 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51216 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51217 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51218 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51219 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51220 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51221 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51222 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51223 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51224 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51225 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51226 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51227 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51228 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51229 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51230 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51231 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51232 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51233 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51234 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51235 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51236 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51237 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51238 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51239 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51240 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51241 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51242 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51243 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51244 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51245 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51246 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51254 …L //Access:WB DataWidth:0x36 // Pointer Table Memory for Other queues 63-0; The mapping is as …
51260 … 0x2f1010UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards…
51264 … 0x2f1030UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards…
51265 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51266 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51267 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51268 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51269 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51270 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51271 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51272 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51273 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51274 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51275 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51276 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51277 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51278 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51279 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51280 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51281 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51282 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51283 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51284 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51367 …-b0: rd first bank in page; b3: reserved (zero); b6-b4: wr first bank in page; b7: reserved (zero)…
51368 …al STU within the PXP (there is STU per PF). 0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
51369 …H field used in the PCI request. Per PF value. bits: 8-0 TPH Steering Tag Index; 12-9 reserved; 14…
51375 …- VOQs [0..31] VoqCrdLineFull_msb - VOQs [32..35] Some VOQs are "not used" depending on the…
51376 … to the matched Voq line credit (relevant only for VOQs that are being used - or in other words VO…
51377 …- VOQs [0..31]. VoqCrdByteFull_msb - VOQs [32..35]. Some VOQs are "not used" depending on t…
51378 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51379 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51380 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51381 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51382 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51383 …- VOQs [0..31]. AFullQmBypThrLineVoqMask_msb - VOQs [32..35]. Some VOQs are "not used" depe…
51388 …- resource is required to be more than the almost full threshold. 0 - resource value is do not car…
51391 …ost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_3
51392 …ost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_4
51395 …- resource is required to be more than the almost full threshold. 0 - resource value is do not car…
51398 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51399 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51400 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51401 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51402 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51403 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51404 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51405 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51406 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51407 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51408 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51409 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51410 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51411 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51412 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51413 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51414 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51415 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51416 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51417 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51418 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51419 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51420 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51421 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51422 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51423 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51424 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b01. NOTE: weight update is allowed only to queues w…
51425 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b11. NOTE: weight update is allowed only to queues w…
51436 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51437 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51438 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51439 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51440 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51441 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51442 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51443 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51444 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51445 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51446 …is masked. i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51447 …-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM se…
51462 …0x2f2800UL //Access:R DataWidth:0x1 // The status of the Other PQ-s: bit0 - PQ paused. Shoul…
51466 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51467 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51468 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51469 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51470 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51471 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51472 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51473 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51474 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51475 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51476 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51477 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51478 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51479 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51480 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51481 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51482 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51483 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51484 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51485 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51486 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51487 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51488 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51489 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51490 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51491 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51492 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51493 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51494 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51495 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51496 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51497 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51498 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51499 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51500 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51501 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51502 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51503 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51504 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51505 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51506 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51507 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51508 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51509 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51510 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51511 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51512 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51513 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51514 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51515 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51516 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51517 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51518 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51519 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51520 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51521 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51522 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51523 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51524 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51525 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51526 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51527 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51528 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51529 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51530 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51531 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51532 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51533 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51534 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51535 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51536 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51537 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51538 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51539 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51540 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51541 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51542 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51543 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51544 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51545 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51550 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for selecting a line…
51551 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for enabling dwords …
51552 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for circular right s…
51553 … // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing valid.
51554 … // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing frame.
51555 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 lsb data that…
51556 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 msb data that…
51557 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 frame bits tha…
51558 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 valid bits tha…
51561 …ough RBC) based on the functional flows (e.g. FLR). It is also possible to set this bit by the RBC…
51562 …x2f2ea4UL //Access:RW DataWidth:0x1 // PF enable vector. Bit per PF. If set the PF is enabled.
51563 …x2f2ea8UL //Access:RW DataWidth:0x1 // VF enable vector. Bit per VF. If set the VF is enabled.
51571 …ut period in 25Mhz clock cycles for the global. VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51572 …out period in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51573 … for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. Upon init should be set with value of …
51574 … cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Global VP/QCN RL Timeout1. …
51575 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51576 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51577 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51578 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51579 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51580 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51581 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51582 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51585 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51587 …-init mode. In init mode should be written with the same value of RlGlblUpperBound. Sign: the msb …
51591 …x1 // when 1 - force cam search and update sts_rlglbl_pq_blocked vector even when the rlglblcrd…
51592 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51593 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51594 …o). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51595 …ector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlGlblCrd; b1 …
51596 …ataWidth:0x20 // The RL timeout period in 25Mhz clock cycles for the PF RL-s. NOTE: ck25 domain.…
51597 …e RL timeout period counter in 25Mhz clock cycles for the PF RL-s. Upon init should be set with va…
51601 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51604 …-init mode. In init mode should be written with the same value of RlPfUpperBound. Sign: the msb is…
51608 … the PF RL mechanism per VOQ. RlPfVoqEnable (This one) - VOQs [0..31]. RlPfVoqEnable_msb - …
51609 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51610 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51611 …ero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51612 … vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlPfCrd; b1 …
51616 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51619 …- VOQ0..VOQ15. WfqPfCrd_msb - VOQ16..VOQ35. Should be read only access in non-init mode. In init m…
51624 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51625 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51626 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51627 …vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqPfCrd; b1 …
51629 …0x1 // when 1 - force cam search and update sts_wfqvp_pq_blocked vector even when the wfqvpcrd …
51630 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51631 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51632 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51633 …vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqVpCrd; b1 …
51634 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51635 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51636 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51637 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51638 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51639 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51640 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51641 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51642 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51643 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51644 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51645 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51646 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51647 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51648 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51649 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51650 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51651 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51652 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51653 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51654 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51655 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51656 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51657 …dth:0x3 // VOQ arbiter strict priority weights. Weight0 - highest priority;...; Weight7 - lowe…
51659 …-idle state, trying to start new TX arbitration depends on the GO mode as follows: 0 - start new T…
51662 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51663 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51664 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51665 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51666 …when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqLineCrd; b1 - Err_…
51667 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51668 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51669 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51670 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51671 …when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqByteCrd; b1 - Err_…
51679 … 0x2f5d80UL //Access:R DataWidth:0x1 // When set indicates that the …
51680 …o command. When set the mem is initiazlied. when reset the mem in not initiazlied. There is mask b…
51681 …o command. When set the mem is initiazlied. when reset the mem in not initiazlied. There is mask b…
51682 … When set the mem is initialized with all ones. when reset the mem in initialized with all zeroes.…
51683 … When set the mem is initialized with all ones. when reset the mem in initialized with all zeroes.…
51684 …set indicates that the mem is not currently being initialized. When set indicates that the mem is …
51685 …set indicates that the mem is not currently being initialized. When set indicates that the mem is …
51686 …L //Access:RW DataWidth:0x1 // Used to enable/disable BIST mode. When set, BIST testing will …
51689 … 0x2f5da8UL //Access:R DataWidth:0x16 // Provides read-only access to the BI…
51936 …th:0x4 // The status of the TX PQ-s: bit0 - PQ global VP/QCN RL block; bit1 - PQ active; bit2 -…
51939 …- PQ valid; bits 8:1 - RL id; bits 17:9 - VP id (value of all ones is reserved for pure-LB VOQ …
51945 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51948 …-init mode. In init mode should be written with the same value of WfqVpUpperBound. Sign: the msb i…
51951 … between VP WFQ counter and its resources as follows: bit 5:0 - Voq id; bit 9:6 - Pf id; Som…
51954 …0UL //Access:WB DataWidth:0x36 // Pointer Table Memory for TX queues 447-0; The mapping is as …
51957 …-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb i…
51958 …-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb i…
51961 …-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM se…
51962 …-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM se…
51964 … // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mo…
51965 … // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mo…
51969 …it and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of …
51970 …it and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of …
51974 … // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mo…
51975 … // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mo…
51979 …0x18 // The init and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16.
51980 …it and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16. Some VOQs are …
51984 …- VOQs [0..31]. AFullQmBypThrLineVoqMask_msb (This one) - VOQs [32..35]. Some VOQs are "not used" …
51985 …F RL mechanism per VOQ. RlPfVoqEnable - VOQs [0..31]. RlPfVoqEnable_msb (This one) …
51986 …- VOQs [0..31]. VoqCrdLineFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51987 …- VOQs [0..31]. VoqCrdByteFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51989 …300040UL //Access:RW DataWidth:0x1 // If set and DIF block found error; the DIF block will be…
51990 … 0x300044UL //Access:RW DataWidth:0x1 // If set allow bypass the pi…
51992 …e EOB within the configured number of cycles the dirty_l1 register will be set. Configuring 0 is t…
51993 …//Access:R DataWidth:0x1 // Indicates that there is a pending L1 WB. Set only if this is the…
52001 … 0x30007cUL //Access:RW DataWidth:0x8 // If bit i is set; the data in the de…
52004 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52005 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52006 … 0x300090UL //Access:R DataWidth:0x20 // DEBUG: Buffer information. Calculated offset in IO.
52007 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52008 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52013 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52014 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52015 … 0x3000b4UL //Access:R DataWidth:0x20 // DEBUG: Buffer information. Calculated offset in IO.
52016 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52017 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52021 … 0x3000ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52022 … 0x3000d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52024 … 0x3000d8UL //Access:R DataWidth:0x1 // DEBUG: if set there is no valid d…
52026 … 0x3000e0UL //Access:RW DataWidth:0x1 // When set the REF_MASK and CR…
52040 … (0x1<<6) // If stop_on_error is set and the DIF block f…
52047 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
52049 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
52051 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
52053 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
52055 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
52057 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
52059 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
52061 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
52063 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
52078 … (0x1<<6) // If stop_on_error is set and the DIF block f…
52097 … (0x1<<6) // If stop_on_error is set and the DIF block f…
52104 … (0x1<<1) // This bit masks, when set, the Parity bit: RD…
52106 …IO will be logged. In bits [5:3] of the address represent the error number (0-7). Do not read from…
52117 …-Initial reference tag Address offset-0 bits [31:0]; Field name-Application tag value Address offs…
52118 …- Has 8 QWORDs per task allocated (All are valid). In RDIF - Has 8 QWORDs per task allocated (QWOR…
52122 …310040UL //Access:RW DataWidth:0x1 // If set and DIF block found error; the DIF block will be…
52124 … 0x310048UL //Access:RW DataWidth:0x1 // If set allow bypass the pi…
52126 …e EOB within the configured number of cycles the dirty_l1 register will be set. Configuring 0 is t…
52127 …//Access:R DataWidth:0x1 // Indicates that there is a pending L1 WB. Set only if this is the…
52135 … 0x31007cUL //Access:RW DataWidth:0x8 // If bit i is set; the data in the de…
52138 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52139 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52140 … 0x310090UL //Access:R DataWidth:0x20 // DEBUG: Buffer information. Calculated offset in IO.
52141 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52142 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52147 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52148 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52149 … 0x3100b4UL //Access:R DataWidth:0x20 // DEBUG: Buffer information. Calculated offset in IO.
52150 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52151 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52155 … 0x3100ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52156 … 0x3100d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52158 … 0x3100d8UL //Access:R DataWidth:0x1b // [3:0] - error type ([0] Writ…
52159 … 0x3100dcUL //Access:R DataWidth:0x1 // DEBUG: if set there is no valid d…
52176 … 0x310120UL //Access:RW DataWidth:0x1 // When set the REF_MASK and CR…
52190 … (0x1<<6) // If stop_on_error is set and the DIF block f…
52197 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
52199 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
52201 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
52203 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
52205 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
52207 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
52209 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
52211 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
52213 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
52228 … (0x1<<6) // If stop_on_error is set and the DIF block f…
52247 … (0x1<<6) // If stop_on_error is set and the DIF block f…
52254 … (0x1<<1) // This bit masks, when set, the Parity bit: TD…
52257 … (0x1<<0) // This bit masks, when set, the Parity bit: TD…
52259 … (0x1<<1) // This bit masks, when set, the Parity bit: TD…
52261 … (0x1<<2) // This bit masks, when set, the Parity bit: TD…
52263 … (0x1<<3) // This bit masks, when set, the Parity bit: TD…
52265 … (0x1<<4) // This bit masks, when set, the Parity bit: TD…
52267 … (0x1<<5) // This bit masks, when set, the Parity bit: TD…
52269 … (0x1<<6) // This bit masks, when set, the Parity bit: TD…
52271 … (0x1<<7) // This bit masks, when set, the Parity bit: TD…
52273 … (0x1<<8) // This bit masks, when set, the Parity bit: TD…
52275 … (0x1<<9) // This bit masks, when set, the Parity bit: TD…
52277 … (0x1<<10) // This bit masks, when set, the Parity bit: TD…
52279 … (0x1<<10) // This bit masks, when set, the Parity bit: TD…
52281 … (0x1<<11) // This bit masks, when set, the Parity bit: TD…
52293 …5_I_ECC_PRTY (0x1<<0) // Set parity only for mem…
52295 …9_I_ECC_PRTY (0x1<<1) // Set parity only for mem…
52297 …0_I_ECC_PRTY (0x1<<2) // Set parity only for mem…
52299 …1_I_ECC_PRTY (0x1<<3) // Set parity only for mem…
52311 …IO will be logged. In bits [5:3] of the address represent the error number (0-7). Do not read from…
52322 …- Has 8 QWORDs per task allocated (All are valid). In RDIF - Has 8 QWORDs per task allocated (QWOR…
52338 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
52348 … (0x1<<0) // This bit masks, when set, the Parity bit: RG…
52350 … (0x1<<1) // This bit masks, when set, the Parity bit: RG…
52358 …02_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
52360 …01_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for mem…
52373 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_…
52374 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_…
52389 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52412 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
52422 … (0x1<<0) // This bit masks, when set, the Parity bit: TG…
52424 … (0x1<<1) // This bit masks, when set, the Parity bit: TG…
52432 …02_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
52434 …01_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for mem…
52447 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_…
52448 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_…
52463 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52473 …Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers…
52474 …Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers…
52475 …set when initialization of all BRTB registers and memories is finished. BRTB will fill all prefetc…
52485 … (0x1<<4) // Read packet client PRM error when SOP bit is set in the packet block…
52495 … (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packet block…
52505 … (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packet block…
52515 … (0x1<<19) // Read packet client parser error when SOP bit is set in the packet block…
52542 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
52544 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
52546 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
52548 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
52550 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
52552 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
52554 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
52556 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
52558 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
52560 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
52562 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
52564 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
52566 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
52568 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
52570 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
52572 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
52574 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
52576 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
52578 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
52580 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
52582 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
52584 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
52586 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
52588 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
52590 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
52592 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
52594 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
52596 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
52598 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
52600 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
52602 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
52604 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
52615 … (0x1<<4) // Read packet client PRM error when SOP bit is set in the packet block…
52625 … (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packet block…
52635 … (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packet block…
52645 … (0x1<<19) // Read packet client parser error when SOP bit is set in the packet block…
52680 … (0x1<<4) // Read packet client PRM error when SOP bit is set in the packet block…
52690 … (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packet block…
52700 … (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packet block…
52710 … (0x1<<19) // Read packet client parser error when SOP bit is set in the packet block…
52798 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
52800 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
52802 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
52804 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
52806 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
52808 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
52810 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
52812 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
52814 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
52816 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
52818 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
52820 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
52822 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
52824 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
52826 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
52828 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
52830 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
52832 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
52834 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
52836 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
52838 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
52840 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
52842 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
52844 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
52846 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
52848 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
52850 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
52852 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
52854 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
52856 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
53038 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
53040 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
53042 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
53044 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
53046 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
53048 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
53050 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
53052 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
53054 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
53056 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
53058 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
53060 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
53062 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
53064 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
53066 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
53068 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
53070 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
53072 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
53074 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
53076 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
53078 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
53080 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
53082 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
53084 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
53086 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
53088 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
53090 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
53092 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
53272 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
53274 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
53276 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
53278 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
53280 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
53282 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
53284 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
53286 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
53288 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
53290 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
53292 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
53294 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
53296 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
53298 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
53300 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
53302 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
53304 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
53306 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
53308 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
53310 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
53312 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
53314 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
53316 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
53318 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
53320 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
53322 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
53324 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
53326 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
53328 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
53330 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
53332 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
53495 … (0x1<<22) // Read packet client parser error when SOP bit is set in the packet block…
53516 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
53518 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
53520 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
53522 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
53524 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
53526 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
53528 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
53530 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
53532 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
53534 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
53536 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
53538 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
53540 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
53542 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
53544 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
53546 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
53548 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
53550 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
53552 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
53554 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
53556 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
53558 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
53560 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
53562 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
53564 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
53566 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
53568 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
53605 … (0x1<<22) // Read packet client parser error when SOP bit is set in the packet block…
53660 … (0x1<<22) // Read packet client parser error when SOP bit is set in the packet block…
53684 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
53710 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
53712 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
53714 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
53716 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
53718 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
53720 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
53722 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
53724 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
53826 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
53828 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
53830 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
53832 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
53834 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
53836 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
53838 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
53840 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
53842 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
53844 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
53846 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
53848 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
53850 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
53852 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
53854 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
53856 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
53858 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
53860 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
53862 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
53864 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
53866 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
53868 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
53870 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
53872 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
53874 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
53876 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
53878 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
53880 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
53882 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
53884 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
53886 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
53888 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
54056 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
54058 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
54060 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
54062 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
54064 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
54066 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
54068 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
54070 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
54072 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
54074 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
54076 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
54078 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
54080 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
54082 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
54084 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
54086 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
54088 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
54164 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
54210 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
54212 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
54214 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
54216 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
54218 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
54220 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
54222 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
54224 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
54226 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
54228 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
54230 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
54232 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
54234 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
54236 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
54238 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
54240 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
54242 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
54244 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
54338 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
54340 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
54342 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
54344 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
54346 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
54348 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
54350 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
54352 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
54389 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54391 … (0x1<<1) // This bit masks, when set, the Parity bit: BR…
54393 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54395 … (0x1<<3) // This bit masks, when set, the Parity bit: BR…
54397 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54400 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54402 … (0x1<<1) // This bit masks, when set, the Parity bit: BR…
54404 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54406 … (0x1<<3) // This bit masks, when set, the Parity bit: BR…
54408 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54410 … (0x1<<5) // This bit masks, when set, the Parity bit: BR…
54412 … (0x1<<6) // This bit masks, when set, the Parity bit: BR…
54414 … (0x1<<7) // This bit masks, when set, the Parity bit: BR…
54416 … (0x1<<8) // This bit masks, when set, the Parity bit: BR…
54418 … (0x1<<9) // This bit masks, when set, the Parity bit: BR…
54420 … (0x1<<10) // This bit masks, when set, the Parity bit: BR…
54422 … (0x1<<11) // This bit masks, when set, the Parity bit: BR…
54424 … (0x1<<12) // This bit masks, when set, the Parity bit: BR…
54426 … (0x1<<13) // This bit masks, when set, the Parity bit: BR…
54428 … (0x1<<14) // This bit masks, when set, the Parity bit: BR…
54430 … (0x1<<15) // This bit masks, when set, the Parity bit: BR…
54432 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54434 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54436 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54438 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54440 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54442 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54444 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54446 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54448 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54450 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54452 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54454 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54456 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54458 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54460 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54462 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54464 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54466 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54468 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54470 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54472 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54474 … (0x1<<30) // This bit masks, when set, the Parity bit: BR…
54476 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54478 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54480 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54482 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54484 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54486 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54488 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54490 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54492 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54494 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54496 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54498 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54500 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54502 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54504 … (0x1<<30) // This bit masks, when set, the Parity bit: BR…
54506 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54508 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54510 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54512 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54514 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54516 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54518 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54520 … (0x1<<30) // This bit masks, when set, the Parity bit: BR…
54523 … (0x1<<10) // This bit masks, when set, the Parity bit: BR…
54525 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54527 … (0x1<<1) // This bit masks, when set, the Parity bit: BR…
54529 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54531 … (0x1<<3) // This bit masks, when set, the Parity bit: BR…
54533 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54535 … (0x1<<5) // This bit masks, when set, the Parity bit: BR…
54537 … (0x1<<6) // This bit masks, when set, the Parity bit: BR…
54539 … (0x1<<7) // This bit masks, when set, the Parity bit: BR…
54541 … (0x1<<8) // This bit masks, when set, the Parity bit: BR…
54543 … (0x1<<9) // This bit masks, when set, the Parity bit: BR…
54545 … (0x1<<10) // This bit masks, when set, the Parity bit: BR…
54547 … (0x1<<11) // This bit masks, when set, the Parity bit: BR…
54549 … (0x1<<12) // This bit masks, when set, the Parity bit: BR…
54551 … (0x1<<13) // This bit masks, when set, the Parity bit: BR…
54553 … (0x1<<14) // This bit masks, when set, the Parity bit: BR…
54555 … (0x1<<15) // This bit masks, when set, the Parity bit: BR…
54557 … (0x1<<11) // This bit masks, when set, the Parity bit: BR…
54559 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54561 … (0x1<<3) // This bit masks, when set, the Parity bit: BR…
54563 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54565 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54567 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54569 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54571 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54573 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54575 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54577 … (0x1<<13) // This bit masks, when set, the Parity bit: BR…
54579 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54581 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54583 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54585 … (0x1<<1) // This bit masks, when set, the Parity bit: BR…
54587 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54589 … (0x1<<8) // This bit masks, when set, the Parity bit: BR…
54591 … (0x1<<14) // This bit masks, when set, the Parity bit: BR…
54593 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54595 … (0x1<<7) // This bit masks, when set, the Parity bit: BR…
54597 … (0x1<<13) // This bit masks, when set, the Parity bit: BR…
54599 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54601 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54603 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54605 … (0x1<<3) // This bit masks, when set, the Parity bit: BR…
54607 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54609 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54611 … (0x1<<6) // This bit masks, when set, the Parity bit: BR…
54613 … (0x1<<12) // This bit masks, when set, the Parity bit: BR…
54615 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54617 … (0x1<<9) // This bit masks, when set, the Parity bit: BR…
54619 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54621 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54623 … (0x1<<10) // This bit masks, when set, the Parity bit: BR…
54625 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54627 … (0x1<<30) // This bit masks, when set, the Parity bit: BR…
54629 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54631 … (0x1<<1) // This bit masks, when set, the Parity bit: BR…
54633 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54635 … (0x1<<5) // This bit masks, when set, the Parity bit: BR…
54637 … (0x1<<6) // This bit masks, when set, the Parity bit: BR…
54639 … (0x1<<7) // This bit masks, when set, the Parity bit: BR…
54641 … (0x1<<8) // This bit masks, when set, the Parity bit: BR…
54643 … (0x1<<9) // This bit masks, when set, the Parity bit: BR…
54645 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54647 … (0x1<<15) // This bit masks, when set, the Parity bit: BR…
54649 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54651 … (0x1<<5) // This bit masks, when set, the Parity bit: BR…
54653 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54655 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54657 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54659 … (0x1<<11) // This bit masks, when set, the Parity bit: BR…
54661 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54663 … (0x1<<12) // This bit masks, when set, the Parity bit: BR…
54665 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54667 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54669 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54671 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54675 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54735 …_I_ECC_PRTY (0x1<<0) // Set parity only for mem…
54737 …_I_ECC_PRTY (0x1<<1) // Set parity only for mem…
54739 …_I_ECC_PRTY (0x1<<2) // Set parity only for mem…
54741 …_I_ECC_PRTY (0x1<<3) // Set parity only for mem…
54743 …_I_ECC_PRTY (0x1<<4) // Set parity only for mem…
54745 …_I_ECC_PRTY (0x1<<5) // Set parity only for mem…
54747 …_I_ECC_PRTY (0x1<<6) // Set parity only for mem…
54749 …_I_ECC_PRTY (0x1<<7) // Set parity only for mem…
54751 …_I_ECC_PRTY (0x1<<8) // Set parity only for mem…
54753 …_I_ECC_PRTY (0x1<<9) // Set parity only for mem…
54755 …I_ECC_PRTY (0x1<<10) // Set parity only for mem…
54757 …I_ECC_PRTY (0x1<<11) // Set parity only for mem…
54759 …I_ECC_PRTY (0x1<<12) // Set parity only for mem…
54761 …I_ECC_PRTY (0x1<<13) // Set parity only for mem…
54763 …I_ECC_PRTY (0x1<<14) // Set parity only for mem…
54765 …I_ECC_PRTY (0x1<<15) // Set parity only for mem…
54767 …I_ECC1_PRTY_E5 (0x1<<16) // Set parity only for mem…
54769 …I_ECC2_PRTY_E5 (0x1<<17) // Set parity only for mem…
54771 …I_ECC1_PRTY_E5 (0x1<<18) // Set parity only for mem…
54773 …I_ECC2_PRTY_E5 (0x1<<19) // Set parity only for mem…
54775 …I_ECC1_PRTY_E5 (0x1<<20) // Set parity only for mem…
54777 …I_ECC2_PRTY_E5 (0x1<<21) // Set parity only for mem…
54779 …I_ECC1_PRTY_E5 (0x1<<22) // Set parity only for mem…
54781 …I_ECC2_PRTY_E5 (0x1<<23) // Set parity only for mem…
54848 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
54849 …04UL //Access:RW DataWidth:0xa // Number of valid bytes in header in 16-bytes resolution. Aft…
54857 … DataWidth:0x5 // There is bit for each PACKET read client. When bit is set then read client wi…
54858 … shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) R…
54920 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54921 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54922 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54923 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54924 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54925 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54926 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54927 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54928 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54929 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54930 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54931 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54932 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54933 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54934 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54935 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54936 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54937 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54938 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54939 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54940 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54941 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54942 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54943 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54944 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54945 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54946 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54947 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54948 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54949 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54950 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54951 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54952 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54953 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54954 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54955 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54956 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54957 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54958 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54959 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54960 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54961 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54962 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54963 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54964 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54965 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54966 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54967 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54968 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54969 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54970 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54971 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54972 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54973 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54974 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54975 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54976 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54977 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54978 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54979 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54980 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54981 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54982 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54983 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54984 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54985 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54986 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54987 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54988 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54989 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54990 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54991 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54992 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54993 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54994 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54995 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54996 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54997 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54998 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54999 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55000 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55001 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55002 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55003 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55004 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55005 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55006 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55007 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55008 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55009 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55010 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55011 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55012 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55013 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55014 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55015 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55016 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55017 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55018 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55019 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55020 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55021 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55022 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55023 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55024 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55025 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55026 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55027 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55033 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55034 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55035 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55036 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55037 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55038 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55039 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55040 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55041 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55042 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55043 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55044 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55045 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55046 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55047 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55048 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55049 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55050 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55051 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55052 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55053 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55054 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55055 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55056 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55057 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55058 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55059 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55060 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55061 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55062 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55063 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55065 …rted when number of allocated blocks in TC bigger lossless_threshold, if 0 - then full to that TC…
55070 …set then packet will be read without dead cycles.B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DE…
55072 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55074 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55076 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55078 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55080 … priority then selection between them is done with RR. Possible values are 1-3. Priority 7 is high…
55082 …ent 0 and so on. If bit is set then packet will be written without intra packet dead cycles .B0-PR…
55083 …and so on. If bit is set then highest priority mechanism is enabled for the corresponding client. …
55084 …is is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
55085 …s is priority for EOP read client to BIG RAM arbiters. Possible values are 0-7. Priority 7 is high…
55086 …cket request of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
55087 …h multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is high…
55116 …-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When…
55118 …- IF0, B1- IF1. When bit is set then appropriate interface is enabled. When bit is reset then requ…
55120 …set then appropriate interface is enabled. When bit is reset then request from that interface will…
55122 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
55125 …-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When…
55127 …- IF0, B1- IF1. When bit is set then appropriate interface is enabled.When bit is reset then valid…
55129 …set then appropriate interface is enabled. When bit is reset then valid to that interface will nev…
55131 …AC port. When bit is set then pause interface is enabled. When bit is reset then any pause will ne…
55133 …port. When bit is set then empty interface is enabled. When bit is reset then empty interface will…
55135 …bit is set then packet avalable interface is enabled. When bit is reset then packet avalable inter…
55137 …en bit is set then stop parsing interface is enabled. When bit is reset then stop parsing interfac…
55139 …t is set then power management interface is enabled. When bit is reset then power management int…
55141 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55142 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55143 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55144 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55145 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55146 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55147 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55148 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55149 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55150 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55151 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55152 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55153 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55154 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55155 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55156 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55159 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55160 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55161 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55162 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55163 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55164 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55165 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55166 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55167 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55168 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55169 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55170 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55171 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55172 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55173 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55174 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55175 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55176 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
55291 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
55294 …ister for each erad packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelli…
55296 …ister for each read packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelli…
55298 …-port per-TC counters. In BigBear, entries 0-7 are port 0 (main 0) TCs 0-7. Entries 8-16 are port …
55301 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55303 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55305 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55307 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55309 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55311 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55313 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55315 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55323 … 0x344008UL //Access:RW DataWidth:0x1 // When this bit is set, then the shared ar…
55324 …When the total port's used shared area crosses this number, over subscription is set for this port.
55326 …cess:RW DataWidth:0x10 // Bit enable per each main TC. When the bit is set, and the port's ove…
55327 …Access:RW DataWidth:0x14 // Bit enable per each LB TC. When the bit is set, and the port's ove…
55328 …cess:RW DataWidth:0x10 // Bit enable per each main TC. When the bit is set, and the port's ove…
55329 …Access:RW DataWidth:0x14 // Bit enable per each LB TC. When the bit is set, and the port's ove…
55330 …Access:RW DataWidth:0xe // Link list dual port memory that contains per-block descriptor::s/B…
55331 …Access:RW DataWidth:0xf // Link list dual port memory that contains per-block descriptor::s/B…
55365 …in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minicache_resp_log is set
55366 …in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minicache_resp_log is set
55367 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
55368 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
55370 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55371 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55372 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55373 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55374 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55375 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55376 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55377 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55378 …0x4c00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55379 …0x4c00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55380 …0x4c00bcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55381 …0x4c00c0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55383 …:0x8 // Logging register for segment message error: bits 3:0 - header len; bits 7:4 - number of…
55384 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 31:0 of the seg…
55385 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 63:32 of the se…
55386 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 95:64 of the se…
55392 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55401 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55403 … (0x1<<3) // Mini cache error - meaning that A load …
55405 … (0x1<<4) // Mini cache error - meaning that A load …
55410 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
55412 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
55414 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
55416 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
55418 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
55420 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
55427 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55429 … (0x1<<3) // Mini cache error - meaning that A load …
55431 … (0x1<<4) // Mini cache error - meaning that A load …
55440 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55442 … (0x1<<3) // Mini cache error - meaning that A load …
55444 … (0x1<<4) // Mini cache error - meaning that A load …
55449 … (0x1<<0) // This bit masks, when set, the Parity bit: XY…
55451 … (0x1<<1) // This bit masks, when set, the Parity bit: XY…
55453 … (0x1<<2) // This bit masks, when set, the Parity bit: XY…
55455 … (0x1<<3) // This bit masks, when set, the Parity bit: XY…
55457 … (0x1<<4) // This bit masks, when set, the Parity bit: XY…
55459 … (0x1<<5) // This bit masks, when set, the Parity bit: XY…
55461 … (0x1<<7) // This bit masks, when set, the Parity bit: XY…
55463 … (0x1<<6) // This bit masks, when set, the Parity bit: XY…
55465 … (0x1<<7) // This bit masks, when set, the Parity bit: XY…
55467 … (0x1<<8) // This bit masks, when set, the Parity bit: XY…
55469 … (0x1<<6) // This bit masks, when set, the Parity bit: XY…
55471 … (0x1<<9) // This bit masks, when set, the Parity bit: XY…
55473 … (0x1<<10) // This bit masks, when set, the Parity bit: XY…
55475 … (0x1<<5) // This bit masks, when set, the Parity bit: XY…
55477 … (0x1<<11) // This bit masks, when set, the Parity bit: XY…
55479 … (0x1<<4) // This bit masks, when set, the Parity bit: XY…
55481 … (0x1<<12) // This bit masks, when set, the Parity bit: XY…
55483 … (0x1<<8) // This bit masks, when set, the Parity bit: XY…
55485 … (0x1<<13) // This bit masks, when set, the Parity bit: XY…
55487 … (0x1<<14) // This bit masks, when set, the Parity bit: XY…
55489 … (0x1<<0) // This bit masks, when set, the Parity bit: XY…
55491 … (0x1<<1) // This bit masks, when set, the Parity bit: XY…
55503 …0_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
55505 …2_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for mem…
55507 …4_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
55509 …6_I_ECC_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
55521 … 0x4c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55523 … 0x4c0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55528 …the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configura…
55530 … (0x1<<2) // defines that only back-to-back aggregation is …
55532 … (0x1<<3) // When this flag is set, all input messages are treated as if their IncS…
55539 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
55541 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
55543 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
55545 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
55549 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
55551 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
55553 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
55555 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
55558 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
55560 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
55562 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
55564 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
55567 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
55569 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
55571 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
55573 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
55576 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
55578 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
55580 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
55582 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
55618 … 0x4c0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55619 … 0x4c0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55620 … 0x4c092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55621 … 0x4c0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55622 … 0x4c0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55623 … 0x4c0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55624 … 0x4c093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55625 … 0x4c0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55626 … 0x4c0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55627 … 0x4c0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55628 … 0x4c094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55629 … 0x4c0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55630 … 0x4c0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55631 … 0x4c0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55632 … 0x4c095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55633 … 0x4c0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55634 … 0x4c0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55635 … 0x4c0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55636 … 0x4c096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55637 … 0x4c0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55638 … 0x4c0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55639 … 0x4c0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55640 … 0x4c097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55641 … 0x4c0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55642 … 0x4c0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55643 … 0x4c0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55644 … 0x4c098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55645 … 0x4c0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55646 … 0x4c0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55647 … 0x4c0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55648 … 0x4c099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55649 … 0x4c09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55651 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
55653 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
55655 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
55657 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
55660 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
55662 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
55664 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
55666 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
55669 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
55671 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
55673 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
55675 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
55678 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
55680 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
55682 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
55684 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
55723 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
55725 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
55727 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
55729 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
55731 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
55733 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
55735 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
55737 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
55740 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0.
55742 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
55744 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 2.
55746 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
55749 … (0xf<<0) // the maximal number of children in a specific aggregation. for set 0.
55751 … (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
55753 … (0xf<<8) // the maximal number of children in a specific aggregation. for set 2.
55755 … (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
55758 …0xff<<0) // The value by which to increment the event-ID in case of successful aggregation. for se…
55760 …0xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for se…
55762 …xff<<16) // The value by which to increment the event-ID in case of successful aggregation. for se…
55764 …xff<<24) // The value by which to increment the event-ID in case of successful aggregation. for se…
55811 …in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minicache_resp_log is set
55812 …in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minicache_resp_log is set
55813 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
55814 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
55816 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55817 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55818 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55819 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55820 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55821 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55822 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55823 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55824 …0x4c8098UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55825 …0x4c809cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55826 …0x4c80a0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55827 …0x4c80a4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55832 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55841 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55843 … (0x1<<3) // Mini cache error - meaning that A load …
55845 … (0x1<<4) // Mini cache error - meaning that A load …
55850 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
55852 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
55854 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
55856 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
55858 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
55860 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
55867 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55869 … (0x1<<3) // Mini cache error - meaning that A load …
55871 … (0x1<<4) // Mini cache error - meaning that A load …
55880 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55882 … (0x1<<3) // Mini cache error - meaning that A load …
55884 … (0x1<<4) // Mini cache error - meaning that A load …
55889 … (0x1<<0) // This bit masks, when set, the Parity bit: YU…
55891 … (0x1<<1) // This bit masks, when set, the Parity bit: YU…
55893 … (0x1<<2) // This bit masks, when set, the Parity bit: YU…
55895 … (0x1<<3) // This bit masks, when set, the Parity bit: YU…
55897 … (0x1<<4) // This bit masks, when set, the Parity bit: YU…
55899 … (0x1<<5) // This bit masks, when set, the Parity bit: YU…
55902 … 0x4c8400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55904 … 0x4c8800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55925 …the BRB read response buffer. The slot size would be the BRB-response-buffer-size/number-of-slots.…
55928 … DataWidth:0x1 // When set the data returning from the BRB is swapped. meaning that bytes 0…
55929 …30UL //Access:RW DataWidth:0x3 // Max credit number for the BRB request-resonse interface::/M…
55947 …in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minicache_resp_log is set
55948 …in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minicache_resp_log is set
55949 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
55950 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
55952 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55953 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55954 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55955 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55956 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55957 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55958 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55959 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55960 …0x4d00acUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55961 …0x4d00b0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55962 …0x4d00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55963 …0x4d00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55968 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55977 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55979 … (0x1<<3) // Mini cache error - meaning that A load …
55981 … (0x1<<4) // Mini cache error - meaning that A load …
55986 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
55988 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
55990 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
55992 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
55994 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
55996 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
56003 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56005 … (0x1<<3) // Mini cache error - meaning that A load …
56007 … (0x1<<4) // Mini cache error - meaning that A load …
56016 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56018 … (0x1<<3) // Mini cache error - meaning that A load …
56020 … (0x1<<4) // Mini cache error - meaning that A load …
56025 … (0x1<<0) // This bit masks, when set, the Parity bit: TM…
56027 … (0x1<<1) // This bit masks, when set, the Parity bit: TM…
56029 … (0x1<<2) // This bit masks, when set, the Parity bit: TM…
56031 … (0x1<<3) // This bit masks, when set, the Parity bit: TM…
56033 … (0x1<<4) // This bit masks, when set, the Parity bit: TM…
56035 … (0x1<<5) // This bit masks, when set, the Parity bit: TM…
56037 … (0x1<<4) // This bit masks, when set, the Parity bit: TM…
56039 … (0x1<<6) // This bit masks, when set, the Parity bit: TM…
56041 … (0x1<<7) // This bit masks, when set, the Parity bit: TM…
56043 … (0x1<<6) // This bit masks, when set, the Parity bit: TM…
56045 … (0x1<<8) // This bit masks, when set, the Parity bit: TM…
56047 … (0x1<<9) // This bit masks, when set, the Parity bit: TM…
56049 … (0x1<<10) // This bit masks, when set, the Parity bit: TM…
56051 … (0x1<<11) // This bit masks, when set, the Parity bit: TM…
56053 … (0x1<<12) // This bit masks, when set, the Parity bit: TM…
56055 … (0x1<<5) // This bit masks, when set, the Parity bit: TM…
56057 … (0x1<<13) // This bit masks, when set, the Parity bit: TM…
56059 … (0x1<<0) // This bit masks, when set, the Parity bit: TM…
56069 …2_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
56071 …2_I_ECC_PRTY (0x1<<1) // Set parity only for mem…
56073 …6_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
56083 … 0x4d0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56085 … 0x4d0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56090 …the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configura…
56092 … (0x1<<2) // defines that only back-to-back aggregation is …
56094 … (0x1<<3) // When this flag is set, all input messages are treated as if their IncS…
56101 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
56103 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
56105 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
56107 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
56111 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
56113 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
56115 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
56117 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
56120 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
56122 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
56124 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
56126 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
56129 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
56131 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
56133 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
56135 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
56138 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
56140 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
56142 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
56144 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
56180 … 0x4d0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56181 … 0x4d0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56182 … 0x4d092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56183 … 0x4d0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56184 … 0x4d0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56185 … 0x4d0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56186 … 0x4d093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56187 … 0x4d0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56188 … 0x4d0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56189 … 0x4d0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56190 … 0x4d094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56191 … 0x4d0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56192 … 0x4d0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56193 … 0x4d0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56194 … 0x4d095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56195 … 0x4d0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56196 … 0x4d0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56197 … 0x4d0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56198 … 0x4d096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56199 … 0x4d0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56200 … 0x4d0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56201 … 0x4d0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56202 … 0x4d097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56203 … 0x4d0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56204 … 0x4d0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56205 … 0x4d0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56206 … 0x4d098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56207 … 0x4d0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56208 … 0x4d0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56209 … 0x4d0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56210 … 0x4d099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56211 … 0x4d09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56213 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
56215 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
56217 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
56219 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
56222 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
56224 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
56226 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
56228 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
56231 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
56233 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
56235 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
56237 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
56240 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
56242 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
56244 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
56246 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
56285 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
56287 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
56289 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
56291 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
56293 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56295 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56297 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56299 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56302 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0.
56304 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
56306 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 2.
56308 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
56311 … (0xf<<0) // the maximal number of children in a specific aggregation. for set 0.
56313 … (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
56315 … (0xf<<8) // the maximal number of children in a specific aggregation. for set 2.
56317 … (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
56320 …0xff<<0) // The value by which to increment the event-ID in case of successful aggregation. for se…
56322 …0xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for se…
56324 …xff<<16) // The value by which to increment the event-ID in case of successful aggregation. for se…
56326 …xff<<24) // The value by which to increment the event-ID in case of successful aggregation. for se…
56353 … 0x4e0014UL //Access:RW DataWidth:0x4 // Log 2 of the BD size in bytes - 2:BD size is 4bytes;…
56355 …0x4e001cUL //Access:RW DataWidth:0x4 // Log 2 of the SGE size in bytes - 2:SGE size is 4bytes…
56387 …in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minicache_resp_log is set
56388 …in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minicache_resp_log is set
56389 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
56390 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
56392 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56393 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56394 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56395 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56396 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56397 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56398 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56399 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56400 …0x4e00d0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56401 …0x4e00d4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56402 …0x4e00d8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56403 …0x4e00dcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56408 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
56417 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56419 … (0x1<<3) // Mini cache error - meaning that A load …
56421 … (0x1<<4) // Mini cache error - meaning that A load …
56426 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
56428 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
56430 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
56432 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
56434 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
56436 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
56443 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56445 … (0x1<<3) // Mini cache error - meaning that A load …
56447 … (0x1<<4) // Mini cache error - meaning that A load …
56456 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56458 … (0x1<<3) // Mini cache error - meaning that A load …
56460 … (0x1<<4) // Mini cache error - meaning that A load …
56465 … (0x1<<0) // This bit masks, when set, the Parity bit: MU…
56467 … (0x1<<1) // This bit masks, when set, the Parity bit: MU…
56469 … (0x1<<2) // This bit masks, when set, the Parity bit: MU…
56471 … (0x1<<3) // This bit masks, when set, the Parity bit: MU…
56473 … (0x1<<4) // This bit masks, when set, the Parity bit: MU…
56475 … (0x1<<5) // This bit masks, when set, the Parity bit: MU…
56477 … (0x1<<6) // This bit masks, when set, the Parity bit: MU…
56479 … (0x1<<7) // This bit masks, when set, the Parity bit: MU…
56481 … (0x1<<9) // This bit masks, when set, the Parity bit: MU…
56483 … (0x1<<8) // This bit masks, when set, the Parity bit: MU…
56485 … (0x1<<9) // This bit masks, when set, the Parity bit: MU…
56487 … (0x1<<8) // This bit masks, when set, the Parity bit: MU…
56489 … (0x1<<10) // This bit masks, when set, the Parity bit: MU…
56491 … (0x1<<11) // This bit masks, when set, the Parity bit: MU…
56493 … (0x1<<7) // This bit masks, when set, the Parity bit: MU…
56495 … (0x1<<12) // This bit masks, when set, the Parity bit: MU…
56497 … (0x1<<6) // This bit masks, when set, the Parity bit: MU…
56499 … (0x1<<13) // This bit masks, when set, the Parity bit: MU…
56501 … (0x1<<14) // This bit masks, when set, the Parity bit: MU…
56503 … (0x1<<15) // This bit masks, when set, the Parity bit: MU…
56505 … (0x1<<0) // This bit masks, when set, the Parity bit: MU…
56507 … (0x1<<2) // This bit masks, when set, the Parity bit: MU…
56509 … (0x1<<3) // This bit masks, when set, the Parity bit: MU…
56527 …1_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
56529 …1_I_ECC_PRTY (0x1<<1) // Set parity only for mem…
56531 …4_I_ECC_PRTY_E5 (0x1<<2) // Set parity only for mem…
56533 …3_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for mem…
56535 …5_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
56537 …8_I_ECC_PRTY_BB_K2 (0x1<<2) // Set parity only for mem…
56539 …7_I_ECC_PRTY_BB_K2 (0x1<<3) // Set parity only for mem…
56557 … 0x4e0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56559 … 0x4e0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56561 … 0x4e0c00UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue2 - Debug access::/TMLD_…
56563 … 0x4e1000UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue3 - Debug access::/TMLD_…
56568 …the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configura…
56570 … (0x1<<2) // defines that only back-to-back aggregation is …
56572 … (0x1<<3) // When this flag is set, all input messages are treated as if their IncS…
56579 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
56581 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
56583 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
56585 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
56589 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
56591 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
56593 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
56595 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
56598 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
56600 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
56602 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
56604 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
56607 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
56609 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
56611 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
56613 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
56616 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
56618 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
56620 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
56622 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
56658 … 0x4e1424UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56659 … 0x4e1428UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56660 … 0x4e142cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56661 … 0x4e1430UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56662 … 0x4e1434UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56663 … 0x4e1438UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56664 … 0x4e143cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56665 … 0x4e1440UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56666 … 0x4e1444UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56667 … 0x4e1448UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56668 … 0x4e144cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56669 … 0x4e1450UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56670 … 0x4e1454UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56671 … 0x4e1458UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56672 … 0x4e145cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56673 … 0x4e1460UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56674 … 0x4e1464UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56675 … 0x4e1468UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56676 … 0x4e146cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56677 … 0x4e1470UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56678 … 0x4e1474UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56679 … 0x4e1478UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56680 … 0x4e147cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56681 … 0x4e1480UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56682 … 0x4e1484UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56683 … 0x4e1488UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56684 … 0x4e148cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56685 … 0x4e1490UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56686 … 0x4e1494UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56687 … 0x4e1498UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56688 … 0x4e149cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56689 … 0x4e14a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56691 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
56693 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
56695 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
56697 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
56700 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
56702 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
56704 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
56706 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
56709 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
56711 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
56713 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
56715 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
56718 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
56720 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
56722 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
56724 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
56763 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
56765 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
56767 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
56769 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
56771 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56773 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56775 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56777 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56780 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0.
56782 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
56784 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 2.
56786 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
56789 … (0xf<<0) // the maximal number of children in a specific aggregation. for set 0.
56791 … (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
56793 … (0xf<<8) // the maximal number of children in a specific aggregation. for set 2.
56795 … (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
56798 …0xff<<0) // The value by which to increment the event-ID in case of successful aggregation. for se…
56800 …0xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for se…
56802 …xff<<16) // The value by which to increment the event-ID in case of successful aggregation. for se…
56804 …xff<<24) // The value by which to increment the event-ID in case of successful aggregation. for se…
56819 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
56823 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
56859 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
56861 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
56863 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
56865 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
56867 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
56869 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
56871 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
56873 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
56875 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
56877 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
56879 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
56881 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
56883 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
56885 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
57011 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
57013 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
57015 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
57017 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
57019 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
57021 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
57023 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
57025 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
57027 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
57029 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
57031 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
57033 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
57035 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
57037 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
57039 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
57041 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
57043 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
57045 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
57047 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
57049 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
57051 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
57053 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
57055 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
57057 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
57059 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
57061 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
57063 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
57065 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
57067 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
57069 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
57071 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
57073 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
57206 … (0x1<<0) // Error in the pure-loopback SOPQ.
57251 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
57253 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
57255 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
57257 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
57259 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
57261 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
57263 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
57265 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
57267 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
57269 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
57271 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
57273 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
57275 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
57277 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
57279 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
57281 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
57283 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
57285 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
57287 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
57289 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
57291 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
57293 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
57296 … (0x1<<0) // Error in the pure-loopback SOPQ.
57341 … (0x1<<0) // Error in the pure-loopback SOPQ.
57423 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
57425 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
57427 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
57429 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
57431 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
57433 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
57435 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
57437 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
57439 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
57441 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
57443 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
57445 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
57447 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
57449 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
57451 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
57453 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
57455 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
57457 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
57534 … (0x1<<0) // Error in the pure-loopback SOPQ.
57579 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
57581 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
57583 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
57585 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
57587 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
57589 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
57591 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
57593 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
57595 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
57597 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
57599 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
57601 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
57603 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
57605 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
57607 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
57609 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
57611 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
57613 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
57615 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
57617 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
57619 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
57621 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
57624 … (0x1<<0) // Error in the pure-loopback SOPQ.
57669 … (0x1<<0) // Error in the pure-loopback SOPQ.
57751 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
57753 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
57755 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
57757 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
57759 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
57761 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
57763 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
57765 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
57767 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
57769 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
57771 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
57773 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
57775 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
57777 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
57779 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
57781 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
57783 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
57785 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
57862 … (0x1<<0) // Error in the pure-loopback SOPQ.
57907 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
57909 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
57911 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
57913 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
57915 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
57917 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
57919 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
57921 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
57923 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
57925 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
57927 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
57929 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
57931 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
57933 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
57935 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
57937 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
57939 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
57941 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
57943 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
57945 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
57947 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
57949 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
57952 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
57997 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58079 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
58081 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
58083 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
58085 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
58087 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
58089 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
58091 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
58093 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
58095 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
58097 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
58099 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
58101 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
58103 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
58105 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
58107 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
58109 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
58111 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
58113 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
58190 … (0x1<<0) // Error in the pure-loopback SOPQ.
58235 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
58237 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
58239 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
58241 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
58243 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
58245 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
58247 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
58249 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
58251 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
58253 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
58255 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
58257 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
58259 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
58261 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
58263 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
58265 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
58267 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
58269 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
58271 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
58273 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
58275 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
58277 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
58280 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58325 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58407 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
58409 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
58411 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
58413 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
58415 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
58417 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
58419 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
58421 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
58423 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
58425 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
58427 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
58429 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
58431 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
58433 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
58435 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
58437 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
58439 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
58441 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
58519 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58555 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
58557 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
58559 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
58561 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
58563 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
58565 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
58567 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
58569 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
58571 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
58573 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
58575 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
58577 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
58579 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
58581 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
58583 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
58585 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
58654 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58656 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
58658 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58660 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58662 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
58664 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58666 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58668 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58670 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58672 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58674 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58676 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58678 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58680 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58682 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58684 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58686 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58688 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58690 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58692 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58694 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58696 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58698 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58700 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58702 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58704 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58706 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58708 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58710 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58712 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58714 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58716 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58718 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58720 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58722 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58724 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58726 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58728 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58730 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58732 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58734 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58736 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58738 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58740 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58742 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58744 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58746 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58748 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58750 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58752 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58754 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58756 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58758 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58760 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58762 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58764 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
58766 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58768 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58770 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
58772 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
58774 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58776 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58778 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58780 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58782 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58784 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58786 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58788 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58790 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58792 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58794 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58796 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58798 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
58800 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58802 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58804 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58806 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58808 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58810 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58812 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58814 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58816 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58818 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58820 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58822 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58824 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58826 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58828 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58830 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58832 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58834 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58836 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58838 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58841 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58843 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58845 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
58847 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58849 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58851 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
58853 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58855 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58857 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58859 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58861 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58863 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58865 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58867 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58869 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58871 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58873 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58875 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58877 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58879 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58881 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58883 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58885 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58887 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58889 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58891 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58893 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58895 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58897 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58899 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58901 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58903 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58905 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58907 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58909 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58911 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58913 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58915 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58917 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58919 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58921 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58923 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58925 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58927 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58929 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58931 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58933 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58935 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58937 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58939 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
58941 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58943 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58945 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58947 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
58949 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58951 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58953 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58955 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58957 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58959 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58961 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58963 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58965 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58967 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58969 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58971 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58973 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58975 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58977 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58979 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
58981 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58983 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
58985 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58987 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58989 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58991 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58993 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58995 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58997 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58999 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59001 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59003 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59005 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59007 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59009 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59011 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59013 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
59015 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
59017 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
59019 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
59021 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
59023 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
59025 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
59028 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59030 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59032 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59034 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
59036 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59038 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
59040 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59042 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59044 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59046 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59048 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59050 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59052 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59054 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
59056 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59058 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59060 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59062 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59064 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59066 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59068 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59070 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59072 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59074 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59076 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59078 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59080 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59082 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59084 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59086 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59088 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59090 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59092 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
59094 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59096 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
59098 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
59100 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
59102 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
59104 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
59106 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
59108 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
59110 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
59112 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59114 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
59116 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59118 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
59120 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
59122 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59124 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
59126 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
59128 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59130 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
59132 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
59134 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
59136 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59138 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
59140 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
59142 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59144 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59146 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59148 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
59150 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59152 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
59154 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59156 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59158 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59160 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59162 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59164 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59166 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59168 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59170 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
59172 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
59174 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
59176 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
59178 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
59180 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
59182 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
59184 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
59186 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
59188 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
59190 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
59192 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59194 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
59196 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59198 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59200 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59202 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59204 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59206 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59208 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
59210 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
59212 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
59215 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59217 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
59219 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59221 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
59223 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59225 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59227 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59229 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59231 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59233 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59235 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59237 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59239 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59241 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59243 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59245 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59247 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59249 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59251 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59253 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59255 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59257 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59259 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59261 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59263 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59265 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59267 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
59269 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59271 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
59273 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59275 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
59277 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59279 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
59281 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59283 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
59285 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59287 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59289 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59291 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59293 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59295 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
59297 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59299 … (0x1<<3) // This bit masks, when set, the Parity bit: NI…
59301 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59303 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59305 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59307 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59309 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59311 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59313 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59315 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59317 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59319 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59321 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59324 …0x1 // Close-gate function disable bit: 0 - egress drain mode is enabled when close-gate input…
59331 … 0x50081cUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59332 … 0x500820UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59333 … 0x500824UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59334 … 0x500828UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59335 … 0x50082cUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59336 … 0x500830UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59338 …RX packets. 0 is for XSTORM; 1 is for YSTORM. This configuration should be static during run-time.
59339 …get the current credit count on the interface. This configuration should be static during run-time.
59343 … (0x1<<8) // T-bit to be used in CM …
59349 …-PF drop and per-VPORT drop packets or forward the packet to the destination with the error bit se…
59350 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59351 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59352 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59353 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59354 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59355 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59356 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59357 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59358 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59359 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59360 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59361 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59362 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59363 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59364 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59365 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59366 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59367 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59368 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59369 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59370 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59371 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59372 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59373 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59374 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59375 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59376 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59377 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59378 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59379 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59380 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59381 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59382 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59383 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59384 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59385 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59386 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59387 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59388 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59389 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59390 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59391 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59392 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59393 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59394 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59395 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59396 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59397 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59398 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59399 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59400 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59401 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59402 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59403 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59404 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59405 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59406 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59407 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59408 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59409 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59410 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59411 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59412 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59413 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59414 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59415 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59416 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59417 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59418 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59419 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59420 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59421 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59422 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59423 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59424 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59425 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59426 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59427 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59428 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59429 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59430 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59431 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59432 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59433 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59434 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59435 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59436 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59437 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59438 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59439 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59440 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59441 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59442 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59443 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59444 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59445 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59446 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59447 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59448 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59449 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59450 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59451 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59452 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59453 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59454 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59455 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59456 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59457 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59458 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59459 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59460 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59461 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59462 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59463 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59464 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59465 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59466 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59467 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59468 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59469 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59470 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59471 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59472 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59473 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59474 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59475 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59476 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59477 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59478 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59479 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59480 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59481 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59482 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59483 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59484 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59485 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59486 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59487 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59488 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59489 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59490 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59491 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59492 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59493 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59494 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59495 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59496 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59497 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59498 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59499 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59500 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59501 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59502 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59503 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59504 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59505 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59506 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59507 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59508 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59509 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59510 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59511 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59512 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59513 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59514 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59515 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59516 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59517 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59518 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59519 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59520 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59521 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59522 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59523 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59524 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59525 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59526 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59527 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59528 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59529 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59530 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59531 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59532 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59533 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59534 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59535 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59536 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59537 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59538 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59539 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59540 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59541 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59542 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59543 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59544 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59545 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59546 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59547 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59548 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59549 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59550 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59551 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59552 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59553 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59554 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59555 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59556 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59557 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
59558 … //Access:RW DataWidth:0x1 // Per-PF drop configuration to be used for main and LB traffic of…
59561 …0cUL //Access:R DataWidth:0x18 // TX SOP descriptor queue empty status - for main traffic que…
59562 …c10UL //Access:R DataWidth:0x18 // TX SOP descriptor queue full status - for main traffic que…
59563 … DataWidth:0x40 // Addresses for TimeSync related registers in the timesync generator sub-module.
59567 …1 // Output enable for the STORM interface. This configuration should be static during run-time.
59580 …00UL //Access:RW DataWidth:0x4 // Size of the proprietary header, in 32-bit words, that is pr…
59582 …501008UL //Access:RW DataWidth:0x1 // Packet has Ethernet FCS field. Set this bit to indicat…
59586 …-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer tag);…
59587 … 0x50101cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59588 … 0x501020UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59589 … 0x501024UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59590 … 0x501028UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59591 … 0x50102cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59592 … 0x501030UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59593 … 0x501034UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59594 …-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer tag);…
59595 … 0x50103cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59596 … 0x501040UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59597 … 0x501044UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59598 … 0x501048UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59599 … 0x50104cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59600 … 0x501050UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59601 … 0x501054UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59603 … (0x1<<0) // Enable bit for Ethernet-over-GRE (L2 GRE) encaps…
59605 … (0x1<<1) // Enable bit for IP-over-GRE (IP GRE) encaps…
59612 … 0x501068UL //Access:RW DataWidth:0x10 // FCOE Ethertype - default is 0x8906.
59617 … 0x50107cUL //Access:RW DataWidth:0x8 // IPv4 protocol field for ICMPv4 - defaults to 0x01.
59618 … 0x501080UL //Access:RW DataWidth:0x8 // IPv6 next header field for ICMPv6 - defaults to 0x3A.
59651 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_0: 0 - IPv6; 1-IPv4.
59652 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_1: 0 - IPv6; 1-IPv4.
59653 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_2: 0 - IPv6; 1-IPv4.
59761 … for forwarding packets for each PF to MCP in multifunction mode. This is a per-PF split register.
59863 … forwarding packets for the PF to the host in multifunction mode. This is a per-PF split register.
59885 … (0x1<<0) // L2 filter rule enable. Set this bit to enable …
59889 …for comparison. A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-80-C2-00-00-0F.
60005 … (0x1<<0) // L2 filter (for not forwarding to the host) rule enable. Set this bit to enable …
60009 … for comparison. A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-80-C2-00-00-0F.
60124 … forwarding packets to the host for this port. No packet is forwarded to BRB when this bit is set.
60125 …isable bit for forwarding packets to the host. No packet is forwarded to BRB when this bit is set.
60126 …ket with classification failed status is forwarded to BRB when this bit is set in multifunction mo…
60127 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60147 …- message FIFO empty. Bit 1 - descriptor FIFO empty. Bit 2 - message FIFO has more than 32 entries…
60148 …-to-send data remaining below which ETS arbiter for the LB path should start selecting the next pa…
60149 …501504UL //Access:RW DataWidth:0x1 // Packet has Ethernet FCS field. Set this bit to indicat…
60150 … 0x501508UL //Access:RW DataWidth:0x1 // Zero-padding enable for LB packets. Set thi…
60156 … DataWidth:0x20 // Increment PERIOD for the BRB interface rate limiter - in term of 25MHz clo…
60157 …W DataWidth:0x20 // Increment VALUE for the BRB interface rate limiter - in term of bytes, cy…
60158 … DataWidth:0x20 // Upper bound VALUE for the BRB interface rate limiter - in term of bytes, cy…
60161 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60163 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60166 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60168 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60171 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60173 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60176 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60178 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60181 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60183 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60186 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60188 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60191 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60193 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60196 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60198 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60200 …40UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60201 …44UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60202 …48UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60203 …4cUL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60204 …50UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60205 …54UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60206 …58UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60207 …5cUL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60208 …560UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60209 …564UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60210 …568UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60211 …56cUL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60212 …570UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60213 …574UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60214 …578UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60215 …57cUL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60216 …0UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60217 …4UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60218 …8UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60219 …cUL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60220 …0UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60221 …4UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60222 …8UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60223 …cUL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60232 …-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6-TC5 traf…
60233 …lient): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6…
60234 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60235 …-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6-TC5 traf…
60237 …Set these bits to have the round-robin arbiter stays on the winning input instead of moving to the…
60239 … 0x5015e0UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbitration mo…
60260 …0x501634UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60261 …0x501638UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60262 …0x50163cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60263 …0x501640UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60264 …0x501644UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60265 …0x501648UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60266 …0x50164cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60267 …0x501650UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60268 …0x501654UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60269 …0x501658UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60270 …isable bit for forwarding packets to the host. No packet is forwarded to BRB when this bit is set.
60271 …ket with classification failed status is forwarded to BRB when this bit is set in multifunction mo…
60272 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60291 … 0x501908UL //Access:RW DataWidth:0x1 // Set to 1 to enable PTP …
60292 … 0x50190cUL //Access:RW DataWidth:0x1 // Set to 1 to enable PTP …
60293 …-specified packet timestamp mode. NIG will capture the timestamp value of the packet that SW indi…
60297 …Set each bit to 1 to mask out the particular parameter. 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1…
60298 …Set each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP …
60299 …Set each bit to 1 to mask out the particular parameter. 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1…
60300 …Set each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP …
60301 …s:RW DataWidth:0x11 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60302 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60303 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60304 …s:RW DataWidth:0x11 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60305 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60306 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60307 …s:RW DataWidth:0x13 // Packet TimeSync information that is buffered in 1-deep FIFOs for TX sid…
60308 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
60309 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
60310 …-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp val…
60311 …-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp val…
60312 … 0x50195cUL //Access:RW DataWidth:0x1 // Multifunction mode enable. Set this bit to perform…
60313 … protocol. 3: dual-stage classification. When no classification is performed in multifunction mode…
60314 …Set this register to select the resolution method for combining the results from the two stages in…
60315 …-port value to be used when protocol-based classification fails. This is the per-port per-PF ID (…
60316 …-port value to be used when outer-tag/inner VLAN/MAC classification fails. This is the per-port …
60317 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60318 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60319 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60320 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60321 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60322 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60323 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60324 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60325 …-bit field immediately following the Ethertype to be used for each of the outer tag value bit. The…
60329 … 0x5019a0UL //Access:RW DataWidth:0x10 // Outer tag value mask. Set a bit to 0 to mask …
60330 …-port per-PF register. This register selects the classification type for the tag/VLAN/MAC mode. …
60331 … 0x5019b0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60333 … 0x5019c0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60335 … 0x5019d0UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. Per-function…
60337 …h:0x1 // This is a per-port per-PF register. Per-function no outer tag/inner VLAN configuratio…
60338 …er-port per-PF register. Per-function MAC addresses to be matched with for MAC-address-based clas…
60340 … 0x501a80UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60342 …-port per-PF register. Per-function mode select bit to indicate whether the filter is to be used …
60344 …-port per-PF register. Per-function select bits for the different protocol types to be evaluated …
60346 … 0x501b40UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60348 …e. 0 selects connection-based classification. 1 selects the PF-based classification. This regist…
60349 …-tuple search for TCP packets. Set this bit to use the TCP 4-tuple (TCP source and destination po…
60350 …-tuple search for UDP packets. Set this bit to use the UDP 4-tuple (UDP source and destination po…
60351 …ed to hash the data string in connection-based engine classification. This register is used only …
60352 …-entry Engine ID lookup table, with 1 bit per entry. Set the bit to 1 to have packets associated …
60354 …ts one of the 24-bit destination QP bits to be used as the engine ID. Valid values are 0-23. Thi…
60355 …-global-PF engine ID to be used in PF-based engine classification. Set the bit to 1 to have packe…
60356 …ss:RW DataWidth:0x3 // Flow control mode. 0 - disable; 1 - PFC; 2 - LLFC; 3 - PPP; 4 - PAUSE…
60357 … 0x501ba4UL //Access:RW DataWidth:0x20 // Eight 4-bit configurations for specifying which TC (…
60359 …values are 2-5 for selecting one of the L2 tags 2-5. This field is evaluated only when the select…
60361 …(0xf<<3) // Bit offset in the outer tag starting from which to extract the 3-bit packet priority i…
60363 …f<<7) // Bit offset in the selected tag starting from which to extract the 3-bit packet priority i…
60365 …Set a bit to 1 to force 'full' condition. This is meant to allow BRB configuration change during …
60366 …n is applicable to both RX and LB interfaces to the BRB of the same port. Set a bit to 1 to force…
60367 …/Access:RW DataWidth:0x8 // Per-TC flow control enable for received XOFF requests to pause tr…
60368 …01bb8UL //Access:RW DataWidth:0x8 // Per-TC flow control enable for XOFF messages sent to the…
60369 …L //Access:RW DataWidth:0x9 // Per-TC flow control enable for received XOFF requests to pause…
60370 …DataWidth:0x1 // Enable bit for the no-drop-hdr-ind field of the LB-only-header. When set, the…
60371 …-drop of LB packets with the no-drop-hdr-ind bit set due to per-TC full backpressure from the BRB.…
60372 …cifies the number of 256-bit cycles, starting from the SOP cycle, of the packet not to be dropped …
60373 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60374 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60375 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60376 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60377 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60378 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60379 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60380 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60381 …-map indicating which received SAFC/PFC priorities to map to the TC. A priority is mapped to the …
60382 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60383 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60384 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60385 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60386 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60387 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60388 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60393 …ode enable. Set this bit to enable drain mode. Drain mode starts immediately upon assertion and s…
60394 …CP traffic. Set this bit to enable drain mode. Drain mode starts immediately upon assertion and …
60395 …Set these bits to enable the drain mode for TC0 and TC7. Bit 0 is for TC0 flow. Bit 7 is for TC7 …
60396 …Set these bits to enable the drain mode for TC0 and TC7. Bit 0 is for TC0 flow. Bit 8 is for TC8 …
60397 …12) / (data rate in Gbps x core clock period in ns). The default value is set for XOFF time of 0x…
60406 … 0x501c50UL //Access:RW DataWidth:0x1 // Set this bit to clear t…
60407 …P internal write interface. This configuration should be static while flowctrl_mode is set to PPP.
60408 …P internal write interface. This configuration should be static while flowctrl_mode is set to PPP.
60409 …XP internal write interface. This configuration should be static while flowctrl_mode is set to PPP.
60410 …XP internal write interface. This configuration should be static while flowctrl_mode is set to PPP.
60436 … // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statist…
60454 …dropped due to buffer full. This is an RF generated RC statistics register - reading this registe…
60455 …uncated due to buffer full. This is an RF generated RC statistics register - reading this registe…
60497 … // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statist…
60498 …the TX packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the MCP/per…
60499 …egister for the number of TX packets that have the per-PF drop or per-VPORT drop configuration set…
60500 …f the LB packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the per-T…
60501 …-PF drop or per-VPORT drop configuration set while the no-drop-hdr-ind in the packet is cleared. T…
60568 …ets from BMB to be forwarded to the host that got truncated due to BRB LB per-TC full backpressure.
60569 …ckets from BMB to be forwarded to the host that got dropped due to BRB LB per-TC full backpressure.
60570 … 0x501f08UL //Access:RW DataWidth:0x1 // Zero-padding enable for TX packets. Set thi…
60576 …-to-transmit data remaining below which ETS arbiter for the transmit path should start selecting …
60584 …ccess:RW DataWidth:0x20 // Increment PERIOD for the global rate limiter - in term of 25MHz clo…
60585 …Access:RW DataWidth:0x20 // Increment VALUE for the global rate limiter - in term of bytes, cy…
60586 …cess:RW DataWidth:0x20 // Upper bound VALUE for the global rate limiter - in term of bytes, cy…
60589 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60590 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60591 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60592 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60594 …Set these bits to have the round-robin arbiter stays on the winning input instead of moving to the…
60596 … 0x501f50UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbitration mo…
60597 … 0x501f54UL //Access:RW DataWidth:0x1 // Set this bit to disable…
60622 …0x501fb8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60623 …0x501fbcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60624 …0x501fc0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60625 …0x501fc4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60626 …0x501fc8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60627 …0x501fccUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60628 …0x501fd0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60629 …0x501fd4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60630 …0x501fd8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60631 …0x501fdcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60632 …0x501fe0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60633 …0x501fe4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60871 …erride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bi…
60872 …erride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bi…
60889 …n the BMC-to-host path to BRB. This is also used in the TX management path (when enabled by *tx_m…
60890 … // Enable the use of TC to control the flow of TX management traffic. Set this bit to 1 to en…
60891 … 0x50209cUL //Access:RW DataWidth:0x1 // Host-to-MCP path enable. Set this bit…
60892 …taWidth:0x1 // Indicate to timestamp the packet from MCP to network when *_ptp_sw_txtsen is set.
60895 … 0x5020acUL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
60900 … 0x5020c0UL //Access:RW DataWidth:0x7 // Almost-full threshold for DO…
60904 …. 0 - send debug traffic through port 0. 1 - send debug traffic through port 1. 2 - send debug tr…
60907 … 0x5020dcUL //Access:RW DataWidth:0x8 // Almost-full threshold for de…
60910 …- the number of valid bytes in the last cycle (0=all bytes are valid); [261]eop - active on the la…
60953 …-port per-PF register. L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L…
60954 …W DataWidth:0x1 // This is a per-port per-PF register. Proprietary header removal configurat…
60955 … DataWidth:0x1 // Set this bit to enable ACPI pattern matching and TCP SYN matching in multi-…
60956 … 0x50800cUL //Access:RW DataWidth:0x1 // Set this bit to enable …
60957 … 0x508080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
60959 …8100UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. When this bit is set…
60960 … 0x508104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60961 … 0x508108UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60962 … 0x50810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60963 … 0x508110UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60964 … 0x508114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60965 … 0x508118UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60966 … 0x50811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60967 … 0x508120UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60968 … 0x508124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60969 … 0x508128UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60970 … 0x50812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60971 … 0x508130UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60972 … 0x508134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60973 … 0x508138UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60974 … 0x50813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60975 … 0x508140UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60976 … is a per-port per-PF register. Set bit 0 to enable wake on IPv4 TCP SYN. Set bit 1 to enable wak…
60977 …-port per-PF register. Enable bits for fields to be compared if IPv6 is present in the packet. B…
60978 …-port per-PF register. Enable bits for fields to be compared if IPv4 is present in the packet. B…
60979 … 0x508150UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60980 … 0x508154UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60981 … 0x508158UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60982 … 0x50815cUL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60983 … 0x508160UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60985 … 0x508170UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60987 … 0x508180UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60988 … 0x508184UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60989 …8188UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. When this bit is set…
60990 … 0x508190UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
60992 … 0x508198UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high …
60993 … 0x5081a0UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wa…
60995 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
60996 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
60997 … 0x5081c8UL //Access:R DataWidth:0xe // Wake packet length - the actual length of…
60998 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
60999 …s:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
61001 …s:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
61019 …ARD � insert timestamp using standard IPv4 Timestamp option. In this mode 32-bit timestamp with se…
61022 …RW DataWidth:0x5 // Global timestamp shift for the free running counter. Legal values are 0-16
61026 …acket information that is buffered in 1-deep FIFOs. Bits [15:0] return the sequence ID of the pac…
61027 …ataWidth:0x40 // RX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp …
61029 …ataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Source add…
61031 …acket information that is buffered in 1-deep FIFOs. Bits [15:0] return the sequence ID of the pac…
61032 …ataWidth:0x40 // TX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp …
61034 …ataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Destinatio…
61050 … 0x5088e0UL //Access:RW DataWidth:0x4 // Bits 3:0 are the active-low output enables fo…
61052 …FO data bytes occupancy is higher than this threshold nig_dorq_edpm_en is de-asserted. The value i…
61059 … // This field maps (ipv4_tos >> 2) 6 bits to 6 bits: bits 5:3 - priority bits 2:0 - TC This co…
61065 …-port register L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L2 tags 0…
61066 …s:RW DataWidth:0x1 // This is a per-port register. Proprietary header removal configuration …
61067 … 0x508b18UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61068 … 0x508b1cUL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61069 … 0x508b20UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61070 … 0x508b24UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61071 … 0x508b28UL //Access:RW DataWidth:0x1 // This is a per-port register. Enabl…
61072 … 0x508b2cUL //Access:RW DataWidth:0x1 // This is a per-port register. Enable…
61073 … 0x508b30UL //Access:RW DataWidth:0x1 // This is a per-port register. Perfo…
61074 … 0x508b34UL //Access:RW DataWidth:0x10 // This is a per-port register. Next …
61075 …-port register. Destination port value used to designate a NGE header following the UDP header. M…
61076 … 0x508b3cUL //Access:RW DataWidth:0x18 // This is a per-port register which d…
61152 …hen this bit is enabled, instead of sending frame[0] from dbgmux, NIG will set an indication that …
61159 … 0x508b78UL //Access:RW DataWidth:0x1 // When this bit is set and there is a pari…
61161 …nables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.
61162 …nables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.
61163 …t reisters. This enables credit sharing with one of the BTB TCs. 0: MNG. 1-8: BTB per TC. 9: B…
61192 …ther to use the MPA CRC calculation on one fully contained PDU (legacy mode - 0) or on multiple PD…
61193 …MAC addresses to be matched with for MAC-address-based classification. This register is also used…
61197 …ter is to be used for MAC-addresss based classification or protocol-based classification. Set thi…
61199 …-based classification mode: bit 0: compare the Ethertype; bit 1: compare the TCP source port; bit …
61203 …ers for every PPF. bits [4:3] are the port ID, bits 2:0 are the PPF ID The set of rlevent configur…
61207 …//Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic …
61209 … 0x50d800UL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
61214 …s_ipv4_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
61215 …s_ipv6_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
61216 …s_ipv4_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
61253 …Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers…
61254 …Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers…
61255 …set when initialization of all BRTB registers and memories is finished. BRTB will fill all prefetc…
61290 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
61292 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
61294 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
61296 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
61298 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
61300 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
61302 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
61304 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
61306 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
61308 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
61310 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
61312 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
61314 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
61316 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
61318 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
61320 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
61446 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
61448 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
61450 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
61452 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
61454 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
61456 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
61458 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
61460 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
61462 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
61464 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
61466 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
61468 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
61470 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
61472 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
61474 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
61476 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
61478 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
61480 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
61482 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
61484 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
61486 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
61488 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
61490 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
61492 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
61494 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
61496 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
61498 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
61500 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
61670 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
61672 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
61674 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
61676 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
61678 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
61680 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
61682 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
61684 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
61686 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
61688 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
61690 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
61692 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
61694 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
61696 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
61698 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
61700 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
61702 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
61704 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
61706 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
61708 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
61710 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
61712 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
61714 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
61716 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
61718 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
61720 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
61892 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
61894 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
61896 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
61898 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
61900 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
61902 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
61904 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
61906 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
61908 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
61910 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
61912 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
61914 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
61916 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
61918 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
61920 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
61922 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
61924 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
61926 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
61928 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
61930 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
61932 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
61934 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
61936 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
61938 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
61940 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
61942 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
61944 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
61946 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
61948 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
61950 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
61952 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
62136 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
62138 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
62140 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
62142 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
62144 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
62146 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
62148 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
62150 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
62152 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
62154 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
62156 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
62158 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
62160 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
62162 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
62164 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
62166 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
62168 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
62170 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
62172 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
62174 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
62176 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
62178 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
62180 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
62182 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
62184 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
62186 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
62188 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
62360 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
62362 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
62364 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
62366 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
62368 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
62370 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
62372 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
62374 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
62376 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
62378 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
62380 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
62382 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
62384 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
62386 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
62388 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
62390 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
62392 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
62394 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
62396 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
62398 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
62400 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
62402 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
62404 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
62406 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
62408 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
62410 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
62412 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
62414 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
62416 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
62598 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
62600 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
62602 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
62604 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
62606 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
62608 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
62610 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
62612 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
62614 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
62616 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
62618 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
62620 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
62622 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
62624 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
62626 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
62628 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
62630 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
62632 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
62634 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
62636 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
62638 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
62640 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
62642 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
62644 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
62646 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
62648 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
62650 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
62652 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
62654 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
62656 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
62846 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
62848 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
62850 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
62852 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
62854 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
62856 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
62858 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
62860 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
62862 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
62864 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
62866 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
62868 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
62870 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
62872 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
62874 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
62876 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
62878 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
62880 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
62882 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
62884 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
62886 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
62888 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
62890 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
62892 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
62894 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
62896 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
62898 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
62900 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
62902 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
62904 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
62906 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
62908 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
63106 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
63108 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
63110 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
63112 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
63114 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
63116 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
63118 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
63120 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
63122 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
63124 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
63126 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
63128 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
63130 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
63132 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
63134 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
63136 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
63138 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
63140 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
63142 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
63144 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
63146 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
63148 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
63150 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
63152 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
63154 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
63156 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
63158 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
63160 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
63162 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
63164 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
63166 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
63168 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
63376 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
63378 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
63380 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
63382 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
63384 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
63386 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
63388 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
63390 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
63392 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
63394 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
63396 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
63398 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
63400 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
63402 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
63404 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
63406 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
63408 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
63410 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
63412 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
63414 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
63416 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
63418 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
63420 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
63422 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
63424 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
63426 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
63428 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
63430 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
63432 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
63434 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
63436 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
63438 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
63440 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
63442 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
63444 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
63446 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
63448 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
63612 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
63614 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
63616 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
63618 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
63620 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
63656 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
63658 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
63660 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
63662 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
63664 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
63689 … (0x1<<0) // This bit masks, when set, the Parity bit: BM…
63691 … (0x1<<1) // This bit masks, when set, the Parity bit: BM…
63693 … (0x1<<2) // This bit masks, when set, the Parity bit: BM…
63695 … (0x1<<3) // This bit masks, when set, the Parity bit: BM…
63697 … (0x1<<4) // This bit masks, when set, the Parity bit: BM…
63700 … (0x1<<0) // This bit masks, when set, the Parity bit: BM…
63702 … (0x1<<1) // This bit masks, when set, the Parity bit: BM…
63704 … (0x1<<2) // This bit masks, when set, the Parity bit: BM…
63706 … (0x1<<3) // This bit masks, when set, the Parity bit: BM…
63708 … (0x1<<4) // This bit masks, when set, the Parity bit: BM…
63710 … (0x1<<5) // This bit masks, when set, the Parity bit: BM…
63712 … (0x1<<6) // This bit masks, when set, the Parity bit: BM…
63714 … (0x1<<7) // This bit masks, when set, the Parity bit: BM…
63716 … (0x1<<8) // This bit masks, when set, the Parity bit: BM…
63718 … (0x1<<9) // This bit masks, when set, the Parity bit: BM…
63720 … (0x1<<10) // This bit masks, when set, the Parity bit: BM…
63722 … (0x1<<11) // This bit masks, when set, the Parity bit: BM…
63724 … (0x1<<12) // This bit masks, when set, the Parity bit: BM…
63726 … (0x1<<13) // This bit masks, when set, the Parity bit: BM…
63728 … (0x1<<14) // This bit masks, when set, the Parity bit: BM…
63730 … (0x1<<15) // This bit masks, when set, the Parity bit: BM…
63732 … (0x1<<16) // This bit masks, when set, the Parity bit: BM…
63734 … (0x1<<17) // This bit masks, when set, the Parity bit: BM…
63736 … (0x1<<18) // This bit masks, when set, the Parity bit: BM…
63738 … (0x1<<19) // This bit masks, when set, the Parity bit: BM…
63740 … (0x1<<20) // This bit masks, when set, the Parity bit: BM…
63742 … (0x1<<21) // This bit masks, when set, the Parity bit: BM…
63744 … (0x1<<22) // This bit masks, when set, the Parity bit: BM…
63746 … (0x1<<23) // This bit masks, when set, the Parity bit: BM…
63748 … (0x1<<24) // This bit masks, when set, the Parity bit: BM…
63750 … (0x1<<25) // This bit masks, when set, the Parity bit: BM…
63752 … (0x1<<26) // This bit masks, when set, the Parity bit: BM…
63754 … (0x1<<27) // This bit masks, when set, the Parity bit: BM…
63756 … (0x1<<28) // This bit masks, when set, the Parity bit: BM…
63758 … (0x1<<29) // This bit masks, when set, the Parity bit: BM…
63760 … (0x1<<30) // This bit masks, when set, the Parity bit: BM…
63762 … (0x1<<16) // This bit masks, when set, the Parity bit: BM…
63764 … (0x1<<17) // This bit masks, when set, the Parity bit: BM…
63766 … (0x1<<18) // This bit masks, when set, the Parity bit: BM…
63768 … (0x1<<19) // This bit masks, when set, the Parity bit: BM…
63770 … (0x1<<20) // This bit masks, when set, the Parity bit: BM…
63772 … (0x1<<21) // This bit masks, when set, the Parity bit: BM…
63774 … (0x1<<22) // This bit masks, when set, the Parity bit: BM…
63776 … (0x1<<23) // This bit masks, when set, the Parity bit: BM…
63778 … (0x1<<24) // This bit masks, when set, the Parity bit: BM…
63780 … (0x1<<25) // This bit masks, when set, the Parity bit: BM…
63782 … (0x1<<26) // This bit masks, when set, the Parity bit: BM…
63784 … (0x1<<27) // This bit masks, when set, the Parity bit: BM…
63786 … (0x1<<28) // This bit masks, when set, the Parity bit: BM…
63788 … (0x1<<29) // This bit masks, when set, the Parity bit: BM…
63790 … (0x1<<30) // This bit masks, when set, the Parity bit: BM…
63793 … (0x1<<11) // This bit masks, when set, the Parity bit: BM…
63795 … (0x1<<0) // This bit masks, when set, the Parity bit: BM…
63797 … (0x1<<12) // This bit masks, when set, the Parity bit: BM…
63799 … (0x1<<1) // This bit masks, when set, the Parity bit: BM…
63801 … (0x1<<2) // This bit masks, when set, the Parity bit: BM…
63803 … (0x1<<3) // This bit masks, when set, the Parity bit: BM…
63805 … (0x1<<4) // This bit masks, when set, the Parity bit: BM…
63807 … (0x1<<5) // This bit masks, when set, the Parity bit: BM…
63809 … (0x1<<6) // This bit masks, when set, the Parity bit: BM…
63811 … (0x1<<7) // This bit masks, when set, the Parity bit: BM…
63813 … (0x1<<8) // This bit masks, when set, the Parity bit: BM…
63815 … (0x1<<9) // This bit masks, when set, the Parity bit: BM…
63817 … (0x1<<10) // This bit masks, when set, the Parity bit: BM…
63819 … (0x1<<11) // This bit masks, when set, the Parity bit: BM…
63821 … (0x1<<12) // This bit masks, when set, the Parity bit: BM…
63823 … (0x1<<13) // This bit masks, when set, the Parity bit: BM…
63825 … (0x1<<14) // This bit masks, when set, the Parity bit: BM…
63827 … (0x1<<0) // This bit masks, when set, the Parity bit: BM…
63829 … (0x1<<15) // This bit masks, when set, the Parity bit: BM…
63831 … (0x1<<1) // This bit masks, when set, the Parity bit: BM…
63833 … (0x1<<16) // This bit masks, when set, the Parity bit: BM…
63835 … (0x1<<17) // This bit masks, when set, the Parity bit: BM…
63837 … (0x1<<18) // This bit masks, when set, the Parity bit: BM…
63839 … (0x1<<19) // This bit masks, when set, the Parity bit: BM…
63841 … (0x1<<20) // This bit masks, when set, the Parity bit: BM…
63843 … (0x1<<13) // This bit masks, when set, the Parity bit: BM…
63845 … (0x1<<21) // This bit masks, when set, the Parity bit: BM…
63847 … (0x1<<14) // This bit masks, when set, the Parity bit: BM…
63849 … (0x1<<22) // This bit masks, when set, the Parity bit: BM…
63851 … (0x1<<2) // This bit masks, when set, the Parity bit: BM…
63853 … (0x1<<3) // This bit masks, when set, the Parity bit: BM…
63855 … (0x1<<4) // This bit masks, when set, the Parity bit: BM…
63857 … (0x1<<5) // This bit masks, when set, the Parity bit: BM…
63859 … (0x1<<6) // This bit masks, when set, the Parity bit: BM…
63861 … (0x1<<7) // This bit masks, when set, the Parity bit: BM…
63863 … (0x1<<8) // This bit masks, when set, the Parity bit: BM…
63865 … (0x1<<9) // This bit masks, when set, the Parity bit: BM…
63867 … (0x1<<10) // This bit masks, when set, the Parity bit: BM…
63919 …_I_ECC_PRTY (0x1<<0) // Set parity only for mem…
63921 …_I_ECC_PRTY (0x1<<1) // Set parity only for mem…
63923 …_I_ECC_PRTY (0x1<<2) // Set parity only for mem…
63925 …_I_ECC_PRTY (0x1<<3) // Set parity only for mem…
63927 …_I_ECC_PRTY (0x1<<4) // Set parity only for mem…
63929 …_I_ECC_PRTY (0x1<<5) // Set parity only for mem…
63931 …_I_ECC_PRTY (0x1<<6) // Set parity only for mem…
63933 …_I_ECC_PRTY (0x1<<7) // Set parity only for mem…
63935 …_I_ECC_PRTY (0x1<<8) // Set parity only for mem…
63937 …_I_ECC_PRTY (0x1<<9) // Set parity only for mem…
63939 …I_ECC_PRTY (0x1<<10) // Set parity only for mem…
63941 …I_ECC_PRTY (0x1<<11) // Set parity only for mem…
63943 …I_ECC_PRTY (0x1<<12) // Set parity only for mem…
63945 …I_ECC_PRTY (0x1<<13) // Set parity only for mem…
63947 …I_ECC_PRTY (0x1<<14) // Set parity only for mem…
63949 …I_ECC_PRTY (0x1<<15) // Set parity only for mem…
63985 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
63986 …04UL //Access:RW DataWidth:0xa // Number of valid bytes in header in 16-bytes resolution. Aft…
63994 … DataWidth:0x3 // There is bit for each PACKET read client. When bit is set then read client wi…
63995 … shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) R…
64009 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64010 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64011 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64012 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64013 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64014 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64015 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64016 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64017 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64018 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64019 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64020 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64021 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64022 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64023 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64024 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64025 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64026 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64027 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64033 …s set then packet will be read without dead cycles.TBD ::s/NO_DEAD_CYCLE_RST/1/g in Reset Value::s…
64035 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64037 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64039 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64041 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64043 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64045 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64047 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64049 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64051 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64053 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64055 …for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then packet will be…
64056 …for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then highest priori…
64057 …is is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
64058 …cket request of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
64059 …h multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is high…
64089 …set then appropriate interface is enabled. When bit is reset then request from that interface will…
64091 …set then appropriate interface is enabled. When bit is reset then request from that interface will…
64093 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
64096 …set then appropriate interface is enabled. When bit is reset then valid to that interface will nev…
64098 …set then appropriate interface is enabled. When bit is reset then valid to that interface will nev…
64100 …AC port. When bit is set then pause interface is enabled. When bit is reset then any pause will ne…
64102 …bit is set then packet avalable interface is enabled. When bit is reset then packet avalable inter…
64104 …t is set then power management interface is enabled. When bit is reset then power management int…
64106 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64107 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64108 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64109 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64110 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64111 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64112 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64113 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64114 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64115 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64128 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64129 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64130 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64131 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64132 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64133 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64134 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64135 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64136 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64137 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64138 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64139 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64140 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64141 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64142 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64143 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64144 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64145 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64146 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64147 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64148 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64149 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64150 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64151 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64152 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64153 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64154 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64155 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64156 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64157 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64158 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64159 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64160 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
64252 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
64254 …s register for each erad packet client interface: TBD. Message spelling (MSB->LSB): rest_size_erro…
64257 …s register for each read packet client interface: TBD. Message spelling (MSB->LSB): opaque[1:0]; r…
64280 …Access:RW DataWidth:0xc // Link list dual port memory that contains per-block descriptor::s/B…
64285 … 0x560000UL //Access:RW DataWidth:0x1 // Initiate the ATC array - reset all the valid …
64287 …taWidth:0x20 // Logging register for reuse miss on transpend entry [31:0] - TID of the problemat…
64288 …taWidth:0x1c // Logging register for reuse miss on transpend entry [27:0] - ATC page index of th…
64289 …gister for reuse miss on transpend entry [11:0] - Reuse count of the problematic lookuprequest [23…
64290 …ster for the case of invalidation halt (lkpres of invalidated range) [31:0] - TID of the problemat…
64291 …ster for the case of invalidation halt (lkpres of invalidated range) [27:0] - ATC page index of th…
64292 …ster for the case of invalidation halt (lkpres of invalidated range) [11:0] - Reuse count of the p…
64294 …s of the PXP read requests issued by the PTU logic. [0:8] - ST index; [10:9] - ST hint; [11] - ST …
64299 …C DataWidth:0x10 // Counter for the number of PTU read responses retunring with error flag set.
64301 … 0x560078UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per PF.
64303 …hould take place. When invalidation operation is done, the corresponding bit in inv_tid_done is set
64304 …aWidth:0x1 // Bit per PF. Indicates that the marked invalidation is done - when read it is also…
64305 … 0x560088UL //Access:RW DataWidth:0x1 // Bit per PF. If set, the block halts in…
64306 … 0x56008cUL //Access:RW DataWidth:0x1 // When set - the block will hal…
64307 … 0x560090UL //Access:RW DataWidth:0x3 // Max credits of the PBF->PXP interface.
64308 … 0x560094UL //Access:RW DataWidth:0x3 // Max credits of the PRM->PXP interface.
64309 … 0x560098UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64310 … 0x56009cUL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64311 … 0x5600a0UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64320 …he ATC. If de-asserted then low priority request will replace a high priority entry only if there …
64339 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64345 … (0x1<<4) // Indicates TCPL response with error code set.
64347 … (0x1<<5) // Indicates Lookup to invalidated range with inv_halt_on_err set
64354 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
64356 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
64358 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
64360 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
64362 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
64364 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
64366 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
64368 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
64373 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64379 … (0x1<<4) // Indicates TCPL response with error code set.
64381 … (0x1<<5) // Indicates Lookup to invalidated range with inv_halt_on_err set
64390 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64396 … (0x1<<4) // Indicates TCPL response with error code set.
64398 … (0x1<<5) // Indicates Lookup to invalidated range with inv_halt_on_err set
64405 … (0x1<<0) // This bit masks, when set, the Parity bit: PT…
64407 … (0x1<<1) // This bit masks, when set, the Parity bit: PT…
64409 … (0x1<<3) // This bit masks, when set, the Parity bit: PT…
64411 … (0x1<<2) // This bit masks, when set, the Parity bit: PT…
64413 … (0x1<<4) // This bit masks, when set, the Parity bit: PT…
64415 … (0x1<<3) // This bit masks, when set, the Parity bit: PT…
64417 … (0x1<<5) // This bit masks, when set, the Parity bit: PT…
64419 … (0x1<<4) // This bit masks, when set, the Parity bit: PT…
64421 … (0x1<<6) // This bit masks, when set, the Parity bit: PT…
64423 … (0x1<<5) // This bit masks, when set, the Parity bit: PT…
64425 … (0x1<<7) // This bit masks, when set, the Parity bit: PT…
64427 … (0x1<<6) // This bit masks, when set, the Parity bit: PT…
64429 … (0x1<<17) // This bit masks, when set, the Parity bit: PT…
64431 … (0x1<<7) // This bit masks, when set, the Parity bit: PT…
64433 … (0x1<<8) // This bit masks, when set, the Parity bit: PT…
64435 … (0x1<<12) // This bit masks, when set, the Parity bit: PT…
64437 … (0x1<<9) // This bit masks, when set, the Parity bit: PT…
64439 … (0x1<<2) // This bit masks, when set, the Parity bit: PT…
64441 … (0x1<<10) // This bit masks, when set, the Parity bit: PT…
64443 … (0x1<<15) // This bit masks, when set, the Parity bit: PT…
64445 … (0x1<<11) // This bit masks, when set, the Parity bit: PT…
64447 … (0x1<<14) // This bit masks, when set, the Parity bit: PT…
64449 … (0x1<<12) // This bit masks, when set, the Parity bit: PT…
64451 … (0x1<<16) // This bit masks, when set, the Parity bit: PT…
64453 … (0x1<<13) // This bit masks, when set, the Parity bit: PT…
64455 … (0x1<<13) // This bit masks, when set, the Parity bit: PT…
64457 … (0x1<<14) // This bit masks, when set, the Parity bit: PT…
64459 … (0x1<<9) // This bit masks, when set, the Parity bit: PT…
64461 … (0x1<<15) // This bit masks, when set, the Parity bit: PT…
64463 … (0x1<<11) // This bit masks, when set, the Parity bit: PT…
64465 … (0x1<<16) // This bit masks, when set, the Parity bit: PT…
64467 … (0x1<<0) // This bit masks, when set, the Parity bit: PT…
64469 … (0x1<<1) // This bit masks, when set, the Parity bit: PT…
64471 … (0x1<<10) // This bit masks, when set, the Parity bit: PT…
64474 … 0x560214UL //Access:RW DataWidth:0x1 // Set parity only for mem…
64477 …00UL //Access:RW DataWidth:0x2 // Defines the number of sets - 3 - 512 ;2- 256; 1- 128; 0- 64.
64478 … 0x560404UL //Access:RW DataWidth:0x1 // If set the ATC will use only one way per set.
64483 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64484 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64485 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64486 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64487 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64488 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64489 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64490 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64491 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64492 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64493 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64494 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64509 …560480UL //Access:RW DataWidth:0x1 // CheckTags configuration bit - when set the available NP…
64510 … 0x560484UL //Access:RW DataWidth:0x8 // TAG threshold - for the checkTags fe…
64523 … 0x5604b8UL //Access:RC DataWidth:0x20 // Number of hits for Main-lookups in the ATC.
64525 … 0x5604c0UL //Access:RC DataWidth:0x20 // Number of treqs issued due to pre-lookup.
64530 … 0x5604d4UL //Access:RW DataWidth:0x1 // When this signal is set the statistics coun…
64568 … 0x56056cUL //Access:RW DataWidth:0x1 // Relevant only if hash_en is set. selects the CRC as…
64572 … //Access:R DataWidth:0x20 // Data belongs to an erroneous TCPL: [31:0]-bits [31:0] of the ad…
64573 … //Access:R DataWidth:0x14 // Data belongs to an erroneous TCPL: [19:0]-bits [51:32] of the a…
64578 … 0x560594UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 31-0.
64579 … 0x560598UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 63-32.
64580 … 0x56059cUL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 95-64.
64581 … 0x5605a0UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 127-96.
64582 … 0x5605a4UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 159-128.
64583 … 0x5605a8UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 191-160.
64584 … 0x5605acUL //Access:R DataWidth:0x10 // Indicates the end of FLI flow for PF 15-0.
64585 …b0UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 31-0 accordingly.
64586 …b4UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 63-32 accordingly.
64587 …8UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 95-64 accordingly.
64588 …cUL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 127-96 accordingly.
64589 …L //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 159-128 accordingly.
64590 …UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 191-160 accordingly.
64591 …c8UL //Access:RW DataWidth:0x10 // Clears the FLI done indication for PF bits 15-0 accordingly.
64592 … on implementation and should not be changed. Its value can't be bigger than the set dbg FIFO size.
64593 …UL //Access:RW DataWidth:0x1 // When set low priority lookup can replace high priority entry;…
64594 … 0x5605d4UL //Access:RW DataWidth:0x1 // When set Ireq event won't be…
64610 …605e4UL //Access:RW DataWidth:0x8 // Resource Type of the invalidated range - register per PF.
64612 …er for the case of invalidation halt (lkpres of invalidated range) [7:0] - Resource type of the…
64614 …x8 // Logging register for reuse miss on transpend entry bits [35:28] - of the problematic r…
64615 …Width:0x8 // Logging register for reuse miss on transpend entry [7:0] - Resource type of the…
64617 … 0x560600UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per Strom.
64621 … 0x560640UL //Access:RW DataWidth:0x8 // TID of the invalidated range - register per Storm.
64625 …hould take place. When invalidation operation is done, the corresponding bit in inv_tid_done is set
64627 …dth:0x1 // Bit per Storm. Indicates that the marked invalidation is done - when read it is also…
64629 … 0x5606c0UL //Access:RW DataWidth:0x1 // Bit per PF. If set, the block halts in…
64631 …x40 // Access the GPA table way 0; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64633 …x40 // Access the GPA table way 1; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64635 …x40 // Access the GPA table way 2; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64639 …h:0x40 // Access the GPA table way3; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID-…
64641 …- {par - [51]; NS bit - [50]; W bit - [49]; R bit - [48]; U bit - [47]; Priority bit - [46]; PLRU …
64643 … // Access the GPA table way 0; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64645 … // Access the GPA table way 1; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64647 … // Access the GPA table way 2; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64649 … // Access the GPA table way3; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64651 …- { Priority bit - [23]; PLRU - [22]; Err bit - [21]; invpend bit [20]; transpend bit - [19]; vali…
64658 … (0x1<<1) // Enables CDU Inputs -- Must be set for normal ope…
64660 … (0x1<<2) // Enables CDU Outputs -- Must be set for normal op…
64668 … (0x1<<6) // Masks all PCIE Errors for Load transactions. NOTE -- This is not connecte…
64722 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
64724 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
64726 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
64728 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
64730 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
64732 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
64734 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
64736 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
64739 … (0x1<<0) // This bit masks, when set, the Parity bit: CD…
64741 … (0x1<<4) // This bit masks, when set, the Parity bit: CD…
64743 … (0x1<<1) // This bit masks, when set, the Parity bit: CD…
64745 … (0x1<<2) // This bit masks, when set, the Parity bit: CD…
64747 … (0x1<<1) // This bit masks, when set, the Parity bit: CD…
64749 … (0x1<<3) // This bit masks, when set, the Parity bit: CD…
64751 … (0x1<<3) // This bit masks, when set, the Parity bit: CD…
64755 …n for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64757 …n for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64759 …n for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64761 …n for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64764 …n for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64766 …n for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64768 …n for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64770 …n for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64773 …n for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64775 …n for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64777 …n for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64779 …n for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64782 …n for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64784 …n for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64786 …n for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64788 …n for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64790 …th; Controls the Full signal to PXP. This register must never be set higher than 8 -- doing so wi…
64791 …ing L1 Memories when past this limit. This register must never be set higher than 13 -- doing so w…
64872 … (0xfff<<12) // Block waste within a page. this number equals to PageSize-NCIB*ContextSize.
64904 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64910 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64911 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64922 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64923 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64924 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64925 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64926 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64927 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64928 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64929 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64930 …0x5a0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64931 …0x5a0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64932 …0x5a0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64933 …0x5a003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64936 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
64945 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64947 … (0x1<<3) // Mini cache error - meaning that A load …
64949 … (0x1<<4) // Mini cache error - meaning that A load …
64954 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
64956 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
64958 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
64960 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
64962 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
64964 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
64971 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64973 … (0x1<<3) // Mini cache error - meaning that A load …
64975 … (0x1<<4) // Mini cache error - meaning that A load …
64984 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64986 … (0x1<<3) // Mini cache error - meaning that A load …
64988 … (0x1<<4) // Mini cache error - meaning that A load …
64993 … (0x1<<0) // This bit masks, when set, the Parity bit: PT…
64995 … (0x1<<1) // This bit masks, when set, the Parity bit: PT…
64997 … (0x1<<2) // This bit masks, when set, the Parity bit: PT…
64999 … (0x1<<3) // This bit masks, when set, the Parity bit: PT…
65001 … (0x1<<4) // This bit masks, when set, the Parity bit: PT…
65003 … (0x1<<5) // This bit masks, when set, the Parity bit: PT…
65005 … (0x1<<6) // This bit masks, when set, the Parity bit: PT…
65007 … (0x1<<7) // This bit masks, when set, the Parity bit: PT…
65010 … 0x5a0214UL //Access:RW DataWidth:0x1 // Set parity only for mem…
65013 … 0x5a0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65018 …the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configura…
65020 … (0x1<<2) // defines that only back-to-back aggregation is …
65022 … (0x1<<3) // When this flag is set, all input messages are treated as if their IncS…
65029 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
65031 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
65033 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
65035 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
65039 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
65041 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
65043 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
65045 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
65048 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
65050 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
65052 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
65054 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
65057 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
65059 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
65061 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
65063 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
65066 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
65068 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
65070 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
65072 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
65108 … 0x5a0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65109 … 0x5a0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65110 … 0x5a082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65111 … 0x5a0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65112 … 0x5a0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65113 … 0x5a0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65114 … 0x5a083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65115 … 0x5a0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65116 … 0x5a0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65117 … 0x5a0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65118 … 0x5a084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65119 … 0x5a0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65120 … 0x5a0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65121 … 0x5a0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65122 … 0x5a085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65123 … 0x5a0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65124 … 0x5a0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65125 … 0x5a0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65126 … 0x5a086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65127 … 0x5a0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65128 … 0x5a0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65129 … 0x5a0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65130 … 0x5a087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65131 … 0x5a0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65132 … 0x5a0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65133 … 0x5a0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65134 … 0x5a088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65135 … 0x5a0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65136 … 0x5a0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65137 … 0x5a0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65138 … 0x5a089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65139 … 0x5a08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65141 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
65143 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
65145 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
65147 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
65150 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
65152 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
65154 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
65156 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
65159 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
65161 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
65163 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
65165 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
65168 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
65170 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
65172 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
65174 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
65213 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
65215 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
65217 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
65219 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
65221 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65223 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65225 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65227 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65230 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0.
65232 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
65234 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 2.
65236 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
65239 … (0xf<<0) // the maximal number of children in a specific aggregation. for set 0.
65241 … (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
65243 … (0xf<<8) // the maximal number of children in a specific aggregation. for set 2.
65245 … (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
65248 …0xff<<0) // The value by which to increment the event-ID in case of successful aggregation. for se…
65250 …0xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for se…
65252 …xff<<16) // The value by which to increment the event-ID in case of successful aggregation. for se…
65254 …xff<<24) // The value by which to increment the event-ID in case of successful aggregation. for se…
65274 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65275 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65276 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65277 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65278 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65279 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65280 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65281 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65282 …0x5c0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65283 …0x5c0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65284 …0x5c0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65285 …0x5c003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65288 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
65297 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65299 … (0x1<<3) // Mini cache error - meaning that A load …
65301 … (0x1<<4) // Mini cache error - meaning that A load …
65306 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
65308 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
65310 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
65312 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
65314 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
65316 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
65323 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65325 … (0x1<<3) // Mini cache error - meaning that A load …
65327 … (0x1<<4) // Mini cache error - meaning that A load …
65336 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65338 … (0x1<<3) // Mini cache error - meaning that A load …
65340 … (0x1<<4) // Mini cache error - meaning that A load …
65345 … (0x1<<0) // This bit masks, when set, the Parity bit: YP…
65347 … (0x1<<1) // This bit masks, when set, the Parity bit: YP…
65349 … (0x1<<2) // This bit masks, when set, the Parity bit: YP…
65351 … (0x1<<3) // This bit masks, when set, the Parity bit: YP…
65353 … (0x1<<4) // This bit masks, when set, the Parity bit: YP…
65355 … (0x1<<5) // This bit masks, when set, the Parity bit: YP…
65357 … (0x1<<6) // This bit masks, when set, the Parity bit: YP…
65359 … (0x1<<7) // This bit masks, when set, the Parity bit: YP…
65362 … 0x5c0214UL //Access:RW DataWidth:0x1 // Set parity only for mem…
65365 … 0x5c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65370 …the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configura…
65372 … (0x1<<2) // defines that only back-to-back aggregation is …
65374 … (0x1<<3) // When this flag is set, all input messages are treated as if their IncS…
65381 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
65383 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
65385 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
65387 …size of the message associated with each child in number of 128b units for set 0(should be in acco…
65391 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
65393 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
65395 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
65397 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
65400 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
65402 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
65404 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
65406 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
65409 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
65411 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
65413 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
65415 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
65418 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
65420 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
65422 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
65424 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
65460 … 0x5c0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65461 … 0x5c0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65462 … 0x5c082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65463 … 0x5c0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65464 … 0x5c0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65465 … 0x5c0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65466 … 0x5c083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65467 … 0x5c0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65468 … 0x5c0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65469 … 0x5c0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65470 … 0x5c084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65471 … 0x5c0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65472 … 0x5c0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65473 … 0x5c0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65474 … 0x5c085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65475 … 0x5c0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65476 … 0x5c0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65477 … 0x5c0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65478 … 0x5c086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65479 … 0x5c0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65480 … 0x5c0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65481 … 0x5c0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65482 … 0x5c087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65483 … 0x5c0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65484 … 0x5c0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65485 … 0x5c0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65486 … 0x5c088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65487 … 0x5c0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65488 … 0x5c0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65489 … 0x5c0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65490 … 0x5c089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65491 … 0x5c08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65493 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
65495 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
65497 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
65499 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
65502 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
65504 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
65506 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
65508 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
65511 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
65513 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
65515 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
65517 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
65520 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
65522 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
65524 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
65526 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
65565 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
65567 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
65569 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
65571 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
65573 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65575 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65577 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65579 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65582 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0.
65584 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
65586 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 2.
65588 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
65591 … (0xf<<0) // the maximal number of children in a specific aggregation. for set 0.
65593 … (0xf<<4) // the maximal number of children in a specific aggregation. for set 1.
65595 … (0xf<<8) // the maximal number of children in a specific aggregation. for set 2.
65597 … (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
65600 …0xff<<0) // The value by which to increment the event-ID in case of successful aggregation. for se…
65602 …0xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for se…
65604 …xff<<16) // The value by which to increment the event-ID in case of successful aggregation. for se…
65606 …xff<<24) // The value by which to increment the event-ID in case of successful aggregation. for se…
65626 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
65644 … (0x1<<0) // This bit masks, when set, the Parity bit: WO…
65646 … (0x1<<1) // This bit masks, when set, the Parity bit: WO…
65648 … (0x1<<2) // This bit masks, when set, the Parity bit: WO…
65650 … (0x1<<3) // This bit masks, when set, the Parity bit: WO…
65652 … (0x1<<4) // This bit masks, when set, the Parity bit: WO…
65654 … (0x1<<5) // This bit masks, when set, the Parity bit: WO…
65656 … (0x1<<6) // This bit masks, when set, the Parity bit: WO…
65658 … (0x1<<7) // This bit masks, when set, the Parity bit: WO…
65660 … (0x1<<8) // This bit masks, when set, the Parity bit: WO…
65662 … (0x1<<9) // This bit masks, when set, the Parity bit: WO…
65664 … (0x1<<10) // This bit masks, when set, the Parity bit: WO…
65666 … (0x1<<11) // This bit masks, when set, the Parity bit: WO…
65668 … (0x1<<12) // This bit masks, when set, the Parity bit: WO…
65670 … (0x1<<13) // This bit masks, when set, the Parity bit: WO…
65672 … (0x1<<14) // This bit masks, when set, the Parity bit: WO…
65674 … (0x1<<15) // This bit masks, when set, the Parity bit: WO…
65676 … (0x1<<16) // This bit masks, when set, the Parity bit: WO…
65678 … (0x1<<17) // This bit masks, when set, the Parity bit: WO…
65680 … (0x1<<18) // This bit masks, when set, the Parity bit: WO…
65682 … (0x1<<19) // This bit masks, when set, the Parity bit: WO…
65684 … (0x1<<20) // This bit masks, when set, the Parity bit: WO…
65686 … (0x1<<21) // This bit masks, when set, the Parity bit: WO…
65688 … (0x1<<22) // This bit masks, when set, the Parity bit: WO…
65690 … (0x1<<23) // This bit masks, when set, the Parity bit: WO…
65693 …-port per-PF register. L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L…
65694 … 0x608004UL //Access:RW DataWidth:0x1 // Set this bit to enable …
65695 … 0x608080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
65697 …0x608100UL //Access:RW DataWidth:0x1 // This is a per-port register. When this bit is set A…
65698 … 0x608104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65699 … 0x608108UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65700 … 0x60810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65701 … 0x608110UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65702 … 0x608114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65703 … 0x608118UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65704 … 0x60811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65705 … 0x608120UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65706 … 0x608124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65707 … 0x608128UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65708 … 0x60812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65709 … 0x608130UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65710 … 0x608134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65711 … 0x608138UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65712 … 0x60813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65713 … 0x608140UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65714 …8144UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. When this bit is set…
65715 … 0x608148UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
65717 … 0x608150UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high …
65718 … 0x608160UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wa…
65720 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
65721 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
65722 … 0x608188UL //Access:R DataWidth:0xe // Wake packet length - the actual length of…
65723 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
65725 …election - acpi_default_pf_sel. 2: Select the first of each: 2 ports (quad_port_mode is 0) - use o…
65726 … This is a per-PF register. Set bit 0 to enable wake on IPv4 TCP SYN. Set bit 1 to enable wake on…
65727 … 0x60819cUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65728 … 0x6081a0UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65729 … 0x6081a4UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65730 … 0x6081a8UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65731 … 0x6081acUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65732 … 0x6081b0UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65743 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
65764 …erride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bi…
65765 …erride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bi…
65766 … 0x6101f8UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65821 … (0xff<<0) // Firmware must set this bit to 1 after…
65823 … (0x1<<8) // Firmware must set this bit to 1 after…
65865 …T_K2_E5 (0x1<<0) // When set to 1, represents FW…
65867 …_K2_E5 (0x1<<1) // When set to 0, HWInit contro…
65869 …K2_E5 (0x1<<2) // When set to 0, HWInit contro…
65886 …d on CMU0 in multiple CMU PHYs if there are any active lanes. Signal is over-riden by por_n_i so h…
65911 …- rxsig_det_mask_i 16 - rxeii_exit_type_i 15 - rxei_infer_i 14 - bslip_req_i 13 - data_width_i - 0…
65915 …pcs_sdet 0 - ln1_stat_o[2] (RX Locked indicator) 1 - ln1_astat_o[5] (Raw signal detext indicator)…
65923 …- not used 12 - ln1_ok_o 11 - ln1_runlen_err_o 10:4 - not used 3:2 - ln1_rx_locked_o - bit 3 =rxda…
65925 …(0x3f<<14) // 19 - Raw signal detect - Bit Slip Ack 18 - ln1_bitslip_ack_o - Bit Slip Ack 17 - not…
65945 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
65967 … 0x6a0250UL //Access:RW DataWidth:0x1 // Debug only: FW trigger is set.
65968 …-0x1ff. Reserved = 0x200-0x3ff. LANE1 registers = 0x400-0x5ff. Reserved = 0x600-0x7f…
65977 …to set0 1: Using registers belonging to set1 SETS_W-1: Using set of registers belonging to set SET…
65979 …corresponds to FLOW 1 Bit [1] : corresponds to FLOW 2 Any toggle from zero-to-one will generate an…
65982 …<0) // This signal is set when the voltage is stable at its target value, typically after a change…
65984 … (0x3<<1) // It replicates the mode-sel value when voltag…
65986 … (0x7<<3) // It replicates the set-sel value when volta…
65996 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
65998 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
66011 … (0x1<<0) // This bit masks, when set, the Parity bit: AV…
66013 … (0x1<<1) // This bit masks, when set, the Parity bit: AV…
66015 … (0x1<<2) // This bit masks, when set, the Parity bit: AV…
66027 … (0x1<<0) // If set overrides hardware …
66029 …<<4) // If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LE…
66031 … (0x1<<8) // If set along with the LED_…
66033 … (0x1<<12) // This bit is set to enable the use o…
66035 … (0x1<<13) // This bit is set to enable the alter…
66039 …-> MAC; 1-2 -> PHY1; 3 -> PHY3; 4 -> MAC2; 5-6 -> PHY4; 7 -> PHY6; 8 -> MAC3; …
66040 …08UL //Access:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66041 …0cUL //Access:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66042 …10UL //Access:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66043 …-> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G This register allows the MAC (Driver/FW) to set …
66045 … corresponding Physical function. 0 -> NW0 connects to PF0 1 -> NW0 connects to PF1 2 -> NW0 co…
66047 … corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connects to PF1 2 -> NW1 co…
66049 … corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1 2 -> NW2 co…
66051 … corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1 2 -> NW3 co…
66053 …1cUL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66054 …20UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66055 …24UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66056 …28UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66057 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
66062 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
66073 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66075 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66081 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66084 …<0) // 0x0 - Select reference clock from Bump 0x1 - Select inter-macro refrence clock from the lef…
66086 … (0x3<<2) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro ref…
66088 … (0x3<<4) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro re…
66090 …l is used for nws_nwm_sd_energy_detect. 0 - use ~lnX_stat_los_o 1 - use ~lnX_stat_los_deglitch_o (…
66108 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66110 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66112 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66114 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66116 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66118 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66121 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66128 … (0x1f<<0) // Sets phy_ctrl_refclk_i used for CMU0 0x09 - refclk is 257.8125Mhz
66130 … Sets phy_ctrl_rate1_i used for CMU0 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66132 … Sets phy_ctrl_rate1_i used for CMU1 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66148 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66150 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66152 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66154 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66157 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66164 … (0x1<<0) // 0x0 - No error 0x1 - Phy has inter…
66166 … (0x1<<1) // 0x1 - Indicates CMU0 PLL h…
66168 … (0x1<<2) // 0x1 - Indicates CMU1 PLL h…
66170 … (0x1<<3) // 0x0 - PHY is not ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. The signal…
66172 … (0x1<<4) // 0x0 - PHY is not ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. The signal…
66174 … (0x1<<5) // 0x0 - PHY is not ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. The signal…
66176 … (0x1<<6) // 0x0 - PHY is not ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. The signal…
66178 … (0x1<<7) // 0x0 - PHY is not ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. The signal…
66180 … (0x1<<8) // 0x0 - PHY is not ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. The signal…
66196 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66198 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66200 … LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instea…
66204 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66207 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66209 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66211 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66213 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66215 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66218 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66220 … (0x1<<1) // 0x0 - data on ln0_rxdata_o is invalid. 0x1 - d…
66222 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66224 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. …
66226 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. …
66231 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66233 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66239 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66242 …STATUS_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respect…
66244 …STATUS_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respect…
66246 …STATUS_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respect…
66248 …STATUS_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respect…
66250 …STATUS_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respect…
66252 …STATUS_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respect…
66254 …STATUS_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respect…
66256 …STATUS_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respect…
66258 …STATUS_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respect…
66261 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66268 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66270 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66272 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66274 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66276 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66278 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66280 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66282 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66284 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66288 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66294 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66296 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66314 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66316 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66318 … LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instea…
66322 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66325 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66332 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66334 … (0x1<<1) // 0x0 - data on ln1_rxdata_o is invalid. 0x1 - d…
66336 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66338 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. …
66340 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. …
66356 …STATUS_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respect…
66358 …STATUS_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respect…
66360 …STATUS_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respect…
66362 …STATUS_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respect…
66364 …STATUS_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respect…
66366 …STATUS_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respect…
66368 …STATUS_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respect…
66370 …STATUS_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respect…
66372 …STATUS_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respect…
66375 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66377 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66379 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66381 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66383 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66386 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66388 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66390 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66392 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66394 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66396 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66398 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66400 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66402 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66406 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66412 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66414 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66421 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66423 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66429 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66432 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66434 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66436 … LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instea…
66440 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66443 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66450 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66452 … (0x1<<1) // 0x0 - data on ln2_rxdata_o is invalid. 0x1 - d…
66454 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66456 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. …
66458 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. …
66474 …STATUS_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respect…
66476 …STATUS_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respect…
66478 …STATUS_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respect…
66480 …STATUS_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respect…
66482 …STATUS_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respect…
66484 …STATUS_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respect…
66486 …STATUS_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respect…
66488 …STATUS_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respect…
66490 …STATUS_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respect…
66493 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66500 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66502 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66504 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66506 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66508 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66510 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66512 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66514 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66516 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66520 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66526 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66528 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66546 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66548 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66550 … LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instea…
66554 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66557 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66559 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66561 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66563 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66565 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66568 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66570 … (0x1<<1) // 0x0 - data on ln3_rxdata_o is invalid. 0x1 - d…
66572 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66574 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. …
66576 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. …
66581 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66583 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66589 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66592 …STATUS_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respect…
66594 …STATUS_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respect…
66596 …STATUS_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respect…
66598 …STATUS_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respect…
66600 …STATUS_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respect…
66602 …STATUS_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respect…
66604 …STATUS_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respect…
66606 …STATUS_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respect…
66608 …STATUS_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respect…
66611 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66618 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66620 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66622 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66624 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66626 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66628 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66630 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66632 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66634 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66638 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66644 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66646 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66664 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66684 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66686 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66688 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66690 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66692 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66695 …ver preconfigurations if bit 10 of Receiver Configuration Mode Register is set to �1�. Otherwise, …
66697 …one bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustm…
66707 …l operation). 1 Enabled (external control of phase rotators). Note: Do not set this bit to �1� unt…
66710 …ver preconfigurations if bit 10 of Receiver Configuration Mode Register is set to �1�. Otherwise, …
66712 …one bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustm…
66722 …l operation). 1 Enabled (external control of phase rotators). Note: Do not set this bit to �1� unt…
66725 …ver preconfigurations if bit 10 of Receiver Configuration Mode Register is set to �1�. Otherwise, …
66727 …one bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustm…
66737 …l operation). 1 Enabled (external control of phase rotators). Note: Do not set this bit to �1� unt…
66740 …ver preconfigurations if bit 10 of Receiver Configuration Mode Register is set to �1�. Otherwise, …
66742 …one bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustm…
66752 …l operation). 1 Enabled (external control of phase rotators). Note: Do not set this bit to �1� unt…
66755 …configurations if bit 10 of the Transmitter Configuration Mode Register is set to �1�. Otherwise, …
66757 …. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient up…
66771 …the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 N…
66777 … follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Re…
66779 …configurations if bit 10 of the Transmitter Configuration Mode Register is set to �1�. Otherwise, …
66781 …. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient up…
66795 …the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 N…
66801 … follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Re…
66803 …configurations if bit 10 of the Transmitter Configuration Mode Register is set to �1�. Otherwise, …
66805 …. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient up…
66819 …the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 N…
66825 … follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Re…
66827 …configurations if bit 10 of the Transmitter Configuration Mode Register is set to �1�. Otherwise, …
66829 …. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient up…
66843 …the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 N…
66849 … follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Re…
66886 … 0x700150UL //Access:RW DataWidth:0x1 // Debug only: FW trigger is set.
66909 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
66911 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
66913 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
66915 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
66917 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
66919 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
66921 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
66923 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
66925 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
66927 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
66991 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
66993 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
66995 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
66997 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
66999 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
67001 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
67003 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
67005 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
67007 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
67067 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
67069 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
67071 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
67073 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
67075 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
67077 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
67079 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
67081 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
67083 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
67143 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
67145 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
67147 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
67149 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
67151 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
67153 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
67155 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
67157 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
67159 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
67200 … (0x1<<1) // This bit masks, when set, the Parity bit: NW…
67202 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67204 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67206 … (0x1<<2) // This bit masks, when set, the Parity bit: NW…
67208 … (0x1<<3) // This bit masks, when set, the Parity bit: NW…
67211 …10 // PHY instance0 = 0x000-0x1fff. PHY instance1 = 0x2000-0x3fff. PHY instance2 = 0x4000-0x5fff…
67213 …-0x7ff. CMU0 registers = 0x0800-0x0bff. CMU1 registers = 0x0c00-0x0fff. Reserved = …
67255 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
67257 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
67259 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
67261 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
67263 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
67265 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
67267 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
67269 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
67271 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
67273 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
67275 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
67277 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
67279 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
67281 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
67283 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
67285 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
67287 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
67359 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67360 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67361 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67362 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67364 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67380 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67396 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67412 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67429 … (0x1<<0) // SGMII PCS Enable. When set to 1, the SGMII PCS is enabled. When se…
67431 … (0x1<<1) // SGMII PCS Enable. When set to 1, the SGMII PCS is enabled. When se…
67433 … (0x1<<2) // SGMII PCS Enable. When set to 1, the SGMII PCS is enabled. When se…
67435 … (0x1<<3) // SGMII PCS Enable. When set to 1, the SGMII PCS is enabled. When se…
67438 …_K2_E5 (0x1<<0) // Set to '1' to indicate …
67440 … (0x1<<1) // Auto-Negotiation status. Set to '1' when the Auto…
67442 …_K2_E5 (0x1<<2) // Set to '1' to indicate …
67444 … (0x1<<3) // Auto-Negotiation status. Set to '1' when the Auto…
67446 …_K2_E5 (0x1<<4) // Set to '1' to indicate …
67448 … (0x1<<5) // Auto-Negotiation status. Set to '1' when the Auto…
67450 …_K2_E5 (0x1<<6) // Set to '1' to indicate …
67452 … (0x1<<7) // Auto-Negotiation status. Set to '1' when the Auto…
67455 …NA_TX_K2_E5 (0xf<<0) // Set to '1' for a given …
67457 …NA_RX_K2_E5 (0xf<<4) // Set to '1' for a given …
67459 …RR_ENA_K2_E5 (0xf<<8) // Set to '1' for a given …
67470 …Controls the fast-wake mode for the LPI transmit and receive functions. When set to 1, the link is…
67480 … (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power stat…
67491 … (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power stat…
67502 … (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power stat…
67513 … (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power stat…
67522 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67531 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67540 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67549 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67554 …(1) the block synchronization state machines could successfully lock onto 66-bit block boundaries …
67558 …-lock or align-done status, depending on current mode, and a cleared hi-ber status. The signal sta…
67568 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67570 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67572 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67574 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67576 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67578 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67580 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67582 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67584 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67586 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67588 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67590 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67627 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67629 … (0x1<<1) // This bit masks, when set, the Parity bit: NW…
67631 … (0x1<<2) // This bit masks, when set, the Parity bit: NW…
67633 … (0x1<<3) // This bit masks, when set, the Parity bit: NW…
67635 … (0x1<<4) // This bit masks, when set, the Parity bit: NW…
67637 … (0x1<<5) // This bit masks, when set, the Parity bit: NW…
67639 … (0x1<<6) // This bit masks, when set, the Parity bit: NW…
67641 … (0x1<<7) // This bit masks, when set, the Parity bit: NW…
67643 … (0x1<<8) // This bit masks, when set, the Parity bit: NW…
67645 … (0x1<<9) // This bit masks, when set, the Parity bit: NW…
67647 … (0x1<<10) // This bit masks, when set, the Parity bit: NW…
67649 … (0x1<<11) // This bit masks, when set, the Parity bit: NW…
67651 … (0x1<<12) // This bit masks, when set, the Parity bit: NW…
67653 … (0x1<<13) // This bit masks, when set, the Parity bit: NW…
67655 … (0x1<<14) // This bit masks, when set, the Parity bit: NW…
67657 … (0x1<<15) // This bit masks, when set, the Parity bit: NW…
67659 … (0x1<<16) // This bit masks, when set, the Parity bit: NW…
67661 … (0x1<<17) // This bit masks, when set, the Parity bit: NW…
67663 … (0x1<<18) // This bit masks, when set, the Parity bit: NW…
67665 … (0x1<<19) // This bit masks, when set, the Parity bit: NW…
67667 … (0x1<<20) // This bit masks, when set, the Parity bit: NW…
67669 … (0x1<<21) // This bit masks, when set, the Parity bit: NW…
67671 … (0x1<<22) // This bit masks, when set, the Parity bit: NW…
67673 … (0x1<<23) // This bit masks, when set, the Parity bit: NW…
67675 … (0x1<<24) // This bit masks, when set, the Parity bit: NW…
67677 … (0x1<<25) // This bit masks, when set, the Parity bit: NW…
67679 … (0x1<<26) // This bit masks, when set, the Parity bit: NW…
67681 … (0x1<<27) // This bit masks, when set, the Parity bit: NW…
67683 … (0x1<<28) // This bit masks, when set, the Parity bit: NW…
67685 … (0x1<<29) // This bit masks, when set, the Parity bit: NW…
67687 … (0x1<<30) // This bit masks, when set, the Parity bit: NW…
67690 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67692 … (0x1<<1) // This bit masks, when set, the Parity bit: NW…
67694 … (0x1<<2) // This bit masks, when set, the Parity bit: NW…
67696 … (0x1<<3) // This bit masks, when set, the Parity bit: NW…
67698 … (0x1<<4) // This bit masks, when set, the Parity bit: NW…
67700 … (0x1<<5) // This bit masks, when set, the Parity bit: NW…
67702 … (0x1<<6) // This bit masks, when set, the Parity bit: NW…
67704 … (0x1<<7) // This bit masks, when set, the Parity bit: NW…
67706 … (0x1<<8) // This bit masks, when set, the Parity bit: NW…
67708 … (0x1<<9) // This bit masks, when set, the Parity bit: NW…
67710 … (0x1<<10) // This bit masks, when set, the Parity bit: NW…
67712 … (0x1<<11) // This bit masks, when set, the Parity bit: NW…
67714 … (0x1<<12) // This bit masks, when set, the Parity bit: NW…
67716 … (0x1<<13) // This bit masks, when set, the Parity bit: NW…
67718 … (0x1<<14) // This bit masks, when set, the Parity bit: NW…
67720 … (0x1<<15) // This bit masks, when set, the Parity bit: NW…
67722 … (0x1<<16) // This bit masks, when set, the Parity bit: NW…
67724 … (0x1<<17) // This bit masks, when set, the Parity bit: NW…
67726 … (0x1<<18) // This bit masks, when set, the Parity bit: NW…
67728 … (0x1<<19) // This bit masks, when set, the Parity bit: NW…
67730 … (0x1<<20) // This bit masks, when set, the Parity bit: NW…
67732 … (0x1<<21) // This bit masks, when set, the Parity bit: NW…
67734 … (0x1<<22) // This bit masks, when set, the Parity bit: NW…
67736 … (0x1<<23) // This bit masks, when set, the Parity bit: NW…
67738 … (0x1<<24) // This bit masks, when set, the Parity bit: NW…
67740 … (0x1<<25) // This bit masks, when set, the Parity bit: NW…
67742 … (0x1<<26) // This bit masks, when set, the Parity bit: NW…
67744 … (0x1<<27) // This bit masks, when set, the Parity bit: NW…
67746 … (0x1<<28) // This bit masks, when set, the Parity bit: NW…
67748 … (0x1<<29) // This bit masks, when set, the Parity bit: NW…
67750 … (0x1<<30) // This bit masks, when set, the Parity bit: NW…
67753 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67755 … (0x1<<1) // This bit masks, when set, the Parity bit: NW…
67757 … (0x1<<2) // This bit masks, when set, the Parity bit: NW…
67759 … (0x1<<3) // This bit masks, when set, the Parity bit: NW…
67761 … (0x1<<4) // This bit masks, when set, the Parity bit: NW…
67763 … (0x1<<5) // This bit masks, when set, the Parity bit: NW…
67765 … (0x1<<6) // This bit masks, when set, the Parity bit: NW…
67767 … (0x1<<7) // This bit masks, when set, the Parity bit: NW…
67769 … (0x1<<8) // This bit masks, when set, the Parity bit: NW…
67771 … (0x1<<9) // This bit masks, when set, the Parity bit: NW…
67806 …h:0x1 // Init bit. When set the initial credits are copied to the credit registers (except the …
67808 … 0xd80008UL //Access:R DataWidth:0x1 // Set when the cache init…
67809 … 0xd8000cUL //Access:RW DataWidth:0x1 // When set to 1 the cam hit pa…
67810 … 0xd80010UL //Access:RW DataWidth:0x1 // When set to 1 the cam miss p…
67891 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
67900 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
67903 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
67905 … (0x1<<1) // This bit masks, when set, the Parity bit: PB…
67907 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
67909 … (0x1<<3) // This bit masks, when set, the Parity bit: PB…
67911 … (0x1<<3) // This bit masks, when set, the Parity bit: PB…
67913 … (0x1<<4) // This bit masks, when set, the Parity bit: PB…
67915 … (0x1<<5) // This bit masks, when set, the Parity bit: PB…
67917 … (0x1<<6) // This bit masks, when set, the Parity bit: PB…
67919 … (0x1<<7) // This bit masks, when set, the Parity bit: PB…
67921 … (0x1<<8) // This bit masks, when set, the Parity bit: PB…
67923 … (0x1<<9) // This bit masks, when set, the Parity bit: PB…
67925 … (0x1<<10) // This bit masks, when set, the Parity bit: PB…
67927 … (0x1<<11) // This bit masks, when set, the Parity bit: PB…
67929 … (0x1<<12) // This bit masks, when set, the Parity bit: PB…
67931 … (0x1<<13) // This bit masks, when set, the Parity bit: PB…
67933 … (0x1<<14) // This bit masks, when set, the Parity bit: PB…
67935 … (0x1<<15) // This bit masks, when set, the Parity bit: PB…
67937 … (0x1<<16) // This bit masks, when set, the Parity bit: PB…
67939 … (0x1<<17) // This bit masks, when set, the Parity bit: PB…
67941 … (0x1<<18) // This bit masks, when set, the Parity bit: PB…
67943 … (0x1<<19) // This bit masks, when set, the Parity bit: PB…
67945 … (0x1<<20) // This bit masks, when set, the Parity bit: PB…
67947 … (0x1<<21) // This bit masks, when set, the Parity bit: PB…
67949 … (0x1<<22) // This bit masks, when set, the Parity bit: PB…
67951 … (0x1<<23) // This bit masks, when set, the Parity bit: PB…
67953 … (0x1<<24) // This bit masks, when set, the Parity bit: PB…
67955 … (0x1<<25) // This bit masks, when set, the Parity bit: PB…
67957 … (0x1<<26) // This bit masks, when set, the Parity bit: PB…
67959 … (0x1<<27) // This bit masks, when set, the Parity bit: PB…
67961 … (0x1<<24) // This bit masks, when set, the Parity bit: PB…
67963 … (0x1<<28) // This bit masks, when set, the Parity bit: PB…
67965 … (0x1<<25) // This bit masks, when set, the Parity bit: PB…
67967 … (0x1<<29) // This bit masks, when set, the Parity bit: PB…
67969 … (0x1<<30) // This bit masks, when set, the Parity bit: PB…
67971 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
67973 … (0x1<<1) // This bit masks, when set, the Parity bit: PB…
67975 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
67977 … (0x1<<4) // This bit masks, when set, the Parity bit: PB…
67979 … (0x1<<5) // This bit masks, when set, the Parity bit: PB…
67981 … (0x1<<6) // This bit masks, when set, the Parity bit: PB…
67983 … (0x1<<7) // This bit masks, when set, the Parity bit: PB…
67985 … (0x1<<8) // This bit masks, when set, the Parity bit: PB…
67987 … (0x1<<9) // This bit masks, when set, the Parity bit: PB…
67989 … (0x1<<10) // This bit masks, when set, the Parity bit: PB…
67991 … (0x1<<11) // This bit masks, when set, the Parity bit: PB…
67993 … (0x1<<12) // This bit masks, when set, the Parity bit: PB…
67995 … (0x1<<13) // This bit masks, when set, the Parity bit: PB…
67997 … (0x1<<14) // This bit masks, when set, the Parity bit: PB…
67999 … (0x1<<15) // This bit masks, when set, the Parity bit: PB…
68001 … (0x1<<16) // This bit masks, when set, the Parity bit: PB…
68003 … (0x1<<17) // This bit masks, when set, the Parity bit: PB…
68005 … (0x1<<18) // This bit masks, when set, the Parity bit: PB…
68007 … (0x1<<19) // This bit masks, when set, the Parity bit: PB…
68009 … (0x1<<20) // This bit masks, when set, the Parity bit: PB…
68011 … (0x1<<21) // This bit masks, when set, the Parity bit: PB…
68013 … (0x1<<22) // This bit masks, when set, the Parity bit: PB…
68015 … (0x1<<23) // This bit masks, when set, the Parity bit: PB…
68017 … (0x1<<26) // This bit masks, when set, the Parity bit: PB…
68019 … (0x1<<27) // This bit masks, when set, the Parity bit: PB…
68021 … (0x1<<28) // This bit masks, when set, the Parity bit: PB…
68023 … (0x1<<29) // This bit masks, when set, the Parity bit: PB…
68025 … (0x1<<30) // This bit masks, when set, the Parity bit: PB…
68028 … (0x1<<21) // This bit masks, when set, the Parity bit: PB…
68030 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
68032 … (0x1<<23) // This bit masks, when set, the Parity bit: PB…
68034 … (0x1<<1) // This bit masks, when set, the Parity bit: PB…
68036 … (0x1<<10) // This bit masks, when set, the Parity bit: PB…
68038 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
68040 … (0x1<<3) // This bit masks, when set, the Parity bit: PB…
68042 … (0x1<<12) // This bit masks, when set, the Parity bit: PB…
68044 … (0x1<<4) // This bit masks, when set, the Parity bit: PB…
68046 … (0x1<<11) // This bit masks, when set, the Parity bit: PB…
68048 … (0x1<<5) // This bit masks, when set, the Parity bit: PB…
68050 … (0x1<<19) // This bit masks, when set, the Parity bit: PB…
68052 … (0x1<<6) // This bit masks, when set, the Parity bit: PB…
68054 … (0x1<<20) // This bit masks, when set, the Parity bit: PB…
68056 … (0x1<<7) // This bit masks, when set, the Parity bit: PB…
68058 … (0x1<<5) // This bit masks, when set, the Parity bit: PB…
68060 … (0x1<<8) // This bit masks, when set, the Parity bit: PB…
68062 … (0x1<<4) // This bit masks, when set, the Parity bit: PB…
68064 … (0x1<<9) // This bit masks, when set, the Parity bit: PB…
68066 … (0x1<<10) // This bit masks, when set, the Parity bit: PB…
68068 … (0x1<<16) // This bit masks, when set, the Parity bit: PB…
68070 … (0x1<<11) // This bit masks, when set, the Parity bit: PB…
68072 … (0x1<<9) // This bit masks, when set, the Parity bit: PB…
68074 … (0x1<<12) // This bit masks, when set, the Parity bit: PB…
68076 … (0x1<<8) // This bit masks, when set, the Parity bit: PB…
68078 … (0x1<<13) // This bit masks, when set, the Parity bit: PB…
68080 … (0x1<<6) // This bit masks, when set, the Parity bit: PB…
68082 … (0x1<<14) // This bit masks, when set, the Parity bit: PB…
68084 … (0x1<<7) // This bit masks, when set, the Parity bit: PB…
68086 … (0x1<<15) // This bit masks, when set, the Parity bit: PB…
68088 … (0x1<<16) // This bit masks, when set, the Parity bit: PB…
68090 … (0x1<<17) // This bit masks, when set, the Parity bit: PB…
68092 … (0x1<<18) // This bit masks, when set, the Parity bit: PB…
68094 … (0x1<<1) // This bit masks, when set, the Parity bit: PB…
68096 … (0x1<<19) // This bit masks, when set, the Parity bit: PB…
68098 … (0x1<<3) // This bit masks, when set, the Parity bit: PB…
68100 … (0x1<<20) // This bit masks, when set, the Parity bit: PB…
68102 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
68104 … (0x1<<21) // This bit masks, when set, the Parity bit: PB…
68106 … (0x1<<18) // This bit masks, when set, the Parity bit: PB…
68108 … (0x1<<22) // This bit masks, when set, the Parity bit: PB…
68110 … (0x1<<23) // This bit masks, when set, the Parity bit: PB…
68112 … (0x1<<26) // This bit masks, when set, the Parity bit: PB…
68114 … (0x1<<24) // This bit masks, when set, the Parity bit: PB…
68116 … (0x1<<24) // This bit masks, when set, the Parity bit: PB…
68118 … (0x1<<25) // This bit masks, when set, the Parity bit: PB…
68120 … (0x1<<25) // This bit masks, when set, the Parity bit: PB…
68122 … (0x1<<26) // This bit masks, when set, the Parity bit: PB…
68124 … (0x1<<27) // This bit masks, when set, the Parity bit: PB…
68126 … (0x1<<28) // This bit masks, when set, the Parity bit: PB…
68128 … (0x1<<29) // This bit masks, when set, the Parity bit: PB…
68130 … (0x1<<30) // This bit masks, when set, the Parity bit: PB…
68132 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
68134 … (0x1<<13) // This bit masks, when set, the Parity bit: PB…
68136 … (0x1<<14) // This bit masks, when set, the Parity bit: PB…
68138 … (0x1<<15) // This bit masks, when set, the Parity bit: PB…
68140 … (0x1<<17) // This bit masks, when set, the Parity bit: PB…
68142 … (0x1<<22) // This bit masks, when set, the Parity bit: PB…
68146 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
68148 … (0x1<<1) // This bit masks, when set, the Parity bit: PB…
68150 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
68152 … (0x1<<3) // This bit masks, when set, the Parity bit: PB…
68256 …_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
68258 …_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for mem…
68260 …_I_ECC_PRTY_E5 (0x1<<2) // Set parity only for mem…
68262 …_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for mem…
68264 …_I_ECC_PRTY_BB_K2 (0x1<<3) // Set parity only for mem…
68266 …_I_ECC_PRTY_E5 (0x1<<4) // Set parity only for mem…
68268 …_I_ECC_PRTY_E5 (0x1<<5) // Set parity only for mem…
68270 …_I_ECC_0_PRTY_E5 (0x1<<6) // Set parity only for mem…
68272 …_I_ECC_1_PRTY_E5 (0x1<<7) // Set parity only for mem…
68274 …_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only for mem…
68276 …_I_ECC_1_PRTY_E5 (0x1<<9) // Set parity only for mem…
68278 …I_ECC_2_PRTY_E5 (0x1<<10) // Set parity only for mem…
68280 …I_ECC_3_PRTY_E5 (0x1<<11) // Set parity only for mem…
68282 …I_ECC_4_PRTY_E5 (0x1<<12) // Set parity only for mem…
68284 …I_ECC_5_PRTY_E5 (0x1<<13) // Set parity only for mem…
68286 …I_ECC_6_PRTY_E5 (0x1<<14) // Set parity only for mem…
68288 …I_ECC_7_PRTY_E5 (0x1<<15) // Set parity only for mem…
68290 …I_ECC_8_PRTY_E5 (0x1<<16) // Set parity only for mem…
68292 …I_ECC_9_PRTY_E5 (0x1<<17) // Set parity only for mem…
68294 …I_ECC_10_PRTY_E5 (0x1<<18) // Set parity only for mem…
68296 …I_ECC_11_PRTY_E5 (0x1<<19) // Set parity only for mem…
68298 …I_ECC_12_PRTY_E5 (0x1<<20) // Set parity only for mem…
68300 …I_ECC_13_PRTY_E5 (0x1<<21) // Set parity only for mem…
68302 …I_ECC_14_PRTY_E5 (0x1<<22) // Set parity only for mem…
68304 …I_ECC_15_PRTY_E5 (0x1<<23) // Set parity only for mem…
68306 …_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
68308 …_I_ECC_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
68310 …_I_ECC_PRTY_BB_K2 (0x1<<2) // Set parity only for mem…
68312 …_I_ECC_PRTY_BB_K2 (0x1<<4) // Set parity only for mem…
68314 …_I_ECC_0_PRTY_BB_K2 (0x1<<5) // Set parity only for mem…
68316 …_I_ECC_1_PRTY_BB_K2 (0x1<<6) // Set parity only for mem…
68318 …_I_ECC_0_PRTY_BB_K2 (0x1<<7) // Set parity only for mem…
68320 …_I_ECC_1_PRTY_BB_K2 (0x1<<8) // Set parity only for mem…
68322 …_I_ECC_2_PRTY_BB_K2 (0x1<<9) // Set parity only for mem…
68324 …I_ECC_3_PRTY_BB_K2 (0x1<<10) // Set parity only for mem…
68326 …I_ECC_4_PRTY_BB_K2 (0x1<<11) // Set parity only for mem…
68328 …I_ECC_5_PRTY_BB_K2 (0x1<<12) // Set parity only for mem…
68330 …I_ECC_6_PRTY_BB_K2 (0x1<<13) // Set parity only for mem…
68332 …I_ECC_7_PRTY_BB_K2 (0x1<<14) // Set parity only for mem…
68334 …I_ECC_8_PRTY_BB_K2 (0x1<<15) // Set parity only for mem…
68336 …I_ECC_9_PRTY_BB_K2 (0x1<<16) // Set parity only for mem…
68338 …I_ECC_10_PRTY_BB_K2 (0x1<<17) // Set parity only for mem…
68340 …I_ECC_11_PRTY_BB_K2 (0x1<<18) // Set parity only for mem…
68342 …I_ECC_12_PRTY_BB_K2 (0x1<<19) // Set parity only for mem…
68344 …I_ECC_13_PRTY_BB_K2 (0x1<<20) // Set parity only for mem…
68346 …I_ECC_14_PRTY_BB_K2 (0x1<<21) // Set parity only for mem…
68348 …I_ECC_15_PRTY_BB_K2 (0x1<<22) // Set parity only for mem…
68448 …0400UL //Access:RW DataWidth:0x3 // PXP read request interface initial credit - transoriented.
68449 … 0xd80404UL //Access:RW DataWidth:0x6 // TDIF pass-through command inter…
68450 … 0xd80408UL //Access:RW DataWidth:0x6 // TDIF non_pass-through command inter…
68452 …10UL //Access:RW DataWidth:0x2 // PXP internal write interface initial credit - transoriented.
68453 … 0xd80414UL //Access:RW DataWidth:0x3 // TM interface initial credit - transoriented.
68482 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
68483 …-port: Bit-map indicating which L2 hdrs may appear after the LLC header on this port. This applie…
68484 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
68485 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
68486 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
68487 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
68488 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
68489 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
68490 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
68491 … 0xd804d4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68492 … 0xd804d8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68493 … 0xd804dcUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68494 … 0xd804e0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68495 … 0xd804e4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68496 … 0xd804e8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68497 … 0xd804ecUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68498 … 0xd804f0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68499 … 0xd804f4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68511 … 0xd80524UL //Access:RW DataWidth:0x1 // Per-port: Flag to compar…
68544 …used only if sal_flex_upper_bytes is not 0, and number of bytes selected = 8 - sal_flex_upper_bytes
68550 …/Access:RW DataWidth:0x20 // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in …
68551 …/Access:RW DataWidth:0x20 // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in …
68556 …s_ipv4_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
68557 …s_ipv6_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set.
68563 …ompared Vs the label field of the last mpls label if mpls_compare_label is set. This is enabled pe…
68608 …XT_UNIFORM_HDR_TYPE_0_VALID_E5 (0x1<<0) // If set, validates the corr…
68610 …XT_UNIFORM_HDR_TYPE_1_VALID_E5 (0x1<<1) // If set, validates the corr…
68612 …XT_UNIFORM_HDR_TYPE_2_VALID_E5 (0x1<<2) // If set, validates the corr…
68614 …XT_UNIFORM_HDR_TYPE_3_VALID_E5 (0x1<<3) // If set, validates the corr…
68616 …XT_UNIFORM_HDR_TYPE_4_VALID_E5 (0x1<<4) // If set, validates the corr…
68618 …XT_UNIFORM_HDR_TYPE_5_VALID_E5 (0x1<<5) // If set, validates the corr…
68620 …XT_UNIFORM_HDR_TYPE_6_VALID_E5 (0x1<<6) // If set, validates the corr…
68622 …XT_UNIFORM_HDR_TYPE_7_VALID_E5 (0x1<<7) // If set, validates the corr…
68624 …XT_UNIFORM_HDR_TYPE_8_VALID_E5 (0x1<<8) // If set, validates the corr…
68626 …XT_UNIFORM_HDR_TYPE_9_VALID_E5 (0x1<<9) // If set, validates the corr…
68628 …T_UNIFORM_HDR_TYPE_10_VALID_E5 (0x1<<10) // If set, validates the corr…
68630 …T_UNIFORM_HDR_TYPE_11_VALID_E5 (0x1<<11) // If set, validates the corr…
68632 …T_UNIFORM_HDR_TYPE_12_VALID_E5 (0x1<<12) // If set, validates the corr…
68634 …T_UNIFORM_HDR_TYPE_13_VALID_E5 (0x1<<13) // If set, validates the corr…
68636 …T_FRAGMENT_HDR_TYPE_VALID_E5 (0x1<<14) // If set, validates the corr…
68638 …T_AUTHENTICATION_HDR_TYPE_VALID_E5 (0x1<<15) // If set, validates the corr…
68641 …rder. Reset value is in the order from left to right: tag0; tag1; tag2; tag3; tag4; tag5; llc-snap.
68642 …//Access:RW DataWidth:0x4 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. T…
68662 … 0xd805b0UL //Access:RW DataWidth:0x1 // If set, enables inclusion …
68663 …DataWidth:0xb // Number of shared BTB 256 byte blocks which can be used by all TC-s in the port.
68667 …-priority w/ anti-starvation arbiter is a RR arbiter. A value of all ones means no RR slots; i.e. …
68668 …W DataWidth:0x8 // L2 EDPM threshold in 256 byte blocks. Only if all TC-s have allocated bloc…
68669 …e blocks. Only if all TC-s in port N have allocated blocks above this threshold, the corresponding…
68670 … DataWidth:0xb // RDMA EDPM threshold in 256 byte blocks. Only if all TC-s have allocated bloc…
68686 … 0xd80644UL //Access:RW DataWidth:0x1 // if set, packets with a PCI…
68695 … 0xd80678UL //Access:RW DataWidth:0x1 // If set, Ethernet over GRE …
68696 … 0xd8067cUL //Access:RW DataWidth:0x1 // If set, IP over GRE tunnel…
68697 … 0xd80680UL //Access:RW DataWidth:0x1 // If set, VXLAN tunneling is…
68698 … 0xd80684UL //Access:RW DataWidth:0x1 // If set, Ethernet over NGE …
68699 … 0xd80688UL //Access:RW DataWidth:0x1 // If set, IP over NGE tunnel…
68700 … 0xd8068cUL //Access:RW DataWidth:0x1 // If set, Ethernet over MPLS…
68701 … 0xd80690UL //Access:RW DataWidth:0x1 // If set, IP over MPLS over …
68702 … 0xd80694UL //Access:RW DataWidth:0x1 // If set, Ethernet over MPLS…
68703 … 0xd80698UL //Access:RW DataWidth:0x1 // If set, IP over MPLS over …
68704 … 0xd8069cUL //Access:RW DataWidth:0x1 // If set, Ethernet over MPLS…
68716 …AN_USE_SHARED_VOQ0 (0x1<<16) // if set, enables using the …
68718 …AN_USE_SHARED_FOR_JUMBO_VOQ0 (0x1<<17) // if set, enables using the …
68734 …AN_USE_SHARED_VOQ1 (0x1<<16) // if set, enables using the …
68736 …AN_USE_SHARED_FOR_JUMBO_VOQ1 (0x1<<17) // if set, enables using the …
68752 …AN_USE_SHARED_VOQ2 (0x1<<16) // if set, enables using the …
68754 …AN_USE_SHARED_FOR_JUMBO_VOQ2 (0x1<<17) // if set, enables using the …
68770 …AN_USE_SHARED_VOQ3 (0x1<<16) // if set, enables using the …
68772 …AN_USE_SHARED_FOR_JUMBO_VOQ3 (0x1<<17) // if set, enables using the …
68788 …AN_USE_SHARED_VOQ4 (0x1<<16) // if set, enables using the …
68790 …AN_USE_SHARED_FOR_JUMBO_VOQ4 (0x1<<17) // if set, enables using the …
68806 …AN_USE_SHARED_VOQ5 (0x1<<16) // if set, enables using the …
68808 …AN_USE_SHARED_FOR_JUMBO_VOQ5 (0x1<<17) // if set, enables using the …
68824 …AN_USE_SHARED_VOQ6 (0x1<<16) // if set, enables using the …
68826 …AN_USE_SHARED_FOR_JUMBO_VOQ6 (0x1<<17) // if set, enables using the …
68842 …AN_USE_SHARED_VOQ7 (0x1<<16) // if set, enables using the …
68844 …AN_USE_SHARED_FOR_JUMBO_VOQ7 (0x1<<17) // if set, enables using the …
68860 …AN_USE_SHARED_VOQ8 (0x1<<16) // if set, enables using the …
68862 …AN_USE_SHARED_FOR_JUMBO_VOQ8 (0x1<<17) // if set, enables using the …
68878 …AN_USE_SHARED_VOQ9 (0x1<<16) // if set, enables using the …
68880 …AN_USE_SHARED_FOR_JUMBO_VOQ9 (0x1<<17) // if set, enables using the …
68896 …CAN_USE_SHARED_VOQ10 (0x1<<16) // if set, enables using the …
68898 …CAN_USE_SHARED_FOR_JUMBO_VOQ10 (0x1<<17) // if set, enables using the …
68914 …CAN_USE_SHARED_VOQ11 (0x1<<16) // if set, enables using the …
68916 …CAN_USE_SHARED_FOR_JUMBO_VOQ11 (0x1<<17) // if set, enables using the …
68932 …CAN_USE_SHARED_VOQ12 (0x1<<16) // if set, enables using the …
68934 …CAN_USE_SHARED_FOR_JUMBO_VOQ12 (0x1<<17) // if set, enables using the …
68950 …CAN_USE_SHARED_VOQ13 (0x1<<16) // if set, enables using the …
68952 …CAN_USE_SHARED_FOR_JUMBO_VOQ13 (0x1<<17) // if set, enables using the …
68968 …CAN_USE_SHARED_VOQ14 (0x1<<16) // if set, enables using the …
68970 …CAN_USE_SHARED_FOR_JUMBO_VOQ14 (0x1<<17) // if set, enables using the …
68986 …CAN_USE_SHARED_VOQ15 (0x1<<16) // if set, enables using the …
68988 …CAN_USE_SHARED_FOR_JUMBO_VOQ15 (0x1<<17) // if set, enables using the …
69004 …CAN_USE_SHARED_VOQ16 (0x1<<16) // if set, enables using the …
69006 …CAN_USE_SHARED_FOR_JUMBO_VOQ16 (0x1<<17) // if set, enables using the …
69022 …CAN_USE_SHARED_VOQ17 (0x1<<16) // if set, enables using the …
69024 …CAN_USE_SHARED_FOR_JUMBO_VOQ17 (0x1<<17) // if set, enables using the …
69040 …CAN_USE_SHARED_VOQ18 (0x1<<16) // if set, enables using the …
69042 …CAN_USE_SHARED_FOR_JUMBO_VOQ18 (0x1<<17) // if set, enables using the …
69058 …CAN_USE_SHARED_VOQ19 (0x1<<16) // if set, enables using the …
69060 …CAN_USE_SHARED_FOR_JUMBO_VOQ19 (0x1<<17) // if set, enables using the …
69076 …CAN_USE_SHARED_VOQ20_E5 (0x1<<16) // if set, enables using the …
69078 …CAN_USE_SHARED_FOR_JUMBO_VOQ20_E5 (0x1<<17) // if set, enables using the …
69094 …CAN_USE_SHARED_VOQ21_E5 (0x1<<16) // if set, enables using the …
69096 …CAN_USE_SHARED_FOR_JUMBO_VOQ21_E5 (0x1<<17) // if set, enables using the …
69112 …CAN_USE_SHARED_VOQ22_E5 (0x1<<16) // if set, enables using the …
69114 …CAN_USE_SHARED_FOR_JUMBO_VOQ22_E5 (0x1<<17) // if set, enables using the …
69130 …CAN_USE_SHARED_VOQ23_E5 (0x1<<16) // if set, enables using the …
69132 …CAN_USE_SHARED_FOR_JUMBO_VOQ23_E5 (0x1<<17) // if set, enables using the …
69148 …CAN_USE_SHARED_VOQ24_E5 (0x1<<16) // if set, enables using the …
69150 …CAN_USE_SHARED_FOR_JUMBO_VOQ24_E5 (0x1<<17) // if set, enables using the …
69166 …CAN_USE_SHARED_VOQ25_E5 (0x1<<16) // if set, enables using the …
69168 …CAN_USE_SHARED_FOR_JUMBO_VOQ25_E5 (0x1<<17) // if set, enables using the …
69184 …CAN_USE_SHARED_VOQ26_E5 (0x1<<16) // if set, enables using the …
69186 …CAN_USE_SHARED_FOR_JUMBO_VOQ26_E5 (0x1<<17) // if set, enables using the …
69202 …CAN_USE_SHARED_VOQ27_E5 (0x1<<16) // if set, enables using the …
69204 …CAN_USE_SHARED_FOR_JUMBO_VOQ27_E5 (0x1<<17) // if set, enables using the …
69220 …CAN_USE_SHARED_VOQ28_E5 (0x1<<16) // if set, enables using the …
69222 …CAN_USE_SHARED_FOR_JUMBO_VOQ28_E5 (0x1<<17) // if set, enables using the …
69238 …CAN_USE_SHARED_VOQ29_E5 (0x1<<16) // if set, enables using the …
69240 …CAN_USE_SHARED_FOR_JUMBO_VOQ29_E5 (0x1<<17) // if set, enables using the …
69256 …CAN_USE_SHARED_VOQ30_E5 (0x1<<16) // if set, enables using the …
69258 …CAN_USE_SHARED_FOR_JUMBO_VOQ30_E5 (0x1<<17) // if set, enables using the …
69274 …CAN_USE_SHARED_VOQ31_E5 (0x1<<16) // if set, enables using the …
69276 …CAN_USE_SHARED_FOR_JUMBO_VOQ31_E5 (0x1<<17) // if set, enables using the …
69292 …CAN_USE_SHARED_VOQ32_E5 (0x1<<16) // if set, enables using the …
69294 …CAN_USE_SHARED_FOR_JUMBO_VOQ32_E5 (0x1<<17) // if set, enables using the …
69310 …CAN_USE_SHARED_VOQ33_E5 (0x1<<16) // if set, enables using the …
69312 …CAN_USE_SHARED_FOR_JUMBO_VOQ33_E5 (0x1<<17) // if set, enables using the …
69328 …CAN_USE_SHARED_VOQ34_E5 (0x1<<16) // if set, enables using the …
69330 …CAN_USE_SHARED_FOR_JUMBO_VOQ34_E5 (0x1<<17) // if set, enables using the …
69346 …CAN_USE_SHARED_VOQ35_E5 (0x1<<16) // if set, enables using the …
69348 …CAN_USE_SHARED_FOR_JUMBO_VOQ35_E5 (0x1<<17) // if set, enables using the …
69375 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
69377 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
69379 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
69381 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
69383 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
69385 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
69387 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
69389 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
69391 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
69432 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
69453 …ived on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
69491 … 0xda2000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
69515 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
69517 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
69519 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
69521 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
69523 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
69525 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
69527 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
69529 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
69531 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
69572 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
69593 …ived on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
69631 … 0xda6000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
69635 …Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers…
69636 …Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers…
69637 …set when initialization of all BRTB registers and memories is finished. BRTB will fill all prefetc…
69672 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
69674 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
69676 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
69678 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
69680 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
69682 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
69684 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
69686 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
69688 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
69690 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
69692 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
69694 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
69696 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
69698 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
69700 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
69702 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
69804 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
69806 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
69808 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
69810 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
69812 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
69814 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
69816 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
69818 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
69820 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
69822 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
69824 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
69826 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
69828 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
69830 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
69832 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
69834 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
69912 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
69914 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
69916 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
69918 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
70004 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
70006 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
70008 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
70010 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
70012 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
70014 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
70016 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
70018 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
70020 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
70022 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
70024 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
70026 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
70028 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
70030 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
70032 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
70034 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
70036 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
70038 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
70040 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
70042 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
70044 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
70046 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
70048 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
70050 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
70052 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
70054 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
70056 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
70058 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
70060 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
70062 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
70064 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
70066 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
70246 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
70248 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
70250 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
70252 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
70254 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
70256 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
70258 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
70260 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
70262 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
70264 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
70266 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
70268 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
70270 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
70272 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
70274 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
70276 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
70278 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
70280 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
70282 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
70284 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
70286 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
70288 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
70290 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
70452 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
70454 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
70456 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
70458 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
70460 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
70462 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
70464 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
70466 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
70468 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
70470 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
70472 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
70474 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
70476 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
70478 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
70480 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
70482 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
70484 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
70486 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
70488 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
70490 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
70492 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
70494 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
70496 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
70498 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
70500 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
70502 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
70504 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
70506 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
70508 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
70510 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
70512 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
70514 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
70650 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
70662 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
70674 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
70686 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
70700 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
70702 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
70715 … (0x1<<0) // This bit masks, when set, the Parity bit: BT…
70717 … (0x1<<1) // This bit masks, when set, the Parity bit: BT…
70719 … (0x1<<2) // This bit masks, when set, the Parity bit: BT…
70721 … (0x1<<3) // This bit masks, when set, the Parity bit: BT…
70723 … (0x1<<4) // This bit masks, when set, the Parity bit: BT…
70726 … (0x1<<0) // This bit masks, when set, the Parity bit: BT…
70728 … (0x1<<1) // This bit masks, when set, the Parity bit: BT…
70730 … (0x1<<2) // This bit masks, when set, the Parity bit: BT…
70732 … (0x1<<3) // This bit masks, when set, the Parity bit: BT…
70734 … (0x1<<4) // This bit masks, when set, the Parity bit: BT…
70736 … (0x1<<5) // This bit masks, when set, the Parity bit: BT…
70738 … (0x1<<6) // This bit masks, when set, the Parity bit: BT…
70740 … (0x1<<7) // This bit masks, when set, the Parity bit: BT…
70742 … (0x1<<8) // This bit masks, when set, the Parity bit: BT…
70744 … (0x1<<9) // This bit masks, when set, the Parity bit: BT…
70746 … (0x1<<10) // This bit masks, when set, the Parity bit: BT…
70748 … (0x1<<11) // This bit masks, when set, the Parity bit: BT…
70750 … (0x1<<12) // This bit masks, when set, the Parity bit: BT…
70752 … (0x1<<13) // This bit masks, when set, the Parity bit: BT…
70754 … (0x1<<14) // This bit masks, when set, the Parity bit: BT…
70756 … (0x1<<15) // This bit masks, when set, the Parity bit: BT…
70758 … (0x1<<16) // This bit masks, when set, the Parity bit: BT…
70760 … (0x1<<17) // This bit masks, when set, the Parity bit: BT…
70762 … (0x1<<18) // This bit masks, when set, the Parity bit: BT…
70764 … (0x1<<19) // This bit masks, when set, the Parity bit: BT…
70766 … (0x1<<20) // This bit masks, when set, the Parity bit: BT…
70768 … (0x1<<21) // This bit masks, when set, the Parity bit: BT…
70770 … (0x1<<22) // This bit masks, when set, the Parity bit: BT…
70772 … (0x1<<23) // This bit masks, when set, the Parity bit: BT…
70774 … (0x1<<16) // This bit masks, when set, the Parity bit: BT…
70776 … (0x1<<24) // This bit masks, when set, the Parity bit: BT…
70778 … (0x1<<17) // This bit masks, when set, the Parity bit: BT…
70780 … (0x1<<25) // This bit masks, when set, the Parity bit: BT…
70782 … (0x1<<18) // This bit masks, when set, the Parity bit: BT…
70784 … (0x1<<26) // This bit masks, when set, the Parity bit: BT…
70786 … (0x1<<19) // This bit masks, when set, the Parity bit: BT…
70788 … (0x1<<27) // This bit masks, when set, the Parity bit: BT…
70790 … (0x1<<17) // This bit masks, when set, the Parity bit: BT…
70792 … (0x1<<20) // This bit masks, when set, the Parity bit: BT…
70794 … (0x1<<28) // This bit masks, when set, the Parity bit: BT…
70796 … (0x1<<21) // This bit masks, when set, the Parity bit: BT…
70798 … (0x1<<29) // This bit masks, when set, the Parity bit: BT…
70800 … (0x1<<22) // This bit masks, when set, the Parity bit: BT…
70802 … (0x1<<30) // This bit masks, when set, the Parity bit: BT…
70804 … (0x1<<23) // This bit masks, when set, the Parity bit: BT…
70806 … (0x1<<24) // This bit masks, when set, the Parity bit: BT…
70808 … (0x1<<22) // This bit masks, when set, the Parity bit: BT…
70810 … (0x1<<25) // This bit masks, when set, the Parity bit: BT…
70812 … (0x1<<21) // This bit masks, when set, the Parity bit: BT…
70814 … (0x1<<26) // This bit masks, when set, the Parity bit: BT…
70816 … (0x1<<20) // This bit masks, when set, the Parity bit: BT…
70818 … (0x1<<27) // This bit masks, when set, the Parity bit: BT…
70820 … (0x1<<19) // This bit masks, when set, the Parity bit: BT…
70822 … (0x1<<28) // This bit masks, when set, the Parity bit: BT…
70824 … (0x1<<18) // This bit masks, when set, the Parity bit: BT…
70826 … (0x1<<29) // This bit masks, when set, the Parity bit: BT…
70828 … (0x1<<16) // This bit masks, when set, the Parity bit: BT…
70830 … (0x1<<30) // This bit masks, when set, the Parity bit: BT…
70834 … (0x1<<0) // This bit masks, when set, the Parity bit: BT…
70836 … (0x1<<1) // This bit masks, when set, the Parity bit: BT…
70838 … (0x1<<2) // This bit masks, when set, the Parity bit: BT…
70840 … (0x1<<3) // This bit masks, when set, the Parity bit: BT…
70842 … (0x1<<4) // This bit masks, when set, the Parity bit: BT…
70844 … (0x1<<5) // This bit masks, when set, the Parity bit: BT…
70846 … (0x1<<6) // This bit masks, when set, the Parity bit: BT…
70848 … (0x1<<7) // This bit masks, when set, the Parity bit: BT…
70908 …_I_ECC_PRTY (0x1<<0) // Set parity only for mem…
70910 …_I_ECC_PRTY (0x1<<1) // Set parity only for mem…
70912 …_I_ECC_PRTY (0x1<<2) // Set parity only for mem…
70914 …_I_ECC_PRTY (0x1<<3) // Set parity only for mem…
70916 …_I_ECC_PRTY (0x1<<4) // Set parity only for mem…
70918 …_I_ECC_PRTY (0x1<<5) // Set parity only for mem…
70920 …_I_ECC_PRTY (0x1<<6) // Set parity only for mem…
70922 …_I_ECC_PRTY (0x1<<7) // Set parity only for mem…
70924 …_I_ECC_PRTY (0x1<<8) // Set parity only for mem…
70926 …_I_ECC_PRTY (0x1<<9) // Set parity only for mem…
70928 …I_ECC_PRTY (0x1<<10) // Set parity only for mem…
70930 …I_ECC_PRTY (0x1<<11) // Set parity only for mem…
70932 …I_ECC_PRTY (0x1<<12) // Set parity only for mem…
70934 …I_ECC_PRTY (0x1<<13) // Set parity only for mem…
70936 …I_ECC_PRTY (0x1<<14) // Set parity only for mem…
70938 …I_ECC_PRTY (0x1<<15) // Set parity only for mem…
70940 …I_ECC1_PRTY_E5 (0x1<<16) // Set parity only for mem…
70942 …I_ECC2_PRTY_E5 (0x1<<17) // Set parity only for mem…
70944 …I_ECC1_PRTY_E5 (0x1<<18) // Set parity only for mem…
70946 …I_ECC2_PRTY_E5 (0x1<<19) // Set parity only for mem…
70948 …I_ECC1_PRTY_E5 (0x1<<20) // Set parity only for mem…
70950 …I_ECC2_PRTY_E5 (0x1<<21) // Set parity only for mem…
70952 …I_ECC1_PRTY_E5 (0x1<<22) // Set parity only for mem…
70954 …I_ECC2_PRTY_E5 (0x1<<23) // Set parity only for mem…
71021 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
71022 …04UL //Access:RW DataWidth:0xa // Number of valid bytes in header in 16-bytes resolution. Aft…
71030 … DataWidth:0x8 // There is bit for each PACKET read client. When bit is set then read client wi…
71031 …L_EN/d in Existance. Value for 40G mode (reset value, both BB and K2): 2880 - (34 + 2 + (9600+32)/…
71032 …set then packet will be read without dead cycles.B0-NIG main port0; B1-NIG LB port0; B2-NIG main p…
71034 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71036 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71038 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71040 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71042 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71044 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71046 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71048 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71050 …on. If bit is set then packet will be written without intra packet dead cycles .B0-NIG main port0;…
71051 …f bit is set then highest priority mechanism is enabled for the corresponding client. B0-NIG main …
71052 …is is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
71053 …cket request of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
71054 …h multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is high…
71077 …-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropr…
71079 …set then appropriate interface is enabled. When bit is reset then request from that interface will…
71081 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
71084 …-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropr…
71086 …set then appropriate interface is enabled. When bit is reset then valid to that interface will nev…
71088 … bit is set then almost full interface is enabled. When bit is reset then almost full will never b…
71090 …bit is set then packet avalable interface is enabled. When bit is reset then packet avalable inter…
71092 …s. When bit is set then release interface is enabled. When bit is reset then release interface wil…
71097 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
71101 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71102 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71103 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71104 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71105 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71106 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71107 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71108 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71109 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71110 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71111 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71112 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71113 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71114 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71115 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71116 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71117 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71118 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71119 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71120 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71121 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71122 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71123 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71124 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71125 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71126 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71127 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
71136 …f the packet arrived it can be sent to the read client. This is because (375-425)/425 is less then…
71141 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
71144 … erad packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1.…
71148 … read packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1.…
71155 …Access:RW DataWidth:0xc // Link list dual port memory that contains per-block descriptor::s/B…
71156 …Access:RW DataWidth:0xd // Link list dual port memory that contains per-block descriptor::s/B…
71163 … (0x1<<31) // This bit is set by the driver before it sets the MCP_RESET bit. …
71176 … (0x1<<30) // This bit is set when the watchdog t…
71178 … (0x1<<31) // This bit is set any time an interna…
71183 … (0x1<<31) // When this bit is set by the driver it in…
71190 … (0x1<<31) // When set this bit validates bits 10-0 of t…
71195 … (0x1<<30) // When set this bit causes MCP…
71197 … (0x1<<31) // When set this bit resets the…
71202 … (0x1<<30) // When set this bit resets the…
71204 … (0x1<<31) // When set this bit resets the…
71209 … (0x1<<27) // When set this bit enables wa…
71211 …NABLE (0x1<<28) // When this bit is set, expiration of watc…
71213 … (0x1<<29) // When set indicates that watc…
71215 … (0x1<<30) // When set this bit enables the watchdog timer to reset the MCP instead of halting i…
71217 … (0x1<<31) // When set this bit enables wa…
71232 … (0x3fff<<0) // Offset (in 32-bit words) of the mai…
71236 … (0xfff<<20) // Mailbox size in 32-bit words. Default ma…
71239 … (0x3fff<<0) // Offset (in 32-bit words) of the mai…
71243 … (0xfff<<20) // Mailbox size in 32-bit words. Default ma…
71248 … (0x1<<31) // Set by the driver to alert the MCP. Changing this register updates…
71266 …taWidth:0x20 // Port mode for GRC Master transactions 0: 1-port mode, 1: 2-port mode, 2: 4-port …
71268 …W DataWidth:0x20 // EPIO mask for signal transitioning from high to low. 1 -> MASK the event
71269 …W DataWidth:0x20 // EPIO mask for signal transitioning from low to high. 1 -> MASK the event
71274 …/ When this bit is written to a 1, the processor will reset as if from power-up state. All "Reset"…
71276 … (0x1<<1) // When this bit is set, the processor is a…
71286 …/ When this bit is set to 1, the interrupt is enabled. When this bit is zero, any interrupt will b…
71290 …bit is set, the CPU will halt. This bit is cleared by an exception or reset. If the processor does…
71292 …0x1<<11) // When this bit is set, the CPU will halt when any condition that causes bit 5 in the CP…
71294 …0x1<<12) // When this bit is set, the CPU will halt when any condition that causes bit 6 in the CP…
71296 … (0x1<<13) // When this bit is set, the CPU will halt when a abort is indicated from a…
71300 … (0x1<<15) // When this bit is set, the CPU will halt when state bit 11 is s…
71303 … (0x1<<0) // This bit is set while the processor…
71307 … (0x1<<2) // This bit is set while the processor…
71309 … (0x1<<3) // This bit is set while the processor…
71311 … (0x1<<4) // This bit is set while the processor…
71313 … (0x1<<5) // This bit is set while the processor…
71315 … (0x1<<6) // This bit is set while the processor…
71317 … (0x1<<7) // This bit is set while the processor…
71319 … (0x1<<8) // This bit is set while the processor is halted due to the generation of a abort condit…
71323 … (0x1<<10) // This bit is set while the processor…
71331 … (0x1<<14) // This bit is set while the processor…
71333 … (0x1<<15) // This bit is set while the processor…
71356 … (0x1<<8) // This bit enables the attention output when bit 8 of the state register is set.
71362 … (0x1<<11) // This bit attention when bit 11 of the state register is set.
71364 … (0x1<<12) // This bit attention when bit 12 of the state register is set.
71366 …nstruction in the decode stage of the pipeline. Bits 31-2 are implemented. '1's written to bits 1-…
71369 …set bit 7 in mode register). This register is intended to allow a way to return from an interrupt …
71373 … (0x1<<0) // Reset: 1 When this bit is set, the hardware break…
71377 … (0x3fffffff<<2) // This field sets the 32-bit word on which the…
71380 … (0x7ff<<0) // 11 bit set-1 debug visibility v…
71384 … (0xf<<12) // 4 bit select for the peek value of the set-1 debug visibility v…
71386 … (0x7ff<<16) // 11 bit set-2 debug visibility v…
71390 … (0xf<<28) // 4 bit select for the peek value of the set-2 debug visibility v…
71399 …/ While the processor is halted, the general purpose processor registers (r0-r31) can be read and …
71402 …o specify the bit at the auto-polled address that indicates "link up". The bit which corresponds t…
71404 …xffff<<16) // This value is used to define the register address in MDIO auto-poll transactions. Fo…
71407 …-B0, on the first read of this register when the START_BUSY bit returns to '0', this value, in the…
71413 … field controls the type of MDIO transaction that will be performed when the START_BUSY bit is set.
71415 … is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurr…
71417 …set in the emac_status register. Writing this bit as a '0' has no effect. This bit must be read as…
71420 …by the MDIO interface if auto-polling is enabled. The value of this bit is reflected by in the mai…
71427 … (0x1<<1) // If this bit is set, the 32-bit pre-amble will not be generated duri…
71431 …-polling. When auto-polling is on, the START_BUSY bit in the mdio_comm register must not be set. T…
71437 …f this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of …
71439 …MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit t…
71441 …to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if …
71453 …set to 1 this bit indicates that the current MDIO transaction will be executed as a Clause 45 tran…
71456 … (0x1<<0) // This bit is set each time an error …
71463 … which of the uC interfaces will be accessed when the access_mode field is set to specific_read or…
71476 …arpCore SERDES microcontroller program memory interfaces. This register auto-increments after each…
71481 … (0x1<<0) // Write this bit as a '1' to set ext_uc_enable for t…
71483 … (0x1<<1) // Write this bit as a '1' to set ext_uc_enable for t…
71485 … (0x1<<2) // Write this bit as a '1' to set ext_uc_enable for t…
71508 … which of the uC interfaces will be accessed when the access_mode field is set to specific_read or…
71521 … 2 PCIE SERDES microcontroller program memory interfaces. This register auto-increments after each…
71526 … (0x1<<0) // Write this bit as a '1' to set ext_uc_enable for t…
71528 … (0x1<<1) // Write this bit as a '1' to set ext_uc_enable for t…
71542 …address offset for the AVS RBUS program memory interface. This register auto-increments after each…
71547 … (0x1f<<0) // Number of bytes to be transfered in Read or Write operation. Valid lengths are 0-16.
71570 …ice ID of the Slave Device. This is a 7-bit field as defined by the I2C spec, but can be written h…
71598 … This bit indicates that M2P is currently sending a packet. If this bit is set, no new data should…
71600 …indicates that in In-Use Error has occured. This is generated if a new VDM transfer is started whe…
71604 … (0x1<<3) // This bit is set when the Length spe…
71606 … (0x1<<4) // This bit is set when a packet is transmitted while the VDM Lengt…
71620 … (0x7f<<0) // This is the length of the VDM packet, in 32-bit DWords. 0x0 is an…
71659 … (0x1<<1) // When set, this bit forces P2…
71661 …<<2) // When set, this bit will cause any packet that doesn't match one of the two Vendor ID Filte…
71668 …_DISCARD (0x1<<16) // When set, this bit causes pa…
71670 …_ENABLE (0x1<<17) // When set, this VID Filter is…
71675 …_DISCARD (0x1<<16) // When set, this bit causes pa…
71677 …_ENABLE (0x1<<17) // When set, this VID Filter is…
71684 …ISCARD (0x1<<16) // When set, packets matching t…
71698 …/Access:R DataWidth:0x20 // Reading this register will give the next 32-bits of the current H…
71707 … 0xe06240UL //Access:R DataWidth:0x20 // 32-bit Packet Data.
71709 … (0x7f<<0) // 7-bit Length from VDM H…
71712 … (0xffff<<0) // 16-bit PCI Requester ID …
71715 … (0xffff<<0) // 16-bit Vendor ID from VD…
71718 … (0xffff<<0) // 16-bit FID from VDM Head…
71720 … 0xe06254UL //Access:R DataWidth:0x20 // 32-bit Vendor Defined DW…
71730 … (0xff<<16) // This is the 8-bit Tag from VDM Head…
71734 … (0x1<<0) // If this bit is cleared then the look-up is bypassed and th…
71738 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71747 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71756 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71765 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71774 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71783 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71792 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71801 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71810 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71819 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71828 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71837 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71846 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71855 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71864 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71873 … (0x1<<0) // If set, this page is treated as part of the static memory. When…
71906 …//Access:RW DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction hi…
71907 …//Access:RW DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction mi…
71911 … (0x1<<1) // If set, this page is the m…
71920 … (0x1<<1) // If set, this page is the m…
71928 …_BOUNDS_READ (0x1<<0) // If set, Paging_enable is c…
71930 …L_FETCH (0x1<<1) // If set, a read attempt to …
71933 … (0x1<<0) // When set, the entire NVM sta…
71939 …e clear before setting this bit. This bit is self clearing and will remain set while the command i…
71941 … (0x1<<5) // The Write/Not_Read command bit. Set high to execute wri…
71943 … (0x1<<6) // The erase page/sector command bit. Set high to execute a p…
71945 … (0x1<<7) // This bit is passed to the SEE_FSM or SPI_FSM if the pass_mode bit is set.
71947 … (0x1<<8) // When this bit is set, the next command s…
71949 … (0x1<<9) // When this bit is set, the address in the…
71953 …nd bit. Set '1' will make flash interface state machine Generate wren_cmd to flash device through …
71955 …nd bit. Set '1' will make flash interface state machine Generate wrdi_cmd to flash device through …
71957 … (0x1<<18) // The erase all/chip command bit. Set high to execute an …
71961 … (0x1<<20) // The read ID command bit. When set, the flash controll…
71963 … (0x1<<21) // The read status command bit. When set, the flash controll…
71965 …when the FIRST bit is set, the 256B page mode is disabled for the next operation. It is self-clear…
71972 …/ 24 bit address value used in read, write and erase operations. When in bit-bang mode, the bottom…
71976 … (0x1<<0) // Legacy strap_value[1]. Read only. Set based on new strap …
71978 … (0x1<<1) // Legacy strap_value[0]. Read only. Set based on new strap …
71980 … (0x1<<2) // Enable pass-thru mode to the byte…
71982 … (0x1<<3) // Enable bit-bang mode to control …
71984 …s "ready". This is automatically interpreted by hardware. This value is self-configured on reset b…
71992 … (0x1<<23) // Legacy strap_control[1] bit. Read only set to 1, indicating FL…
71994 … (0x1<<24) // Legacy strap_value[2]. Read only. Set based on new strap …
71996 … (0x1<<25) // Legacy strap_value[3]. Read only. Set based on new strap …
71998 … (0x1<<26) // Legacy strap_value[1]. Read only. Set based on new strap …
72000 … (0x1<<27) // Legacy strap_value[0]. Read only. Set based on new strap …
72002 … (0x1<<28) // Legacy strap_value[2]. Read only. Set based on new strap …
72004 … (0x1<<29) // Legacy strap_value[3]. Read only. Set based on new strap …
72006 … (0x1<<30) // Legacy strap_control[1] bit. Read only set to 1, indicating FL…
72029 … (0x1<<0) // Set Software Arbitration request Bit 0. This bit …
72031 … (0x1<<1) // Set Software Arbitration request Bit 1. This bit …
72033 … (0x1<<2) // Set Software Arbitration request Bit 2. This bit …
72035 … (0x1<<3) // Set Software Arbitration request Bit 3. This bit …
72053 …nt status of requester 0. When this bit is one, it means that REQ_SET0 has been set since REQ_CLR0.
72055 …nt status of requester 1. When this bit is one, it means that REQ_SET1 has been set since REQ_CLR1.
72057 …nt status of requester 2. When this bit is one, it means that REQ_SET2 has been set since REQ_CLR2.
72059 …nt status of requester 3. When this bit is one, it means that REQ_SET3 has been set since REQ_CLR3.
72069 …rface state machine through SPI interface To flash device, and make the flash device write-enabled.
72071 …face state machine through SPI interface To flash device, and make the flash device write-disabled.
72077 … (0x1<<30) // When set to 1, write operati…
72079 … (0x1<<31) // Set to 1 to use legacy/…
72082 …s not used by FLSH hardware. It is only used by software. This value is self-configured on reset b…
72084 … (0x1<<3) // This bit is self-configured on reset b…
72086 …re to insert an empty address bit when MODE_256 is not set with Atmel devices. This value is self-…
72088 …or Atmel, this defaults to 1. For ST, this defaults to 0. This value is self-configured on reset b…
72090 …set in ST mode, fast read command is used. In Atmel mode, this bit should be set when using the 0x…
72092 … (0x1<<8) // When this bit is set, the SI input from …
72094 …set, the pass mode data is captured one cycle later than normal. If using pass mode, this bit shou…
72096 …bit is set, a turnaround cycle is inserted in between the address and data phases of a status read…
72102 …ng f(SCLK) = f(core_clk)/(2*(SPI_SLOW_CLK_DIV +1)). [Ex: SPI_SLOW_CLK_DIV=0 -> f(SCLK) = f(core…
72104 …Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK ge…
72106 …Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK ge…
72108 …Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK ge…
72110 …Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK ge…
72112 …Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK ge…
72114 …Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK ge…
72116 …Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK ge…
72118 …Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK ge…
72120 …Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK ge…
72122 … 0xe06430UL //Access:RW DataWidth:0x20 // NVM re-configuration registe…
72125 …ally encode how the FLSH has been reconfigured. On reset, this register is set to the same value a…
72129 …s bit is 0 on reset. After software finishes reconfiguring FLSH, they will set this bit to 1 to in…
72134 … (0x1<<1) // When this bit is set to '1', the expansi…
72146 … (0x1<<28) // This bit is set to '1' when the cac…
72148 … (0x1<<29) // This bit is set to '1' when an arbi…
72150 … (0x1<<30) // This bit is set to '1' when a read …
72152 … (0x1<<31) // This bit is set to '1' when the exp…
72167 …AR area, it will place the offset from the BAR value in this register and re-try the PCI bus to ma…
72173 … (0x1<<31) // This bit will be set if there is a pendi…
72211 …This bit indicates that this image loader engine is busy. When this bit is set, the baddr/gaddr/cf…
72248 …This bit indicates that this image loader engine is busy. When this bit is set, the baddr/gaddr/cf…
72285 …This bit indicates that this image loader engine is busy. When this bit is set, the baddr/gaddr/cf…
72292 … (0x1<<7) // When this bit is set HW will service the ARP Assign Address comman…
72294 … (0x1<<8) // When this bit is set the SMBUS block wil…
72296 … (0x1<<9) // When this bit is set the SMBUS block wil…
72310 … bit is '1', the SMBUS block is placed into bit-bang mode. SMBUS interface pins are controlled usi…
72312 …0) // When this bit is '1', the SMBUS block is enabled for operation. When set the SMBUS block wil…
72314 … (0x1<<31) // When this bit is set it will reset SMBUS…
72325 … (0x1<<31) // When this bit is set the SMBUS block ope…
72336 …s address is also used for ARP. The address will be resolved using ARP when the ARP_EN1 bit is set.
72347 …old the SMBUS block will generate an event for the control processor. When set to 0x0 event genera…
72355 … (0x1<<30) // When this bit is set HW will flush Maste…
72357 … (0x1<<31) // When this bit is set HW will flush Maste…
72362 …old the SMBUS block will generate an event for the control processor. When set to 0x0 event genera…
72370 … (0x1<<30) // When this bit is set HW will flush Slave…
72372 … (0x1<<31) // When this bit is set HW will flush Slave…
72377 … (0x1<<28) // When the SMBUS interface is configured for bit-bang mode, this bit c…
72381 … (0x1<<30) // When the SM Bus interface is configured for bit-bang mode, this bit c…
72402 … number of bytes that SMBUS block should read from the slave in Block Write - Block Read Process C…
72410 …its encode status of the last master transaction. Valid when START_BUSY is cleared after it was set
72414 … (0x1<<30) // Transaction Abort. This bit can be set at any time by the …
72416 … has no effect. This bit must be read as a '0' before setting it to prevent un-predictable results.
72425 …bits encode status of the last slave transaction. Valid when START_BUSY is cleared after it was set
72429 …set at any time by the firmware or the driver in order to abort the transaction. The HW will abort…
72431 …as no effect. This bit must be read as a '0' before setting it to prevent un-predictable results. …
72434 … (0x1<<0) // When set enables Watchdog Ti…
72436 …N (0x1<<1) // When set enables Heartbeat T…
72438 … (0x1<<2) // When set enables ASF Sensor …
72440 …_EN (0x1<<3) // When set enables Legacy Sens…
72442 …EN (0x1<<4) // When set enables Retransmit …
72446 … (0x1<<20) // When set enables hardware to generate smbus event any time and ARP command is receiv…
72450 …UN_EN (0x1<<22) // When set enables generation …
72452 …Y_EN (0x1<<23) // When set enables generation …
72456 …OLD_HIT_EN (0x1<<25) // When set enables SLAVE_RX_TH…
72458 …ULL_EN (0x1<<26) // When set enables SLAVE_RX_FI…
72460 …RUN_EN (0x1<<27) // When set enables generation …
72462 …SY_EN (0x1<<28) // When set enables generation …
72464 …_EN (0x1<<29) // When set enables MASTER_RX_E…
72466 …HOLD_HIT_EN (0x1<<30) // When set enables MASTER_RX_T…
72468 …FULL_EN (0x1<<31) // When set enables MASTER_RX_F…
72483 … (0x1<<20) // This bit set when slave hardware received an ARP command and ARP_EN0 or…
72485 … (0x1<<21) // This bit is set when slave hardware…
72487 … (0x1<<22) // This bit is set when Slave Tx FIFO …
72489 … (0x1<<23) // This bit is set when slave START_BU…
72491 … (0x1<<24) // This bit is set when the slave rece…
72493 … (0x1<<25) // This bit is set when the slave rece…
72495 … (0x1<<26) // This bit is set when the slave rece…
72497 … (0x1<<27) // This bit is set when Master Tx FIFO…
72499 … (0x1<<28) // This bit is set when master START_B…
72501 … (0x1<<29) // This bit is set when the master rec…
72503 …T (0x1<<30) // This bit is set when the master rec…
72505 … (0x1<<31) // This bit is set when the master rec…
72512 … (0x1<<31) // 0 - Byte other then last in an WMBUS transaction …
72519 …ck the PEC only in case where PEC bit in SMBUS Master Command Register was set for rhe transaction…
72540 … (0x1<<0) // This bit should be set by firmware before ARP_EN0 bit is set. This bit is t…
72542 … (0x1<<1) // This bit should be set by firmware before ARP_EN0 bit is set.…
72546 … (0x1<<4) // This bit should be set by firmware before ARP_EN1 bit is set. This bit is t…
72548 … (0x1<<5) // This bit should be set by firmware before ARP_EN1 bit is set.…
72550 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN0 bit is set.
72559 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN0 bit is set.
72568 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN0 bit is set.
72577 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN0 bit is set.
72586 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN1 bit is set.
72595 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN1 bit is set.
72604 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN1 bit is set.
72613 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN1 bit is set.
72626 … (0x1<<1) // Setting this bit to '1' will set the error bit for t…
72684 … processor. This can be modified at any time and may be used for processor-to-processor communicat…
72700 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
72702 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
72704 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
72706 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
72750 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
72786 … (0x1<<0) // This bit should be set to disable the DMA …
72788 … (0x1<<1) // This bit should be set to disable the time…
72790 … (0x1<<2) // This bit should be set to disable the CCFC…
72792 … (0x1<<3) // This bit should be set to disable the TCFC…
72794 … (0x1<<4) // This bit should be set to disable the inte…
72796 … (0x1<<5) // This bit should be set to disable the SDM …
72798 … (0x1<<6) // This bit should be set to disable the GRC …
72800 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from process…
72802 … (0x1<<8) // This bit should be set to disable the PRM …
72804 … (0x1<<9) // This bit should be set to disable the DORQ…
72815 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
72865 … (0x1<<29) // Last-cycle indication not …
72870 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
72872 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
72874 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
72876 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
72878 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
72880 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
72882 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
72884 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
72886 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
72888 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
72890 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
72892 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
72894 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
72896 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
72898 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
72900 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
72902 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
72904 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
72906 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
72908 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
72910 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
72912 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
72914 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
72916 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
72918 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
72920 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
72922 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
72924 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
72926 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
72928 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
72930 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
72941 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
72991 …E5 (0x1<<29) // Last-cycle indication not …
73004 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73054 …_E5 (0x1<<29) // Last-cycle indication not …
73059 … (0x1<<5) // This bit masks, when set, the Parity bit: XS…
73061 … (0x1<<0) // This bit masks, when set, the Parity bit: XS…
73063 … (0x1<<0) // This bit masks, when set, the Parity bit: XS…
73065 … (0x1<<1) // This bit masks, when set, the Parity bit: XS…
73067 … (0x1<<1) // This bit masks, when set, the Parity bit: XS…
73069 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
73071 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
73073 … (0x1<<3) // This bit masks, when set, the Parity bit: XS…
73075 … (0x1<<4) // This bit masks, when set, the Parity bit: XS…
73077 … (0x1<<5) // This bit masks, when set, the Parity bit: XS…
73079 … (0x1<<6) // This bit masks, when set, the Parity bit: XS…
73081 … (0x1<<7) // This bit masks, when set, the Parity bit: XS…
73083 … (0x1<<8) // This bit masks, when set, the Parity bit: XS…
73085 … (0x1<<3) // This bit masks, when set, the Parity bit: XS…
73087 … (0x1<<9) // This bit masks, when set, the Parity bit: XS…
73089 … (0x1<<9) // This bit masks, when set, the Parity bit: XS…
73091 … (0x1<<10) // This bit masks, when set, the Parity bit: XS…
73100 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
73101 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
73102 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
73104 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
73107 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
73127 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
73204 … 0xf82000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73206 … 0xf82400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
73208 … 0xf82800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
73210 … 0xf82c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
73212 … 0xf83000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
73214 … 0xf83400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
73216 … 0xf83800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
73218 … 0xf83c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
73220 … 0xf84000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
73241 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
73243 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
73245 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
73247 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73291 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
73327 … (0x1<<0) // This bit should be set to disable the DMA …
73329 … (0x1<<1) // This bit should be set to disable the time…
73331 … (0x1<<2) // This bit should be set to disable the CCFC…
73333 … (0x1<<3) // This bit should be set to disable the TCFC…
73335 … (0x1<<4) // This bit should be set to disable the inte…
73337 … (0x1<<5) // This bit should be set to disable the SDM …
73339 … (0x1<<6) // This bit should be set to disable the GRC …
73341 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from process…
73343 … (0x1<<8) // This bit should be set to disable the PRM …
73345 … (0x1<<9) // This bit should be set to disable the DORQ…
73356 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73406 … (0x1<<29) // Last-cycle indication not …
73411 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
73413 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
73415 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
73417 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
73419 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
73421 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
73423 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
73425 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
73427 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
73429 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
73431 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
73433 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
73435 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
73437 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
73439 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
73441 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
73443 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
73445 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
73447 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
73449 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
73451 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
73453 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
73455 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
73457 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
73459 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
73461 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
73463 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
73465 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
73467 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
73469 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
73471 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
73482 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73532 …E5 (0x1<<29) // Last-cycle indication not …
73545 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73595 …_E5 (0x1<<29) // Last-cycle indication not …
73600 … (0x1<<5) // This bit masks, when set, the Parity bit: YS…
73602 … (0x1<<0) // This bit masks, when set, the Parity bit: YS…
73604 … (0x1<<0) // This bit masks, when set, the Parity bit: YS…
73606 … (0x1<<1) // This bit masks, when set, the Parity bit: YS…
73608 … (0x1<<1) // This bit masks, when set, the Parity bit: YS…
73610 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
73612 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
73614 … (0x1<<3) // This bit masks, when set, the Parity bit: YS…
73616 … (0x1<<4) // This bit masks, when set, the Parity bit: YS…
73618 … (0x1<<5) // This bit masks, when set, the Parity bit: YS…
73620 … (0x1<<6) // This bit masks, when set, the Parity bit: YS…
73622 … (0x1<<7) // This bit masks, when set, the Parity bit: YS…
73624 … (0x1<<8) // This bit masks, when set, the Parity bit: YS…
73626 … (0x1<<3) // This bit masks, when set, the Parity bit: YS…
73628 … (0x1<<9) // This bit masks, when set, the Parity bit: YS…
73637 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
73638 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
73639 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
73641 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
73644 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
73665 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
73742 … 0xf92000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73744 … 0xf92400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
73746 … 0xf92800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
73748 … 0xf92c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
73750 … 0xf93000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
73752 … 0xf93400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
73754 … 0xf93800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
73756 … 0xf93c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
73758 … 0xf94000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
73779 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
73781 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
73783 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
73785 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73829 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
73865 … (0x1<<0) // This bit should be set to disable the DMA …
73867 … (0x1<<1) // This bit should be set to disable the time…
73869 … (0x1<<2) // This bit should be set to disable the CCFC…
73871 … (0x1<<3) // This bit should be set to disable the TCFC…
73873 … (0x1<<4) // This bit should be set to disable the inte…
73875 … (0x1<<5) // This bit should be set to disable the SDM …
73877 … (0x1<<6) // This bit should be set to disable the GRC …
73879 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from process…
73881 … (0x1<<8) // This bit should be set to disable the PRM …
73883 … (0x1<<9) // This bit should be set to disable the DORQ…
73894 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73944 … (0x1<<29) // Last-cycle indication not …
73949 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
73951 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
73953 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
73955 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
73957 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
73959 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
73961 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
73963 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
73965 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
73967 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
73969 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
73971 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
73973 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
73975 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
73977 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
73979 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
73981 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
73983 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
73985 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
73987 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
73989 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
73991 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
73993 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
73995 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
73997 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
73999 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
74001 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
74003 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
74005 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
74007 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
74009 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
74020 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74070 …E5 (0x1<<29) // Last-cycle indication not …
74083 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74133 …_E5 (0x1<<29) // Last-cycle indication not …
74138 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
74140 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
74142 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
74144 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
74146 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
74148 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
74150 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
74152 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
74154 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
74156 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
74158 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
74160 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
74162 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
74164 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
74166 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
74168 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
74170 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
74172 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
74174 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
74182 …3_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
74184 …4_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for mem…
74199 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
74200 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
74201 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
74203 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
74206 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
74227 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
74304 … 0xfa2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74306 … 0xfa2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
74308 … 0xfa2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
74310 … 0xfa2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
74312 … 0xfa3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
74314 … 0xfa3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
74316 … 0xfa3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
74318 … 0xfa3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
74320 … 0xfa4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
74341 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
74343 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
74345 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
74347 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74391 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
74427 … (0x1<<0) // This bit should be set to disable the DMA …
74429 … (0x1<<1) // This bit should be set to disable the time…
74431 … (0x1<<2) // This bit should be set to disable the CCFC…
74433 … (0x1<<3) // This bit should be set to disable the TCFC…
74435 … (0x1<<4) // This bit should be set to disable the inte…
74437 … (0x1<<5) // This bit should be set to disable the SDM …
74439 … (0x1<<6) // This bit should be set to disable the GRC …
74441 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from process…
74443 … (0x1<<8) // This bit should be set to disable the PRM …
74445 … (0x1<<9) // This bit should be set to disable the DORQ…
74456 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74506 … (0x1<<29) // Last-cycle indication not …
74511 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
74513 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
74515 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
74517 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
74519 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
74521 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
74523 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
74525 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
74527 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
74529 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
74531 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
74533 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
74535 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
74537 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
74539 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
74541 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
74543 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
74545 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
74547 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
74549 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
74551 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
74553 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
74555 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
74557 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
74559 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
74561 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
74563 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
74565 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
74567 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
74569 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
74571 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
74582 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74632 …E5 (0x1<<29) // Last-cycle indication not …
74645 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74695 …_E5 (0x1<<29) // Last-cycle indication not …
74700 … (0x1<<6) // This bit masks, when set, the Parity bit: TS…
74702 … (0x1<<0) // This bit masks, when set, the Parity bit: TS…
74704 … (0x1<<0) // This bit masks, when set, the Parity bit: TS…
74706 … (0x1<<1) // This bit masks, when set, the Parity bit: TS…
74708 … (0x1<<1) // This bit masks, when set, the Parity bit: TS…
74710 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
74712 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
74714 … (0x1<<3) // This bit masks, when set, the Parity bit: TS…
74716 … (0x1<<3) // This bit masks, when set, the Parity bit: TS…
74718 … (0x1<<4) // This bit masks, when set, the Parity bit: TS…
74720 … (0x1<<5) // This bit masks, when set, the Parity bit: TS…
74722 … (0x1<<6) // This bit masks, when set, the Parity bit: TS…
74724 … (0x1<<7) // This bit masks, when set, the Parity bit: TS…
74726 … (0x1<<8) // This bit masks, when set, the Parity bit: TS…
74728 … (0x1<<9) // This bit masks, when set, the Parity bit: TS…
74730 … (0x1<<4) // This bit masks, when set, the Parity bit: TS…
74732 … (0x1<<10) // This bit masks, when set, the Parity bit: TS…
74741 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
74742 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
74743 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
74745 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
74748 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
74768 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
74845 … 0xfb2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74847 … 0xfb2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
74849 … 0xfb2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
74851 … 0xfb2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
74853 … 0xfb3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
74855 … 0xfb3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
74857 … 0xfb3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
74859 … 0xfb3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
74861 … 0xfb4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
74882 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
74884 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
74886 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
74888 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74932 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
74968 … (0x1<<0) // This bit should be set to disable the DMA …
74970 … (0x1<<1) // This bit should be set to disable the time…
74972 … (0x1<<2) // This bit should be set to disable the CCFC…
74974 … (0x1<<3) // This bit should be set to disable the TCFC…
74976 … (0x1<<4) // This bit should be set to disable the inte…
74978 … (0x1<<5) // This bit should be set to disable the SDM …
74980 … (0x1<<6) // This bit should be set to disable the GRC …
74982 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from process…
74984 … (0x1<<8) // This bit should be set to disable the PRM …
74986 … (0x1<<9) // This bit should be set to disable the DORQ…
74997 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75047 … (0x1<<29) // Last-cycle indication not …
75052 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
75054 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
75056 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
75058 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
75060 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
75062 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
75064 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
75066 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
75068 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
75070 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
75072 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
75074 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
75076 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
75078 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
75080 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
75082 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
75084 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
75086 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
75088 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
75090 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
75092 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
75094 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
75096 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
75098 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
75100 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
75102 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
75104 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
75106 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
75108 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
75110 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
75112 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
75123 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75173 …E5 (0x1<<29) // Last-cycle indication not …
75186 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75236 …_E5 (0x1<<29) // Last-cycle indication not …
75241 … (0x1<<0) // This bit masks, when set, the Parity bit: MS…
75243 … (0x1<<1) // This bit masks, when set, the Parity bit: MS…
75245 … (0x1<<10) // This bit masks, when set, the Parity bit: MS…
75247 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
75249 … (0x1<<0) // This bit masks, when set, the Parity bit: MS…
75251 … (0x1<<3) // This bit masks, when set, the Parity bit: MS…
75253 … (0x1<<1) // This bit masks, when set, the Parity bit: MS…
75255 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
75257 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
75259 … (0x1<<5) // This bit masks, when set, the Parity bit: MS…
75261 … (0x1<<3) // This bit masks, when set, the Parity bit: MS…
75263 … (0x1<<6) // This bit masks, when set, the Parity bit: MS…
75265 … (0x1<<5) // This bit masks, when set, the Parity bit: MS…
75267 … (0x1<<7) // This bit masks, when set, the Parity bit: MS…
75269 … (0x1<<8) // This bit masks, when set, the Parity bit: MS…
75271 … (0x1<<7) // This bit masks, when set, the Parity bit: MS…
75273 … (0x1<<9) // This bit masks, when set, the Parity bit: MS…
75275 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
75277 … (0x1<<10) // This bit masks, when set, the Parity bit: MS…
75279 … (0x1<<6) // This bit masks, when set, the Parity bit: MS…
75281 … (0x1<<11) // This bit masks, when set, the Parity bit: MS…
75283 … (0x1<<8) // This bit masks, when set, the Parity bit: MS…
75285 … (0x1<<9) // This bit masks, when set, the Parity bit: MS…
75293 …3_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
75295 …4_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for mem…
75310 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
75311 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
75312 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
75314 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
75317 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
75339 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
75416 … 0xfc2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75418 … 0xfc2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
75420 … 0xfc2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
75422 … 0xfc2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
75424 … 0xfc3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
75426 … 0xfc3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
75428 … 0xfc3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
75430 … 0xfc3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
75432 … 0xfc4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
75453 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
75455 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
75457 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
75459 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
75503 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
75539 … (0x1<<0) // This bit should be set to disable the DMA …
75541 … (0x1<<1) // This bit should be set to disable the time…
75543 … (0x1<<2) // This bit should be set to disable the CCFC…
75545 … (0x1<<3) // This bit should be set to disable the TCFC…
75547 … (0x1<<4) // This bit should be set to disable the inte…
75549 … (0x1<<5) // This bit should be set to disable the SDM …
75551 … (0x1<<6) // This bit should be set to disable the GRC …
75553 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from process…
75555 … (0x1<<8) // This bit should be set to disable the PRM …
75557 … (0x1<<9) // This bit should be set to disable the DORQ…
75568 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75618 … (0x1<<29) // Last-cycle indication not …
75623 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
75625 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
75627 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
75629 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
75631 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
75633 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
75635 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
75637 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
75639 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
75641 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
75643 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
75645 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
75647 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
75649 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
75651 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
75653 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
75655 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
75657 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
75659 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
75661 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
75663 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
75665 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
75667 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
75669 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
75671 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
75673 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
75675 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
75677 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
75679 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
75681 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
75683 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
75694 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75744 …E5 (0x1<<29) // Last-cycle indication not …
75757 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75807 …_E5 (0x1<<29) // Last-cycle indication not …
75812 … (0x1<<9) // This bit masks, when set, the Parity bit: US…
75814 … (0x1<<0) // This bit masks, when set, the Parity bit: US…
75816 … (0x1<<0) // This bit masks, when set, the Parity bit: US…
75818 … (0x1<<1) // This bit masks, when set, the Parity bit: US…
75820 … (0x1<<1) // This bit masks, when set, the Parity bit: US…
75822 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
75824 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
75826 … (0x1<<3) // This bit masks, when set, the Parity bit: US…
75828 … (0x1<<4) // This bit masks, when set, the Parity bit: US…
75830 … (0x1<<5) // This bit masks, when set, the Parity bit: US…
75832 … (0x1<<6) // This bit masks, when set, the Parity bit: US…
75834 … (0x1<<7) // This bit masks, when set, the Parity bit: US…
75836 … (0x1<<8) // This bit masks, when set, the Parity bit: US…
75838 … (0x1<<3) // This bit masks, when set, the Parity bit: US…
75840 … (0x1<<9) // This bit masks, when set, the Parity bit: US…
75842 … (0x1<<5) // This bit masks, when set, the Parity bit: US…
75844 … (0x1<<10) // This bit masks, when set, the Parity bit: US…
75853 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
75854 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
75855 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
75857 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
75860 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
75881 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
75958 … 0xfd2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75960 … 0xfd2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
75962 … 0xfd2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
75964 … 0xfd2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
75966 … 0xfd3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
75968 … 0xfd3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
75970 … 0xfd3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
75972 … 0xfd3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
75974 … 0xfd4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
75982 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
76026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76027 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76029 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76031 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76033 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76035 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76037 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76039 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76041 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76042 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76043 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76044 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76045 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76046 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76047 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76048 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76049 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76050 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76051 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76052 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76053 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76054 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76055 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76056 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76057 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76058 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76059 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76060 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76061 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76062 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76063 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76064 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76065 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76066 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76067 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76068 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76069 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76070 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76071 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76073 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76074 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76113 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
76115 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
76117 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
76119 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
76121 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
76123 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
76125 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
76127 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
76129 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
76131 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
76133 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
76135 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
76137 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
76139 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
76141 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
76143 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
76145 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
76147 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
76262 … (0x1<<19) // In-process Table overflo…
76275 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
76277 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
76279 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
76281 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
76283 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
76285 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
76287 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
76289 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
76291 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
76293 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
76295 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
76297 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
76299 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
76301 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
76303 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
76305 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
76307 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
76309 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
76311 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
76313 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
76315 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
76317 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
76319 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
76321 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
76323 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
76364 … (0x1<<19) // In-process Table overflo…
76415 … (0x1<<19) // In-process Table overflo…
76445 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
76447 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
76449 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
76451 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
76453 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
76455 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
76457 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
76459 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
76496 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76498 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76500 … (0x1<<1) // This bit masks, when set, the Parity bit: XC…
76502 … (0x1<<2) // This bit masks, when set, the Parity bit: XC…
76504 … (0x1<<3) // This bit masks, when set, the Parity bit: XC…
76506 … (0x1<<4) // This bit masks, when set, the Parity bit: XC…
76508 … (0x1<<5) // This bit masks, when set, the Parity bit: XC…
76510 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76512 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76514 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76516 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76518 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76520 … (0x1<<9) // This bit masks, when set, the Parity bit: XC…
76522 … (0x1<<10) // This bit masks, when set, the Parity bit: XC…
76524 … (0x1<<11) // This bit masks, when set, the Parity bit: XC…
76526 … (0x1<<14) // This bit masks, when set, the Parity bit: XC…
76528 … (0x1<<12) // This bit masks, when set, the Parity bit: XC…
76530 … (0x1<<12) // This bit masks, when set, the Parity bit: XC…
76532 … (0x1<<13) // This bit masks, when set, the Parity bit: XC…
76534 … (0x1<<13) // This bit masks, when set, the Parity bit: XC…
76536 … (0x1<<14) // This bit masks, when set, the Parity bit: XC…
76538 … (0x1<<27) // This bit masks, when set, the Parity bit: XC…
76540 … (0x1<<15) // This bit masks, when set, the Parity bit: XC…
76542 … (0x1<<15) // This bit masks, when set, the Parity bit: XC…
76544 … (0x1<<16) // This bit masks, when set, the Parity bit: XC…
76546 … (0x1<<16) // This bit masks, when set, the Parity bit: XC…
76548 … (0x1<<17) // This bit masks, when set, the Parity bit: XC…
76550 … (0x1<<17) // This bit masks, when set, the Parity bit: XC…
76552 … (0x1<<18) // This bit masks, when set, the Parity bit: XC…
76554 … (0x1<<18) // This bit masks, when set, the Parity bit: XC…
76556 … (0x1<<19) // This bit masks, when set, the Parity bit: XC…
76558 … (0x1<<19) // This bit masks, when set, the Parity bit: XC…
76560 … (0x1<<20) // This bit masks, when set, the Parity bit: XC…
76562 … (0x1<<20) // This bit masks, when set, the Parity bit: XC…
76564 … (0x1<<21) // This bit masks, when set, the Parity bit: XC…
76566 … (0x1<<21) // This bit masks, when set, the Parity bit: XC…
76568 … (0x1<<22) // This bit masks, when set, the Parity bit: XC…
76570 … (0x1<<22) // This bit masks, when set, the Parity bit: XC…
76572 … (0x1<<24) // This bit masks, when set, the Parity bit: XC…
76574 … (0x1<<23) // This bit masks, when set, the Parity bit: XC…
76576 … (0x1<<23) // This bit masks, when set, the Parity bit: XC…
76578 … (0x1<<25) // This bit masks, when set, the Parity bit: XC…
76580 … (0x1<<24) // This bit masks, when set, the Parity bit: XC…
76582 … (0x1<<24) // This bit masks, when set, the Parity bit: XC…
76584 … (0x1<<25) // This bit masks, when set, the Parity bit: XC…
76586 … (0x1<<25) // This bit masks, when set, the Parity bit: XC…
76588 … (0x1<<26) // This bit masks, when set, the Parity bit: XC…
76590 … (0x1<<26) // This bit masks, when set, the Parity bit: XC…
76592 … (0x1<<27) // This bit masks, when set, the Parity bit: XC…
76594 … (0x1<<28) // This bit masks, when set, the Parity bit: XC…
76596 … (0x1<<28) // This bit masks, when set, the Parity bit: XC…
76598 … (0x1<<29) // This bit masks, when set, the Parity bit: XC…
76600 … (0x1<<29) // This bit masks, when set, the Parity bit: XC…
76602 … (0x1<<30) // This bit masks, when set, the Parity bit: XC…
76604 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76606 … (0x1<<5) // This bit masks, when set, the Parity bit: XC…
76608 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76610 … (0x1<<23) // This bit masks, when set, the Parity bit: XC…
76612 … (0x1<<27) // This bit masks, when set, the Parity bit: XC…
76614 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76616 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76618 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76620 … (0x1<<30) // This bit masks, when set, the Parity bit: XC…
76623 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76625 … (0x1<<1) // This bit masks, when set, the Parity bit: XC…
76627 … (0x1<<1) // This bit masks, when set, the Parity bit: XC…
76629 … (0x1<<2) // This bit masks, when set, the Parity bit: XC…
76631 … (0x1<<2) // This bit masks, when set, the Parity bit: XC…
76633 … (0x1<<3) // This bit masks, when set, the Parity bit: XC…
76635 … (0x1<<3) // This bit masks, when set, the Parity bit: XC…
76637 … (0x1<<4) // This bit masks, when set, the Parity bit: XC…
76639 … (0x1<<4) // This bit masks, when set, the Parity bit: XC…
76641 … (0x1<<5) // This bit masks, when set, the Parity bit: XC…
76643 … (0x1<<5) // This bit masks, when set, the Parity bit: XC…
76645 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76647 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76649 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76651 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76653 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76655 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76657 … (0x1<<9) // This bit masks, when set, the Parity bit: XC…
76659 … (0x1<<9) // This bit masks, when set, the Parity bit: XC…
76661 … (0x1<<10) // This bit masks, when set, the Parity bit: XC…
76663 … (0x1<<10) // This bit masks, when set, the Parity bit: XC…
76665 … (0x1<<11) // This bit masks, when set, the Parity bit: XC…
76667 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76707 …_I_ECC_PRTY_BB (0x1<<0) // Set parity only for mem…
76709 …_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
76711 …_I_ECC_0_PRTY (0x1<<1) // Set parity only for mem…
76713 …_I_ECC_1_PRTY (0x1<<2) // Set parity only for mem…
76715 …_I_ECC_2_PRTY (0x1<<3) // Set parity only for mem…
76717 …_I_ECC_3_PRTY (0x1<<4) // Set parity only for mem…
76719 …_I_ECC_0_PRTY_E5 (0x1<<5) // Set parity only for mem…
76721 …_I_ECC_1_PRTY_E5 (0x1<<6) // Set parity only for mem…
76723 …_I_ECC_0_PRTY_K2 (0x1<<6) // Set parity only for mem…
76725 …_I_ECC_0_PRTY_E5 (0x1<<7) // Set parity only for mem…
76727 …_I_ECC_1_PRTY_K2 (0x1<<7) // Set parity only for mem…
76729 …_I_ECC_1_PRTY_E5 (0x1<<8) // Set parity only for mem…
76731 …_I_ECC_PRTY_K2 (0x1<<0) // Set parity only for mem…
76733 …_I_ECC_PRTY_BB_K2 (0x1<<5) // Set parity only for mem…
76735 …_I_ECC_PRTY_K2 (0x1<<8) // Set parity only for mem…
76737 …_I_ECC_0_PRTY_BB (0x1<<6) // Set parity only for mem…
76739 …_I_ECC_1_PRTY_BB (0x1<<7) // Set parity only for mem…
76741 …_I_ECC_PRTY_BB (0x1<<8) // Set parity only for mem…
76781 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
76782 …UL //Access:RW DataWidth:0x8 // The Event ID in case one of errors is set in QM input message.
76783 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76784 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76785 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76786 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76787 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76788 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76789 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76790 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76791 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76792 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76793 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76794 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76795 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76796 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76797 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76798 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76799 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76800 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76801 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76802 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76803 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76804 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76805 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76806 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76807 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76808 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76810 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76812 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76814 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76816 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76817 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76818 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76819 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76820 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76821 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76822 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76823 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76824 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76825 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76826 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76827 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76828 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76829 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76830 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76831 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76832 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76833 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76834 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76835 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76836 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76849 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76850 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76851 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76852 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76853 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76854 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76855 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
76856 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76857 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76858 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76859 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76860 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76861 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76862 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76863 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76864 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76865 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76866 … 0x1000680UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
76868 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
76879 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
76880 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
76881 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
76883 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
76888 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76889 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76890 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76891 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
76901 … 0x1000794UL //Access:RC DataWidth:0x1 // Set when the error; ind…
76905 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76906 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76907 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76908 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76909 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76910 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76911 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76912 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76913 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76914 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76915 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76916 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76917 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76918 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76919 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76920 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76921 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76922 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76923 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76924 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76925 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76926 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76927 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76928 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76941 … Is used to determine the number of the AG context REGQ written back; when the Reg1WbFlg isn't set.
76942 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
76943 … 0x1000904UL //Access:RW DataWidth:0xa // [9]: PQ Type (0-Other PQ; 1-TX PQ); if bit[…
76944 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
76945 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
76946 … 0x1000a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
76947 … 0x1000a10UL //Access:R DataWidth:0x1 // In-process Table almost …
76952 … 0x1000a24UL //Access:RW DataWidth:0x1 // If set, Xx connection bypa…
76969 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
76970 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
76971 …th:0x5 // QM output initial credit (XCM TX queues). Max credit available - 16.Write writes the …
76972 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
76975 … 0x1000aacUL //Access:RC DataWidth:0x1 // Set at message length m…
76976 … 0x1000ab0UL //Access:RC DataWidth:0x1 // Set at message length m…
76977 … 0x1000ab4UL //Access:RC DataWidth:0x1 // Set at message length m…
76978 … 0x1000ab8UL //Access:RC DataWidth:0x1 // Set at message length m…
76979 … 0x1000abcUL //Access:RC DataWidth:0x1 // Set at message length m…
77008 …tive counter overflow/uder-run. Is reset on read. [0] - If set, there was under-run; [1] - If set,…
77025 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
77028 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
77030 …ess:R DataWidth:0x20 // Debug read from XSEM Input stage buffer with 32-bits granularity. Rea…
77032 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
77034 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
77036 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
77038 …ess:R DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Rea…
77040 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
77042 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
77043 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
77044 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
77050 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
77053 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
77247 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77248 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77249 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77250 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77251 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77252 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77253 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77254 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77255 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77256 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77257 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77258 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77259 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77260 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77261 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77262 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77265 … 0x1000aa8UL //Access:RC DataWidth:0x1 // Set at message length m…
77266 … 0x1001e44UL //Access:RC DataWidth:0x1 // Set at message length m…
77273 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
77283 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
77284 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
77286 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
77288 …alue. [28:20] PQ number. [29:29] Reserved. [31:30] Command type: 0 - SET; 1 - DEC; 2 - INC; The ad…
77291 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
77333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77334 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77336 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77338 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77371 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
77373 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
77375 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
77377 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
77379 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
77381 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
77383 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
77385 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
77387 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
77389 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
77391 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
77393 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
77395 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
77397 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
77399 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
77492 … (0x1<<14) // In-process Table overflo…
77511 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
77513 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
77515 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
77517 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
77519 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
77521 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
77523 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
77525 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
77527 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
77529 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
77531 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
77533 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
77535 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
77537 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
77539 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
77541 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
77543 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
77545 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
77547 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
77549 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
77551 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
77553 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
77555 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
77586 … (0x1<<14) // In-process Table overflo…
77633 … (0x1<<14) // In-process Table overflo…
77655 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
77664 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77666 … (0x1<<1) // This bit masks, when set, the Parity bit: YC…
77668 … (0x1<<2) // This bit masks, when set, the Parity bit: YC…
77670 … (0x1<<3) // This bit masks, when set, the Parity bit: YC…
77672 … (0x1<<4) // This bit masks, when set, the Parity bit: YC…
77674 … (0x1<<6) // This bit masks, when set, the Parity bit: YC…
77676 … (0x1<<5) // This bit masks, when set, the Parity bit: YC…
77678 … (0x1<<7) // This bit masks, when set, the Parity bit: YC…
77680 … (0x1<<6) // This bit masks, when set, the Parity bit: YC…
77682 … (0x1<<7) // This bit masks, when set, the Parity bit: YC…
77684 … (0x1<<8) // This bit masks, when set, the Parity bit: YC…
77686 … (0x1<<9) // This bit masks, when set, the Parity bit: YC…
77688 … (0x1<<27) // This bit masks, when set, the Parity bit: YC…
77690 … (0x1<<10) // This bit masks, when set, the Parity bit: YC…
77692 … (0x1<<13) // This bit masks, when set, the Parity bit: YC…
77694 … (0x1<<14) // This bit masks, when set, the Parity bit: YC…
77696 … (0x1<<11) // This bit masks, when set, the Parity bit: YC…
77698 … (0x1<<26) // This bit masks, when set, the Parity bit: YC…
77700 … (0x1<<11) // This bit masks, when set, the Parity bit: YC…
77702 … (0x1<<12) // This bit masks, when set, the Parity bit: YC…
77704 … (0x1<<25) // This bit masks, when set, the Parity bit: YC…
77706 … (0x1<<13) // This bit masks, when set, the Parity bit: YC…
77708 … (0x1<<10) // This bit masks, when set, the Parity bit: YC…
77710 … (0x1<<14) // This bit masks, when set, the Parity bit: YC…
77712 … (0x1<<11) // This bit masks, when set, the Parity bit: YC…
77714 … (0x1<<12) // This bit masks, when set, the Parity bit: YC…
77716 … (0x1<<15) // This bit masks, when set, the Parity bit: YC…
77718 … (0x1<<16) // This bit masks, when set, the Parity bit: YC…
77720 … (0x1<<23) // This bit masks, when set, the Parity bit: YC…
77722 … (0x1<<17) // This bit masks, when set, the Parity bit: YC…
77724 … (0x1<<24) // This bit masks, when set, the Parity bit: YC…
77726 … (0x1<<18) // This bit masks, when set, the Parity bit: YC…
77728 … (0x1<<12) // This bit masks, when set, the Parity bit: YC…
77730 … (0x1<<13) // This bit masks, when set, the Parity bit: YC…
77732 … (0x1<<19) // This bit masks, when set, the Parity bit: YC…
77734 … (0x1<<16) // This bit masks, when set, the Parity bit: YC…
77736 … (0x1<<17) // This bit masks, when set, the Parity bit: YC…
77738 … (0x1<<20) // This bit masks, when set, the Parity bit: YC…
77740 … (0x1<<17) // This bit masks, when set, the Parity bit: YC…
77742 … (0x1<<18) // This bit masks, when set, the Parity bit: YC…
77744 … (0x1<<21) // This bit masks, when set, the Parity bit: YC…
77746 … (0x1<<18) // This bit masks, when set, the Parity bit: YC…
77748 … (0x1<<19) // This bit masks, when set, the Parity bit: YC…
77750 … (0x1<<22) // This bit masks, when set, the Parity bit: YC…
77752 … (0x1<<14) // This bit masks, when set, the Parity bit: YC…
77754 … (0x1<<15) // This bit masks, when set, the Parity bit: YC…
77756 … (0x1<<23) // This bit masks, when set, the Parity bit: YC…
77758 … (0x1<<24) // This bit masks, when set, the Parity bit: YC…
77760 … (0x1<<25) // This bit masks, when set, the Parity bit: YC…
77762 … (0x1<<26) // This bit masks, when set, the Parity bit: YC…
77764 … (0x1<<22) // This bit masks, when set, the Parity bit: YC…
77766 … (0x1<<23) // This bit masks, when set, the Parity bit: YC…
77768 … (0x1<<27) // This bit masks, when set, the Parity bit: YC…
77770 … (0x1<<20) // This bit masks, when set, the Parity bit: YC…
77772 … (0x1<<22) // This bit masks, when set, the Parity bit: YC…
77774 … (0x1<<28) // This bit masks, when set, the Parity bit: YC…
77776 … (0x1<<29) // This bit masks, when set, the Parity bit: YC…
77778 … (0x1<<20) // This bit masks, when set, the Parity bit: YC…
77780 … (0x1<<30) // This bit masks, when set, the Parity bit: YC…
77782 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77784 … (0x1<<3) // This bit masks, when set, the Parity bit: YC…
77786 … (0x1<<4) // This bit masks, when set, the Parity bit: YC…
77788 … (0x1<<5) // This bit masks, when set, the Parity bit: YC…
77790 … (0x1<<8) // This bit masks, when set, the Parity bit: YC…
77792 … (0x1<<9) // This bit masks, when set, the Parity bit: YC…
77794 … (0x1<<15) // This bit masks, when set, the Parity bit: YC…
77796 … (0x1<<16) // This bit masks, when set, the Parity bit: YC…
77798 … (0x1<<19) // This bit masks, when set, the Parity bit: YC…
77800 … (0x1<<21) // This bit masks, when set, the Parity bit: YC…
77802 … (0x1<<24) // This bit masks, when set, the Parity bit: YC…
77804 … (0x1<<25) // This bit masks, when set, the Parity bit: YC…
77806 … (0x1<<26) // This bit masks, when set, the Parity bit: YC…
77808 … (0x1<<27) // This bit masks, when set, the Parity bit: YC…
77810 … (0x1<<28) // This bit masks, when set, the Parity bit: YC…
77812 … (0x1<<28) // This bit masks, when set, the Parity bit: YC…
77814 … (0x1<<29) // This bit masks, when set, the Parity bit: YC…
77816 … (0x1<<29) // This bit masks, when set, the Parity bit: YC…
77818 … (0x1<<30) // This bit masks, when set, the Parity bit: YC…
77820 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77822 … (0x1<<3) // This bit masks, when set, the Parity bit: YC…
77824 … (0x1<<4) // This bit masks, when set, the Parity bit: YC…
77826 … (0x1<<5) // This bit masks, when set, the Parity bit: YC…
77828 … (0x1<<8) // This bit masks, when set, the Parity bit: YC…
77830 … (0x1<<9) // This bit masks, when set, the Parity bit: YC…
77832 … (0x1<<21) // This bit masks, when set, the Parity bit: YC…
77834 … (0x1<<30) // This bit masks, when set, the Parity bit: YC…
77837 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77839 … (0x1<<1) // This bit masks, when set, the Parity bit: YC…
77841 … (0x1<<2) // This bit masks, when set, the Parity bit: YC…
77843 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77845 … (0x1<<3) // This bit masks, when set, the Parity bit: YC…
77847 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77849 … (0x1<<1) // This bit masks, when set, the Parity bit: YC…
77851 … (0x1<<4) // This bit masks, when set, the Parity bit: YC…
77853 … (0x1<<5) // This bit masks, when set, the Parity bit: YC…
77855 … (0x1<<1) // This bit masks, when set, the Parity bit: YC…
77857 … (0x1<<2) // This bit masks, when set, the Parity bit: YC…
77859 … (0x1<<6) // This bit masks, when set, the Parity bit: YC…
77861 … (0x1<<2) // This bit masks, when set, the Parity bit: YC…
77863 … (0x1<<3) // This bit masks, when set, the Parity bit: YC…
77865 … (0x1<<7) // This bit masks, when set, the Parity bit: YC…
77922 …_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
77924 …_I_ECC_0_PRTY (0x1<<1) // Set parity only for mem…
77926 …_I_ECC_1_PRTY (0x1<<2) // Set parity only for mem…
77928 …_I_ECC_0_PRTY_E5 (0x1<<3) // Set parity only for mem…
77930 …_I_ECC_1_PRTY_E5 (0x1<<4) // Set parity only for mem…
77932 …_I_ECC_0_PRTY_BB_K2 (0x1<<6) // Set parity only for mem…
77934 …_I_ECC_0_PRTY_E5 (0x1<<5) // Set parity only for mem…
77936 …_I_ECC_1_PRTY_BB_K2 (0x1<<7) // Set parity only for mem…
77938 …_I_ECC_1_PRTY_E5 (0x1<<6) // Set parity only for mem…
77940 …_I_ECC_PRTY_E5 (0x1<<7) // Set parity only for mem…
77942 …_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only for mem…
77944 …_I_ECC_1_PRTY_E5 (0x1<<9) // Set parity only for mem…
77946 …_I_ECC_PRTY_K2 (0x1<<0) // Set parity only for mem…
77948 …_I_ECC_0_PRTY_K2 (0x1<<3) // Set parity only for mem…
77950 …_I_ECC_1_PRTY_K2 (0x1<<4) // Set parity only for mem…
77952 …_I_ECC_PRTY_K2 (0x1<<5) // Set parity only for mem…
77954 …_I_ECC_0_PRTY_K2 (0x1<<8) // Set parity only for mem…
77956 …_I_ECC_1_PRTY_K2 (0x1<<9) // Set parity only for mem…
77958 …_I_ECC_PRTY_BB (0x1<<0) // Set parity only for mem…
77960 …_I_ECC_0_PRTY_BB (0x1<<3) // Set parity only for mem…
77962 …_I_ECC_1_PRTY_BB (0x1<<4) // Set parity only for mem…
77964 …_I_ECC_PRTY_BB (0x1<<5) // Set parity only for mem…
77966 …_I_ECC_0_PRTY_BB (0x1<<8) // Set parity only for mem…
77968 …_I_ECC_1_PRTY_BB (0x1<<9) // Set parity only for mem…
78022 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
78071 …UL //Access:RW DataWidth:0x8 // The Event ID in case one of errors is set in QM input message.
78072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78073 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78074 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78075 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78076 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78077 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78078 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78079 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78080 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78081 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78091 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78092 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78093 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78094 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78095 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78096 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78097 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
78098 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78099 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78100 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78101 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78102 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78103 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78104 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78105 … 0x1080664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
78107 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78108 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78121 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
78122 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
78123 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
78125 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
78130 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78131 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78132 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78133 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
78146 … 0x10807a0UL //Access:RC DataWidth:0x1 // Set when the error; ind…
78150 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78151 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78152 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78153 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78154 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78155 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78156 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78157 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78158 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78159 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78160 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78161 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78162 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78163 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78164 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78165 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78166 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78167 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78168 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78169 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78170 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78171 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78172 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78173 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78213 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
78214 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
78219 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78220 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78221 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78222 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78223 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78224 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78225 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78226 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78227 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78228 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78229 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78230 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78231 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78232 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78233 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78242 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
78243 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
78244 … 0x1080a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
78245 … 0x1080a10UL //Access:R DataWidth:0x1 // In-process Table almost …
78251 … 0x1080a28UL //Access:RW DataWidth:0x1 // If set, Xx connection bypa…
78252 … 0x1080a2cUL //Access:RW DataWidth:0x1 // If set, Xx task bypass sta…
78269 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
78270 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
78271 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
78272 …1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the i…
78273 …th:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the i…
78276 … 0x1080aacUL //Access:RC DataWidth:0x1 // Set at message length m…
78277 … 0x1080ab0UL //Access:RC DataWidth:0x1 // Set at message length m…
78278 … 0x1080ab4UL //Access:RC DataWidth:0x1 // Set at message length m…
78312 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
78314 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
78316 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
78318 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
78320 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
78321 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
78322 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
78323 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
78324 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
78333 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
78336 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
78508 … 0x1080aa8UL //Access:RC DataWidth:0x1 // Set at message length m…
78509 … 0x1081ec4UL //Access:RC DataWidth:0x1 // Set at message length m…
78516 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
78517 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
78519 …ess:R DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Rea…
78520 …ess:R DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Rea…
78525 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
78526 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
78529 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78535 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
78536 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
78539 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
78569 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
78571 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
78573 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
78575 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
78577 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
78579 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
78581 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
78583 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
78585 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
78658 …K2 (0x1<<10) // In-process Table overflo…
78660 … (0x1<<8) // In-process Table overflo…
78679 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
78681 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
78683 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
78685 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
78687 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
78689 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
78691 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
78693 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
78695 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
78697 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
78699 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
78701 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
78703 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
78705 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
78707 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
78709 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
78711 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
78713 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
78715 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
78717 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
78719 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
78721 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
78723 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
78725 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
78727 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
78729 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
78764 …BB_K2 (0x1<<10) // In-process Table overflo…
78766 …_E5 (0x1<<8) // In-process Table overflo…
78817 …_BB_K2 (0x1<<10) // In-process Table overflo…
78819 …L_E5 (0x1<<8) // In-process Table overflo…
78841 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
78850 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
78852 … (0x1<<1) // This bit masks, when set, the Parity bit: PC…
78854 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
78856 … (0x1<<3) // This bit masks, when set, the Parity bit: PC…
78858 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
78860 … (0x1<<3) // This bit masks, when set, the Parity bit: PC…
78862 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
78864 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
78866 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
78868 … (0x1<<3) // This bit masks, when set, the Parity bit: PC…
78870 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
78872 … (0x1<<13) // This bit masks, when set, the Parity bit: PC…
78874 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
78876 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
78878 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
78880 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
78882 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
78884 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
78886 … (0x1<<8) // This bit masks, when set, the Parity bit: PC…
78888 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
78890 … (0x1<<8) // This bit masks, when set, the Parity bit: PC…
78892 … (0x1<<9) // This bit masks, when set, the Parity bit: PC…
78894 … (0x1<<8) // This bit masks, when set, the Parity bit: PC…
78896 … (0x1<<9) // This bit masks, when set, the Parity bit: PC…
78898 … (0x1<<10) // This bit masks, when set, the Parity bit: PC…
78900 … (0x1<<11) // This bit masks, when set, the Parity bit: PC…
78902 … (0x1<<10) // This bit masks, when set, the Parity bit: PC…
78904 … (0x1<<12) // This bit masks, when set, the Parity bit: PC…
78906 … (0x1<<13) // This bit masks, when set, the Parity bit: PC…
78908 … (0x1<<9) // This bit masks, when set, the Parity bit: PC…
78910 … (0x1<<14) // This bit masks, when set, the Parity bit: PC…
78912 … (0x1<<10) // This bit masks, when set, the Parity bit: PC…
78914 … (0x1<<14) // This bit masks, when set, the Parity bit: PC…
78916 … (0x1<<15) // This bit masks, when set, the Parity bit: PC…
78918 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
78920 … (0x1<<1) // This bit masks, when set, the Parity bit: PC…
78922 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
78924 … (0x1<<11) // This bit masks, when set, the Parity bit: PC…
78926 … (0x1<<12) // This bit masks, when set, the Parity bit: PC…
78928 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
78930 … (0x1<<1) // This bit masks, when set, the Parity bit: PC…
78932 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
78960 …_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
78962 …_I_ECC_0_PRTY_E5 (0x1<<1) // Set parity only for mem…
78964 …_I_ECC_1_PRTY_E5 (0x1<<2) // Set parity only for mem…
78966 …_I_ECC_PRTY_K2 (0x1<<0) // Set parity only for mem…
78968 …_I_ECC_0_PRTY_K2 (0x1<<1) // Set parity only for mem…
78970 …_I_ECC_1_PRTY_K2 (0x1<<2) // Set parity only for mem…
78972 …_I_ECC_PRTY_BB (0x1<<0) // Set parity only for mem…
78974 …_I_ECC_0_PRTY_BB (0x1<<1) // Set parity only for mem…
78976 …_I_ECC_1_PRTY_BB (0x1<<2) // Set parity only for mem…
78998 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
78999 …UL //Access:RW DataWidth:0x8 // The Event ID in case one of errors is set in QM input message.
79003 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79004 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79005 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79006 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79007 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79008 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79009 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
79010 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79011 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79012 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79013 … 0x110063cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
79015 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
79025 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
79026 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
79027 … DataWidth:0x2 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
79029 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
79034 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79035 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79036 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79037 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
79042 … 0x1100760UL //Access:RC DataWidth:0x1 // Set when the error; ind…
79052 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
79053 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
79054 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
79055 … 0x1100a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
79056 … 0x1100a10UL //Access:R DataWidth:0x1 // In-process Table almost …
79059 … 0x1100a1cUL //Access:RW DataWidth:0x1 // If set, Xx connection bypa…
79060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
79063 … 0x1100aacUL //Access:RC DataWidth:0x1 // Set at message length m…
79076 …ess:R DataWidth:0x20 // Debug read from PSEM Input stage buffer with 32-bits granularity. Rea…
79079 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
79081 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
79082 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
79085 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
79087 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
79115 … 0x1100aa8UL //Access:RC DataWidth:0x1 // Set at message length m…
79116 … 0x1101754UL //Access:RC DataWidth:0x1 // Set at message length m…
79123 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
79124 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
79127 … 0x11017c4UL //Access:RC DataWidth:0x1 // Set at message length m…
79131 …ess:R DataWidth:0x20 // Debug read from YPLD Input stage buffer with 32-bits granularity. Rea…
79133 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
79135 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
79177 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79178 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79179 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79180 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79182 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79184 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79186 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79187 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79188 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79189 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79190 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79191 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79192 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79193 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79194 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79195 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79196 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79197 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79198 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79199 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79240 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
79242 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
79244 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
79246 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
79248 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
79250 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
79252 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
79254 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
79256 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
79258 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
79260 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
79262 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
79264 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
79266 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
79268 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
79270 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
79272 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
79274 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
79276 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
79399 … (0x1<<21) // In-process Table overflo…
79426 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
79428 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
79430 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
79432 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
79434 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
79436 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
79438 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
79440 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
79442 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
79444 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
79446 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
79448 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
79450 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
79452 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
79454 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
79456 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
79458 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
79460 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
79462 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
79464 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
79466 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
79468 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
79470 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
79472 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
79474 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
79476 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
79478 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
79480 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
79482 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
79484 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
79486 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
79488 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
79490 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
79492 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
79537 … (0x1<<21) // In-process Table overflo…
79606 … (0x1<<21) // In-process Table overflo…
79636 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
79645 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79647 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
79649 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
79651 … (0x1<<3) // This bit masks, when set, the Parity bit: TC…
79653 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
79655 … (0x1<<5) // This bit masks, when set, the Parity bit: TC…
79657 … (0x1<<6) // This bit masks, when set, the Parity bit: TC…
79659 … (0x1<<7) // This bit masks, when set, the Parity bit: TC…
79661 … (0x1<<8) // This bit masks, when set, the Parity bit: TC…
79663 … (0x1<<9) // This bit masks, when set, the Parity bit: TC…
79665 … (0x1<<25) // This bit masks, when set, the Parity bit: TC…
79667 … (0x1<<10) // This bit masks, when set, the Parity bit: TC…
79669 … (0x1<<23) // This bit masks, when set, the Parity bit: TC…
79671 … (0x1<<11) // This bit masks, when set, the Parity bit: TC…
79673 … (0x1<<24) // This bit masks, when set, the Parity bit: TC…
79675 … (0x1<<12) // This bit masks, when set, the Parity bit: TC…
79677 … (0x1<<26) // This bit masks, when set, the Parity bit: TC…
79679 … (0x1<<13) // This bit masks, when set, the Parity bit: TC…
79681 … (0x1<<12) // This bit masks, when set, the Parity bit: TC…
79683 … (0x1<<13) // This bit masks, when set, the Parity bit: TC…
79685 … (0x1<<14) // This bit masks, when set, the Parity bit: TC…
79687 … (0x1<<9) // This bit masks, when set, the Parity bit: TC…
79689 … (0x1<<15) // This bit masks, when set, the Parity bit: TC…
79691 … (0x1<<26) // This bit masks, when set, the Parity bit: TC…
79693 … (0x1<<15) // This bit masks, when set, the Parity bit: TC…
79695 … (0x1<<16) // This bit masks, when set, the Parity bit: TC…
79697 … (0x1<<27) // This bit masks, when set, the Parity bit: TC…
79699 … (0x1<<17) // This bit masks, when set, the Parity bit: TC…
79701 … (0x1<<15) // This bit masks, when set, the Parity bit: TC…
79703 … (0x1<<16) // This bit masks, when set, the Parity bit: TC…
79705 … (0x1<<18) // This bit masks, when set, the Parity bit: TC…
79707 … (0x1<<21) // This bit masks, when set, the Parity bit: TC…
79709 … (0x1<<19) // This bit masks, when set, the Parity bit: TC…
79711 … (0x1<<11) // This bit masks, when set, the Parity bit: TC…
79713 … (0x1<<12) // This bit masks, when set, the Parity bit: TC…
79715 … (0x1<<20) // This bit masks, when set, the Parity bit: TC…
79717 … (0x1<<14) // This bit masks, when set, the Parity bit: TC…
79719 … (0x1<<10) // This bit masks, when set, the Parity bit: TC…
79721 … (0x1<<21) // This bit masks, when set, the Parity bit: TC…
79723 … (0x1<<16) // This bit masks, when set, the Parity bit: TC…
79725 … (0x1<<17) // This bit masks, when set, the Parity bit: TC…
79727 … (0x1<<22) // This bit masks, when set, the Parity bit: TC…
79729 … (0x1<<17) // This bit masks, when set, the Parity bit: TC…
79731 … (0x1<<18) // This bit masks, when set, the Parity bit: TC…
79733 … (0x1<<23) // This bit masks, when set, the Parity bit: TC…
79735 … (0x1<<18) // This bit masks, when set, the Parity bit: TC…
79737 … (0x1<<19) // This bit masks, when set, the Parity bit: TC…
79739 … (0x1<<24) // This bit masks, when set, the Parity bit: TC…
79741 … (0x1<<10) // This bit masks, when set, the Parity bit: TC…
79743 … (0x1<<11) // This bit masks, when set, the Parity bit: TC…
79745 … (0x1<<25) // This bit masks, when set, the Parity bit: TC…
79747 … (0x1<<26) // This bit masks, when set, the Parity bit: TC…
79749 … (0x1<<27) // This bit masks, when set, the Parity bit: TC…
79751 … (0x1<<28) // This bit masks, when set, the Parity bit: TC…
79753 … (0x1<<29) // This bit masks, when set, the Parity bit: TC…
79755 … (0x1<<20) // This bit masks, when set, the Parity bit: TC…
79757 … (0x1<<30) // This bit masks, when set, the Parity bit: TC…
79759 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79761 … (0x1<<3) // This bit masks, when set, the Parity bit: TC…
79763 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
79765 … (0x1<<5) // This bit masks, when set, the Parity bit: TC…
79767 … (0x1<<6) // This bit masks, when set, the Parity bit: TC…
79769 … (0x1<<7) // This bit masks, when set, the Parity bit: TC…
79771 … (0x1<<8) // This bit masks, when set, the Parity bit: TC…
79773 … (0x1<<13) // This bit masks, when set, the Parity bit: TC…
79775 … (0x1<<14) // This bit masks, when set, the Parity bit: TC…
79777 … (0x1<<19) // This bit masks, when set, the Parity bit: TC…
79779 … (0x1<<21) // This bit masks, when set, the Parity bit: TC…
79781 … (0x1<<20) // This bit masks, when set, the Parity bit: TC…
79783 … (0x1<<22) // This bit masks, when set, the Parity bit: TC…
79785 … (0x1<<22) // This bit masks, when set, the Parity bit: TC…
79787 … (0x1<<23) // This bit masks, when set, the Parity bit: TC…
79789 … (0x1<<24) // This bit masks, when set, the Parity bit: TC…
79791 … (0x1<<25) // This bit masks, when set, the Parity bit: TC…
79793 … (0x1<<27) // This bit masks, when set, the Parity bit: TC…
79795 … (0x1<<28) // This bit masks, when set, the Parity bit: TC…
79797 … (0x1<<28) // This bit masks, when set, the Parity bit: TC…
79799 … (0x1<<29) // This bit masks, when set, the Parity bit: TC…
79801 … (0x1<<29) // This bit masks, when set, the Parity bit: TC…
79803 … (0x1<<30) // This bit masks, when set, the Parity bit: TC…
79805 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79807 … (0x1<<3) // This bit masks, when set, the Parity bit: TC…
79809 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
79811 … (0x1<<7) // This bit masks, when set, the Parity bit: TC…
79813 … (0x1<<8) // This bit masks, when set, the Parity bit: TC…
79815 … (0x1<<30) // This bit masks, when set, the Parity bit: TC…
79818 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79820 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
79822 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
79824 … (0x1<<3) // This bit masks, when set, the Parity bit: TC…
79826 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
79828 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79830 … (0x1<<5) // This bit masks, when set, the Parity bit: TC…
79832 … (0x1<<6) // This bit masks, when set, the Parity bit: TC…
79834 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79836 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
79838 … (0x1<<7) // This bit masks, when set, the Parity bit: TC…
79840 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
79842 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
79844 … (0x1<<8) // This bit masks, when set, the Parity bit: TC…
79892 …_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
79894 …_I_ECC_0_PRTY (0x1<<1) // Set parity only for mem…
79896 …_I_ECC_1_PRTY (0x1<<2) // Set parity only for mem…
79898 …_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for mem…
79900 …_I_ECC_0_PRTY_E5 (0x1<<4) // Set parity only for mem…
79902 …_I_ECC_1_PRTY_E5 (0x1<<5) // Set parity only for mem…
79904 …_I_ECC_0_PRTY_E5 (0x1<<6) // Set parity only for mem…
79906 …_I_ECC_1_PRTY_E5 (0x1<<7) // Set parity only for mem…
79908 …_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only for mem…
79910 …_I_ECC_1_PRTY_E5 (0x1<<9) // Set parity only for mem…
79912 …_I_ECC_PRTY_K2 (0x1<<0) // Set parity only for mem…
79914 …_I_ECC_0_PRTY_K2 (0x1<<3) // Set parity only for mem…
79916 …_I_ECC_1_PRTY_K2 (0x1<<4) // Set parity only for mem…
79918 …_I_ECC_0_PRTY_BB_K2 (0x1<<5) // Set parity only for mem…
79920 …_I_ECC_1_PRTY_BB_K2 (0x1<<6) // Set parity only for mem…
79922 …_I_ECC_0_PRTY_K2 (0x1<<7) // Set parity only for mem…
79924 …_I_ECC_1_PRTY_K2 (0x1<<8) // Set parity only for mem…
79926 …_I_ECC_PRTY_BB (0x1<<0) // Set parity only for mem…
79928 …_I_ECC_0_PRTY_BB (0x1<<3) // Set parity only for mem…
79930 …_I_ECC_1_PRTY_BB (0x1<<4) // Set parity only for mem…
79932 …_I_ECC_0_PRTY_BB (0x1<<7) // Set parity only for mem…
79934 …_I_ECC_1_PRTY_BB (0x1<<8) // Set parity only for mem…
79982 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
80023 …UL //Access:RW DataWidth:0x8 // The Event ID in case one of errors is set in QM input message.
80024 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80025 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80027 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80029 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80031 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80033 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80035 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80037 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80039 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80041 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80042 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80043 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80053 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80054 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80055 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80056 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80057 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80058 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80059 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
80060 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80061 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80062 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80063 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80064 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80065 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80066 … 0x1180664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
80068 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80069 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80082 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
80083 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
80084 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
80086 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
80091 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80092 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80093 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80094 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
80107 … 0x11807a0UL //Access:RC DataWidth:0x1 // Set when the error; ind…
80111 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80112 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80113 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80114 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80115 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80116 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80117 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80118 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80119 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80120 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80121 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80122 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80123 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80124 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80125 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80126 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80127 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80128 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80129 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80130 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80131 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80132 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80133 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80134 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80174 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
80175 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
80180 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80182 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80184 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80194 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
80195 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
80196 … 0x1180a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
80197 … 0x1180a10UL //Access:R DataWidth:0x1 // In-process Table almost …
80205 … 0x1180a30UL //Access:RW DataWidth:0x1 // If set, Xx connection bypa…
80206 … 0x1180a34UL //Access:RW DataWidth:0x1 // If set, Xx task bypass sta…
80223 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
80224 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
80225 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
80226 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
80229 … 0x1180aacUL //Access:RC DataWidth:0x1 // Set at message length m…
80230 … 0x1180ab0UL //Access:RC DataWidth:0x1 // Set at message length m…
80231 … 0x1180ab4UL //Access:RC DataWidth:0x1 // Set at message length m…
80264 …ess:R DataWidth:0x20 // Debug read from TSEM Input stage buffer with 32-bits granularity. Rea…
80267 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
80269 …cess:R DataWidth:0x20 // Debug read from PRS Input stage buffer with 32-bits granularity. Rea…
80271 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
80273 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
80275 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
80276 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
80277 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
80278 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
80279 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
80288 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
80291 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
80487 … 0x1180aa8UL //Access:RC DataWidth:0x1 // Set at message length m…
80488 … 0x1181b04UL //Access:RC DataWidth:0x1 // Set at message length m…
80495 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
80496 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
80499 … 0x1181b84UL //Access:RC DataWidth:0x1 // Set at message length m…
80503 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
80506 … 0x1181c04UL //Access:RC DataWidth:0x1 // Set at message length m…
80510 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
80520 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
80521 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
80524 … 0x1181e04UL //Access:RC DataWidth:0x1 // Set at message length m…
80528 …ess:R DataWidth:0x20 // Debug read from PTLD Input stage buffer with 32-bits granularity. Rea…
80530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80535 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80536 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80537 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80538 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80539 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80540 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80541 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80542 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80543 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80544 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80545 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80546 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
80549 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
80591 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80592 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80593 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80594 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80595 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80596 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80653 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
80655 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
80657 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
80659 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
80661 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
80663 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
80665 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
80667 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
80669 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
80671 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
80673 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
80675 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
80677 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
80679 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
80681 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
80683 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
80685 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
80687 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
80689 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
80691 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
80693 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
80695 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
80697 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
80699 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
80701 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
80703 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
80705 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
80848 … (0x1<<15) // In-process Table overflo…
80871 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
80873 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
80875 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
80877 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
80879 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
80881 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
80883 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
80885 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
80887 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
80889 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
80891 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
80893 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
80895 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
80897 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
80899 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
80901 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
80903 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
80905 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
80907 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
80909 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
80911 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
80913 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
80915 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
80917 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
80919 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
80921 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
80954 … (0x1<<15) // In-process Table overflo…
81007 … (0x1<<15) // In-process Table overflo…
81033 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
81042 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
81044 … (0x1<<1) // This bit masks, when set, the Parity bit: MC…
81046 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
81048 … (0x1<<3) // This bit masks, when set, the Parity bit: MC…
81050 … (0x1<<4) // This bit masks, when set, the Parity bit: MC…
81052 … (0x1<<5) // This bit masks, when set, the Parity bit: MC…
81054 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
81056 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
81058 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
81060 … (0x1<<14) // This bit masks, when set, the Parity bit: MC…
81062 … (0x1<<9) // This bit masks, when set, the Parity bit: MC…
81064 … (0x1<<10) // This bit masks, when set, the Parity bit: MC…
81066 … (0x1<<13) // This bit masks, when set, the Parity bit: MC…
81068 … (0x1<<11) // This bit masks, when set, the Parity bit: MC…
81070 … (0x1<<12) // This bit masks, when set, the Parity bit: MC…
81072 … (0x1<<9) // This bit masks, when set, the Parity bit: MC…
81074 … (0x1<<13) // This bit masks, when set, the Parity bit: MC…
81076 … (0x1<<11) // This bit masks, when set, the Parity bit: MC…
81078 … (0x1<<14) // This bit masks, when set, the Parity bit: MC…
81080 … (0x1<<15) // This bit masks, when set, the Parity bit: MC…
81082 … (0x1<<26) // This bit masks, when set, the Parity bit: MC…
81084 … (0x1<<16) // This bit masks, when set, the Parity bit: MC…
81086 … (0x1<<27) // This bit masks, when set, the Parity bit: MC…
81088 … (0x1<<17) // This bit masks, when set, the Parity bit: MC…
81090 … (0x1<<18) // This bit masks, when set, the Parity bit: MC…
81092 … (0x1<<24) // This bit masks, when set, the Parity bit: MC…
81094 … (0x1<<19) // This bit masks, when set, the Parity bit: MC…
81096 … (0x1<<15) // This bit masks, when set, the Parity bit: MC…
81098 … (0x1<<20) // This bit masks, when set, the Parity bit: MC…
81100 … (0x1<<17) // This bit masks, when set, the Parity bit: MC…
81102 … (0x1<<21) // This bit masks, when set, the Parity bit: MC…
81104 … (0x1<<18) // This bit masks, when set, the Parity bit: MC…
81106 … (0x1<<22) // This bit masks, when set, the Parity bit: MC…
81108 … (0x1<<19) // This bit masks, when set, the Parity bit: MC…
81110 … (0x1<<23) // This bit masks, when set, the Parity bit: MC…
81112 … (0x1<<12) // This bit masks, when set, the Parity bit: MC…
81114 … (0x1<<24) // This bit masks, when set, the Parity bit: MC…
81116 … (0x1<<25) // This bit masks, when set, the Parity bit: MC…
81118 … (0x1<<26) // This bit masks, when set, the Parity bit: MC…
81120 … (0x1<<27) // This bit masks, when set, the Parity bit: MC…
81122 … (0x1<<23) // This bit masks, when set, the Parity bit: MC…
81124 … (0x1<<28) // This bit masks, when set, the Parity bit: MC…
81126 … (0x1<<21) // This bit masks, when set, the Parity bit: MC…
81128 … (0x1<<29) // This bit masks, when set, the Parity bit: MC…
81130 … (0x1<<30) // This bit masks, when set, the Parity bit: MC…
81132 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
81134 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
81136 … (0x1<<3) // This bit masks, when set, the Parity bit: MC…
81138 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
81140 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
81142 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
81144 … (0x1<<16) // This bit masks, when set, the Parity bit: MC…
81146 … (0x1<<20) // This bit masks, when set, the Parity bit: MC…
81148 … (0x1<<22) // This bit masks, when set, the Parity bit: MC…
81150 … (0x1<<25) // This bit masks, when set, the Parity bit: MC…
81152 … (0x1<<28) // This bit masks, when set, the Parity bit: MC…
81154 … (0x1<<29) // This bit masks, when set, the Parity bit: MC…
81156 … (0x1<<30) // This bit masks, when set, the Parity bit: MC…
81159 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
81161 … (0x1<<1) // This bit masks, when set, the Parity bit: MC…
81163 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
81165 … (0x1<<3) // This bit masks, when set, the Parity bit: MC…
81167 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
81169 … (0x1<<4) // This bit masks, when set, the Parity bit: MC…
81171 … (0x1<<1) // This bit masks, when set, the Parity bit: MC…
81173 … (0x1<<5) // This bit masks, when set, the Parity bit: MC…
81175 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
81177 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
81179 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
81181 … (0x1<<3) // This bit masks, when set, the Parity bit: MC…
81183 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
81221 …_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
81223 …_I_ECC_PRTY (0x1<<1) // Set parity only for mem…
81225 …_I_ECC_0_PRTY_E5 (0x1<<2) // Set parity only for mem…
81227 …_I_ECC_1_PRTY_E5 (0x1<<3) // Set parity only for mem…
81229 …_I_ECC_0_PRTY (0x1<<4) // Set parity only for mem…
81231 …_I_ECC_1_PRTY (0x1<<5) // Set parity only for mem…
81233 …_I_ECC_PRTY_E5 (0x1<<6) // Set parity only for mem…
81235 …_I_ECC_0_PRTY_E5 (0x1<<7) // Set parity only for mem…
81237 …_I_ECC_1_PRTY_E5 (0x1<<8) // Set parity only for mem…
81239 …_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
81241 …_I_ECC_0_PRTY_BB_K2 (0x1<<2) // Set parity only for mem…
81243 …_I_ECC_1_PRTY_BB_K2 (0x1<<3) // Set parity only for mem…
81245 …_I_ECC_0_PRTY_BB_K2 (0x1<<6) // Set parity only for mem…
81247 …_I_ECC_1_PRTY_BB_K2 (0x1<<7) // Set parity only for mem…
81249 …_I_ECC_PRTY_BB_K2 (0x1<<8) // Set parity only for mem…
81283 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
81332 …UL //Access:RW DataWidth:0x8 // The Event ID in case one of errors is set in QM input message.
81333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81334 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81336 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81338 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81339 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81340 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81341 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81342 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81352 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81353 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81354 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81355 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81356 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81357 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81358 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
81359 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81360 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81361 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81362 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81363 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81364 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81365 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81366 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81367 … 0x120066cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
81369 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81370 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81383 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
81384 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
81385 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
81387 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
81392 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81393 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81394 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81395 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
81408 … 0x12007a0UL //Access:RC DataWidth:0x1 // Set when the error; ind…
81412 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81413 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81414 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81415 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81416 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81417 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81418 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81419 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81420 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81421 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81422 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81423 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81424 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81425 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81426 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81427 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81428 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81429 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81430 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81431 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81432 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81433 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81434 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81435 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81475 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
81476 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
81481 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81482 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81483 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81484 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81485 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81486 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81487 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81488 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81497 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
81498 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
81499 … 0x1200a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
81500 … 0x1200a10UL //Access:R DataWidth:0x1 // In-process Table almost …
81506 … 0x1200a28UL //Access:RW DataWidth:0x1 // If set, Xx connection bypa…
81507 … 0x1200a2cUL //Access:RW DataWidth:0x1 // If set, Xx task bypass sta…
81524 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
81525 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
81526 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
81527 …1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the i…
81528 …th:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the i…
81531 … 0x1200aacUL //Access:RC DataWidth:0x1 // Set at message length m…
81532 … 0x1200ab0UL //Access:RC DataWidth:0x1 // Set at message length m…
81533 … 0x1200ab4UL //Access:RC DataWidth:0x1 // Set at message length m…
81534 … 0x1200ab8UL //Access:RC DataWidth:0x1 // Set at message length m…
81568 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
81571 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
81573 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
81575 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
81577 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
81579 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
81580 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
81581 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
81582 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
81583 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
81592 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
81595 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
81765 …ess:R DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Rea…
81766 …ess:R DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Rea…
81770 … 0x1202804UL //Access:RC DataWidth:0x1 // Set at message length m…
81774 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
81777 … 0x1202884UL //Access:RC DataWidth:0x1 // Set at message length m…
81781 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
81785 … 0x1200aa8UL //Access:RC DataWidth:0x1 // Set at message length m…
81786 … 0x1202904UL //Access:RC DataWidth:0x1 // Set at message length m…
81793 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
81794 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
81804 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
81805 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
81808 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81810 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81812 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81814 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81816 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
81817 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
81820 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
81866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81867 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81868 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81869 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81870 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81871 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81872 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81873 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81874 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81875 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81876 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81877 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81878 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81879 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81880 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81881 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81924 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
81926 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
81928 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
81930 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
81932 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
81934 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
81936 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
81938 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
81940 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
81942 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
81944 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
81946 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
81948 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
81950 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
81952 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
81954 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
81956 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
81958 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
81960 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
81962 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
82121 …K2 (0x1<<18) // In-process Table overflo…
82123 … (0x1<<19) // In-process Table overflo…
82166 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
82168 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
82170 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
82172 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
82174 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
82176 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
82178 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
82180 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
82182 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
82184 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
82186 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
82188 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
82190 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
82192 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
82194 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
82196 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
82198 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
82200 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
82202 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
82204 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
82206 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
82208 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
82210 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
82212 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
82214 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
82216 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
82218 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
82220 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
82222 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
82224 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
82226 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
82228 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
82230 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
82232 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
82234 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
82236 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
82238 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
82240 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
82242 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
82244 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
82246 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
82248 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
82250 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
82252 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
82254 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
82256 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
82258 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
82260 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
82262 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
82264 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
82266 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
82268 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
82270 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
82272 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
82274 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
82276 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
82278 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
82280 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
82282 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
82359 …BB_K2 (0x1<<18) // In-process Table overflo…
82361 …E5 (0x1<<19) // In-process Table overflo…
82478 …_BB_K2 (0x1<<18) // In-process Table overflo…
82480 …_E5 (0x1<<19) // In-process Table overflo…
82526 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
82535 … (0x1<<0) // This bit masks, when set, the Parity bit: UC…
82537 … (0x1<<1) // This bit masks, when set, the Parity bit: UC…
82539 … (0x1<<2) // This bit masks, when set, the Parity bit: UC…
82541 … (0x1<<3) // This bit masks, when set, the Parity bit: UC…
82543 … (0x1<<4) // This bit masks, when set, the Parity bit: UC…
82545 … (0x1<<5) // This bit masks, when set, the Parity bit: UC…
82547 … (0x1<<6) // This bit masks, when set, the Parity bit: UC…
82549 … (0x1<<7) // This bit masks, when set, the Parity bit: UC…
82551 … (0x1<<9) // This bit masks, when set, the Parity bit: UC…
82553 … (0x1<<8) // This bit masks, when set, the Parity bit: UC…
82555 … (0x1<<10) // This bit masks, when set, the Parity bit: UC…
82557 … (0x1<<9) // This bit masks, when set, the Parity bit: UC…
82559 … (0x1<<13) // This bit masks, when set, the Parity bit: UC…
82561 … (0x1<<10) // This bit masks, when set, the Parity bit: UC…
82563 … (0x1<<17) // This bit masks, when set, the Parity bit: UC…
82565 … (0x1<<11) // This bit masks, when set, the Parity bit: UC…
82567 … (0x1<<12) // This bit masks, when set, the Parity bit: UC…
82569 … (0x1<<15) // This bit masks, when set, the Parity bit: UC…
82571 … (0x1<<13) // This bit masks, when set, the Parity bit: UC…
82573 … (0x1<<16) // This bit masks, when set, the Parity bit: UC…
82575 … (0x1<<14) // This bit masks, when set, the Parity bit: UC…
82577 … (0x1<<14) // This bit masks, when set, the Parity bit: UC…
82579 … (0x1<<15) // This bit masks, when set, the Parity bit: UC…
82581 … (0x1<<29) // This bit masks, when set, the Parity bit: UC…
82583 … (0x1<<16) // This bit masks, when set, the Parity bit: UC…
82585 … (0x1<<18) // This bit masks, when set, the Parity bit: UC…
82587 … (0x1<<17) // This bit masks, when set, the Parity bit: UC…
82589 … (0x1<<19) // This bit masks, when set, the Parity bit: UC…
82591 … (0x1<<18) // This bit masks, when set, the Parity bit: UC…
82593 … (0x1<<20) // This bit masks, when set, the Parity bit: UC…
82595 … (0x1<<19) // This bit masks, when set, the Parity bit: UC…
82597 … (0x1<<21) // This bit masks, when set, the Parity bit: UC…
82599 … (0x1<<20) // This bit masks, when set, the Parity bit: UC…
82601 … (0x1<<23) // This bit masks, when set, the Parity bit: UC…
82603 … (0x1<<21) // This bit masks, when set, the Parity bit: UC…
82605 … (0x1<<24) // This bit masks, when set, the Parity bit: UC…
82607 … (0x1<<22) // This bit masks, when set, the Parity bit: UC…
82609 … (0x1<<23) // This bit masks, when set, the Parity bit: UC…
82611 … (0x1<<24) // This bit masks, when set, the Parity bit: UC…
82613 … (0x1<<26) // This bit masks, when set, the Parity bit: UC…
82615 … (0x1<<25) // This bit masks, when set, the Parity bit: UC…
82617 … (0x1<<27) // This bit masks, when set, the Parity bit: UC…
82619 … (0x1<<26) // This bit masks, when set, the Parity bit: UC…
82621 … (0x1<<27) // This bit masks, when set, the Parity bit: UC…
82623 … (0x1<<28) // This bit masks, when set, the Parity bit: UC…
82625 … (0x1<<30) // This bit masks, when set, the Parity bit: UC…
82627 … (0x1<<29) // This bit masks, when set, the Parity bit: UC…
82629 … (0x1<<30) // This bit masks, when set, the Parity bit: UC…
82631 … (0x1<<0) // This bit masks, when set, the Parity bit: UC…
82633 … (0x1<<3) // This bit masks, when set, the Parity bit: UC…
82635 … (0x1<<4) // This bit masks, when set, the Parity bit: UC…
82637 … (0x1<<5) // This bit masks, when set, the Parity bit: UC…
82639 … (0x1<<6) // This bit masks, when set, the Parity bit: UC…
82641 … (0x1<<7) // This bit masks, when set, the Parity bit: UC…
82643 … (0x1<<8) // This bit masks, when set, the Parity bit: UC…
82645 … (0x1<<11) // This bit masks, when set, the Parity bit: UC…
82647 … (0x1<<22) // This bit masks, when set, the Parity bit: UC…
82649 … (0x1<<25) // This bit masks, when set, the Parity bit: UC…
82651 … (0x1<<28) // This bit masks, when set, the Parity bit: UC…
82654 … (0x1<<1) // This bit masks, when set, the Parity bit: UC…
82656 … (0x1<<0) // This bit masks, when set, the Parity bit: UC…
82658 … (0x1<<2) // This bit masks, when set, the Parity bit: UC…
82660 … (0x1<<1) // This bit masks, when set, the Parity bit: UC…
82662 … (0x1<<3) // This bit masks, when set, the Parity bit: UC…
82664 … (0x1<<2) // This bit masks, when set, the Parity bit: UC…
82666 … (0x1<<4) // This bit masks, when set, the Parity bit: UC…
82668 … (0x1<<3) // This bit masks, when set, the Parity bit: UC…
82670 … (0x1<<5) // This bit masks, when set, the Parity bit: UC…
82672 … (0x1<<4) // This bit masks, when set, the Parity bit: UC…
82674 … (0x1<<6) // This bit masks, when set, the Parity bit: UC…
82676 … (0x1<<5) // This bit masks, when set, the Parity bit: UC…
82678 … (0x1<<0) // This bit masks, when set, the Parity bit: UC…
82726 …_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for mem…
82728 …_I_ECC_0_PRTY (0x1<<1) // Set parity only for mem…
82730 …_I_ECC_1_PRTY (0x1<<2) // Set parity only for mem…
82732 …_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for mem…
82734 …_I_ECC_0_PRTY_E5 (0x1<<4) // Set parity only for mem…
82736 …_I_ECC_1_PRTY_E5 (0x1<<5) // Set parity only for mem…
82738 …_I_ECC_0_PRTY_E5 (0x1<<6) // Set parity only for mem…
82740 …_I_ECC_1_PRTY_E5 (0x1<<7) // Set parity only for mem…
82742 …_I_ECC_0_PRTY_BB_K2 (0x1<<9) // Set parity only for mem…
82744 …_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only for mem…
82746 …I_ECC_1_PRTY_BB_K2 (0x1<<10) // Set parity only for mem…
82748 …_I_ECC_1_PRTY_E5 (0x1<<9) // Set parity only for mem…
82750 …_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
82752 …_I_ECC_0_PRTY_BB_K2 (0x1<<3) // Set parity only for mem…
82754 …_I_ECC_1_PRTY_BB_K2 (0x1<<4) // Set parity only for mem…
82756 …_I_ECC_PRTY_BB_K2 (0x1<<5) // Set parity only for mem…
82758 …_I_ECC_0_PRTY_BB_K2 (0x1<<6) // Set parity only for mem…
82760 …_I_ECC_1_PRTY_BB_K2 (0x1<<7) // Set parity only for mem…
82762 …_I_ECC_PRTY_BB_K2 (0x1<<8) // Set parity only for mem…
82764 …I_ECC_PRTY_BB_K2 (0x1<<11) // Set parity only for mem…
82808 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
82849 …UL //Access:RW DataWidth:0x8 // The Event ID in case one of errors is set in QM input message.
82850 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82851 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82852 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82853 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82854 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82855 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82856 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82857 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82858 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82859 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82860 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82861 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82862 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82863 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82864 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82865 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82867 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82882 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82883 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82884 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82885 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82886 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82887 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82888 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
82889 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82890 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82891 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82892 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82893 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82894 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82895 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82896 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82897 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82898 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82899 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82900 … 0x1280684UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
82902 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82903 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82916 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
82917 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
82918 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
82920 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
82925 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82926 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82927 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82928 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
82941 … 0x12807a0UL //Access:RC DataWidth:0x1 // Set when the error; ind…
82945 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82946 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82947 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82948 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82949 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82950 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82951 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82952 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82953 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82954 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82955 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82956 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82957 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82958 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82959 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82960 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82961 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82962 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82963 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82964 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82965 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82966 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82967 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82968 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
83008 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
83009 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
83014 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83015 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83016 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83017 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83018 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83019 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83020 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83021 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83022 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83031 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
83032 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
83033 … 0x1280a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
83034 … 0x1280a10UL //Access:R DataWidth:0x1 // In-process Table almost …
83042 … 0x1280a30UL //Access:RW DataWidth:0x1 // If set, Xx connection bypa…
83043 … 0x1280a34UL //Access:RW DataWidth:0x1 // If set, Xx task bypass sta…
83060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
83061 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
83062 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
83063 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
83066 … 0x1280aa8UL //Access:RC DataWidth:0x1 // Set at message length m…
83067 … 0x1280aacUL //Access:RC DataWidth:0x1 // Set at message length m…
83068 … 0x1280ab0UL //Access:RC DataWidth:0x1 // Set at message length m…
83069 … 0x1280ab4UL //Access:RC DataWidth:0x1 // Set at message length m…
83070 … 0x1280ab8UL //Access:RC DataWidth:0x1 // Set at message length m…
83071 … 0x1280abcUL //Access:RC DataWidth:0x1 // Set at message length m…
83072 … 0x1280ac0UL //Access:RC DataWidth:0x1 // Set at message length m…
83073 … 0x1280ac4UL //Access:RC DataWidth:0x1 // Set at message length m…
83074 … 0x1280ac8UL //Access:RC DataWidth:0x1 // Set at message length m…
83124 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
83127 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
83129 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
83131 …ess:R DataWidth:0x20 // Debug read from RDIF Input stage buffer with 32-bits granularity. Rea…
83133 …ess:R DataWidth:0x20 // Debug read from TDIF Input stage buffer with 32-bits granularity. Rea…
83135 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
83137 …ess:R DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Rea…
83139 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
83141 …ess:R DataWidth:0x20 // Debug read from YULD Input stage buffer with 32-bits granularity. Rea…
83143 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
83144 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
83145 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
83146 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
83147 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
83156 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
83159 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
83353 …ess:R DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Rea…
83354 …ess:R DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Rea…
83363 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
83365 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83366 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83367 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83368 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83369 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83370 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83371 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83372 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83373 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83374 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83375 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83376 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
83424 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
83435 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
83438 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
83440 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
83442 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
83444 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
83446 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
83449 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
83451 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
83453 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
83455 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83458 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
83460 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
83462 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
83464 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83485 …PEND_BLOCK_EN_E5 (0x1<<2) // When set, there may only be …
83487 … (0x1<<3) // When set, the Affintiy field of the thread is set…
83494 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83522 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83570 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83609 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
83611 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
83613 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
83615 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
83617 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
83619 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
83621 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
83623 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
83625 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
83627 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
83629 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
83631 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
83633 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
83635 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
83637 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
83639 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
83641 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
83643 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
83645 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
83647 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
83649 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
83651 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
83653 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
83655 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
83657 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
83659 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
83661 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
83663 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
83665 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
83667 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
83669 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
83671 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
83673 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
83675 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
83677 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
83679 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
83681 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
83683 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
83685 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
83687 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
83689 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
83691 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
83693 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
83695 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
83697 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
83699 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
83701 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
83703 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
83705 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
83707 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
83709 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
83711 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
83713 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
83715 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
83717 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
83719 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
83721 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
83723 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
83725 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
83732 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83760 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83808 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83851 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83879 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83927 … (0x1<<11) // Signals an unknown address in the fast-memory window.
84038 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84040 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84042 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
84044 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84054 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84057 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
84059 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
84061 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
84063 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
84065 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
84067 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
84069 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
84071 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
84073 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
84075 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
84077 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
84079 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
84081 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
84083 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
84085 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
84087 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
84089 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
84091 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
84093 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
84095 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
84097 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
84099 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
84101 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
84103 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
84105 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
84107 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
84109 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
84111 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
84113 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
84115 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
84117 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
84119 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
84121 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
84123 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
84125 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
84127 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
84129 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
84131 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
84133 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
84135 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
84137 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
84139 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
84141 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
84143 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
84145 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
84220 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84222 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84224 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
84226 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84236 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84311 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84313 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84315 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
84317 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84327 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84356 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84358 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84393 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
84395 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
84397 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
84399 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
84401 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
84403 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
84405 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
84407 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
84409 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
84411 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
84413 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
84415 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
84417 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
84419 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
84421 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
84423 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
84425 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
84427 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
84429 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
84431 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
84433 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
84435 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
84437 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
84439 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
84441 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
84443 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
84445 …A_E5 (0x1<<26) // This bit masks, when set, the Interrupt bit:…
84447 …B_E5 (0x1<<27) // This bit masks, when set, the Interrupt bit:…
84449 …5 (0x1<<28) // This bit masks, when set, the Interrupt bit:…
84451 …5 (0x1<<29) // This bit masks, when set, the Interrupt bit:…
84453 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
84482 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84484 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84545 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84547 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84582 … (0x1<<0) // This bit masks, when set, the Parity bit: XS…
84584 … (0x1<<1) // This bit masks, when set, the Parity bit: XS…
84586 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
84588 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
84590 … (0x1<<3) // This bit masks, when set, the Parity bit: XS…
84592 … (0x1<<4) // This bit masks, when set, the Parity bit: XS…
84594 … (0x1<<1) // This bit masks, when set, the Parity bit: XS…
84597 … (0x1<<0) // This bit masks, when set, the Parity bit: XS…
84599 … (0x1<<1) // This bit masks, when set, the Parity bit: XS…
84601 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
84603 … (0x1<<3) // This bit masks, when set, the Parity bit: XS…
84605 … (0x1<<4) // This bit masks, when set, the Parity bit: XS…
84607 … (0x1<<5) // This bit masks, when set, the Parity bit: XS…
84609 … (0x1<<6) // This bit masks, when set, the Parity bit: XS…
84617 …6_I_ECC_0_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
84619 …6_I_ECC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
84628 … 0x1400408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
84629 … 0x140040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
84630 … 0x1400420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
84633 … 0x1400440UL //Access:R DataWidth:0x10 // This read-only register provide…
84640 … 0x1400458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-powe…
84641 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
84642 … set the mode of the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on…
84643 …set the DRA RD block cut through mode in which write to a thread address section passive buffer ma…
84647 … 0x1400600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
84649 …set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface w…
84650 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
84653 … 0x14006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows th…
84656 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
84658 …set, an attempt to write to the passive buffer over the external passive interface will be enabled…
84659 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84660 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84662 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
84664 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
84667 …0x1400b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
84670 …400b0cUL //Access:W DataWidth:0x6 // Thread ID. Write thread ID will set ready indication fo…
84674 …1400b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
84675 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
84677 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
84681 … 0x1400d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
84683 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
84685 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
84686 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
84690 … 0x1401008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DR…
84696 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
84701 …- No external stall is asserted when Storm's breakpoint is set (either by PRAM accessed ocpcode or…
84714 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
84717 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
84720 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
84721 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
84733 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
84738 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
84749 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
84751 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
84756 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
84759 …s. The counter is incremanted only for the event IDs which have Debug Monitor event indication set.
84772 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
84782 … 0x1408000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
84788 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
84793 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84794 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84847 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
84858 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
84861 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
84863 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
84865 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
84867 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
84869 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
84872 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
84874 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
84876 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
84878 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84881 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
84883 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
84885 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
84887 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84908 …PEND_BLOCK_EN_E5 (0x1<<2) // When set, there may only be …
84910 … (0x1<<3) // When set, the Affintiy field of the thread is set…
84917 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
84945 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84993 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85032 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
85034 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
85036 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
85038 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
85040 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
85042 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
85044 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
85046 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
85048 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
85050 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
85052 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
85054 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
85056 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
85058 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
85060 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
85062 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
85064 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
85066 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
85068 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
85070 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
85072 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
85074 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
85076 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
85078 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
85080 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
85082 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
85084 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
85086 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
85088 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
85090 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
85092 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
85094 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
85096 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
85098 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
85100 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
85102 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
85104 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
85106 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
85108 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
85110 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
85112 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
85114 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
85116 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
85118 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
85120 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
85122 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
85124 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
85126 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
85128 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
85130 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
85132 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
85134 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
85136 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
85138 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
85140 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
85142 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
85144 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
85146 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
85148 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
85155 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85183 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85231 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85274 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85302 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85350 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85461 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85463 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85465 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
85467 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85477 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85480 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
85482 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
85484 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
85486 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
85488 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
85490 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
85492 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
85494 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
85496 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
85498 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
85500 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
85502 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
85504 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
85506 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
85508 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
85510 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
85512 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
85514 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
85516 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
85518 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
85520 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
85522 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
85524 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
85526 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
85528 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
85530 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
85532 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
85534 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
85536 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
85538 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
85540 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
85542 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
85544 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
85546 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
85548 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
85550 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
85552 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
85554 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
85556 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
85558 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
85560 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
85562 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
85564 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
85566 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
85568 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
85643 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85645 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85647 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
85649 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85659 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85734 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85736 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85738 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
85740 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85750 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85779 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85781 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85816 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
85818 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
85820 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
85822 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
85824 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
85826 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
85828 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
85830 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
85832 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
85834 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
85836 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
85838 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
85840 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
85842 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
85844 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
85846 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
85848 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
85850 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
85852 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
85854 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
85856 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
85858 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
85860 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
85862 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
85864 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
85866 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
85868 …A_E5 (0x1<<26) // This bit masks, when set, the Interrupt bit:…
85870 …B_E5 (0x1<<27) // This bit masks, when set, the Interrupt bit:…
85872 …5 (0x1<<28) // This bit masks, when set, the Interrupt bit:…
85874 …5 (0x1<<29) // This bit masks, when set, the Interrupt bit:…
85876 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
85905 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85907 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85968 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85970 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
86005 … (0x1<<0) // This bit masks, when set, the Parity bit: YS…
86007 … (0x1<<1) // This bit masks, when set, the Parity bit: YS…
86009 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
86011 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
86013 … (0x1<<3) // This bit masks, when set, the Parity bit: YS…
86015 … (0x1<<4) // This bit masks, when set, the Parity bit: YS…
86017 … (0x1<<1) // This bit masks, when set, the Parity bit: YS…
86020 … (0x1<<0) // This bit masks, when set, the Parity bit: YS…
86022 … (0x1<<1) // This bit masks, when set, the Parity bit: YS…
86024 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
86026 … (0x1<<3) // This bit masks, when set, the Parity bit: YS…
86028 … (0x1<<4) // This bit masks, when set, the Parity bit: YS…
86030 … (0x1<<5) // This bit masks, when set, the Parity bit: YS…
86032 … (0x1<<6) // This bit masks, when set, the Parity bit: YS…
86040 …6_I_ECC_0_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
86042 …6_I_ECC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
86051 … 0x1500408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
86052 … 0x150040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
86053 … 0x1500420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
86056 … 0x1500440UL //Access:R DataWidth:0x10 // This read-only register provide…
86063 … 0x1500458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-powe…
86064 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
86065 … set the mode of the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on…
86066 …set the DRA RD block cut through mode in which write to a thread address section passive buffer ma…
86070 … 0x1500600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
86072 …set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface w…
86073 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
86076 … 0x15006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows th…
86079 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
86081 …set, an attempt to write to the passive buffer over the external passive interface will be enabled…
86082 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86083 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86085 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
86087 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
86090 …0x1500b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
86093 …500b0cUL //Access:W DataWidth:0x6 // Thread ID. Write thread ID will set ready indication fo…
86097 …1500b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
86098 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
86100 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
86104 … 0x1500d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
86106 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
86108 …L //Access:RW DataWidth:0xe // Provides access to the thread ordering queue pop-enable vector.
86109 … //Access:RW DataWidth:0xe // Provides access to the thread ordering queue wake-enable vector.
86113 … 0x1501008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DR…
86119 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
86124 …- No external stall is asserted when Storm's breakpoint is set (either by PRAM accessed ocpcode or…
86137 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
86140 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
86143 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
86144 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
86156 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
86161 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
86172 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
86174 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
86179 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
86182 …s. The counter is incremanted only for the event IDs which have Debug Monitor event indication set.
86195 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
86205 … 0x1508000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the ex…
86211 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
86216 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86217 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86271 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
86282 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
86285 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
86287 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
86289 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
86291 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
86293 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
86296 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
86298 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
86300 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
86302 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86305 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
86307 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
86309 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
86311 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86332 …PEND_BLOCK_EN_E5 (0x1<<2) // When set, there may only be …
86334 … (0x1<<3) // When set, the Affintiy field of the thread is set…
86341 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86369 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86417 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86456 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
86458 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
86460 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
86462 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
86464 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
86466 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
86468 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
86470 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
86472 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
86474 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
86476 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
86478 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
86480 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
86482 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
86484 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
86486 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
86488 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
86490 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
86492 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
86494 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
86496 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
86498 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
86500 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
86502 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
86504 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
86506 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
86508 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
86510 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
86512 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
86514 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
86516 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
86518 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
86520 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
86522 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
86524 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
86526 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
86528 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
86530 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
86532 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
86534 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
86536 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
86538 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
86540 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
86542 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
86544 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
86546 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
86548 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
86550 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
86552 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
86554 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
86556 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
86558 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
86560 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
86562 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
86564 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
86566 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
86568 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
86570 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
86572 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
86579 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86607 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86655 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86698 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86726 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86774 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86885 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
86887 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
86889 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
86891 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86901 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
86904 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
86906 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
86908 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
86910 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
86912 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
86914 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
86916 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
86918 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
86920 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
86922 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
86924 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
86926 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
86928 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
86930 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
86932 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
86934 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
86936 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
86938 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
86940 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
86942 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
86944 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
86946 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
86948 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
86950 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
86952 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
86954 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
86956 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
86958 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
86960 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
86962 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
86964 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
86966 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
86968 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
86970 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
86972 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
86974 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
86976 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
86978 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
86980 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
86982 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
86984 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
86986 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
86988 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
86990 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
86992 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
87067 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
87069 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
87071 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
87073 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87083 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87158 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
87160 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
87162 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
87164 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87174 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87203 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87205 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87240 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
87242 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
87244 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
87246 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
87248 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
87250 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
87252 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
87254 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
87256 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
87258 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
87260 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
87262 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
87264 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
87266 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
87268 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
87270 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
87272 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
87274 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
87276 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
87278 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
87280 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
87282 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
87284 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
87286 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
87288 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
87290 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
87292 …A_E5 (0x1<<26) // This bit masks, when set, the Interrupt bit:…
87294 …B_E5 (0x1<<27) // This bit masks, when set, the Interrupt bit:…
87296 …5 (0x1<<28) // This bit masks, when set, the Interrupt bit:…
87298 …5 (0x1<<29) // This bit masks, when set, the Interrupt bit:…
87300 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
87329 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87331 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87392 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87394 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87429 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
87431 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
87433 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
87435 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
87437 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
87439 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
87441 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
87444 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
87446 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
87448 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
87450 … (0x1<<3) // This bit masks, when set, the Parity bit: PS…
87452 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
87454 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
87462 …5_I_ECC_0_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
87464 …5_I_ECC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
87473 … 0x1600408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
87474 … 0x160040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
87475 … 0x1600420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
87478 … 0x1600440UL //Access:R DataWidth:0x10 // This read-only register provide…
87485 … 0x1600458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-powe…
87486 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
87487 … set the mode of the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on…
87488 …set the DRA RD block cut through mode in which write to a thread address section passive buffer ma…
87492 … 0x1600600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
87493 …set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface w…
87494 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
87497 … 0x16006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows th…
87500 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
87502 …set, an attempt to write to the passive buffer over the external passive interface will be enabled…
87503 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87504 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87506 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
87508 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
87511 …0x1600b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
87514 …600b0cUL //Access:W DataWidth:0x6 // Thread ID. Write thread ID will set ready indication fo…
87518 …1600b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
87519 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
87521 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
87525 … 0x1600d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
87527 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
87529 …L //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue pop-enable vector.
87530 … //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue wake-enable vector.
87534 … 0x1601008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DR…
87540 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
87545 …- No external stall is asserted when Storm's breakpoint is set (either by PRAM accessed ocpcode or…
87557 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
87560 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
87563 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
87564 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
87575 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
87580 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
87591 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
87593 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
87598 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
87601 …s. The counter is incremanted only for the event IDs which have Debug Monitor event indication set.
87614 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
87624 … 0x1608000UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the ex…
87630 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
87635 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87636 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87690 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
87701 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
87704 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
87706 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
87708 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
87710 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
87712 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
87715 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
87717 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
87719 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
87721 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87724 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
87726 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
87728 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
87730 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87751 …PEND_BLOCK_EN_E5 (0x1<<2) // When set, there may only be …
87753 … (0x1<<3) // When set, the Affintiy field of the thread is set…
87760 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
87788 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87836 … (0x1<<11) // Signals an unknown address in the fast-memory window.
87875 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
87877 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
87879 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
87881 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
87883 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
87885 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
87887 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
87889 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
87891 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
87893 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
87895 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
87897 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
87899 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
87901 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
87903 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
87905 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
87907 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
87909 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
87911 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
87913 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
87915 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
87917 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
87919 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
87921 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
87923 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
87925 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
87927 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
87929 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
87931 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
87933 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
87935 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
87937 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
87939 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
87941 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
87943 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
87945 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
87947 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
87949 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
87951 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
87953 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
87955 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
87957 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
87959 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
87961 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
87963 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
87965 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
87967 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
87969 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
87971 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
87973 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
87975 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
87977 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
87979 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
87981 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
87983 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
87985 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
87987 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
87989 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
87991 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
87998 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88026 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88074 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88117 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88145 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88193 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88304 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88306 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88308 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
88310 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88320 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88323 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
88325 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
88327 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
88329 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
88331 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
88333 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
88335 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
88337 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
88339 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
88341 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
88343 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
88345 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
88347 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
88349 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
88351 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
88353 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
88355 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
88357 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
88359 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
88361 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
88363 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
88365 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
88367 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
88369 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
88371 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
88373 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
88375 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
88377 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
88379 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
88381 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
88383 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
88385 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
88387 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
88389 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
88391 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
88393 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
88395 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
88397 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
88399 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
88401 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
88403 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
88405 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
88407 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
88409 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
88411 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
88486 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88488 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88490 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
88492 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88502 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88577 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88579 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88581 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
88583 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88593 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88622 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88624 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88659 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
88661 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
88663 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
88665 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
88667 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
88669 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
88671 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
88673 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
88675 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
88677 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
88679 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
88681 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
88683 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
88685 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
88687 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
88689 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
88691 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
88693 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
88695 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
88697 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
88699 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
88701 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
88703 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
88705 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
88707 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
88709 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
88711 …A_E5 (0x1<<26) // This bit masks, when set, the Interrupt bit:…
88713 …B_E5 (0x1<<27) // This bit masks, when set, the Interrupt bit:…
88715 …5 (0x1<<28) // This bit masks, when set, the Interrupt bit:…
88717 …5 (0x1<<29) // This bit masks, when set, the Interrupt bit:…
88719 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
88748 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88750 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88811 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88813 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88848 … (0x1<<0) // This bit masks, when set, the Parity bit: TS…
88850 … (0x1<<1) // This bit masks, when set, the Parity bit: TS…
88852 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
88854 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
88856 … (0x1<<3) // This bit masks, when set, the Parity bit: TS…
88858 … (0x1<<4) // This bit masks, when set, the Parity bit: TS…
88860 … (0x1<<1) // This bit masks, when set, the Parity bit: TS…
88863 … (0x1<<0) // This bit masks, when set, the Parity bit: TS…
88865 … (0x1<<1) // This bit masks, when set, the Parity bit: TS…
88867 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
88869 … (0x1<<3) // This bit masks, when set, the Parity bit: TS…
88871 … (0x1<<4) // This bit masks, when set, the Parity bit: TS…
88873 … (0x1<<5) // This bit masks, when set, the Parity bit: TS…
88881 …5_I_ECC_0_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
88883 …5_I_ECC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
88892 … 0x1700408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
88893 … 0x170040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
88894 … 0x1700420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
88897 … 0x1700440UL //Access:R DataWidth:0x10 // This read-only register provide…
88904 … 0x1700458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-powe…
88905 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
88906 … set the mode of the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on…
88907 …set the DRA RD block cut through mode in which write to a thread address section passive buffer ma…
88911 … 0x1700600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
88912 …set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface w…
88913 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
88916 … 0x17006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows th…
88919 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
88921 …set, an attempt to write to the passive buffer over the external passive interface will be enabled…
88922 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88923 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88925 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
88927 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
88930 …0x1700b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
88933 …700b0cUL //Access:W DataWidth:0x6 // Thread ID. Write thread ID will set ready indication fo…
88937 …1700b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
88938 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
88940 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
88944 … 0x1700d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
88946 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
88948 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
88949 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
88953 … 0x1701008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DR…
88959 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
88964 …- No external stall is asserted when Storm's breakpoint is set (either by PRAM accessed ocpcode or…
88976 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
88979 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
88982 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
88983 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
88994 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
88999 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
89010 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
89012 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
89017 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
89020 …s. The counter is incremanted only for the event IDs which have Debug Monitor event indication set.
89033 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
89043 … 0x1708000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
89049 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
89054 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89055 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89108 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
89119 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
89122 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
89124 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
89126 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
89128 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
89130 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
89133 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
89135 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
89137 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
89139 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89142 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
89144 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
89146 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
89148 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89169 …PEND_BLOCK_EN_E5 (0x1<<2) // When set, there may only be …
89171 … (0x1<<3) // When set, the Affintiy field of the thread is set…
89178 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89206 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89254 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89293 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
89295 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
89297 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
89299 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
89301 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
89303 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
89305 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
89307 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
89309 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
89311 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
89313 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
89315 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
89317 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
89319 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
89321 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
89323 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
89325 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
89327 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
89329 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
89331 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
89333 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
89335 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
89337 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
89339 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
89341 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
89343 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
89345 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
89347 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
89349 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
89351 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
89353 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
89355 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
89357 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
89359 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
89361 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
89363 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
89365 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
89367 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
89369 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
89371 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
89373 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
89375 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
89377 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
89379 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
89381 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
89383 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
89385 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
89387 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
89389 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
89391 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
89393 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
89395 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
89397 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
89399 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
89401 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
89403 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
89405 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
89407 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
89409 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
89416 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89444 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89492 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89535 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89563 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89611 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89722 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89724 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89726 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
89728 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89738 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
89741 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
89743 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
89745 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
89747 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
89749 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
89751 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
89753 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
89755 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
89757 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
89759 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
89761 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
89763 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
89765 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
89767 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
89769 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
89771 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
89773 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
89775 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
89777 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
89779 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
89781 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
89783 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
89785 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
89787 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
89789 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
89791 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
89793 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
89795 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
89797 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
89799 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
89801 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
89803 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
89805 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
89807 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
89809 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
89811 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
89813 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
89815 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
89817 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
89819 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
89821 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
89823 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
89825 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
89827 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
89829 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
89904 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89906 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89908 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
89910 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89920 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
89995 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89997 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89999 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
90001 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90011 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
90040 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90042 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90077 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
90079 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
90081 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
90083 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
90085 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
90087 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
90089 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
90091 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
90093 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
90095 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
90097 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
90099 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
90101 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
90103 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
90105 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
90107 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
90109 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
90111 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
90113 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
90115 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
90117 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
90119 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
90121 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
90123 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
90125 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
90127 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
90129 …A_E5 (0x1<<26) // This bit masks, when set, the Interrupt bit:…
90131 …B_E5 (0x1<<27) // This bit masks, when set, the Interrupt bit:…
90133 …5 (0x1<<28) // This bit masks, when set, the Interrupt bit:…
90135 …5 (0x1<<29) // This bit masks, when set, the Interrupt bit:…
90137 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
90166 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90168 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90229 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90231 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90266 … (0x1<<0) // This bit masks, when set, the Parity bit: MS…
90268 … (0x1<<1) // This bit masks, when set, the Parity bit: MS…
90270 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
90272 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
90274 … (0x1<<3) // This bit masks, when set, the Parity bit: MS…
90276 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
90278 … (0x1<<1) // This bit masks, when set, the Parity bit: MS…
90281 … (0x1<<0) // This bit masks, when set, the Parity bit: MS…
90283 … (0x1<<1) // This bit masks, when set, the Parity bit: MS…
90285 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
90287 … (0x1<<3) // This bit masks, when set, the Parity bit: MS…
90289 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
90291 … (0x1<<5) // This bit masks, when set, the Parity bit: MS…
90293 … (0x1<<6) // This bit masks, when set, the Parity bit: MS…
90295 … (0x1<<7) // This bit masks, when set, the Parity bit: MS…
90297 … (0x1<<5) // This bit masks, when set, the Parity bit: MS…
90299 … (0x1<<8) // This bit masks, when set, the Parity bit: MS…
90301 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
90303 … (0x1<<9) // This bit masks, when set, the Parity bit: MS…
90305 … (0x1<<10) // This bit masks, when set, the Parity bit: MS…
90307 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
90309 … (0x1<<11) // This bit masks, when set, the Parity bit: MS…
90311 … (0x1<<12) // This bit masks, when set, the Parity bit: MS…
90313 … (0x1<<3) // This bit masks, when set, the Parity bit: MS…
90315 … (0x1<<13) // This bit masks, when set, the Parity bit: MS…
90317 … (0x1<<14) // This bit masks, when set, the Parity bit: MS…
90319 … (0x1<<15) // This bit masks, when set, the Parity bit: MS…
90339 …5_I_ECC_0_PRTY (0x1<<0) // Set parity only for mem…
90341 …5_I_ECC_1_PRTY (0x1<<1) // Set parity only for mem…
90343 …5_I_ECC_2_PRTY_E5 (0x1<<2) // Set parity only for mem…
90345 …5_I_ECC_3_PRTY_E5 (0x1<<3) // Set parity only for mem…
90347 …5_I_ECC_4_PRTY_E5 (0x1<<4) // Set parity only for mem…
90349 …5_I_ECC_5_PRTY_E5 (0x1<<5) // Set parity only for mem…
90351 …5_I_ECC_6_PRTY_E5 (0x1<<6) // Set parity only for mem…
90353 …5_I_ECC_7_PRTY_E5 (0x1<<7) // Set parity only for mem…
90374 … 0x1800408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
90375 … 0x180040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
90376 … 0x1800420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
90379 … 0x1800440UL //Access:R DataWidth:0x10 // This read-only register provide…
90386 … 0x1800458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-powe…
90387 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
90388 … set the mode of the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on…
90389 …set the DRA RD block cut through mode in which write to a thread address section passive buffer ma…
90393 … 0x1800600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
90394 …set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface w…
90395 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
90398 … 0x18006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows th…
90401 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
90403 …set, an attempt to write to the passive buffer over the external passive interface will be enabled…
90404 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90405 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90407 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
90409 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
90412 …0x1800b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
90415 …800b0cUL //Access:W DataWidth:0x6 // Thread ID. Write thread ID will set ready indication fo…
90419 …1800b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
90420 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
90422 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
90426 … 0x1800d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
90428 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
90430 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
90431 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
90435 … 0x1801008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DR…
90441 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
90446 …- No external stall is asserted when Storm's breakpoint is set (either by PRAM accessed ocpcode or…
90458 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
90461 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
90464 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
90465 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
90476 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
90481 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
90492 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
90494 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
90499 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
90502 …s. The counter is incremanted only for the event IDs which have Debug Monitor event indication set.
90515 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
90525 … 0x1808000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
90531 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
90536 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90537 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90591 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
90602 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
90605 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
90607 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
90609 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
90611 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
90613 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
90616 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
90618 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
90620 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
90622 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90625 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
90627 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
90629 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
90631 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90652 …PEND_BLOCK_EN_E5 (0x1<<2) // When set, there may only be …
90654 … (0x1<<3) // When set, the Affintiy field of the thread is set…
90661 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90689 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90737 … (0x1<<11) // Signals an unknown address in the fast-memory window.
90776 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
90778 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
90780 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
90782 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
90784 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
90786 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
90788 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
90790 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
90792 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
90794 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
90796 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
90798 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
90800 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
90802 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
90804 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
90806 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
90808 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
90810 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
90812 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
90814 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
90816 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
90818 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
90820 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
90822 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
90824 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
90826 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
90828 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
90830 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
90832 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
90834 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
90836 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
90838 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
90840 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
90842 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
90844 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
90846 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
90848 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
90850 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
90852 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
90854 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
90856 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
90858 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
90860 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
90862 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
90864 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
90866 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
90868 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
90870 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
90872 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
90874 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
90876 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
90878 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
90880 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
90882 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
90884 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
90886 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
90888 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
90890 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
90892 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
90899 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90927 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90975 … (0x1<<11) // Signals an unknown address in the fast-memory window.
91018 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
91046 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91094 … (0x1<<11) // Signals an unknown address in the fast-memory window.
91205 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91207 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91209 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
91211 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91221 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91224 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
91226 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
91228 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
91230 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
91232 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
91234 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
91236 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
91238 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
91240 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
91242 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
91244 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
91246 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
91248 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
91250 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
91252 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
91254 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
91256 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
91258 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
91260 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
91262 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
91264 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
91266 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
91268 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
91270 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
91272 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
91274 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
91276 … (0x1<<26) // This bit masks, when set, the Interrupt bit:…
91278 … (0x1<<27) // This bit masks, when set, the Interrupt bit:…
91280 … (0x1<<28) // This bit masks, when set, the Interrupt bit:…
91282 … (0x1<<29) // This bit masks, when set, the Interrupt bit:…
91284 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
91286 … (0x1<<31) // This bit masks, when set, the Interrupt bit:…
91288 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
91290 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
91292 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
91294 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
91296 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
91298 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
91300 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
91302 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
91304 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
91306 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
91308 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
91310 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
91312 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
91387 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91389 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91391 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
91393 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91403 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91478 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91480 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91482 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
91484 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91494 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91523 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91525 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91560 … (0x1<<0) // This bit masks, when set, the Interrupt bit:…
91562 … (0x1<<1) // This bit masks, when set, the Interrupt bit:…
91564 … (0x1<<2) // This bit masks, when set, the Interrupt bit:…
91566 … (0x1<<3) // This bit masks, when set, the Interrupt bit:…
91568 … (0x1<<4) // This bit masks, when set, the Interrupt bit:…
91570 … (0x1<<5) // This bit masks, when set, the Interrupt bit:…
91572 … (0x1<<6) // This bit masks, when set, the Interrupt bit:…
91574 … (0x1<<7) // This bit masks, when set, the Interrupt bit:…
91576 … (0x1<<8) // This bit masks, when set, the Interrupt bit:…
91578 … (0x1<<9) // This bit masks, when set, the Interrupt bit:…
91580 … (0x1<<10) // This bit masks, when set, the Interrupt bit:…
91582 … (0x1<<11) // This bit masks, when set, the Interrupt bit:…
91584 … (0x1<<12) // This bit masks, when set, the Interrupt bit:…
91586 … (0x1<<13) // This bit masks, when set, the Interrupt bit:…
91588 … (0x1<<14) // This bit masks, when set, the Interrupt bit:…
91590 … (0x1<<15) // This bit masks, when set, the Interrupt bit:…
91592 … (0x1<<16) // This bit masks, when set, the Interrupt bit:…
91594 … (0x1<<17) // This bit masks, when set, the Interrupt bit:…
91596 … (0x1<<18) // This bit masks, when set, the Interrupt bit:…
91598 … (0x1<<19) // This bit masks, when set, the Interrupt bit:…
91600 … (0x1<<20) // This bit masks, when set, the Interrupt bit:…
91602 … (0x1<<21) // This bit masks, when set, the Interrupt bit:…
91604 … (0x1<<22) // This bit masks, when set, the Interrupt bit:…
91606 … (0x1<<23) // This bit masks, when set, the Interrupt bit:…
91608 … (0x1<<24) // This bit masks, when set, the Interrupt bit:…
91610 … (0x1<<25) // This bit masks, when set, the Interrupt bit:…
91612 …A_E5 (0x1<<26) // This bit masks, when set, the Interrupt bit:…
91614 …B_E5 (0x1<<27) // This bit masks, when set, the Interrupt bit:…
91616 …5 (0x1<<28) // This bit masks, when set, the Interrupt bit:…
91618 …5 (0x1<<29) // This bit masks, when set, the Interrupt bit:…
91620 … (0x1<<30) // This bit masks, when set, the Interrupt bit:…
91649 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91651 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91712 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91714 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91749 … (0x1<<0) // This bit masks, when set, the Parity bit: US…
91751 … (0x1<<1) // This bit masks, when set, the Parity bit: US…
91753 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
91755 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
91757 … (0x1<<3) // This bit masks, when set, the Parity bit: US…
91759 … (0x1<<4) // This bit masks, when set, the Parity bit: US…
91761 … (0x1<<1) // This bit masks, when set, the Parity bit: US…
91764 … (0x1<<0) // This bit masks, when set, the Parity bit: US…
91766 … (0x1<<1) // This bit masks, when set, the Parity bit: US…
91768 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
91770 … (0x1<<3) // This bit masks, when set, the Parity bit: US…
91772 … (0x1<<4) // This bit masks, when set, the Parity bit: US…
91774 … (0x1<<5) // This bit masks, when set, the Parity bit: US…
91782 …5_I_ECC_0_PRTY_BB_K2 (0x1<<0) // Set parity only for mem…
91784 …5_I_ECC_1_PRTY_BB_K2 (0x1<<1) // Set parity only for mem…
91793 … 0x1900408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
91794 … 0x190040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
91795 … 0x1900420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
91798 … 0x1900440UL //Access:R DataWidth:0x10 // This read-only register provide…
91805 … 0x1900458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-powe…
91806 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
91807 … set the mode of the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on…
91808 …set the DRA RD block cut through mode in which write to a thread address section passive buffer ma…
91812 … 0x1900600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
91813 …set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface w…
91814 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
91817 … 0x19006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows th…
91820 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
91822 …set, an attempt to write to the passive buffer over the external passive interface will be enabled…
91823 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91824 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91826 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
91828 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
91831 …0x1900b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
91834 …900b0cUL //Access:W DataWidth:0x6 // Thread ID. Write thread ID will set ready indication fo…
91838 …1900b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
91839 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
91841 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
91845 … 0x1900d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
91847 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
91849 …L //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue pop-enable vector.
91850 … //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue wake-enable vector.
91854 … 0x1901008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DR…
91860 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
91865 …- No external stall is asserted when Storm's breakpoint is set (either by PRAM accessed ocpcode or…
91877 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
91880 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
91883 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
91884 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
91895 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
91900 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
91911 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
91913 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
91918 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
91921 …s. The counter is incremanted only for the event IDs which have Debug Monitor event indication set.
91934 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
91944 … 0x1908000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the ex…
91950 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
91955 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
91956 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…