Lines Matching +full:rmii +full:- +full:refclk +full:- +full:in
2 * Copyright (c) 2017-2018 Cavium, Inc.
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11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
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24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
54 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
83 …t be loaded, EEPROM load will stop, and the FastLinkEnable bit will be set in the PCIEEP_PORT_CTL …
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
95 … the value read by host. The default value reflects the value of DEVICE_ID in version.v or strap p…
102 …will be generated setting PEM()_DBG_INFO[BMD_E]. Transactions are dropped in the client. Nonposte…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
147 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
185 …2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
189 …20 // This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)
206 …abled to do so either through this bit or though PCI express specific bits in DCR Path = i_cfg_fun…
210 …s (de-asserted) regardless of any internal chip logic. Setting this bit has no effect on the INT_S…
226 …rity error bit is set by a requester if the parity error enable bit is set in its command register…
236 …unction sends an ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register…
250 …n Revision ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
252 …ing Interface. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
254 …t Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
256 …t Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
261 …-bit Class Code register identifies the generic function of the device. All of the legal values ar…
281 …multifunction. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
290 …-bit Header Type register identifies both the layout of bytes 10h through 3Fh of the Configuration…
292 … (0xff<<24) // The 8-bit BIST register is used to initiate and report the results o…
297 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
304 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
306 … (0x3<<1) // BAR0 32-bit or 64-bit. Note: The access attributes of this field a…
308 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
310 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
312 …-bit BAR_1 register programs the base address for the memory space mapped by the card onto the PCI…
315 … indicate that BAR_1 may be programmed to map this adapter to anywhere in the 64-bit address space…
317 … (0x1<<3) // This bit indicates that the area mapped by BAR_1 may be pre-fetched or cached by …
319 …-bit address space that will be card will respond in. These bits may be combined with the bits in …
323 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
325 … (0x3<<1) // BAR1 32-bit or 64-bit. Note: The access attributes of this field a…
327 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
329 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
331 … 0x000014UL //Access:RW DataWidth:0x20 // The 32-bit BAR_2 register pr…
335 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
342 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
344 … (0x3<<1) // BAR2 32-bit or 64-bit. Note: The access attributes of this field a…
346 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
348 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
350 …-bit BAR_3 register programs the 2nd base address for the memory space mapped by the card onto the…
353 … indicate that BAR_2 may be programmed to map this adapter to anywhere in the 64-bit address space…
355 … (0x1<<3) // This bit indicates that the area mapped by BAR_2 may be pre-fetched or cached by …
357 …-bit address space that will be card will respond in. These bits may be combined with the bits in …
361 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
363 … (0x3<<1) // BAR3 32-bit or 64-bit. Note: The access attributes of this field a…
365 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
367 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
369 … 0x00001cUL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register pr…
373 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
380 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
382 … (0x3<<1) // BAR4 32-bit or 64-bit. Note: The access attributes of this field a…
384 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
386 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
388 …-bit BAR_5 register programs the 3rd base address for the memory space mapped by the card onto the…
391 … indicate that BAR_3 may be programmed to map this adapter to anywhere in the 64-bit address space…
393 … (0x1<<3) // This bit indicates that the area mapped by BAR_3 may be pre-fetched or cached by …
395 …-bit address space that will be card will respond in. These bits may be combined with the bits in …
399 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
401 … (0x3<<1) // BAR5 32-bit or 64-bit. Note: The access attributes of this field a…
403 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
405 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
407 … 0x000024UL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register pr…
412 … (0xffff<<0) // Subsystem vendor ID. Assigned by PCI-SIG, writable through…
414 … (0xffff<<16) // Subsystem ID. Assigned by PCI-SIG, writable through…
417 …tem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
419 …tem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
422 …VENDOR_ID_BB (0xffff<<0) // The 16-bit Subsystem Vendor …
424 …D_BB (0xffff<<16) // The 16-bit Subsystem ID regi…
432 …<<0) // Expansion ROM Enable. Note: The access attributes of this field are as follows: - Dbi: R
434 …Expansion ROM Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W
436 … 0x000030UL //Access:RW DataWidth:0x20 // The 32-bit Expansion ROM BAR…
449 …<0) // Pointer to first item in the PCI Capability Structure. Note: The access attributes of thi…
452 …-bit Capabilities Pointer register specifies an offset in the PCI address space of a linked list o…
466 …egister Field. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
469 …_INT_LINE_BB (0xff<<0) // The 8-bit Interrupt Line re…
471 …_INT_PIN_BB (0xff<<8) // The 8-bit Interrupt Pin reg…
494 …t the device (or function) is not capable of generating PME messages while in that power state: _…
499 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
501 … Spec Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
505 … Return to D0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
507 …alization Bit. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
509 … Requirements. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
511 …State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
513 …State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
515 …in this register. The reset value PME_SUPPORT_n && {sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT…
537 …owever, the read-back value is the actual power state, not the write value. Note: The access attr…
539 …No soft Reset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
556 … (0xff<<0) // The 8-bit Power Management …
558 …ed an offset in the PCI address space of the next capability. The read-only value of this register…
568 …a specific initialization (DSI) sequence following a transition to the D0 un-initialized state. Th…
572 …he D1 power management state. This bit is controlled by the D1_SUPPORT bit in the PCI register spa…
574 …he D2 power management state. This bit is controlled by the D2_SUPPORT bit in the PCI register spa…
576 …ssage from the D0 power state. This bit is controlled by the PME_IN_D0 bit in the PCI register spa…
578 …ssage from the D1 power state. This bit is controlled by the PME_IN_D1 bit in the PCI register spa…
580 …ssage from the D2 power state. This bit is controlled by the PME_IN_D2 bit in the PCI register spa…
582 …rom the D3hot power state. This bit is controlled by the PME_IN_D3_HOT bit in the PCI register spa…
599 …e bits indicate the scaling factor to be used when interpreting the values in the PM data register…
601 …put will be asserted low. This bit is cleared by writing a 1 in this bit position. At power-up, th…
610 … Next Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
614 …ssage Capable. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
618 … (0x1<<23) // MSI 64-bit Address Capable. Note: The access attributes of this fiel…
623 … (0xff<<0) // The 8-bit VPD Capability ID…
625 …ed an offset in the PCI address space of the next capability. The read-only value of this register…
629 …// This value is the 32-bit word address of the VPD value being accessed in the vpd_data register.…
631 …bit is used to control passing of data between the vpd_data register and Non-Volatile memory. To r…
634 …essage Lower Address Field. Note: The access attributes of this field are as follows: - Dbi: R/W
638 …-bit MSI Message, this field contains Data. For 64-bit it contains lower 16 bits of the Upper Addr…
640 …is reserved. For 64-bit it contains upper 16 bits of the Upper Address. Note: The access attribut…
643 … (0xff<<0) // The 8-bit MSI Capability ID…
645 …ed an offset in the PCI address space of the next capability. The read-only value of this register…
649 … This value comes from the Path = i_cfg_func.i_cfg_private MULTI_MSG_CAP bit in the register space.
655 …supports per vector masking. This value comes from the MSI_PV_MASK_CAP bit in the register space. …
658 …-bit MSI Message, this field contains Data. For 32-bit, it contains the lower Mask Bits if PVM is …
660 …-bit MSI Message, this field contains Data. For 32-bit, it contains the upper Mask Bits if PVM is …
665 …e address of the MSI message that are generated. This register is readable in the pci register spa…
668 …e address of the MSI message that are generated. This register is readable in the pci register spa…
670 …fied to indicate different interrupt conditions. This register is readable in the pci register spa…
676 … (0xff<<8) // Next capability pointer. Points to the MSI-X Capabilities by def…
689 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
695 …emented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
697 …essage Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
712 … (0x1<<15) // Role-based error reporting…
718 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core.
721 …ize Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
723 …ons Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
725 …eld Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
727 …table latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
729 …table latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
731 … (0x1<<15) // Role-based Error Reporting Implemented. Note: The access attributes of th…
737 …dpoints only). Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
764 …in this register regardless of whether or not error reporting is enabled in the device control reg…
766 …in this register regardless of whether or not error reporting is enabled in the device control reg…
768 …in this register regardless of whether or not error reporting is enabled in the device control reg…
770 …in this register regardless of whether or not error reporting is enabled in the device control reg…
779 …S_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting…
787 …icated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilit…
789 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
791 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
795 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
803 …_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
824 …e clock(s) via the clock request (PCI_CLKREQ_L) mechanism when the Link is in the L1 and L2/L3 rea…
837 … In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: Th…
839 … In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: Th…
841 …ment) Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
843 …in the core when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DE…
845 …in the core when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DE…
847 …er Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
855 …ty Compliance. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
857 …/ Port Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
872 …ock power management. Hardwired to 0 if clock power management is disabled in the link capabilitie…
882 …t link speed. The encoded value specifies a bit location in the supported link speeds vector (in t…
899 …d Completion Boundary (RCB). Note: The access attributes of this field are as follows: - Dbi: R/W
901 …In a DSP that supports crosslink, the core gates the write value with the CROSS_LINK_EN field in P…
903 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
909 …e PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG. Note: The access attributes of this fi…
911 …e Autonomous Width Disable. Note: The access attributes of this field are as follows: - Dbi: R/W
913 …e PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this fi…
915 …e PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this fi…
923 … (0x1<<27) // LTSSM is in Configuration or Recovery State. Note: The access attributes of th…
925 …Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
929 …e PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this fi…
931 …e PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this fi…
942 … (0x1<<7) // 32-bit AtomicOp supporte…
944 … (0x1<<8) // 64-bit AtomicOp supporte…
946 … (0x1<<9) // 128-bit AtomicOp supporte…
948 … (0x1<<10) // No RO-enabled PR-PR passing. (Thi…
956 …SUPP_E5 (0x1<<16) // 10-bit tag completer sup…
958 …SUPP_E5 (0x1<<17) // 10-bit tag requestor sup…
964 … (0x1<<21) // End-end TLP prefix suppor…
966 … (0x3<<22) // Max end-end TLP prefixes. 0x…
983 …R2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
1010 …EN_E5 (0x1<<12) // 10-bit tag requester ena…
1014 … (0x1<<15) // End-end TLP prefix blocki…
1017 …/ Completion Timeout Value. Note: The access attributes of this field are as follows: - Dbi: R/W
1045 …PEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIE…
1049 …DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1052 …in its training sequences: 0x1 = 2.5 Gb/s target link speed. 0x2 = 5 Gb/s target link speed. 0x…
1054 … enter compliance mode at the speed indicated in the target link speed field by setting this bit t…
1056 …he application must disable hardware from changing the link speed for device-specific reasons othe…
1060 …-deemphasized voltage level at the transmitter pins: 0x0 = 800-1200 mV for full swing 400-600 mV …
1064 …en set to one, the LTSSM is required to send SKP ordered sets periodically in between the (modifie…
1066 …eemphasis level in Polling.Compliance state if the entry occurred due to the TX compliance receive…
1068 …T/s speed, this bit reflects the level of deemphasis. 0 = -6 dB. 1 = -3.5 dB. The value in thi…
1091 …INK_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the cont…
1095 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1097 …EMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
1101 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1103 … transmission. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1105 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
1107 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
1126 …ed an offset in the PCI address space of the next capability. The read-only value of this register…
1128 …f<<16) // System sw reads this field to determine the MSI-X table size N, which is encoded as N-1 …
1134 … (0x1<<31) // If 1, and the MSI enable bit in the MSI message cont…
1137 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X table into memory s…
1142 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X PBA into memory spa…
1157 …-X vector is used for the interrupt message generated in association with any of the status bits o…
1160 …MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
1164 … (0x7ff<<16) // MSI-X table size encoded as (table size - 1)…
1166 …ctors associated with the function are masked, regardless of their respective per-vector mask bits.
1168 … (0x1<<31) // MSI-X enable. If MSI-X is enabled,…
1170 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
1171 …TRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
1173 … (0xff<<8) // MSI-X Next Capability Pointer. Note: The access attributes of this f…
1175 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
1177 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
1179 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
1182 … programmable from the register space and default value is based on define in version.v file. Path…
1202 … (0x1<<28) // FLR capability is advertized when flr_supported bit in private device_capab…
1205 … (0x7<<0) // MSI-X table BAR indicator register (BIR). Indicates which BAR is u…
1207 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
1209 … 0x0000b4UL //Access:RW DataWidth:0x20 // MSI-X Table Offset and BI…
1210 … (0x7<<0) // MSI-X Table Bar Indicator Register Field. Note: The access attributes of …
1212 … (0x1fffffff<<3) // MSI-X Table Offset. Note: The access attributes of this field …
1217 …L_ERR_REPORT_EN_BB (0x1<<1) // Non-Fatal Error Reporting…
1225 …unctions. For ARI devices max payload size is determined solely by setting in Function 0. Path= i_…
1233 … this bit is set to 1, PCIE initiates a read request with the No Snoop bit in the attribute field …
1237 …iate Function Level reset. This bit is writeable only if flr_supported bit in private device_capab…
1241 …TAL_ERR_DET_BB (0x1<<17) // Non-Fatal Error Detected.…
1249 … (0x1<<21) // This is bit is read back a 1, whenever a non-posted request initia…
1252 … (0x7<<0) // MSI-X PBA BAR indicator register (BIR). Indicates which BAR is us…
1254 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
1256 … 0x0000b8UL //Access:RW DataWidth:0x20 // MSI-X PBA Offset and BIR …
1257 … (0x7<<0) // MSI-X PBA BIR. Note: The access attributes of this field are…
1259 … (0x1fffffff<<3) // MSI-X PBA Offset. Note: The access attributes of this field a…
1264 …always 0 and is not programmable. Default value is based on numLanes field in version.v Path= i_cf…
1268 …Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Depending on whether device is in common clock mode or…
1270 …Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Depending on whether device is in common clock mode or…
1272 …ts are programmable through register. The feature itself has to be enabled in version.v Path= i_cf…
1285 …unction. For ARI devices, ASPM setting is determined solely by the setting in Function 0. Path= i_…
1297 …red sets in the L0s state followed by a single SKP ordered set prior to entering the L0 state, and…
1317 … (0x1<<28) // Slot Clock configuration. This bit is read-only by host, but rea…
1355 …xt Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1357 …0x7fff<<16) // VPD Address. Note: The access attributes of this field are as follows: - Dbi: R/W
1359 … (0x1<<31) // VPD Flag. Note: The access attributes of this field are as follows: - Dbi: R/W
1368 …gh register space. This field will read 1, when bit 5 of ext_cap_ena field in private register spa…
1374 …ed using WAKE# signaling only. Value is programmable through private register space in Device_cap2.
1379 …n timeout value. The spec specifies a range, the device uses the max value in the range. Path= i_c…
1393 …d is writeable, when bit 5 of ext_cap_ena field in private register space is set. This bit is RW o…
1397 …d is writeable, when bit 5 of ext_cap_ena field in private register space is set. This bit is RW o…
1404 …nce with PCIE spec 1.1. To enable this register, reset comply_pcie_1_1 bit in the register space t…
1411 …6) // When link is operating at Gen2 rates, this bit selects the level of de-emphasis. Path= i_cfg…
1425 … (0x1<<17) // Equalization Complete - when set, this indic…
1427 … (0x1<<18) // Equalization Phase 1 Successful - when set, this indic…
1429 … (0x1<<19) // Equalization Phase 2 Successful - when set, this indic…
1431 … (0x1<<20) // Equalization Phase 3 Successful - when set, this indic…
1451 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1453 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1455 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1518 …ore details, see the "Data Integrity (Wire, Datapath, and RAM Protection)" section in the Databook.
1597 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1603 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1605 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1686 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1692 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1694 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1751 …ATAL_ERR_STATUS_K2 (0x1<<13) // Advisory Non-Fatal Error Status.
1802 …ERR_MASK_K2 (0x1<<13) // Advisory Non-Fatal Error Mask. N…
1858 … (0x1f<<0) // First Error Pointer - These bits correspond to the bit position i…
1952 …ice Serial Number bits [31:0]. This register will contain the data written in the Device Serial Nu…
1963 …ce Serial Number bits [63:32]. This register will contain the data written in the Device Serial Nu…
1972 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1974 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1976 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1982 …nded VC Count. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1990 …on Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1999 … an offset in the PCI address space of the next capability. The read-only value of this register i…
2009 … (0xff<<0) // This value selects the value visible in the pb_dr. Path = i_…
2021 …// Reject Snoop Transactions. Note: The access attributes of this field are as follows: - Dbi: R
2023 … (0x3f<<16) // Maximum Time Slots-1 supported. Note: The access attributes of this field ar…
2027 …esent in this register is selected from one of the POWER BUDGET DATA ACCESS Registers from offset …
2077 …Access:R DataWidth:0x20 // The read-back value of this register is controlled by the EXT_CAP_…
2082 …s value continues the PCI capability chain. It's value specified an offset in the PCI address spac…
2096 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2098 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2100 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2124 …Access:RW DataWidth:0x20 // The read-back value of this register is controlled by the EXT_CAP_…
2141 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2143 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2145 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2176 …-only value of this register is controlled by setting bit 0 of the EXT_CAP_ENA for EP, or setting …
2181 …s value continues the PCI capability chain. It's value specified an offset in the PCI address spac…
2201 … Allocated PB. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2203 …-only value of this register is controlled by setting bit 0 of the EXT_CAP_ENA for EP, or setting …
2204 … (0xffff<<0) // VSEC ID. This field is a vendor-defined ID number tha…
2206 … (0xf<<16) // VSEC Rev. This field is a vendor-defined version numbe…
2208 …ber of bytes in the entire VSEC structure, including the PCI Express Enhanced Capability header, t…
2228 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2230 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2232 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2234 …The capability can be enabled by default by defining VendorCapOn or PCIE_VF_BAR_STRIDE in version.v
2328 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2330 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2332 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2357 …0) // Perform Equalization. Note: The access attributes of this field are as follows: - Dbi: R/W
2359 …n Request Interrupt Enable. Note: The access attributes of this field are as follows: - Dbi: R/W
2382 …tter Preset 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2384 …Preset Hint 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2386 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2388 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2390 …tter Preset 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2392 …Preset Hint 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2394 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2396 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2405 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2406 …itter Preset2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2408 … Preset Hint2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2410 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2412 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2414 …itter Preset3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2416 … Preset Hint3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2418 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2420 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2423 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2424 …itter Preset4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2426 … Preset Hint4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2428 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2430 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2432 …itter Preset5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2434 … Preset Hint5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2436 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2438 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2441 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2442 …itter Preset6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2444 … Preset Hint6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2446 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2448 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2450 …itter Preset7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2452 … Preset Hint7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2454 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2456 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2458 …-only value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP, By default,…
2463 …s value continues the PCI capability chain. It's value specified an offset in the PCI address spac…
2477 …g with Max snoop latency scale field, this register specifies the maximum no-snoop latency that a …
2483 …ith Max No snoop latency scale field, this register specifies the maximum no-snoop latency that a …
2490 … 0x0001b8UL //Access:RW DataWidth:0x20 // SR-IOV Capability Header…
2491 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2493 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2495 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2497 …ad-only value of this register is controlled by setting bit 6 of the EXT_CAP_ENA for EP, The capab…
2507 … 0x0001bcUL //Access:RW DataWidth:0x20 // SR-IOV Capability Regist…
2510 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2521 …he function number of the next higher numbered function in device. Value reflects programming in A…
2528 … 0x0001c0UL //Access:RW DataWidth:0x20 // SR-IOV Control and Statu…
2537 …access attributes of this field are as follows: - Dbi: R/W but read-value is not always same as w…
2539 …ad-only value of this register is controlled by setting bit 7 of the EXT_CAP_ENA for EP, The capab…
2547 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2549 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2554 … (0x1<<1) // This field is only present in PF0. This bet when s…
2575 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2576 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: STATUS_CONTROL_…
2585 … (0x1<<2) // This bit has no effect in IP. However spec has…
2589 … set, the device is permitted to locate VF in Func Number 8 to 255. This field is RW only in PF0 a…
2613 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register" det…
2615 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register". de…
2618 … (0xffff<<0) // The Value in this register is based on programming in…
2620 … (0xffff<<16) // The Value in this register is based on programming in…
2640 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2645 … (0xff<<16) // The Value in this register is based on programming in…
2668 … (0xffff<<0) // The value in this register is based on programming in…
2683 … (0xffff<<16) // The value in this register is based on programming in…
2692 …in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO an…
2693 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2695 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2697 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2699 …x0001dcUL //Access:R DataWidth:0x20 // This value in this register is based on programming in…
2717 …in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO an…
2718 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2720 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2722 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2742 …in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO an…
2743 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2745 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2747 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2749 …-bit VF_BAR0 register programs the base address for the memory space mapped by the VFs belonging t…
2752 …ndicate that VF_BAR0 may be programmed to map this adapter to anywhere in the 64-bit address space…
2754 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR0 may be pre-fetched or cached by …
2758 …-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR…
2777 …in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO an…
2778 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2780 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2782 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2784 … 0x0001e8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR1 register …
2802 …in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO an…
2803 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2805 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2807 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2809 …-bit VF_BAR2 register programs the base address for the memory space mapped by the VFs belonging t…
2812 …ndicate that VF_BAR2 may be programmed to map this adapter to anywhere in the 64-bit address space…
2814 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR2 may be pre-fetched or cached by …
2818 …-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR…
2837 …in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO an…
2838 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2840 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2842 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2844 … 0x0001f0UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR3 register …
2867 …-bit VF_BAR4 register programs the base address for the memory space mapped by the VFs belonging t…
2870 …ndicate that VF_BAR4 may be programmed to map this adapter to anywhere in the 64-bit address space…
2872 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR4 may be pre-fetched or cached by …
2876 …-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR…
2896 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2898 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2900 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2902 … 0x0001f8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR5 register …
2920 …taWidth:0x20 // TPH Requestor Capability Register. SRIOV Note: All VFs in a single PF have the…
2923 …ode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2925 …ode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2927 …ter Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2929 …ocation Bit 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2931 …ocation Bit 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2933 …ST Table Size. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2953 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
2957 …-only value of this register is controlled by setting bit 0 of the EXT3_CAP_ENA for EP, The capabi…
2962 …s value continues the PCI capability chain. It's value specified an offset in the PCI address spac…
2982 … 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
2984 … 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
3007 … (0x1<<0) // When Set, Function is permitted to participate in PTM mechanism
3049 …ad-only value of this register is controlled by setting bit 9 of the EXT_CAP_ENA for EP, The capab…
3054 …s value continues the PCI capability chain. It's value specified an offset in the PCI address spac…
3074 …tting backpressure on the upstream request. the value in this field is controlled by programming i…
3076 …d Address is always aligned to 4K boundary. the value in this field is controlled by programming i…
3080 …indicates to the Function, the minimum of 4K byte blocks that is indicated in a Translation Comple…
3127 …-only value of this register is controlled by setting bit 8 of the EXT_CAP_ENA for EP, The capabil…
3132 …s value continues the PCI capability chain. It's value specified an offset in the PCI address spac…
3139 …5 (0x1<<2) // VF 10-bit tag requester sup…
3146 …l operate with Bar sized to 1M. Value reflected here is from corresponding bit in private register.
3148 …l operate with Bar sized to 2M. Value reflected here is from corresponding bit in private register.
3150 …l operate with Bar sized to 4M. Value reflected here is from corresponding bit in private register.
3152 …l operate with Bar sized to 8M. Value reflected here is from corresponding bit in private register.
3154 … operate with Bar sized to 16M. Value reflected here is from corresponding bit in private register.
3156 … operate with Bar sized to 32M. Value reflected here is from corresponding bit in private register.
3158 … operate with Bar sized to 64M. Value reflected here is from corresponding bit in private register.
3160 …operate with Bar sized to 128M. Value reflected here is from corresponding bit in private register.
3162 …operate with Bar sized to 256M. Value reflected here is from corresponding bit in private register.
3164 …operate with Bar sized to 512M. Value reflected here is from corresponding bit in private register.
3166 …l operate with Bar sized to 1G. Value reflected here is from corresponding bit in private register.
3179 …erarchy. 0 = All PFs have non-ARI capable hierarchy. 1 = All PFs have ARI capable hierarchy. T…
3181 …5 (0x1<<5) // VF 10-bit Tag Requester Ena…
3190 … (0x7<<5) // Indicates number of resizeable BARs in capability.
3192 …programmed, value is immediately reflected in the size of the resource, as encoded in the number o…
3197 … (0xffff<<16) // Total VFs. Read-only copy of PCIEEP_S…
3204 …-only value of this register is controlled by setting bit 0 of the EXT2_CAP_ENA for EP, By default…
3209 …s value continues the PCI capability chain. It's value specified an offset in the PCI address spac…
3212 …-ARI capable hierarchies. The PCIEEP_SRIOV_CTL[ACH] determines which one is being used for SR-IOV…
3214 …-ARI: 0x1. There are two VF stride registers; one for each ARI capable and non-ARI capable…
3219 …orts Interrupt Vector mode of operation. Value in this field can be programmed through TPH_CAP reg…
3227 …es if and where the ST table is located. Value in this field can be programmed through TPH_CAP reg…
3231 …d as N-1. So a returned value of 16, indicates a table size of 17. The value in this field can be …
3245 …-only value of this register is controlled by setting bit 2 of the EXT2_CAP_ENA for EP, By default…
3246 …) // Vendor Specific Extended Capability ID. Value is from corresponding field in private register.
3248 …<<16) // PM L1 substates Capability version. Value is from corresponding field in private register.
3250 …s value continues the PCI capability chain. It's value specified an offset in the PCI address spac…
3255 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3274 … (0xff<<8) // Time in us that device advertizes that it requires to…
3276 …6) // Along with the value field, this field advertizes the tpower_on time in us, that the link pa…
3280 …9) // Along with the scale field, this field advertizes the tpower_on time in us, that the link pa…
3307 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3314 …field along with value sets the min amount of time that the Port must wait in L1.2 exit after samp…
3318 …field along with scale sets the min amount of time that the Port must wait in L1.2 exit after samp…
3324 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3356 … (0x7ff<<16) // ST table size (limited by MSI-X table size).
3369 …d Capacity ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3371 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3373 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3375 … 0x000288UL //Access:RW DataWidth:0x20 // LTR Max Snoop and No-Snoop Latency Registe…
3380 …T_K2 (0x3ff<<16) // Max No-Snoop Latency Value.
3382 …LAT_SCALE_K2 (0x7<<26) // Max No-Snoop Latency Scale.
3384 … 0x00028cUL //Access:RW DataWidth:0x20 // Vendor-Specific Extended Cap…
3385 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3387 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3389 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3391 … 0x000290UL //Access:R DataWidth:0x20 // Vendor-Specific Header.
3398 …- Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register det…
3399 …in this register. You can clear the value of a specific Event Counter by writing the 'per clear' c…
3401 …in this register. By default, all event counters are disabled. You can enable/disable a specific E…
3403 …alue of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT…
3405 …in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVEN…
3407 …in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by…
3409 …- EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_CO…
3410 …-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time sp…
3411 … (0x1<<0) // Timer Start. - 0: Start/Restart - 1: Stop Th…
3413 …-based Duration Select. Selects the duration of time-based analysis. When "manual control" is sele…
3415 …-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_…
3417 …-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in …
3418 …in this register. The specific injection controls for each type of error are defined in the follow…
3433 …- LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link …
3434 …have been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE…
3436 …- 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b:…
3438 …- ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 409…
3439 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE …
3441 …nce number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - …
3443 …-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. …
3445 …- If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the trans…
3446 … being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABL…
3448 … inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block …
3450 …- If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeo…
3451 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE …
3453 …- Mask K symbol. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set)…
3455 …in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP He…
3456 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE …
3458 …-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Po…
3462 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is repr…
3464 …- For Duplicate TLP, the core initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TL…
3465 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE …
3467 …be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Null…
3469 …re with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When…
3470 …re with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When…
3471 …re with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When…
3472 …re with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When…
3473 …re with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When…
3481 …re with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When…
3513 …re with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When…
3519 …re with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When…
3527 …in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are spe…
3533 … (0x3ff<<16) // Max no-snoop latency value.
3535 … (0x7<<26) // Max no-snoop latency scale.
3537 …in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are spe…
3545 …in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are spe…
3546 …-only value of this register is controlled by setting bit 1 of the EXT2_CAP_ENA for EP, The capabi…
3551 …s value continues the PCI capability chain. It's value specified an offset in the PCI address spac…
3554 …PCIPM_SUP_E5 (0x1<<0) // PCI-PM L12 supported.
3556 …PCIPM_SUP_E5 (0x1<<1) // PCI-PM L11 supported.
3564 … (0xff<<8) // Port common mode restore time. Time (in us) required for thi…
3568 … with [PWRON_SCALE] sets the time (in us) that this Port requires the port on the opposite side of…
3570 …in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are spe…
3577 …1_2_PCIPM_EN_E5 (0x1<<0) // PCI-PM L12 enable.
3579 …1_1_PCIPM_EN_E5 (0x1<<1) // PCI-PM L11 enable.
3587 …ield indicates the LTR threshold use to determine if entry into L1 results in L1.1 (if enabled) or…
3589 …s. 0x2 = 1024 ns. 0x3 = 32,768 ns. 0x4 = 1,048,575 ns. 0x5 = 33,554,432 ns. 0x6-7 = Reserved.
3591 …in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are spe…
3598 …g with the [T_PWR_ON_SCA], sets the minimum amount of time (in us) that the Port must wait in L.1.…
3600 …in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are spe…
3625 …in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are spe…
3656 …in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are spe…
3681 …in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx …
3682 …are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE …
3684 …ror Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EI…
3686 …e TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Pref…
3736 … in conjunction with [EV_CNTR_DATA_SEL] indexes the event counter data returned in the PCIEEP_RAS_…
3738 … (0xfff<<16) // Event counter data select. This field in conjunction with [EV…
3778 …-based duration select. Selects the duration of time-based analysis. 0x0 = Manual control. Ana…
3780 …ff<<24) // Time-based report select. Selects what type of data is measured for the selected durati…
3800 …20 // Silicon Debug Control 1. For more details, see the RAS DES section in the Core Operations …
3801 …uring LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. -…
3805 …-reset exit. The core selects the greater value between this register and the value defined by the…
3807 …m receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - …
3809 …20 // Silicon Debug Control 2. For more details, see the RAS DES section in the Core Operations …
3810 …ld and Release LTSSM. For as long as this register is '1', the core stays in the current LTSSM. …
3812 …s bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This request d…
3816 …ect Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State,…
3818 …irect Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance S…
3820 …) // Detect Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Activ…
3824 …-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in…
3825 …er for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 …
3839 …icon Debug Status(Layer1 LTSSM). For more details, see the RAS DES section in the Core Operations …
3840 …- 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When …
3846 …sal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. …
3848 …in the PCI Express base specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_spe…
3850 …0 // Silicon Debug Status(PM). For more details, see the RAS DES section in the Core Operations …
3851 …- 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDL…
3853 …- 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 08h: L1 - 09h: L1_BLOCK_…
3855 … Re-send flag. When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host soft…
3857 … (0xff<<16) // Latched N_FTS. Indicates the value of N_FTS in the received TS Orde…
3874 …// Silicon Debug Status(Layer2). For more details, see the RAS DES section in the Core Operations …
3879 … (0x3<<24) // DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 1…
3881 … (0x1<<26) // FC_INIT1. Indicates the core is in FC_INIT1(VC0) state.…
3883 … (0x1<<27) // FC_INIT2. Indicates the core is in FC_INIT2(VC0) state.…
3888 …in inserted. TX path: 0x0 = New TLP's LCRC error injection. 0x1 = 16bCRC error injection of ACK…
3890 …in this viewport register return the data for the VC and TLP Type selected by the following fields…
3891 …in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-se…
3893 …in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fiel…
3895 …in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select f…
3897 …in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-se…
3899 …TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value …
3901 …YPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value …
3908 …-assigned sequence numbers. This value is represented by two's complement. 0x0FFF = +4095. 0x0…
3910 …// Silicon Debug Status(Layer3). For more details, see the RAS DES section in the Core Operations …
3911 …- 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: T…
3923 …ng - Mask K symbol. 0x0 = Reserved. 0x1 = COM/PAD(TS1 Order Set). 0x2 = COM/PAD(TS2 Order Set)…
3928 …-FC type. Selects the credit type. 0x0 = Posted TLP header credit value control. 0x1 = Non-Pos…
3932 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. The value is rep…
3934 …in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[…
3935 …in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data ret…
3937 …in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data ret…
3939 …e of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ M…
3943 … Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2).…
3948 …ACK DLLP as NAK DLLP. 0x1 = Generates nullified TLP (Original TLP will be stored in retry buffer).
3950 … EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details, see the …
3951 …x3f<<0) // Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in…
3953 …ansmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3),…
3955 …f<<12) // Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in…
3957 …ver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3),…
3959 … // Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) …
3961 …fficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CUR…
3968 … EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details, see the …
3969 …f<<0) // Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in…
3971 …nsmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2),…
3973 …<12) // Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in…
3975 …ficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CU…
3979 …in the SD_EQ_CONTROL1_REG register. The following fields are available when Equalization finished …
3982 …nformation. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x…
3984 … violation is detected in the values provided by PHY using direction change method during EQ Maste…
3986 … violation is detected in the values provided by PHY using direction change method during EQ Maste…
3988 … violation is detected in the values provided by PHY using direction change method during EQ Maste…
3990 …ives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2).…
3993 …in the SD_EQ_CONTROL1_REG register. Each field is available when Equalization finished successfull…
3994 …_K2 (0x3f<<0) // EQ Local Pre-Cursor. Indicates Lo…
3998 …K2 (0x3f<<12) // EQ Local Post-Cursor. Indicates Lo…
4005 …in the SD_EQ_CONTROL1_REG register. Each field is available when Equalization finished successfull…
4006 …_K2 (0x3f<<0) // EQ Remote Pre-Cursor. Indicates Re…
4010 …K2 (0x3f<<12) // EQ Remote Post-Cursor. Indicates Re…
4023 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4025 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4027 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4038 …ck (core_clk), you must not write this register while operations are in progress in the AXI master…
4039 …for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. …
4055 …mpletion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. …
4068 …-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COU…
4071 …) // Enable correctable errors counters. - 1: counters increment when the core detects a correcta…
4073 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4078 …-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNT…
4081 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4083 … (0xff<<24) // Counter selection. Returns the value set in the CORR_COUNTER_SEL…
4086 …-bit ECC and parity) counter selection and control. This is a viewport control register. Setting t…
4089 … Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correct…
4091 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4100 …ors into. 0x0 = TLP header. 0x1 = TLP prefix 1st 4-DWORDs. 0x2 = TLP prefix 2nd 4-DWORDs. 0x3…
4102 …-bit ECC and parity) counter data. This viewport register returns the counter data selected by the…
4105 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4107 … (0xff<<24) // Counter selection. Returns the value set in the UNCORR_COUNTER_S…
4109 …he following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection mod…
4112 … (0x3<<4) // Error injection type: - 0: none - 1: 1-bit - 2: 2-bit
4114 … (0xff<<8) // Error injection count. - 0: errors are inserted in every TLP until you clear ERR…
4118 …rors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations …
4119 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4123 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4127 …rors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations …
4128 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4132 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4136 …- Rx TLPs that are forwarded to your application are not guaranteed to be correct; you must discar…
4146 …-reset exit. The core selects the greater value between this register and the value defined by the…
4148 …ing EIOS to, RXELECIDLE assertion at the PHY 0x0 = 40ns. 0x1 = 160ns. 0x2 = 320ns. 0x3 - 640ns.
4150 …SDP error mode. For more details, see the RAS Data Protection (DP) section in the Core Operations …
4154 …x1<<0) // Hold and release LTSSM. For as long as this is set, the core stays in the current LTSSM.
4156 … (0x1<<1) // Recovery request. When this bit is set in L0 or L0s, the LTSSM…
4160 …ect Recovery.Idle to configuration. When this bit is set and the LTSSM is in recovery idle state,…
4162 …irect Polling.Compliance to detect. When this bit is set and the LTSSM is in polling compliance s…
4164 … (0x1<<10) // Direct loopback slave to exit. When set and the LTSSM is in loopback slave activ…
4168 …ress where a corrected error (1-bit ECC) has been detected. For more details, see the RAS Data Pro…
4169 … (0x7ffffff<<0) // RAM Address where a corrected error (1-bit ECC) has been det…
4171 … (0xf<<28) // RAM index where a corrected error (1-bit ECC) has been det…
4173 …s where an uncorrected error (2-bit ECC) has been detected. For more details, see the RAS Data Pro…
4174 … (0x7ffffff<<0) // RAM Address where an uncorrected error (2-bit ECC) has been det…
4176 … (0xf<<28) // RAM index where an uncorrected error (2-bit ECC) has been det…
4179 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4181 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4183 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4186 … silicon debug status register of Layer1-PerLane. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. 0x7 …
4201 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4203 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4205 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4207 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4210 …-STP/SDP/IDL token was received and it was not in TLP/DLLP reception. 0x02 = When current token w…
4218 …in the PCI Express base specification. 0x0 = directed_speed change. 0x1 = changed_speed_recovery…
4221 …0x1<<0) // PTM Enable. When set, this function is permitted to participate in the PTM mechanism. F…
4223 …s Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT
4225 …s Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT
4228 … 0x17 = L0S_BLOCK_TLP. 0x18 = WAIT_LAST_PMDLLP. 0x19 = WAIT_DSTATE_UPDATE. 0x20-0x1F = Reserved.
4230 …S_L23RDY_WAIT4ALIVE. 0x0F = S_L23RDY_WAIT4IDLE. 0x10 = S_WAIT_LAST_PMDLLP. 0x10-0x1F = Reserved.
4232 …_Status bit. If host software does not clear PME_Status bit for 100ms (+50%/-5%), the DUT resends …
4236 … (0xff<<16) // Latched N_FTS. Indicates the value of N_FTS in the received TS orde…
4238 …surement Requester Capability Header (VSEC). For more details, see the PTM section in the Databook.
4239 …or more details, see the PTM section in the Databook. Note: The access attributes of this field a…
4241 …or more details, see the PTM section in the Databook. Note: The access attributes of this field a…
4243 …or more details, see the PTM section in the Databook. Note: The access attributes of this field a…
4252 … (0x1<<26) // Indicates the core is in FC_INIT1(VC0) state.
4254 … (0x1<<27) // Indicates the core is in FC_INIT2(VC0) state.
4256 …easurement Requester Vendor Specific Header. For more details, see the PTM section in the Databook.
4257 …or more details, see the PTM section in the Databook. Note: The access attributes of this field a…
4259 …or more details, see the PTM section in the Databook. Note: The access attributes of this field a…
4261 …or more details, see the PTM section in the Databook. Note: The access attributes of this field a…
4264 …select (VC). This field in conjunction with the [CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], …
4266 …ct (credit type). This field in conjunction with the [CREDIT_SEL_VC], [CREDIT_SEL_TLP_TYPE], and …
4268 …in conjunction with the [CREDIT_SEL_VC], [CREDIT_SEL_CREDIT_TYPE], and [CREDIT_SEL_HD] viewport-se…
4270 …HeaderData). This field in conjunction with the [CREDIT_SEL_VC], [CREDIT_SEL_CREDIT_TYPE], and [C…
4272 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = …
4274 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = …
4276 … Requester Vendor Specific Control Register. For more details, see the PTM section in the Databook.
4277 …te Enabled - When enabled PTM Requester will automatically atempt to update it's context every 10m…
4279 …e - When set the PTM Requester will attempt a PTM Dialogue to update it's context; This bit is sel…
4281 …- Debug mode for PTM Timers. The 100us timer output will go high at 30us and the 10ms timer output…
4283 …- Determines the period between each auto update PTM Dialogue in miliseconds. Update period is the…
4286 …in message TLP. 0x09 = Unexpected CRS status in completion TLP. 0x0A = Byte enable. 0x0B = Memo…
4290 …M Requester Vendor Specific Status Register. For more details, see the PTM section in the Databook.
4291 …0) // PTM Requester Context Valid - Indicate that the Timing Context is valid. For more details, s…
4293 …ter Manual Update Allowed - Indicates whether or not a Manual Update can be signalled. For more de…
4295 …dth:0x20 // PTM Requester Local Clock LSB For more details, see the PTM section in the Databook.
4296 …dth:0x20 // PTM Requester Local Clock MSB. For more details, see the PTM section in the Databook.
4298 …in conjunction with [EQ_RATE_SEL] determines the per-lane silicon debug EQ status data returned by…
4300 …<4) // EQ status rate select. Setting this field in conjunction with [EQ_LANE_SEL] determines the…
4302 …in Recovery.EQ2/3. When this field is set, the value of the EQ2/3 timeout is extended. EQ maste…
4304 …. 0x2 = 2 us. 0x3 = 4 us. This field is used for EQ master (DSP in EQ Phase3/USP in EQ Phase2).
4308 … Indicates figure of merit target criteria value of EQ master (DSP in EQ Phase3/USP in EQ Phase2).…
4310 …th:0x20 // PTM Requester T1 Timestamp LSB. For more details, see the PTM section in the Databook.
4312 …itter precursor. Indicates the coefficient value of EQ slave (DSP in EQ Phase2/USP in EQ Phase3),…
4314 …nsmitter cursor. Indicates the coefficient value of EQ slave (DSP in EQ Phase2/USP in EQ Phase3),…
4316 …tter postcursor. Indicates the coefficient value of EQ slave (DSP in EQ Phase2/USP in EQ Phase3),…
4318 …er preset hint. Indicates the RxPresetHint value of EQ slave (DSP in EQ Phase2/USP in EQ Phase3),…
4320 … // Force local transmitter preset. Indicates initial preset value of USP in EQ slave (EQ Phase2)…
4328 …th:0x20 // PTM Requester T1 Timestamp MSB. For more details, see the PTM section in the Databook.
4330 …nsmitter pre-cursor as selected by PCIEEP_RAS_SD_EQ_CTL1[EQ_LANE_SEL]. Indicates the coefficient …
4332 …1[EQ_LANE_SEL]. Indicates the coefficient value of EQ master (DSP in EQ Phase3/USP in EQ Phase2),…
4334 …1[EQ_LANE_SEL]. Indicates the coefficient value of EQ master (DSP in EQ Phase3/USP in EQ Phase2),…
4338 … // PTM Requester T1 Previous Timestamp LSB. For more details, see the PTM section in the Databook.
4339 … // PTM Requester T1 Previous Timestamp MSB. For more details, see the PTM section in the Databook.
4345 …in the values provided by PHY using direction change method during EQ master phase (DSP in EQ Phas…
4347 …in the values provided by PHY using direction change method during EQ master phase (DSP in EQ Phas…
4349 …in the values provided by PHY using direction change method during EQ master phase (DSP in EQ Phas…
4351 …ves two consecutive TS1 OS w/Reject=1b during EQ master phase (DSP in EQ Phase3/USP in EQ Phase2).…
4353 …th:0x20 // PTM Requester T4 Timestamp LSB. For more details, see the PTM section in the Databook.
4365 …th:0x20 // PTM Requester T4 Timestamp MSB. For more details, see the PTM section in the Databook.
4377 … // PTM Requester T4 Previous Timestamp LSB. For more details, see the PTM section in the Databook.
4378 … // PTM Requester T4 Previous Timestamp MSB. For more details, see the PTM section in the Databook.
4379 …dth:0x20 // PTM Requester Master Time LSB. For more details, see the PTM section in the Databook.
4381 … (0xf<<0) // These bits control the size of the BAR1 area advertised in the bar_1 register o…
4383 … (0x1<<4) // This bit enables the advertisement of bar_1 as a 32-bit address. The valu…
4385 … (0x1<<5) // This bit will force the PCI bus to re-try all cycles to the…
4387 …-try all cycles to the configuration space until it is cleared. This is used to block the host fro…
4391 …in the Exp_ROM_BAR register of the PCI configuration space. When this value is non-zero, the Expan…
4393 … (0x1<<16) // This bit when set is reflected in bit 3 of bar_1 and indicates that the BAR is …
4397 …dth:0x20 // PTM Requester Master Time MSB. For more details, see the PTM section in the Databook.
4399 …t by HARD Reset such that it can be used to detect initial power up if a non-zero value is written…
4403 … (0x1<<16) // This bits exists in VF only Setting this…
4407 … PME message to be send This simulates the PME event. The PME control bits in the configuration sp…
4409 … (0x1<<25) // This bit indicates the current state of the PME_STATUS bit in configuration space.…
4411 … (0x1<<26) // This is the current state of the PME_ENABLE bit in configuration space.…
4413 …PM_STATE value in the Power Management configuration space. Reads of this register return the last…
4417 … in the current configuration. The value also controls the value of the Power Management PME_SUPPO…
4421 …h:0x20 // PTM Requester Propagation Delay. For more details, see the PTM section in the Databook.
4423 …m the pm_data register when the DATA_SEL value in the PM_CSR register is 0. This is the power cons…
4425 …m the pm_data register when the DATA_SEL value in the PM_CSR register is 1. This is the power cons…
4427 …m the pm_data register when the DATA_SEL value in the PM_CSR register is 2. This is the power cons…
4429 …m the pm_data register when the DATA_SEL value in the PM_CSR register is 3. This is the power cons…
4431 …20 // PTM Requester Master Time at T1 LSB. For more details, see the PTM section in the Databook.
4433 … the pm_data register when the DATA_SEL value in the PM_CSR register is 4. This is the power dissi…
4435 … the pm_data register when the DATA_SEL value in the PM_CSR register is 5. This is the power dissi…
4437 … the pm_data register when the DATA_SEL value in the PM_CSR register is 6. This is the power dissi…
4439 … the pm_data register when the DATA_SEL value in the PM_CSR register is 7. This is the power dissi…
4448 …20 // PTM Requester Master Time at T1 MSB. For more details, see the PTM section in the Databook.
4450 … (0xf<<0) // These bits control the size of the BAR1 area advertised in the bar_1 register o…
4452 … (0xf<<4) // These bits control the size of the BAR2 area advertised in the bar_3 register o…
4454 … (0xf<<8) // These bits control the size of the BAR3 area advertised in the bar_5 register o…
4456 … (0x7<<12) // These bits control the size of the BAR1 area advertised in the bar_1 register o…
4460 … (0x7<<16) // These bits control the size of the BAR2 area advertised in the bar_3 register o…
4462 … (0x7<<19) // These bits control the size of the BAR3 area advertised in the bar_5 register o…
4471 …ataWidth:0x20 // PTM Requester TX Latency. For more details, see the PTM section in the Databook.
4472 …<0) // PTM Requester TX Latency - Requester Transmit path latency (12 bit wide). For more details,…
4503 …ataWidth:0x20 // PTM Requester RX Latency. For more details, see the PTM section in the Databook.
4504 …<0) // PTM Requester RX Latency - Requester Receive path latency (12 bit wide). For more details, …
4511 …). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved.
4516 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4518 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4520 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4525 …ot supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved.
4527 … (0xff<<24) // Counter selection. Returns the value set in PCIEEP_RASDP_CE_CTL[…
4530 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4532 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4534 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4536 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4538 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4540 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4542 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4544 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4546 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4548 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4550 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4552 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4554 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4556 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4558 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4560 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4562 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4564 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4566 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4568 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4571 …al Product Data interface. This bit is set when the vpd_flag_addr register in configuation space i…
4578 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4587 …) // BAR Size. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4592 …his value is the byte address of the VPD value being requested by the host in the vpd_flag_addr re…
4594 …in the vpd_data register to be passed to the NVM interface. If the value is clear, then the host h…
4599 …). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved.
4601 … (0xff<<24) // Counter selection. Returns the value set in PCIEEP_RASDP_UCE_CTL…
4603 …in the configuration space. When INTF_REQ is '1' and the WR bit is clear, this word should be writ…
4607 … (0x3<<4) // Error injection type. 0x0 = None. 0x1 = 1-bit. 0x2 = 2-bit. 0x3 = Re…
4609 … Error injection count. 0x0 = errors are injected in every TLP until [ERR_INJ_EN] is cleared. 0x…
4614 …nly reset by HARD Reset. The default value reflects the value of DEVICE_ID in version.v defined by…
4619 …ot supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved.
4623 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4628 …<0) // This value controls the read value of the subsystem_vendor_id value in the configuration sp…
4630 …m_id value in the configuration space. This value is sticky and only reset by HARD Reset. The defa…
4633 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4637 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4642 …-bit Class Code register identifies the generic function of the device. All of the legal values ar…
4644 …fault value is provided by user_revision_id strap pins. This field also exists in VF register space
4652 …<<0) // This value controls the read value of the next capability pointers in the PCIE configurati…
4656 … (0x3<<6) // This value is read as the DATA_SCALE value in the Power Management CSR register in t…
4658 … (0x1<<8) // This value controls the per vector masking capability in the MSI control field
4660 … (0x7<<9) // This value reports the MSI value that is programmed in the PCI configuratio…
4662 …(0x7<<12) // This value controls the read value of the MSI_CTRL_MCAP value in the PCI configuratio…
4664 … (0x1<<15) // This bit indicates the programming of the MSI Enable bit in PCI configuration sp…
4672 … device supports the D1 power management state. It is reflected in the D1_SUPPORT bit in the confi…
4674 … device supports the D2 power management state. It is reflected in the D2_SUPPORT bit in the confi…
4676 …transmiting PME message from the D0 power state. It is reflected in the PME_IN_D0 bit in the confi…
4678 …transmiting PME message from the D1 power state. It is reflected in the PME_IN_D1 bit in the confi…
4680 …transmiting PME message from the D2 power state. It is reflected in the PME_IN_D2 bit in the confi…
4682 …miting PME message from the D3hot power state. It is reflected in the PME_IN_D3_HOT bit in the con…
4684 …ies with which revision of PCI PM spec. This value is reflected in corresponding field in PM capab…
4686 …al reset when transitioning from D3 to D0. the value is reflected in corresponding field in PM CSR.
4703 … (0xff<<16) // This register controls the read value of the bist register in the configuration sp…
4713 … (0xffff<<0) // This register reflects the MSI data register value in the configuration sp…
4722 …// This register reflects the upper half of the MSI address register value in the configuration sp…
4724 … (0x7fffff<<0) // Only bit 0 is currently defined - remote scaled flow c…
4730 …/ This register reflects the lower half of the MSI address bit[31:2] value in the configuration sp…
4748 … (0x1<<0) // PTM enable. When set, this function is permitted to participate in the PTM mechanism.
4754 … DataWidth:0x20 // This register reflects the MSI mask register value in the configuration sp…
4762 …he function has a pending associated message. This register gets reflected in the configuration sp…
4771 …data register when the DATA_SEL value in the PM_CSR register is 8. This is the power dissipated by…
4778 …ate it's context; This bit is self clearing. For more details, see the PTM section in the Databook.
4780 …er operation will otherwise remain the same. For more details, see the PTM section in the Databook.
4782 …in miliseconds. Update period is the register value +1 milisecond. For the Switch product this va…
4818 …orted resource sizes. PEM advertises the maximum allowable BAR size (512 GB - 0xF_FFFF) when the f…
4821 …10:0] register in the configuration space. A value of "00000000011" indicates a table size of 4 Lo…
4835 …ed at 10h in configuration space is used to map the function's MSI-X table into memory space. Valu…
4837 …dress registers to point to the base of the MSI-X table. Value is controlled by PCIE_MSIX_TBL_OFF …
4847 …ted at 10h in configuration space is used to map the function's MSI-X PBA into memory space. Value…
4849 …ddress registers to point to the base of the MSI-X PBA Value is controlled by PCIE_MSIX_PBA_OFF fi…
4859 …-zero values indicate some software-defined post-firmware loaded state information or failure code…
4862 … (0x1f<<0) // This controls the value in configuration space
4866 … (0x1<<6) // This bit when set, sets the ASPM optionality bit in the Link cap registe…
4869 … (0x7<<0) // This controls the value of this field in the DEVICE_CAP register in the co…
4873 … (0x1<<5) // This controls the value of this field in the DEVICE_CAP register in the co…
4875 … (0x7<<6) // This controls the value of this field in the configuration sp…
4877 … (0x7<<9) // This controls the value in the configuration sp…
4881 … (0x1<<15) // This controls value in configuration space
4885 … (0x1<<28) // This controls value in configuration space …
4890 …in FLR state. Func can be brought out of FLR state either by writing 1 to this register (at least …
4897 … (0xf<<0) // This controls the value of the same field in the link_capability register in conf…
4899 … (0x1f<<4) // This controls the value of the same field in the link_capability register in conf…
4901 … (0x1<<9) // This controls the value of the same field in the link_capability register in conf…
4903 … (0x3<<10) // This controls the value of the same field in the link_capability register in conf…
4905 … (0x7<<12) // This controls the value of the same field in the link_capability register in conf…
4907 … (0x7<<15) // This controls the value of the same field in the link_capability register in conf…
4909 … (0x7<<18) // This controls the value of the same field in the link_capability register in conf…
4911 … (0x7<<21) // This controls the value of the same field in the link_capability register in conf…
4913 … (0xff<<24) // This controls the value of the same field in the link_capability register in conf…
4916 … (0xf<<0) // These bits control the size of the BAR2 area advertised in the bar_3 register o…
4918 … (0x1<<4) // This bit enables the advertisement of bar_3 as a 32-bit address. The valu…
4920 … (0x1<<5) // This bit when set is reflected in bit 3 of bar_3 and indicates that the BAR is …
4925 …) // Completion Timeout Ranges Supported. Controls value in same field in the config space 0xF- Ra…
4927 … (0x1<<4) // Completion Timeout Disable Supported, Controls value in same field in the config sp…
4931 … (0x1<<10) // This bit is valid only if IDO_Enabled is defined in version.v. When this…
4935 …ported using Messages) This bit is valid only if PCIE_OBFF_SUPP is defined in version.v. When this…
4944 …20 of link_capability register. For EP, this field will not has any effect in link_capability regi…
4949 … (0xf<<0) // These bits control the size of the BAR3 area advertised in the bar_5 register o…
4951 … (0x1<<4) // This bit enables the advertisement of bar_5 as a 32-bit address. The valu…
4953 … (0x1<<5) // This bit when set is reflected in bit 3 of bar_5 and indicates that the BAR is …
4964 …in bits 31:30 of RC_EXT_CAP_ENA field . AER in bits 31:30 is always enabled, so that extended capa…
4970 …fff<<0) // This register controls the value of CAP_ID in the DEV_SER_NUM_CAP_ID (0x13C) register i…
4972 …f<<16) // This register controls the value of CAP_VER in the DEV_SER_NUM_CAP_ID (0x13C) register i…
4974 … budget, virtual channel LTR capability will be present only if LTR_ENABLED is defined in version.v
4976 …in bits 25:20. AER in bits 25:20 should always be enabled, so that extended capability structure w…
4980 …ss:RW DataWidth:0x20 // This register controls the value in the LOWER_SER_NUM (0x104) in the c…
4981 …ss:RW DataWidth:0x20 // This register controls the value in the UPPER_SER_NUM (0x108) in the c…
4983 … (0x1<<0) // This value controls the corresponding bit in the ADV_ERR_CAP _CON…
4985 … (0x1<<1) // This value controls the corresponding bit in the ADV_ERR_CAP _CON…
5028 …in bits 25:20 and additional extended capability is in 29:26 in dev_ser_num_cap_id register. AER i…
5030 …in bits 25:20 and additional extended capability is in 29:26 in dev_ser_num_cap_id register. The n…
5052 … (0xff<<8) // Time in us that device advertizes that it requires to…
5054 …6) // Along with the value field, this field advertizes the tpower_on time in us, that the link pa…
5058 …9) // Along with the scale field, this field advertizes the tpower_on time in us, that the link pa…
5068 … (0x1<<0) // This bit controls the system alloc bit in the PWR_BDGT_CAP (0x15c) in the co…
5077 … (0xfff<<20) // VSEC Length: Indicates the number of bytes in the entire VSEC stru…
5084 …in RC mode. If this bit is set, then memory transactions received in Rx direction are compared aga…
5088 … (0xffff<<16) // USER_BAR_LOWER_ADDRESS: Lower 16 bits of BAR for user in RC mode. This is not…
5090 …ataWidth:0x20 // USER_BAR_HIGHER_ADDRESS: Higher 32 bits of BAR for user in RC mode. This is not…
5096 …in RC mode. If this bit is set, then memory transactions received in Rx direction are compared aga…
5100 … (0xffff<<16) // USER_BAR_LOWER_ADDRESS: Lower 16 bits of BAR for user in RC mode. This is not…
5102 …ataWidth:0x20 // USER_BAR_HIGHER_ADDRESS: Higher 32 bits of BAR for user in RC mode. This is not…
5103 …s:RW DataWidth:0x20 // This register is visible only if PCIE_EP_MC_SUPP is defined in version.v
5104 …f<<0) // Default value of this field is 64KB. This field will be reflected in the MC Capability re…
5106 …ess:RW DataWidth:0x20 // This register is visible only if PCIE_PTM_SUPP is defined in version.v
5107 … (0x1<<0) // This field will be reflected in the PTM capability r…
5109 … (0x1<<1) // This field will be reflected in the PTM capability r…
5112 …terrupt vector mode of op. Value programmed here is reflected in the corresponding bits in the TPH…
5114 …pecific mode of operation. Value programmed here is reflected in the corresponding bits in the TPH…
5116 … ST table is located in MSI-X Table structure. All other values should not be programmed. The valu…
5118 … (0x7ff<<4) // This field will be reflected in the ST Table Size fi…
5123 …rate with Bar sized to 1M. Value programmed here is reflected in the corresponding bits in the RBA…
5125 …rate with Bar sized to 2M. Value programmed here is reflected in the corresponding bits in the RBA…
5127 …rate with Bar sized to 4M. Value programmed here is reflected in the corresponding bits in the RBA…
5129 …rate with Bar sized to 8M. Value programmed here is reflected in the corresponding bits in the RBA…
5131 …ate with Bar sized to 16M. Value programmed here is reflected in the corresponding bits in the RBA…
5133 …ate with Bar sized to 32M. Value programmed here is reflected in the corresponding bits in the RBA…
5135 …ate with Bar sized to 64M. Value programmed here is reflected in the corresponding bits in the RBA…
5137 …te with Bar sized to 128M. Value programmed here is reflected in the corresponding bits in the RBA…
5139 …te with Bar sized to 256M. Value programmed here is reflected in the corresponding bits in the RBA…
5141 …te with Bar sized to 512M. Value programmed here is reflected in the corresponding bits in the RBA…
5143 …rate with Bar sized to 1G. Value programmed here is reflected in the corresponding bits in the RBA…
5148 …in the corresponding bits in the ari_control_register. This field should be programmed to indicate…
5151 … (0xffff<<0) // Value programmed here is reflected in the corresponding bits in the SRI…
5153 … (0xffff<<16) // Value programmed here is reflected in the corresponding bits in the SRI…
5156 …in the corresponding bits in the SRIOV_VFOffset cfg register. This field defines the Routing ID of…
5158 …in the corresponding bits in the SRIOV_VFOffset Cfg register. This field indicates device ID for a…
5161 … field influences the size of the VFs BAR register, advertized in the VF BAR0 register in the PCIE…
5163 … (0x1<<4) // This bit enables the advertisement of VF BAR0 as a 64-bit address. The valu…
5165 … (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR0 and indicates that the BAR is…
5169 … field influences the size of the VFs BAR register, advertized in the VF BAR2 register in the PCIE…
5171 … (0x1<<12) // This bit enables the advertisement of VF BAR2 as a 64-bit address. The valu…
5173 … (0x1<<13) // This bit when set is reflected in bit 3 of VF BAR2 and indicates that the BAR is…
5177 … (0xf<<16) // Value programmed here is reflected in the corresponding bits in the SRI…
5181 … (0xff<<24) // Value programmed here is reflected in the corresponding bits in the SRI…
5183 …s:RW DataWidth:0x20 // Value programmed here is reflected in the corresponding bits in the SRI…
5185 …<<0) // This value controls the read value of the next capability pointers in the VF configuration…
5189 … (0x3f<<8) // Enable for the VF extended capability structures in the VF config space.…
5192 …in the VF Cfg space. This indicates which one of the function's Base address registers located in …
5194 …in the VF cfg space. This is used as an offset from the address contained by one of the functions …
5197 …in the VF Cfg space. This indicates which one of the function's Base address registers located in …
5199 …ress contained by one of the functions Base address registers to point to the base of the MSI-X PBA
5202 …in VF only and does not exist in PF. This register controls the read value of the MSIX_CONTROL[10:…
5207 … field influences the size of the VFs BAR register, advertized in the VF BAR4 register in the PCIE…
5209 … (0x1<<4) // This bit enables the advertisement of VF BAR4 as a 64-bit address. The valu…
5211 … (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR4 and indicates that the BAR is…
5213 …to reside in a contiguous space starting at VFNUM =0. This register identifies the first VFNUM loc…
5214 … (0x1f<<0) // First VF_NUM for PF is encoded in this register. The n…
5224 … (0x1f<<0) // This register controls the corresponding value in the ATS capability r…
5226 … (0x1<<5) // This register controls the corresponding value in the ATS capability r…
5231 …terrupt vector mode of op. Value programmed here is reflected in the corresponding bits in the TPH…
5233 …pecific mode of operation. Value programmed here is reflected in the corresponding bits in the TPH…
5235 …in MSI-X Table structure. All other values should not be programmed. The value programmed here is …
5237 …7ff<<4) // This field will be reflected in the ST Table Size field of the PCIE defined TPH capabil…
5241 … (0x1<<31) // This field when set enables TPH capability in all the VF's.
5249 …-7, 3-8, and 3-9 of the PCIe 3.0 specification. The limit must reflect the round trip latency from…
5251 …-4, 3-5, and 3-6 of the PCIe 3.0 specification. If there is a change in the payload size or link s…
5267 … (0xff<<0) // Link Number. Not used for endpoint. Not used for M-PCIe. Note: This reg…
5269 …t (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1…
5271 …- Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the core to t…
5273 …it (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1…
5275 …-state register to go low-power. This register is intended for applications that do not let the co…
5288 …in L0s. Allow core to enter ASPM L1 even when link partner did not go to L0s (receive is not in L0…
5290 … 0x00070cUL //Access:RW DataWidth:0x20 // Ack Frequency and L0-L1 ASPM Control Regis…
5291 …- 0: Indicates that this Ack frequency control feature is turned off. The core schedules a low-pri…
5293 …-sets that a component can request is 255. The core does not support a value of zero; a value of z…
5295 …-sets that a component can request is 255. This field is only writable (sticky) when all of the fo…
5297 … - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us…
5299 … Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 …
5301 …- 1: Core enters ASPM L1 after a period in which it has been idle. - 0: Core enters ASPM L1 only …
5304 …tes a one to this bit, the PCI Express bus transmits the message contained in the other message re…
5308 … (0x1<<2) // Loopback enable. Initiate loopback mode as a master. On a 0->1 transition, the PC…
5322 …ield does not indicate the number of lanes in use by the PCIe. This field sets the maximum number …
5335 …he core transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Readi…
5339 …-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during C…
5347 …-outs and to link up faster. The scaling factor is selected in FAST_LINK_SCALING_FACTOR(default : …
5351 …in the link that you want to connect to the link partner. When you have unused lanes in your syste…
5362 …tween lanes for test purposes. There are three bits per lane. The value is in units of one symbol …
5370 … (0xf<<27) // Set the implementation-specific number of la…
5372 … (0x1<<31) // Disable lane-to-lane deskew. Disables the internal lane-t…
5375 …tween Lanes for test purposes. There are three bits per Lane. The value is in units of one symbol …
5381 … (0x1<<31) // Disable Lane-to-Lane Deskew. Causes the core to disable the intern…
5384 … (0xff<<0) // Max number of functions supported. Used for SR-IOV.
5386 …modifier for replay timer. Increases the timer value for the replay timer, in increments of 64 clo…
5388 …AK latency timer. Increases the timer value for the ACK/NAK latency timer, in increments of 64 clo…
5395 … (0xff<<0) // Maximum function number that can be used in a request. Configura…
5397 …-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in inc…
5399 …atency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clo…
5403 …- 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Fa…
5406 …d sets. Note that the controller actually waits the number of symbol times in this register plus o…
5444 …ror handling rules. For more details, see the "Receive Filtering" section. In each case, '0' appli…
5445 …in this register plus 1 between transmitting SKP ordered sets. Your application must program this …
5451 …In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rul…
5472 …ror handling rules. For more details, see the "Receive Filtering" section. In each case, '0' appli…
5492 … 0x000734UL //Access:R DataWidth:0x20 // Transmit Non-Posted FC Credit Stat…
5493 … (0xfff<<0) // Transmit Non-Posted Data FC Credits. The non-poste…
5495 … (0xff<<12) // Transmit Non-Posted Header FC Credits. The non-post…
5510 … (0x1<<1) // Transmit retry buffer not empty. Indicates that there is data in the transmit retry b…
5512 … (0x1<<2) // Received queue not empty. Indicates there is data in one or more of the r…
5516 …0x1<<13) // Receive serialization queue not empty. Indicates there is data in the serialization qu…
5522 … timer override value. When you set PCIEEP_QUEUE_STATUS[FCLTOE], the value in this field will over…
5524 …<<31) // FC latency timer override enable. When this bit is set, the value in PCIEEP_QUEUE_STATUS[…
5529 … (0x1<<1) // Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry b…
5531 … (0x1<<2) // Received Queue Not Empty. Indicates there is data in one or more of the r…
5533 …e Value. When you set the "FC Latency Timer Override Enable" in this register, the value in this f…
5535 …his bit is set, the value from the "FC Latency Timer Override Value" field in this register will o…
5547 …xff<<0) // WRR Weight for VC0. Note: The access attributes of this field are as follows: - Dbi: R
5549 …xff<<8) // WRR Weight for VC1. Note: The access attributes of this field are as follows: - Dbi: R
5551 …ff<<16) // WRR Weight for VC2. Note: The access attributes of this field are as follows: - Dbi: R
5553 …ff<<24) // WRR Weight for VC3. Note: The access attributes of this field are as follows: - Dbi: R
5565 …xff<<0) // WRR Weight for VC4. Note: The access attributes of this field are as follows: - Dbi: R
5567 …xff<<8) // WRR Weight for VC5. Note: The access attributes of this field are as follows: - Dbi: R
5569 …ff<<16) // WRR Weight for VC6. Note: The access attributes of this field are as follows: - Dbi: R
5571 …ff<<24) // WRR Weight for VC7. Note: The access attributes of this field are as follows: - Dbi: R
5580 …in the segmented-buffer configuration, writable through PEM()_CFG_WR. However, the application mus…
5588 …in the segmented-buffer configuration, writable through PEM()_CFG_WR: 0 = Strict ordering for rece…
5590 …. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer config…
5592 … 0x000748UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Posted Rec…
5593 …redits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of t…
5595 …redits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of t…
5603 … used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: St…
5605 …ceive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbe…
5614 …in the segmented-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at …
5616 … (0x3<<24) // VC0 scale non-posted header credits.
5618 … (0x3<<26) // VC0 scale non-posted data credits.
5622 … 0x00074cUL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Non-Posted Receive…
5623 …-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segm…
5625 …-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the …
5640 …in the segmented-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at …
5648 … 0x000750UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Completion…
5649 …redits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of t…
5651 …redits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of t…
5688 … (0x1<<15) // If set, completions received for a function which is in FLR will not be dire…
5700 … (0x1<<21) // When set, it enables WAKE generation in any L-state, when PME_E…
5706 … (0x1<<24) // When set, it prevents PM from re-entering L1 when programmed to non-D0 p…
5714 … (0x1<<28) // In RC mode, when set, it enables pcie_scnd_rst_b to be asserted whe…
5716 …D_RST_BB (0x1<<29) // In RC mode, when set, i…
5725 … (0x1<<2) // Enable check to determine if the length field and bytecount field are in sync
5759 … and not wait for LTR message to be sent first even though device state may have changed to non-D0.
5763 … (0x1<<21) // Enables uncorrectable Internal Error Reporting if feature is implemented in h/w
5765 … (0x1<<22) // When enabled, hardware checks the bytecount field in completion headers.
5767 …LTR values programmed in 'h848 whenever the h/w asserts the user_send_ltr1 port. This bit is used …
5769 …ammable value(which ever is smaller). This bit is used only if AutoCRSClrOn is defined in version.v
5771 …LTR values programmed in 'h84c whenever the h/w asserts the user_send_ltr2 port. This bit is used …
5773 …in addition to the time that DL waits for bus to be idle. This timer is required to allow DUT to s…
5775 …R values programmed in 'h844 and 'h848 whenever the DUT enters or leaves ASPM L1. This bit is used…
5777 …in 'h840. This state has highest priority and when this bit is set, no other LTR message (other th…
5845 …in Polling.Active and L2.Idle. 0x1 = 1 lane. 0x2 = 2 lanes. 0x3 = 3 lanes. _ ... 0x10 = 16 l…
5847 …in detect. 0x0 = Reserved. 0x1 = Connect logical Lane0 to physical lane 1. 0x2 = Connect …
5857 … (0x1<<20) // Set the deemphasis level for upstream ports. 0 = -6 dB. 1 = -3.5 dB.
5859 …in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a one value on …
5862 …his field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as…
5864 …in Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or b…
5866 …in Detect. Allowed values are: - 3'b000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or C…
5868 …in the core. For more details, see the 'Lane Reversal' appendix in the Databook. This field is res…
5870 …- Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deas…
5872 …ld. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe. Note: The …
5874 …his field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as…
5876 …-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at…
5878 …in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value on …
5885 …t. When this bit is set, PH credits are not released by IP if FIFO at the DL-TL boundary reaches a…
5887 …-posted credit is available to user when bit is set. The credits to user are artificially reduced …
5889 … (0x1<<4) // Enable the reporting of receiver errors in the advanced error r…
5891 …s entry into L1, due to function being in D0unint state. When set, it would require all enabled fu…
5893 … (0x3<<6) // When clear, field overrides the values in the ASPm Control fie…
5897 … (0x1<<16) // This bit when set prevents DUT from entering L1 due to being in non-d0 state.
5899 … (0x7fff<<17) // Programmable delay to prevent link from re-entering L1, when lin…
5931 … (0x1<<10) // This bit is set when h/w detects Poisoned Error Status in function 1. If set, …
5933 …11) // This bit is set when h/w detects Flow Control Protocol Error Status in function 1. If set, …
5935 … (0x1<<12) // This bit is set when h/w detects Completer Timeout Status in function 1. If set, …
5937 … (0x1<<13) // This bits is set when h/w detects Receive UR Status in function 1. If set, …
5939 …(0x1<<14) // This bit is set when h/w detects Unexpected Completion Status in function 1. If set, …
5941 … (0x1<<15) // This bit is set when h/w detects Receiver Overflow Status in function 1. If set, …
5943 … (0x1<<16) // This bit is set when h/w detects Malformed TLP Status in function 1. If set, …
5945 … (0x1<<17) // This bit is set when h/w detects ECRC Error TLP Status in function 1. If set, …
5947 …<<18) // This bit is set when h/w detects Unsupported Request Error Status in function1. If set, h…
6003 …multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to …
6011 …multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to …
6020 …multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to …
6028 …multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to …
6037 …multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to …
6045 …multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to …
6054 …multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to …
6062 …multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to …
6138 … (0x1<<3) // This bit is set when h/w detects Receive UR Status in Function 2. If set, …
6152 … (0x1<<10) // This bit is set when h/w detects Poisoned Error Status in function 3. If set, …
6154 …11) // This bit is set when h/w detects Flow Control Protocol Error Status in function 3. If set, …
6156 … (0x1<<12) // This bit is set when h/w detects Completer Timeout Status in function 3. If set, …
6158 … (0x1<<13) // This bit is set when h/w detects Receive UR Status in function 3. If set, …
6160 …(0x1<<14) // This bit is set when h/w detects Unexpected Completion Status in function 3. If set, …
6162 … (0x1<<15) // This bit is set when h/w detects Receiver Overflow Status in function 3. If set, …
6164 … (0x1<<16) // s bit is set when h/w detects Malformed TLP Status Status in function 3. If set, …
6166 … (0x1<<17) // This bit is set when h/w detects ECRC Error TLP Status in function 3. If set, …
6168 …<<18) // This bit is set when h/w detects Unsupported Request Error Status in function3. If set, h…
6172 …(0x1<<20) // This bit is set when h/w detects Poisoned Error Status Status in function 4. If set, …
6174 …21) // This bit is set when h/w detects Flow Control Protocol Error Status in function 4. If set, …
6176 … (0x1<<22) // This bit is set when h/w detects Completer Timeout Status in function 4. If set, …
6180 …(0x1<<24) // This bit is set when h/w detects Unexpected Completion Status in function 4. If set, …
6182 … (0x1<<25) // This bit is set when h/w detects Receiver Overflow Status in function 4. If set, …
6184 … (0x1<<26) // This bit is set when h/w detects Malformed TLP Status in function 4. If set, …
6186 … (0x1<<27) // This bit is set when h/w detects ECRC Error TLP Status in function 4. If set, …
6188 …<<28) // This bit is set when h/w detects Unsupported Request Error Status in function4. If set, h…
6278 … (0x1<<10) // Poisoned Error Status detected in function 6. If set, …
6280 … (0x1<<11) // Flow Control Protocol Error Status detected in function 6, if set, …
6282 … (0x1<<12) // Completer Timeout Status detected in function 6. If set, …
6286 … (0x1<<14) // Unexpected Completion Status detected in function 6, if set, …
6288 … (0x1<<15) // Receiver Overflow Status detected in function 6. If set, …
6290 … (0x1<<16) // Malformed TLP Status detected in function 6. If set, …
6292 … (0x1<<17) // ECRC Error TLP Status detected in function 6. If set, …
6294 … (0x1<<18) // Unsupported Request Error Status detected in function6. If set, h…
6298 … (0x1<<20) // Poisoned Error Status detected in function 7. If set, …
6300 … (0x1<<21) // Flow Control Protocol Error Status detected in function 7, if set, …
6302 … (0x1<<22) // Completer Timeout Status detected in function 7. If set, …
6306 … (0x1<<24) // Unexpected Completion Status detected in function 7, if set, …
6308 … (0x1<<25) // Receiver Overflow Status detected in function 7. If set, …
6310 … (0x1<<26) // Malformed TLP Status detected in function 7. If set, …
6312 … (0x1<<27) // ECRC Error TLP Status detected in function 7. If set, …
6314 … (0x1<<28) // Unsupported Request Error Status detected in function7. If set, h…
6359 … (0x1<<0) // This bit when cleared will keep the Serdes MDIO regs in reset till PERST_N i…
6361 … (0x1<<1) // This bit when cleared will keep the micro in reset till PERST_N i…
6389 … either due to hide_func_1 pad being driven high or due to programming bit in TL reg This bit is t…
6391 …func2 is hidden either due to hide_func_2 pad being driven high or due to programming bit in TL reg
6393 …func3 is hidden either due to hide_func_3 pad being driven high or due to programming bit in TL reg
6395 …func4 is hidden either due to hide_func_4 pad being driven high or due to programming bit in TL reg
6397 …func5 is hidden either due to hide_func_5 pad being driven high or due to programming bit in TL reg
6399 …func6 is hidden either due to hide_func_6 pad being driven high or due to programming bit in TL reg
6401 …func7 is hidden either due to hide_func_7 pad being driven high or due to programming bit in TL reg
6403 …func8 is hidden either due to hide_func_8 pad being driven high or due to programming bit in TL reg
6405 …func9 is hidden either due to hide_func_9 pad being driven high or due to programming bit in TL reg
6407 …nc10 is hidden either due to hide_func_10 pad being driven high or due to programming bit in TL reg
6409 …nc11 is hidden either due to hide_func_11 pad being driven high or due to programming bit in TL reg
6411 …nc12 is hidden either due to hide_func_12 pad being driven high or due to programming bit in TL reg
6413 …nc13 is hidden either due to hide_func_13 pad being driven high or due to programming bit in TL reg
6415 …nc14 is hidden either due to hide_func_14 pad being driven high or due to programming bit in TL reg
6417 …nc15 is hidden either due to hide_func_15 pad being driven high or due to programming bit in TL reg
6535 … (0x1<<10) // Poisoned Error Status detected in function 9. If set, …
6537 … (0x1<<11) // Flow Control Protocol Error Status detected in function 9, if set, …
6539 … (0x1<<12) // Completer Timeout Status detected in function 9. If set, …
6543 … (0x1<<14) // Unexpected Completion Status detected in function 9, if set, …
6545 … (0x1<<15) // Receiver Overflow Status detected in function 9. If set, …
6547 … (0x1<<16) // Malformed TLP Status detected in function 9. If set, …
6549 … (0x1<<17) // ECRC Error TLP Status detected in function 9. If set, …
6551 … (0x1<<18) // Unsupported Request Error Status detected in function9. If set, h…
6555 … (0x1<<20) // Poisoned Error Status detected in function 10. If set,…
6557 … (0x1<<21) // Flow Control Protocol Error Status detected in function 10, if set,…
6559 … (0x1<<22) // Completer Timeout Status detected in function 10. If set,…
6563 … (0x1<<24) // Unexpected Completion Status detected in function 10, if set,…
6565 … (0x1<<25) // Receiver Overflow Status detected in function 10. If set,…
6567 … (0x1<<26) // Malformed TLP Status detected in function 10. If set,…
6569 … (0x1<<27) // ECRC Error TLP Status detected in function 10. If set,…
6571 … (0x1<<28) // Unsupported Request Error Status detected in function10. If set, …
6641 …gating feature when there is no receive traffic, receive queues and pre/post-queue pipelines are e…
6664 … (0x1<<10) // Poisoned Error Status detected in function 12. If set,…
6666 … (0x1<<11) // Flow Control Protocol Error Status detected in function 12. If set,…
6668 … (0x1<<12) // Completer Timeout Status detected in function 12. If set,…
6672 … (0x1<<14) // Unexpected Completion Status detected in function 12. If set,…
6674 … (0x1<<15) // Receiver Overflow Status detected in function 12. If set,…
6676 … (0x1<<16) // Malformed TLP Status detected in function 12. If set,…
6678 … (0x1<<17) // ECRC Error TLP Status detected in function 12. If set,…
6680 … (0x1<<18) // Unsupported Request Error Status detected in function12. If set, …
6684 … (0x1<<20) // Poisoned Error Status detected in function 13. If set,…
6686 … (0x1<<21) // Flow Control Protocol Error Status detected in function 13. If set,…
6688 … (0x1<<22) // Completer Timeout Status detected in function 13. If set,…
6692 … (0x1<<24) // Unexpected Completion Status detected in function 13. If set,…
6694 … (0x1<<25) // Receiver Overflow Status detected in function 13. If set,…
6696 … (0x1<<26) // Malformed TLP Status detected in function 13. If set,…
6698 … (0x1<<27) // ECRC Error TLP Status detected in function 13. If set,…
6700 … (0x1<<28) // Unsupported Request Error Status detected in function13. If set, …
6707 … (0x1<<0) // Gen3 receiver impedance ZRX-DC not compliant.
6727 …in L0 state at Gen3 data rate and equalization was completed successfully in Autonomous EQ Mechani…
6729 …can optionally send 8GT EQ TS2 and it means USP can set DSP TxPreset value in Gen4 Data Rate. If t…
6735 …-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is us…
6736 …-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defin…
6740 …Gen4 data rate. Note: The access attributes of this field are as follows: - Dbi: see description…
6746 …-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the…
6748 …- 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. - 1: mac_phy_rxeq…
6822 … (0x1<<10) // Poisoned Error Status detected in function 15. If set,…
6824 … (0x1<<11) // Flow Control Protocol Error Status detected in function 15. If set,…
6826 … (0x1<<12) // Completer Timeout Status detected in function 15. If set,…
6830 … (0x1<<14) // Unexpected Completion Status detected in function 15. If set,…
6832 … (0x1<<15) // Receiver Overflow Status detected in function 15. If set,…
6834 … (0x1<<16) // Malformed TLP Status detected in function 15. If set,…
6836 … (0x1<<17) // ECRC Error TLP Status detected in function 15. If set,…
6838 … (0x1<<18) // Unsupported Request Error Status detected in function15. If set, …
6845 …he MSB of a PF's HIDE_PFn is non-zero, the PF is considered hidden, and the power management state…
6880 …K2 (0x3<<2) // Operates in the same way as PF0.
6882 …K2 (0x3<<4) // Operates in the same way as PF0.
6884 …K2 (0x3<<6) // Operates in the same way as PF0.
6886 …K2 (0x3<<8) // Operates in the same way as PF0.
6888 …2 (0x3<<10) // Operates in the same way as PF0.
6890 …2 (0x3<<12) // Operates in the same way as PF0.
6892 …2 (0x3<<14) // Operates in the same way as PF0.
6894 …2 (0x3<<16) // Operates in the same way as PF0.
6896 …2 (0x3<<18) // Operates in the same way as PF0.
6898 …K2 (0x3<<20) // Operates in the same way as PF0.
6900 …K2 (0x3<<22) // Operates in the same way as PF0.
6902 …K2 (0x3<<24) // Operates in the same way as PF0.
6904 …K2 (0x3<<26) // Operates in the same way as PF0.
6906 …K2 (0x3<<28) // Operates in the same way as PF0.
6908 …K2 (0x3<<30) // Operates in the same way as PF0.
6911 … (0xf<<0) // Feedback mode. 0 = Direction of change. 1 = Figure of merit. 2-15 = Reserved.
6913 …3 successful status bit is not set in the link status register. * Equalization phase 3 complete s…
6915 … (0x1<<5) // Phase2_3 2 ms timeout disable. Determine behavior in Phase2 for USP (Phas…
6919 …in the EQ master phase. Bit [i] = 1: Preset=i is requested and evaluated in the EQ master phase.…
6921 …ude, or not, the FOM feedback from the initial preset evaluation performed in the EQ master, when …
6925 … (0x1<<26) // Request core to send back-to-back EIEOS in Recovery.Rcv…
6927 … register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream po…
6928 … (0xf<<0) // Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserv…
6930 …- 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found then: …
6932 …in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxE…
6934 …in EQ Master Phase. Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase. - 000…
6936 …eset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluati…
6940 … core to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping …
6943 … (0x1f<<0) // Minimum time (in ms) to remain in EQ master phase. The LTSSM st…
6945 …in phase 2/3 when determining if optimal coefficients have been found. When 0x0, EQ master is pe…
6947 … (0xf<<10) // Convergence window aperture for C-1. Precursor coeffici…
6951 …Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feed…
6952 … (0x1f<<0) // Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM st…
6954 …in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0,1,2,..16 u…
6956 …TA_K2 (0xf<<10) // Convergence Window Aperture for C-1. Pre-cursor coefficient…
6958 …K2 (0xf<<14) // Convergence Window Aperture for C+1. Post-cursor coefficients m…
6961 …-Posted passing posted ordering rule control. Determines if a NP can pass halted P queue. 0x0 = …
6963 …lted P queue. 0x0 = CPL can not pass P (recommended). 0x1 = CPL can pass P. 0x2-0xFF = Reserved.
6966 …<0) // Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue…
6968 … Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1…
6971 … (0xffff<<0) // Loopback rxvalid (lane enable - 1 bit per lane).
6984 … (0x1<<31) // PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This reg…
6989 …error reporting). A completion with UR status will be generated for non-posted requests. 0x1…
6991 …e suppresses error logging, error message generation, and CPL generation (for non-posted requests).
6995 … (0x1<<4) // Disable the autonomous generation of LTR clear message in upstream port. 0 = …
6999 … 0x0008bcUL //Access:RW DataWidth:0x20 // DBI Read-Only Write Enable Reg…
7000 …he local application through the DBI. For more details, see "Writing to Read-Only Registers." Not…
7003 …th. 0x0 = Core does not start upconfigure or autonomous width downsizing in configuration state.…
7005 …in the configuration state. If [TRGT_LNK_WDTH] is 0x0, the core does not start upconfigure or au…
7007 …t. The core sends this value to the link upconfigure capability in TS2 ordered sets in Configurat…
7009 …-lane Control Register. Used when upsizing or downsizing the link width through Configuration sta…
7010 …- 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration s…
7012 …- If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CO…
7014 …ink Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is res…
7017 …in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus …
7023 …s aux_clk switch and core_clk gating in L1. 1 = Controller does not request aux_clk switch and …
7026 …in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus …
7028 …- 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Core wai…
7030 …ccess:RW DataWidth:0x20 // Using this register you can delete on entry in the target completio…
7033 …This is a one-shot bit. Writing a one triggers the deletion of the target completion LUT entry tha…
7035 …in the target completion LUT. Note:: The target completion LUT (and associated target completion …
7038 …on of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-cl…
7052 … (0x3<<10) // Split table Contents for tag0. This corresponds to attr field in PCIE header.
7096 … (0xff<<24) // Non-Posted Data credits a…
7105 …BB (0xf<<28) // Non-Posted Data credits a…
7114 … (0xff<<24) // Non-Posted Data credits c…
7123 …BB (0xf<<28) // Non-Posted Data credits c…
7134 … (0x1<<16) // Available Non-posted credit for tar…
7137 …B (0xff<<0) // Non-Posted header credits…
7139 …B (0xff<<8) // Non-Posted data credits a…
7145 … 0x000998UL //Access:R DataWidth:0x20 // State machines in TL status for debug.
7146 … (0xf<<0) // Target Non-Posted request State …
7175 …ultiple bus numbers. In this case VFs are accessed using Cfg Type 1 Transactions. This bit should …
7177 …56(when vf_nextbus, bit 0 is set). User would have to set the offset bit on their own in this case.
7182 …non-posted data credits since the last request for immediate update that are needed to force an im…
7184 … (0xff<<12) // The number of accumulated non-posted header credits…
7186 …-posted credits are flagged for immediate update. When clear, the credits may or not be updated un…
7188 …the forced update if there are outstanding non-posted credits to update. The resolution on the tim…
7190 …-posted credit updates are forwarded to the DLL as immediate updates after a given number of micro…
7199 … update if there are outstanding posted credits to update. The resolution on the timer is +/- 1 us.
7201 …w) elapses since the last update. This is typically used with non-immediate (threshold-based) upda…
7204 … Each bit, when set, indicates that the corresponding capability available in cap_ena is valid onl…
7206 … Each bit, when set, indicates that the corresponding capability available in ext_cap_ena is valid…
7208 … Each bit, when set, indicates that the corresponding capability available in rc_ext_cap_ena is va…
7210 … Each bit, when set, indicates that the corresponding capability available in ext2_cap_ena is vali…
7212 … Each bit, when set, indicates that the corresponding capability available in ext3_cap_ena is vali…
7216 … Each bit, when set, indicates that the corresponding capability available in rc_ext2_cap_ena is v…
7218 …//Access:RW DataWidth:0x20 // This register is present if PCIE_VDM_SUPP is defined in version.v
7219 … (0x3ff<<0) // Length in bytes to which VDM m…
7225 …//Access:RW DataWidth:0x20 // This register is present if PCIE_PTM_SUPP is defined in version.v
7228 … field when set will prevent hardware from generating attention when PTM req- response handshake h…
7232 … (0x1<<30) // This field when set inidcates that the PTM req-response handshake in…
7234 … (0x1<<31) // This field when set inidcates that the PTM req-response handshake co…
7236 …//Access:R DataWidth:0x20 // This register is present if PCIE_PTM_SUPP is defined in version.v
7237 …//Access:R DataWidth:0x20 // This register is present if PCIE_PTM_SUPP is defined in version.v
7238 …//Access:R DataWidth:0x20 // This register is present if PCIE_PTM_SUPP is defined in version.v
7239 …//Access:R DataWidth:0x20 // This register is present if PCIE_PTM_SUPP is defined in version.v
7240 …//Access:R DataWidth:0x20 // This register is present if PCIE_PTM_SUPP is defined in version.v
7241 …//Access:R DataWidth:0x20 // This register is present if PCIE_PTM_SUPP is defined in version.v
7242 …//Access:R DataWidth:0x20 // This register is present if PCIE_PTM_SUPP is defined in version.v
7244 …in the TX direction, as programmed in the reg_ttx_det_tlp_type register. When this bit is reset to…
7248 …on time in microseconds. When it is set to '0', software has to clear the reg_ttx_tlp_stat_en bit …
7277 …in the reg_trx_det_tlp_type register in RX direction. When this bit is reset to '0', the counting …
7281 …on time in microseconds. When it is set to '0', software has to clear the reg_trx_tlp_stat_en bit …
7309 …ng fields in the LTR messages that are transmitted by the port. For a downstream port, the regist…
7322 …in this register) differs between an upstream port and a downstream port. For an upstream port, th…
7323 …<<0) // Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7325 …<10) // Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7327 …/ Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7329 …) // No Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7331 …) // No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7333 …o Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7336 …x3ff<<0) // The aux_clk frequency in MHz. This value is used to provide a 1 us reference for count…
7339 …in MHz. This value is used to provide a 1 us reference for counting time during low-power states w…
7342 …R_OFF_E5 (0x3<<0) // Duration (in us) of L1.2 entry.
7344 …T_L1_2_E5 (0xf<<2) // Duration (in us) of L1.2.
7346 …E5 (0x3<<6) // Max delay (in 1 us units) between …
7388 …us and control register for the PL DL Debug FIFO. Trigger and status shown in this register. For t…
7389 …RETRIG_CNT_BB (0xff<<0) // When non-zero, indicates the m…
7393 …where data corresponding to the trigger cycle is collected). Bit 17 is a wrap condition in the FIFO
7403 …buffer is filled, the trig_addr field is used to determine the amount of pre-trigger data collected
7422 … (0x1ff<<23) // Current write address to the external FIFO. Bit 31 is a wrap condition in the FIFO
7424 …- mask bits [319:0] for 0to1 trigger0 Register 10 :: IND_PCIE_DBG_TRIG0_1TO0_MASK - mask bits [319…
7455 …- no FIFO selected to read by user if 001 - PL/DL FIFO is selected to read by user if 010 - TLDA…
7459 … (0x7<<12) // 000 - generic lane is selected 001 - predefined lane 1 010 - predefine…
7479 …register for the Transaction Layer Data Analyzer. Trigger and status shown in this register. If bo…
7482 …, indicates that the lower 160 bits from the current FIFO read address are in the RDFIFO registers.
7484 … (0x1<<8) // When set and in local mode, reads to…
7486 … (0x1<<9) // When set, the FIFOs are linked in series to increase t…
7488 … (0x1<<10) // When set, the FIFOs are linked in parallel to increase…
7490 …esent on the interface. Note that there is a bug in earlier versions of the TLDA that make this a …
7496 … (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be …
7498 … (0x7f<<15) // The number of pre-trigger samples to ke…
7523 …in the TLDA docs. The registers are: -- First trigger configuration registers Register 0 :: IND_T…
7524 …in these registers is advanced to the next half of the FIFO data. So when the first PCIER_TLDA0_RD…
7525 … 0x000c50UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the FIFO
7526 … 0x000c54UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the FIFO
7527 … 0x000c58UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the FIFO
7528 … 0x000c5cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the FIFO
7529 …register for the second Transaction Layer Data Analyzer. Trigger and status shown in this register.
7532 …, indicates that the lower 160 bits from the current FIFO read address are in the RDFIFO registers.
7534 … (0x1<<8) // When set and in local mode, reads to…
7536 … (0x1<<9) // When set, this indicates the FIFOs are linked in series to increase t…
7538 … (0x1<<10) // When set, this indicates the FIFOs are linked in parallel to increase…
7540 …esent on the interface. Note that there is a bug in earlier versions of the TLDA that make this a …
7546 … (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be …
7548 … (0x7f<<15) // The number of pre-trigger samples to ke…
7573 …in the TLDA docs. The registers are: -- First trigger configuration registers Register 0 :: IND_T…
7574 …in these registers is advanced to the next half of the FIFO data. So when the first PCIER_TLDA1_RD…
7575 …000c70UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the second …
7576 …x000c74UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the second …
7577 …x000c78UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the second …
7578 …0x000c7cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the second …
7584 … (0x1<<2) // DL: Disable Replay Timer. In effect, REPLAY only …
7596 …either inferred electrical idle occurs or signal is not detected on all lanes while in L0 or RxL0s.
7625 …// When this bit is set, the software value will be used for UpdateFC Latency of Non-Posted credit.
7627 …ill not be reset if a NAK is received during a Replay operation. While not in Replay, a NAK always…
7633 … (0x1<<14) // This initiates Link re-training by directing…
7637 …fore initiating ASPM L1 request. If L0s is enabled, it is the time link is in L0s. If L0s is not e…
7641 …y control ASPM L1 by monitoring link activities. Signal user_early_l1_exit also works in this mode.
7650 … (0x1<<3) // DL: If set, it will enable ACK Latency Timer. In this case, DL ACK or…
7652 …timer. HW will select programmable value depending on whether PHY operates in gen 1or gen2. The pr…
7654 …timer. HW will select programmable value depending on whether PHY operates in gen 1or gen2. The pr…
7658 …is field specifies the minimum number of clock cycles that LTSSM will stay in RxL0s, L1, L2 Idle s…
7664 …1<<17) // DL: Enable Non-Posted Latency Timer. If this timer reaches MAX_ACK_LAT_TIMER value, DL w…
7666 …ust detect within an 256us interval before asserting Correctable Error flag in DLATTN_VEC register.
7678 … (0xfff<<0) // DL: Non-Posted Data for INITFC
7696 … (0xff<<0) // Gen3 N_FTS value advertised when in common clock mode.
7698 … (0xff<<8) // Gen3 N_FTS value advertised when not in common clock mode.
7700 … (0xffff<<16) // Reserved - always write 0
7703 …alue for the replay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1…
7705 …are Gen3 internal delay for the replay timeout in symbol time. This delay is only applied to the h…
7707 …_BB (0x7ff<<21) // Reserved - always write 0
7710 … (0xfff<<0) // Software Gen3 AckNak latency timer value in symbol time.
7712 …in symbol time. Depending on speed and Max Packet Size (MPS), hardware automatically generates an …
7714 … (0xfff<<20) // Software Gen3 UpdateFC latency value in symbol time.
7717 …alue for the replay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1…
7719 …are Gen1 internal delay for the replay timeout in symbol time. This delay is only applied to the h…
7734 …t from sending more Posted FC updates , potentially stall DMA requests, until the flag de-asserted.
7737 …alue for the replay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1…
7739 …are Gen2 internal delay for the replay timeout in symbol time. This delay is only applied to the h…
7742 … (0xfff<<0) // Software Gen1 AckNak latency timer value in symbol time.
7744 …in symbol time. Depending on speed and Max Packet Size (MPS), hardware automatically generates an …
7746 … (0xfff<<20) // Software Gen1 UpdateFC latency value in symbol time.
7749 … (0xfff<<0) // Software Gen2 AckNak latency timer value in symbol time.
7751 …in symbol time. Depending on speed and Max Packet Size (MPS), hardware automatically generates an …
7753 … (0xfff<<20) // Software Gen2 UpdateFC latency value in symbol time.
7779 … counter is incremented if there is any error associate with LCRC mismatch in DLP, DLL, PHY on rec…
7781 … (0x1<<6) // Indicate un-decoded condition in de-framing l…
7791 … (0x1<<11) // Set if DL detects impossible condition to de-allocate entries in Replay Buff…
7801 … (0x1<<16) // Detect DLLP with mismatched CRC-16 on receiving side.
7812 … (0x1fffff<<0) // If set mask out DL attentions specified in register 0x1040
7837 … (0x3f<<0) // DL: Maximum time in microseconds that DL…
7839 … (0xff<<6) // DL: Maximum time in microseconds that DL…
7844 …in T2D FIFO becomes available, next data may not be available as fast as DL can retrieve. This can…
7846 … (0x7<<1) // T2D FIFO Count Threshold. This is the number of valid data in T2D FIFO before DL s…
7859 …0) // Replay FIFO Test Size Select. When this bit is set to '1', the value in replayfifo_testsize …
7861 …<<31) // D2T FIFO Test Size Select. When this bit is set to '1', the value in d2tfifo_testsize wil…
7869 …'0' to these bits causes no action and allows the address to be programmed in preparation for a wr…
7874 …is bit must be written as a '1' to initiate write cycle based ont the data in bits [15:0] and the …
7877 … (0x7fffffff<<0) // After a read has been requested in the mdio_addr regist…
7879 … will read as '0' until a requested read of the PCIE serdes has completed, in which case, this bit…
7881 …In ATE test mode this register together with ate_tlp_hdr_1, ate_tlp_hdr_2, and ate_tlp_hdr_3 form …
7882 … 0x001110UL //Access:RW DataWidth:0x20 // When a TLP is generated in ATE test mode, this …
7883 … 0x001114UL //Access:RW DataWidth:0x20 // When a TLP is generated in ATE test mode, this …
7884 … 0x001118UL //Access:RW DataWidth:0x20 // When a TLP is generated in ATE test mode, this …
7886 …umber of TLP's to be transferred. When ate_tlp_go is set to '1', the value in this field is loaded…
7894 …d. This field holds the first data byte of the first TLP payload generated in ATE test mode. The r…
7911 … HW transmits number of TLPs equal to ATE_TLP_CNT (bits[7:0] of ate_tlp_cfg - offset 0x111c). trx_…
7915 …] of ate_tlp_cfg - offset 0x111c). This register value needs to be ignored until user writes '1' t…
7937 …his bit must be written as a '1' to initiate write cycle based on the data in bits [15:0] and the …
7940 … (0xffff<<0) // After a read has been requested in the pmi_addr registe…
7944 … will read as '0' until a requested read of the PCIE serdes has completed, in which case, this bit…
7967 … (0x1<<0) // Request a width change (ie -make the link wider, …
7969 … (0x1<<1) // Request a speed change (ie -make the link fast or…
7975 …0x1<<6) // For multi-lane links on a 2.0 compliant core, enable advertisement of the capability to…
7985 …Ie Serdes as errors when processing ordered sets, DLLPs, and TLPs BUG: do not use in EP/RC Ax cores
7987 …Ie Serdes as errors when processing ordered sets, DLLPs, and TLPs BUG: do not use in EP/RC Ax cores
7989 …Ie Serdes as errors when processing ordered sets, DLLPs, and TLPs BUG: do not use in EP/RC Ax cores
7995 … (0x1<<17) // If set, both error symbols must match in the received Modifie…
7997 …(0x1<<18) // Directed exit from generating the Modified Compliance Pattern in Polling.Compliance i…
8001 …Polling.Active. This also causes the Compliance Receive bit in the outgoing TS1s to be set in Poll…
8003 …electable Deemphasis bit set in TS1s in Polling.Active, Loopback, Recovery, and some Configuration…
8005 …in the Detect state (this propagates to the PCIe Serdes via the TxDeemph signal. 0 == -6 dB, 1 == …
8007 …alue for the Autonomous Change bit set in TS1s in the Configuration state when PhyLinkUp is set an…
8013 …ctrical idle or inferred electrical ide as a condition for exiting loopback in 2.0 compliant cores.
8015 … (0x1<<27) // Disable use of electrical idle in Recovery.Speed - only use in…
8019 … (0x1<<29) // Disable the ability to compensate for lane reversal in multi-lane links.
8021 … the transition to Recovery.Idle. This is newly specified for the 2.1 spec in cases where no speed…
8023 … (0x1<<31) // Enable gen2 features when in 1.1 compliance mode …
8026 … (0x1<<0) // Force the PIPE interface to be 16-bit, even in Gen 1 Software…
8030 … (0x1<<2) // Enable the PIPE-style powerdown of unused lanes in a multi-…
8032 … (0x1<<3) // Enable the auxilliary powerdown of unused lanes in a multi-lane link.
8034 … (0x1<<4) // Initiate PL changes required for a far-end loopback
8040 … (0x1f<<7) // Tuning field to set the delay in clocks for the elect…
8042 …goes to the PCIe Serdes to enable the PLL to power down when all lanes are in L1 If ClkReq is acti…
8044 …<<13) // Enable using lack of received COM instead of lack of received TS2 in Recovery.RcvrCfg for…
8046 …the number of EIE symbols to send before the first FTS when exiting Tx_L0s in Gen2 b00 : Four EIE…
8048 … (0x1<<16) // Use valid data as "exit from electrical idle" in the Loopback states
8052 … (0x1<<18) // Declare an inferred electrical idel in L0 if no Skip Ordered Set (SOS) is received…
8054 …nferred electrical idle in L0 if no UpdateFC is received in any 128 us interval. Can be combined w…
8068 … (0x1<<29) // Clear the LTSSM histogram. Not self-clearing
8070 … (0x1<<30) // Clear the Gen2 debug histogram. Not self-clearing
8072 … (0x1<<31) // Clear the recovery histogram. Not self-clearing
8077 … (0x1ff<<7) // Minimum time (in 4 ns clocks) to hold the transmitter in …
8079 …nimum time (in 4 ns clocks) to hold the transmitter in electrical idle when changing line rate aft…
8081 …erved - only write 0. Spare flops for the PL - train_ctl_in[1:0]. [29] (PL_FIX_19) Enable Phase 3 …
8083 …es elastic buffers will be prevented from adjusting - generating dynamic clock compensation events…
8085 … (0x1<<31) // Reserved - only write 0. Spare flop for the PL - t…
8088 … (using prescaled increments) before declaring an inferred electrical idle in Recovery.RcvrCfg bas…
8090 … (using prescaled increments) before declaring an inferred electrical idle in Recovery.Speed or Lo…
8092 … (0x1<<14) // Enable the "pins" gloopback - assumes an external …
8100 … (0x1<<18) // Enable received data to be presented to the DLL in Configuration.Idle o…
8108 … (0x1<<22) // Disable requirement for all lanes in EI on transition to …
8110 … (0x1<<23) // Enable requirement for Serdes to be in P1 before receiver d…
8114 … (0x1<<25) // Change the rate to the Serdes to Gen1 in the Disabled state r…
8116 … (0x7<<26) // Select the delay to gate off data from the PL to the DLL in Gen1 and Gen2 rates.
8118 … (0x7<<29) // Select the delay to gate off data from the PL to the DLL in Gen3 rate.
8133 … (0x1<<6) // For RC only. Report automatic speed up/slow down by the RC in the Autonomous Bandw…
8141 …rtion of electrical idle to the power state change to P2. The delay is the in clocks and is 4 + th…
8143 … This is needed in Gen2 when entering L2. The minimum time to wait in Detect.Quiet (in 32 ns incre…
8149 … (0x1<<16) // Enable exit from Compliance on 1.1-compliant systems on …
8162 …// High 4 bits of the 10 bit-counter of 25 MHz clks for the minimum time to spend waiting for the …
8168 …erdes device type to minimize the PLL lock time (when set, don't reuse the old value - start over).
8170 …-frequency clock used to advance the L0s exit state machine. Default is from the version.v b00 : …
8172 … // Low 6 bits of the 10 bit-counter of 25 MHz clks for the minimum time to spend waiting for the …
8174 … (0x1<<30) // Reserved - only write 0
8179 … to delay between the start of active clkreq (not in the standby state) and the switchover from Re…
8181 …B (0x3<<6) // Reserved - only write 0
8185 … (0x3<<14) // Reserved - only write 0
8189 … (0x1<<17) // Use any PhyStatus to indicate the P0->P2 transition. De…
8195 … (0xfff<<20) // Reserved - only write 0
8198 … (0xf<<0) // b0000: select pseudo-random value between …
8204 … start of frame (STP or SDP. b01 : corrupt end of frame b00 : corrupt data in frame (second symbol…
8212 … (0x1fff<<18) // Reserved - always write 0
8214 …cleared (the default), Gen3 block alignment errors and invalid data result in the link being decla…
8217 … (0x1<<0) // If set, either an elastic buffer overflow or underflow (in the Serdes)
8219 … (0x1<<1) // If set, a disparity error occurred in the Serdes WC 0
8221 … (0x1<<2) // If set, an 8b10b decode error occurred in the Serdes
8227 …B (0x1<<5) // Receiver training error in L0S
8233 …1_BB (0xf<<8) // Reserved - only write 0
8254 …_1_BB (0xf<<8) // Reserved - only write 0
8269 … (0x1<<8) // *** Do not modify!! Enable 16-bit data for all rate…
8273 …RAM_BB (0x1<<10) // Disable scrambling in Gen3.
8277 … (0x1<<12) // Allow locking to the data blocks in Gen3 Modified Compli…
8283 …isable the logic that corrects for misaligned deassertions of RxDataValid (in other words, null da…
8287 … (0x3<<17) // Reserved - only write 0
8291 … (0xf<<20) // Minimum time (in PCLKs) to wait for E…
8293 … (0x1<<24) // Enable TX preset encoding for value b1010 in CLB/CBB environments
8295 … (0x1<<25) // Enable 4 ms inferred electrical idle in Recovery.RcvrCfg at …
8297 … // Enable transmission of 128 TS2s in Recovery.RcvrCfg prior to transition to Recovery.Speed (ins…
8310 …xfffff<<0) // Clear the corresponding bits indicating Gen3 errors reported in offset 0x1d34, bits …
8312 … (0x1<<20) // Enable a bad/misplaced End-of-Data-Stream token as a…
8320 … (0x1<<24) // Enable the auxilliary bad sync header to be reported as an error in all cases.
8322 …0x1<<25) // Enable the auxilliary alignment error to be reported as a framing/receiver error in L0.
8324 … the auxilliary alignment error to be reported as a framing/receiver error in Configuration and Re…
8326 … (0x1<<27) // Enable bad sync header errors as lane status errors in the Secondary PCIE s…
8332 … (0x1<<30) // Disable reporting Gen3 data parity errors in the Secondary PCIE s…
8334 … (0x1<<31) // Eanble error when idle symbols appear in the DW before a TLP …
8339 … (0x7<<1) // Upper three bits of the local deephasis setting in cases where no prese…
8343 … (0x1<<5) // Software sets if it can disable data traffic during re-equalization.
8371 …O_PRESET_BB (0x1<<22) // enable echo preset bit in Phase 3
8375 …BK_EC23_ENA_BB (0x1<<24) // In Gen3 Loopback Slave …
8379 … (0x1<<26) // Disable presets in Phase 2 (raw data to…
8383 …B (0x1<<28) // Reserved - only write 0
8385 … (0x1<<29) // Disable timeout counter delay waiting for EC bits to change in equalization
8392 … (0x1f<<0) // Delay value for raw electrical idle to sig detect in Gen3 mode
8398 …5_BB (0x1<<7) // For Gen3 TS1s in Equalization, match …
8406 … (0x1<<11) // Enable Gen3 redo deskew on framing/post-deskew alignment issu…
8412 … (0x1<<14) // Enable the L1 failure on 24 ms timeout in R.Lock
8424 … (0x1<<20) // Enable check for mismatch of presets in R.Lock after equaliz…
8426 … (0x1<<21) // Enable PhyLinkUp holdoff in Gen3 (for InitFC vs …
8428 … (0x1<<22) // (PL_FIX_05) Enable preset-coefficient lookup fo…
8430 … (0x1<<23) // (PL_FIX_05) Tx/Rx presets in phase 2 must match b…
8447 …C_BB (0x1<<6) // SED read address auto-increment
8463 …/ [DEBUG_BIT}: Captures internal defined FS and LF values when receive use preset = 1 in EQ Phase 1
8468 …ET_LUT_ENTRY_5_TO_0_BB (0x3f<<0) // Pre-cursor for the coeffi…
8472 …_LUT_ENTRY_17_TO_12_BB (0x3f<<12) // Post-cursor for the coeffi…
8478 … (0x1<<23) // Conbtrol bit to select the default preset to use in phase2 advertizement…
8480 … to the Link partner-RC Transmitter in Phase2 EQ programmable preset value advertized by the RC to…
8482 … (0x1<<28) // Use programmable preset Phase2 EQ in EP mode
8484 … (0x1<<29) // [DEBUG_BIT]: use programmable coefficients in Phase2 EQ
8486 … (0x1<<30) // enable LP coeffcient match checking in default/noraml Phase…
8491 … (0xf<<0) // (PL_FIX_15) Transmitter preset to transmit in EP EQ TS2s
8493 … (0x7<<4) // (PL_FIX_15) Receiver preset hint to transmit in EP EQ TS2s
8511 … (0x1<<15) // [SEMI_FUNCTIONAL]: Extend timeout in RecovRecvrLock State…
8513 … (0x1<<16) // [SEMI_FUNCTIONAL]: Extend timeout in RecovRecvrLock State…
8515 … (0x1<<17) // [SEMI_FUNCTIONAL]: Extend programmable timeout select control in RecovRecvrLock State
8517 … (0x1f<<18) // [SEMI_FUNCTIONAL]: Extend programmable timeout value in RecovRecvrLock State
8519 … (0x1ff<<23) // programmable wait delay in Phase2 of equalizati…
8523 …asis register control programming of coefficients for preset-0(-6dB) and preset-1(-3.5dB) in the f…
8525 …reset 0 and 1 0: points to the preset 0 coefficients(-6dB) 1: points to the preset 1 coefficients(…
8529 …0) // Gen2 deemphasis register select control bit to change from Preset-1(-3.5dB) to preset-0(-6dB)
8531 …/ Select control bit for the read status of the gen1/2 and gen2 lut entry 18-bit value poining to …
8541 …lears the previous statate transitions captured for recovery eq statemachine in ph2(EP) and ph3(RC)
8576 … (0x1<<31) // RX reset EIEOS control bit for TS1(SYM6-Bit2) in Recovery.Equaliz…
8579 …x1<<0) // Enable bit to control the registered programmed FULL SWING value in Phase 1 of eualizati…
8581 … (0x3f<<1) // Registered programmed 6-bit FULL SWING value in Phase 1 o…
8583 …<7) // Enable bit to control the registered programmed LOW FREQUENCY value in Phase 1 of eualizati…
8585 … (0x3f<<8) // Registered programmed 6-bit LOW FREQUENCY value in Phase 1…
8587 … (0x1<<14) // Selects to the received coefficients in the phase 2 of equal…
8589 …]: Disables the 1usec wait time for LP to response for preset or coeff req in phase2(EP and phase3…
8591 …BB (0x1<<16) // Enables EC0 echo use preset bit in EP mode
8593 …ET_BB (0x1<<17) // Enables EC2 echo use preset bit in RC mode
8595 …BB (0x1<<18) // Use programmable preset Phase3 EQ in RC mode
8597 … (0x1<<19) // [DEBUG_BIT]: Ignore the receive ec2 use preset check in phase2 of equalizati…
8599 …[DEBUG_BIT]: Disables Preset and coefficient rule check error in phase 3 of equalization in EP mode
8601 …[DEBUG_BIT]: Disables Preset and coefficient rule check error in phase 2 of equalization in RC mode
8607 … [DEBUG_BIT]: EP mode Phase2: Disables the coefficient match reject status in EVAL and Adjust eval…
8609 … [DEBUG_BIT]: RC mode Phase3: Disables the coefficient match reject status in EVAL and Adjust eval…
8611 …<<26) // [DEBUG_BIT]: RC mode : Forces Gen3 equalization for every Speed change over from Gen1-Gen3
8613 … (0x1f<<27) // [DEBUG_BITS]: Equalization static debug 5-bit address control f…
8615 … DataWidth:0x20 // Notes: There are more Gen3 framing error enable bits in reg_phy_ctl_9 regist…
8620 …en3 framing error if an OS is detected without a preceding EDS token while in middle of a data str…
8622 …en this bit is set to '1', report Gen3 framing error if bad framing CRC is detected in a STP token.
8624 …this bit is set to '1', report Gen3 framing error if bad framing parity is detected in a STP token.
8633 …erwise, hardware automatically clears this bit when the operation is done. In case the loopback op…
8637 … Compliance Receive. If this bit is set to '1', the Compliance Receive bit in TS1 is set to '1' wh…
8639 … bit is set to '1', hardware automatically sets the Compliance Receive bit in TS1 to '1' during Lo…
8641 … state and this bit is set to '1', hardware applies the settings specified in lpbk_master_slave_se…
8645 … (0x1<<6) // Loopback Master One Skip Ordered Set. PCIE Spec requires that in Gen3 loopback master…
8653 …operation in milliseconds. When it is set to '0', software has to clear the lpbk_master_ena bit to…
8656 …in Loopback.Entry state, if Compliance Receive bit was not set in transmitting TS1 and Loopback Ma…
8661 …he Slave's TX settings that Loopback Master will transmit in TS1 during Loopback.Entry state in fo…
8662 … (0x7<<0) // Loopback Master TS1 Receiver Preset Hint. This value is sent in TS1, byte6[2:0] if c…
8664 … (0xf<<3) // Loopback Master TS1 Transmitter Preset. This value is sent in TS1, byte6[6:3] if t…
8666 … (0x1<<7) // Loopback Master TS1 Use Preset. This value is sent in TS1, byte6[7] if the…
8668 … (0x3f<<8) // Loopback Master TS1 Pre-Cursor Coefficient. This value is sent in …
8670 … (0x3f<<14) // Loopback Master TS1 Cursor Coefficient. This value is sent in TS1, byte8[5:0] if t…
8672 … (0x3f<<20) // Loopback Master TS1 Post-cursor Coefficient. This value is sent in …
8674 … (0x1<<26) // Loopback Master TS1 Selectable De-emphasis. This value is sent in TS1, …
8676 …ataWidth:0x20 // This register specifies the Loopback Master TX settings in following cases: 1. …
8677 …f<<0) // Loopback Master Gen3 TX Deemphasis. This TX setting is used when loopback is in Gen3 rate.
8679 …This TX setting is used when loopback is in Gen2 rate. Notes that for Gen1 the TX deemphasis is al…
8684 …w_ltssm_ena is reset to '0'. This feature allows software to control LTSSM in some certain states …
8686 …_topst and sw_ltssm_subst. If software is in control, the new state will be applied to LTSSM. This…
8692 …-level State. This field specifies the state of the sub-level state machine that software wants LT…
8696 … (0x1ff<<20) // Software LTSSM Top-level State. This field specifies the state of th…
8700 …nternal software LTSSM enable that is set to '1' only when S/W is actually in control of the LTSSM…
8703 …in both RX and TX direction, the number of detected errors etc. When this bit is reset to '0', the…
8707 …tion time in microseconds. When it is set to '0', software has to clear the pcie_statis_ena bit to…
8741 …SM Statistic Readback Address. ltssm_statis_0 to ltssm_statis_N are stored in FIFOs. This field in…
8744 …/ Equalization Phase 1 Time. This field contains the time that LTSSM spent in Equalization Phase 1…
8746 …/ Equalization Phase 0 Time. This field contains the time that LTSSM spent in Equalization Phase 0…
8749 …/ Equalization Phase 3 Time. This field contains the time that LTSSM spent in Equalization Phase 3…
8751 …/ Equalization Phase 2 Time. This field contains the time that LTSSM spent in Equalization Phase 2…
8758 …16) // Electrical Idle Time. This field contains the time that LTSSM spent in Electrical Idle stat…
8761 …0xffff<<0) // Recovery Time. This field contains the time that LTSSM spent in Recovery state. The …
8775 … (0x7f<<8) // For lane 13 in a multi-lane system: The…
8777 … (0x1<<15) // For lane 13 in a multi-lane system: Set…
8783 … (0x7f<<24) // For lane 15 in a multi-lane system: The…
8785 … (0x1<<31) // For lane 15 in a multi-lane system: Set…
8792 … (0x7f<<8) // For lane 9 in a multi-lane system: The…
8794 … (0x1<<15) // For lane 9 in a multi-lane system: Set…
8800 … (0x7f<<24) // For lane 11 in a multi-lane system: The…
8802 … (0x1<<31) // For lane 11 in a multi-lane system: Set…
8809 … (0x7f<<8) // For lane 5 in a multi-lane system: The…
8811 … (0x1<<15) // For lane 5 in a multi-lane system: Set…
8817 … (0x7f<<24) // For lane 7 in a multi-lane system: The…
8819 … (0x1<<31) // For lane 7 in a multi-lane system: Set…
8826 … (0x7f<<8) // For lane 1 in a multi-lane system: The…
8828 … (0x1<<15) // For lane 1 in a multi-lane system: Set…
8834 … (0x7f<<24) // For lane 3 in a multi-lane system: The…
8836 … (0x1<<31) // For lane 3 in a multi-lane system: Set…
8839 …cking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8841 …the received Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8843 …in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/…
8845 … 13 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compl…
8847 …cking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8849 …the received Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8851 …in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/…
8853 … 15 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compl…
8856 …cking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8858 …the received Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8860 …in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/…
8862 …e 9 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compl…
8864 …cking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8866 …the received Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8868 …in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/…
8870 … 11 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compl…
8873 …cking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8875 …the received Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8877 …in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/…
8879 …e 5 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compl…
8881 …cking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8883 …the received Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8885 …in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/…
8887 …e 7 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compl…
8890 …cking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8892 …the received Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8894 …in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/…
8896 …e 1 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compl…
8898 …cking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8900 …the received Modified Compliance Pattern. This is sent to the link partner in the Modified Complia…
8902 …in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/…
8904 …e 3 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compl…
8939 … (0xff<<0) // Gen2 Debug History - current. Changes are…
8957 … (0xff<<0) // Recovery History - current. Changes are…
8966 … (0xff<<0) // LTSSM state 12 transitions in the past
8968 … (0xff<<8) // LTSSM state 13 transitions in the past (see encodi…
8970 … (0xff<<16) // LTSSM state 14 transitions in the past (see encodi…
8972 … (0xff<<24) // LTSSM state 15 transitions in the past (see encodi…
8975 … (0xff<<0) // LTSSM state 8 transitions in the past (see encodi…
8977 … (0xff<<8) // LTSSM state 9 transitions in the past (see encodi…
8979 … (0xff<<16) // LTSSM state 10 transitions in the past (see encodi…
8981 … (0xff<<24) // LTSSM state 11 transitions in the past (see encodi…
8984 … (0xff<<0) // LTSSM state 4 transitions in the past (see encodi…
8986 … (0xff<<8) // LTSSM state 5 transitions in the past (see encodi…
8988 … (0xff<<16) // LTSSM state 6 transitions in the past (see encodi…
8990 … (0xff<<24) // LTSSM state 7 transitions in the past (see encodi…
8997 … (0xff<<16) // LTSSM state 6 transitions in the past (see encodi…
8999 … (0xff<<24) // LTSSM state 3 transitions in the past (see encodi…
9015 …- not active b00101 : Waiting for L0 state b00110 : In L0, waiting for L0 at Gen2 b01001 : In L0 a…
9026 …ERR_BAD_FCRC_BB (0x1<<1) // FCRC error in the STP token
9028 …R_BAD_FP_BB (0x1<<2) // Parity error in the STP token
9032 …_SYM_BB (0x1<<4) // No valid framing symbol in the data stream
9040 …_BB (0x1<<8) // An ordered set occurred in the data stream with…
9052 …BB (0x1<<14) // Mismatch or misalignment in the sync headers
9056 …DATA_BB (0x1<<16) // Misalignment in the null/skipped data
9058 … (0x1<<17) // Too many or too few RxDataValid deassertions in 65 clocks at Gen3.
9060 … (0x1<<18) // Error when in the same symbol time Idle symbols appear i…
9066 … 0x001d38UL //Access:R DataWidth:0x20 // PHY Debug - Polling Compliance s…
9067 … 0x001d3cUL //Access:R DataWidth:0x20 // PHY Debug - Equalization signals
9180 …xf<<0) // The state of the clock PM state machine and perstb 7 transitions in the past. See encodi…
9182 …xf<<4) // The state of the clock PM state machine and perstb 6 transitions in the past. See encodi…
9184 …xf<<8) // The state of the clock PM state machine and perstb 5 transitions in the past. See encodi…
9186 …f<<12) // The state of the clock PM state machine and perstb 4 transitions in the past. See encodi…
9188 …f<<16) // The state of the clock PM state machine and perstb 3 transitions in the past. See encodi…
9190 …f<<20) // The state of the clock PM state machine and perstb 2 transitions in the past. See encodi…
9192 …xf<<24) // The state of the clock PM state machine and perstb 1 transition in the past. See encodi…
9197 …f<<0) // The state of the clock PM state machine and perstb 15 transitions in the past. See encodi…
9199 …f<<4) // The state of the clock PM state machine and perstb 14 transitions in the past. See encodi…
9201 …f<<8) // The state of the clock PM state machine and perstb 13 transitions in the past. See encodi…
9203 …<<12) // The state of the clock PM state machine and perstb 12 transitions in the past. See encodi…
9205 …<<16) // The state of the clock PM state machine and perstb 11 transitions in the past. See encodi…
9207 …<<20) // The state of the clock PM state machine and perstb 10 transitions in the past. See encodi…
9209 …f<<24) // The state of the clock PM state machine and perstb 9 transitions in the past. See encodi…
9211 …f<<28) // The state of the clock PM state machine and perstb 8 transitions in the past. See encodi…
9214 …f<<0) // The state of the clock PM state machine and perstb 23 transitions in the past. See encodi…
9216 …f<<4) // The state of the clock PM state machine and perstb 22 transitions in the past. See encodi…
9218 …f<<8) // The state of the clock PM state machine and perstb 21 transitions in the past. See encodi…
9220 …<<12) // The state of the clock PM state machine and perstb 20 transitions in the past. See encodi…
9222 …<<16) // The state of the clock PM state machine and perstb 19 transitions in the past. See encodi…
9224 …<<20) // The state of the clock PM state machine and perstb 18 transitions in the past. See encodi…
9226 …<<24) // The state of the clock PM state machine and perstb 17 transitions in the past. See encodi…
9228 …<<28) // The state of the clock PM state machine and perstb 16 transitions in the past. See encodi…
9231 …f<<0) // The state of the clock PM state machine and perstb 31 transitions in the past. See encodi…
9233 …f<<4) // The state of the clock PM state machine and perstb 30 transitions in the past. See encodi…
9235 …f<<8) // The state of the clock PM state machine and perstb 29 transitions in the past. See encodi…
9237 …<<12) // The state of the clock PM state machine and perstb 28 transitions in the past. See encodi…
9239 …<<16) // The state of the clock PM state machine and perstb 27 transitions in the past. See encodi…
9241 …<<20) // The state of the clock PM state machine and perstb 26 transitions in the past. See encodi…
9243 …<<24) // The state of the clock PM state machine and perstb 25 transitions in the past. See encodi…
9245 …<<28) // The state of the clock PM state machine and perstb 24 transitions in the past. See encodi…
9248 … (0x1<<0) // Instantaneous value of the top-level user_allow_gen3…
9253 … (0xffff<<0) // Vendor ID. For SR-IOV VFs always 0xFFFF.
9255 … (0xffff<<16) // Device ID. For SR-IOV VFs always 0xFFFF.
9258 …ENDOR_ID_K2 (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufact…
9263 …E_E5 (0x1<<0) // VF read-only zero.
9265 …E_E5 (0x1<<1) // VF read-only zero.
9267 …the SPEM()_PF()_DBG_INFO[P()_BMD_E bit. Transactions are dropped in the Client. Non-posted trans…
9281 … (0x1<<9) // Fast back-to-back transaction ena…
9283 …S_E5 (0x1<<10) // VF read-only zero.
9289 … (0x1<<19) // INTx status. Not applicable for SR-IOV. Hardwired to 0.
9295 … (0x1<<23) // Fast back-to-back capable. Not ap…
9312 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9314 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9352 …_ERR_K2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
9359 … (0xff<<8) // Read-only copy of the asso…
9361 … (0xff<<16) // Read-only copy of the asso…
9363 … (0xff<<24) // Read-only copy of the asso…
9375 … (0xff<<0) // Read-only copy of the asso…
9381 … (0x1<<23) // Read-only copy of the asso…
9400 …E_K2 (0x3<<1) // BAR0 32-bit or 64-bit.
9410 …E_K2 (0x3<<1) // BAR1 32-bit or 64-bit.
9420 …E_K2 (0x3<<1) // BAR2 32-bit or 64-bit.
9430 …E_K2 (0x3<<1) // BAR3 32-bit or 64-bit.
9440 …E_K2 (0x3<<1) // BAR4 32-bit or 64-bit.
9450 …E_K2 (0x3<<1) // BAR5 32-bit or 64-bit.
9459 … (0xffff<<0) // Read-only copy of the asso…
9461 … (0xffff<<16) // Read-only copy of the asso…
9464 …tem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9466 …tem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9469 … (0x1<<0) // Read-only copy of the asso…
9471 … (0x1fff<<19) // Read-only copy of the asso…
9477 … (0xff<<0) // Pointer to first item in the PCI Capability S…
9480 … (0xff<<0) // VF's read-only zeros.
9482 … (0xff<<8) // VF's read-only zeros.
9484 … (0xff<<16) // VF's read-only zeros.
9486 … (0xff<<24) // VF's read-only zeros.
9496 … (0xff<<8) // Next capability pointer. Points to the MSI-X capabilities by def…
9498 …_E5 (0xf<<16) // Read-only copy of the asso…
9500 … (0xf<<20) // Read-only copy of the asso…
9502 … (0x1<<24) // Read-only copy of the asso…
9504 … (0x1f<<25) // Read-only copy of the asso…
9515 …emented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9522 … (0x7<<0) // Read-only copy of the asso…
9524 … (0x3<<3) // Read-only copy of the asso…
9526 … (0x1<<5) // Read-only copy of the asso…
9528 … (0x7<<6) // Read-only copy of the asso…
9530 … (0x7<<9) // Read-only copy of the asso…
9532 … (0x1<<15) // Read-only copy of the asso…
9538 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core.
9545 …eld Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9551 …_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2 (0x1<<15) // Role-based Error Reporting…
9584 …in this register regardless of whether or not error reporting is enabled in the device control reg…
9586 …in this register regardless of whether or not error reporting is enabled in the device control reg…
9588 …in this register regardless of whether or not error reporting is enabled in the device control reg…
9590 …in this register regardless of whether or not error reporting is enabled in the device control reg…
9592 …D_E5 (0x1<<20) // VF's read-only zeros.
9599 …_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting…
9607 …icated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilit…
9609 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9611 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9615 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
9623 …STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
9634 … (0xf<<0) // Read-only copy of the asso…
9636 … (0x3f<<4) // Read-only copy of the asso…
9638 …5 (0x3<<10) // Read-only copy of the asso…
9640 … (0x7<<12) // Read-only copy of the asso…
9642 … (0x7<<15) // Read-only copy of the asso…
9644 … (0x1<<18) // Read-only copy of the asso…
9646 … (0x1<<19) // Read-only copy of the asso…
9648 …5 (0x1<<20) // Read-only copy of the asso…
9650 … (0x1<<21) // Read-only copy of the asso…
9652 … (0x1<<22) // Read-only copy of the asso…
9654 … (0xff<<24) // Read-only copy of the asso…
9657 …EED_K2 (0xf<<0) // Maximum Link Speed. In M-PCIe mode, the rese…
9659 …TH_K2 (0x3f<<4) // Maximum Link Width. In M-PCIe mode, the rese…
9663 …in the core when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DE…
9665 …in the core when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DE…
9667 …er Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9675 … ASPM Optionality Compliance. Note: The access attributes of this field are as follows: - Dbi: R
9702 …t link speed. The encoded value specifies a bit location in the supported link speeds vector (in t…
9721 …In a DSP that supports crosslink, the core gates the write value with the CROSS_LINK_EN field in P…
9723 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
9729 …e PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG. Note: The access attributes of this fi…
9733 …e PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this fi…
9735 …e PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this fi…
9743 … (0x1<<27) // LTSSM is in Configuration or Recovery State. Note: The access attributes of th…
9745 …Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9749 …e PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this fi…
9751 …e PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this fi…
9762 …2S_E5 (0x1<<7) // 32-bit AtomicOp supporte…
9764 …4S_E5 (0x1<<8) // 64-bit AtomicOp supporte…
9766 …8S_E5 (0x1<<9) // 128-bit AtomicOp supporte…
9768 … (0x1<<10) // No RO-enabled PR-PR passing. (Thi…
9776 …_CPL_SUPP_E5 (0x1<<16) // 10-bit tag completer sup…
9778 …_REQ_SUPP_E5 (0x1<<17) // 10-bit tag requestor sup…
9784 …5 (0x1<<21) // End-end TLP prefix suppor…
9786 … (0x3<<22) // Read-only copy of the asso…
9803 …O_EN_PR2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
9828 …_REQ_EN_E5 (0x1<<12) // 10-bit tag requestor ena…
9832 … (0x1<<15) // Unsupported end-end TLP prefix blocki…
9854 … (0x7f<<1) // Read-only copy of the asso…
9863 …PEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIE…
9867 …DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9870 …TLS_E5 (0xf<<0) // VF's read-only zeros.
9872 …EC_E5 (0x1<<4) // VF's read-only zeros.
9874 …HASD_E5 (0x1<<5) // VF's read-only zeros.
9876 …SDE_E5 (0x1<<6) // VF's read-only zeros.
9878 …TM_E5 (0x7<<7) // VF's read-only zeros.
9880 …MC_E5 (0x1<<10) // VF's read-only zeros.
9882 …SOS_E5 (0x1<<11) // VF's read-only zeros.
9884 …DE_E5 (0xf<<12) // VF's read-only zeros.
9886 … (0x1<<16) // Read-only copy of the asso…
9909 …RGET_LINK_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the cont…
9913 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9915 …SEL_DEEMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
9919 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9921 … transmission. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9923 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
9925 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
9942 …NTRL_MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
9946 … (0x7ff<<16) // MSI-X table size encoded as (table size - 1)…
9948 …ctors associated with the function are masked, regardless of their respective per-vector mask bits.
9950 …X_CAP_CNTRL_MSIXEN_E5 (0x1<<31) // MSI-X enable.
9952 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
9953 …NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
9955 …TRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2 (0xff<<8) // MSI-X Next Capability Poi…
9957 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
9959 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
9961 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
9964 …BIR_E5 (0x7<<0) // Read-only copy of the asso…
9966 … (0x1fffffff<<3) // Read-only copy of the asso…
9968 … 0x0000b4UL //Access:R DataWidth:0x20 // MSI-X Table Offset and BI…
9969 …_PCI_MSIX_BIR_K2 (0x7<<0) // MSI-X Table Bar Indicator…
9971 …_PCI_MSIX_TABLE_OFFSET_K2 (0x1fffffff<<3) // MSI-X Table Offset.
9974 …R_E5 (0x7<<0) // Read-only copy of the asso…
9976 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
9978 … 0x0000b8UL //Access:R DataWidth:0x20 // MSI-X PBA Offset and BIR …
9979 …OFFSET_REG_PCI_MSIX_PBA_K2 (0x7<<0) // MSI-X PBA BIR.
9981 …_PCI_MSIX_PBA_OFFSET_K2 (0x1fffffff<<3) // MSI-X PBA Offset.
9991 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9993 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9995 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10031 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10033 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10035 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10052 …taWidth:0x20 // TPH Requestor Capability Register. SRIOV Note: All VFs in a single PF have the…
10073 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
10083 … 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
10085 … 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
10132 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10134 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10138 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10140 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10154 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10156 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10160 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10162 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10170 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if RO…
10172 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if RO…
10174 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10175 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10177 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10180 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10182 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10185 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10187 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10190 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10192 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10195 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10197 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10200 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10202 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10205 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10207 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10210 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10212 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10290 …-only access of the GPRE registers. Register can be accessed only when storm is stalled. Address b…
10292 … 0x000480UL //Access:R DataWidth:0x20 // 15-0 STORM0 GPRE0 bits 15:0. 31-16 STOR…
10293 …- misc_local_mux_other_stall, 20 - ram_mux_bkpt_stall, 19 - mux_lock_stall, 18 - pram_mux_pipe_st…
10298 …ether or not the Storm is currently stalled. bit0- STORM A. bit1- STORM B. bit2- Pram Breakpoint. …
10299 … causes all the internal and external stall sources to be reset, resulting in the negation of the …
10303 …R DataWidth:0xf // This register delivers the PRAM address for the low-word instruction that…
10304 … DataWidth:0xf // This register delivers the PRAM address for the high-word instruction that…
10307 …en as a single bit , a value of 2 means that the PortID will be taken as a 2-bit field. A value of…
10308 …s:RW DataWidth:0x5 // Defines the offset (in bits) from the lsb of the CID in which to assign…
10309 …dth:0x1 // Defines the Storm register file set that is currently active. 0 - STORM A 1 - STORM B
10310 …- DRA WR STM Core_A, 3:5 - DRA WR STM Core_B, 6:8 - DRA RD STM Core_A, 9:11 - DRA RD STM Core_B, …
10313 …in internal RAM ECC error injection the next time there is a write to the internal RAM by RBC. For…
10315 …th:0x20 // This register delivers the Storm PC for read-only debug access. 15-0 - STORM A. 31-16…
10316 …in the range between the start address and the end address (which matches the access type defined …
10317 …in the range between the start address and the end address (which matches the access type defined …
10318 …in which IRAM breakpoint stall will be initiate. bit0 - stall on read access. bit1 - stall on …
10319 …er defines the IRAM address for which the data breakpoint stall was set. bits 0:15 - IRAM address.
10323 … indirect registers defines the modulus (roll-over) values for the corresponding real time clocks.…
10326 …-time clock with regard to the associated RTClkTickValue. The Storm decode assignments used for th…
10329 …-time clocks. This value is assigned to the corresponding real-time clock only when the Storm corr…
10332 …-time clock with the value provided by the associated RTClkInitValue register. The Storm decode as…
10335 …direct registers provides read access to the real time clock values. The sub-address for this indi…
10337 … per RTC used to enable each of the ten real-time clocks. The bit index corresponds with the ID of…
10338 …taWidth:0x20 // The following register assigns bits 31:0 of the CAM mask in preparation for upco…
10339 …aWidth:0x20 // The following register assigns bits 63:31 of the CAM mask in preparation for upco…
10340 …aWidth:0x4 // The following register assigns bits 67:64 of the CAM mask in preparation for upco…
10341 …aWidth:0x20 // The following register assigns bits 31:0 of the CAM value in preparation for upco…
10342 …Width:0x20 // The following register assigns bits 63:32 of the CAM value in preparation for upco…
10343 …Width:0x4 // The following register assigns bits 67:64 of the CAM value in preparation for upco…
10347 …or the most recent RBC read request issued. The valid bit is returned on bit-0 of the data. All ot…
10357 …0x20 // This array of registers returns the 128-bit CAM match vector returned in the most recent…
10360 …-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fas…
10361 …ources for modes 2 and 3 on the fast debug channel: b0-DRA write disable; b1-DRA read disable; b2-…
10362 …able any of the following debug sources for mode-4 on the fast debug channel: b0-store data disabl…
10363 …ces for mode-6 on the fast debug channel: b0-dra_in disable; b1-fin disable; b2-load disable; b3-t…
10364 …x20 // Connection id that should compared with cid field of the data (in Dra-In message); Note: …
10365 …aWidth:0x8 // Event id that should compared with event id field of the data (in Dra-In message).
10366 …075cUL //Access:RW DataWidth:0x8 // Mask for event id. 1- specified bit is ignored; 0 - speci…
10367 …e event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active stat…
10368 …e event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active stat…
10370 …- Filter off; in that case all data should be transmitted to the DBG block without any filtering i…
10372 …- use the recorded connection id field which arrives from the DBG block (dbg_sem_cid interface) fo…
10378 … (0x3<<5) // Used to define the DRA-In source that should …
10386 … 0x00076cUL //Access:RW DataWidth:0x10 // Used in conjunction with dbg…
10387 … 0x000770UL //Access:RW DataWidth:0x10 // Used in conjunction with dbg…
10388 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
10402 … (0x3<<2) // Used to define the DRA-In source that should …
10408 …x000a44UL //Access:R DataWidth:0x20 // Statistics - The accumulated number of Storm cycles in…
10409 …x000a44UL //Access:RC DataWidth:0x20 // Statistics - The accumulated number of Storm cycles in…
10411 …x000a4cUL //Access:R DataWidth:0x20 // Statistics - The accumulated number of Storm cycles in…
10412 …x000a4cUL //Access:RC DataWidth:0x20 // Statistics - The accumulated number of Storm cycles in…
10413 …- The accumulated number of Storm cycles in which the Storm has been idle due to having no threads…
10414 …- The accumulated number of Storm cycles in which the Storm has been idle due to having no threads…
10415 …x000a54UL //Access:R DataWidth:0x20 // Statistics - The accumulated number of Storm cycles in…
10416 …x000a54UL //Access:RC DataWidth:0x20 // Statistics - The accumulated number of Storm cycles in…
10417 …x000a58UL //Access:R DataWidth:0x20 // Statistics - The accumulated number of Storm cycles in…
10418 …x000a5cUL //Access:R DataWidth:0x20 // Statistics - The accumulated number of Storm cycles in…
10419 …- The accumulated number of Storm cycles in which the Storm has been idle due to having no threads…
10420 …x000a64UL //Access:R DataWidth:0x20 // Statistics - The accumulated number of Storm cycles in…
10425 …- response is ready. It is set when response cycle of 32 bit is ready from VFC block. It is reset …
10429 … 0x000c4cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
10437 …-address. Bits [3:0] of the data bus provide the OpCode for the request where the following numera…
10439 … 0x00a000UL //Access:RW DataWidth:0x20 // Provides a memory-mapped region for VFC…
10458 …it per ALU vector: 0-4 long vectors; 5-11 short vectors. When it is set then appropriate vector wi…
10461 …s to not existing address in VFC. Also it will be asserted when there is attempt to write to read …
10471 …ycle not equal 64 bit or number of data cycles bigger than 6. It will be de-asserted aftre write …
10473 …asserted when waitp is asserted and output FIFO is also full. It will be de-asserted aftre write …
10475 …asserted when it was address overflow of INFO part of RSS RAM. It will be de-asserted aftre write …
10477 …ted when it was address overflow of KEY LSB part of RSS RAM. It will be de-asserted aftre write …
10479 …erted when it was address overflow of KEY MSB part of RSS RAM. It will be de-asserted aftre write …
10482 …ty interrupt. It may be asserted when it was CAM parity error. It will be de-asserted aftre write …
10484 …pt. It may be asserted when it was parity error inside TT RAM. It will be de-asserted aftre write …
10486 …terrupt. It may be asserted when it was RSS RAM parity error. It will be de-asserted aftre write …
10534 …this bit will cause reset of all CAM rows including valid bit and all bits in a row. Write 0 to it…
10536 …at RAM reset was finished. Read 1 from this bit means that TT RAM reset is in progress. Read 0 fro…
10538 … 0 to it will have no effect. Read 1 from this bit means that RAM reset is in progress. Read 0 fro…
10540 …-If this bit is set then background mechanism for parity check will be enabled; 0 - disabled. This…
10542 … 0x000048UL //Access:RW DataWidth:0x3 // REQUIRED - 0 - parity is enabled;…
10543 … 0x00004cUL //Access:RW DataWidth:0xa // REQUIRED - 0 - interrupt is enabled;1- interr…
10556 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
10557 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
10632 …able ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4…
10634 …ble ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_…
10636 …able ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4…
10638 …ble ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_…
10641 …ity only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4…
10643 …ty only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_…
10645 …ity only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4…
10647 …ty only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_…
10650 … occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4…
10652 …occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_…
10654 … occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4…
10656 …occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_…
10757 …an error received on the ingress interface will be masked for instructions in which the "dummy rea…
10780 …bug register. This register stores the calculated CRC value that resulted in the most recent CRC …
10781 …nstruction is the first instruction in the task. Bit 29 indicates whether the instruction is the …
10791 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
10795 … 0x002000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
10800 …_E5 (0xff<<0) // 8-bit value from packag…
10802 …E5 (0xff<<8) // 8-bit value from packag…
10816 …s with a destination address not matching the Core MAC address (programmed in registers MAC_ADDR_0…
10820 …If set to '0' (Reset value), the CRC field is stripped from the frame. Note - If padding (Bit PAD_…
10824 …t value), the transmit process is stopped for the amount of time specified in the pause quanta rec…
10826 …address received from the client interface with the MAC address programmed in registers MAC_ADDR_0…
10832 …5 (0x1<<12) // Self-Clearing Software Res…
10846 …ow Control Interface signals. If set to 0 (Reset Value), the Core operates in legacy Pause Frame m…
10860 … (0x1<<26) // Self-Clearing TX FIFO reset command. May not be suppor…
10862 …et to '0' (default), the MAC automatically inserts remote faults and idles in egress direction on …
10913 … (0x1<<5) // MDIO transaction preamble disable. Shortens transaction but is non-standard.
10924 … If written with 1, a read with address post-increment will be performed. Post-increment will be p…
10929 …-bit data word. When written- Initiates a write transaction to the PHY. The MDIO_COMMAND register …
10931 …PHY device to read from or write to. After writing this register, an address-write transaction wil…
10939 … (0x1<<2) // PHY indicates loss-of-signal. Represents v…
10941 …s that the timestamp of the last transmitted 1588 event frame is available in the register TS_TIME…
10949 … (0x1<<7) // Special Link Interruption Fault Sequence detected in receive
10954 … (0x7f<<0) // Number of octets in steps of 4 (XGMII) o…
10959 …E5 (0x1<<0) // Credit-based FIFO only: When…
10962 …5 (0xff<<0) // Credit-based FIFO only: Spec…
10970 …C quanta value for that class when a class XOFF is triggered. Each Quanta specifies a 512 bit-time.
11012 … (0x1<<0) // Enable XGMII-64 (4byte alignment)
11016 … (0x1<<5) // Enable 1-step capable datapath…
11019 …/ Configure saturation behavior. When set to 1, the counters saturate at all-1. Otherwise counters…
11021 … (0x1<<1) // Configure clear-on-read behavior. When …
11023 … (0x1<<2) // Clear all counters command (self-clearing). When writt…
11167 …_K2_E5 (0xf<<8) // RS-FEC receive lane lock…
11169 … (0x1<<14) // Indicates, when 1 that the RS-FEC receiver has lock…
11173 …x20 // Counts number of corrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11174 …umber of corrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11176 …h:0x20 // Counts number of corrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11177 … (0xffff<<0) // Counts number of corrected FEC codewords upper 16-bits; None roll-over; Clears …
11179 …0 // Counts number of uncorrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11180 …ber of uncorrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11182 …0x20 // Counts number of uncorrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11183 … (0xffff<<0) // Counts number of uncorrected FEC codewords upper 16-bits; None roll-over; Clears …
11194 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 0; None roll-over whe…
11195 … (corrected) 10-bit symbol errors found in lane 0 for correctable codewords only; Lower 16-bit of …
11197 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11198 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 0; Clears o…
11200 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 1; None roll-over whe…
11201 … (corrected) 10-bit symbol errors found in lane 1 for correctable codewords only; Lower 16-bit of …
11203 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11204 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 1; Clears o…
11206 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 2; None roll-over whe…
11207 … (corrected) 10-bit symbol errors found in lane 2 for correctable codewords only; Lower 16-bit of …
11209 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11210 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 2; Clears o…
11212 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 3; None roll-over whe…
11213 … (corrected) 10-bit symbol errors found in lane 3 for correctable codewords only; Lower 16-bit of …
11215 … DataWidth:0x20 // Upper 16 bit of counter (with above register); Clears on read; None roll-over.
11216 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 3; Clears o…
11218 … 0x000200UL //Access:RW DataWidth:0x20 // Additional control to enable RS-FEC operation.
11240 …_EMPTY_K2_E5 (0xf<<12) // Real-time indication from …
11248 …W DataWidth:0x20 // Bits 7:0; Must be written with the 8-bit value of 0x57 to enable RS-FEC tr…
11249 … (0xff<<0) // Bits 7:0; Must be written with 8-bit value 0x57 to enable RS-FEC tra…
11251 … 0x000214UL //Access:RW DataWidth:0x20 // Bits 15:0. One bit per 10-bit Symbol; Each bit …
11252 … (0xffff<<0) // Bits 15:0. One bit per 10-bit Symbol; When a bi…
11254 … 0x000218UL //Access:RW DataWidth:0x20 // Bits 9:0; A 10-bit value which XORed…
11255 …N_TEST_PATTERN_K2_E5 (0x3ff<<0) // A 10-bit value which will …
11265 … (0x1<<8) // Indicate full-duplex operation; alw…
11279 … (0x1<<15) // PCS soft-reset command; self-clearing
11284 … (0x1<<2) // Indicate link status; latch-low
11296 …x20 // Local Device Abilities for Autonegotiation. Contents differs for 1000Base-X or SGMII mode.
11299 … (0x1<<5) // Indicate full-duplex support; SGMII…
11301 … (0x1<<6) // Indicate half-duplex support; SGMII…
11317 …/ Received Abilities during Autonegotiation. Contents differ depending on 1000Base-X or SGMII mode.
11320 … (0x1<<5) // Indicate full-duplex support; SGMII…
11322 … (0x1<<6) // Indicate half-duplex support; SGMII…
11341 … (0x1<<1) // Autoneg page received indication; latch-high
11392 … (0x1<<4) // Set SGMII half-duplex mode when not …
11396 … DataWidth:0x20 // 10B decoder error counter for test/debug; May not exist in all Core Variants;
11397 … (0xffff<<0) // RX 10B/8B code errors; May not be supported in all Core variants; C…
11419 … (0x1<<8) // 1: receive is currently in LPI state; 0: norma…
11421 … (0x1<<9) // 1: transmit is currently in LPI state; 0: norma…
11423 … (0x1<<10) // 1: receive is or was in LPI state; 0: norma…
11425 … (0x1<<11) // 1: transmit is or was in LPI state; 0: norma…
11428 …ffff<<0) // Bits 15:0 of Device Identifier defined by parameter PHY_IDENTIFIER in PCS package file.
11431 …fff<<0) // Bits 31:16 of Device Identifier defined by parameter PHY_IDENTIFIER in PCS package file.
11436 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
11468 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11470 … (0x1<<1) // When 1, this PCS is 10GBase-X capable.
11472 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11474 … (0x1<<3) // When 1, this PCS is 10GBase-T capable.
11476 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11478 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11495 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11497 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11499 … (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
11502 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11512 … (0xff<<0) // Errored blocks counter; None roll-over.
11514 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11520 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11521 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11523 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11524 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11526 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11527 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11529 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11530 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11532 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11533 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11535 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11536 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11538 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11539 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11541 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11542 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11549 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11551 …ESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enable.
11555 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11556 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11558 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11559 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11561 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11562 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11586 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11587 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11589 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11590 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11592 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11593 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11595 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11596 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11614 … (0xffff<<0) // Core Design version as defined by DEV_VERSION parameter in PCS package file.
11616 …x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
11617 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dis…
11620 …_THRESHOLD_K2_E5 (0xf<<0) // A 4-bit value to define t…
11622 …0010UL //Access:RW DataWidth:0x20 // Vendor Specific Reg; Define Reduced-XLAUI PMA mode using …
11623 …_K2_E5 (0x1<<0) // Enable Reduced-XLAUI PMA mode using …
11668 …2_E5 (0x1<<1) // When 0 PCS 4-lane MLD function is …
11694 … (0x1<<8) // 1: receive is currently in LPI state; 0: normal…
11696 … (0x1<<9) // 1: transmit is currently in LPI state; 0: normal…
11698 … (0x1<<10) // 1: receive is or was in LPI state; 0: normal…
11700 … (0x1<<11) // 1: transmit is or was in LPI state; 0: normal…
11703 …ffff<<0) // Bits 15:0 of Device Identifier defined by parameter PHY_IDENTIFIER in PCS package file.
11706 …fff<<0) // Bits 31:16 of Device Identifier defined by parameter PHY_IDENTIFIER in PCS package file.
11711 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
11743 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11745 … (0x1<<1) // When 1, this PCS is 10GBase-X capable.
11747 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11749 … (0x1<<3) // When 1, this PCS is 10GBase-T capable.
11751 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11753 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11770 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11772 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11774 … (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
11777 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11787 … (0xff<<0) // Errored blocks counter; None roll-over.
11789 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11795 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11796 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11798 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11799 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11801 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11802 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11804 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11805 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11807 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11808 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11810 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11811 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11813 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11814 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11816 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11817 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11824 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11826 …ESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enable.
11830 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11831 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11833 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11834 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11836 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11837 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11853 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11854 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11856 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11857 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11859 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11860 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11862 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11863 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11869 … (0xffff<<0) // Core Design version as defined by DEV_VERSION parameter in PCS package file.
11871 …x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
11872 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dis…
11875 …_THRESHOLD_K2_E5 (0xf<<0) // A 4-bit value to define t…
11912 …2_E5 (0x1<<1) // When 0 PCS 4-lane MLD function is …
11962 …- off high-impedance 0x1 - CMU 0 0x3 - Lane 0 0x4 - Lane 1 0x5 - Lane 2 0x6 - Lane 3 0x15 - SoC ci…
11965 …1_o/atest2_o bumps located over the CMU macro. Decoding table is provided in separate documentati…
12362 …x0 - no error 0x1 - PHY has an internal error detected by firmware. PHY error code can be used to …
12364 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12365 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12370 … (0x1<<0) // Clear the debug info presented in REGBUS_ERR_INFO_STAT…
12383 …ess:RW DataWidth:0x8 // lower 8-bits of the 16-bit digital test bus tbus address. Decoding ta…
12384 …ss:RW DataWidth:0x8 // higher 8-bits of the 16-bit digital test bus tbus address. Decoding ta…
14398 …s clock can be used in gearbox applications. 0x0 - DIV4 0x1 - DIV8 0x2 - DIV16 0x3 - DIV20 0x4 - …
14429 …to the half-rate TX clock path to provide visibility at the TX driver output. 0x0 - mission mode …
14431 …CMU macro to all lanes macros. 0x0 - DIV1 0x1 - DIV2 0x2 - DIV4 0x3 - DIV5 0x4 - DIV8 0x5 - DIV10…
14473 … (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indica…
14477 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14478 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14480 … (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro…
14515 … (0x1<<0) // CMU PLL regulator vddha setting. 0x0 - vddha is 1.5V nominal 0x1 - vddha …
14670 … (0x1<<0) // CMU PLL lock detector status. 0x0 - CMU PLL is not locked 0x1 - CMU PL…
14910 … (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indica…
14914 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14915 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14917 … (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro…
14940 …L2_FRACN_N_K2_E5 (0x1<<0) // Resets the DivN counter in the FracN
14950 … (0x1<<0) // Select the reference clock. 0 - clk_ref 1- clk_pllref
15081 … 0x003524UL //Access:RW DataWidth:0x8 // Sets maximum spreading frequency in SSC mode.
15082 … 0x003528UL //Access:RW DataWidth:0x8 // Sets maximum spreading frequency in SSC mode.
15084 …2_E5 (0xf<<0) // Sets maximum spreading frequency in SSC mode.
15086 … 0x003530UL //Access:RW DataWidth:0x8 // Increment value in SSC mode;Enabled whe…
15087 … 0x003534UL //Access:RW DataWidth:0x8 // Increment value in SSC mode;Enabled whe…
15089 … (0x1<<0) // Enable for both Upspreading and Downspreading in SSC mode
15095 … 0x00353cUL //Access:RW DataWidth:0x8 // Used as frequency offset in SSC when ssc_gen_en=…
15096 … 0x003540UL //Access:RW DataWidth:0x8 // Used as frequency offset in SSC when ssc_gen_en=…
15098 … (0xf<<0) // Used as frequency offset in SSC when ssc_gen_en=…
15204 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
15206 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
15208 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
15210 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
15284 … (0x1<<0) // Enables register control of TX data path mux in DPL
15286 …in DPL. The corresponding mux select override enable must also be set. 0 : TX data from customer …
15290 … (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode. In FED…
15293 … (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-E…
15295 … (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits…
15334 … (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
15336 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
15418 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15419 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15421 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
15488 … 0x0062fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
15490 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
15497 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
15502 … 0x006314UL //Access:R DataWidth:0x8 // Value of the accumulator in the CDR integral path
15503 … 0x006318UL //Access:R DataWidth:0x8 // Value of the accumulator in the CDR integral path
15505 …6_K2_E5 (0xf<<0) // Value of the accumulator in the CDR integral path
15655 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
15658 … (0x1<<0) // Restarts AN that is already in progress or otherwis…
15673 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
15677 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
15681 … (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
15686 … (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK…
15696 … 0x006650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
15697 … 0x006654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
15701 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
15704 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
15717 … (0x1f<<0) // Transmitted Nonce Field. It is generated in hardware.
15720 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
15722 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
15724 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
15726 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
15728 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
15730 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
15732 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
15734 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
15737 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
15739 …<<1) // 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For …
15741 …1<<2) // 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For p…
15743 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
15746 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
15753 …t F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior v…
15755 …C-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE …
15758 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15760 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
15762 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15764 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
15766 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15768 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15770 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15772 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15825 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
15828 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
15846 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
15848 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
15850 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
15852 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
15854 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
15856 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
15858 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
15860 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
15863 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
15865 …partner 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For …
15867 … partner 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For p…
15869 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
15872 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
15879 …t F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior v…
15881 …C-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE …
15884 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15886 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
15888 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15890 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
15892 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15894 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15896 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15898 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15949 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
15951 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
15953 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
15955 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
15957 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
15959 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
15961 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
15963 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
15966 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
15968 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
15970 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
15972 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
15974 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
15976 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
15978 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
15981 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
15994 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
15996 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
15998 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
16000 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
16002 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
16004 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
16006 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
16008 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
16011 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
16013 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
16015 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
16017 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
16019 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
16021 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
16564 … (0x3<<0) // When HIGH, TX driver goes into a low power IDLE model. In this mode, the outpu…
16627 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
16633 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
16744 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
16777 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
16779 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
16781 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
16783 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
16785 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16787 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16789 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16791 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
17203 …2_E5 (0x1<<0) // Enables the run-length detection digi…
17205 … 0x007410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
17207 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
17209 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
17289 … (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
17380 … 0x00781cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17381 … 0x007820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17416 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
17439 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17440 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17441 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17442 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17444 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
17590 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
17592 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
17665 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
17717 … 0x007ce4UL //Access:RW DataWidth:0x8 // How often in ms to run continuous…
17718 … 0x007ce8UL //Access:RW DataWidth:0x8 // How often in ms to run continuous…
17719 … 0x007cecUL //Access:RW DataWidth:0x8 // How often in ms to run continuous…
17792 … (0x1<<1) // Output from LTSM indicating that link training is in progress. This is a…
17794 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
17801 …nitial PRBS LFSR seed. This needs to be set according to the requirements in 802.3 CL72 or CL93 d…
17806 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
17810 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
17817 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
17821 …E5 (0x3<<4) // Status report field for pre-cursor tap.
17843 …Access:RW DataWidth:0x8 // Maximum number of PRBS bit errors allowed in single LT frame for …
17847 … (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
17849 … 0x007f18UL //Access:R DataWidth:0x8 // Number of bit errors in PRBS pattern since l…
17864 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
17868 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
17875 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
17879 … (0x3<<4) // Received status report field for pre-cursor tap.
17886 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
17888 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
17890 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
17892 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
17966 … (0x1<<0) // Enables register control of TX data path mux in DPL
17968 …in DPL. The corresponding mux select override enable must also be set. 0 : TX data from customer …
17972 … (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode. In FED…
17975 … (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-E…
17977 … (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits…
18016 … (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
18018 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
18100 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18101 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18103 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
18170 … 0x0082fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
18172 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
18179 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
18184 … 0x008314UL //Access:R DataWidth:0x8 // Value of the accumulator in the CDR integral path
18185 … 0x008318UL //Access:R DataWidth:0x8 // Value of the accumulator in the CDR integral path
18187 …6_K2_E5 (0xf<<0) // Value of the accumulator in the CDR integral path
18337 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
18340 … (0x1<<0) // Restarts AN that is already in progress or otherwis…
18355 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
18359 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
18363 … (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
18368 … (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK…
18378 … 0x008650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
18379 … 0x008654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
18383 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
18386 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
18399 … (0x1f<<0) // Transmitted Nonce Field. It is generated in hardware.
18402 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
18404 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
18406 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
18408 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
18410 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
18412 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
18414 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
18416 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
18419 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
18421 …<<1) // 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For …
18423 …1<<2) // 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For p…
18425 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
18428 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
18435 …t F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior v…
18437 …C-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE …
18440 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18442 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
18444 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18446 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
18448 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18450 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18452 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18454 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
18507 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
18510 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
18528 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
18530 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
18532 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
18534 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
18536 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
18538 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
18540 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
18542 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
18545 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
18547 …partner 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For …
18549 … partner 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For p…
18551 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
18554 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
18561 …t F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior v…
18563 …C-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE …
18566 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18568 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
18570 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18572 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
18574 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18576 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18578 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18580 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
18631 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
18633 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
18635 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
18637 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
18639 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
18641 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
18643 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
18645 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
18648 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
18650 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
18652 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
18654 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
18656 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
18658 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
18660 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
18663 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
18676 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
18678 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
18680 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
18682 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
18684 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
18686 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
18688 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
18690 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
18693 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
18695 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
18697 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
18699 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
18701 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
18703 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
19246 … (0x3<<0) // When HIGH, TX driver goes into a low power IDLE model. In this mode, the outpu…
19309 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
19315 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
19426 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
19459 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
19461 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
19463 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
19465 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
19467 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19469 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19471 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19473 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19885 …2_E5 (0x1<<0) // Enables the run-length detection digi…
19887 … 0x009410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
19889 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
19891 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
19971 … (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
20062 … 0x00981cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20063 … 0x009820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20098 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
20121 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20122 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20123 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20124 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20126 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
20272 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
20274 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
20347 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
20399 … 0x009ce4UL //Access:RW DataWidth:0x8 // How often in ms to run continuous…
20400 … 0x009ce8UL //Access:RW DataWidth:0x8 // How often in ms to run continuous…
20401 … 0x009cecUL //Access:RW DataWidth:0x8 // How often in ms to run continuous…
20474 … (0x1<<1) // Output from LTSM indicating that link training is in progress. This is a…
20476 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
20483 …nitial PRBS LFSR seed. This needs to be set according to the requirements in 802.3 CL72 or CL93 d…
20488 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
20492 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
20499 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
20503 …E5 (0x3<<4) // Status report field for pre-cursor tap.
20525 …Access:RW DataWidth:0x8 // Maximum number of PRBS bit errors allowed in single LT frame for …
20529 … (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
20531 … 0x009f18UL //Access:R DataWidth:0x8 // Number of bit errors in PRBS pattern since l…
20546 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
20550 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
20557 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
20561 … (0x3<<4) // Received status report field for pre-cursor tap.
20568 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
20570 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
20572 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
20574 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
20648 … (0x1<<0) // Enables register control of TX data path mux in DPL
20650 …in DPL. The corresponding mux select override enable must also be set. 0 : TX data from customer …
20654 … (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode. In FED…
20657 … (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-E…
20659 … (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits…
20698 … (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
20700 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
20782 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20783 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20785 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
20852 … 0x00a2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
20854 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
20861 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
20866 … 0x00a314UL //Access:R DataWidth:0x8 // Value of the accumulator in the CDR integral path
20867 … 0x00a318UL //Access:R DataWidth:0x8 // Value of the accumulator in the CDR integral path
20869 …6_K2_E5 (0xf<<0) // Value of the accumulator in the CDR integral path
21019 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
21022 … (0x1<<0) // Restarts AN that is already in progress or otherwis…
21037 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
21041 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
21045 … (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
21050 … (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK…
21060 … 0x00a650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
21061 … 0x00a654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
21065 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
21068 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
21081 … (0x1f<<0) // Transmitted Nonce Field. It is generated in hardware.
21084 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
21086 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
21088 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
21090 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
21092 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
21094 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
21096 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
21098 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
21101 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
21103 …<<1) // 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For …
21105 …1<<2) // 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For p…
21107 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
21110 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
21117 …t F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior v…
21119 …C-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE …
21122 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21124 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
21126 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21128 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
21130 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21132 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
21134 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21136 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
21189 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
21192 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
21210 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
21212 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
21214 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
21216 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
21218 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
21220 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
21222 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
21224 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
21227 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
21229 …partner 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For …
21231 … partner 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For p…
21233 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
21236 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
21243 …t F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior v…
21245 …C-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE …
21248 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21250 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
21252 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21254 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
21256 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21258 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
21260 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21262 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
21313 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
21315 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
21317 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
21319 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
21321 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
21323 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
21325 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
21327 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
21330 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
21332 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
21334 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
21336 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
21338 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
21340 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
21342 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
21345 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
21358 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
21360 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
21362 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
21364 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
21366 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
21368 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
21370 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
21372 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
21375 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
21377 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
21379 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
21381 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
21383 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
21385 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
21928 … (0x3<<0) // When HIGH, TX driver goes into a low power IDLE model. In this mode, the outpu…
21991 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
21997 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
22108 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
22141 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
22143 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
22145 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
22147 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
22149 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22151 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22153 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22155 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22567 …2_E5 (0x1<<0) // Enables the run-length detection digi…
22569 … 0x00b410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
22571 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
22573 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
22653 … (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
22744 … 0x00b81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22745 … 0x00b820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22780 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
22803 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22804 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22805 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22806 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22808 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
22954 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
22956 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
23029 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
23081 … 0x00bce4UL //Access:RW DataWidth:0x8 // How often in ms to run continuous…
23082 … 0x00bce8UL //Access:RW DataWidth:0x8 // How often in ms to run continuous…
23083 … 0x00bcecUL //Access:RW DataWidth:0x8 // How often in ms to run continuous…
23156 … (0x1<<1) // Output from LTSM indicating that link training is in progress. This is a…
23158 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
23165 …nitial PRBS LFSR seed. This needs to be set according to the requirements in 802.3 CL72 or CL93 d…
23170 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
23174 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
23181 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
23185 …E5 (0x3<<4) // Status report field for pre-cursor tap.
23207 …Access:RW DataWidth:0x8 // Maximum number of PRBS bit errors allowed in single LT frame for …
23211 … (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
23213 … 0x00bf18UL //Access:R DataWidth:0x8 // Number of bit errors in PRBS pattern since l…
23228 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
23232 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
23239 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
23243 … (0x3<<4) // Received status report field for pre-cursor tap.
23250 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
23252 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
23254 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
23256 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
23330 … (0x1<<0) // Enables register control of TX data path mux in DPL
23332 …in DPL. The corresponding mux select override enable must also be set. 0 : TX data from customer …
23336 … (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode. In FED…
23339 … (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-E…
23341 … (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits…
23380 … (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
23382 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
23464 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23465 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23467 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
23534 … 0x00c2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
23536 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
23543 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
23548 … 0x00c314UL //Access:R DataWidth:0x8 // Value of the accumulator in the CDR integral path
23549 … 0x00c318UL //Access:R DataWidth:0x8 // Value of the accumulator in the CDR integral path
23551 …6_K2_E5 (0xf<<0) // Value of the accumulator in the CDR integral path
23701 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
23704 … (0x1<<0) // Restarts AN that is already in progress or otherwis…
23719 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
23723 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
23727 … (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
23732 … (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK…
23742 … 0x00c650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
23743 … 0x00c654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
23747 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
23750 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
23763 … (0x1f<<0) // Transmitted Nonce Field. It is generated in hardware.
23766 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
23768 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
23770 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
23772 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
23774 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
23776 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
23778 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
23780 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
23783 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
23785 …<<1) // 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For …
23787 …1<<2) // 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For p…
23789 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
23792 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
23799 …t F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior v…
23801 …C-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE …
23804 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23806 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
23808 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23810 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
23812 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23814 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
23816 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23818 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
23871 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
23874 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
23892 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
23894 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
23896 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
23898 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
23900 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
23902 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
23904 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
23906 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
23909 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
23911 …partner 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For …
23913 … partner 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For p…
23915 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
23918 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
23925 …t F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior v…
23927 …C-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE …
23930 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23932 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
23934 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23936 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
23938 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23940 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
23942 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23944 … be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
23995 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
23997 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
23999 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
24001 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
24003 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
24005 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
24007 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
24009 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
24012 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
24014 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
24016 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
24018 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
24020 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
24022 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
24024 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
24027 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
24040 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
24042 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
24044 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
24046 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
24048 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
24050 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
24052 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
24054 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
24057 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
24059 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
24061 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
24063 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
24065 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
24067 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
24610 … (0x3<<0) // When HIGH, TX driver goes into a low power IDLE model. In this mode, the outpu…
24673 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
24679 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
24790 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
24823 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
24825 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
24827 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
24829 …nd executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set t…
24831 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24833 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24835 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24837 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
25249 …2_E5 (0x1<<0) // Enables the run-length detection digi…
25251 … 0x00d410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
25253 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
25255 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
25335 … (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
25426 … 0x00d81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25427 … 0x00d820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25462 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
25485 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25486 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25487 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25488 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25490 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
25636 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
25638 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
25711 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
25763 … 0x00dce4UL //Access:RW DataWidth:0x8 // How often in ms to run continuous…
25764 … 0x00dce8UL //Access:RW DataWidth:0x8 // How often in ms to run continuous…
25765 … 0x00dcecUL //Access:RW DataWidth:0x8 // How often in ms to run continuous…
25838 … (0x1<<1) // Output from LTSM indicating that link training is in progress. This is a…
25840 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
25847 …nitial PRBS LFSR seed. This needs to be set according to the requirements in 802.3 CL72 or CL93 d…
25852 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
25856 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
25863 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
25867 …E5 (0x3<<4) // Status report field for pre-cursor tap.
25889 …Access:RW DataWidth:0x8 // Maximum number of PRBS bit errors allowed in single LT frame for …
25893 … (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
25895 … 0x00df18UL //Access:R DataWidth:0x8 // Number of bit errors in PRBS pattern since l…
25910 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
25914 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
25921 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
25925 … (0x3<<4) // Received status report field for pre-cursor tap.
25937 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
25948 …<<3) // Selects one lane's recovered byte clock of all existing lanes, which goes to refclk buffer.
25950 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
25953 …AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
25965 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25966 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25967 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25969 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25971 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
25972 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
25973 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
25974 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
25975 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
25976 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
25977 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
25978 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
25979 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
25980 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
25981 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
25982 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
25983 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
25984 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
25985 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
25986 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
26004 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
26006 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
26008 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
26010 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26013 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
26015 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26017 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26019 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
26022 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26024 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26026 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26028 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26031 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
26033 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26035 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26037 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
26040 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
26042 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26044 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26096 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
26104 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
26138 …2_E5 (0x1<<2) // Override enable for overriding N-div value
26157 …1_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
26189 …UL //Access:RW DataWidth:0x8 // Frequency offset control word for SSC in synth mode or SSC_GE…
26190 …UL //Access:RW DataWidth:0x8 // Frequency offset control word for SSC in synth mode or SSC_GE…
26192 … (0xf<<0) // Frequency offset control word for SSC in synth mode or SSC_GE…
26198 …of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
26199 …of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
26201 …of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
26207 … (0x1<<6) // Enable in SSC_GEN mode for upwards and downwards spreading. 0- down…
26209 …/Access:RW DataWidth:0x8 // In Spread Spectrum Generation mode, represents the magnitude of t…
26210 …/Access:RW DataWidth:0x8 // In Spread Spectrum Generation mode, represents the magnitude of t…
26214 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
26216 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
26229 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
26231 …P_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
26234 …_CM_REFCLK_TERM_OVR_O_K2_E5 (0x1f<<0) // Refclk Termination overri…
26236 …A_CM_REFCLK_TERM_OVR_EN_O_K2_E5 (0x1<<5) // Refclk Termination overri…
26243 … 0x0001f0UL //Access:RW DataWidth:0x8 // In txterm calibration, the number refclk c…
26245 …_UP_8_K2_E5 (0x1<<0) // In txterm calibration, the number refclk c…
26247 …_SAMPLE_K2_E5 (0x7<<1) // in txterm calibration, the number refclk c…
26249 …AHB_RX_TC_UP_NUM_SAMPLES_K2_E5 (0xf<<4) // in txterm calibration, …
26259 … pcs_rate_o[1] : 0: PMA operates in 10b/20b mode Enables %5 circuit 1: PMA oper…
26263 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
26271 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
26273 …BUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
26287 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
26523 … 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b010 - pma_lX_rxb_iRecovered byte clock 3'b011 - ck_soc1_int…
26525 … (0x1<<3) // Clock divider for TX path branch 1 : 0-No division, 1- Divide by 2
26527 …h branch 2 clock : 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b011 - ck_soc1_int_root 3'b010,3'b100,3'b1…
26529 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
26532 …ck : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b0…
26534 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
26536 …ck : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b0…
26538 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
26541 …- qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmi…
26543 … (0x1<<3) // Clock divider for RX path branch 3 : 0-No division, 1- Divide by 2
26545 …- qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmi…
26547 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
26550 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
26552 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
26555 …0_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
26560 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
26562 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
26567 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
26569 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
26575 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
26577 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
26582 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
26584 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
26586 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26587 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26588 … 0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
26589 … 0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
26590 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
26592 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
26599 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
26607 …040UL //Access:RW DataWidth:0x8 // Bist checker preamble word 0. When in 8b mode, and prior t…
26609 … (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior t…
26619 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
26620 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26621 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26622 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26623 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26631 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
26632 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
26633 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
26634 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
26635 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
26636 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
26637 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
26638 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
26639 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
26640 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
26641 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
26642 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
26643 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
26644 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
26645 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
26646 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
26647 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
26648 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
26649 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
26650 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
26655 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
26657 …E5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
26659 …_K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
26667 …libration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfs…
26679 …asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_…
26680 …asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_…
26691 …dle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
26695 …dle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
26705 … 0x001118UL //Access:RW DataWidth:0x8 // CDR control block cycle length When not in PCIe Gen3.
26712 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
26714 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
26716 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
26720 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26721 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26722 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26724 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26726 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
26776 …_O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
26778 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler…
26783 …_O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
26810 … (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler …
26828 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
26830 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
26836 …_PMA_LN_EYE_ENA270_O_K2_E5 (0x1<<4) // In eye diagram generati…
26838 …_PMA_LN_EYE_ENA90_O_K2_E5 (0x1<<5) // In eye diagram generati…
26868 …T_CMP_K2_E5 (0xf<<0) // in txterm calibration, the number refclk c…
26870 …T_SAMPLE_K2_E5 (0x7<<4) // in txterm calibration, the number refclk c…
26873 …_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5 (0xf<<0) // in txterm calibration, …
26875 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
26877 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
26894 … 0x0011f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
26898 …rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They a…
26900 …s bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
26902 …s bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
26904 …s bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
26906 …s bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
26962 …_K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
26964 …K2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
27041 …is bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is logically OR'ed with the b…
27046 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
27048 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
27069 … (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables c…
27071 … (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables c…
27073 …W DataWidth:0x8 // Enables for various cdfe component during init cal in rate3 bit[0] : enabl…
27074 …ataWidth:0x8 // Enables for various cdfe component during continuos cal in rate3 bit[0] : enabl…
27075 …RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 bit[0] …
27083 …:0x8 // Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enabl…
27084 …0x8 // Enables for various cdfe component during post txeq adaptation in rate3 bit[0] : enabl…
27085 …W DataWidth:0x8 // Enables for various cdfe component during init cal in rate2 bit[0] : enabl…
27086 …ataWidth:0x8 // Enables for various cdfe component during continuos cal in rate2 bit[0] : enabl…
27087 …RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 bit[0] …
27239 …2_E5 (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
27359 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
27361 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27363 …0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
27365 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27369 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
27372 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27374 …1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
27376 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27378 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27380 …1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
27382 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27387 …0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
27389 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27407 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
27411 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
27433 … To skip cdr calibration routines for PCIe gen3. Can be used when PHY is operating in gen1,2 only.
27435 … (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2. May not be needed in real scenario.
27462 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
27464 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
27488 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
27498 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
27501 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
27503 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
27553 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
27554 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
27555 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
27556 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
27557 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
27558 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
27559 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
27560 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
27561 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
27562 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
27563 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
27564 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
27565 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
27566 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
27567 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
27568 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
27571 …nction. Varies depending on function number. Bits 15-7: Address of first command to run Bits: 6-…
27640 …MFSM state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to …
27641 …MFSM state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to …
27643 … (0x1<<0) // MSM Function IDDQ state's default value for iddq_sd in SAPIS mode
27645 … (0x1<<1) // MSM Function IDDQ state's default value for pd_dfe in SAPIS mode
27647 … (0x1<<2) // MSM Function IDDQ state's default value for pd_dfe_bias in SAPIS mode
27649 … (0x1<<3) // MSM Function IDDQ state's default value for pd_lnreg in SAPIS mode
27651 … (0x1<<4) // MSM Function IDDQ state's default value for pd_lnregh in SAPIS mode
27653 … (0x1<<5) // MSM Function IDDQ state's default value for pd_p2s in SAPIS mode
27655 … (0x1<<6) // MSM Function IDDQ state's default value for pd_ra in SAPIS mode
27657 … (0x1<<7) // MSM Function IDDQ state's default value for pd_s2p in SAPIS mode
27660 … (0x1<<0) // MSM Function IDDQ state's default value for pd_slv_bias in SAPIS mode
27662 … (0x1<<1) // MSM Function IDDQ state's default value for pd_txdrv in SAPIS mode
27664 … (0x1<<2) // MSM Function IDDQ state's default value for pd_txreg in SAPIS mode
27666 … (0x1<<3) // MSM Function IDDQ state's default value for pd_vco in SAPIS mode
27668 … (0x1<<4) // MSM Function IDDQ state's default value for pd_vco_buf in SAPIS mode
27670 … (0x1<<5) // MSM Function IDDQ state's default value for reset_cdr in SAPIS mode
27672 … (0x1<<6) // MSM Function IDDQ state's default value for reset_cdr_gcrx in SAPIS mode
27674 … (0x1<<7) // MSM Function IDDQ state's default value for reset_dfe in SAPIS mode
27677 … (0x1<<0) // MSM Function IDDQ state's default value for reset_lnreg in SAPIS mode
27679 … (0x1<<1) // MSM Function IDDQ state's default value for reset_lnregh in SAPIS mode
27681 … (0x1<<2) // MSM Function IDDQ state's default value for reset_p2s in SAPIS mode
27683 … (0x1<<3) // MSM Function IDDQ state's default value for reset_ra in SAPIS mode
27685 … (0x1<<4) // MSM Function IDDQ state's default value for reset_s2p in SAPIS mode
27687 … (0x1<<5) // MSM Function IDDQ state's default value for reset_vco in SAPIS mode
27689 … (0x1<<6) // MSM Function IDDQ state's default value for txreg_bleed_ena in SAPIS mode
27691 … (0x1<<7) // MSM Function IDDQ state's default value for tx_lowpwr_idle_ena in SAPIS mode
27694 … (0x1<<0) // MSM Function IDDQ state's default value for cdr_en in SAPIS mode
27696 … (0x1<<1) // MSM Function IDDQ state's default value for rxbclk_en in SAPIS mode
27698 … (0x1<<2) // MSM Function IDDQ state's default value for rx_gate_en in SAPIS mode
27700 … (0x1<<3) // MSM Function IDDQ state's default value for reset_tx_clkdiv in SAPIS mode
27703 … (0x1<<0) // MSM Function RESET state's default value for iddq_sd in SAPIS mode
27705 … (0x1<<1) // MSM Function RESET state's default value for pd_dfe in SAPIS mode
27707 … (0x1<<2) // MSM Function RESET state's default value for pd_dfe_bias in SAPIS mode
27709 … (0x1<<3) // MSM Function RESET state's default value for pd_lnreg in SAPIS mode
27711 … (0x1<<4) // MSM Function RESET state's default value for pd_lnregh in SAPIS mode
27713 … (0x1<<5) // MSM Function RESET state's default value for pd_p2s in SAPIS mode
27715 … (0x1<<6) // MSM Function RESET state's default value for pd_ra in SAPIS mode
27717 … (0x1<<7) // MSM Function RESET state's default value for pd_s2p in SAPIS mode
27720 … (0x1<<0) // MSM Function RESET state's default value for pd_slv_bias in SAPIS mode
27722 … (0x1<<1) // MSM Function RESET state's default value for pd_txdrv in SAPIS mode
27724 … (0x1<<2) // MSM Function RESET state's default value for pd_txreg in SAPIS mode
27726 … (0x1<<3) // MSM Function RESET state's default value for pd_vco in SAPIS mode
27728 … (0x1<<4) // MSM Function RESET state's default value for pd_vco_buf in SAPIS mode
27730 … (0x1<<5) // MSM Function RESET state's default value for reset_cdr in SAPIS mode
27732 … (0x1<<6) // MSM Function RESET state's default value for reset_cdr_gcrx in SAPIS mode
27734 … (0x1<<7) // MSM Function RESET state's default value for reset_dfe in SAPIS mode
27737 … (0x1<<0) // MSM Function RESET state's default value for reset_lnreg in SAPIS mode
27739 … (0x1<<1) // MSM Function RESET state's default value for reset_lnregh in SAPIS mode
27741 … (0x1<<2) // MSM Function RESET state's default value for reset_p2s in SAPIS mode
27743 … (0x1<<3) // MSM Function RESET state's default value for reset_ra in SAPIS mode
27745 … (0x1<<4) // MSM Function RESET state's default value for reset_s2p in SAPIS mode
27747 … (0x1<<5) // MSM Function RESET state's default value for reset_vco in SAPIS mode
27749 … (0x1<<6) // MSM Function RESET state's default value for txreg_bleed_ena in SAPIS mode
27751 … (0x1<<7) // MSM Function RESET state's default value for tx_lowpwr_idle_ena in SAPIS mode
27754 … (0x1<<0) // MSM Function RESET state's default value for cdr_en in SAPIS mode
27756 … (0x1<<1) // MSM Function RESET state's default value for rxbclk_en in SAPIS mode
27758 … (0x1<<2) // MSM Function RESET state's default value for rx_gate_en in SAPIS mode
27760 … (0x1<<3) // MSM Function RESET state's default value for reset_tx_clkdiv in SAPIS mode
27763 … (0x1<<0) // MSM Function NORMAL state's default value for iddq_sd in SAPIS mode
27765 … (0x1<<1) // MSM Function NORMAL state's default value for pd_dfe in SAPIS mode
27767 … (0x1<<2) // MSM Function NORMAL state's default value for pd_dfe_bias in SAPIS mode
27769 … (0x1<<3) // MSM Function NORMAL state's default value for pd_lnreg in SAPIS mode
27771 … (0x1<<4) // MSM Function NORMAL state's default value for pd_lnregh in SAPIS mode
27773 … (0x1<<5) // MSM Function NORMAL state's default value for pd_p2s in SAPIS mode
27775 … (0x1<<6) // MSM Function NORMAL state's default value for pd_ra in SAPIS mode
27777 … (0x1<<7) // MSM Function NORMAL state's default value for pd_s2p in SAPIS mode
27780 … (0x1<<0) // MSM Function NORMAL state's default value for pd_slv_bias in SAPIS mode
27782 … (0x1<<1) // MSM Function NORMAL state's default value for pd_txdrv in SAPIS mode
27784 … (0x1<<2) // MSM Function NORMAL state's default value for pd_txreg in SAPIS mode
27786 … (0x1<<3) // MSM Function NORMAL state's default value for pd_vco in SAPIS mode
27788 … (0x1<<4) // MSM Function NORMAL state's default value for pd_vco_buf in SAPIS mode
27790 … (0x1<<5) // MSM Function NORMAL state's default value for reset_cdr in SAPIS mode
27792 … (0x1<<6) // MSM Function NORMAL state's default value for reset_cdr_gcrx in SAPIS mode
27794 … (0x1<<7) // MSM Function NORMAL state's default value for reset_dfe in SAPIS mode
27797 … (0x1<<0) // MSM Function NORMAL state's default value for reset_lnreg in SAPIS mode
27799 … (0x1<<1) // MSM Function NORMAL state's default value for reset_lnregh in SAPIS mode
27801 … (0x1<<2) // MSM Function NORMAL state's default value for reset_p2s in SAPIS mode
27803 … (0x1<<3) // MSM Function NORMAL state's default value for reset_ra in SAPIS mode
27805 … (0x1<<4) // MSM Function NORMAL state's default value for reset_s2p in SAPIS mode
27807 … (0x1<<5) // MSM Function NORMAL state's default value for reset_vco in SAPIS mode
27809 … (0x1<<6) // MSM Function NORMAL state's default value for txreg_bleed_ena in SAPIS mode
27811 … (0x1<<7) // MSM Function NORMAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
27814 … (0x1<<0) // MSM Function NORMAL state's default value for cdr_en in SAPIS mode
27816 … (0x1<<1) // MSM Function NORMAL state's default value for rxbclk_en in SAPIS mode
27818 … (0x1<<2) // MSM Function NORMAL state's default value for rx_gate_en in SAPIS mode
27820 … (0x1<<3) // MSM Function NORMAL state's default value for reset_tx_clkdiv in SAPIS mode
27823 … (0x1<<0) // MSM Function PARTIAL state's default value for iddq_sd in SAPIS mode
27825 … (0x1<<1) // MSM Function PARTIAL state's default value for pd_dfe in SAPIS mode
27827 … (0x1<<2) // MSM Function PARTIAL state's default value for pd_dfe_bias in SAPIS mode
27829 … (0x1<<3) // MSM Function PARTIAL state's default value for pd_lnreg in SAPIS mode
27831 … (0x1<<4) // MSM Function PARTIAL state's default value for pd_lnregh in SAPIS mode
27833 … (0x1<<5) // MSM Function PARTIAL state's default value for pd_p2s in SAPIS mode
27835 … (0x1<<6) // MSM Function PARTIAL state's default value for pd_ra in SAPIS mode
27837 … (0x1<<7) // MSM Function PARTIAL state's default value for pd_s2p in SAPIS mode
27840 … (0x1<<0) // MSM Function PARTIAL state's default value for pd_slv_bias in SAPIS mode
27842 … (0x1<<1) // MSM Function PARTIAL state's default value for pd_txdrv in SAPIS mode
27844 … (0x1<<2) // MSM Function PARTIAL state's default value for pd_txreg in SAPIS mode
27846 … (0x1<<3) // MSM Function PARTIAL state's default value for pd_vco in SAPIS mode
27848 … (0x1<<4) // MSM Function PARTIAL state's default value for pd_vco_buf in SAPIS mode
27850 … (0x1<<5) // MSM Function PARTIAL state's default value for reset_cdr in SAPIS mode
27852 … (0x1<<6) // MSM Function PARTIAL state's default value for reset_cdr_gcrx in SAPIS mode
27854 … (0x1<<7) // MSM Function PARTIAL state's default value for reset_dfe in SAPIS mode
27857 … (0x1<<0) // MSM Function PARTIAL state's default value for reset_lnreg in SAPIS mode
27859 … (0x1<<1) // MSM Function PARTIAL state's default value for reset_lnregh in SAPIS mode
27861 … (0x1<<2) // MSM Function PARTIAL state's default value for reset_p2s in SAPIS mode
27863 … (0x1<<3) // MSM Function PARTIAL state's default value for reset_ra in SAPIS mode
27865 … (0x1<<4) // MSM Function PARTIAL state's default value for reset_s2p in SAPIS mode
27867 … (0x1<<5) // MSM Function PARTIAL state's default value for reset_vco in SAPIS mode
27869 … (0x1<<6) // MSM Function PARTIAL state's default value for txreg_bleed_ena in SAPIS mode
27871 … (0x1<<7) // MSM Function PARTIAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
27874 … (0x1<<0) // MSM Function PARTIAL state's default value for cdr_en in SAPIS mode
27876 … (0x1<<1) // MSM Function PARTIAL state's default value for rxbclk_en in SAPIS mode
27878 … (0x1<<2) // MSM Function PARTIAL state's default value for rx_gate_en in SAPIS mode
27880 … (0x1<<3) // MSM Function PARTIAL state's default value for reset_tx_clkdiv in SAPIS mode
27883 … (0x1<<0) // MSM Function SLUMBER state's default value for iddq_sd in SAPIS mode
27885 … (0x1<<1) // MSM Function SLUMBER state's default value for pd_dfe in SAPIS mode
27887 … (0x1<<2) // MSM Function SLUMBER state's default value for pd_dfe_bias in SAPIS mode
27889 … (0x1<<3) // MSM Function SLUMBER state's default value for pd_lnreg in SAPIS mode
27891 … (0x1<<4) // MSM Function SLUMBER state's default value for pd_lnregh in SAPIS mode
27893 … (0x1<<5) // MSM Function SLUMBER state's default value for pd_p2s in SAPIS mode
27895 … (0x1<<6) // MSM Function SLUMBER state's default value for pd_ra in SAPIS mode
27897 … (0x1<<7) // MSM Function SLUMBER state's default value for pd_s2p in SAPIS mode
27900 … (0x1<<0) // MSM Function SLUMBER state's default value for pd_slv_bias in SAPIS mode
27902 … (0x1<<1) // MSM Function SLUMBER state's default value for pd_txdrv in SAPIS mode
27904 … (0x1<<2) // MSM Function SLUMBER state's default value for pd_txreg in SAPIS mode
27906 … (0x1<<3) // MSM Function SLUMBER state's default value for pd_vco in SAPIS mode
27908 … (0x1<<4) // MSM Function SLUMBER state's default value for pd_vco_buf in SAPIS mode
27910 … (0x1<<5) // MSM Function SLUMBER state's default value for reset_cdr in SAPIS mode
27912 … (0x1<<6) // MSM Function SLUMBER state's default value for reset_cdr_gcrx in SAPIS mode
27914 … (0x1<<7) // MSM Function SLUMBER state's default value for reset_dfe in SAPIS mode
27917 … (0x1<<0) // MSM Function SLUMBER state's default value for reset_lnreg in SAPIS mode
27919 … (0x1<<1) // MSM Function SLUMBER state's default value for reset_lnregh in SAPIS mode
27921 … (0x1<<2) // MSM Function SLUMBER state's default value for reset_p2s in SAPIS mode
27923 … (0x1<<3) // MSM Function SLUMBER state's default value for reset_ra in SAPIS mode
27925 … (0x1<<4) // MSM Function SLUMBER state's default value for reset_s2p in SAPIS mode
27927 … (0x1<<5) // MSM Function SLUMBER state's default value for reset_vco in SAPIS mode
27929 … (0x1<<6) // MSM Function SLUMBER state's default value for txreg_bleed_ena in SAPIS mode
27931 … (0x1<<7) // MSM Function SLUMBER state's default value for tx_lowpwr_idle_ena in SAPIS mode
27934 … (0x1<<0) // MSM Function SLUMBER state's default value for cdr_en in SAPIS mode
27936 … (0x1<<1) // MSM Function SLUMBER state's default value for rxbclk_en in SAPIS mode
27938 … (0x1<<2) // MSM Function SLUMBER state's default value for rx_gate_en in SAPIS mode
27940 … (0x1<<3) // MSM Function SLUMBER state's default value for reset_tx_clkdiv in SAPIS mode
27978 …_LOW_EN_O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a prog…
27980 …LOW_EN_O_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor down to a prog…
27998 … (0x1<<6) // Set all DFE calibration values to mid-scale instead of usin…
28000 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
28002 …ONT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
28004 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
28005 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
28006 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
28007 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
28008 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
28009 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
28010 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
28014 …ECAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration for { Tap…
28023 …ATE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
28084 …O_5_0_K2_E5 (0x3f<<0) // Sets certain bits in training pattern as …
28088 …2_E5 (0x1<<7) // Step calibration in test mode, rising ed…
28091 …0_K2_E5 (0x7f<<0) // Enable average 4 in calibration, otherwi…
28096 …IFT_O_3_0_K2_E5 (0xf<<0) // Shift the edge samples in rxeq_ctrl
28113 … 0x002bf8UL //Access:RW DataWidth:0x8 // Training pattern for boost in rate2
28115 …TE2_BOOST_TRAINING_PATT_O_8_K2_E5 (0x1<<0) // Training pattern for boost in rate2
28117 … 0x002c00UL //Access:RW DataWidth:0x8 // Training pattern for boost in rate3
28119 …TE3_BOOST_TRAINING_PATT_O_8_K2_E5 (0x1<<0) // Training pattern for boost in rate3
28122 …_K2_E5 (0x3f<<0) // Sets certain bits in training pattern as don't care in rat…
28125 …_K2_E5 (0x3f<<0) // Sets certain bits in training pattern as don't care in rat…
28128 …_K2_E5 (0x3f<<0) // Sets certain bits in training pattern as don't care in rat…
28173 …NE_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
28175 …ADAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
28375 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28377 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28379 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28381 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28383 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28385 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28387 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28389 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28392 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28394 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28396 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28398 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28400 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28402 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28404 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28406 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28409 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28411 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28413 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28415 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28417 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28419 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28421 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28423 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28426 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28428 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28430 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28432 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28435 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28437 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28439 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28441 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28443 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28445 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28447 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28449 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28452 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28454 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28456 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28458 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28460 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28462 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28464 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28466 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28469 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28471 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28473 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28475 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28477 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28479 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28481 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28483 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28486 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28488 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28490 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28492 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28495 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28497 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28499 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28501 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28503 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28505 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28507 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28509 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28512 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28514 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28516 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28518 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28520 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28522 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28524 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28526 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28529 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28531 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28533 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28535 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28537 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28539 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28541 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28543 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28546 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28548 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28550 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28552 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28555 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28557 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28559 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28561 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28563 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28565 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28567 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28569 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28572 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28574 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28576 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28578 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28580 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28582 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28584 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28586 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28589 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28591 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28593 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28595 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28597 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28599 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28601 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28603 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28606 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28608 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28610 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28612 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28615 … (0x1f<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28619 … (0x1f<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
28637 …E_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
28709 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28711 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28713 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28715 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28717 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28719 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28721 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28723 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28726 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28728 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28730 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28732 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28734 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28736 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28738 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28740 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28743 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28745 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28747 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28749 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28751 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28753 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28755 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28757 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28760 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28762 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28764 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28766 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28769 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28771 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28773 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28775 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28777 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28779 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28781 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28783 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28786 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28788 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28790 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28792 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28794 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28796 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28798 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28800 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28803 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28805 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28807 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28809 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28811 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28813 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28815 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28817 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28820 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28822 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28824 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28826 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28829 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28831 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28833 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28835 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28837 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28839 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28841 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28843 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28846 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28848 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28850 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28852 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28854 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28856 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28858 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28860 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28863 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28865 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28867 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28869 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28871 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28873 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28875 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28877 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28880 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28882 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28884 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28886 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28888 … DataWidth:0x8 // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28889 … DataWidth:0x8 // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28890 … DataWidth:0x8 // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28891 … DataWidth:0x8 // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28893 … (0x7<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
28901 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
28912 …<<3) // Selects one lane's recovered byte clock of all existing lanes, which goes to refclk buffer.
28914 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
28917 …_AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
28929 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28930 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28931 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28933 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28935 … 0x003028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
28936 … 0x00302cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
28937 … 0x003030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
28938 … 0x003034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
28939 … 0x003038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
28940 … 0x00303cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
28941 … 0x003040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
28942 … 0x003044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
28943 … 0x003048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
28944 … 0x00304cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
28945 … 0x003050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
28946 … 0x003054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
28947 … 0x003058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
28948 … 0x00305cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
28949 … 0x003060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
28950 … 0x003064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
28968 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
28970 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
28972 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
28974 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28977 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
28979 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28981 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28983 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
28986 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28988 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28990 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28992 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28995 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
28997 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28999 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29001 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29004 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29006 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29008 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29060 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29068 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
29102 …K2_E5 (0x1<<2) // Override enable for overriding N-div value
29121 …01_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29153 …UL //Access:RW DataWidth:0x8 // Frequency offset control word for SSC in synth mode or SSC_GE…
29154 …UL //Access:RW DataWidth:0x8 // Frequency offset control word for SSC in synth mode or SSC_GE…
29156 … (0xf<<0) // Frequency offset control word for SSC in synth mode or SSC_GE…
29162 …of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
29163 …of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
29165 …of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
29171 … (0x1<<6) // Enable in SSC_GEN mode for upwards and downwards spreading. 0- down…
29173 …/Access:RW DataWidth:0x8 // In Spread Spectrum Generation mode, represents the magnitude of t…
29174 …/Access:RW DataWidth:0x8 // In Spread Spectrum Generation mode, represents the magnitude of t…
29178 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29180 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29193 … 0x0031e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29195 …MP_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29198 …A_CM_REFCLK_TERM_OVR_O_K2_E5 (0x1f<<0) // Refclk Termination overri…
29200 …MA_CM_REFCLK_TERM_OVR_EN_O_K2_E5 (0x1<<5) // Refclk Termination overri…
29207 … 0x0031f0UL //Access:RW DataWidth:0x8 // In txterm calibration, the number refclk c…
29209 …T_UP_8_K2_E5 (0x1<<0) // In txterm calibration, the number refclk c…
29211 …T_SAMPLE_K2_E5 (0x7<<1) // in txterm calibration, the number refclk c…
29213 …_AHB_RX_TC_UP_NUM_SAMPLES_K2_E5 (0xf<<4) // in txterm calibration, …
29223 … pcs_rate_o[1] : 0: PMA operates in 10b/20b mode Enables %5 circuit 1: PMA oper…
29227 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
29235 … 0x003210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29237 …TBUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29251 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
29492 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
29503 …<<3) // Selects one lane's recovered byte clock of all existing lanes, which goes to refclk buffer.
29505 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
29508 …HB_PMA_CM_DIVNSEL_6_0_O_K2_E5 (0x7f<<0) // CMU N-divider setting
29520 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29521 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29522 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29524 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29526 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
29527 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
29528 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
29529 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
29530 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
29531 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
29532 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
29533 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
29534 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
29535 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
29536 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
29537 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
29538 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
29539 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
29540 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
29541 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
29559 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
29561 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
29563 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
29565 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29568 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
29570 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29572 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29574 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
29577 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29579 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29581 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29583 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29586 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
29588 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29590 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29592 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29595 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29597 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29599 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29640 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29648 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
29682 …_E5 (0x1<<2) // Override enable for overriding N-div value
29701 …_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29728 …UL //Access:RW DataWidth:0x8 // Frequency offset control word for SSC in synth mode or SSC_GE…
29729 …UL //Access:RW DataWidth:0x8 // Frequency offset control word for SSC in synth mode or SSC_GE…
29731 … (0xf<<0) // Frequency offset control word for SSC in synth mode or SSC_GE…
29737 …of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
29738 …of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
29740 …of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
29746 … (0x1<<6) // Enable in SSC_GEN mode for upwards and downwards spreading. 0- down…
29748 …/Access:RW DataWidth:0x8 // In Spread Spectrum Generation mode, represents the magnitude of t…
29749 …/Access:RW DataWidth:0x8 // In Spread Spectrum Generation mode, represents the magnitude of t…
29753 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29755 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29768 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29770 …_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29773 …CM_REFCLK_TERM_OVR_O_K2_E5 (0x1f<<0) // Refclk Termination overri…
29775 …_CM_REFCLK_TERM_OVR_EN_O_K2_E5 (0x1<<5) // Refclk Termination overri…
29782 … 0x0001f0UL //Access:RW DataWidth:0x8 // In txterm calibration, the number refclk c…
29784 …UP_8_K2_E5 (0x1<<0) // In txterm calibration, the number refclk c…
29786 …SAMPLE_K2_E5 (0x7<<1) // in txterm calibration, the number refclk c…
29788 …HB_RX_TC_UP_NUM_SAMPLES_K2_E5 (0xf<<4) // in txterm calibration, …
29798 … pcs_rate_o[1] : 0: PMA operates in 10b/20b mode Enables %5 circuit 1: PMA oper…
29802 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
29810 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29812 …US_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29816 … (0x3<<0) // "Divider for pma_cm_ref_clk in gen3 rate. Used only in PCIe3 1C…
29818 …U GCFSM clock in gen3 rate The only access to this divider. Not an override 4�d0: No division 4�…
29820 …the SSC clock in gen3 rate. The only access to this divider. Not an override 4�d0: No division 4…
29823 …in gen3 rate pcs_rate_o[0] : 0: VCO clock untouched 1: VCO clock divided by 2 …
29832 …E5 (0x3<<2) // CMU LF Force value in gen3 rate Used only in PCIe3 1C…
29836 … (0x1<<6) // CMU PLL HIZ setting in gen3 rate Used only in PCIe3 1C…
29843 …_E5 (0x1<<3) // Charge pump chop enable in gen3 rate Used only in PCIe3 1C…
29852 … (0x3<<4) // CMU VREG setting in gen3 rate Used only in PCIe3 1C…
29854 … (0x3<<6) // CMU VREGH setting in gen3 rate Used only in PCIe3 1C…
29857 … (0x1<<0) // Force PFD to output down in gen3 rate Used only in PCIe3 1C…
29859 …5 (0x1<<1) // Force PFD to output up in gen3 rate Used only in PCIe3 1C…
29861 …_K2_E5 (0x1<<2) // CMU V2I filter enable in gen3 rate Used only in PCIe3 1C…
29869 … 0x000234UL //Access:RW DataWidth:0x8 // CMU AFE spares in gen3 rate Used only in PCIe3 1C…
29871 … (0x3<<0) // PFD pulse width setting in gen3 rate Used only in PCIe3 1C…
29875 … (0x1f<<3) // CMU PLL KVCO setting in gen3 rate Used only in PCIe3 1C…
29878 …2_E5 (0x7f<<0) // CMU P-divider setting in gen3 rate Used only in …
29881 … (0x7<<0) // Override enable for overriding VCOFR value in gen3 rate Used only in PCIe3 1C…
29899 … // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode in gen3 rate U…
29900 … // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode in gen3 rate U…
29902 …) // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode in gen3 rate U…
29906 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
30139 …_SETVAL_O_K2_E5 (0x1<<0) // MSM Function NORM REFCLK mode default value…
30141 …ETVAL_O_K2_E5 (0x1<<1) // MSM Function NORM REFCLK mode default value…
30143 …ORM_REFCLK_SETVAL_O_K2_E5 (0x1<<2) // MSM Function NORM REFCLK mode default value…
30145 …TVAL_O_K2_E5 (0x1<<3) // MSM Function NORM REFCLK mode default value…
30147 …_SETVAL_O_K2_E5 (0x1<<4) // MSM Function NORM REFCLK mode default value…
30149 …CLK_SETVAL_O_K2_E5 (0x1<<5) // MSM Function NORM REFCLK mode default value…
30151 …TVAL_O_K2_E5 (0x1<<6) // MSM Function NORM REFCLK mode default value…
30153 …CLK_SETVAL_O_K2_E5 (0x1<<7) // MSM Function NORM REFCLK mode default value…
30156 …_SETVAL_O_K2_E5 (0x1<<0) // MSM Function NORM REFCLK mode default value…
30158 …EFCLK_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NORM REFCLK mode default value…
30160 …CLK_SETVAL_O_K2_E5 (0x1<<2) // MSM Function NORM REFCLK mode default value…
30162 …REFCLK_SETVAL_O_K2_E5 (0x1<<3) // MSM Function NORM REFCLK mode default value…
30164 …EFCLK_SETVAL_O_K2_E5 (0x1<<4) // MSM Function NORM REFCLK mode default value…
30166 …CLK_SETVAL_O_K2_E5 (0x1<<5) // MSM Function NORM REFCLK mode default value…
30168 …EFCLK_SETVAL_O_K2_E5 (0x1<<6) // MSM Function NORM REFCLK mode default value…
30170 …LK_SETVAL_O_K2_E5 (0x1<<7) // MSM Function NORM REFCLK mode default value…
30173 …K_SETVAL_O_K2_E5 (0x1<<0) // MSM Function NORM REFCLK mode default value…
30175 …_SETVAL_O_K2_E5 (0x1<<1) // MSM Function NORM REFCLK mode default value…
30177 …LK_SETVAL_O_K2_E5 (0x1<<2) // MSM Function NORM REFCLK mode default value…
30245 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
30248 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
30250 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
30253 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
30256 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
30258 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
30261 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
30265 …ratio setting for lnX_ck_txb_o. When ln_common_sync_txclk_en_o is high and in NORM state: …
30270 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
30272 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
30277 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
30279 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
30285 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
30287 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
30292 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
30294 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
30296 … 0x000824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30297 … 0x000828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30298 … 0x00082cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
30299 … 0x000830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
30300 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
30302 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
30309 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
30317 …840UL //Access:RW DataWidth:0x8 // Bist checker preamble word 0. When in 8b mode, and prior t…
30319 … (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior t…
30329 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
30330 … 0x000854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30331 … 0x000858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30332 … 0x00085cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30333 … 0x000860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30341 … 0x000880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
30342 … 0x000884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
30343 … 0x000888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
30344 … 0x00088cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
30345 … 0x000890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
30346 … 0x000894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
30347 … 0x000898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
30348 … 0x00089cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
30349 … 0x0008a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
30350 … 0x0008a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
30351 … 0x0008a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
30352 … 0x0008acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
30353 … 0x0008b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
30354 … 0x0008b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
30355 … 0x0008b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
30356 … 0x0008bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
30357 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
30358 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
30359 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
30360 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
30365 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
30367 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
30369 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
30377 …libration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfs…
30389 …asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_…
30390 …asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_…
30399 …dle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
30403 …dle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
30413 … 0x000918UL //Access:RW DataWidth:0x8 // CDR control block cycle length When not in PCIe Gen3.
30414 … 0x00091cUL //Access:RW DataWidth:0x8 // CDR control block cycle length When in PCIe Gen3.
30421 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
30423 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
30425 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
30429 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30430 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30431 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30433 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30435 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
30485 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
30487 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler…
30492 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
30519 … (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler …
30536 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
30538 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
30544 …PMA_LN_EYE_ENA270_O_K2_E5 (0x1<<4) // In eye diagram generati…
30546 …PMA_LN_EYE_ENA90_O_K2_E5 (0x1<<5) // In eye diagram generati…
30577 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler…
30602 … (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler …
30620 …_CMP_K2_E5 (0xf<<0) // in txterm calibration, the number refclk c…
30622 …_SAMPLE_K2_E5 (0x7<<4) // in txterm calibration, the number refclk c…
30625 …AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5 (0xf<<0) // in txterm calibration, …
30627 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
30629 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
30646 … 0x0009f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
30650 …rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They a…
30652 …s bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
30654 …s bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
30656 …s bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
30658 …s bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
30714 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
30716 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
30794 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
30800 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
30802 … 0x000a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
30804 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
30806 … 0x000a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
30816 …is bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is logically OR'ed with the b…
30824 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
30832 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
30834 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
30855 … (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables c…
30857 … (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables c…
30859 …W DataWidth:0x8 // Enables for various cdfe component during init cal in rate3 bit[0] : enabl…
30860 …ataWidth:0x8 // Enables for various cdfe component during continuos cal in rate3 bit[0] : enabl…
30861 …RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 bit[0] …
30865 …:0x8 // Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enabl…
30866 …0x8 // Enables for various cdfe component during post txeq adaptation in rate3 bit[0] : enabl…
30867 …W DataWidth:0x8 // Enables for various cdfe component during init cal in rate2 bit[0] : enabl…
30868 …ataWidth:0x8 // Enables for various cdfe component during continuos cal in rate2 bit[0] : enabl…
30869 …RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 bit[0] …
31019 …_E5 (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
31139 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
31141 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31143 …0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
31145 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31149 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
31152 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31154 …1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
31156 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31158 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31160 …1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
31162 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31167 …0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
31169 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31187 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
31191 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
31200 …in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divide…
31203 …N_TO_CLK_TXB_WAIT_O_K2_E5 (0x1f<<0) // In per lane common sync…
31234 … (0x1<<5) // Enables skpos error status propagation in Gen3
31241 …K_IN_LB_O_K2_E5 (0x1<<7) // Disables the EIEOS check in loopback
31244 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
31258 … To skip cdr calibration routines for PCIe gen3. Can be used when PHY is operating in gen1,2 only.
31260 … (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2. May not be needed in real scenario.
31264 …LN_P2S_RBUF_REALIGN_DIFF_O_K2_E5 (0xf<<4) // In per lane common sync…
31289 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
31291 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
31317 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
31325 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
31328 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
31330 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
31333 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
31336 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
31338 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
31341 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
31345 …ratio setting for lnX_ck_txb_o. When ln_common_sync_txclk_en_o is high and in NORM state: …
31350 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
31352 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
31357 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
31359 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
31365 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
31367 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
31372 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
31374 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
31376 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31377 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31378 … 0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
31379 … 0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
31380 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
31382 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
31389 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
31397 …040UL //Access:RW DataWidth:0x8 // Bist checker preamble word 0. When in 8b mode, and prior t…
31399 … (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior t…
31409 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
31410 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31411 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31412 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31413 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31421 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
31422 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
31423 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
31424 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
31425 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
31426 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
31427 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
31428 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
31429 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
31430 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
31431 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
31432 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
31433 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
31434 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
31435 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
31436 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
31437 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
31438 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
31439 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
31440 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
31445 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
31447 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
31449 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
31457 …libration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfs…
31469 …asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_…
31470 …asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_…
31479 …dle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
31483 …dle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
31493 … 0x001118UL //Access:RW DataWidth:0x8 // CDR control block cycle length When not in PCIe Gen3.
31494 … 0x00111cUL //Access:RW DataWidth:0x8 // CDR control block cycle length When in PCIe Gen3.
31501 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
31503 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
31505 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
31509 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31510 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31511 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31513 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31515 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
31565 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
31567 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler…
31572 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
31599 … (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler …
31616 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
31618 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
31624 …PMA_LN_EYE_ENA270_O_K2_E5 (0x1<<4) // In eye diagram generati…
31626 …PMA_LN_EYE_ENA90_O_K2_E5 (0x1<<5) // In eye diagram generati…
31657 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler…
31682 … (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler …
31700 …_CMP_K2_E5 (0xf<<0) // in txterm calibration, the number refclk c…
31702 …_SAMPLE_K2_E5 (0x7<<4) // in txterm calibration, the number refclk c…
31705 …AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5 (0xf<<0) // in txterm calibration, …
31707 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
31709 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
31726 … 0x0011f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
31730 …rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They a…
31732 …s bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
31734 …s bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
31736 …s bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
31738 …s bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
31794 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
31796 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
31874 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
31880 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
31882 … 0x001280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
31884 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
31886 … 0x001288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
31896 …is bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is logically OR'ed with the b…
31904 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
31912 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
31914 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
31935 … (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables c…
31937 … (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables c…
31939 …W DataWidth:0x8 // Enables for various cdfe component during init cal in rate3 bit[0] : enabl…
31940 …ataWidth:0x8 // Enables for various cdfe component during continuos cal in rate3 bit[0] : enabl…
31941 …RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 bit[0] …
31945 …:0x8 // Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enabl…
31946 …0x8 // Enables for various cdfe component during post txeq adaptation in rate3 bit[0] : enabl…
31947 …W DataWidth:0x8 // Enables for various cdfe component during init cal in rate2 bit[0] : enabl…
31948 …ataWidth:0x8 // Enables for various cdfe component during continuos cal in rate2 bit[0] : enabl…
31949 …RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 bit[0] …
32099 …_E5 (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
32219 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
32221 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32223 …0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
32225 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32229 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
32232 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32234 …1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
32236 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32238 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32240 …1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
32242 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32247 …0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
32249 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32267 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
32271 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
32280 …in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divide…
32283 …N_TO_CLK_TXB_WAIT_O_K2_E5 (0x1f<<0) // In per lane common sync…
32314 … (0x1<<5) // Enables skpos error status propagation in Gen3
32321 …K_IN_LB_O_K2_E5 (0x1<<7) // Disables the EIEOS check in loopback
32324 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
32338 … To skip cdr calibration routines for PCIe gen3. Can be used when PHY is operating in gen1,2 only.
32340 … (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2. May not be needed in real scenario.
32344 …LN_P2S_RBUF_REALIGN_DIFF_O_K2_E5 (0xf<<4) // In per lane common sync…
32369 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
32371 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
32397 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
32405 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
32408 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
32410 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
32413 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
32416 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
32418 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
32421 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
32425 …ratio setting for lnX_ck_txb_o. When ln_common_sync_txclk_en_o is high and in NORM state: …
32430 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
32432 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
32437 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
32439 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
32445 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
32447 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
32452 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
32454 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
32456 … 0x001824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32457 … 0x001828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32458 … 0x00182cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
32459 … 0x001830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
32460 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
32462 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
32469 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
32477 …840UL //Access:RW DataWidth:0x8 // Bist checker preamble word 0. When in 8b mode, and prior t…
32479 … (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior t…
32489 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
32490 … 0x001854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32491 … 0x001858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32492 … 0x00185cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32493 … 0x001860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32501 … 0x001880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
32502 … 0x001884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
32503 … 0x001888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
32504 … 0x00188cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
32505 … 0x001890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
32506 … 0x001894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
32507 … 0x001898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
32508 … 0x00189cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
32509 … 0x0018a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
32510 … 0x0018a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
32511 … 0x0018a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
32512 … 0x0018acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
32513 … 0x0018b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
32514 … 0x0018b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
32515 … 0x0018b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
32516 … 0x0018bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
32517 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
32518 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
32519 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
32520 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
32525 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
32527 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
32529 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
32537 …libration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfs…
32549 …asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_…
32550 …asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_…
32559 …dle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
32563 …dle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
32573 … 0x001918UL //Access:RW DataWidth:0x8 // CDR control block cycle length When not in PCIe Gen3.
32574 … 0x00191cUL //Access:RW DataWidth:0x8 // CDR control block cycle length When in PCIe Gen3.
32581 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
32583 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
32585 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
32589 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32590 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32591 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32593 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32595 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
32645 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
32647 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler…
32652 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
32679 … (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler …
32696 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
32698 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
32704 …PMA_LN_EYE_ENA270_O_K2_E5 (0x1<<4) // In eye diagram generati…
32706 …PMA_LN_EYE_ENA90_O_K2_E5 (0x1<<5) // In eye diagram generati…
32737 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler…
32762 … (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler …
32780 …_CMP_K2_E5 (0xf<<0) // in txterm calibration, the number refclk c…
32782 …_SAMPLE_K2_E5 (0x7<<4) // in txterm calibration, the number refclk c…
32785 …AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5 (0xf<<0) // in txterm calibration, …
32787 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
32789 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
32806 … 0x0019f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
32810 …rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They a…
32812 …s bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
32814 …s bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
32816 …s bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
32818 …s bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
32874 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
32876 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
32954 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
32960 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
32962 … 0x001a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
32964 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
32966 … 0x001a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
32976 …is bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is logically OR'ed with the b…
32984 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
32992 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
32994 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
33015 … (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables c…
33017 … (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables c…
33019 …W DataWidth:0x8 // Enables for various cdfe component during init cal in rate3 bit[0] : enabl…
33020 …ataWidth:0x8 // Enables for various cdfe component during continuos cal in rate3 bit[0] : enabl…
33021 …RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 bit[0] …
33025 …:0x8 // Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enabl…
33026 …0x8 // Enables for various cdfe component during post txeq adaptation in rate3 bit[0] : enabl…
33027 …W DataWidth:0x8 // Enables for various cdfe component during init cal in rate2 bit[0] : enabl…
33028 …ataWidth:0x8 // Enables for various cdfe component during continuos cal in rate2 bit[0] : enabl…
33029 …RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 bit[0] …
33179 …_E5 (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
33299 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
33301 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33303 …0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
33305 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33309 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
33312 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33314 …1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
33316 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33318 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33320 …1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
33322 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33327 …0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
33329 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33347 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
33351 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
33360 …in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divide…
33363 …N_TO_CLK_TXB_WAIT_O_K2_E5 (0x1f<<0) // In per lane common sync…
33394 … (0x1<<5) // Enables skpos error status propagation in Gen3
33401 …K_IN_LB_O_K2_E5 (0x1<<7) // Disables the EIEOS check in loopback
33404 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
33418 … To skip cdr calibration routines for PCIe gen3. Can be used when PHY is operating in gen1,2 only.
33420 … (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2. May not be needed in real scenario.
33424 …LN_P2S_RBUF_REALIGN_DIFF_O_K2_E5 (0xf<<4) // In per lane common sync…
33449 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
33451 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
33477 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
33485 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
33488 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
33490 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
33493 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
33496 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
33498 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
33501 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
33505 …ratio setting for lnX_ck_txb_o. When ln_common_sync_txclk_en_o is high and in NORM state: …
33510 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
33512 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
33517 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
33519 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
33525 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
33527 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
33532 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
33534 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
33536 … 0x002024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33537 … 0x002028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33538 … 0x00202cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
33539 … 0x002030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
33540 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
33542 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
33549 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
33557 …040UL //Access:RW DataWidth:0x8 // Bist checker preamble word 0. When in 8b mode, and prior t…
33559 … (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior t…
33569 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
33570 … 0x002054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33571 … 0x002058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33572 … 0x00205cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33573 … 0x002060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33581 … 0x002080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
33582 … 0x002084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
33583 … 0x002088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
33584 … 0x00208cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
33585 … 0x002090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
33586 … 0x002094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
33587 … 0x002098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
33588 … 0x00209cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
33589 … 0x0020a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
33590 … 0x0020a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
33591 … 0x0020a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
33592 … 0x0020acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
33593 … 0x0020b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
33594 … 0x0020b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
33595 … 0x0020b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
33596 … 0x0020bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
33597 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
33598 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
33599 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
33600 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
33605 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
33607 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
33609 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
33617 …libration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfs…
33629 …asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_…
33630 …asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_…
33639 …dle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
33643 …dle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
33653 … 0x002118UL //Access:RW DataWidth:0x8 // CDR control block cycle length When not in PCIe Gen3.
33654 … 0x00211cUL //Access:RW DataWidth:0x8 // CDR control block cycle length When in PCIe Gen3.
33661 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
33663 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
33665 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
33669 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33670 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33671 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33673 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33675 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
33725 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
33727 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler…
33732 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
33759 … (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler …
33776 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
33778 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
33784 …PMA_LN_EYE_ENA270_O_K2_E5 (0x1<<4) // In eye diagram generati…
33786 …PMA_LN_EYE_ENA90_O_K2_E5 (0x1<<5) // In eye diagram generati…
33817 … (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler…
33842 … (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler …
33860 …_CMP_K2_E5 (0xf<<0) // in txterm calibration, the number refclk c…
33862 …_SAMPLE_K2_E5 (0x7<<4) // in txterm calibration, the number refclk c…
33865 …AHB_TX_TC_CMP_OUT_NUM_SAMPLES_K2_E5 (0xf<<0) // in txterm calibration, …
33867 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
33869 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
33886 … 0x0021f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
33890 …rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They a…
33892 …s bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
33894 …s bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
33896 …s bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
33898 …s bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the b…
33954 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
33956 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
34034 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
34040 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
34042 … 0x002280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
34044 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
34046 … 0x002288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
34056 …is bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is logically OR'ed with the b…
34064 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
34072 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
34074 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
34095 … (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables c…
34097 … (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables c…
34099 …W DataWidth:0x8 // Enables for various cdfe component during init cal in rate3 bit[0] : enabl…
34100 …ataWidth:0x8 // Enables for various cdfe component during continuos cal in rate3 bit[0] : enabl…
34101 …RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 bit[0] …
34105 …:0x8 // Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enabl…
34106 …0x8 // Enables for various cdfe component during post txeq adaptation in rate3 bit[0] : enabl…
34107 …W DataWidth:0x8 // Enables for various cdfe component during init cal in rate2 bit[0] : enabl…
34108 …ataWidth:0x8 // Enables for various cdfe component during continuos cal in rate2 bit[0] : enabl…
34109 …RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 bit[0] …
34259 …_E5 (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
34379 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
34381 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34383 …0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
34385 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34389 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
34392 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34394 …1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
34396 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34398 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34400 …1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
34402 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34407 …0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit or…
34409 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34427 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
34431 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
34440 …in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divide…
34443 …N_TO_CLK_TXB_WAIT_O_K2_E5 (0x1f<<0) // In per lane common sync…
34474 … (0x1<<5) // Enables skpos error status propagation in Gen3
34481 …K_IN_LB_O_K2_E5 (0x1<<7) // Disables the EIEOS check in loopback
34484 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
34498 … To skip cdr calibration routines for PCIe gen3. Can be used when PHY is operating in gen1,2 only.
34500 … (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2. May not be needed in real scenario.
34504 …LN_P2S_RBUF_REALIGN_DIFF_O_K2_E5 (0xf<<4) // In per lane common sync…
34529 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
34531 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
34557 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
34565 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
34568 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
34570 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
34587 … 0x002828UL //Access:RW DataWidth:0x8 // The first 16 bits of an encoded EIEOS in Gen3
34588 … 0x00282cUL //Access:RW DataWidth:0x8 // The first 16 bits of an encoded EIEOS in Gen3
34589 … 0x002830UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of an EIEOS in Gen3
34590 … 0x002834UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of an EIEOS in Gen3
34591 … 0x002838UL //Access:RW DataWidth:0x8 // The first 16 bits of an encoded SDSOS in Gen3
34592 … 0x00283cUL //Access:RW DataWidth:0x8 // The first 16 bits of an encoded SDSOS in Gen3
34593 … 0x002840UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of an SDSOS in Gen3
34594 … 0x002844UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of an SDSOS in Gen3
34595 … 0x002848UL //Access:RW DataWidth:0x8 // The first 16 bits of an encoded SKPOS in Gen3
34596 … 0x00284cUL //Access:RW DataWidth:0x8 // The first 16 bits of an encoded SKPOS in Gen3
34597 … 0x002850UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of a SKPOS in Gen3
34598 … 0x002854UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of a SKPOS in Gen3
34621 … 0x002880UL //Access:RW DataWidth:0x8 // SKP symbol for PCIe Gen3 SKP OS ---8'hAA
34631 … 0x002898UL //Access:RW DataWidth:0x8 // 10-bit align symbol for …
34633 …_S0_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for …
34635 … 0x0028a0UL //Access:RW DataWidth:0x8 // 10-bit align symbol for …
34637 …_S1_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for …
34702 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
34703 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
34704 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
34705 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
34706 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
34707 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
34708 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
34709 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
34710 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
34711 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
34712 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
34713 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
34714 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
34715 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
34716 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
34717 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
34720 …nction. Varies depending on function number. Bits 15-7: Address of first command to run Bits: 6-…
34789 …MFSM state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to …
34790 …MFSM state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to …
34792 … (0x1<<0) // MSM Function IDDQ state's default value for iddq_sd in SAPIS mode
34794 … (0x1<<1) // MSM Function IDDQ state's default value for pd_dfe in SAPIS mode
34796 … (0x1<<2) // MSM Function IDDQ state's default value for pd_dfe_bias in SAPIS mode
34798 … (0x1<<3) // MSM Function IDDQ state's default value for pd_lnreg in SAPIS mode
34800 … (0x1<<4) // MSM Function IDDQ state's default value for pd_lnregh in SAPIS mode
34802 … (0x1<<5) // MSM Function IDDQ state's default value for pd_p2s in SAPIS mode
34804 … (0x1<<6) // MSM Function IDDQ state's default value for pd_ra in SAPIS mode
34806 … (0x1<<7) // MSM Function IDDQ state's default value for pd_s2p in SAPIS mode
34809 … (0x1<<0) // MSM Function IDDQ state's default value for pd_slv_bias in SAPIS mode
34811 … (0x1<<1) // MSM Function IDDQ state's default value for pd_txdrv in SAPIS mode
34813 … (0x1<<2) // MSM Function IDDQ state's default value for pd_txreg in SAPIS mode
34815 … (0x1<<3) // MSM Function IDDQ state's default value for pd_vco in SAPIS mode
34817 … (0x1<<4) // MSM Function IDDQ state's default value for pd_vco_buf in SAPIS mode
34819 … (0x1<<5) // MSM Function IDDQ state's default value for reset_cdr in SAPIS mode
34821 … (0x1<<6) // MSM Function IDDQ state's default value for reset_cdr_gcrx in SAPIS mode
34823 … (0x1<<7) // MSM Function IDDQ state's default value for reset_dfe in SAPIS mode
34826 … (0x1<<0) // MSM Function IDDQ state's default value for reset_lnreg in SAPIS mode
34828 … (0x1<<1) // MSM Function IDDQ state's default value for reset_lnregh in SAPIS mode
34830 … (0x1<<2) // MSM Function IDDQ state's default value for reset_p2s in SAPIS mode
34832 … (0x1<<3) // MSM Function IDDQ state's default value for reset_ra in SAPIS mode
34834 … (0x1<<4) // MSM Function IDDQ state's default value for reset_s2p in SAPIS mode
34836 … (0x1<<5) // MSM Function IDDQ state's default value for reset_vco in SAPIS mode
34838 … (0x1<<6) // MSM Function IDDQ state's default value for txreg_bleed_ena in SAPIS mode
34840 … (0x1<<7) // MSM Function IDDQ state's default value for tx_lowpwr_idle_ena in SAPIS mode
34843 … (0x1<<0) // MSM Function IDDQ state's default value for cdr_en in SAPIS mode
34845 … (0x1<<1) // MSM Function IDDQ state's default value for rxbclk_en in SAPIS mode
34847 … (0x1<<2) // MSM Function IDDQ state's default value for rx_gate_en in SAPIS mode
34849 … (0x1<<3) // MSM Function IDDQ state's default value for reset_tx_clkdiv in SAPIS mode
34852 … (0x1<<0) // MSM Function RESET state's default value for iddq_sd in SAPIS mode
34854 … (0x1<<1) // MSM Function RESET state's default value for pd_dfe in SAPIS mode
34856 … (0x1<<2) // MSM Function RESET state's default value for pd_dfe_bias in SAPIS mode
34858 … (0x1<<3) // MSM Function RESET state's default value for pd_lnreg in SAPIS mode
34860 … (0x1<<4) // MSM Function RESET state's default value for pd_lnregh in SAPIS mode
34862 … (0x1<<5) // MSM Function RESET state's default value for pd_p2s in SAPIS mode
34864 … (0x1<<6) // MSM Function RESET state's default value for pd_ra in SAPIS mode
34866 … (0x1<<7) // MSM Function RESET state's default value for pd_s2p in SAPIS mode
34869 … (0x1<<0) // MSM Function RESET state's default value for pd_slv_bias in SAPIS mode
34871 … (0x1<<1) // MSM Function RESET state's default value for pd_txdrv in SAPIS mode
34873 … (0x1<<2) // MSM Function RESET state's default value for pd_txreg in SAPIS mode
34875 … (0x1<<3) // MSM Function RESET state's default value for pd_vco in SAPIS mode
34877 … (0x1<<4) // MSM Function RESET state's default value for pd_vco_buf in SAPIS mode
34879 … (0x1<<5) // MSM Function RESET state's default value for reset_cdr in SAPIS mode
34881 … (0x1<<6) // MSM Function RESET state's default value for reset_cdr_gcrx in SAPIS mode
34883 … (0x1<<7) // MSM Function RESET state's default value for reset_dfe in SAPIS mode
34886 … (0x1<<0) // MSM Function RESET state's default value for reset_lnreg in SAPIS mode
34888 … (0x1<<1) // MSM Function RESET state's default value for reset_lnregh in SAPIS mode
34890 … (0x1<<2) // MSM Function RESET state's default value for reset_p2s in SAPIS mode
34892 … (0x1<<3) // MSM Function RESET state's default value for reset_ra in SAPIS mode
34894 … (0x1<<4) // MSM Function RESET state's default value for reset_s2p in SAPIS mode
34896 … (0x1<<5) // MSM Function RESET state's default value for reset_vco in SAPIS mode
34898 … (0x1<<6) // MSM Function RESET state's default value for txreg_bleed_ena in SAPIS mode
34900 … (0x1<<7) // MSM Function RESET state's default value for tx_lowpwr_idle_ena in SAPIS mode
34903 … (0x1<<0) // MSM Function RESET state's default value for cdr_en in SAPIS mode
34905 … (0x1<<1) // MSM Function RESET state's default value for rxbclk_en in SAPIS mode
34907 … (0x1<<2) // MSM Function RESET state's default value for rx_gate_en in SAPIS mode
34909 … (0x1<<3) // MSM Function RESET state's default value for reset_tx_clkdiv in SAPIS mode
34912 … (0x1<<0) // MSM Function NORMAL state's default value for iddq_sd in SAPIS mode
34914 … (0x1<<1) // MSM Function NORMAL state's default value for pd_dfe in SAPIS mode
34916 … (0x1<<2) // MSM Function NORMAL state's default value for pd_dfe_bias in SAPIS mode
34918 … (0x1<<3) // MSM Function NORMAL state's default value for pd_lnreg in SAPIS mode
34920 … (0x1<<4) // MSM Function NORMAL state's default value for pd_lnregh in SAPIS mode
34922 … (0x1<<5) // MSM Function NORMAL state's default value for pd_p2s in SAPIS mode
34924 … (0x1<<6) // MSM Function NORMAL state's default value for pd_ra in SAPIS mode
34926 … (0x1<<7) // MSM Function NORMAL state's default value for pd_s2p in SAPIS mode
34929 … (0x1<<0) // MSM Function NORMAL state's default value for pd_slv_bias in SAPIS mode
34931 … (0x1<<1) // MSM Function NORMAL state's default value for pd_txdrv in SAPIS mode
34933 … (0x1<<2) // MSM Function NORMAL state's default value for pd_txreg in SAPIS mode
34935 … (0x1<<3) // MSM Function NORMAL state's default value for pd_vco in SAPIS mode
34937 … (0x1<<4) // MSM Function NORMAL state's default value for pd_vco_buf in SAPIS mode
34939 … (0x1<<5) // MSM Function NORMAL state's default value for reset_cdr in SAPIS mode
34941 … (0x1<<6) // MSM Function NORMAL state's default value for reset_cdr_gcrx in SAPIS mode
34943 … (0x1<<7) // MSM Function NORMAL state's default value for reset_dfe in SAPIS mode
34946 … (0x1<<0) // MSM Function NORMAL state's default value for reset_lnreg in SAPIS mode
34948 … (0x1<<1) // MSM Function NORMAL state's default value for reset_lnregh in SAPIS mode
34950 … (0x1<<2) // MSM Function NORMAL state's default value for reset_p2s in SAPIS mode
34952 … (0x1<<3) // MSM Function NORMAL state's default value for reset_ra in SAPIS mode
34954 … (0x1<<4) // MSM Function NORMAL state's default value for reset_s2p in SAPIS mode
34956 … (0x1<<5) // MSM Function NORMAL state's default value for reset_vco in SAPIS mode
34958 … (0x1<<6) // MSM Function NORMAL state's default value for txreg_bleed_ena in SAPIS mode
34960 … (0x1<<7) // MSM Function NORMAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
34963 … (0x1<<0) // MSM Function NORMAL state's default value for cdr_en in SAPIS mode
34965 … (0x1<<1) // MSM Function NORMAL state's default value for rxbclk_en in SAPIS mode
34967 … (0x1<<2) // MSM Function NORMAL state's default value for rx_gate_en in SAPIS mode
34969 … (0x1<<3) // MSM Function NORMAL state's default value for reset_tx_clkdiv in SAPIS mode
34972 … (0x1<<0) // MSM Function PARTIAL state's default value for iddq_sd in SAPIS mode
34974 … (0x1<<1) // MSM Function PARTIAL state's default value for pd_dfe in SAPIS mode
34976 … (0x1<<2) // MSM Function PARTIAL state's default value for pd_dfe_bias in SAPIS mode
34978 … (0x1<<3) // MSM Function PARTIAL state's default value for pd_lnreg in SAPIS mode
34980 … (0x1<<4) // MSM Function PARTIAL state's default value for pd_lnregh in SAPIS mode
34982 … (0x1<<5) // MSM Function PARTIAL state's default value for pd_p2s in SAPIS mode
34984 … (0x1<<6) // MSM Function PARTIAL state's default value for pd_ra in SAPIS mode
34986 … (0x1<<7) // MSM Function PARTIAL state's default value for pd_s2p in SAPIS mode
34989 … (0x1<<0) // MSM Function PARTIAL state's default value for pd_slv_bias in SAPIS mode
34991 … (0x1<<1) // MSM Function PARTIAL state's default value for pd_txdrv in SAPIS mode
34993 … (0x1<<2) // MSM Function PARTIAL state's default value for pd_txreg in SAPIS mode
34995 … (0x1<<3) // MSM Function PARTIAL state's default value for pd_vco in SAPIS mode
34997 … (0x1<<4) // MSM Function PARTIAL state's default value for pd_vco_buf in SAPIS mode
34999 … (0x1<<5) // MSM Function PARTIAL state's default value for reset_cdr in SAPIS mode
35001 … (0x1<<6) // MSM Function PARTIAL state's default value for reset_cdr_gcrx in SAPIS mode
35003 … (0x1<<7) // MSM Function PARTIAL state's default value for reset_dfe in SAPIS mode
35006 … (0x1<<0) // MSM Function PARTIAL state's default value for reset_lnreg in SAPIS mode
35008 … (0x1<<1) // MSM Function PARTIAL state's default value for reset_lnregh in SAPIS mode
35010 … (0x1<<2) // MSM Function PARTIAL state's default value for reset_p2s in SAPIS mode
35012 … (0x1<<3) // MSM Function PARTIAL state's default value for reset_ra in SAPIS mode
35014 … (0x1<<4) // MSM Function PARTIAL state's default value for reset_s2p in SAPIS mode
35016 … (0x1<<5) // MSM Function PARTIAL state's default value for reset_vco in SAPIS mode
35018 … (0x1<<6) // MSM Function PARTIAL state's default value for txreg_bleed_ena in SAPIS mode
35020 … (0x1<<7) // MSM Function PARTIAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
35023 … (0x1<<0) // MSM Function PARTIAL state's default value for cdr_en in SAPIS mode
35025 … (0x1<<1) // MSM Function PARTIAL state's default value for rxbclk_en in SAPIS mode
35027 … (0x1<<2) // MSM Function PARTIAL state's default value for rx_gate_en in SAPIS mode
35029 … (0x1<<3) // MSM Function PARTIAL state's default value for reset_tx_clkdiv in SAPIS mode
35032 … (0x1<<0) // MSM Function SLUMBER state's default value for iddq_sd in SAPIS mode
35034 … (0x1<<1) // MSM Function SLUMBER state's default value for pd_dfe in SAPIS mode
35036 … (0x1<<2) // MSM Function SLUMBER state's default value for pd_dfe_bias in SAPIS mode
35038 … (0x1<<3) // MSM Function SLUMBER state's default value for pd_lnreg in SAPIS mode
35040 … (0x1<<4) // MSM Function SLUMBER state's default value for pd_lnregh in SAPIS mode
35042 … (0x1<<5) // MSM Function SLUMBER state's default value for pd_p2s in SAPIS mode
35044 … (0x1<<6) // MSM Function SLUMBER state's default value for pd_ra in SAPIS mode
35046 … (0x1<<7) // MSM Function SLUMBER state's default value for pd_s2p in SAPIS mode
35049 … (0x1<<0) // MSM Function SLUMBER state's default value for pd_slv_bias in SAPIS mode
35051 … (0x1<<1) // MSM Function SLUMBER state's default value for pd_txdrv in SAPIS mode
35053 … (0x1<<2) // MSM Function SLUMBER state's default value for pd_txreg in SAPIS mode
35055 … (0x1<<3) // MSM Function SLUMBER state's default value for pd_vco in SAPIS mode
35057 … (0x1<<4) // MSM Function SLUMBER state's default value for pd_vco_buf in SAPIS mode
35059 … (0x1<<5) // MSM Function SLUMBER state's default value for reset_cdr in SAPIS mode
35061 … (0x1<<6) // MSM Function SLUMBER state's default value for reset_cdr_gcrx in SAPIS mode
35063 … (0x1<<7) // MSM Function SLUMBER state's default value for reset_dfe in SAPIS mode
35066 … (0x1<<0) // MSM Function SLUMBER state's default value for reset_lnreg in SAPIS mode
35068 … (0x1<<1) // MSM Function SLUMBER state's default value for reset_lnregh in SAPIS mode
35070 … (0x1<<2) // MSM Function SLUMBER state's default value for reset_p2s in SAPIS mode
35072 … (0x1<<3) // MSM Function SLUMBER state's default value for reset_ra in SAPIS mode
35074 … (0x1<<4) // MSM Function SLUMBER state's default value for reset_s2p in SAPIS mode
35076 … (0x1<<5) // MSM Function SLUMBER state's default value for reset_vco in SAPIS mode
35078 … (0x1<<6) // MSM Function SLUMBER state's default value for txreg_bleed_ena in SAPIS mode
35080 … (0x1<<7) // MSM Function SLUMBER state's default value for tx_lowpwr_idle_ena in SAPIS mode
35083 … (0x1<<0) // MSM Function SLUMBER state's default value for cdr_en in SAPIS mode
35085 … (0x1<<1) // MSM Function SLUMBER state's default value for rxbclk_en in SAPIS mode
35087 … (0x1<<2) // MSM Function SLUMBER state's default value for rx_gate_en in SAPIS mode
35089 … (0x1<<3) // MSM Function SLUMBER state's default value for reset_tx_clkdiv in SAPIS mode
35187 …TXCTRL_MASTER_ATT_IN_OVR_3_0_K2_E5 (0xf<<0) // Override value for att in.
35260 …LOW_EN_O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a prog…
35262 …OW_EN_O_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor down to a prog…
35280 … (0x1<<6) // Set all DFE calibration values to mid-scale instead of usin…
35282 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
35284 …NT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
35286 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
35287 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
35288 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
35289 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
35290 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
35291 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
35292 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
35296 …CAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration for { Tap…
35305 …TE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
35366 …_5_0_K2_E5 (0x3f<<0) // Sets certain bits in training pattern as …
35370 …_E5 (0x1<<7) // Step calibration in test mode, rising ed…
35373 …_K2_E5 (0x7f<<0) // Enable average 4 in calibration, otherwi…
35378 …FT_O_3_0_K2_E5 (0xf<<0) // Shift the edge samples in rxeq_ctrl
35395 … 0x002bf8UL //Access:RW DataWidth:0x8 // Training pattern for boost in rate2
35397 …E2_BOOST_TRAINING_PATT_O_8_K2_E5 (0x1<<0) // Training pattern for boost in rate2
35399 … 0x002c00UL //Access:RW DataWidth:0x8 // Training pattern for boost in rate3
35401 …E3_BOOST_TRAINING_PATT_O_8_K2_E5 (0x1<<0) // Training pattern for boost in rate3
35404 …K2_E5 (0x3f<<0) // Sets certain bits in training pattern as don't care in rat…
35407 …K2_E5 (0x3f<<0) // Sets certain bits in training pattern as don't care in rat…
35410 …K2_E5 (0x3f<<0) // Sets certain bits in training pattern as don't care in rat…
35464 …E_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
35466 …DAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
35475 …2_E5 (0x1f<<0) // Bit 4 - latency check control enable Bit 3:0 - l…
35708 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35710 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35712 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35714 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35716 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35718 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35720 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35722 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35725 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35727 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35729 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35731 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35733 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35735 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35737 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35739 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35742 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35744 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35746 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35748 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35750 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35752 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35754 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35756 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35759 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35761 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35763 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35765 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35768 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35770 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35772 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35774 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35776 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35778 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35780 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35782 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35785 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35787 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35789 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35791 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35793 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35795 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35797 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35799 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35802 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35804 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35806 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35808 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35810 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35812 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35814 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35816 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35819 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35821 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35823 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35825 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35828 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35830 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35832 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35834 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35836 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35838 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35840 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35842 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35845 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35847 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35849 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35851 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35853 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35855 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35857 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35859 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35862 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35864 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35866 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35868 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35870 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35872 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35874 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35876 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35879 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35881 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35883 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35885 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35888 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35890 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35892 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35894 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35896 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35898 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35900 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35902 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35905 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35907 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35909 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35911 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35913 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35915 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35917 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35919 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35922 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35924 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35926 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35928 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35930 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35932 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35934 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35936 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35939 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35941 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35943 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35945 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35948 … (0x1f<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35951 … (0x1f<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
35973 …_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
36036 …X414_TXPRESET_COEFF_P0CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P0 C-1
36045 …X417_TXPRESET_COEFF_P1CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P1 C-1
36054 …X420_TXPRESET_COEFF_P2CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P2 C-1
36063 …X423_TXPRESET_COEFF_P3CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P3 C-1
36072 …X426_TXPRESET_COEFF_P4CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P4 C-1
36081 …X429_TXPRESET_COEFF_P5CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P5 C-1
36090 …X432_TXPRESET_COEFF_P6CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P6 C-1
36099 …X435_TXPRESET_COEFF_P7CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P7 C-1
36108 …X438_TXPRESET_COEFF_P8CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P8 C-1
36117 …X441_TXPRESET_COEFF_P9CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P9 C-1
36126 …444_TXPRESET_COEFF_P10CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P10 C-1
36169 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36171 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36173 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36175 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36177 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36179 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36181 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36183 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36186 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36188 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36190 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36192 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36194 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36196 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36198 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36200 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36203 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36205 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36207 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36209 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36211 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36213 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36215 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36217 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36220 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36222 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36224 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36226 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36229 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36231 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36233 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36235 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36237 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36239 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36241 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36243 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36246 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36248 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36250 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36252 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36254 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36256 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36258 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36260 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36263 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36265 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36267 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36269 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36271 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36273 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36275 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36277 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36280 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36282 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36284 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36286 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36289 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36291 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36293 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36295 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36297 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36299 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36301 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36303 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36306 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36308 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36310 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36312 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36314 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36316 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36318 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36320 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36323 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36325 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36327 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36329 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36331 … (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36333 … (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36335 … (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36337 … (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36340 … (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36342 … (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36344 … (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36346 … (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36348 … DataWidth:0x8 // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36349 … DataWidth:0x8 // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36350 … DataWidth:0x8 // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36351 … DataWidth:0x8 // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36353 … (0x7<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
36355 …- no auto deassertion; 1 - auto deassertion); [1] rst_pswrd_auto_mode (0- no auto deassertion; 1 -…
36356 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36358 …-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific bloc…
36360 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36362 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36364 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36366 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36380 …ccess:RW DataWidth:0x1 // Set/clr general attention 0; this will set/clr bit 48 in AEU vector.
36381 …cess:RW DataWidth:0x1 // Set/clr general attention 1; this will set/clr bit 49 in AEU vector.
36382 …cess:RW DataWidth:0x1 // Set/clr general attention 2; this will set/clr bit 50 in AEU vector.
36383 …cess:RW DataWidth:0x1 // Set/clr general attention 3; this will set/clr bit 51 in AEU vector.
36384 …ccess:RW DataWidth:0x1 // Set/clr general attention 4; this will set/clr bit 52 in AEU vector.
36385 …ccess:RW DataWidth:0x1 // Set/clr general attention 5; this will set/clr bit 53 in AEU vector.
36386 …ccess:RW DataWidth:0x1 // Set/clr general attention 6; this will set/clr bit 54 in AEU vector.
36387 …ccess:RW DataWidth:0x1 // Set/clr general attention 7; this will set/clr bit 55 in AEU vector.
36388 …ccess:RW DataWidth:0x1 // Set/clr general attention 8; this will set/clr bit 56 in AEU vector.
36389 …ccess:RW DataWidth:0x1 // Set/clr general attention 9; this will set/clr bit 57 in AEU vector.
36390 …cess:RW DataWidth:0x1 // Set/clr general attention 10; this will set/clr bit 58 in AEU vector.
36391 …cess:RW DataWidth:0x1 // Set/clr general attention 11; this will set/clr bit 59 in AEU vector.
36392 …cess:RW DataWidth:0x1 // Set/clr general attention 12; this will set/clr bit 60 in AEU vector.
36393 …cess:RW DataWidth:0x1 // Set/clr general attention 13; this will set/clr bit 61 in AEU vector.
36394 …cess:RW DataWidth:0x1 // Set/clr general attention 14; this will set/clr bit 62 in AEU vector.
36395 …cess:RW DataWidth:0x1 // Set/clr general attention 15; this will set/clr bit 63 in AEU vector.
36396 …cess:RW DataWidth:0x1 // Set/clr general attention 16; this will set/clr bit 64 in AEU vector.
36397 …cess:RW DataWidth:0x1 // Set/clr general attention 17; this will set/clr bit 65 in AEU vector.
36398 …cess:RW DataWidth:0x1 // Set/clr general attention 18; this will set/clr bit 66 in AEU vector.
36399 …cess:RW DataWidth:0x1 // Set/clr general attention 19; this will set/clr bit 67 in AEU vector.
36400 …cess:RW DataWidth:0x1 // Set/clr general attention 20; this will set/clr bit 68 in AEU vector.
36401 …cess:RW DataWidth:0x1 // Set/clr general attention 21; this will set/clr bit 69 in AEU vector.
36402 …cess:RW DataWidth:0x1 // Set/clr general attention 22; this will set/clr bit 70 in AEU vector.
36403 …cess:RW DataWidth:0x1 // Set/clr general attention 23; this will set/clr bit 71 in AEU vector.
36404 …cess:RW DataWidth:0x1 // Set/clr general attention 24; this will set/clr bit 72 in AEU vector.
36405 …cess:RW DataWidth:0x1 // Set/clr general attention 25; this will set/clr bit 73 in AEU vector.
36406 …cess:RW DataWidth:0x1 // Set/clr general attention 26; this will set/clr bit 74 in AEU vector.
36407 …cess:RW DataWidth:0x1 // Set/clr general attention 27; this will set/clr bit 75 in AEU vector.
36408 …cess:RW DataWidth:0x1 // Set/clr general attention 28; this will set/clr bit 76 in AEU vector.
36409 …cess:RW DataWidth:0x1 // Set/clr general attention 29; this will set/clr bit 77 in AEU vector.
36410 …cess:RW DataWidth:0x1 // Set/clr general attention 30; this will set/clr bit 78 in AEU vector.
36411 …cess:RW DataWidth:0x1 // Set/clr general attention 31; this will set/clr bit 79 in AEU vector.
36412 …cess:RW DataWidth:0x1 // Set/clr general attention 32; this will set/clr bit 80 in AEU vector.
36413 …cess:RW DataWidth:0x1 // Set/clr general attention 33; this will set/clr bit 81 in AEU vector.
36414 …cess:RW DataWidth:0x1 // Set/clr general attention 34; this will set/clr bit 82 in AEU vector.
36415 …cess:RW DataWidth:0x1 // Set/clr general attention 35; this will set/clr bit 83 in AEU vector.
36422 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36424 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36426 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36431 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36433 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36435 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36440 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36442 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36444 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36449 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36451 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36453 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36458 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36460 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36462 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36467 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36469 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36471 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36476 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36478 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36480 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36485 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36487 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36489 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36494 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36496 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36498 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36503 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36505 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36507 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36512 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36514 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36516 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36521 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36523 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36525 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36530 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36532 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36534 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36539 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36541 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36543 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36548 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36550 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36552 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36557 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36559 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36561 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36566 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36568 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36570 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36575 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36577 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36579 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36584 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36586 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36588 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36593 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36595 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36597 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36602 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36604 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36606 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36611 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36613 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36615 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36620 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36622 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36624 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36629 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36631 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36633 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36636 …0x008800UL //Access:RW DataWidth:0x1 // The System Kill enable: 0 - none; 1 - hard reset. Res…
36640 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36642 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36644 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36655 …m_attn; [6] one clears PERST_N assertion (goes 0); [7] one clears PERST_N de-assertion (goes 1). […
36657 …ister results with the clear of the latched signals; [0] - clears pglue_misc_vpd_attn[0], [1] - cl…
36659 … 0x00883cUL //Access:RW DataWidth:0x9 // Attention sticky number - latches first attent…
36660 …s:RW DataWidth:0x2 // Port mode. 0 - single port; 1 - 2 ports; 2 - 4 ports. 2 is prohibited c…
36661 … Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 1x …
36662 …s is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 10 - Tri Port…
36663 …- disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port. Port…
36664 …ync FIFOs should be bypassed in latency-critical paths. bit0 - clock mux control (Obsolete), bit1 …
36665 …yte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on …
36667 …- Storms stall is disallowed; AEU unifier bit[7] output to MCP is disabled; 1 - All Storms are for…
36668 …c20UL //Access:RW DataWidth:0x17 // 23 bit GRC address where the scratch-pad of the MCP that i…
36669 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36670 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36671 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36672 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36673 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36674 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36675 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36676 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36685 …e bit will clear the appropriate event to the AEU (if the attn bit (bit 2) in the MISC_REGISTERS_S…
36701 …he counter for sw timers1-8. there are 8 addresses in this register. address 0 - timer 1; address …
36703 …- no auto deassertion; 1 - auto deassertion); [1] rst_umac_on_core_rst (0- no auto deassertion; 1 …
36704 …- is not reset on hard reset; 1 - is reset on hard reset); [1] rst_n_hard_misc_rbc_pcie (0 - is no…
36705 …in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a bl…
36707 …in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a bl…
36709 … frequency (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G mode. In AH it co…
36710 …en programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 1…
36711 …- source of privilege level, 0 - the source is external pin, 1 - the source are bits[2:1] of this …
36712 … // Privilege level as defined by external pin. 0 - non-secured mode; 1 - secured mode; 2 - full…
36713 …-disable to the NVM block is generated. '0' - PROTECT: This value protects the NVM from any writes…
36714 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36716 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36718 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36720 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36722 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36724 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36726 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36728 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36730 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36732 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36734 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36736 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36738 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36740 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36742 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36744 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36746 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
36748 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
36750 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
36752 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
36754 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
36756 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
36758 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
36760 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
36762 …in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a bl…
36892 …state of the ptw_miscs_pcie_link_up signal which is driven by the PCIE core - a pulse at the begin…
36893 …ate of the ptw_miscs_pcie_hot_reset signal which is driven by the PCIE core - a pulse at the begin…
36894 …RW DataWidth:0x10 // Accounts for HOT RESET assertion when the chip is in prepared state. Is r…
36895 … DataWidth:0x10 // Accounts for HOT RESET assertion when the chip is in un-prepared state. Is …
36897 …Width:0x1 // Set to 1 when main PLL lock indication is de-asserted when hard reset is de-assert…
36898 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36899 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36900 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36901 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36902 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36903 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36904 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36905 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36906 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36907 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36908 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36909 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36910 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36911 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36912 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36913 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36914 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36915 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36916 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36917 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36918 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36919 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36920 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36921 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36922 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36923 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36924 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36925 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36926 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36927 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36928 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36929 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36996 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
36997 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
36998 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
36999 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37000 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37001 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37002 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37003 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37004 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37005 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37006 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37007 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37008 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37009 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37010 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37011 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37012 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37013 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37014 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37015 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37016 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37017 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37018 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37019 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37020 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37021 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37022 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37023 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37024 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37025 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37026 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37027 …in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding…
37029 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
37031 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
37033 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
37035 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
37037 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
37039 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
37041 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
37043 …In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and ano…
37046 … 0x009654UL //Access:RW DataWidth:0x3 // Bit[0]: PERST# IO de-assertion. If == 1, t…
37047 … PERST# de-assert. Bit[1]: WAKE control � direct MFW control of the WAKE# IO. Set to 1 to asserts …
37048 … //Access:RW DataWidth:0x1 // When 0, indicated PCIE EP controller is in reset, except for PM…
37049 …0x009660UL //Access:RW DataWidth:0x1 // When 0, indicated PCIE PHY is in reset Refer to PCIE …
37050 …0x0096b8UL //Access:R DataWidth:0x1 // Chip core_rst_n status. 0 - asserted; 1 - de-asserted.
37051 …in conjunction with MISC_REGISTERS_LINK_HOLDOFF_REQ.LINK_HOLDOFF_REQ . Bit 1 : LINK_HOLDOFF_FAILUR…
37059 …in the MCP register space; but this bit needs to be set to make use of that. Bit[3:1] spare. Bit[4…
37061 …- spare RW register reset by por reset; [10:8] : PCIe Device Type: 3'b000 - Endpoint mode; 3'b010 …
37063 … DataWidth:0x2 // 0-bypass the Vmain PORBG. for Vmain POR; if sel=1 the output wil be MISC_REGI…
37064 …// Bypass to the FUNC_HIDE pin. Bit 0 - bypass select; Bits[15:1] - bypass value per function (1 -…
37069 … DataWidth:0x1 // NIG debug mux vector control. 0 - NIG0 debug vector is output to IFMUX; 1 -…
37070 …nig_mux_4port_shared_mdio_en output. Applicable both in 2-port and 4-port mode. TBD: unconnected i…
37071 …- path0 gmii/mii emac debug outputs are selected by NIG; If 1 - path1 gmii/mii emac debug outputs …
37072 …s:R DataWidth:0x2 // SEL_VAUX_B - Control to power switching logic. [0] - output value drive…
37075 …same mapping E2 and E3 have. If the bit is set then those PFs are coupled. In this case the even P…
37076 … DataWidth:0x1 // This bit will be set by the MCP when the device works in PDA mode. The value …
37077 …ware mode defined defaults. Global register. Reset on Hard reset. TBD: unconnected in NM. Reserved.
37078 …-chip PHY devices and MAC ports to the four MDIO domains. It is only used when MISC_REGISTERS_MDIO…
37079 …is asserted (Hot Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state. Res…
37082 …it as a '1' will cause the chip to do an internal reset exactly like a power-up reset. There is no…
37083 …in the MISC_REGISTERS_MAIN_SEQ_BYP_VAL.MAIN_SEQ_BYP_VAL affects the controls; when reset; the SM a…
37084 …in the MISC_REGISTERS_MAIN_SEQ_BYP_SEL.MAIN_SEQ_BYP_VAL is set; when reset; the SM affects the con…
37085 …09744UL //Access:RW DataWidth:0x1 // Writing to this register results in resetting entire chi…
37087 …-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bi…
37088 …0UL //Access:RW DataWidth:0x1 // [0]clock storm bypass: 0-select Storm SPLL clock; 1-select e…
37089 … by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset…
37090 … by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset…
37091 … the Driver to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset…
37092 … 0x009760UL //Access:R DataWidth:0x1 // 0 - VAUX is not present (external pin is 0); 1 …
37093 …-6] RESERVED (FLOAT: these IOs are outputs only). [5-4] CLR: When any of these bits is written as …
37096 … the chip. This value starts at 0x0 for the A0 tape-out and increments by one for each all-layer t…
37097 …f the chip. This value starts at 0x00 for each all-layer tape-out and increments by one for each t…
37099 …hat the link is down and PCIE is prepared for operation off of VAUX. TBD: set to 0 in NM. Reserved.
37100 …management only. The PCI power will always read as '0' in this state; as if the chip is in Out-Of-…
37103 … 0x00978cUL //Access:RW DataWidth:0x10 // Accounts for Hard reset de-assertion. Is reset o…
37105 … 0x009794UL //Access:RW DataWidth:0x10 // Accounts for Core de-reset assertion. Is r…
37107 … 0x00979cUL //Access:RW DataWidth:0x10 // Accounts for PERST_B reset de-assertion. Is reset o…
37108 …RW DataWidth:0x10 // Accounts for PCI_RST_N assertion when the chip is in prepared state. Is r…
37109 … DataWidth:0x10 // Accounts for PCI_RST_N assertion when the chip is in un-prepared state. Is …
37110 … 0x0097a8UL //Access:RW DataWidth:0x10 // Accounts for PCI_RST_N de-assertion. Is reset o…
37111 …in un-prepared state, hard reset is asserted. When =0, when ptw_miscs_pcie_hot_reset is asserted (…
37113 …UL //Access:RW DataWidth:0x20 // Eco reserved. Global register. [31:30] - used to programm loo…
37118 …97c8UL //Access:RW DataWidth:0x11 // Indirect address. Used to addrerss a register in avs_top.
37120 …r-ride: When set, over-ride DAC code from AVS monitor with on from this register [20:11] VMgmt DAC…
37121 …- Per-TC packet available status; [10] - STORM FIFO; [9] - BTB SOP FIFO for engine 0; [8] - BTB S…
37122 …- STORM FIFO almost full; [10] - STORM FIFO full; [9] - BTB SOP FIFO full for engine 0; [8] - …
37123 …- Received packet from BTB IF0 of engine 0; [6] - Received packet from BTB IF0 of engine 1; [5] …
37124 …- storm_init_crd: Credits for the output STORM Packet interface. [3:2] - storm_pkt_dst: Select t…
37125 …-full Threshold. [29:25] - Btb_if0_fifo_almfull_thr: Almost-full threshold for BTB main traffic F…
37133 …ll continue to read as a '1' until the command register is written with a '1' in this bit position.
37135 …ll continue to read as a '1' until the command register is written with a '1' in this bit position.
37138 … (0x1<<0) // This bit will read '1' if there is a valid byte to read in dbu_rxdata. Once dbu…
37140 …1<<1) // This bit will read '1' if there is data pending to be transmitted in the txdata register.…
37143 … // When this bit is set, the UART timing will be determined by the values in the dbu_timing regis…
37150 …in that the start bit should be sampled. The default value of 0x6C results in 115200 baud operatio…
37152 …its set the number of core_clock cycles in between bits for both rx and tx. The default value of 0…
37154 …tes that the data currently in bits 7:0 of this register was received in error. This bit is valid …
37155 …data on the serial interface. Firmware should poll the txdata_occupied bit in the status register …
37165 …ction is done by PFID[0]. When 1, the path selection is done by the PATHID field in this register.
37167 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
37168 … enable. If 0 - the acknowledge input is disregarded; valid is deasserted; full is asserted; all o…
37169 …t;Master) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
37231 … 0x00c400UL //Access:RW DataWidth:0x4 // DMAE- PCI Request Interfac…
37232 …404UL //Access:RW DataWidth:0x1 // Relaxed ordering. 0-strict PCI ordering is used;1-PCI-X re…
37233 … 0x00c408UL //Access:RW DataWidth:0x1 // 0-PCI type cache snoop protection is required;…
37234 …00c40cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 initial value is all zeroes; if 1 - t…
37235 … //Access:RW DataWidth:0x1 // If 0 - the CRC-16 final calculation result isn't byte swapped; …
37236 …0c414UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16c initial value is all zeroes; if 1 - t…
37237 …c418UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 T10 initial value is all zeroes; if 1 -…
37238 …00c41cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-32 initial value is all zeroes; if 1 - t…
37239 … //Access:RW DataWidth:0x1 // If 0 - the CRC-32 final calculation result isn't byte swapped; …
37240 …0c424UL //Access:RW DataWidth:0x1 // If 0 - the CRC-32c initial value is all zeroes; if 1 - t…
37241 …//Access:RW DataWidth:0x1 // If 0 - the CRC-32c final calculation result isn't byte swapped; …
37242 …0x00c42cUL //Access:RW DataWidth:0x1 // If 0 - the final checksum equal 0 won't be changed;if…
37243 …st ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; …
37244 …st ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; …
37245 …38UL //Access:RW DataWidth:0x1 // When set discards 1- or 2-Dword PCI transaction read in cas…
37246 … 0x00c43cUL //Access:RW DataWidth:0x14 // GRC address in case 1- or 2-Dword PCI tran…
37248 … (0x1ff<<0) // Steering Tag Index (value of 0x1FF means no steering tag in which case steering …
37250 …- Bidirectional shared data structure; 01 - Device writes/reads then device reads/writes soon; 10 …
37255 …in FID: 0 - VN Virtualized NIC (Used for VF access); 1 - PDA Physical Device Assignment (Assigned …
37262 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
37272 …- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other e…
37273 …- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other e…
37281 …as follows: 0-NONE; 1-DoubleBwTx (DoubleBw the TX side); 2-DoubleBwRx (DoubleBw the RX side); 3-Cr…
37282 …ts are a client index for slot 0 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37283 …ts are a client index for slot 1 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37284 …ts are a client index for slot 2 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37285 …ts are a client index for slot 3 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37286 …ts are a client index for slot 4 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37287 …ts are a client index for slot 5 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37288 …ts are a client index for slot 6 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37289 …ts are a client index for slot 7 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37290 …ts are a client index for slot 8 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37291 …ts are a client index for slot 9 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37292 …s are a client index for slot 10 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37293 …s are a client index for slot 11 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37294 …s are a client index for slot 12 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37295 …s are a client index for slot 13 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37296 …s are a client index for slot 14 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37297 …s are a client index for slot 15 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 i…
37298 …e next slot to support lower rates (During the number of cycles configured in the DBG_REGISTERS_CA…
37299 …- 128b STORM (A and B) data is logged 1 - 64b STORM (A and B) data + 4 different (in general case)…
37300 …only: These bits indicate the target of the debug data: 0 - internal buffer; 1 - NIG; 2 - PCI.
37301 …-one shot (newest data is thrown) as follows: (a) When DBG_REGISTERS_DEBUG_TARGET =0 (internal buf…
37320 …e read from the external buffer; WB Read Only (write request will not be acknowledged); (in bytes).
37322 …when DBG_REGISTERS_DEBUG_TARGET =1 (NIG) and DBG_REGISTERS_FULL_MODE =0 (one-shot); WB Read Only (…
37332 …Debug only: These bits indicate the value of the external PCI buffer size in target_packet_size c…
37333 …rget_packet_size data byte each); Relevant only when debug_target=1 (NIG) & full_mode=0 (one-shot).
37340 …in case the internal buffer is almost full as follows: (a) 1 - no grants will be made to the stor…
37341 …in the internal buffer under which the full would go high; not applicable when DBG_REGISTERS_DEBUG…
37342 … This bit indicates logical/physical address in PCI request as follows: (a) 1 - logical address;…
37343 … to internal buffer to be output to IFMUX interface. 0 - bits[31:0] 1 - bits[63:32] 2:6 - etc. 7 -…
37344 …-like mechanism to set SEMI grant. When the number of empty lines of 512b in internal buffer is le…
37345 …on is done as follows: bits 255:0 - data; bits 263:256 - frame; bits 271:264 - valid; bits 303:272…
37347 …ing to stored in the internal buffer; to allow recognize sop the following should be applied: trig…
37349 …tor as follows: (a) 1 - bit is masked. This bit won't be compared with the DBG_REGISTERS_EXPECTED…
37351 … pattern recognition feature is disabled/enabled as follows: (a) 1 - disabled; (b) 0 - enabled;.
37352 …nition feature as follows: (a) 1 - stop debug data storgae when the expected pattern is initially…
37353 …in the dbg block until/from pattern recognition initial event; or stored only in cycles of a patte…
37354 … // (a) 0 - trigger machine is off (all data will bypass the triggering machine); dbg_sem_trgr_…
37355 …010550UL //Access:RW DataWidth:0x1 // (a) 0 - triggering interleaved messages is disabled. (b…
37356 … to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits…
37357 … to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits…
37358 … to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits…
37359 …DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 …
37360 …DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 …
37361 …DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 …
37362 …/Access:RW DataWidth:0x2 // Next state in the fsm triggering machine if the referred constrai…
37363 …/Access:RW DataWidth:0x2 // Next state in the fsm triggering machine if the referred constrai…
37364 …/Access:RW DataWidth:0x2 // Next state in the fsm triggering machine if the referred constrai…
37365 …/Access:RW DataWidth:0x2 // Next state in the fsm triggering machine if the referred constrai…
37366 …/Access:RW DataWidth:0x2 // Next state in the fsm triggering machine if the referred constrai…
37367 …/Access:RW DataWidth:0x2 // Next state in the fsm triggering machine if the referred constrai…
37374 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37375 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37376 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37377 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37378 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37379 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37380 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37381 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37382 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37383 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37384 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37385 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37386 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37387 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37388 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37389 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37390 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37391 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37392 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37393 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37394 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37395 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37396 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37397 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37422 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37423 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37424 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37425 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37426 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37427 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37428 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37429 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37430 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37431 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37432 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37433 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37434 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37435 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37436 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37437 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37438 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37439 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37440 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37441 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37442 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37443 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37444 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37445 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37446 … 0x0106bcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37447 … 0x0106c0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37448 … 0x0106c4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37449 … 0x0106c8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37450 … 0x0106ccUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37451 … 0x0106d0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37452 … 0x0106d4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37453 … 0x0106d8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37454 … 0x0106dcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37455 … 0x0106e0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37456 … 0x0106e4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37457 … 0x0106e8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37458 … 0x0106ecUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37459 … 0x0106f0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37460 … 0x0106f4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37461 … 0x0106f8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37462 … 0x0106fcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37463 … 0x010700UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37464 … 0x010704UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37465 … 0x010708UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37466 … 0x01070cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37467 … 0x010710UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37468 … 0x010714UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37469 … 0x010718UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37470 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37471 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37472 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37473 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37474 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37475 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37476 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37477 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37478 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37479 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37480 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37481 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37482 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37483 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37484 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37485 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37486 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37487 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37488 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37489 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37490 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37491 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37492 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37493 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37614 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37615 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37616 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37617 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37618 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37619 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37620 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37621 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37622 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37623 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37624 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37625 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37626 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37627 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37628 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37629 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37630 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37631 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37632 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37633 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37634 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37635 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37636 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37637 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37662 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37663 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37664 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37665 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37666 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37667 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37668 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37669 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37670 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37671 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37672 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37673 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37674 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37675 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37676 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37677 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37678 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37679 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37680 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37681 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37682 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37683 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37684 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37685 …W DataWidth:0x2 // (a) 00: direct: use the value which was configured in the trigger_state_se…
37686 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37687 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37688 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37689 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37690 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37691 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37692 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37693 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37694 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37695 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37696 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37697 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37698 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37699 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37700 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37701 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37702 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37703 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37704 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37705 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37706 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37707 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37708 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37709 …in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (…
37713 … 0x010968UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37714 … 0x01096cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37715 … 0x010970UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37717 …RW DataWidth:0x3 // If set then record data in relevant state; If clear then do not record d…
37718 …in relevant state (fsm triggering machine) from beginning of message to the data that should be re…
37719 …in relevant state (fsm triggering machine) from beginning of message to the data that should be re…
37720 …in relevant state (fsm triggering machine) from beginning of message to the data that should be re…
37724 …corded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnst…
37725 …corded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnst…
37726 …corded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnst…
37727 …_offset cycles after start of message (during triggering machine operation in state trigger_indire…
37728 …RW DataWidth:0x3 // If set then record data in relevant state; If clear then do not record d…
37729 …in relevant state (fsm triggering machine) from beginning of message to the data that should be re…
37730 …in relevant state (fsm triggering machine) from beginning of message to the data that should be re…
37731 …in relevant state (fsm triggering machine) from beginning of message to the data that should be re…
37735 …corded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnst…
37736 …corded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnst…
37737 …corded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnst…
37738 …_offset cycles after start of message (during triggering machine operation in state trigger_indire…
37739 …- Filter off; in that case all data should be transmitted to the internal buffer without any filte…
37740 … to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits…
37741 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37742 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37743 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37744 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37749 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37750 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37751 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37752 …/Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the above data vecto…
37753 … 0x010a08UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37754 … 0x010a0cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37755 … 0x010a10UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37756 … 0x010a14UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37761 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37762 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37763 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37764 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37789 …in the filter_cnstr_datai.(b) 01: indirect: use the recorded value 0 from of fsm triggering machin…
37790 …in the filter_cnstr_datai.(b) 01: indirect: use the recorded value 0 from of fsm triggering machin…
37791 …in the filter_cnstr_datai.(b) 01: indirect: use the recorded value 0 from of fsm triggering machin…
37792 …in the filter_cnstr_datai.(b) 01: indirect: use the recorded value 0 from of fsm triggering machin…
37793 …in case the operation is NOT (equal or not equal) (filter_cnstr_oprtni > 000 or 101) (a) 0 - reg…
37794 …in case the operation is NOT (equal or not equal) (filter_cnstr_oprtni > 000 or 101) (a) 0 - reg…
37795 …in case the operation is NOT (equal or not equal) (filter_cnstr_oprtni > 000 or 101) (a) 0 - reg…
37796 …in case the operation is NOT (equal or not equal) (filter_cnstr_oprtni > 000 or 101) (a) 0 - reg…
37798 … 0x010a7cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37800 …cess:RW DataWidth:0x8 // The message length-1 of the recorded part size in terms of numbers o…
37801 …nt: (a) 00 - record from time=0; (b) 01 - record rcrd_on_window_pre_num_chunks chunks to internal…
37802 … (a) 0- enable recording data upon triggering event; in that case record for rcrd_on_window_post_…
37803 …in the internal buffer is the most recent data prior to the triggering event. (4) rcrd_on_window_p…
37804 …ndow_post_trgr_evnt_mode=0; (2) value of 0xffffffff (maximum value) result in recording of unlimit…
37805 … 0x010a98UL //Access:RW DataWidth:0x10 // 16-bit opaque FID for pc…
37814 … // Used for triggering on driver assertions. For example this can be used in Emulation when The d…
37815 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37816 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37817 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37818 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37819 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37820 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37821 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37822 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37823 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37824 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37825 …- bits[31:0]; [5:3] - bits[63:32]; [8:6] - bits[95:64]; [11:9] - bits[127:96]; [14:12] - bits…
37826 …ll be added to trailer when STORM will be selected: B2:0 - TSEM; B5:3- MSEM; B8:6- USEM; B11:9- XS…
37835 …0x4 // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 M…
37836 … to NIG or PXP target is in granularity of chunks. The allowed range is 1-48 that suits to packet …
37844 …tput from DBG to SEM block as result of trigger event: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is …
37845 …aWidth:0x2 // Current state machine status of trigger block in dbg_trigger.v: states 0-2 are fu…
37846 …tus of trigger block in dbg_trigger_state.v: : state 0 - NOT_HNDLR_MSG; state 1- FRST_HNDLR_MSG; s…
37847 … DataWidth:0x10 // Counter for number of times set 0 appeared in current state in dbg_trigger…
37848 … DataWidth:0x10 // Counter for number of times set 1 appeared in current state in dbg_trigger…
37849 …- constraint 0 set0; B1 - constraint 1 set0; B2 - constraint 2 set0; B3 - constraint 3 set0; B4 - …
37851 …DataWidth:0x20 // Debug only: These bits represent the total number of 128-bit cycles sent from …
37855 …rrent state status in trailer block : 0 - WAIT_FOR_NEW_LINE; 1- END_OF_CHUNK; 2 - SEND_ADDITIONAL_…
37856 … 0x010b8cUL //Access:R DataWidth:0x6 // Debug only: number of valid dwords in trailer block.
37857 … // Statistics. Match constraint status. B0 - constraint 0; B1 - constraint 1; B2 - constraint …
37862 … 0x010ba4UL //Access:R DataWidth:0x8 // Number of empty lines in internal buffer.
37863 …o 0 - only client which HW ID is defined in DBG_REGISTERS_FILTER_ID_NUM.FILTER_ID_NUM is logged. W…
37864 …ccess:RW DataWidth:0x1 // When 0 - SEMI core A is selected for all trigger/filter related act…
37873 …in the next field. This bit should be set to Low and high again for the next command execution to…
37876 …in burst mode; [1]: cmd_done: Command Done, This signal indicates the completion of the command; […
37878 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37887 … 0x020218UL //Access:RW DataWidth:0x1 // XCORE_BIAS in normal operation is …
37888 … 0x02021cUL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
37893 … 0x020220UL //Access:RW DataWidth:0x1 // HIPASS in normal operation is …
37897 …hen pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases.
37908 … 0x020238UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
37909 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37911 … 0x02023cUL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3)…
37949 …hen pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases.
37957 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
37960 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
37965 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37966 … 0x020264UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
37967 … 0x020268UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
37968 … 0x020268UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
37970 … 0x02026cUL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-2 000000…
37973 … 0x020270UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-3 000000…
37976 … 0x020274UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-4 000000…
37979 … 0x020278UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-5 000000…
37984 …hen pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases.
37986 … 0x020284UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
37988 … 0x020288UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3)…
37991 … 0x02028cUL //Access:R DataWidth:0x4 // Delay for each channel 2-5 is completed.
38003 …refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay…
38006 …refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay…
38008 … 0x02029cUL //Access:RW DataWidth:0x3 // Loop gain in frequency acquisitio…
38019 … 0x0202b4UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
38020 … 0x0202b4UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset i…
38022 …0x0202b8UL //Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset i…
38024 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38026 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
38030 … 0x0202c8UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38032 … 0x0202ccUL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38033 … 0x0202d0UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
38035 … 0x0202d4UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3)…
38036 …refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay…
38038 …refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay…
38041 … 0x0202dcUL //Access:RW DataWidth:0x3 // Loop gain in frequency acquisitio…
38044 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38045 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38046 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38048 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38049 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38050 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38052 …2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is clea…
38053 …2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is clea…
38054 …2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is clea…
38061 … 0x0202f4UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset i…
38062 …04a4UL //Access:W DataWidth:0x1 // Setting this bit high will result in the HW to capture th…
38063 …0298UL //Access:W DataWidth:0x1 // Setting this bit high will result in the HW to capture th…
38064 …02f8UL //Access:W DataWidth:0x1 // Setting this bit high will result in the HW to capture th…
38065 …0x0202f8UL //Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset i…
38069 …ween measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*…
38071 … (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in …
38073 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38077 …ween measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*…
38079 … (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in …
38084 …ween measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*…
38086 … (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in …
38088 … 0x020304UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38089 … 0x0204b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38090 … 0x0202a8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38091 … 0x020308UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38092 … 0x020308UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38093 … 0x0204b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38094 … 0x0202acUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38095 … 0x02030cUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38097 … 0x0204bcUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38098 … 0x0202b0UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38099 … 0x020310UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38100 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38101 … 0x0204c0UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38102 … 0x0202b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38103 … 0x020314UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38104 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38105 … 0x0204c4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38106 … 0x0202b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38107 … 0x020318UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38108 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38109 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38110 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38111 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38117 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38118 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38119 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38120 … 0x020324UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL digita…
38121 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38122 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38123 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38129 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38130 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38131 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38133 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38134 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38135 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38136 … 0x020334UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset i…
38140 … (0xff<<0) // Strap value on TEST IN pins
38144 …0x020338UL //Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset i…
38152 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN go…
38156 … (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# g…
38174 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38212 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN go…
38216 … (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# g…
38234 … 0x020344UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38242 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN go…
38246 … (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# g…
38264 … 0x020348UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38268 …-bit compliance enable pins on the ballout. These bits are used to override the pins if needed. 2'…
38273 …ss:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_contro…
38274 …ss:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_contro…
38275 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38276 …Width:0x5 // select the cam instance when reading the status of the cam in tcam_bist_status 0 c…
38277 …Width:0x5 // select the cam instance when reading the status of the cam in tcam_bist_status 0 c…
38278 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38279 …am bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist…
38280 …am bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist…
38281 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38282 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38283 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38285 …- bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - re…
38286 …- bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - re…
38288 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38289 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38290 … 0x020364UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL digita…
38291 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38292 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38294 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38295 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38297 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38298 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38300 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38301 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38303 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38304 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38306 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38307 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38309 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38310 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38312 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38313 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38315 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38316 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38318 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38319 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38321 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38322 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38324 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38325 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38327 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38328 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38329 … 0x020398UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38330 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38331 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38332 … 0x02039cUL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38362 … 0x0203c4UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38363 …0368UL //Access:RW DataWidth:0x6 // Sets the CTL# (# in [0..5]) I/Os of the PADS in non - sca…
38365 … 0x0203c8UL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38366 …2036cUL //Access:RW DataWidth:0x2 // Sets the SL# (# in [0..1]) I/Os of the PADS in non - sca…
38368 … 0x0203ccUL //Access:R DataWidth:0x8 // PCIe lock signals. 0-unlocked; 1-locked. Global …
38372 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38373 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38386 …1 : powers down for the analog front end and turns off all clocks except refclk. MDIO is operation…
38406 … (0x1<<12) // 1: Running in SGMII mode. Global R…
38412 … (0x1<<1) // 1 : Hold the VTMON in powerdown state.
38414 …//Access:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the…
38420 … (0x1<<1) // 1 : Hold the VTMON in powerdown state.
38422 …//Access:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the…
38424 …cal 0: Normal Operation Mode 1: Powerdown the RESCAL block Transition from 1->0 to start calibrati…
38429 …refclk 1'b1: 16 refclk [8:7] power-up time before starting calibration 2'b00: 32 refclk = 1.28us 2…
38431 … (0x1<<0) // Indicates if the calibraion operation is done. 0: Calibration in progress 1: Calibrat…
38435 … On-chip Sheet Resistance 0000 -24% ~ -21% 0001 -21% ~ -18% 0010 -18% ~ -15% 0011 -15% ~ -12% 0100…
38443 … 0x020458UL //Access:RW DataWidth:0x1 // Reset the Registers in VManagement Switchin…
38446 … 0x020464UL //Access:RW DataWidth:0x1 // Reset the Registers in VMain Switching Regu…
38449 … 0x020470UL //Access:RW DataWidth:0x1 // Reset the Registers in VAnalog Switching Re…
38452 … 0x02047cUL //Access:RW DataWidth:0x1 // Reset the Registers in V1p8 Switching Regul…
38456 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38457 …2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is clea…
38458 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38460 …ween measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*…
38462 … (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in …
38464 …ccess:R DataWidth:0x20 // These bits represent the 256-bits of the configuration space in the…
38465 …ccess:R DataWidth:0x20 // These bits represent the 256-bits of the configuration space in the…
38466 …ccess:R DataWidth:0x20 // These bits represent the 256-bits of the configuration space in the…
38467 …ccess:R DataWidth:0x20 // These bits represent the 256-bits of the configuration space in the…
38468 …ccess:R DataWidth:0x20 // These bits represent the 256-bits of the configuration space in the…
38469 …ccess:R DataWidth:0x20 // These bits represent the 256-bits of the configuration space in the…
38470 …ccess:R DataWidth:0x20 // These bits represent the 256-bits of the configuration space in the…
38471 …ccess:R DataWidth:0x20 // These bits represent the 256-bits of the configuration space in the…
38481 …in the LPI request logic. When this mode is enabled, CPMU will not exit LPI at the earliest indica…
38483 …ataWidth:0x20 // This register sets the Sleep Threshold for the LPI mode in the Batch and Burst …
38497 … (0x1<<6) // 0 : PCIe in D3 State is not part of LPI request generation logic.…
38508 … (0x1<<3) // This bit will be used in the Batch and Burst mode. In this …
38510 … (0x1<<4) // This bit will be used in the Batch and Burst mode. In this …
38512 … (0x1<<5) // This bit will be used in the Normal mode. In this mode,…
38516 …is bit will not automatically guarantee an exit from LPI if other elements in the LPI equation is …
38539 …er sets the short timer threshold for OBFF operation w.r.t memory requests in 40ns resolution. The…
38540 …ter sets the long timer threshold for OBFF operation w.r.t memory requests in 40ns resolution. The…
38541 …ister sets the short timer threshold for OBFF operation w.r.t IGU requests in 40ns resolution. The…
38542 …gister sets the long timer threshold for OBFF operation w.r.t IGU requests in 40ns resolution. The…
38543 …Setting each bit in this register to "1" will cause the CPMU to launch a timer when the correspond…
38544 …Setting each bit in this register to "1" will cause the CPMU to launch a timer when the correspond…
38545 …Setting each bit in this register to "1" will cause the CPMU to launch a timer when the correspond…
38546 …Setting each bit in this register to "1" will cause the CPMU to launch a timer when the correspond…
38596 … (0x1<<2) // This bit will be used in the Normal mode. In this mode,…
38601 …. 1 : Entry to PCIe L1 is enabled. This reflects the CPMU output and it is in addition to PCIE COR…
38629 … (0x1<<1) // This bit will be used in the Normal mode. In this mode,…
38631 …his bit will not automatically guarantee an exit from L1 if other elements in the L1 equation is c…
38665 … (0x1<<1) // This bit will be used in the Normal mode. In this mode,…
38667 …is bit will not automatically guarantee an exit from LTR if other elements in the LTR equation is …
38740 …in the register will result in the clock generation logic to send 1 clock pulse through for every …
38741 …in the register will result in the clock generation logic to send 1 clock pulse through for every …
38742 …in the register will result in the clock generation logic to send 1 clock pulse through for every …
38743 …in the register will result in the clock generation logic to send 1 clock pulse through for every …
38787 … (0x1<<21) // 0 : PCIE in D3 is not part of Main Clock slowdown logic. 1 :…
38841 … (0x1<<21) // 0 : PCIE in D3 is not part of Storm Clock slowdown logic. 1 :…
38895 … (0x1<<21) // 0 : PCIE in D3 is not part of NW Clock slowdown logic. 1 : …
38949 … (0x1<<21) // 0 : PCIE in D3 is not part of PCI Clock slowdown logic. 1 : …
39186 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in LPI state. this is a…
39188 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in RX LPI state. this i…
39190 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in LPI state. this is a…
39192 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in Stall Memory state. …
39194 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in Stall Intterupt stat…
39196 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in L1 state. this is a …
39198 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in LTR state. this is a…
39200 …ataWidth:0x20 // Duration Counter: counts number of ticks main clock was in slow down state. thi…
39202 …aWidth:0x20 // Duration Counter: counts number of ticks storm clock was in slow down state. thi…
39204 …Width:0x20 // Duration Counter: counts number of ticks network clock was in slow down state. thi…
39206 …DataWidth:0x20 // Duration Counter: counts number of ticks pci clock was in slow down state. thi…
39208 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in LPI state. this is a…
39210 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in RX LPI state. this i…
39212 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in LPI state. this is a…
39214 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in Stall Memory state. …
39216 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in Stall Intterupt stat…
39218 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in L1 state. this is a …
39220 …ataWidth:0x20 // Duration Counter: Counts number of ticks the device was in LTR state. this is a…
39222 …ataWidth:0x20 // Duration Counter: Counts number of ticks main clock was in slow down state. thi…
39224 …taWidth:0x20 // Duration Counter: counts number of ticks storm clock was in slow down state. thi…
39226 …Width:0x20 // Duration Counter: counts number of ticks network clock was in slow down state. thi…
39228 …DataWidth:0x20 // Duration Counter: counts number of ticks pci clock was in slow down state. thi…
39259 … (0x1<<0) // Setting this bit to a '1' will result in all packets received…
39261 … (0x1<<1) // Setting this bit to a '1' will result in all packets received…
39263 … (0x1<<2) // 0 -> Send all broadcast packets to the appropriate networ…
39265 … (0x1<<3) // 0 -> Send all multicast packets to the appropriate networ…
39267 … (0x1<<4) // 0 -> only MAC address is used for comparison to detect Host2B…
39269 … (0x1<<5) // 0 -> Do not enable source MAC address learning for packets from…
39271 … (0x1<<6) // 0 -> Entries in SA Learning Cache are valid even after they are a…
39273 … (0x1<<7) // Setting this bit to a '1' will result in enabling flow contro…
39275 … (0x1<<8) // Setting this bit to a '1' will result in XOFF to be sent out …
39279 … (0x1<<10) // 0 -> Select NCSI RMII interface as the MII port …
39281 … (0x1<<11) // 0 -> Select NCSI RMII interface as the Management Po…
39283 … (0x1<<12) // 1 -> When BMB asserts any full condition, drop all the p…
39285 … (0x1<<13) // 1 -> When this bit is set, all pass through traffic will be directed to hos…
39287 …ccess:RW DataWidth:0x1 // When set, this bit indicates that the value in pkt_ethertype regist…
39288 …ackets as defined in the spec. This register allows SW to program one more ethertype other that 0x…
39289 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the BMC MAC address …
39290 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the BMC MAC address …
39291 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the BMC MAC address …
39292 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the BMC MAC address …
39293 …in the chip. Each channel represents the number of network ports in the chip. BMC will allocate on…
39294 …in the chip. Each channel represents the number of network ports in the chip. BMC will allocate on…
39295 …in the chip. Each channel represents the number of network ports in the chip. BMC will allocate on…
39296 …in the chip. Each channel represents the number of network ports in the chip. BMC will allocate on…
39297 …in the chip. Each channel represents the number of network ports in the chip. BMC will allocate on…
39298 …in the chip. Each channel represents the number of network ports in the chip. BMC will allocate on…
39299 …in the chip. Each channel represents the number of network ports in the chip. BMC will allocate on…
39300 …in the chip. Each channel represents the number of network ports in the chip. BMC will allocate on…
39305 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39306 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39307 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39308 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39309 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39310 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39311 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39312 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39313 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39314 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39315 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39316 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39317 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39318 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39319 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39320 …ss:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC addre…
39369 …4034cUL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid o…
39370 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39371 …40354UL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid o…
39372 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39373 …4035cUL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid o…
39374 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39375 …40364UL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid o…
39376 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39377 …4036cUL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid o…
39378 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39379 …40374UL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid o…
39380 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39381 …4037cUL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid o…
39382 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39383 …40384UL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid o…
39384 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39385 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39386 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39387 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39388 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39389 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39390 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39391 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39392 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39393 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39394 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39395 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39396 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39397 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39398 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39399 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39400 …m Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek a…
39401 … // This is a debug only register. it captures which of the four channels in the host, the MAC ad…
39402 … // This is a debug only register. it captures which of the four channels in the host, the MAC ad…
39403 … // This is a debug only register. it captures which of the four channels in the host, the MAC ad…
39404 … // This is a debug only register. it captures which of the four channels in the host, the MAC ad…
39405 … // This is a debug only register. it captures which of the four channels in the host, the MAC ad…
39406 … // This is a debug only register. it captures which of the four channels in the host, the MAC ad…
39407 … // This is a debug only register. it captures which of the four channels in the host, the MAC ad…
39408 … // This is a debug only register. it captures which of the four channels in the host, the MAC ad…
39417 …x20 // Provides Aging threshold of Source Address Learning cache entries in seconds. When an ent…
39418 …UL //Access:RW DataWidth:0x1 // When this bit is set, all the entries in the cache will be cl…
39420 … (0x1<<0) // Setting this bit to "1" will result in removing proprietary…
39422 …-to six TAGs present in a packet. This field sets which of the TAGs need to be removed. This field…
39424 …in a packet. 2'b00 -> Use the configuration bit associated with the Inner VLAN tag to decide wheth…
39426 …from the packet before sending it out to BMC. it is expected that once a non-zero value is set, al…
39427 …// The length of the info field for L2 tag 0. The length is between 2B and 14B; in 2B granularity.
39428 …// The length of the info field for L2 tag 1. The length is between 2B and 14B; in 2B granularity.
39429 …// The length of the info field for L2 tag 2. The length is between 2B and 14B; in 2B granularity.
39430 …// The length of the info field for L2 tag 3. The length is between 2B and 14B; in 2B granularity.
39431 …// The length of the info field for L2 tag 4. The length is between 2B and 14B; in 2B granularity.
39432 …// The length of the info field for L2 tag 5. The length is between 2B and 14B; in 2B granularity.
39434 … (0x1<<0) // Tells HW to set the INS_PROP_HEADER flag in the SOP descriptor f…
39436 … (0x1<<1) // Tells HW to set the INS_OUTER_TAG flag in the SOP descriptor f…
39438 …RRIDE_INNER_VLAN flag in the SOP descriptor for a BMC to Network packet if there is a VLAN header …
39440 …in the SOP descriptor for a BMC to Network packet if there is a VLAN header in the packet and VLAN…
39442 … HW to set the OVRRIDE_PRIORITY flag in the SOP descriptor for a BMC to Network packet if there is…
39451 …to '1' causes the hardware arbitration scheme to begin. Any NCSI port can re-start the arbitration.
39453 …(0x1<<6) // Setting this field to '1' the HW arbitration logic to function in bypass mode. This al…
39457 … (0x1f<<8) // This field is a programmable inter-packet gap for when t…
39465 … // This field indicates the value in number of Ingress clock cycles that the arbitration master w…
39484 …ansfer to NCSI has started. Setting a value of all 1s in this register will guarantee a store-and-…
39486 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
39510 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39511 …rted these registers will not latch new data in case the event happened again. Asserted by the har…
39513 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39514 …rted these registers will not latch new data in case the event happened again. Asserted by the har…
39516 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39517 …rted these registers will not latch new data in case the event happened again. Asserted by the har…
39519 …in the FIFO contains data regarding previous GRC rd/wr access. This FIFO conatins 32 rows. Before …
39525 …masked, access with the PF is not written to the trace FIFO. BB: only bits 0-7 are applicable. The…
39526 … 0x050084UL //Access:RW DataWidth:0x1 // If = 1, selects only the VF in GRC_REG_TRACE_FIFO_V…
39527 …L = 1. Value of all 1s is applicable and represents VF not valid. BB: only bits 0-6 are applicable.
39528 …sked, access with the port is not written to the trace FIFO. BB: only bits 0-1 are applicable. The…
39530 …_OV. Over-ride to VN PROTECTION. Bit [5]: PDA_OV. Over-ride to PDA PROTECTION. Bit [6]: HV_OV. Ove…
39531 …ess by enforcing the msbits. In order to select all the addresses of a specific block, need to enf…
39532 …lect or a specific address, or a range of address by enforcing the msbits. In order to select all …
39535 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
39544 …dth:0x4 // Debug only: If more than this Number of entries are occupied in the dbgsyn clock syn…
39595 …taWidth:0x20 // The count value for the timeout timer. The count is done in common main clock do…
39596 …50404UL //Access:RW DataWidth:0x1 // Setting this bit enables a timer in the GRC block to tim…
39598 … 0x05040cUL //Access:RW DataWidth:0x5 // Number of valid windows in the GRC_REG_PROTECTI…
39599 …in the GRC space (for a window of one address needs to write value of 0x1). Bit [47]: Rd access. …
39605 …nable 100Mbps Ethernet mode (SGMII) 010: Enable Gigabit Ethernet mode (SGMII) 101: Enable RMII mode
39611 … (0x1<<16) // Transmit packets to PHY while in MAC local loopback; …
39615 …Enable/Disable MAC transmit path for data packets & pause/pfc packets sent in the normal data path…
39627 …cation. If disabled (Set to reset value '0'); pause frames are terminated and discarded in the MAC.
39629 …alue '0') the transmit process is stopped for the amount of time specified in the pause quanta rec…
39631 … the MAC overwrites the source MAC address with the programmed MAC address in registers MAC_0 and …
39633 …en set to '1'; enables half duplex mode; when set to '0'; the MAC operates in full duplex mode. Ig…
39637 …low logic. In this case; the RXFIFO_STAT[1] register bit is not operational (always set to 0). If …
39639 …X are disabled. Config registers are not affected by sw reset. Write a 0 to de-assert the sw reset.
39645 … (0x1<<16) // Transmit packets to PHY while in MAC local loopback; …
39661 …ard Enable. When set to '1'; any frame received with an error is discarded in the Core and not for…
39667 …-of-band egress flow control is enabled. When this bit is set and input pin ext_tx_flow_control is…
39673 … 0x051014UL //Access:RW DataWidth:0x10 // Defines a 16-Bit maximum frame len…
39674 …/Access:RW DataWidth:0x10 // 16-Bit value; sets; in increment of 512 Ethernet bit times; the p…
39685 … (0x1<<3) // MAC Pause Enabled in Receive. 0: MAC Pause Disabled in Receive 1: MAC Paus…
39687 … (0x1<<4) // MAC Pause Enabled in Transmit. 0: MAC Pause Disabled in Transmit 1: MAC Pau…
39706 …; then receive pause quanta is ignored and a fixed quanta value programmed in SCALE_VALUE is loade…
39709 …G between Back-to-Back packets. This is the IPG parameter used exclusively in Full-Duplex mode whe…
39710 …ess:RW DataWidth:0x10 // Time value sent in the Timer Field for classes in XOFF state (Unit is…
39716 … (0x1<<5) // If enabled; UNIMAC will shut down TXCLK to PHY; when in LPI state.
39718 …by reduced PHY's output swing). UNIMAC ignores EEE feature on both Tx & Rx in 10Mbps. When cleared…
39722 …the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register…
39723 …the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register…
39724 …ined within 1us. We may consider having 0.5us reference; as timeout values in 802.3az/D1.3 are not…
39727 …tate when it receives packet for transmission. The decrement unit is 1 micro-second. This register…
39728 …tate when it receives packet for transmission. The decrement unit is 1 micro-second. This register…
39737 … (0x7f<<16) // Non Back-to-Back Transmit IPG pa…
39739 … (0x7f<<24) // Non Back-to-Back Transmit IPG pa…
39743 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
39774 …tination address of received packets. The remaining 16 bits are contained in the next register. …
39776 …tination address of received packets. The remaining 32 bits are contained in the previous registe…
39778 …tination address of received packets. The remaining 16 bits are contained in the next register. …
39779 …rupted by replacing the FCS of the transmitted frame by the FCS programmed in this register. This …
39780 …tination address of received packets. The remaining 32 bits are contained in the previous registe…
39786 … (0x1<<2) // If CRC corruption feature in enabled (TX_CRC_CORUPT_EN set); then in …
39790 …Access:RW DataWidth:0x20 // This register contains the bits [31:0] in the 48-bit MAC address. …
39792 …L_BB (0x1<<0) // Read-only field assertion …
39794 …TY_BB (0x1<<1) // Read-only field assertion …
39796 … (0x7<<2) // Indicates number of cells filled in the TX timestamp FIF…
39798 …ccess:RW DataWidth:0x10 // This register contains the bits [47:32] in the 48-bit MAC address. …
39799 …from the transmit FIFO. Every 49 bit; val_bit + seq_id + timestamp is read in two steps; i.e.; one…
39801 …me is being forced, send a Pause frame with the Pause Time Field specified in rf_omac_pause_time. …
39803 …me is being forced, send a Pause frame with the Pause Time Field specified in rf_omac_pause_time. …
39809 …sending a Per Priority Pause Frame. Each bit in this field corresponds to a priority that should …
39811 … (0x1ffff<<0) // Each bit in this register repres…
39815 …- skipped (unsupported) 1 - stackvlan (unsupported) 2 - carrerr (on by default) 3 - codeerr (on by…
39816 …//Access:RW DataWidth:0x1 // Flush enable bit to drop out all packets in Tx FIFO without egre…
39817 … 0x051338UL //Access:RW DataWidth:0x8 // probe address bit 7 - U/L bit 6 - GMII/XMGII CLK…
39830 … (0x1<<0) // Enables the PPP-Tx functionality.
39832 … (0x1<<1) // Enables the PPP-Rx functionality.
39838 … none of PFC related counters should increment. Otherwise; PFC counters is in full function. Note:…
39920 …(0x1<<0) // Enable ECC for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer
39922 …<1) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpa…
39924 …mory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpa…
39926 …mory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpa…
39928 …mory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpa…
39930 …mory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpa…
39932 …mory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpa…
39934 …mory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpa…
39936 …mory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpa…
39938 …mory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpa…
39940 …(0x1<<0) // Enable ECC for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer
39942 …) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpa…
39944 …) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpa…
39946 …) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpa…
39948 …) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpa…
39950 …<5) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpa…
39954 …<0) // Set parity only for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer
39956 …/ Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpa…
39958 …mory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpa…
39960 …mory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpa…
39962 …mory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpa…
39964 …mory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpa…
39966 …mory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpa…
39968 …mory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpa…
39970 …mory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpa…
39972 …mory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpa…
39974 …<0) // Set parity only for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer
39976 …Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpa…
39978 …Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpa…
39980 …Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpa…
39982 …Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpa…
39984 …/ Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpa…
39988 …rectable error occurred on memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer
39990 …ble error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpa…
39992 …mory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpa…
39994 …mory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpa…
39996 …mory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpa…
39998 …mory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpa…
40000 …mory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpa…
40002 …mory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpa…
40004 …mory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpa…
40006 …mory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpa…
40008 …rectable error occurred on memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer
40010 …e error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpa…
40012 …e error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpa…
40014 …e error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpa…
40016 …e error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpa…
40018 …ble error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpa…
40023 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
40056 …es number of 256 bits data entries in the DORQ FIFO. When the occupancy is more than that number, …
40112 …) // Enable ECC for memory ecc instance pcie_top_wrapper.u_debug_mem.i_ecc in module pcie_debug_me…
40114 …0) // Enable ECC for memory ecc instance pcie_top_wrapper.i_ram_1p_rbuf.i_ecc in module ram_1p_rbuf
40116 …/ Enable ECC for memory ecc instance pcie_top_wrapper.i_ram_2p_sotbuf.i_ecc in module ram_2p_sotbuf
40118 …1<<0) // Enable ECC for memory ecc instance pcie_top_wrapper.u_d2t_fifo.i_ecc in module d2t_fifo_e4
40120 … // Enable ECC for memory ecc instance pcie_top_wrapper.u_header_mem.i_ecc in module header_log_me…
40122 …2) // Enable ECC for memory ecc instance pcie_top_wrapper.u_tlda_mem.i_ecc in module pcie_tlda_mem…
40124 …) // Enable ECC for memory ecc instance pcie_top_wrapper.u_tlda2_mem.i_ecc in module pcie_tlda_mem…
40126 …nable ECC for memory ecc instance pcie_top_wrapper.u_replay_data_mem.i_ecc in module pcie_replay_e4
40129 …Set parity only for memory ecc instance pcie_top_wrapper.u_debug_mem.i_ecc in module pcie_debug_me…
40131 … Set parity only for memory ecc instance pcie_top_wrapper.i_ram_1p_rbuf.i_ecc in module ram_1p_rbuf
40133 … parity only for memory ecc instance pcie_top_wrapper.i_ram_2p_sotbuf.i_ecc in module ram_2p_sotbuf
40135 … // Set parity only for memory ecc instance pcie_top_wrapper.u_d2t_fifo.i_ecc in module d2t_fifo_e4
40137 …et parity only for memory ecc instance pcie_top_wrapper.u_header_mem.i_ecc in module header_log_me…
40139 … Set parity only for memory ecc instance pcie_top_wrapper.u_tlda_mem.i_ecc in module pcie_tlda_mem…
40141 …Set parity only for memory ecc instance pcie_top_wrapper.u_tlda2_mem.i_ecc in module pcie_tlda_mem…
40143 …rity only for memory ecc instance pcie_top_wrapper.u_replay_data_mem.i_ecc in module pcie_replay_e4
40146 …e error occurred on memory ecc instance pcie_top_wrapper.u_debug_mem.i_ecc in module pcie_debug_me…
40148 …le error occurred on memory ecc instance pcie_top_wrapper.i_ram_1p_rbuf.i_ecc in module ram_1p_rbuf
40150 …rror occurred on memory ecc instance pcie_top_wrapper.i_ram_2p_sotbuf.i_ecc in module ram_2p_sotbuf
40152 …table error occurred on memory ecc instance pcie_top_wrapper.u_d2t_fifo.i_ecc in module d2t_fifo_e4
40154 … error occurred on memory ecc instance pcie_top_wrapper.u_header_mem.i_ecc in module header_log_me…
40156 …le error occurred on memory ecc instance pcie_top_wrapper.u_tlda_mem.i_ecc in module pcie_tlda_mem…
40158 …e error occurred on memory ecc instance pcie_top_wrapper.u_tlda2_mem.i_ecc in module pcie_tlda_mem…
40160 …r occurred on memory ecc instance pcie_top_wrapper.u_replay_data_mem.i_ecc in module pcie_replay_e4
40178 …L0 (0x1<<1) // Link in L0 Status bit.
40180 …23 (0x1<<4) // Link in L23 Status bit.
40182 … (0x1<<0) // Timesynch Data is ready in PCIE FIFO.
40184 …11_BB (0x1<<2) // Link in L11 Status bit.
40186 …12_BB (0x1<<3) // Link in L12 Status bit.
40217 …te that the pcore WakeIn input is active high. This bit should only be set in the event a workarou…
40258 … 0x054224UL //Access:RW DataWidth:0x20 // 32 bit value to be sent in LTR message
40259 … 0x054228UL //Access:RW DataWidth:0x20 // 32 bit value to be sent in LTR message
40260 … 0x05422cUL //Access:R DataWidth:0x20 // LTR latency value being sent in LTR messages
40268 …en low by your application after cold, warm or hot reset to hold the LTSSM in the Detect state unt…
40280 …K_SWITCH_CORE_CLK_GATE_EN_K2_E5 (0x1<<2) // While in L1 enable AUX clock …
40289 … (0xff<<3) // Indicates whether the PHY RX is active when the PHY is in P0 or P0s.
40318 …eq_rst_not signal. For more details, see the 'Warm and Hot Resets' section in the Architecture cha…
40333 … (0x7f<<9) // Common event signal status bus used in RAS D.E.S. time base…
40337 … (0x1<<17) // Autonomous speed disable. Used in downstream ports onl…
40340 … (0xffff<<0) // State of selected internal signals in relation to electric…
40342 …MSG_UNLOCK_K2_E5 (0x1<<16) // One-cycle pulse that indi…
40344 …TURNOFF_K2_E5 (0x1<<17) // One-clock-cycle pulse that i…
40349 … to wake up the PMC state machine from a D1, D2 or D3 power state. Upon wake-up, the core sends a …
40357 …<0) // WARNING: this bit should not be used by firmware due to a bug filed in CQ85027. Indicates t…
40359 … (0xffff<<1) // PME Enable bit in the PMCSR. There is …
40361 …S_K2_E5 (0x1<<17) // Power management is in L0s state
40363 …_K2_E5 (0x1<<18) // Power management is in L2 state.
40368 … (0xffff<<0) // This is the value of the No Soft Reset bit in the Power Management…
40373 … (0xffff<<0) // Auxiliary Power Enable bit in the Device Control r…
40380 …cUL //Access:R DataWidth:0x20 // Common debug signal bus that is used in RAS D.E.S. silicon d…
40381 …0UL //Access:R DataWidth:0x20 // Common debug signal bus that is used in RAS D.E.S. silicon d…
40382 …4UL //Access:R DataWidth:0xb // Common debug signal bus that is used in RAS D.E.S. silicon d…
40383 …a8UL //Access:R DataWidth:0x20 // Lane0 debug signal bus that is used in RAS D.E.S. silicon d…
40384 …acUL //Access:R DataWidth:0x20 // Lane0 debug signal bus that is used in RAS D.E.S. silicon d…
40385 …b0UL //Access:R DataWidth:0xe // Lane0 debug signal bus that is used in RAS D.E.S. silicon d…
40386 …b4UL //Access:R DataWidth:0x20 // Lane1 debug signal bus that is used in RAS D.E.S. silicon d…
40387 …b8UL //Access:R DataWidth:0x20 // Lane1 debug signal bus that is used in RAS D.E.S. silicon d…
40388 …bcUL //Access:R DataWidth:0xe // Lane1 debug signal bus that is used in RAS D.E.S. silicon d…
40389 …c0UL //Access:R DataWidth:0x20 // Lane2 debug signal bus that is used in RAS D.E.S. silicon d…
40390 …c4UL //Access:R DataWidth:0x20 // Lane2 debug signal bus that is used in RAS D.E.S. silicon d…
40391 …c8UL //Access:R DataWidth:0xe // Lane2 debug signal bus that is used in RAS D.E.S. silicon d…
40392 …ccUL //Access:R DataWidth:0x20 // Lane3 debug signal bus that is used in RAS D.E.S. silicon d…
40393 …d0UL //Access:R DataWidth:0x20 // Lane3 debug signal bus that is used in RAS D.E.S. silicon d…
40394 …d4UL //Access:R DataWidth:0xe // Lane3 debug signal bus that is used in RAS D.E.S. silicon d…
40395 …d8UL //Access:R DataWidth:0x20 // Lane4 debug signal bus that is used in RAS D.E.S. silicon d…
40396 …dcUL //Access:R DataWidth:0x20 // Lane4 debug signal bus that is used in RAS D.E.S. silicon d…
40397 …e0UL //Access:R DataWidth:0xe // Lane4 debug signal bus that is used in RAS D.E.S. silicon d…
40398 …e4UL //Access:R DataWidth:0x20 // Lane5 debug signal bus that is used in RAS D.E.S. silicon d…
40399 …e8UL //Access:R DataWidth:0x20 // Lane5 debug signal bus that is used in RAS D.E.S. silicon d…
40400 …ecUL //Access:R DataWidth:0xe // Lane5 debug signal bus that is used in RAS D.E.S. silicon d…
40401 …f0UL //Access:R DataWidth:0x20 // Lane6 debug signal bus that is used in RAS D.E.S. silicon d…
40402 …f4UL //Access:R DataWidth:0x20 // Lane6 debug signal bus that is used in RAS D.E.S. silicon d…
40403 …f8UL //Access:R DataWidth:0xe // Lane6 debug signal bus that is used in RAS D.E.S. silicon d…
40404 …fcUL //Access:R DataWidth:0x20 // Lane7 debug signal bus that is used in RAS D.E.S. silicon d…
40405 …00UL //Access:R DataWidth:0x20 // Lane7 debug signal bus that is used in RAS D.E.S. silicon d…
40406 …04UL //Access:R DataWidth:0xe // Lane7 debug signal bus that is used in RAS D.E.S. silicon d…
40407 …4308UL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon d…
40408 …430cUL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon d…
40409 …4310UL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon d…
40410 …4314UL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon d…
40411 …4318UL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon d…
40412 …431cUL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon d…
40413 …4320UL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon d…
40414 …4324UL //Access:R DataWidth:0x10 // VC0 debug signal bus that is used in RAS D.E.S. silicon d…
40415 … 0x054328UL //Access:R DataWidth:0x5 // pm_dev_num[4:0]- Device number
40416 … 0x05432cUL //Access:R DataWidth:0x8 // pm_bus_num[7:0]- Bus Number
40472 … (0x1<<10) // Do not use -- keep mask bit set to…
40478 … (0x1<<13) // Non-Fatal Error Message s…
40484 … (0x1<<16) // Vendor-Defined Message recei…
40542 … (0x1<<10) // Do not use -- keep mask bit set to…
40548 …E5 (0x1<<13) // Non-Fatal Error Message s…
40554 … (0x1<<16) // Vendor-Defined Message recei…
40577 … (0x1<<10) // Do not use -- keep mask bit set to…
40583 …_E5 (0x1<<13) // Non-Fatal Error Message s…
40589 … (0x1<<16) // Vendor-Defined Message recei…
40603 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
40608 …_E5 (0x1<<0) // Power-on reset occurred.
40618 …_2_K2_E5 (0x1<<5) // Non-sticky register reset…
40640 …(0x1<<16) // Soft power-on reset occurred. NOTE: This bit is unreliable for indication of a soft p…
40650 …2_K2_E5 (0x1<<21) // Soft non-sticky register reset…
40718 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
40719 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
40737 … (0x1<<8) // CFC load request FIFO under-run
40741 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40787 …RR (0x1<<8) // CFC load request FIFO under-run
40791 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40812 …ERR (0x1<<8) // CFC load request FIFO under-run
40816 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40858 …dth:0x1 // Enable ECC for memory ecc instance dorq.i_dorq_fifo_mem.i_ecc in module dorq_fifo_mem
40859 …x1 // Set parity only for memory ecc instance dorq.i_dorq_fifo_mem.i_ecc in module dorq_fifo_mem
40860 …orrectable error occurred on memory ecc instance dorq.i_dorq_fifo_mem.i_ecc in module dorq_fifo_mem
40862 … 0x100400UL //Access:RW DataWidth:0x14 // The offset in units of 4KB from th…
40863 … 0x100404UL //Access:RW DataWidth:0x14 // The offset in units of 4KB from th…
40864 … 0x100408UL //Access:RW DataWidth:0xc // The value in the register, when m…
40865 … 0x10040cUL //Access:RW DataWidth:0xc // The value in the register, when m…
40866 … 0x100410UL //Access:RW DataWidth:0xc // The value in the register, when m…
40867 … 0x100414UL //Access:RW DataWidth:0xc // The value in the register, when m…
40868 … 0x100418UL //Access:RW DataWidth:0xc // The value in the register, when m…
40869 … 0x10041cUL //Access:RW DataWidth:0xc // The value in the register, when m…
40870 … 0x100420UL //Access:RW DataWidth:0xc // The value in the register, when m…
40871 … 0x100424UL //Access:RW DataWidth:0xc // The value in the register, when m…
40872 … 0x100428UL //Access:RW DataWidth:0xc // The value in the register, when m…
40873 … 0x10042cUL //Access:RW DataWidth:0xc // The value in the register, when m…
40874 … 0x100430UL //Access:RW DataWidth:0xc // The value in the register, when m…
40875 … 0x100434UL //Access:RW DataWidth:0xc // The value in the register, when m…
40876 … 0x100438UL //Access:RW DataWidth:0xc // The value in the register, when m…
40877 … 0x10043cUL //Access:RW DataWidth:0xc // The value in the register, when m…
40878 … 0x100440UL //Access:RW DataWidth:0xc // The value in the register, when m…
40879 … 0x100444UL //Access:RW DataWidth:0xc // The value in the register, when m…
40880 …h:0x2 // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of …
40881 …h:0x2 // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of …
40882 …RW DataWidth:0x5 // Indicates the size of a page in PWM. This is the LOG2 of PWM page size in…
40883 …RW DataWidth:0x5 // Indicates the size of a page in PWM. This is the LOG2 of PWM page size in…
40886 … 0x100460UL //Access:RW DataWidth:0x2 // Target value used in DEMS mode for DEMS =…
40887 …ccess:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 1. Bit 2 of AggValSel is alw…
40888 … 0x100468UL //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS =…
40889 … 0x10046cUL //Access:RW DataWidth:0x2 // Target value used in DEMS mode for DEMS =…
40890 …ccess:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 2. Bit 2 of AggValSel is alw…
40891 … 0x100474UL //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS =…
40892 … 0x100478UL //Access:RW DataWidth:0x2 // Target value used in DEMS mode for DEMS =…
40893 …ccess:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 3. Bit 2 of AggValSel is alw…
40894 … 0x100480UL //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS =…
40895 … 0x100484UL //Access:RW DataWidth:0x2 // Target value used in DEMS mode for DEMS =…
40896 …ccess:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 4. Bit 2 of AggValSel is alw…
40897 … 0x10048cUL //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS =…
40898 … 0x100490UL //Access:RW DataWidth:0x2 // Target value used in DEMS mode for DEMS =…
40899 …ccess:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 5. Bit 2 of AggValSel is alw…
40900 … 0x100498UL //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS =…
40901 … 0x10049cUL //Access:RW DataWidth:0x2 // Target value used in DEMS mode for DEMS =…
40902 …ccess:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 6. Bit 2 of AggValSel is alw…
40903 … 0x1004a4UL //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS =…
40904 … 0x1004a8UL //Access:RW DataWidth:0x2 // Target value used in DEMS mode for DEMS =…
40905 …ccess:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 7. Bit 2 of AggValSel is alw…
40906 … 0x1004b0UL //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS =…
40907 … 0x1004f4UL //Access:RW DataWidth:0x2 // AGG command value in PWM non-DPM mode.
40908 …UL //Access:RW DataWidth:0x8 // The initial value for Agg CM messages in case of DPM L2 or DP…
40910 …this PF belongs to. In 2 port mode it is equal to 0 for all PF-s. In 4 port mode, it is equal to 0…
40911 …indication on all ports. This is a per PF per configuration. Should be set in case of coupled mode…
40912 …0x100508UL //Access:RW DataWidth:0x1 // Enable doorbells for this PF. In case not set the doo…
40913 …0x10050cUL //Access:RW DataWidth:0x1 // Enable doorbells for this VF. In case not set the doo…
40914 …0510UL //Access:RW DataWidth:0x1 // Enable DPM doorbells for this PF. In case not set the DPM…
40915 …ss:RW DataWidth:0x1 // Enable DPM doorbells for all this PF child VF-s. In case not set the D…
40918 … 0x100608UL //Access:RW DataWidth:0x10 // Aggregation value command in case of successful L…
40919 … 0x10060cUL //Access:RW DataWidth:0x10 // Aggregation value command in case of legacy and R…
40920 … 0x100610UL //Access:RW DataWidth:0x10 // Aggregation value command in case of aborted L2 E…
40921 …UL //Access:RW DataWidth:0x5 // The value of AggDecType in CM header in XCM message in case o…
40922 … 0x1006fcUL //Access:RW DataWidth:0x5 // The value of AggDecType in CM header in UCM message.
40923 … 0x100700UL //Access:RW DataWidth:0x5 // The value of AggDecType in CM header in TCM message.
40924 …8UL //Access:RW DataWidth:0x1 // The value of the SmCtxLdStFlg in XCM header in case of EDPM …
40929 … 0x100810UL //Access:RW DataWidth:0x1 // If set then CCFC mini-cache is enabled.
40930 … 0x100814UL //Access:RW DataWidth:0xa // DORQ FIFO almost full threshold (in FIFO entries).
40931 …ll appears it is truncated to one entry and aborted; non-first doorbell is dropped. (Measured in F…
40932 …uncated to one entry and DpmAbort flag is set; non-first doorbell is silently dropped. Is calculat…
40937 … 0x100834UL //Access:RW DataWidth:0xc // Timeout (measured in main clock cycles) f…
40938 … DataWidth:0x4 // Indicates which ExistInQm bits are taken into account in the EDPM check. If a…
40940 … 0x100840UL //Access:RW DataWidth:0xa // DORQ FIFO full threshold (in FIFO entries). If DO…
40941 …//Access:RW DataWidth:0xe // Number of cycles in which full towards PXP is asserted if DORQ i…
40942 …Access:RW DataWidth:0x10 // Tag 1 Ethertype used for packet generation in RoCE EDPM mode. Defa…
40943 …Access:RW DataWidth:0x10 // Tag 2 Ethertype used for packet generation in RoCE EDPM mode. Defa…
40944 …Access:RW DataWidth:0x10 // Tag 3 Ethertype used for packet generation in RoCE EDPM mode. Defa…
40945 …Access:RW DataWidth:0x10 // Tag 4 Ethertype used for packet generation in RoCE EDPM mode. Defa…
40946 … 1 used for packet generation in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - …
40947 … 2 used for packet generation in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - …
40948 … 3 used for packet generation in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - …
40949 … 4 used for packet generation in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - …
40950 …1008a4UL //Access:RW DataWidth:0x8 // GRH Next Header used for packet generation in RoCE EDPM.
40951 … 0x1008a8UL //Access:RW DataWidth:0x4 // TVER value in RoCE BTH header.
40952 …L //Access:RW DataWidth:0x20 // Enable bit per each RoCE Opcode 5 LSB-s. N-th bit set means co…
40953 …Access:RW DataWidth:0x1 // If 0 - the RoCE CRC-32 final calculation result isn't byte swapped…
40961 …ss:RW DataWidth:0x10 // RoCE Ethertype used for RoCE packet generation in EDPM mode. addr=0 � …
40964 …100904UL //Access:RW DataWidth:0x8 // Size in Words of header extracted by PBF and sent to PS…
40965 …0908UL //Access:RW DataWidth:0x8 // Offset in Words of header extracted by PBF and sent to PS…
40966 …:RW DataWidth:0x1 // Indicates whether Ethernet over GRE header is expected in packet payload.
40967 …Access:RW DataWidth:0x1 // Indicates whether IP over GRE header is expected in packet payload.
40968 …4UL //Access:RW DataWidth:0x1 // Indicates whether VXLAN header is expected in packet payload.
40969 … 0x100918UL //Access:RW DataWidth:0x2 // TPH Hint value in case of non-inline L2 EDPM.
40970 … 0x10091cUL //Access:RW DataWidth:0x3 // ATC attribute value of non-inline L2 EDPM.
40971 …00920UL //Access:RW DataWidth:0x5 // Start offset to read PCM STORM context. Measured in REGQ.
40972 … 0x100924UL //Access:RW DataWidth:0xe // Maximum non-inline L2 EDPM PktSiz…
40973 … 0x100928UL //Access:RW DataWidth:0x8 // The maximum number of WORD-s which the PBF may a…
40974 …//Access:RW DataWidth:0x1 // Set to 1 if IP over NGE header is expected in the packet payload.
40975 …ss:RW DataWidth:0x1 // Set to 1 if Ethernet over NGE header is expected in the packet payload.
40980 …DataWidth:0xb // Counter of DORQ FIFO entries used by corresponding PF or any of its child VF-s.
40982 … number of DORQ FIFO entries used by corresponding PF or any of its child VF-s. This is a per PF c…
40991 …nters auto drop mode on the first doorbell drop due to DORQ FIFO overflow. In this mode all incomi…
40992 …de is active and all doorbells are dropped at the entrance to DORQ FIFO. De-asserted when auto_di…
40994 … 0x1009f8UL //Access:RW DataWidth:0x8 // Size in bytes of the PXP transactions to be counted…
40995 … 0x1009fcUL //Access:R DataWidth:0x20 // Accounts for any non-DPM doorbell or first…
40998 …0x100a08UL //Access:R DataWidth:0x6 // CFC load request FIFO current fill level (in entries).
40999 … 0x100a0cUL //Access:R DataWidth:0xb // DORQ FIFO current fill level (in entries REGQ each).
41000 … 0x100a10UL //Access:RC DataWidth:0xb // DORQ FIFO sticky fill level (in entries REGQ each). …
41003 … after logging was re-armed by db_drop_details_rel. The following details of the transaction will …
41004 …-armed by db_drop_details_rel. The following details of the transaction will be recorded: Doorbell…
41005 …-armed by db_drop_details_rel. The following details of the transaction will be recorded: bits[15:…
41007 …- Size of the data is not equal to 4 or to a multiple of 8 bytes; 1 - 2 LSB-s of the address are n…
41013 …- DPM doorbell and rewind configuration of DPM timer (dpm_timeout) is 0; 1 - PF DPM doorbell and i…
41015 …- DPM doorbell and rewind configuration of DPM timer (dpm_timeout) is 0; 1 - First DPM doorbell an…
41027 … be done at first cycle of first DPM doorbell by the size of DpmSize. No non-first DPM doorbells s…
41032 …In case of LCID validation error or load error, the current value of the single entry in the CID l…
41034 …in case mini-cache was used. 36 - CDU Validation Error; 35 - CFC Load Cancel; 34 - CFC Load Error;…
41039 …Width:0x1 // comment="Selects IEDPM payload endianity. 0 - little endian (lsB first); 1 - big e…
41045 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
41053 …- DPM FSM state [194:192] - DbAggValSel [191:190] - DbAggCmd [189:182] - DbAggFlgCmd [181] - IEDPM…
41060 … 0x102800UL //Access:RW DataWidth:0xc // The value in the register, when m…
41061 … 0x102804UL //Access:RW DataWidth:0xc // The value in the register, when m…
41064 … 0x102810UL //Access:RW DataWidth:0xc // The value in the register, when m…
41065 … 0x102814UL //Access:RW DataWidth:0xc // The value in the register, when m…
41066 … 0x102818UL //Access:RW DataWidth:0xc // The value in the register, when m…
41067 … 0x10281cUL //Access:RW DataWidth:0xc // The value in the register, when m…
41068 … 0x102820UL //Access:RW DataWidth:0xc // The value in the register, when m…
41069 … 0x102824UL //Access:RW DataWidth:0xc // The value in the register, when m…
41070 … 0x102828UL //Access:RW DataWidth:0xc // The value in the register, when m…
41071 … 0x10282cUL //Access:RW DataWidth:0xc // The value in the register, when m…
41080 … DataWidth:0x4 // Indicates which ExistInQm bits are taken into account in the IEDPM check. If …
41081 …4UL //Access:RW DataWidth:0x5 // The value of the AggDecType in the XCM message in IEDPM inpu…
41082 …4UL //Access:RW DataWidth:0x5 // The value of the AggDecType in the XCM message in case of le…
41083 …8UL //Access:RW DataWidth:0x5 // The value of the AggDecType in the XCM message in case of le…
41085 …0UL //Access:RW DataWidth:0x5 // The value of the AggDecType in the XCM message in case QM by…
41087 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41088 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41089 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41090 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41091 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41092 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41093 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41094 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41095 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41096 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41097 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41098 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41099 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41100 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41101 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41102 …f two EDPM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, b…
41103 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41104 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41105 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41106 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41107 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41108 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41109 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41110 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41111 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41112 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41113 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41114 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41115 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41116 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41117 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41118 … which will select which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per con…
41167 … 0x1006d4UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41168 … 0x102968UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41169 … 0x1006d8UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41170 … 0x10296cUL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41171 … 0x1006dcUL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41172 … 0x102970UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41173 … 0x1006e0UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41174 … 0x102974UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41175 … 0x1006e4UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41176 … 0x102978UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41177 … 0x1006e8UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41178 … 0x10297cUL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41179 … 0x1006ecUL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41180 … 0x102980UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41181 … 0x1006f0UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41182 … 0x102984UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41183 … 0x102988UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41184 … 0x10298cUL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41185 … 0x102990UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41186 … 0x102994UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41187 … 0x102998UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41188 … 0x10299cUL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41189 … 0x1029a0UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41190 … 0x1029a4UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell…
41191 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41192 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41193 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41194 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41195 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41196 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41197 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41198 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41199 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41200 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41201 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41202 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41203 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41204 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41205 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41206 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41207 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41208 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41209 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41210 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41211 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41212 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41213 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41214 …DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in case of RoCE or lega…
41362 … 0x102b74UL //Access:RW DataWidth:0x2 // DDP version in iWARP.
41363 … 0x102b78UL //Access:RW DataWidth:0x2 // RDMAP version in iWARP.
41364 …Access:RW DataWidth:0x1 // If 0 - the iWARP CRC-32 final calculation result isn't byte swappe…
41365 … //Access:RW DataWidth:0x20 // Enable bit per each iWARP Opcode 5 LSB-s. N-th bit set means co…
41366 …x102b84UL //Access:RW DataWidth:0x4 // The priority value and DEI bit in external VLAN TAG of…
41367 …x102b88UL //Access:RW DataWidth:0x4 // The priority value and DEI bit in external VLAN TAG of…
41368 …x102b8cUL //Access:RW DataWidth:0x4 // The priority value and DEI bit in internal VLAN TAG of…
41377 … DataWidth:0x4 // Indicates which ExistInQm bits are taken into account in RoCE EDPM check. If …
41378 … DataWidth:0x4 // Indicates which ExistInQm bits are taken into account in iWARP EDPM check. If…
41379 … DataWidth:0x4 // Indicates which ExistInQm bits are taken into account in L2 EDPM check. If a …
41380 …the transaction will be recorded: Doorbell DPM type. 0 - Legacy 1 - RDMA 2 - L2 Inline 3 - L2 Non-…
41385 …- First DPM doorbell does not match DPM global start conditions at CFC load response for Internal …
41387 …- First DPM doorbell does not match DPM global start conditions at CFC load response for Internal …
41388 …-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: IEDPM…
41389 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41390 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41391 … after logging was re-armed by iedpm_drop_details_rel. The following details of the transaction wi…
41392 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41394 …- First QWord (offset 0) arives on IEDPM buffer which is not free; 3 - Non-first QWord (offset oth…
41400 …c0cUL //Access:RW DataWidth:0x1 // The value of UpdPstormEventId flag in PBF command should b…
41401 … 0x102c10UL //Access:RW DataWidth:0x1 // Same as last enable flag sent in PBF command.
41402 … 0x102c14UL //Access:RW DataWidth:0x1 // GFS command exist flag sent in PBF command.
41405 …ccess:RW DataWidth:0x8 // Event ID, which is sent in the PCM message (part of PBF command) in…
41406 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in case of…
41407 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in case of…
41408 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in case of…
41409 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41410 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41411 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41412 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41413 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41414 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41415 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41416 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41417 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41418 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41419 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41420 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41421 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41422 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41423 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41424 …L //Access:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (R…
41425 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41426 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41427 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41428 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41429 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41430 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41431 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41432 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41433 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41434 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41435 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41436 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41437 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41438 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41439 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41440 … //Access:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (R…
41441 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41442 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41443 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41444 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41445 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41446 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41447 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41448 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41449 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41450 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41451 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41452 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41453 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41454 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41455 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41456 …//Access:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (R…
41461 …- mapping memory; Bit 1 - SB memory (producer and consumer); Bit 2 - SB interrupt before mask and …
41463 …// If enabled the IGU forwards write/read requests to the TPH interface. 1 - enabled; 0 - disabled.
41465 …ed the IGU allows to VF to send cleanup commands on the int ack address. 1 - enabled; 0 - disabled.
41467 …the IGU allows bypass mode of the rate limiter when the system is empty. 1 - enabled; 0 - disabled.
41473 … 0x18006cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
41488 … (0x1<<5) // MME value in MSI control is bigge…
41492 … (0x1<<7) // During interrupt read from function that is not in SIMD mode.
41534 … (0x1<<5) // MME value in MSI control is bigge…
41538 … (0x1<<7) // During interrupt read from function that is not in SIMD mode.
41557 … (0x1<<5) // MME value in MSI control is bigge…
41561 … (0x1<<7) // During interrupt read from function that is not in SIMD mode.
41749 …le ECC for memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_…
41750 …le ECC for memory ecc instance igu.IGU_MSIX_368_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_368_…
41751 …idth:0x1 // Enable ECC for memory ecc instance igu.i_igu_msix_mem.i_ecc in module igu_msix_512_…
41752 …y only for memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_…
41753 …y only for memory ecc instance igu.IGU_MSIX_368_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_368_…
41754 …0x1 // Set parity only for memory ecc instance igu.i_igu_msix_mem.i_ecc in module igu_msix_512_…
41755 …ccurred on memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_…
41756 …ccurred on memory ecc instance igu.IGU_MSIX_368_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_368_…
41757 …correctable error occurred on memory ecc instance igu.i_igu_msix_mem.i_ecc in module igu_msix_512_…
41761 …r of MSI/MSIX/ATTN messages sent for the PF: address 0 - number of MSI/MSIX messages; address 1 - …
41771 …he number of PXP requests sent on behalf of a specific MSI/MSI-X vector on the SB index in pxp_req…
41777 …h arrived on a specific SB, on the SB index in prod_upd_counter_sb_num. If the S…
41783 …ests which arrived on a specific SB, on the SB index in cons_upd_counter_sb_num. If the SB number …
41785 … 0x180600UL //Access:RW DataWidth:0x14 // IPS statistics - number of messages s…
41787 …- function enable; b1 - MSI/MSIX enable; b2 - INT enable; b3 - attention enable; b4 - single ISR m…
41788 …h:0x9 // d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enabl…
41812 … (0x3<<26) // Endianity mode in MSI/MSIX and attenti…
41816 …th:0x1 // PF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41818 …th:0x1 // VF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41821 …oward the driver as attention bit status index). This is the same value as in the attention messag…
41822 … condition monitoring; each bit that is set will lock a change from 0 to 1 in the corresponding at…
41823 … condition monitoring; each bit that is set will lock a change from 1 to 0 in the corresponding at…
41824 …bit register with the latched attention values. These are the same bits as in the attention messag…
41825 …/ 32 bit register with the attention ACK values.These are the same bits as in the attention messag…
41826 …s set to 1, the corresponding bit in the attention vector is enabled. If the bit is set to 0, the …
41827 …in each bit means PBA message wasnt sent due to mask). If address = SIMD with mask 64b/32LSB: 32 L…
41828 …in each bit means PBA message wasnt sent due to mask). If address = SIMD with mask 64b/32MSB: 32 …
41829 …idth:0x20 // [15:0] - function number: opaque fid. [28:16] - PXP BAR address; [30:29] - Reserved…
41830 … 0x18084cUL //Access:RW DataWidth:0x1 // Enable to collect data in the statistic_num_vf…
41831 … DataWidth:0x20 // Address 0 - MSI address low (two Lsbit are zero). Address 1 - MSI address hig…
41834 …g is enabled, the match address of the hit response is used to perform a two-cycle …
41836 … there is a search that results in a miss, a read of the entire CAM …
41838 … 0x180864UL //Access:RW DataWidth:0x1 // Enable the RL statistic. 0 - disabled; 1 - enabled.
41848 … bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in these registers are …
41852 … bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are s…
41856 … bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are s…
41860 … bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are s…
41864 … bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are s…
41868 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41869 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41870 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41871 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41872 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41873 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41874 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41875 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41876 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41877 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41878 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41879 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41880 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41881 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41882 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41883 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41884 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41885 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41886 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41887 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41888 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41889 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41890 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41891 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41892 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41893 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41894 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41895 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41896 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41897 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41898 …ng the absolute SB index to the register will clear the appropriate vector in the MSIX table (writ…
41899 … - prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits …
41901 …- prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits o…
41902 …- prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits o…
41903 …h:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The bits order is according to the vector…
41905 …- unmasked. 1 - masked. The bits order is according to the vector number of each SB in that functi…
41906 … 0 - unmasked. 1 - masked. The bits order is according to the vector number of each SB in that fun…
41907 …- PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or v…
41909 …- PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or v…
41910 …- PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or v…
41911 …d - sets the max value that the rate_counter can reach; [19:10] tick_interval - define the max int…
41913 …- receives the tick_interval value when reaching zero; or when writing to the tick_interval. The t…
41923 …er - incremented by one when Tick_value reaches zero and decremented whenever a message from that …
41926 …in the IPS mechanism. The number of cycles multiply by clock 25 cycle time should give 1 usec. In …
41927 …Tph field for attention message. Bits 8:0 - steering tag; bits 12:9 - reserved; bits 14:13 - st hi…
41928 …miter group enable status bit for groups 0-31. For each bit: 0 - the rate limiter of the group is …
41929 …iter group enable status bit for groups 32-63. For each bit: 0 - the rate limiter of the group is …
41930 …/ Rate Limiter group credit status bit for groups 0-31. For each bit: 0 - the group has no credit.…
41931 … Rate Limiter group credit status bit for groups 32-63. For each bit: 0 - the group has no credit.…
41932 … pending status bit for groups 0-31. For each bit: 0 - there are no pending SB in that group. 1 - …
41933 …pending status bit for groups 32-63. For each bit: 0 - there are no pending SB in that group. 1 - …
41934 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port0.
41935 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port1.
41936 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port2.
41937 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port3.
41939 …L //Access:R DataWidth:0x5 // Debug: [4] - attention write done message is pending (0-no pen…
41940 …518UL //Access:RW DataWidth:0x1 // Debug only: 0 - FIFO collects 64 first error messages; 1 -…
41942 …in according to the command_debug value. If command_debug is clear it holds the first 64 error com…
41966 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 0; [7:0] = VF number; if PF - [8…
41968 …<<9) // Debug: if set the debug information is collected for FID specified in debug_record_mask_fi…
41978 …- MSIX read/write; Bit [1] - PBA read/write; Bit [2] - Producer update (or cleanup command through…
41985 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
41993 … DataWidth:0x18 // Producers only. Address 0-511 match to the mapping memory. Address 512-227:…
41997 …W DataWidth:0x18 // Consumers only. Address 0-511 match to the mapping memory. Address 512-227…
42001 …- valid. [8:1] - vector number (0-128 for PF; 0-63 for VF). [17:9] - FID (if VF: [17] = 0; [16:9] …
42005 …x61 // [63:0] - MSIX message address (bit [1:0] are always zero); [95:64] - MSIX message data; […
42016 …x > CAU_NUM_PI/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and …
42020 …x > CAU_PI_NUM/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and …
42039 …x > CAU_NUM_PI/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and …
42043 …x > CAU_PI_NUM/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and …
42062 …x > CAU_NUM_PI/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and …
42066 …x > CAU_PI_NUM/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and …
42165 …e ECC for memory ecc instance cau.cau_pi_mem_368sb_IF.i_cau_pi_mem.i_ecc_0 in module cau_pi_mem_36…
42167 …e ECC for memory ecc instance cau.cau_pi_mem_512sb_IF.i_cau_pi_mem.i_ecc_0 in module cau_pi_mem_51…
42169 …e ECC for memory ecc instance cau.cau_pi_mem_368sb_IF.i_cau_pi_mem.i_ecc_1 in module cau_pi_mem_36…
42171 …e ECC for memory ecc instance cau.cau_pi_mem_512sb_IF.i_cau_pi_mem.i_ecc_1 in module cau_pi_mem_51…
42173 …r memory ecc instance cau.cau_sb_addr_mem_368sb_IF.i_cau_sb_addr_mem.i_ecc in module cau_sb_addr_m…
42175 …r memory ecc instance cau.cau_sb_addr_mem_512sb_IF.i_cau_sb_addr_mem.i_ecc in module cau_sb_addr_m…
42177 …for memory ecc instance cau.cau_sb_var_mem_368sb_IF.i_cau_sb_var_mem.i_ecc in module cau_sb_var_me…
42179 …for memory ecc instance cau.cau_sb_var_mem_512sb_IF.i_cau_sb_var_mem.i_ecc in module cau_sb_var_me…
42181 …0x1<<0) // Enable ECC for memory ecc instance cau.i_cau_agg_unit_mem.i_ecc in module cau_agg_unit_…
42184 … only for memory ecc instance cau.cau_pi_mem_368sb_IF.i_cau_pi_mem.i_ecc_0 in module cau_pi_mem_36…
42186 … only for memory ecc instance cau.cau_pi_mem_512sb_IF.i_cau_pi_mem.i_ecc_0 in module cau_pi_mem_51…
42188 … only for memory ecc instance cau.cau_pi_mem_368sb_IF.i_cau_pi_mem.i_ecc_1 in module cau_pi_mem_36…
42190 … only for memory ecc instance cau.cau_pi_mem_512sb_IF.i_cau_pi_mem.i_ecc_1 in module cau_pi_mem_51…
42192 …r memory ecc instance cau.cau_sb_addr_mem_368sb_IF.i_cau_sb_addr_mem.i_ecc in module cau_sb_addr_m…
42194 …r memory ecc instance cau.cau_sb_addr_mem_512sb_IF.i_cau_sb_addr_mem.i_ecc in module cau_sb_addr_m…
42196 …for memory ecc instance cau.cau_sb_var_mem_368sb_IF.i_cau_sb_var_mem.i_ecc in module cau_sb_var_me…
42198 …for memory ecc instance cau.cau_sb_var_mem_512sb_IF.i_cau_sb_var_mem.i_ecc in module cau_sb_var_me…
42200 …0) // Set parity only for memory ecc instance cau.i_cau_agg_unit_mem.i_ecc in module cau_agg_unit_…
42203 …curred on memory ecc instance cau.cau_pi_mem_368sb_IF.i_cau_pi_mem.i_ecc_0 in module cau_pi_mem_36…
42205 …curred on memory ecc instance cau.cau_pi_mem_512sb_IF.i_cau_pi_mem.i_ecc_0 in module cau_pi_mem_51…
42207 …curred on memory ecc instance cau.cau_pi_mem_368sb_IF.i_cau_pi_mem.i_ecc_1 in module cau_pi_mem_36…
42209 …curred on memory ecc instance cau.cau_pi_mem_512sb_IF.i_cau_pi_mem.i_ecc_1 in module cau_pi_mem_51…
42211 …n memory ecc instance cau.cau_sb_addr_mem_368sb_IF.i_cau_sb_addr_mem.i_ecc in module cau_sb_addr_m…
42213 …n memory ecc instance cau.cau_sb_addr_mem_512sb_IF.i_cau_sb_addr_mem.i_ecc in module cau_sb_addr_m…
42215 … on memory ecc instance cau.cau_sb_var_mem_368sb_IF.i_cau_sb_var_mem.i_ecc in module cau_sb_var_me…
42217 … on memory ecc instance cau.cau_sb_var_mem_512sb_IF.i_cau_sb_var_mem.i_ecc in module cau_sb_var_me…
42219 …ectable error occurred on memory ecc instance cau.i_cau_agg_unit_mem.i_ecc in module cau_agg_unit_…
42224 … (0x3<<0) // The value of the TPH Hint field in the PXP request for …
42226 … (0x3<<4) // The endianity mode in the PXP request.
42228 … (0x1<<6) // The value of the Relax Ordering field in the PXP request.
42230 … (0x1<<7) // The value of the No Snoop field in the PXP request.
42232 … (0x1f<<8) // The value of the VQID field in the PXP request.
42234 … (0x1<<13) // The value of the Pad to Cache Line field in the SB DMA PXP reque…
42236 … (0x7<<15) // The value of the ATC flags in the PXP request.
42238 … (0x1<<18) // The value of the done type in the PXP request.
42240 … (0x3<<2) // The value of the TPH Hint field in the PXP request for …
42242 … (0x1<<14) // The value of the Pad to Cache Line field in the CQE PXP request.
42245 … number of outstanding write requests without receiving write done. Values 1-128. Zero is not a va…
42246 …appropriate bit will be clear. [0] - PI memory; [1] - SB var memory; [2]- SB address memory; [3] -…
42247 …p on the written SB number. [8:0] - SB absolute index; [9] - Cleanup set/clr (0-clr; 1 - set); [12…
42251 … 0x1c0600UL //Access:RW DataWidth:0x1 // Indicate the size of the CQE. 0 - 32B; 1 - 64B.
42252 …W DataWidth:0x2 // Indicate the size of the AGG unit. 0 - 64B; 1 - 128B; 2 - 256B; 3 - illega…
42253 …L //Access:RW DataWidth:0x1 // Flush all command - will flush all the CQE AGG unit that are i…
42255 …in system clock cycles (25MHz). Each expiration will generate an event that affect the FSM of each…
42256 …in each tick of the timer. Clock 25 MHz. value must be bigger than 2. In case this configuration s…
42258 … 0x1c0708UL //Access:RW DataWidth:0xa // Threshold in ticks for indicating…
42259 …etting this bit will disable the timer expiration mechanism. Should be used in close the gate only.
42260 … 0x1c0780UL //Access:R DataWidth:0x20 // Rx timers status. 0 - inactive 1 - active.
42262 … 0x1c0800UL //Access:R DataWidth:0x20 // Tx timers status. 0 - inactive 1 - active.
42266 … 0x1c0980UL //Access:R DataWidth:0x1 // Debug: IGU-CAU request interface credit. In idle…
42267 … 0x1c0984UL //Access:R DataWidth:0x1 // Debug: IGU-CAU command interface credit. In idle…
42293 … timer command type. One bit for each timer command type: [0] - rewind; [1] - clear; [2] - rewind …
42305 … 0x1c0bacUL //Access:RW DataWidth:0x20 // The amount of CQE data that was sent in QWORD.
42306 …:RW DataWidth:0x20 // The number of CQE command that there was a match in the aggregation memo…
42307 …RW DataWidth:0x20 // The number of CQE command that there was no match in the aggregation memo…
42308 …RW DataWidth:0x20 // The number of CQE command that there was no match in the aggregation memo…
42311 …- FIFO empty; 1 - FIFO not empty. [0] - PXP command FIFO; [1] - reserved; [2] - timers expiration …
42312 …- error typ (1- read request; 2 - reserved; 3 - sb_index >= CAU_NUM_SB or SB index > CAU_NUM_PI/n…
42313 …- source (0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM)…
42314 … // Debug; [9] if set data valid; [8] previous FSM_sel; [7:4] - previous state; [3:0] - previous…
42316 …h:0x19 // comment="Debug: [15:0] The PF that caused the error- one bit per PF; [24:16] - SB inde…
42318 …e was writing to agg_units_state_read_en register. (i =0-15). 0 - free; 1 - dirty; 2 - clean; 3 - …
42319 …was writing to agg_units_state_read_en register. (i = 16-31). 0 - free; 1 - dirty; 2 - clean; 3 - …
42320 …was writing to agg_units_state_read_en register. (i = 32-47). 0 - free; 1 - dirty; 2 - clean; 3 - …
42321 …was writing to agg_units_state_read_en register. (i = 48-63). 0 - free; 1 - dirty; 2 - clean; 3 - …
42334 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 1; [7:0] = VF number; if PF - [8…
42336 …// Debug: if set the debug information will be collected for FID specified in debug_record_mask_fi…
42346 … (0x7<<0) // Debug: command type for the debug. [0] - PI producer update; [1] - cleanup; [2] - …
42358 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
42365 … 0x1c0f0cUL //Access:R DataWidth:0x5 // Debug: FSM state for debug.Idle state value are 0-2
42367 … 0x1c2000UL //Access:WB_R DataWidth:0x80 // Debug: Provides read-only access of the CQ…
42369 … 0x1c2200UL //Access:WB_R DataWidth:0x35 // Debug: Provides read-only access of the IG…
42371 … 0x1c2300UL //Access:WB_R DataWidth:0x62 // Debug: Provides read-only access of the PX…
42373 …2400UL //Access:WB_R DataWidth:0x84 // Debug: Provides read-only access of the PXP write-data FI…
42375 … and PI relative number of each aggregation unit. [0] - valid; [9:1] - absolute SB index; [14:10] …
42377 …in the RAM. The bits [7:4] of the address are the current_state and bits [3:0] are the event_id. T…
42379 …in ticks. Valid values are 0-2 only); [49:48] TimerRes1 (This value will determine the TX FSM time…
42387 …ry.[15:0] - protocol producer; [22:16] - PiTimeSet (This value determines the TimeSet that the PI …
42391 … agg_unit_index[5:0]}; Note that line_couner is running index in the slot;
42394 …- address; [71:64] - valid slots; [84:72] - FID ([13:9] - PF number (in case of VF the parent PF);…
42396 …h:0x18 // The SB timers. For each SB there are two timers: [11:0] - RX timer; [23:12] - TX timer.
42400 … 0x1f0000UL //Access:RW DataWidth:0x1 // Soft reset - reset all FSM.
42401 …UL //Access:W DataWidth:0x1 // Any write to this register triggers MAC-VLAN Cache initializa…
42403 …th:0x1 // When set to 1 the cam hit parity scrubbing feature is enabled in the MAC/VLAN cache C…
42404 …h:0x1 // When set to 1 the cam miss parity scrubbing feature is enabled in the MAC/VLAN cache C…
42408 … (0x1<<1) // Load Request Mini-cache validation error
42418 … (0x1<<1) // Load Request Mini-cache validation error
42423 … (0x1<<1) // Load Request Mini-cache validation error
42430 … 0x1f0140UL //Access:RW DataWidth:0x8 // The increment value to send in the TCFC load reques…
42432 …0168UL //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a PF packet, task-…
42433 …016cUL //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a VF packet, task-…
42434 …0170UL //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a PF packet, task-…
42435 …0174UL //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a VF packet, task-…
42437 … 0x1f017cUL //Access:RW DataWidth:0x8 // Context region used in TCFC load requests f…
42438 … 0x1f0180UL //Access:RW DataWidth:0x8 // Context region used in TCFC load requests f…
42439 … 0x1f0184UL //Access:RW DataWidth:0x4 // Connection type used in TCFC load requests f…
42440 … 0x1f0188UL //Access:RW DataWidth:0x4 // Connection type used in TCFC load requests f…
42441 … 0x1f018cUL //Access:RW DataWidth:0x4 // Connection type to be used in RoCE load requests.
42442 … 0x1f0190UL //Access:RW DataWidth:0x1 // Per-PF: If set, override …
42443 …/Access:RW DataWidth:0x20 // Per-opcode requester/responder bit to be used in the CID of RoCE …
42444 … 0x1f0198UL //Access:RW DataWidth:0x1 // Per-PF: If set, a load re…
42445 … 0x1f019cUL //Access:RW DataWidth:0x1 // If set, CFC load mini-cache is enabled.
42446 … 0x1f01a0UL //Access:RW DataWidth:0x1 // 0-search response initiator type,1-Excha…
42447 …//Access:RW DataWidth:0x1 // 0-Exchange Context field in the fcoe search req is zero. 1-Excha…
42622 …ble ECC for memory ecc instance prs.i_msgb_if2_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42624 …ecc instance prs.i_prs_prsu.i_prs_prmsg.i_prs_single_line_fifo_mem_h.i_ecc in module prs_single_li…
42626 …ble ECC for memory ecc instance prs.i_msgb_if2_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42628 …ecc instance prs.i_prs_prsu.i_prs_prmsg.i_prs_single_line_fifo_mem_l.i_ecc in module prs_single_li…
42630 …ecc instance prs.i_prs_prsu.i_prs_prmsg.i_prs_double_line_fifo_mem_h.i_ecc in module prs_double_li…
42632 …ecc instance prs.i_prs_prsu.i_prs_prmsg.i_prs_double_line_fifo_mem_l.i_ecc in module prs_double_li…
42634 …le ECC for memory ecc instance prs.i_prs_prsu.i_prs_prmsg.i_fifo_mem.i_ecc in module prs_local_hdr…
42636 …ble ECC for memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42638 …ble ECC for memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42640 …ble ECC for memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42642 …ble ECC for memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42644 …ble ECC for memory ecc instance prs.i_msgb_if3_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42646 …ble ECC for memory ecc instance prs.i_msgb_if3_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42648 …ble ECC for memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42650 …ble ECC for memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42652 …ble ECC for memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42654 …ble ECC for memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42658 …ty only for memory ecc instance prs.i_msgb_if2_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42660 …ecc instance prs.i_prs_prsu.i_prs_prmsg.i_prs_single_line_fifo_mem_h.i_ecc in module prs_single_li…
42662 …ty only for memory ecc instance prs.i_msgb_if2_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42664 …ecc instance prs.i_prs_prsu.i_prs_prmsg.i_prs_single_line_fifo_mem_l.i_ecc in module prs_single_li…
42666 …ecc instance prs.i_prs_prsu.i_prs_prmsg.i_prs_double_line_fifo_mem_h.i_ecc in module prs_double_li…
42668 …ecc instance prs.i_prs_prsu.i_prs_prmsg.i_prs_double_line_fifo_mem_l.i_ecc in module prs_double_li…
42670 …y only for memory ecc instance prs.i_prs_prsu.i_prs_prmsg.i_fifo_mem.i_ecc in module prs_local_hdr…
42672 …ty only for memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42674 …ty only for memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42676 …ty only for memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42678 …ty only for memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42680 …ty only for memory ecc instance prs.i_msgb_if3_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42682 …ty only for memory ecc instance prs.i_msgb_if3_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42684 …ty only for memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42686 …ty only for memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42688 …ty only for memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42690 …ty only for memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42767 …occurred on memory ecc instance prs.i_msgb_if2_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42769 …ecc instance prs.i_prs_prsu.i_prs_prmsg.i_prs_single_line_fifo_mem_h.i_ecc in module prs_single_li…
42771 …occurred on memory ecc instance prs.i_msgb_if2_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42773 …ecc instance prs.i_prs_prsu.i_prs_prmsg.i_prs_single_line_fifo_mem_l.i_ecc in module prs_single_li…
42775 …ecc instance prs.i_prs_prsu.i_prs_prmsg.i_prs_double_line_fifo_mem_h.i_ecc in module prs_double_li…
42777 …ecc instance prs.i_prs_prsu.i_prs_prmsg.i_prs_double_line_fifo_mem_l.i_ecc in module prs_double_li…
42779 …ccurred on memory ecc instance prs.i_prs_prsu.i_prs_prmsg.i_fifo_mem.i_ecc in module prs_local_hdr…
42781 …occurred on memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42783 …occurred on memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42785 …occurred on memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42787 …occurred on memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42789 …occurred on memory ecc instance prs.i_msgb_if3_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42791 …occurred on memory ecc instance prs.i_msgb_if3_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42793 …occurred on memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42795 …occurred on memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42797 …occurred on memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo…
42799 …occurred on memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo…
42803 … 0x1f0400UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42804 … 0x1f0404UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42805 … 0x1f0408UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42806 … 0x1f040cUL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42809 …0x1<<0) // If this bit is 0, the dest_ip_address_ipv4 field will be masked in the TCP search reque…
42811 …0x1<<1) // If this bit is 0, the dest_ip_address_ipv6 field will be masked in the TCP search reque…
42813 …1<<2) // If this bit is 0, the source_ip_address_ipv4 field will be masked in the TCP search reque…
42815 …1<<3) // If this bit is 0, the source_ip_address_ipv6 field will be masked in the TCP search reque…
42817 … (0x1<<4) // If this bit is 0, the tcp_dest_port field will be masked in the TCP search reque…
42819 … (0x1<<5) // If this bit is 0, the tcp_source_port field will be masked in the TCP search reque…
42821 … (0x1<<6) // If this bit is 0, the ip_version field will be masked in the TCP search reque…
42824 …0x1<<0) // If this bit is 0, the dest_ip_address_ipv4 field will be masked in the UDP search reque…
42826 …0x1<<1) // If this bit is 0, the dest_ip_address_ipv6 field will be masked in the UDP search reque…
42828 …1<<2) // If this bit is 0, the source_ip_address_ipv4 field will be masked in the UDP search reque…
42830 …1<<3) // If this bit is 0, the source_ip_address_ipv6 field will be masked in the UDP search reque…
42832 … (0x1<<4) // If this bit is 0, the udp_dest_port field will be masked in the UDP search reque…
42834 … (0x1<<5) // If this bit is 0, the udp_source_port field will be masked in the UDP search reque…
42836 … (0x1<<6) // If this bit is 0, the ip_version field will be masked in the UDP search reque…
42838 … 0x1f041cUL //Access:RW DataWidth:0x1 // Per-PF: If set, search re…
42839 … 0x1f0420UL //Access:RW DataWidth:0x1 // Per-PF: Enables VF_ID (if it exists) to be sent …
42840 … 0x1f0424UL //Access:RW DataWidth:0x1 // Per-PF: Enables load requ…
42842 … 0x1f042cUL //Access:RW DataWidth:0x11 // Per-PF: Max value for temp_qpid used in RoC…
42843 … 0x1f0430UL //Access:RW DataWidth:0x11 // Per-PF: Max value for temp_qpid used in RoC…
42844 … 0x1f0434UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow …
42845 … 0x1f0438UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow search for non-IP …
42846 … 0x1f043cUL //Access:RW DataWidth:0x1 // Per-PF: If this field is 1, Over-IPv4-prot…
42848 … (0x1<<0) // If this bit is 0, the tcp_source_port field will be masked in the Openflow search …
42850 … (0x1<<1) // If this bit is 0, the udp_source_port field will be masked in the Openflow search …
42852 … (0x1<<2) // If this bit is 0, the sctp_source_port field will be masked in the Openflow search …
42854 … (0x1<<3) // If this bit is 0, the icmp_type field will be masked in the Openflow search …
42856 … (0x1<<4) // If this bit is 0, the tcp_dest_port field will be masked in the Openflow search …
42858 … (0x1<<5) // If this bit is 0, the udp_dest_port field will be masked in the Openflow search …
42860 … (0x1<<6) // If this bit is 0, the sctp_dest_port field will be masked in the Openflow search …
42862 … (0x1<<7) // If this bit is 0, the icmp_code field will be masked in the Openflow search …
42864 … (0x1<<8) // If this bit is 0, the priority field will be masked in the Openflow search …
42866 … (0x1<<9) // If this bit is 0, the ipv4_frag_type field will be masked in the Openflow search …
42868 … (0x1<<10) // If this bit is 0, the dest_mac_address field will be masked in the Openflow search …
42870 …(0x1<<11) // If this bit is 0, the over_ipv4_protocol field will be masked in the Openflow search …
42872 … (0x1<<12) // If this bit is 0, the arp_opcode field will be masked in the Openflow search …
42874 … (0x1<<13) // If this bit is 0, the ipv4_dscp field will be masked in the Openflow search …
42876 …(0x1<<14) // If this bit is 0, the source_mac_address field will be masked in the Openflow search …
42878 …<<15) // If this bit is 0, the source_ip_address_ipv4 field will be masked in the Openflow search …
42880 …1<<16) // If this bit is 0, the source_ip_address_arp field will be masked in the Openflow search …
42882 …x1<<17) // If this bit is 0, the dest_ip_address_ipv4 field will be masked in the Openflow search …
42884 …0x1<<18) // If this bit is 0, the dest_ip_address_arp field will be masked in the Openflow search …
42886 … (0x1<<19) // If this bit is 0, the ethertype field will be masked in the Openflow search …
42888 …-PF: Indicates whether to include the Inner VLAN in the search for each protocol. 0 - TCP, 1 - UDP…
42889 …-PF: Indicates whether to include the Outer TAG in the search for each protocol. 0 - TCP, 1 - UDP,…
42890 …-PF: Indicates whether to include Tenant ID (if it exists) in the search for each encapsulation ty…
42891 … Exists bit in the search request to be 0 if the ID matches the default value. 0 - L2 GRE, 1 - IP…
42892 …// Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated Ethernet…
42893 … // Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated IP ove…
42894 …20 // Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated VXL…
42895 …20 // Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated T-t…
42896 … 0x1f0464UL //Access:RW DataWidth:0x20 // If the Tenant ID exists in the encapsulated Eth…
42897 … 0x1f0468UL //Access:RW DataWidth:0x20 // If the Tenant ID exists in the encapsulated IP …
42898 … 0x1f046cUL //Access:RW DataWidth:0x20 // If the Tenant ID exists in the encapsulated VXL…
42899 …0470UL //Access:RW DataWidth:0x20 // If the Tenant ID exists in the encapsulated T-Tag packet …
42900 …ataWidth:0x3 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. The T-tag bit of …
42901 …x20 // Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated ng…
42902 …x20 // Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated ng…
42903 … 0x1f0480UL //Access:RW DataWidth:0x20 // If the Tenant ID exists in the encapsulated ETH…
42904 … 0x1f0484UL //Access:RW DataWidth:0x20 // If the Tenant ID exists in the encapsulated IP …
42905 …DataWidth:0x1 // MAC port arbitration guarantees fairness at byte-level (0) or packet-level (1).
42906 … DataWidth:0x1 // Main/LB arbitration guarantees fairness at byte-level (0) or packet-level (1).
42909 … 0x1f0510UL //Access:RW DataWidth:0x8 // Size of inter-packet gap and FCS us…
42910 …in the strict priority arbiter. The bits are mapped according to client ID (client IDs are defin…
42911 …d in *_arb_priority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 tra…
42912 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
42913 …bits are for priority 8 client. The clients are assigned the IDs corresponding to their TC # (0-8)
42914 …bits are for priority 8 client. The clients are assigned the IDs corresponding to their TC # (0-8)
42915 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
42916 … 0x1f052cUL //Access:RW DataWidth:0x1 // Enables pseudo-random round robin ar…
42918 … 0x1f0534UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42919 …38UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42921 … 0x1f0540UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42922 …44UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42924 … 0x1f054cUL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42925 …50UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42927 … 0x1f0558UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42928 …5cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42930 … 0x1f0564UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42931 …68UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42933 … 0x1f0570UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42934 …74UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42936 … 0x1f057cUL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42937 …80UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42939 … 0x1f0588UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42940 …8cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42942 … 0x1f0594UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42943 …98UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42945 … 0x1f05a0UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42946 …a4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit reg…
42948 … 0x1f05acUL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42949 …b0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42951 … 0x1f05b8UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42952 …bcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit reg…
42954 … 0x1f05c4UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42955 …c8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42957 … 0x1f05d0UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42958 …d4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit reg…
42960 … 0x1f05dcUL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42961 …e0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42963 … 0x1f05e8UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42964 …ecUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit reg…
42966 … 0x1f05f4UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42967 …f8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42969 … 0x1f0600UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42970 …04UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit reg…
42972 … 0x1f060cUL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42973 …10UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42975 … 0x1f0618UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42976 …1cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit reg…
42978 … 0x1f0624UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42979 …28UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42981 … 0x1f0630UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42982 …34UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit reg…
42984 … 0x1f063cUL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42985 …40UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42987 … 0x1f0648UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42988 …4cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit reg…
42990 … 0x1f0654UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42991 …58UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
42993 … 0x1f0660UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
42994 …64UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit reg…
42995 … 0x1f0700UL //Access:RW DataWidth:0x4 // Per-port: Size of the proprietary header for this po…
42998 …L //Access:RW DataWidth:0x10 // Ethertype for encapsulated ethernet used in GRE header parsing.
43003 … 0x1f0720UL //Access:RW DataWidth:0x8 // Value used to designate TCP in the IPv4 Protocol an…
43004 … 0x1f0724UL //Access:RW DataWidth:0x8 // Value used to designate UDP in the IPv4 Protocol an…
43005 … 0x1f0728UL //Access:RW DataWidth:0x8 // Value used to designate SCTP in the IPv4 Protocol an…
43006 … 0x1f072cUL //Access:RW DataWidth:0x8 // Value used to designate ICMP in the IPv4 Protocol fi…
43007 …ataWidth:0x6 // Per-port: Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - V…
43008 … 0x1f0734UL //Access:RW DataWidth:0x8 // Value used to designate GRE in the IPv4 Protocol an…
43010 … 0x1f073cUL //Access:RW DataWidth:0x10 // Per-PF: Base value used in the TID c…
43011 … 0x1f0740UL //Access:RW DataWidth:0x10 // Per-PF: Base value used in the TID c…
43020 …// The length of the info field for L2 tag 0. The length is between 2B and 14B; in 2B granularity.
43021 …// The length of the info field for L2 tag 1. The length is between 2B and 14B; in 2B granularity.
43022 …// The length of the info field for L2 tag 2. The length is between 2B and 14B; in 2B granularity.
43023 …// The length of the info field for L2 tag 3. The length is between 2B and 14B; in 2B granularity.
43024 …// The length of the info field for L2 tag 4. The length is between 2B and 14B; in 2B granularity.
43025 …// The length of the info field for L2 tag 5. The length is between 2B and 14B; in 2B granularity.
43026 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
43027 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
43028 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
43029 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
43030 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
43031 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
43032 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
43033 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
43034 … 0x1f079cUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43035 … 0x1f07a0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43036 … 0x1f07a4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43037 … 0x1f07a8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43038 … 0x1f07acUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43039 … 0x1f07b0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43040 … 0x1f07b4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43041 … 0x1f07b8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating which headers must appe…
43044 …tion address match value. A zero in this register will cause the corresponding bit…
43045 …tion address match value. A zero in this register will cause the corresponding bit…
43046 … 0x1f07ccUL //Access:RW DataWidth:0x20 // Per-PF/Per-port: Destination …
43047 … 0x1f07d0UL //Access:RW DataWidth:0x10 // Per-PF/Per-port: Destination …
43048 … 0x1f07d4UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43049 … 0x1f07d8UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43050 … 0x1f07dcUL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43051 … 0x1f07e0UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43052 … 0x1f07e4UL //Access:RW DataWidth:0x2 // Per-PF: Destination IP address match value - …
43053 … 0x1f07e8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43054 … 0x1f07ecUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43055 … 0x1f07f0UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43056 … 0x1f07f4UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43057 … 0x1f07f8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43058 … 0x1f07fcUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43059 … 0x1f0800UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43060 … 0x1f0804UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43061 … 0x1f0808UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43062 … 0x1f080cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43063 … 0x1f0810UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43064 … 0x1f0814UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43065 … 0x1f0818UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43066 … 0x1f081cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43067 … 0x1f0820UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43068 … 0x1f0824UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43069 … 0x1f0828UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43070 … 0x1f082cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43071 … 0x1f0830UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43072 … 0x1f0834UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43073 … 0x1f0838UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43074 … 0x1f083cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43075 … 0x1f0840UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43076 … 0x1f0844UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43077 … 0x1f0848UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43078 … 0x1f084cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43079 … 0x1f0850UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43080 … 0x1f0854UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43081 … 0x1f0858UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43082 … 0x1f085cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43083 … 0x1f0860UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43084 … 0x1f0864UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43085 …L //Access:RW DataWidth:0x10 // Ethertype for encapsulated ethernet used in NGE header parsing.
43088 … 0x1f0874UL //Access:RW DataWidth:0x1 // Per-port: Flag enabling …
43089 … 0x1f0878UL //Access:RW DataWidth:0x1 // Per-port: Flag to compar…
43093 …errored packets. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43095 … (0x3<<18) // Affinity type to be used in the CM header.
43098 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43100 …o match in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdS…
43102 … (0x3<<18) // Affinity type to be used in the CM header.
43104 … (0x1<<20) // en_l2_ma to be used in storm context update…
43106 … (0x3<<21) // l2_ma_config to be used in storm context update…
43108 … (0x1<<23) // inc_sn to be used in storm context update…
43111 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43113 …o match in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdS…
43115 … (0x3<<18) // Affinity type to be used in the CM header.
43117 … (0x1<<20) // en_l2_ma to be used in storm context update…
43119 … (0x3<<21) // l2_ma_config to be used in storm context update…
43121 … (0x1<<23) // inc_sn to be used in storm context update…
43124 … (0xff<<0) // Event ID for packets that hit in the MAC/VLAN cache
43126 …hat hit in the MAC/VLAN cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdS…
43128 … (0x3<<18) // Affinity type to be used in the CM header.
43130 … (0x1<<20) // en_l2_ma to be used in storm context update…
43132 … (0x3<<21) // l2_ma_config to be used in storm context update…
43134 … (0x1<<23) // inc_sn to be used in storm context update…
43139 …er for light L2. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43141 … (0x3<<18) // Affinity type to be used in the CM header.
43146 …regular packets. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43148 … (0x3<<18) // Affinity type to be used in the CM header.
43150 … (0x1<<20) // en_l2_ma to be used in storm context update…
43152 … (0x3<<21) // l2_ma_config to be used in storm context update…
43154 … (0x1<<23) // inc_sn to be used in storm context update…
43156 … an FCoE packet. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43157 … 0x1f093cUL //Access:RW DataWidth:0x4 // Connection type for no-match packets.
43158 … 0x1f0940UL //Access:RW DataWidth:0x4 // Per-port: PFID for no-match packet…
43159 … 0x1f0944UL //Access:RW DataWidth:0x1 // Per-PF: If set, the PFID may be overridden for n…
43160 … 0x1f0948UL //Access:RW DataWidth:0x20 // Per-PF: CID for no-match packets.
43161 … 0x1f094cUL //Access:RW DataWidth:0x9 // Per-PF: LCID for no-match packets.
43169 … 0x1f096cUL //Access:RW DataWidth:0x1 // Per-PF: If set, and PF cl…
43170 … first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - L2 GR…
43171 … first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - L2 GR…
43172 … first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - L2 GR…
43173 …-PF: Indicates whether to include Tenant ID (if it exists) in the MAC VLAN Cache entry for each en…
43174 …-VLAN Cache Flexible Field. If two blocks are used, this block is used for the upper bytes. 14:11…
43175 …the MAC-VLAN Cache Flexible Field. This block is only used if the number of bytes in mac_vlan_fle…
43176 …ng block information in mac_vlan_flex_upper and/or mac_vlan_flex_lower. A zero in this register w…
43177 …ng block information in mac_vlan_flex_upper and/or mac_vlan_flex_lower. A zero in this register w…
43178 … 0x1f09d0UL //Access:RW DataWidth:0x1 // Per-PF: If set, the SACK …
43179 …-FCoE packets. This allows Over-L2-Raw Part2 to be available on non-RoCE packets. The RoCE specifi…
43180 … 0x1f09d8UL //Access:RW DataWidth:0x20 // Per-PF: Mask used in RDMA SYN coo…
43181 … 0x1f09dcUL //Access:RW DataWidth:0x20 // Seeds used in RDMA SYN cookie calc…
43182 … 0x1f09e0UL //Access:RW DataWidth:0x20 // Seeds used in RDMA SYN cookie calc…
43183 … 0x1f09e4UL //Access:RW DataWidth:0x20 // Seeds used in RDMA SYN cookie calc…
43184 … 0x1f09e8UL //Access:RW DataWidth:0x20 // Seeds used in RDMA SYN cookie calc…
43185 … 0x1f09ecUL //Access:RW DataWidth:0x20 // Seeds used in RDMA SYN cookie calc…
43186 … 0x1f09f0UL //Access:RW DataWidth:0x20 // Seeds used in RDMA SYN cookie calc…
43187 … 0x1f09f4UL //Access:RW DataWidth:0x20 // Seeds used in RDMA SYN cookie calc…
43188 … 0x1f09f8UL //Access:RW DataWidth:0x20 // Seeds used in RDMA SYN cookie calc…
43189 … 0x1f09fcUL //Access:RW DataWidth:0x1 // Per-PF: Enables SYN cooki…
43190 … 0x1f0a00UL //Access:RW DataWidth:0x1 // Per-PF: If set, enables i…
43191 …1 // Per-PF: If set, 4B for Ethernet CRC is included in Packet Length for Statistics field. For…
43192 …-PF: For each bit set, the length of the corresponding tag in the inner header will be subtracted …
43193 …-PF: For each bit set, the length of the corresponding tag in the first header will be subtracted …
43194 …L //Access:RW DataWidth:0x1 // Per-Port: If set and classification failed, 4B for Ethernet CR…
43195 …ess:RW DataWidth:0x8 // Per-Port: If classification failed, for each bit set, the length of t…
43196 …ess:RW DataWidth:0x9 // Per-Port: If classification failed, for each bit set, the length of t…
43197 …f0a1cUL //Access:RW DataWidth:0x20 // Per-PF: This value is passed to the per-PF configuration…
43198 … 0x1f0a20UL //Access:RW DataWidth:0x2 // Per-Port: This value goes in the NIG …
43199 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 0. In …
43200 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 0. In 4…
43201 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 1. In …
43202 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 1. In 4…
43203 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 2. In …
43204 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 2. In 4…
43205 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 3. In …
43206 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 3. In 4…
43207 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 4. In …
43208 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 4. In 4…
43209 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 5. In …
43210 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 5. In 4…
43211 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 6. In …
43212 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 6. In 4…
43213 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 7. In …
43214 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 7. In 4…
43215 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 8. In 4…
43216 …0x1f0a68UL //Access:RW DataWidth:0x3 // bit 0 - ignore for VXLAN, bit 1 - ignore for NGE, bit…
43232 …he counter in the Input Arbiter that keeps track of the number of packets that have been selected …
43233 …-port): Packet available status of the main and loopback queues of each traffic class, before bein…
43234 …dth:0x18 // Debug only (per-port): STORM backpressure status (blocked priorities) Each set bit r…
43236 …In case of LCID validation error, the current value of the single entry in the CID load mini-cache…
43238 … 0x1f0b68UL //Access:R DataWidth:0xd // Debug only: In the case of a mini-cache LCID …
43240 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
43250 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
43251 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
43266 …kts sent to TCM: Reserved - 127:66, Parsing and Error flags - 65:50, Start block - 49:37, Priority…
43269 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
43277 … 0x1f0f00UL //Access:RW DataWidth:0x8 // The initial credit in the packet start mes…
43278 … 0x1f0f00UL //Access:RW DataWidth:0x8 // The initial credit in the packet start mes…
43291 … // Debug only: Outstanding SOP request count. The value of the counter in the BRB Interface Un…
43292 … // Debug only: Outstanding EOP request count. The value of the counter in the BRB Interface Un…
43293 … 0x1f0f38UL //Access:RW DataWidth:0x8 // The initial credit in the packet start mes…
43303 … 0x1f0f8cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
43307 …-encasulated packet): 40.Source MAC 39.Destination MAC 38.VLAN (12b) ) � Tag 1 37.Provider VLAN (1…
43309 …-14 data 14-11 PF ID (3bit BB 4bit K2) 10-7 Tunnel type (4b) 0000-no tunnel 0001-vxlan 0010-GRE MA…
43324 …0x1 // used to build the priority field in the GFT used frame fields inner header 0- use CVLAN …
43325 …0x1 // used to build the priority field in the GFT used frame fields tunnel header 0- use CVLAN…
43326 … 0x1f11bcUL //Access:RW DataWidth:0x1 // Per-PF: Enables gft searc…
43327 … 0x1f11c0UL //Access:RW DataWidth:0x1 // Per-PF: Enables gft search for non-IP pac…
43328 … the connection type returned in the search response equal to this value, use the CM_HDR_GFT intea…
43332 …onnection type . Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43334 … (0x3<<18) // Affinity type to be used in the CM header.
43377 …t region for received Ethernet packet with a match and packet type 0. Used in CFC load request mes…
43378 …t region for received Ethernet packet with a match and packet type 0. Used in CFC load request mes…
43379 …t region for received Ethernet packet with a match and packet type 1. Used in CFC load request mes…
43380 …t region for received Ethernet packet with a match and packet type 1. Used in CFC load request mes…
43381 …t region for received Ethernet packet with a match and packet type 2. Used in CFC load request mes…
43382 …t region for received Ethernet packet with a match and packet type 2. Used in CFC load request mes…
43383 …t region for received Ethernet packet with a match and packet type 3. Used in CFC load request mes…
43384 …t region for received Ethernet packet with a match and packet type 3. Used in CFC load request mes…
43385 …t region for received Ethernet packet with a match and packet type 4. Used in CFC load request mes…
43386 …t region for received Ethernet packet with a match and packet type 4. Used in CFC load request mes…
43387 …t region for received Ethernet packet with a match and packet type 5. Used in CFC load request mes…
43388 …t region for received Ethernet packet with a match and packet type 5. Used in CFC load request mes…
43389 …t region for received Ethernet packet with a match and packet type 6. Used in CFC load request mes…
43390 …t region for received Ethernet packet with a match and packet type 6. Used in CFC load request mes…
43391 …t region for received Ethernet packet with a match and packet type 7. Used in CFC load request mes…
43392 …t region for received Ethernet packet with a match and packet type 7. Used in CFC load request mes…
43393 …t region for received Ethernet packet with a match and packet type 8. Used in CFC load request mes…
43394 …t region for received Ethernet packet with a match and packet type 9. Used in CFC load request mes…
43395 … region for received Ethernet packet with a match and packet type 10. Used in CFC load request mes…
43396 … region for received Ethernet packet with a match and packet type 11. Used in CFC load request mes…
43397 … region for received Ethernet packet with a match and packet type 12. Used in CFC load request mes…
43398 … region for received Ethernet packet with a match and packet type 13. Used in CFC load request mes…
43399 … region for received Ethernet packet with a match and packet type 14. Used in CFC load request mes…
43400 … region for received Ethernet packet with a match and packet type 15. Used in CFC load request mes…
43401 …1f14dcUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for ipv…
43402 …1f14e0UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for ipv…
43403 …1f14e4UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for agg…
43404 …1f14e8UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for agg…
43405 …1f14ecUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for agg…
43406 …1f14f0UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for agg…
43407 …1f14f4UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for tun…
43408 …1f14f8UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for tun…
43409 …1f14fcUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for tun…
43410 …1f1500UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for tun…
43411 …1f1504UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for cac…
43412 …1f1508UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for cac…
43413 …1f150cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for reg…
43414 …1f1510UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for reg…
43415 …1f1514UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in RGFS message for ipv…
43416 …1f1518UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in RGFS message for ipv…
43417 …1f151cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in RGFS message for agg…
43418 …1f1520UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in RGFS message for agg…
43419 …1f1524UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in RGFS message for agg…
43420 …1f1528UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in RGFS message for agg…
43421 …1f152cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in RGFS message for tun…
43422 …1f1530UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in RGFS message for tun…
43423 …1f1534UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in RGFS message for tun…
43424 …1f1538UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in RGFS message for tun…
43425 …1f153cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in RGFS message for cac…
43426 …1f1540UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in RGFS message for cac…
43427 …1f1544UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in RGFS message for reg…
43428 …1f1548UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in RGFS message for reg…
43429 …/ Context region for pure acknowledge packets with connection type 0. Used in CFC load request mes…
43430 …/ Context region for pure acknowledge packets with connection type 0. Used in CFC load request mes…
43431 …/ Context region for pure acknowledge packets with connection type 1. Used in CFC load request mes…
43432 …/ Context region for pure acknowledge packets with connection type 1. Used in CFC load request mes…
43433 …/ Context region for pure acknowledge packets with connection type 2. Used in CFC load request mes…
43434 …/ Context region for pure acknowledge packets with connection type 2. Used in CFC load request mes…
43435 …/ Context region for pure acknowledge packets with connection type 3. Used in CFC load request mes…
43436 …/ Context region for pure acknowledge packets with connection type 3. Used in CFC load request mes…
43437 …/ Context region for pure acknowledge packets with connection type 4. Used in CFC load request mes…
43438 …/ Context region for pure acknowledge packets with connection type 4. Used in CFC load request mes…
43439 …/ Context region for pure acknowledge packets with connection type 5. Used in CFC load request mes…
43440 …/ Context region for pure acknowledge packets with connection type 5. Used in CFC load request mes…
43441 …/ Context region for pure acknowledge packets with connection type 6. Used in CFC load request mes…
43442 …/ Context region for pure acknowledge packets with connection type 6. Used in CFC load request mes…
43443 …/ Context region for pure acknowledge packets with connection type 7. Used in CFC load request mes…
43444 …/ Context region for pure acknowledge packets with connection type 7. Used in CFC load request mes…
43445 …/ Context region for pure acknowledge packets with connection type 8. Used in CFC load request mes…
43446 …/ Context region for pure acknowledge packets with connection type 9. Used in CFC load request mes…
43447 … Context region for pure acknowledge packets with connection type 10. Used in CFC load request mes…
43448 … Context region for pure acknowledge packets with connection type 11. Used in CFC load request mes…
43449 … Context region for pure acknowledge packets with connection type 12. Used in CFC load request mes…
43450 … Context region for pure acknowledge packets with connection type 13. Used in CFC load request mes…
43451 … Context region for pure acknowledge packets with connection type 14. Used in CFC load request mes…
43452 … Context region for pure acknowledge packets with connection type 15. Used in CFC load request mes…
43453 … 0x1f0144UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43454 … 0x1f158cUL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43455 … 0x1f0148UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43456 … 0x1f1590UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43457 … 0x1f014cUL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43458 … 0x1f1594UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43459 … 0x1f0150UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43460 … 0x1f1598UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43461 … 0x1f0154UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43462 … 0x1f159cUL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43463 … 0x1f0158UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43464 … 0x1f15a0UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43465 … 0x1f015cUL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43466 … 0x1f15a4UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43467 … 0x1f0160UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43468 … 0x1f15a8UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43469 … 0x1f15acUL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43470 … 0x1f15b0UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43471 … 0x1f15b4UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43472 … 0x1f15b8UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43473 … 0x1f15bcUL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43474 … 0x1f15c0UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43475 … 0x1f15c4UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43476 … 0x1f15c8UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC load reques…
43481 …nnection type 0. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43483 … (0x3<<18) // Affinity type to be used in the CM header.
43489 …nnection type 1. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43491 … (0x3<<18) // Affinity type to be used in the CM header.
43497 …nnection type 2. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43499 … (0x3<<18) // Affinity type to be used in the CM header.
43505 …nnection type 3. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43507 … (0x3<<18) // Affinity type to be used in the CM header.
43513 …nnection type 4. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43515 … (0x3<<18) // Affinity type to be used in the CM header.
43521 …nnection type 5. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43523 … (0x3<<18) // Affinity type to be used in the CM header.
43529 …nnection type 6. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43531 … (0x3<<18) // Affinity type to be used in the CM header.
43537 …nnection type 7. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43539 … (0x3<<18) // Affinity type to be used in the CM header.
43544 …nnection type 8. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43546 … (0x3<<18) // Affinity type to be used in the CM header.
43551 …nnection type 9. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43553 … (0x3<<18) // Affinity type to be used in the CM header.
43558 …nection type 10. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43560 … (0x3<<18) // Affinity type to be used in the CM header.
43565 …nection type 11. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43567 … (0x3<<18) // Affinity type to be used in the CM header.
43572 …nection type 12. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43574 … (0x3<<18) // Affinity type to be used in the CM header.
43579 …nection type 13. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43581 … (0x3<<18) // Affinity type to be used in the CM header.
43586 …nection type 14. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43588 … (0x3<<18) // Affinity type to be used in the CM header.
43593 …nection type 15. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43595 … (0x3<<18) // Affinity type to be used in the CM header.
43597 …1f097cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in TSTORM message for c…
43598 …1f160cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43599 …1f0980UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in TSTORM message for c…
43600 …1f1610UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43601 …1f0984UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in TSTORM message for c…
43602 …1f1614UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43603 …1f0988UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in TSTORM message for c…
43604 …1f1618UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43605 …1f098cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in TSTORM message for c…
43606 …1f161cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43607 …1f0990UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in TSTORM message for c…
43608 …1f1620UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43609 …1f0994UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in TSTORM message for c…
43610 …1f1624UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43611 …1f0998UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in TSTORM message for c…
43612 …1f1628UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43613 …1f099cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in TSTORM message for c…
43614 …1f162cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43615 …1f09a0UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in TSTORM message for c…
43616 …1f1630UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43617 …1f09a4UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in TSTORM message for c…
43618 …1f1634UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43619 …1f09a8UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in TSTORM message for c…
43620 …1f1638UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43621 …1f09acUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in TSTORM message for c…
43622 …1f163cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43623 …1f09b0UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in TSTORM message for c…
43624 …1f1640UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43625 …1f09b4UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in TSTORM message for c…
43626 …1f1644UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43627 …1f09b8UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in TSTORM message for c…
43628 …1f1648UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43629 …1f164cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43630 …1f1650UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43631 …1f1654UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43632 …1f1658UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43633 …1f165cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43634 …1f1660UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43635 …1f1664UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43636 …1f1668UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43637 …1f166cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43638 …1f1670UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43639 …1f1674UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43640 …1f1678UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43641 …1f167cUL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43642 …1f1680UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43643 …1f1684UL //Access:RW DataWidth:0x20 // Ordered list of building blocks in PTLD message for con…
43644 …1f1688UL //Access:RW DataWidth:0x10 // Ordered list of building blocks in PTLD message for con…
43648 …/ The CM header. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43650 … (0x3<<18) // Affinity type to be used in the CM header.
43652 … (0x1<<20) // en_l2_ma to be used in storm context update…
43654 … (0x3<<21) // l2_ma_config to be used in storm context update…
43656 … (0x1<<23) // inc_sn to be used in storm context update…
43661 …/ The CM header. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43663 … (0x3<<18) // Affinity type to be used in the CM header.
43665 … (0x1<<20) // en_l2_ma to be used in storm context update…
43667 … (0x3<<21) // l2_ma_config to be used in storm context update…
43669 … (0x1<<23) // inc_sn to be used in storm context update…
43674 …/ The CM header. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggC…
43676 … (0x3<<18) // Affinity type to be used in the CM header.
43678 … (0x1<<20) // en_l2_ma to be used in storm context update…
43680 … (0x3<<21) // l2_ma_config to be used in storm context update…
43682 … (0x1<<23) // inc_sn to be used in storm context update…
43685 … 0x1f169cUL //Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on TCP 4 tuple. 0- p…
43686 … 0x1f16a0UL //Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on UDP 4 tuple. 0- p…
43687 … 0x1f16a4UL //Access:RW DataWidth:0x10 // Used in the aggregatable dec…
43688 … 0x1f16a8UL //Access:RW DataWidth:0x10 // Used in the aggregatable dec…
43689 … 0x1f16acUL //Access:RW DataWidth:0x20 // Used in the aggregatable dec…
43690 … 0x1f16b0UL //Access:RW DataWidth:0x10 // Used in the aggregatable dec…
43691 … 0x1f16b4UL //Access:RW DataWidth:0x10 // Used in the aggregatable dec…
43692 … 0x1f16b8UL //Access:RW DataWidth:0x10 // Used in the aggregatable dec…
43693 … 0x1f16bcUL //Access:RW DataWidth:0x20 // Used in the aggregatable dec…
43694 … 0x1f16c0UL //Access:RW DataWidth:0x10 // Used in the aggregatable dec…
43695 … 0x1f16c4UL //Access:RW DataWidth:0x1 // Used in the mac vlan cache
43696 … 0x1f16c8UL //Access:RW DataWidth:0x1 // Used in the mac vlan cache
43697 … 0x1f16ccUL //Access:RW DataWidth:0x1 // Used in the mac vlan cache
43698 … 0x1f16d0UL //Access:RW DataWidth:0x1 // Used in the mac vlan cache
43699 … 0x1f16d4UL //Access:RW DataWidth:0x1 // Used in the mac vlan cache
43700 … 0x1f16d8UL //Access:RW DataWidth:0x1 // Used in the mac vlan cache
43701 … 0x1f16dcUL //Access:RW DataWidth:0x8 // Used in the source affinity …
43702 … 0x1f16e0UL //Access:RW DataWidth:0x20 // Used in the source affinity …
43703 … 0x1f16e4UL //Access:RW DataWidth:0x1 // Used in the source affinity …
43704 … 0x1f16e8UL //Access:RW DataWidth:0x1 // Used in the source affinity …
43706 …ataWidth:0x1 // Burst mode enabled. Set this bits to have the main round-robin arbiter stays o…
43713 …rom TX to RX. This loopback is on the line side after clock domain crossing - from the last TX pip…
43715 …om TX to RX. This loopback is on the core side before clock domain crossing - from the first TX pi…
43717 …om RX to TX. This loopback is on the line side before clock domain crossing - from the first RX pi…
43719 …rom RX to TX. This loopback is on the core side after clock domain crossing - from the last RX pip…
43723 … (0x1<<7) // Enables SOP; SOM & Sequence alignment to 8 byte boundaries; as defined in 40G mode.
43729 … (0x1<<10) // Resets the RS layer functionality - fault handling.
43731 …column idle/sequence ordered set check before SOP in XGMII mode - effectively supporting 1 byte IP…
43740 … (0x1<<3) // If set; exclude the SOP byte for CRC calculation in HG modes.
43770 …RW DataWidth:0x20 // Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC packets tr…
43771 …RW DataWidth:0x10 // Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC packets tr…
43775 … (0x1<<1) // True to allow any non-Idle character to sta…
43779 …the MAC checks for IEEE Ethernet format premable - K.SOP + 5 '55' premable bytes + 'D5' SFD charac…
43783 …ceive packet size is reduced to 18 bytes from the default 33 bytes - Should be used in MACSEC chip…
43787 … // Lower 48 bits of rx_sa register. SA recognized for MAC control packets in addition to the stan…
43788 … // Upper 48 bits of rx_sa register. SA recognized for MAC control packets in addition to the stan…
43789 …cess:RW DataWidth:0xe // Maximum packet size in receive direction; exclusive of preamble & CR…
43805 …; the TX faults inputs are used to send out fault sequences - else receive faults are used -- used…
43825 … (0x1<<0) // A rising edge on this register bit (0->1); clears the stick…
43827 … (0x1<<1) // A rising edge on this register bit (0->1); clears the stick…
43829 … (0x1<<2) // A rising edge on this register bit (0->1); clears the stick…
43832 …<<0) // This field is Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
43838 … (0x1<<18) // Process PAUSE Frames in the receive directio…
43842 …x1<<20) // If set; the recive pause is used to stop the frame transmission in the GMII convertor b…
43844 …bits of pause_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 …
43846 …bits of pause_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 …
43848 … (0xffff<<0) // Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
43850 … (0xffff<<16) // Time value sent in the Timer Field for classes in XOFF state (Unit is…
43853 … (0x1<<0) // Enable automatic re-send of PFC packet af…
43867 … DataWidth:0x20 // Lower 48 bits of pfc_macda register. Used as the DA in PFC packets transmit…
43868 … DataWidth:0x10 // Upper 48 bits of pfc_macda register. Used as the DA in PFC packets transmit…
43870 … (0x1<<0) // This bit enables llfc for Tx path in XMAC; works with llfc_en in xport.
43872 … (0x1<<1) // This bit enables llfc for Rx path in XMAC; works with llfc_en in xport.
43876 … (0x1<<3) // When set and llfc_in_ipg_only =0; GXPORT operates in cut-through mode.
43901 … (0x1<<0) // This bit enables HCFC for Tx path in XMAC.
43903 … (0x1<<1) // This bit enables HCFC for Rx path in XMAC.
43931 … (0x1<<0) // A rising edge on this register bit (0->1); clears the stick…
43933 … (0x1<<1) // A rising edge on this register bit (0->1); clears the stick…
43935 … (0x1<<2) // A rising edge on this register bit (0->1); clears the stick…
43937 … (0x1<<3) // A rising edge on this register bit (0->1); clears the stick…
43939 … (0x1<<4) // A rising edge on this register bit (0->1); clears the stick…
43941 … (0x1<<5) // A rising edge on this register bit (0->1); clears the stick…
43943 … (0x1<<6) // A rising edge on this register bit (0->1); clears the stick…
43946 … (0x3f<<0) // Credits for TX FIFO; used by Ports 0/1/2/3 in quad port mode.
43948 … (0x3f<<6) // Credits for TX FIFO; used by Port 0 & 2 in dual port mode.
43950 … (0x3f<<12) // Credits for TX FIFO; used by Port 0 in single port mode.
43955 …x1<<1) // If set; EEE FSM can go to EMPTY state even when transmit path is in XOFF state and Refre…
43957 …x1<<2) // If set; EEE FSM can go to EMPTY state even when transmit path is in XOFF state per PFC i…
43961 …st be satisfied; at the end of which MAC transitions to LPI State. This is in terms of micro secon…
43963 …IVE state from LPI state when it receives packet for transmission. This is in terms of micro secon…
43967 …n Link status becomes active before transitioning to ACTIVE state. This is in terms of micro secon…
43973 … (0x1<<17) // When set to 1; GMII interface will shut down TXCLK to PHY; when in LPI state.
43980 …C_CORRUPTION_MODE_BB (0x1<<2) // In CRC corruption mode;…
43982 …g_tx_crc register. Programmable CRC value to corrupt the Tx CRC to be used in MACSEC. The computed…
43984 …g_tx_crc register. Programmable CRC value to corrupt the Tx CRC to be used in MACSEC. The computed…
43985 … 0x210130UL //Access:RW DataWidth:0x10 // XMAC IP Version ID - corresponds to RTL/D…
43986 …ss for version of the register at XMAC TX_CTRL. The register can be access in either this loation …
43988 … for version of the register at XMAC TX_MAC_SA. The register can be access in either this loation …
43990 … for version of the register at XMAC RX_MAC_SA. The register can be access in either this loation …
43992 …for version of the register at XMAC PAUSE_CTRL. The register can be access in either this loation …
43994 …ess for version of the register at XMAC PFC_DA. The register can be access in either this loation …
43996 …or version of the register at XMAC MACSEC_CTRL. The register can be access in either this loation …
44007 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44009 … (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, re…
44011 … (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, an…
44013 …8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity …
44015 …9) // This bit controls the option for corrupting the calculated CRC value in TX path when error i…
44019 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44027 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44029 … (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, re…
44031 … (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, an…
44033 …8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity …
44035 …9) // This bit controls the option for corrupting the calculated CRC value in TX path when error i…
44039 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44047 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44049 … (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, re…
44051 … (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, an…
44053 …8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity …
44055 …9) // This bit controls the option for corrupting the calculated CRC value in TX path when error i…
44059 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44068 …TO_INC_SIZE_BB (0xf<<4) // In Port Macro the regis…
44079 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44081 … (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, re…
44083 … (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, an…
44085 …8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity …
44087 …9) // This bit controls the option for corrupting the calculated CRC value in TX path when error i…
44091 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44098 … (0x1<<2) // 1 : Last transaction resulted in an error
44101 …1<<0) // This regiseter enables loopback mode (used for debug) 0 - loopback inactive 1 - loopback …
44130 …saction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
44132 …saction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
44136 …saction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
44138 …saction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
44184 …TO_INC_SIZE_BB (0xf<<4) // In Port Macro the regis…
44196 …saction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
44198 …saction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
44202 …saction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
44204 …saction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
44221 … (0x1<<2) // 1 : Last transaction resulted in an error
44229 …saction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
44231 …saction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
44235 …saction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
44237 …saction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
44264 …_TRAFFIC bit bit is also set; the LED will blink with blink rate specified in LED_CONTROL_BLINK_RA…
44266 …_TRAFFIC LED bit; the Traffic LED will blink with the blink rate specified in LED_CONTROL_BLINK_RA…
44270 …in milliseconds. Must be a non-zero value. This 12-bit field is reset to 0x162; giving a default b…
44274 … // Led mode: 0 -> MAC; 1-3 -> PHY1; 4 -> MAC2; 5-7 -> PHY4; 8 -> MAC3; 9 -…
44275 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44276 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44277 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44280 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44283 …In a typical setup, Physical function 0 is connected to Network Port 0, PF1 to NW1 and so on. Howe…
44285 … corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connects to PF1 2 -> NW1 co…
44287 … corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1 2 -> NW2 co…
44289 … corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1 2 -> NW3 co…
44291 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
44292 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44294 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44296 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44298 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44299 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44300 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44301 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44302 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44303 … DataWidth:0x1 // When set, PMIF block uses values in following registers to configure NIG - …
44304 …hese bits are used to set which NIG Ports are used with the PM4x10. A 1'b0 in these bits indicates…
44307 …G port is assigned to each PMEG Port. [1:0] -- PMEG Port 0 [3:2] -- PMEG Port 1 [5:4] -- PMEG Port…
44308 …G port is assigned to each PMFC Port. [1:0] -- PMFC Port 0 [3:2] -- PMFC Port 1 [5:4] -- PMFC Port…
44309 …e value in this register is added to the PMEG Port ID every cycle. Valid values are: 0 -- Only Por…
44310 …e value in this register is added to the PMFC Port ID every cycle. Valid values are: 0 -- Only Por…
44312 … to the PM unless the current number of credits is greater than the number in this register. This…
44313 … to the PM unless the current number of credits is greater than the number in this register. This…
44374 …in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC c…
44375 …in CNIG TX datapath, and append CRC field at the end of the packet. Note: this mode can be active…
44376 …in TX path when Parity or error indication is received from NIG. Note: a. This mode can be active…
44377 …in TX path when error indication is received from NIG. Note: a. This mode can be active only for P…
44399 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44401 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44403 … (0x1<<7) // End of packet error on M-Storm command interfa…
44405 … (0x1<<8) // End of packet error on U-Storm command interfa…
44445 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44447 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44449 … (0x1<<7) // End of packet error on M-Storm command interfa…
44451 … (0x1<<8) // End of packet error on U-Storm command interfa…
44468 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44470 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44472 … (0x1<<7) // End of packet error on M-Storm command interfa…
44474 … (0x1<<8) // End of packet error on U-Storm command interfa…
44611 …CC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_secto…
44613 …CC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_secto…
44615 …CC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_secto…
44617 …CC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_secto…
44619 …CC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_secto…
44621 … (0x1<<3) // Enable ECC for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
44623 … (0x1<<3) // Enable ECC for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
44625 …CC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_secto…
44627 … (0x1<<3) // Enable ECC for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
44630 …ly for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_secto…
44632 …ly for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_secto…
44634 …ly for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_secto…
44636 …ly for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_secto…
44638 …ly for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_secto…
44640 …<<3) // Set parity only for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
44642 …<<3) // Set parity only for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
44644 …ly for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_secto…
44646 …<<3) // Set parity only for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
44649 …red on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_secto…
44651 …red on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_secto…
44653 …red on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_secto…
44655 …red on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_secto…
44657 …red on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_secto…
44659 …rrectable error occurred on memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
44661 …rrectable error occurred on memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
44663 …red on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_secto…
44665 …rrectable error occurred on memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
44668 …in units of two bytes) for each of the possible seven configurable L2 tags to remove, where the di…
44670 … 0x230420UL //Access:RW DataWidth:0x10 // Provides the value of the 16-bit pad that will be …
44673 … Initial credit to be used on the RDIF command interface for regular (non-pass-through) requests. …
44674 …on the RDIF command interface for pass-through requests. This value defines the maximum number of …
44675 …s:RW DataWidth:0x6 // Defines the number of occupied entries required in the RPB data buffer …
44676 …s:RW DataWidth:0x8 // Defines the number of occupied entries required in the RPB task queue b…
44677 …s:RW DataWidth:0x5 // Defines the number of occupied entries required in the BRB input FIFO b…
44678 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
44679 …DataWidth:0x9 // Defines the number of occupied entries required in the PXP read-response FIFO …
44680 … DataWidth:0x20 // Statistics counter provides a count of the number of M-Storm comands that ha…
44681 … DataWidth:0x20 // Statistics counter provides a count of the number of U-Storm comands that ha…
44706 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
44710 … 0x232000UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the M-Storm comma…
44712 … 0x232400UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the U-Storm comma…
44714 … 0x232800UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the BR…
44716 … 0x232c00UL //Access:R DataWidth:0x7 // Provides read-only access of the BR…
44718 … 0x233000UL //Access:WB_R DataWidth:0x2c // Provides read-only access of the ta…
44720 … 0x233400UL //Access:R DataWidth:0x11 // Provides read-only access of the pa…
44722 … 0x233600UL //Access:R DataWidth:0xb // Provides read-only access of the PB…
44724 … 0x233800UL //Access:WB_R DataWidth:0x100 // Provides read-only access of the PR…
44726 … 0x233c00UL //Access:R DataWidth:0x8 // Provides read-only access of the PXP write-done re…
44736 … (0x1<<16) // Enable for VLAN in Hash Address. !!! NO…
44748 … (0x1<<22) // Enables the use of the tenant_id value in Hash address calcula…
44772 …ccess:RW DataWidth:0xc // Key for searcher hash function vlan field. HAS NO EFFECT IN E4 B0!!!
44773 … 0x238480UL //Access:RW DataWidth:0x10 // Per-PF Bitmask for inclusion in Ingress…
44774 … 0x238484UL //Access:RW DataWidth:0x8 // Per-StringType Bitmask for inclusion in Ing…
44782 … 0x238500UL //Access:WB DataWidth:0x40 // First free element in the free list of T2 …
44784 … 0x238520UL //Access:WB DataWidth:0x40 // Last free element in the free list of T2 …
44786 … 0x238540UL //Access:RW DataWidth:0x16 // Number of free element in the free list of T2 …
44802 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
44858 … (0x1<<21) // Received RSS hash command where f4tuple_offset field puts f4tuple in the tmld header.
44860 … (0x1<<1) // Number of cycles in CM message from TSEM…
44862 … (0x1<<2) // Number of cycles in CM message to TM loa…
44868 … (0x1<<5) // Main state machine in RSS calculation bloc…
44870 … (0x1<<6) // CALC state machine in RSS calculation bloc…
44948 … (0x1<<21) // Received RSS hash command where f4tuple_offset field puts f4tuple in the tmld header.
44950 … (0x1<<1) // Number of cycles in CM message from TSEM…
44952 … (0x1<<2) // Number of cycles in CM message to TM loa…
44958 … (0x1<<5) // Main state machine in RSS calculation bloc…
44960 … (0x1<<6) // CALC state machine in RSS calculation bloc…
44993 … (0x1<<21) // Received RSS hash command where f4tuple_offset field puts f4tuple in the tmld header.
44995 … (0x1<<1) // Number of cycles in CM message from TSEM…
44997 … (0x1<<2) // Number of cycles in CM message to TM loa…
45003 … (0x1<<5) // Main state machine in RSS calculation bloc…
45005 … (0x1<<6) // CALC state machine in RSS calculation bloc…
45029 … (0x1<<0) // Enable ECC for memory ecc instance rss.i_rss_info_ram.i_ecc in module rss_info_ram
45031 … (0x1<<1) // Enable ECC for memory ecc instance rss.i_rss_key_ram.i_ecc in module rss_key_ram
45033 … (0x1<<2) // Enable ECC for memory ecc instance rss.i_rss_cid_ram.i_ecc in module rss_cid_ram
45035 … (0x1<<3) // Enable ECC for memory ecc instance rss.i_rss_ind_ram.i_ecc in module rss_ind_ram
45037 …able ECC for memory ecc instance rss.RSS_MEM_K2_GEN_IF.i_rss_mem_ram.i_ecc in module rss_mem_4port…
45039 …able ECC for memory ecc instance rss.RSS_IND_K2_GEN_IF.i_rss_ind_ram.i_ecc in module rss_ind_4port…
45042 …(0x1<<0) // Set parity only for memory ecc instance rss.i_rss_info_ram.i_ecc in module rss_info_ram
45044 … (0x1<<1) // Set parity only for memory ecc instance rss.i_rss_key_ram.i_ecc in module rss_key_ram
45046 … (0x1<<2) // Set parity only for memory ecc instance rss.i_rss_cid_ram.i_ecc in module rss_cid_ram
45048 … (0x1<<3) // Set parity only for memory ecc instance rss.i_rss_ind_ram.i_ecc in module rss_ind_ram
45050 …ity only for memory ecc instance rss.RSS_MEM_K2_GEN_IF.i_rss_mem_ram.i_ecc in module rss_mem_4port…
45052 …ity only for memory ecc instance rss.RSS_IND_K2_GEN_IF.i_rss_ind_ram.i_ecc in module rss_ind_4port…
45055 …a correctable error occurred on memory ecc instance rss.i_rss_info_ram.i_ecc in module rss_info_ram
45057 …f a correctable error occurred on memory ecc instance rss.i_rss_key_ram.i_ecc in module rss_key_ram
45059 …f a correctable error occurred on memory ecc instance rss.i_rss_cid_ram.i_ecc in module rss_cid_ram
45061 …f a correctable error occurred on memory ecc instance rss.i_rss_ind_ram.i_ecc in module rss_ind_ram
45063 … occurred on memory ecc instance rss.RSS_MEM_K2_GEN_IF.i_rss_mem_ram.i_ecc in module rss_mem_4port…
45065 … occurred on memory ecc instance rss.RSS_IND_K2_GEN_IF.i_rss_ind_ram.i_ecc in module rss_ind_4port…
45070 …am_data for appropriate location will be written. Other way data will stay in this place without c…
45072 …register will generate read or write transaction to RSS memory. Write data in this register will s…
45076 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45077 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45078 …0x20 // Debug register. FIFO empty status: {b15:8 - inp_fifo_counter; b7:6- cmd_fifo_couter; b5:…
45079 …ster. State of each state machine {b15:12 - calc_cur_state; b11:8 - main_cur_state;b7:4 - msg_cur_…
45082 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
45149 … (0xf<<0) // number of valid words in the inp fifo.
45151 … (0x1f<<4) // number of valid words in the msg fifo.
45153 … (0x7<<9) // number of valid words in the cmd fifo.
45155 … (0x3<<12) // number of valid words in the header fifo.
45157 … (0x3<<14) // number of valid words in the info fifo.
45159 … (0x3<<16) // number of valid words in the key_low fifo.
45161 … (0x3<<18) // number of valid words in the key_mid fifo.
45163 … (0x3<<20) // number of valid words in the key_high fifo.
45165 … (0x3<<22) // number of valid words in the tuple fifo.
45167 … (0x3<<24) // number of valid words in the hash fifo.
45169 … (0x3<<26) // number of valid words in the hash_tuple fifo.
45171 … (0x3<<28) // number of valid words in the ind_hash fifo.
45173 … (0x3<<30) // number of valid words in the rsp fifo.
45286 …an error received on the ingress interface will be masked for instructions in which the "dummy rea…
45309 …bug register. This register stores the calculated CRC value that resulted in the most recent CRC …
45310 …nstruction is the first instruction in the task. Bit 29 indicates whether the instruction is the …
45320 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
45324 … 0x23e000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
45328 …L //Access:RW DataWidth:0x1 // Driver should write 1 to this register in order to signal the …
45331 …ataWidth:0x4 // Page size in L2P table for CDU-Task module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6…
45332 … DataWidth:0x4 // Page size in L2P table for CDU module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-25…
45333 … DataWidth:0x4 // Page size in L2P table for TM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-25…
45334 … DataWidth:0x4 // Page size in L2P table for QM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-25…
45335 … DataWidth:0x4 // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-25…
45336 … DataWidth:0x4 // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-25…
45337 … DataWidth:0x4 // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-25…
45338 … DataWidth:0x4 // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-25…
45339 … DataWidth:0x4 // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-25…
45340 … 0x240030UL //Access:RW DataWidth:0xe // First memory address base for tm in ILT.
45341 … 0x240034UL //Access:RW DataWidth:0xe // Last memory address base for tm in ILT.
45342 … 0x240038UL //Access:RW DataWidth:0xe // First memory address base for qm in ILT.
45343 … 0x24003cUL //Access:RW DataWidth:0xe // Last memory address base for qm in ILT.
45344 … 0x240040UL //Access:RW DataWidth:0xe // First memory address base for src in ILT.
45345 … 0x240044UL //Access:RW DataWidth:0xe // Last memory address base for src in ILT.
45346 … 0x240048UL //Access:RW DataWidth:0xe // First memory address base for cdu-connection in ILT.
45347 … 0x24004cUL //Access:RW DataWidth:0xe // Last memory address base for cdu-connection in ILT.
45348 … 0x240050UL //Access:RW DataWidth:0xe // First memory address base for cdu-task in ILT.
45349 … 0x240054UL //Access:RW DataWidth:0xe // Last memory address base for cdu-task in ILT.
45350 … 0x240058UL //Access:RW DataWidth:0xe // First memory address base for xsdm in ILT.
45351 … 0x24005cUL //Access:RW DataWidth:0xe // Last memory address base for xsdm in ILT.
45352 … 0x240060UL //Access:RW DataWidth:0xe // First memory address base for tsdm in ILT.
45353 … 0x240064UL //Access:RW DataWidth:0xe // Last memory address base for tsdm in ILT.
45354 … 0x240068UL //Access:RW DataWidth:0xe // First memory address base for usdm in ILT.
45355 … 0x24006cUL //Access:RW DataWidth:0xe // Last memory address base for usdm in ILT.
45356 … 0x240070UL //Access:RW DataWidth:0xe // First memory address base for dbg in ILT.
45357 … 0x240074UL //Access:RW DataWidth:0xe // Last memory address base for dbg in ILT.
45378 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
45387 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45389 … (0x1<<2) // Overflow in src write done fifo.
45391 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45393 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45395 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45397 …s then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; …
45399 … (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all …
45403 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glu…
45405 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45407 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45409 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45411 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45413 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45415 … (0x1<<15) // Overflow in the short wdone fifo.
45417 … (0x1<<16) // Overflow in the SR submit fifo.
45461 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45463 … (0x1<<2) // Overflow in src write done fifo.
45465 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45467 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45469 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45471 …s then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; …
45473 … (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all …
45477 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glu…
45479 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45481 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45483 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45485 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45487 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45489 … (0x1<<15) // Overflow in the short wdone fifo.
45491 …5 (0x1<<16) // Overflow in the SR submit fifo.
45498 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45500 … (0x1<<2) // Overflow in src write done fifo.
45502 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45504 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45506 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45508 …s then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; …
45510 … (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all …
45514 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glu…
45516 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45518 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45520 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45522 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45524 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45526 … (0x1<<15) // Overflow in the short wdone fifo.
45528 …E5 (0x1<<16) // Overflow in the SR submit fifo.
45582 … (0x1<<1) // Enable ECC for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr…
45584 … (0x1<<2) // Enable ECC for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr…
45586 … (0x1<<0) // Enable ECC for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p…
45588 …1<<1) // Enable ECC for memory ecc instance pswrq.i_pswrq_mem_vqmem1.i_ecc in module pswrq_mem_vqm…
45590 …1<<2) // Enable ECC for memory ecc instance pswrq.i_pswrq_mem_vqmem2.i_ecc in module pswrq_mem_vqm…
45592 … (0x1<<0) // Enable ECC for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p…
45594 …0x1<<1) // Enable ECC for memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p…
45600 …(0x1<<1) // Set parity only for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr…
45602 …(0x1<<2) // Set parity only for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr…
45604 …0x1<<0) // Set parity only for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p…
45606 … // Set parity only for memory ecc instance pswrq.i_pswrq_mem_vqmem1.i_ecc in module pswrq_mem_vqm…
45608 … // Set parity only for memory ecc instance pswrq.i_pswrq_mem_vqmem2.i_ecc in module pswrq_mem_vqm…
45610 …0x1<<0) // Set parity only for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p…
45612 …1) // Set parity only for memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p…
45617 …a correctable error occurred on memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr…
45619 …a correctable error occurred on memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr…
45621 … correctable error occurred on memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p…
45623 …table error occurred on memory ecc instance pswrq.i_pswrq_mem_vqmem1.i_ecc in module pswrq_mem_vqm…
45625 …table error occurred on memory ecc instance pswrq.i_pswrq_mem_vqmem2.i_ecc in module pswrq_mem_vqm…
45627 … correctable error occurred on memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p…
45629 …ectable error occurred on memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p…
45634 …W DataWidth:0x3 // Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010:…
45635 …RW DataWidth:0x3 // Max burst size filed for read requests port 0; 000 - 128B; 001:256B; 010:…
45638 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45639 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45640 … DataWidth:0x3 // This number indicates how many entries are guaranteed to usdm in the queues.
45641 …W DataWidth:0x3 // This number indicates how many entries are guaranteed to prm in the queues.
45642 … DataWidth:0x3 // This number indicates how many entries are guaranteed to tsdm in the queues.
45643 … DataWidth:0x3 // This number indicates how many entries are guaranteed to xsdm in the queues.
45644 …W DataWidth:0x3 // This number indicates how many entries are guaranteed to rwh in the queues.
45645 … DataWidth:0x3 // This number indicates how many entries are guaranteed to cduwr in the queues.
45646 … DataWidth:0x3 // This number indicates how many entries are guaranteed to cdurd in the queues.
45647 …W DataWidth:0x7 // This number indicates how many entries are guaranteed to pbf in the queues.
45648 …RW DataWidth:0x3 // This number indicates how many entries are guaranteed to qm in the queues.
45649 …RW DataWidth:0x3 // This number indicates how many entries are guaranteed to tm in the queues.
45650 …W DataWidth:0x3 // This number indicates how many entries are guaranteed to src in the queues.
45651 … DataWidth:0x3 // This number indicates how many entries are guaranteed to debug in the queues.
45652 …RW DataWidth:0x2 // This number indicates how many entries are guaranteed to hc in the queues.
45653 …DataWidth:0x8 // Initial value of global counter; This value MUST be 256 - sum of all clients t…
45659 … 0x240454UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 0 in pswrq memory.
45660 … 0x240458UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 1 in pswrq memory.
45661 … 0x24045cUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 2 in pswrq memory.
45662 … 0x240460UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 3 in pswrq memory.
45663 … 0x240464UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 4 in pswrq memory.
45664 … 0x240468UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 5 in pswrq memory.
45665 … 0x24046cUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 6 in pswrq memory.
45666 … 0x240470UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 7 in pswrq memory.
45667 … 0x240474UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 8 in pswrq memory.
45668 … 0x240478UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 9 in pswrq memory.
45669 … 0x24047cUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 10 in pswrq memory.
45670 … 0x240480UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 11 in pswrq memory.
45671 … 0x240484UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 12 in pswrq memory.
45672 … 0x240488UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 13 in pswrq memory.
45673 … 0x24048cUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 14 in pswrq memory.
45674 … 0x240490UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 15 in pswrq memory.
45675 … 0x240494UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 16 in pswrq memory.
45676 … 0x240498UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 17 in pswrq memory.
45677 … 0x24049cUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 18 in pswrq memory.
45678 … 0x2404a0UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 19 in pswrq memory.
45679 … 0x2404a4UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 20 in pswrq memory.
45680 … 0x2404a8UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 21 in pswrq memory.
45681 … 0x2404acUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 22 in pswrq memory.
45682 … 0x2404b0UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 23 in pswrq memory.
45683 … 0x2404b4UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 24 in pswrq memory.
45684 … 0x2404b8UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 25 in pswrq memory.
45685 … 0x2404bcUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 26 in pswrq memory.
45686 … 0x2404c0UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 27 in pswrq memory.
45687 … 0x2404c4UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 28 in pswrq memory.
45688 … 0x2404c8UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 29 in pswrq memory.
45689 … 0x2404ccUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 30 in pswrq memory.
45690 … 0x2404d0UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 31 in pswrq memory.
45723 … 0x240554UL //Access:R DataWidth:0x5 // Number of entries in the ufifo;This fifo …
45740 … (0x1<<0) // Relaxed oredering attribute for cdu. Removed in E4B0, PXP request fl…
45742 … (0x1<<1) // Nosnoop attribute for cdu. Removed in E4B0, PXP request fl…
46001 … 0x2406a0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ5 Read- currently not used.
46090 … (0x3ff<<0) // Bandwidth addition for read requests in the read write arbit…
46092 … (0x1ff<<10) // Bandwidth upperbound for read requests in the read write arbit…
46094 … (0x1ff<<19) // Bandwidth Typical L for read requests in the read write arbit…
46097 … (0x3ff<<0) // Bandwidth addition for write requests in the read write arbit…
46099 … (0x1ff<<10) // Bandwidth upperbound for write requests in the read write arbit…
46101 … (0x1ff<<19) // Bandwidth Typical L for write requests in the read write arbit…
46104 … (0xf<<0) // Indicates the number of credits for read sub-requests in th requester gl…
46106 … (0x1f<<4) // Indicates the number of credits for write sub-requests in th requester gl…
46109 …8 // When number of free entries in the context ram will be lower than this;the input clients a…
46110 … 0x240720UL //Access:RW DataWidth:0xe // Pending read limiter threshold; in Dwords.
46111 … 0x240724UL //Access:RW DataWidth:0x5 // Sets which vq head pointer to see out of queues 0-31.
46112 … 0x240728UL //Access:RW DataWidth:0x5 // Sets which vq tail pointer to see out of queues 0-31.
46113 …idth:0x1 // Will determine how the logical address is calculated; 0: as in E1; 1:with new algor…
46146 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46147 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46148 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46149 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46150 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46151 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46152 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46153 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46154 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46155 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46156 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46157 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46158 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46159 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46160 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46161 …- SR from the VQ can send ATC lookup request to the ATC (assuming all other conditions are met). W…
46162 …ATC enable values per PF as follows: b0 - PF enable; b1 - VF enable; PF enable bit is relevant whe…
46163 …ues of rq_atc_internal_ats_enable as follows: b0 - PF0; b1 - VF0; b2 - PF1; b3 - VF1; b30 - PF15 ;…
46164 …he GLUE with the at_valid=1 indication (see atc_code in PSWRQ-PGLUE interface for more details). I…
46165 …e same as RD_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core.
46166 … 0x240800UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i.e. can be chosen by the GA…
46167 …-s that are enabled (i.e. can be chosen by the GARB) in close the gates scenario; VQ32 = TREQ; VQ3…
46168 … 0x240808UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i.e. can be chosen by the GA…
46169 …-s that are enabled (i.e. can be chosen by the GARB) in stall mem scenario; VQ32 = TREQ; VQ33 = IC…
46170 … 0x240810UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i.e. can be chosen by the GA…
46171 …-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ33 = IC…
46175 …- assert ilt fail interrupt (rq_elt_addr) in case working in ilt mode and onchip translation fail …
46176 …from the hoq ram; the write data represents the address which is the vqid; in order to read from t…
46178 …FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 d…
46182 … //Access:R DataWidth:0x20 // FOR DBG: bit 0 relaxed ordering; bit 1 no-snoop; bits 5:2 clien…
46183 … 0x240844UL //Access:R DataWidth:0x20 // The total number of WR SR-s that were sent to t…
46184 … 0x240848UL //Access:R DataWidth:0x20 // The total number of RD SR-s that were sent to t…
46185 … 0x24084cUL //Access:R DataWidth:0x20 // The number of PBF RD SR-s that were sent to t…
46186 … 0x240850UL //Access:R DataWidth:0x20 // The number of USDM-DP WR SR-s that were sent …
46187 … 0x240854UL //Access:R DataWidth:0x20 // The number of TREQ SR-s that were sent to t…
46188 … 0x240858UL //Access:R DataWidth:0x20 // The number of ICPL SR-s that were sent to t…
46189 …20 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46190 …9 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46191 …20 // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46192 …c // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46193 …0x20 // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46194 …0xc // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46195 …:0x20 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46196 …:0x9 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46197 … // Counting window mode. 0 - manual window: counting is manually being initiated & stopped by t…
46198 …h:0x20 // Determines the size of the counting window. Valid when working in predefined window mo…
46200 …d sent by the user. Valid when working in manual window mode (i.e. Sr_cnt_window_mode = 0). 0 - st…
46201 …is reg (any value) will reset the SR counters & the global window counter. In addition it'll move …
46202 …global window counter). 0 - start counting upon any first SR that is sent to the PGLUE. 1 - start …
46205 …atus of the SR count mechanism: 0 - idle: ready to start new counting. 1 - ongoing: counting is cu…
46206 … 0x2408a0UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46207 … 0x2408a4UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46208 … 0x2408a8UL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46209 …dth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client …
46210 … 0x2408b0UL //Access:R DataWidth:0x9 // bit 8-0: srid.
46211 … 0x2408b4UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46212 … 0x2408b8UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46213 … 0x2408bcUL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46214 … DataWidth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15…
46215 … 0x2408c4UL //Access:R DataWidth:0xa // b1-0: atc code; b2: wdone type; b4-3: endianity; …
46216 … DataWidth:0x3 // This number indicates how many entries are guaranteed to msdm in the queues.
46217 … DataWidth:0x3 // This number indicates how many entries are guaranteed to ysdm in the queues.
46218 … DataWidth:0x3 // This number indicates how many entries are guaranteed to psdm in the queues.
46219 … DataWidth:0x3 // This number indicates how many entries are guaranteed to muld in the queues.
46220 …W DataWidth:0x3 // This number indicates how many entries are guaranteed to ptu in the queues.
46226 …W DataWidth:0x3 // This number indicates how many entries are guaranteed to m2p in the queues.
46237 … DataWidth:0x3 // This number indicates how many entries are guaranteed to xyld in the queues.
46243 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46244 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46245 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46246 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46247 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46249 …only. Round trip measurement of latest request that was measured. Measured in clk_pci cycles (375 …
46250 …ent value from the time rmm_enable register was written with '1'. Measured in clk_pci cycles (375 …
46251 …ent value from the time rmm_enable register was written with '1'. Measured in clk_pci cycles (375 …
46255 … 0x240924UL //Access:RW DataWidth:0x2 // In case this register i…
46258 …l2p_vf_err or rq_elt_addr interrupt. [12:0] - Length in bytes. [16:13] - PFID. [17] - VF_VALID. …
46259 …:16] client ID. [21] - Error type - 0 - rq_l2p_vf_err; 1 - rq_elt_addr. [22] - w_nr - 0 - read; 1 …
46261 …:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must be big…
46262 …cess:RW DataWidth:0xa // Debug only: Total number of available blocks in Tetris Buffer. Must …
46263 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46264 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46265 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46266 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46267 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46268 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46269 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46270 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46271 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46272 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46273 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46274 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46275 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46276 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46277 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46278 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46279 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46280 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46281 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46282 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46283 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46284 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46285 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46286 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46287 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46288 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46289 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46290 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46291 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46294 … of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be …
46295 … 0x2409c4UL //Access:R DataWidth:0x9 // Debug only: The SR counter - number of unused sub…
46328 …0x240a48UL //Access:R DataWidth:0xa // Debug only: The blocks counter - number of unused blo…
46361 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46362 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46363 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46364 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46365 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46366 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46367 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46368 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46369 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46370 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46371 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46372 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46373 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46374 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46375 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46376 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46377 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46378 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46379 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46380 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46381 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46382 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46383 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46384 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46385 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46386 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46387 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46388 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46389 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46390 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46391 … 0x240b44UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46392 … 0x240b48UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46393 … 0x240b4cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46394 … 0x240b50UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46395 … 0x240b54UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46396 … 0x240b58UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46397 … 0x240b5cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46398 … 0x240b60UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46399 … 0x240b64UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46400 … 0x240b68UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46401 … 0x240b6cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46402 … 0x240b70UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46403 … 0x240b74UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46404 … 0x240b78UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46405 … 0x240b7cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46406 … 0x240b80UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46407 … 0x240b84UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46408 … 0x240b88UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46409 … 0x240b8cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46410 … 0x240b90UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46411 … 0x240b94UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46412 … 0x240b98UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46413 … 0x240b9cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46414 … 0x240ba0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46415 … 0x240ba4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46416 … 0x240ba8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46417 … 0x240bacUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46418 … 0x240bb0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46419 … 0x240bb4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46420 … 0x240bb8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46421 … 0x240bbcUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46422 … 0x240bc0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46427 …idth:0x1 // GARB config: 1 indicates read SRs have strict priority over write SRs in RW arbiter.
46429 … no BWC is greater or equal to Li. Default value: 0. This is a chicken bit in case there are probl…
46430 …- the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters…
46431 …- the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters…
46432 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46433 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46434 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46435 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46436 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46437 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46438 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46439 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46440 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46441 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46442 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46443 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46444 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46445 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46446 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46447 …Q: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with s…
46448 …-PGLUE request interface write credit; 0 - no more credit for wr SR-s (i.e. write SR-s cannot be s…
46449 …-PGLUE request interface read credit; 0 - no more credit for rd SR-s (i.e. read SR-s cannot be sen…
46450 …rived. This can be a workaround for possible bugs in the byte counters. Id-s are based on wr clien…
46451 …-1] between qc_cmg_add_2_q (indication that new request is written into hoq0) and cmg_qc_del_head …
46452 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46453 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46454 … 0x240c40UL //Access:R DataWidth:0xe // For debug and Idle-check use. The value …
46456 …ite done for them from the PGLUE). Upon reaching the threshold no more wr SR-s will be sent by the…
46513 …DataWidth:0x4 // Page size in L2P table for tgsrc module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-2…
46514 …DataWidth:0x4 // Page size in L2P table for RGSRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-2…
46515 … 0x240d04UL //Access:RW DataWidth:0xe // First memory address base for tgsrc in ILT.
46516 … 0x240d08UL //Access:RW DataWidth:0xe // First memory address base for rgsrc in ILT.
46517 … 0x240d0cUL //Access:RW DataWidth:0xe // Last memory address base for tgsrc in ILT.
46518 … 0x240d10UL //Access:RW DataWidth:0xe // Last memory address base for rgsrc in ILT.
46519 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46520 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46521 …eop counter per wr client. Describes the number of packets that are stored in the pswwr client fif…
46522 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46523 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46524 … byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fif…
46552 …nternal lookup table for logical to physical address translation. Re-instantiated in E4 due to siz…
46559 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
46569 … (0x1<<1) // Overflow in pbf request input fi…
46571 … (0x1<<2) // Overflow in src request input fi…
46573 … (0x1<<3) // Overflow in qm request input fif…
46575 … (0x1<<4) // Overflow in tm request fifo.
46577 … (0x1<<5) // Overflow in usdm request input f…
46579 … (0x1<<6) // Overflow in m2p request input fi…
46581 … (0x1<<7) // Overflow in xsdm request input f…
46583 … (0x1<<8) // Overflow in tsdm request input f…
46585 … (0x1<<9) // Overflow in ptu request input fi…
46587 … (0x1<<10) // Overflow in cduwr request input …
46589 … (0x1<<11) // Overflow in cdurd request input …
46591 … (0x1<<12) // Overflow in dmae request input f…
46593 … (0x1<<13) // Overflow in hc request input fif…
46595 … (0x1<<14) // Overflow in dbg request input fi…
46597 … (0x1<<15) // Overflow in msdm request input f…
46599 … (0x1<<16) // Overflow in ysdm request input f…
46601 … (0x1<<17) // Overflow in psdm request input f…
46603 … (0x1<<18) // Overflow in prm request input fi…
46605 … (0x1<<19) // Overflow in muld request input f…
46607 … (0x1<<20) // Overflow in muld request input f…
46609 … (0x1<<21) // Overflow in tgsrc request input …
46611 … (0x1<<22) // Overflow in rgsrc request input …
46663 … (0x1<<1) // Overflow in pbf request input fi…
46665 … (0x1<<2) // Overflow in src request input fi…
46667 … (0x1<<3) // Overflow in qm request input fif…
46669 … (0x1<<4) // Overflow in tm request fifo.
46671 … (0x1<<5) // Overflow in usdm request input f…
46673 … (0x1<<6) // Overflow in m2p request input fi…
46675 … (0x1<<7) // Overflow in xsdm request input f…
46677 … (0x1<<8) // Overflow in tsdm request input f…
46679 … (0x1<<9) // Overflow in ptu request input fi…
46681 … (0x1<<10) // Overflow in cduwr request input …
46683 … (0x1<<11) // Overflow in cdurd request input …
46685 … (0x1<<12) // Overflow in dmae request input f…
46687 … (0x1<<13) // Overflow in hc request input fif…
46689 … (0x1<<14) // Overflow in dbg request input fi…
46691 … (0x1<<15) // Overflow in msdm request input f…
46693 … (0x1<<16) // Overflow in ysdm request input f…
46695 … (0x1<<17) // Overflow in psdm request input f…
46697 … (0x1<<18) // Overflow in prm request input fi…
46699 … (0x1<<19) // Overflow in muld request input f…
46701 … (0x1<<20) // Overflow in muld request input f…
46703 … (0x1<<21) // Overflow in tgsrc request input …
46705 … (0x1<<22) // Overflow in rgsrc request input …
46710 … (0x1<<1) // Overflow in pbf request input fi…
46712 … (0x1<<2) // Overflow in src request input fi…
46714 … (0x1<<3) // Overflow in qm request input fif…
46716 … (0x1<<4) // Overflow in tm request fifo.
46718 … (0x1<<5) // Overflow in usdm request input f…
46720 … (0x1<<6) // Overflow in m2p request input fi…
46722 … (0x1<<7) // Overflow in xsdm request input f…
46724 … (0x1<<8) // Overflow in tsdm request input f…
46726 … (0x1<<9) // Overflow in ptu request input fi…
46728 … (0x1<<10) // Overflow in cduwr request input …
46730 … (0x1<<11) // Overflow in cdurd request input …
46732 … (0x1<<12) // Overflow in dmae request input f…
46734 … (0x1<<13) // Overflow in hc request input fif…
46736 … (0x1<<14) // Overflow in dbg request input fi…
46738 … (0x1<<15) // Overflow in msdm request input f…
46740 … (0x1<<16) // Overflow in ysdm request input f…
46742 … (0x1<<17) // Overflow in psdm request input f…
46744 … (0x1<<18) // Overflow in prm request input fi…
46746 … (0x1<<19) // Overflow in muld request input f…
46748 … (0x1<<20) // Overflow in muld request input f…
46750 … (0x1<<21) // Overflow in tgsrc request input …
46752 … (0x1<<22) // Overflow in rgsrc request input …
46757 … 0x29a040UL //Access:RW DataWidth:0x4 // If number of entries in the usdm fifo is big…
46758 … 0x29a044UL //Access:RW DataWidth:0x4 // If number of entries in the msdm fifo is big…
46759 … 0x29a048UL //Access:RW DataWidth:0x4 // If number of entries in the ysdm fifo is big…
46760 … 0x29a04cUL //Access:RW DataWidth:0x4 // If number of entries in the psdm fifo is big…
46761 … 0x29a050UL //Access:RW DataWidth:0x4 // If number of entries in the xsdm fifo is big…
46762 … 0x29a054UL //Access:RW DataWidth:0x4 // If number of entries in the tsdm fifo is big…
46763 … 0x29a058UL //Access:RW DataWidth:0x4 // If number of entries in M2P fifo is bigger t…
46764 … 0x29a05cUL //Access:RW DataWidth:0x3 // If number of entries in the qm fifo is bigge…
46765 … 0x29a060UL //Access:RW DataWidth:0x4 // If number of entries in the tm fifo is bigge…
46766 … 0x29a064UL //Access:RW DataWidth:0x4 // If number of entries in the src fifo is bigg…
46767 … 0x29a068UL //Access:RW DataWidth:0x4 // If number of entries in the dbg fifo is bigg…
46768 … 0x29a06cUL //Access:RW DataWidth:0x4 // If number of entries in the hc fifo is bigge…
46769 … 0x29a070UL //Access:RW DataWidth:0x4 // If number of entries in the dmae input fifo …
46770 … 0x29a074UL //Access:RW DataWidth:0x4 // If number of entries in the cdu input fifo i…
46771 … 0x29a078UL //Access:RW DataWidth:0x4 // If number of entries in the usdmdp input fif…
46772 …- TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM; 5 - PSDM; 6 - QM; 7 - TM; 8 - SRC; 9 - DMAE; 10 - …
46773 …- TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM; 5 - PSDM; 6 - QM; 7 - TM; 8 - SRC; 9 - DMAE; 10 - …
46775 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
46784 … 0x29a0ccUL //Access:RW DataWidth:0x4 // If number of entries in the PRM Secondary in…
46785 … 0x29a0d0UL //Access:RW DataWidth:0x4 // If number of entries in the RGSRC input fifo…
46786 … 0x29a0d4UL //Access:RW DataWidth:0x4 // If number of entries in the TGSRC input fifo…
46790 … (0x1<<1) // Overflow in src input fifo.
46792 … (0x1<<2) // Overflow in qm input fifo.
46794 …OW (0x1<<3) // Overflow in tm fifo.
46796 … (0x1<<4) // Overflow in usdm input fifo.
46798 … (0x1<<5) // Overflow in usdmdp input fifo.
46800 … (0x1<<6) // Overflow in xsdm input fifo.
46802 … (0x1<<7) // Overflow in tsdm input fifo.
46804 … (0x1<<8) // Overflow in cduwr input fifo.
46806 … (0x1<<9) // Overflow in dbg input fifo.
46808 … (0x1<<10) // Overflow in dmae input fifo.
46810 … (0x1<<11) // Overflow in hc input fifo.
46812 … (0x1<<12) // Overflow in msdm write input fif…
46814 … (0x1<<13) // Overflow in ysdm write input fif…
46816 … (0x1<<14) // Overflow in psdm write input fif…
46818 … (0x1<<15) // Overflow in M2P input fifo.
46820 … (0x1<<16) // Overflow in PRM Secondary input …
46822 … (0x1<<17) // Overflow in RGSRC input fifo.
46824 … (0x1<<18) // Overflow in TGSRC input fifo.
46868 … (0x1<<1) // Overflow in src input fifo.
46870 … (0x1<<2) // Overflow in qm input fifo.
46872 …RFLOW (0x1<<3) // Overflow in tm fifo.
46874 … (0x1<<4) // Overflow in usdm input fifo.
46876 … (0x1<<5) // Overflow in usdmdp input fifo.
46878 … (0x1<<6) // Overflow in xsdm input fifo.
46880 … (0x1<<7) // Overflow in tsdm input fifo.
46882 … (0x1<<8) // Overflow in cduwr input fifo.
46884 … (0x1<<9) // Overflow in dbg input fifo.
46886 … (0x1<<10) // Overflow in dmae input fifo.
46888 … (0x1<<11) // Overflow in hc input fifo.
46890 … (0x1<<12) // Overflow in msdm write input fif…
46892 … (0x1<<13) // Overflow in ysdm write input fif…
46894 … (0x1<<14) // Overflow in psdm write input fif…
46896 … (0x1<<15) // Overflow in M2P input fifo.
46898 … (0x1<<16) // Overflow in PRM Secondary input …
46900 …5 (0x1<<17) // Overflow in RGSRC input fifo.
46902 …5 (0x1<<18) // Overflow in TGSRC input fifo.
46907 … (0x1<<1) // Overflow in src input fifo.
46909 … (0x1<<2) // Overflow in qm input fifo.
46911 …ERFLOW (0x1<<3) // Overflow in tm fifo.
46913 … (0x1<<4) // Overflow in usdm input fifo.
46915 … (0x1<<5) // Overflow in usdmdp input fifo.
46917 … (0x1<<6) // Overflow in xsdm input fifo.
46919 … (0x1<<7) // Overflow in tsdm input fifo.
46921 … (0x1<<8) // Overflow in cduwr input fifo.
46923 … (0x1<<9) // Overflow in dbg input fifo.
46925 … (0x1<<10) // Overflow in dmae input fifo.
46927 … (0x1<<11) // Overflow in hc input fifo.
46929 … (0x1<<12) // Overflow in msdm write input fif…
46931 … (0x1<<13) // Overflow in ysdm write input fif…
46933 … (0x1<<14) // Overflow in psdm write input fif…
46935 … (0x1<<15) // Overflow in M2P input fifo.
46937 … (0x1<<16) // Overflow in PRM Secondary input …
46939 …E5 (0x1<<17) // Overflow in RGSRC input fifo.
46941 …E5 (0x1<<18) // Overflow in TGSRC input fifo.
46946 … 0x29b040UL //Access:RW DataWidth:0x6 // If Number of entries in the cdu internal fif…
46947 … 0x29b044UL //Access:RW DataWidth:0x9 // If Number of entries in the usdmdp internal …
46948 …- client ID. [7:5] - (sum1[5:3] + 1) or (sum1[5:4] + 1) according to the definition in the spec. […
46950 … 0x29b050UL //Access:R DataWidth:0x8 // Current internal PRM fill level in 64B lines.
46951 …9b054UL //Access:R DataWidth:0x8 // Maximum internal PRM fill level since reset in 64B lines.
46952 … 0x29b058UL //Access:R DataWidth:0x6 // Current internal CDU fill level in 64B lines.
46953 …9b05cUL //Access:R DataWidth:0x6 // Maximum internal CDU fill level since reset in 64B lines.
46954 … 0x29b060UL //Access:RW DataWidth:0x7 // If Number of entries in the PRM error fifo i…
46956 … 0x29b068UL //Access:RW DataWidth:0x7 // If Number of entries in the PRM-secondary intern…
46957 …x29b06cUL //Access:R DataWidth:0x7 // Current internal PRM-secondary fill level in 64B lines.
46958 …0UL //Access:R DataWidth:0x7 // Maximum internal PRM-secondary fill level since reset in 64B…
46962 … (0x1<<1) // Indicates that there was not 'eop' in the last read reques…
46964 … (0x1<<2) // Indicates that there was 'eop' not in the last read reques…
46966 … (0x1<<3) // Underflow in the tm fifo.
46968 … (0x1<<4) // Underflow in the qm fifo.
46970 … (0x1<<5) // Underflow in the src fifo.
46972 … (0x1<<6) // Underflow in the usdm fifo.
46974 … (0x1<<7) // Underflow in the tsdm fifo.
46976 … (0x1<<8) // Underflow in the xsdm fifo.
46978 … (0x1<<9) // Underflow in the usdmdp fifo.
46980 … (0x1<<10) // Underflow in the cdu fifo.
46982 … (0x1<<11) // Underflow in the dbg fifo.
46984 … (0x1<<12) // Underflow in the dmae fifo.
46986 … (0x1<<13) // Underflow in the hc fifo.
46988 … (0x1<<14) // Underflow in the msdm fifo.
46990 … (0x1<<15) // Underflow in the ysdm fifo.
46992 … (0x1<<16) // Underflow in the psdm fifo.
46994 … (0x1<<17) // Underflow in the M2P fifo.
46996 …icates that there was 'eop' in the last read request from the glue block; but the number of valid …
46998 … (0x1<<19) // Underflow in the PRM Secondary fi…
47000 … (0x1<<20) // Underflow in the RGSRC fifo.
47002 … (0x1<<21) // Underflow in the TGSRC fifo.
47052 … (0x1<<1) // Indicates that there was not 'eop' in the last read reques…
47054 … (0x1<<2) // Indicates that there was 'eop' not in the last read reques…
47056 … (0x1<<3) // Underflow in the tm fifo.
47058 … (0x1<<4) // Underflow in the qm fifo.
47060 … (0x1<<5) // Underflow in the src fifo.
47062 … (0x1<<6) // Underflow in the usdm fifo.
47064 … (0x1<<7) // Underflow in the tsdm fifo.
47066 … (0x1<<8) // Underflow in the xsdm fifo.
47068 … (0x1<<9) // Underflow in the usdmdp fifo.
47070 … (0x1<<10) // Underflow in the cdu fifo.
47072 … (0x1<<11) // Underflow in the dbg fifo.
47074 … (0x1<<12) // Underflow in the dmae fifo.
47076 … (0x1<<13) // Underflow in the hc fifo.
47078 … (0x1<<14) // Underflow in the msdm fifo.
47080 … (0x1<<15) // Underflow in the ysdm fifo.
47082 … (0x1<<16) // Underflow in the psdm fifo.
47084 … (0x1<<17) // Underflow in the M2P fifo.
47086 …icates that there was 'eop' in the last read request from the glue block; but the number of valid …
47088 … (0x1<<19) // Underflow in the PRM Secondary fi…
47090 … (0x1<<20) // Underflow in the RGSRC fifo.
47092 … (0x1<<21) // Underflow in the TGSRC fifo.
47097 … (0x1<<1) // Indicates that there was not 'eop' in the last read reques…
47099 … (0x1<<2) // Indicates that there was 'eop' not in the last read reques…
47101 … (0x1<<3) // Underflow in the tm fifo.
47103 … (0x1<<4) // Underflow in the qm fifo.
47105 … (0x1<<5) // Underflow in the src fifo.
47107 … (0x1<<6) // Underflow in the usdm fifo.
47109 … (0x1<<7) // Underflow in the tsdm fifo.
47111 … (0x1<<8) // Underflow in the xsdm fifo.
47113 … (0x1<<9) // Underflow in the usdmdp fifo.
47115 … (0x1<<10) // Underflow in the cdu fifo.
47117 … (0x1<<11) // Underflow in the dbg fifo.
47119 … (0x1<<12) // Underflow in the dmae fifo.
47121 … (0x1<<13) // Underflow in the hc fifo.
47123 … (0x1<<14) // Underflow in the msdm fifo.
47125 … (0x1<<15) // Underflow in the ysdm fifo.
47127 … (0x1<<16) // Underflow in the psdm fifo.
47129 … (0x1<<17) // Underflow in the M2P fifo.
47131 …icates that there was 'eop' in the last read request from the glue block; but the number of valid …
47133 … (0x1<<19) // Underflow in the PRM Secondary fi…
47135 … (0x1<<20) // Underflow in the RGSRC fifo.
47137 … (0x1<<21) // Underflow in the TGSRC fifo.
47650 … (0x1<<0) // Enable ECC for memory ecc instance pswwr.i_prm_fifo.i_ecc in module pswwr_mem_prm…
47652 … (0x1<<1) // Enable ECC for memory ecc instance pswwr.i_prms_fifo.i_ecc in module pswwr_mem_prm…
47654 … (0x1<<0) // Enable ECC for memory ecc instance pswwr.i_prm_fifo.i_ecc in module pswwr_mem_prm…
47658 …(0x1<<0) // Set parity only for memory ecc instance pswwr.i_prm_fifo.i_ecc in module pswwr_mem_prm…
47660 …0x1<<1) // Set parity only for memory ecc instance pswwr.i_prms_fifo.i_ecc in module pswwr_mem_prm…
47662 …(0x1<<0) // Set parity only for memory ecc instance pswwr.i_prm_fifo.i_ecc in module pswwr_mem_prm…
47666 …a correctable error occurred on memory ecc instance pswwr.i_prm_fifo.i_ecc in module pswwr_mem_prm…
47668 … correctable error occurred on memory ecc instance pswwr.i_prms_fifo.i_ecc in module pswwr_mem_prm…
47670 …a correctable error occurred on memory ecc instance pswwr.i_prm_fifo.i_ecc in module pswwr_mem_prm…
47675 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
47689 … (0x1<<1) // An error in one of the clients' …
47691 … (0x1<<2) // An error in the PBF FIFO pop int…
47703 … (0x1<<1) // An error in one of the clients' …
47705 … (0x1<<2) // An error in the PBF FIFO pop int…
47710 … (0x1<<1) // An error in one of the clients' …
47712 … (0x1<<2) // An error in the PBF FIFO pop int…
47717 …L //Access:RW DataWidth:0x1 // Driver should write 1 to this register in order to signal the …
47719 …in 3 VQs. SR ID of 0x1ff is NULL and means there is no sub request in this VQ in PSWRD. The reset …
47723 … (0xffff<<0) // Data pattern that should override the data in case of an error. Du…
47725 …in case of an error and use the error pattern. 0 indicates not to override the data. Arrowhead: Th…
47727 …in case of an error only in the last request cycle. 0 indicates to override the data from the time…
47729 …uest with error on receive side: [15:0] - Echo ID. [28:16] - sub-request length minus 1. [29] - fi…
47730 …ils of first request with error on receive side: [4:0] - VQ ID. [9:5] - client ID. [10] - valid - …
47737 …in 3 VQs. SR ID of 0x1ff is NULL and means there is no sub request in this VQ in PSWRD. The reset …
47763 …taWidth:0x5 // Debug only: If more than this Number of entries are used in the clock synchroniz…
47764 …: If less or equal than this Number of entries are used in the clock synchronization FIFO; it de-a…
47765 …taWidth:0x5 // Debug only: If more than this Number of entries are used in the CDU clock synchr…
47766 …If less or equal than this Number of entries are used in the CDU clock synchronization FIFO; it de…
47767 …taWidth:0x7 // Debug only: If more than this Number of entries are used in the PBF clock synchr…
47768 …If less or equal than this Number of entries are used in the PBF clock synchronization FIFO; it de…
47769 …taWidth:0x3 // Debug only: If more than this Number of entries are used in the PRM clock synchr…
47770 …: If less or equal than this Number of entries are used in the clock synchronization FIFO; it de-a…
47772 … 0x29d144UL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since rese…
47773 … 0x29d148UL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since rese…
47774 … 0x29d14cUL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since rese…
47775 … 0x29d150UL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since rese…
47776 …d154UL //Access:R DataWidth:0x8 // PBF maximum sync FIFO fill level since reset in 16B lines.
47779 … 0x29d160UL //Access:R DataWidth:0x8 // Per-client maximum sync FIFO fill level since rese…
47783 … (0x1<<1) // An error in the SR free list FIF…
47785 … (0x1<<2) // An error in the blocks free list…
47787 … (0x1<<3) // An error in one of the clients' …
47789 … (0x1<<4) // An error in the PBF FIFO push in…
47805 … (0x1<<1) // An error in the SR free list FIF…
47807 … (0x1<<2) // An error in the blocks free list…
47809 … (0x1<<3) // An error in one of the clients' …
47811 … (0x1<<4) // An error in the PBF FIFO push in…
47816 … (0x1<<1) // An error in the SR free list FIF…
47818 … (0x1<<2) // An error in the blocks free list…
47820 … (0x1<<3) // An error in one of the clients' …
47822 … (0x1<<4) // An error in the PBF FIFO push in…
47982 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_…
47984 … ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_…
47986 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_…
47988 … ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_…
47990 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_…
47992 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_…
47994 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_…
47996 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_…
47998 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_…
48000 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_…
48002 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_…
48004 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_…
48006 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_…
48008 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_…
48010 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_…
48012 … ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_…
48014 …wrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fi…
48016 …wrd.SYNC_FIFO_GEN_CDU_FOR[6].SYNC_FIFO_GEN_CDU_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fi…
48018 … ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_…
48020 … ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_…
48022 …wrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fi…
48025 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_…
48027 …only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_…
48029 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_…
48031 …only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_…
48033 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_…
48035 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_…
48037 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_…
48039 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_…
48041 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_…
48043 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_…
48045 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_…
48047 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_…
48049 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_…
48051 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_…
48053 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_…
48055 …only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_…
48057 …wrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fi…
48059 …wrd.SYNC_FIFO_GEN_CDU_FOR[6].SYNC_FIFO_GEN_CDU_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fi…
48061 …only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_…
48063 …only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_…
48065 …wrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fi…
48068 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_…
48070 …urred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_…
48072 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_…
48074 …urred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_…
48076 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_…
48078 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_…
48080 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_…
48082 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_…
48084 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_…
48086 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_…
48088 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_…
48090 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_…
48092 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_…
48094 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_…
48096 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_…
48098 …urred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_…
48100 …wrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fi…
48102 …wrd.SYNC_FIFO_GEN_CDU_FOR[6].SYNC_FIFO_GEN_CDU_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fi…
48104 …urred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_…
48106 …urred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_…
48108 …wrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fi…
48112 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
48121 …:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must be big…
48122 …cess:RW DataWidth:0xa // Debug only: Total number of available blocks in Tetris Buffer. Must …
48123 …ame as PSWRQ_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core.
48124 …in the Tetris buffer. 0 - The delivery port continues delivering the next PBF request only if the …
48126 …lient; this register determines the number of additional requests to serve in this port without do…
48127 …lient; this register determines the number of additional requests to serve in this port without do…
48128 …lient; this register determines the number of additional requests to serve in this port without do…
48129 …lient; this register determines the number of additional requests to serve in this port without do…
48130 …lient; this register determines the number of additional requests to serve in this port without do…
48131 …lient; this register determines the number of additional requests to serve in this port without do…
48132 …lient; this register determines the number of additional requests to serve in this port without do…
48133 …lient; this register determines the number of additional requests to serve in this port without do…
48134 …lient; this register determines the number of additional requests to serve in this port without do…
48135 …lient; this register determines the number of additional requests to serve in this port without do…
48136 …lient; this register determines the number of additional requests to serve in this port without do…
48137 …lient; this register determines the number of additional requests to serve in this port without do…
48138 …lient; this register determines the number of additional requests to serve in this port without do…
48139 …lient; this register determines the number of additional requests to serve in this port without do…
48140 …lient; this register determines the number of additional requests to serve in this port without do…
48141 …lient; this register determines the number of additional requests to serve in this port without do…
48142 …0x29e040UL //Access:R DataWidth:0x7 // Debug only: Number of used entries in the header FIFO.
48143 … 0x29e044UL //Access:R DataWidth:0x7 // Debug only: Number of used entries in the data FIFO.
48144 …s:R DataWidth:0x7 // Debug only: Maximum number of entries that were used in the header FIFO.
48145 …ess:R DataWidth:0x7 // Debug only: Maximum number of entries that were used in the data FIFO.
48146 …dth:0x4 // Debug only: If more than this Number of entries are occupied in the dbgsyn clock syn…
48149 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
48160 … (0x1<<1) // An error in the header clock syn…
48162 … (0x1<<2) // An error in the data clock sync …
48164 … (0x1<<3) // An error in the completion clock…
48166 … (0x1<<4) // An error in the ireq clock sync FIFO. Removed in E…
48182 … (0x1<<1) // An error in the header clock syn…
48184 … (0x1<<2) // An error in the data clock sync …
48186 … (0x1<<3) // An error in the completion clock…
48188 … (0x1<<4) // An error in the ireq clock sync FIFO. Removed in E…
48193 … (0x1<<1) // An error in the header clock syn…
48195 … (0x1<<2) // An error in the data clock sync …
48197 … (0x1<<3) // An error in the completion clock…
48199 … (0x1<<4) // An error in the ireq clock sync FIFO. Removed in E…
48212 …ter-engine indicating if the engine is idle. Idle means the engine is not sending request (and the…
48213 …- pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 P…
48214 … 0x2a0060UL //Access:R DataWidth:0x1 // 1 - An error request is …
48216 …- RSV [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM…
48217 …0x7 // The data of the first incorrect access. the format is: [6:0] - length in DWs. The data i…
48218 … 0x2a0070UL //Access:R DataWidth:0x1 // 1 - An incorrect access …
48220 … 0x2a0078UL //Access:R DataWidth:0x1 // 1- permission violation…
48222 …a0080UL //Access:RW DataWidth:0x2 // Number of credits for source SDM in internal write inter…
48223 …a0084UL //Access:RW DataWidth:0x2 // Number of credits for source SDM in internal write inter…
48224 …a0088UL //Access:RW DataWidth:0x3 // Number of credits for source SDM in internal write inter…
48225 …L //Access:R DataWidth:0x13 // Number of available credits for source in internal write inter…
48226 …te source that consumed more than its allowed credits. the format is: [3:0] - client (0 TSDM; 1 MS…
48227 … 0x2a0094UL //Access:R DataWidth:0x1 // 1 - A source credit viol…
48228 …UL //Access:RW DataWidth:0x2 // Number of credits for destination SDM in target write interfa…
48229 …UL //Access:RW DataWidth:0x2 // Number of credits for destination IGU in target write interfa…
48230 …UL //Access:RW DataWidth:0x2 // Number of credits for destination CAU in target write interfa…
48231 …ccess:R DataWidth:0x12 // Number of available credits for destination in internal write inter…
48233 … 0x2a00acUL //Access:R DataWidth:0x1 // 1 - PSWHST is in drain mode.
48235 …- length in DWs; [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - cli…
48236 … 0x2a00b8UL //Access:R DataWidth:0x1 // 1 - An hst timeout data …
48238 …of credits for source USDM in internal write interface. PSWHST issues an attention if more credits…
48239 …L //Access:RW DataWidth:0x2 // Number of credits for destination DORQ in target write interfa…
48240 … When 1; host requests have strict priority on internal write requests; as in A0. When 0; arbiter …
48241 …/ Maximum write transaction data in DWs that is sent to SDMs and IGU. Write requests with bigger l…
48254 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
48267 … (0x1<<1) // An error in write source FIFO 1.
48269 … (0x1<<2) // An error in write source FIFO 2.
48271 … (0x1<<3) // An error in write source FIFO 3.
48273 … (0x1<<4) // An error in write source FIFO 4.
48275 … (0x1<<5) // An error in write source FIFO 5.
48277 … (0x1<<6) // An error in header clock sync FI…
48279 … (0x1<<7) // An error in data clock sync FIFO.
48281 … (0x1<<8) // An error in completion clock syn…
48285 …<<10) // Indicates Zone permission violation. The relevant data is stored in hst_per_violation_da…
48287 …y of the clients with incorrect length and alignement. Details are logged in incorrect access reg…
48289 … (0x1<<12) // An error in write source FIFO 6.
48291 … (0x1<<13) // An error in write source FIFO 7.
48293 … (0x1<<14) // An error in write source FIFO 8.
48295 … (0x1<<15) // An error in write source FIFO 9 …
48297 …es an internal write source credit violation. The relevant data is stored in hst_source_credit_vi…
48341 … (0x1<<1) // An error in write source FIFO 1.
48343 … (0x1<<2) // An error in write source FIFO 2.
48345 … (0x1<<3) // An error in write source FIFO 3.
48347 … (0x1<<4) // An error in write source FIFO 4.
48349 … (0x1<<5) // An error in write source FIFO 5.
48351 … (0x1<<6) // An error in header clock sync FI…
48353 … (0x1<<7) // An error in data clock sync FIFO.
48355 … (0x1<<8) // An error in completion clock syn…
48359 …<<10) // Indicates Zone permission violation. The relevant data is stored in hst_per_violation_da…
48361 …y of the clients with incorrect length and alignement. Details are logged in incorrect access reg…
48363 … (0x1<<12) // An error in write source FIFO 6.
48365 … (0x1<<13) // An error in write source FIFO 7.
48367 … (0x1<<14) // An error in write source FIFO 8.
48369 … (0x1<<15) // An error in write source FIFO 9 …
48371 …es an internal write source credit violation. The relevant data is stored in hst_source_credit_vi…
48378 … (0x1<<1) // An error in write source FIFO 1.
48380 … (0x1<<2) // An error in write source FIFO 2.
48382 … (0x1<<3) // An error in write source FIFO 3.
48384 … (0x1<<4) // An error in write source FIFO 4.
48386 … (0x1<<5) // An error in write source FIFO 5.
48388 … (0x1<<6) // An error in header clock sync FI…
48390 … (0x1<<7) // An error in data clock sync FIFO.
48392 … (0x1<<8) // An error in completion clock syn…
48396 …<<10) // Indicates Zone permission violation. The relevant data is stored in hst_per_violation_da…
48398 …y of the clients with incorrect length and alignement. Details are logged in incorrect access reg…
48400 … (0x1<<12) // An error in write source FIFO 6.
48402 … (0x1<<13) // An error in write source FIFO 7.
48404 … (0x1<<14) // An error in write source FIFO 8.
48406 … (0x1<<15) // An error in write source FIFO 9 …
48408 …es an internal write source credit violation. The relevant data is stored in hst_source_credit_vi…
48451 …und interrupts memory. E4 entry structure: [15:0] - CompParams. [23:16] - EventID. [24] - T. [28:2…
48461 … the PGLUE block to start calculating the start address of each SDM zone A in VF BAR according to …
48462 …//Access:R DataWidth:0x2 // Calculation of SDMs zone A start address in VF BAR is done. Dri…
48470 …QW aligned; window is GRC and length is more than 1 DW. Details are stored in vf_length_violation_…
48472 …on permission; RW permission; address range permission. Details are stored in vf_grc_space_violati…
48476 …<<6) // Indicates ATS Translation Completion received in two rcbs (packets). Details are stored in…
48478 … (0x1<<7) // Indicates an overflow in CSSNOOP sync fifo.
48488 … range function. Relevant when number of PFs or VFs is not a power of two. In E4, it indicates VFI…
48490 … an illegal address event - address smaller than minimal_address_log or bigger than maximal_addres…
48508 …T error indication from PSWRQ. The request was dropped. Details are stored in vf_ilt_err_add and v…
48568 …QW aligned; window is GRC and length is more than 1 DW. Details are stored in vf_length_violation_…
48570 …on permission; RW permission; address range permission. Details are stored in vf_grc_space_violati…
48574 …<<6) // Indicates ATS Translation Completion received in two rcbs (packets). Details are stored in…
48576 … (0x1<<7) // Indicates an overflow in CSSNOOP sync fifo.
48586 … range function. Relevant when number of PFs or VFs is not a power of two. In E4, it indicates VFI…
48588 … an illegal address event - address smaller than minimal_address_log or bigger than maximal_addres…
48606 …T error indication from PSWRQ. The request was dropped. Details are stored in vf_ilt_err_add and v…
48617 …QW aligned; window is GRC and length is more than 1 DW. Details are stored in vf_length_violation_…
48619 …on permission; RW permission; address range permission. Details are stored in vf_grc_space_violati…
48623 …<<6) // Indicates ATS Translation Completion received in two rcbs (packets). Details are stored in…
48625 … (0x1<<7) // Indicates an overflow in CSSNOOP sync fifo.
48635 … range function. Relevant when number of PFs or VFs is not a power of two. In E4, it indicates VFI…
48637 … an illegal address event - address smaller than minimal_address_log or bigger than maximal_addres…
48655 …T error indication from PSWRQ. The request was dropped. Details are stored in vf_ilt_err_add and v…
48775 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
48783 …- for Atomic Op / MRD handling of NPH credits. 0 - Can send both if there is one NPH credit and th…
48785 …dth:0x4 // Debug only: If more than this Number of entries are occupied in the dbgsyn clock syn…
48787 … (0x1<<0) // 0 - Debug bus is not output to RBCN_e0. 1 - …
48789 … (0x1<<1) // 0 - Debug bus is not output to RBCN_e1. 1 - …
48804 … (0x1<<8) // This bit forces a parity error in the replay buffer.
48806 … (0x1<<9) // This bit give strict priority to read over write on the PGL read-write arbiter.
48809 …uest was blocked because of bus_master_en was deasserted. Bit 1: Added in BigBear-B0. Indicates th…
48810 …uest was blocked because of bus_master_en was deasserted. Bit 1: Added in BigBear-B0. Indicates th…
48811 … 0x2a8488UL //Access:R DataWidth:0x4 // Debug only: Occupancy level in PGLUE master read FI…
48812 …8cUL //Access:R DataWidth:0x5 // Debug only: Maximal occupancy level in PGLUE master write F…
48813 …90UL //Access:R DataWidth:0x4 // Debug only: Maximal occupancy level in PGLUE master read FI…
48814 … 0x2a8494UL //Access:R DataWidth:0x5 // Debug only: Write pointer in PGLUE master write F…
48815 …2a8498UL //Access:R DataWidth:0x5 // Debug only: Driver read pointer in PGLUE master write F…
48816 …2a849cUL //Access:R DataWidth:0x5 // Debug only: Filler read pointer in PGLUE master write F…
48817 … 0x2a84a0UL //Access:R DataWidth:0x4 // Debug only: Write pointer in PGLUE master read FI…
48818 …2a84a4UL //Access:R DataWidth:0x4 // Debug only: Driver read pointer in PGLUE master read FI…
48820 …in user RX interface since last reset. Note that such errors are legitimate. Bit 0 - Target memory…
48821 …dth:0x4 // Debug only: If more than this Number of entries are occupied in the PCIe dbgsyn cloc…
48822 …lock synchronization FIFO is disabled and pcie_top_wrapper should output 0 in frame, valid and dat…
48834 …cUL //Access:R DataWidth:0x1 // Indicates there was an error in PCIe checksum in data from P…
48835 …ebug only: 0 - PCIe checksum is generated towards PCIe core. 1 - PCIe checksum is not generated to…
48839 …:0x5 // Pseudo VF target mode configuration that controls the size of each pseudo-VF in the BAR.
48841 … to accesss DORQ via BAR0: 0-disable access; 1-enable access if BAR0 size is 128K; 2-enable acces…
48842 …L //Access:RW DataWidth:0x9 // VSC fields: bit 0 - enable VSC; bits 1-8 - VSC reserved bits i…
48852 …dth:0x2 // Debug only: If more than this Number of entries are occupied in the cssnoop clock sy…
48853 …in the TXW header clock synchronization FIFO; it does not enable writing to the fifo. This value i…
48854 …dth:0x5 // Debug only: If more than this Number of entries are occupied in the TXW data clock s…
48855 …dth:0x5 // Debug only: If more than this Number of entries are occupied in the TXR header clock…
48858 …-PF region. Addresses 0x0 - 0x5c: 12 per-PF PF windows. Each PF window contains two 32-bit values.…
48860 …region. 0x0 - 0x3c8 (0x200 - 0x5c8) - 243 global windows. Each entry is the 12-bit window offset.…
48862 …ress[12:7] in PCI configuration space of the first register on which config space A attention is g…
48863 …ates which of the 32 registers starting in address cfg_space_a_address generates an attention. If …
48864 …ress[12:7] in PCI configuration space of the first register on which config space B attention is g…
48865 …ates which of the 32 registers starting in address cfg_space_b_address generates an attention. If …
48867 …in this register in order to clear the corresponding bit in cfg_space_a_request register. Note: re…
48869 …in this register in order to clear the corresponding bit in cfg_space_b_request register. Note: re…
48879 …s clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the correspondin…
48880 … clear for VFs 32 to 63. MCP writes 1 to a bit in this register in order to clear the correspondin…
48881 … clear for VFs 64 to 95. MCP writes 1 to a bit in this register in order to clear the correspondin…
48882 …clear for VFs 96 to 127. MCP writes 1 to a bit in this register in order to clear the correspondin…
48883 …lear for VFs 128 to 159. MCP writes 1 to a bit in this register in order to clear the correspondin…
48884 …lear for VFs 160 to 191. MCP writes 1 to a bit in this register in order to clear the correspondin…
48885 …lear for VFs 192 to 223. MCP writes 1 to a bit in this register in order to clear the correspondin…
48886 …lear for VFs 224 to 255. MCP writes 1 to a bit in this register in order to clear the correspondin…
48887 …bits clear for all PFs. MCP writes 1 to a bit in this register in order to clear the correspondin…
48891 …ABLED_REQUEST (0x1<<1) // Debug only: When 1 SR-IOV disbaled request …
48894 …ention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the correspondin…
48904 …in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_…
48905 …in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_…
48906 …in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_…
48907 …in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_…
48908 …in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_…
48909 …in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_…
48910 …in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_…
48911 …in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_…
48912 …- Shadow bits clear for PFs 0 to 31. MCP writes 1 to a bit in this register in order to reset the…
48922 …th:0x10 // Shadow vf_enable register for all PFs. Each bit indicates if SR-IOV for the correspon…
48926 …in user RX interface. Bit 0 - Reserved. Bit 1 - Reserved. Bit 2 - Reserved. Bit 3 - Reserved. Bit …
48936 …s clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the correspondin…
48937 … clear for VFs 32 to 63. MCP writes 1 to a bit in this register in order to clear the correspondin…
48938 … clear for VFs 64 to 95. MCP writes 1 to a bit in this register in order to clear the correspondin…
48939 …clear for VFs 96 to 127. MCP writes 1 to a bit in this register in order to clear the correspondin…
48940 …lear for VFs 128 to 159. MCP writes 1 to a bit in this register in order to clear the correspondin…
48941 …lear for VFs 160 to 191. MCP writes 1 to a bit in this register in order to clear the correspondin…
48942 …lear for VFs 192 to 223. MCP writes 1 to a bit in this register in order to clear the correspondin…
48943 …lear for VFs 224 to 255. MCP writes 1 to a bit in this register in order to clear the correspondin…
48944 …s clear for PFs 0 to 7. MCP writes 1 to a bit in this register in order to clear the correspondin…
48945 …- PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of …
48946 …- PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of …
48949 …ot submitted due to error. [4:0] VQID. [17:5] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. …
48950 …- Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indica…
48953 …QID. [5] TREQ. 1 - Indicates the request is a Translation Request. [18:6] - Length in bytes. [19] …
48954 …- Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indica…
48955 …- PFID. [11:4] - VFID. [12] - VF_VALID. [17:13] - ITAG Index. [21:18] - Error type - [18] - Indic…
48956 …68UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-VF for master and tar…
48957 …6cUL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for master transac…
48958 …70UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target write t…
48959 …74UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target read tr…
48968 …pfid_enable registers for target flow. Bits [15:0] - internal_pfid_enable_target_write; Bits [31:1…
48969 … global view of internal_pfid_enable registers for master flow. Bits [15:0] - internal_pfid_enable…
48970 …0UL //Access:RW DataWidth:0x13 // Start offset of TSDM zone A (queue zone) in the internal RAM.
48971 …a4UL //Access:RW DataWidth:0x5 // Offset mask of TSDM zone A (queue zone) in the internal RAM.
48972 …UL //Access:RW DataWidth:0x13 // Start offset of TSDM zone B (legacy zone) in the internal RAM.
48973 …cUL //Access:RW DataWidth:0x9 // Offset mask of TSDM zone B (legacy zone) in the internal RAM.
48974 …a1b0UL //Access:RW DataWidth:0x5 // VF Shift of TSDM zone B (legacy zone) in the internal RAM.
48975 …4UL //Access:RW DataWidth:0x13 // Start offset of msdm zone A (queue zone) in the internal RAM.
48976 …b8UL //Access:RW DataWidth:0x5 // Offset mask of msdm zone A (queue zone) in the internal RAM.
48977 …UL //Access:RW DataWidth:0x13 // Start offset of msdm zone B (legacy zone) in the internal RAM.
48978 …0UL //Access:RW DataWidth:0x9 // Offset mask of msdm zone B (legacy zone) in the internal RAM.
48979 …a1c4UL //Access:RW DataWidth:0x5 // VF Shift of msdm zone B (legacy zone) in the internal RAM.
48980 …8UL //Access:RW DataWidth:0x13 // Start offset of USDM zone A (queue zone) in the internal RAM.
48981 …ccUL //Access:RW DataWidth:0x5 // Offset mask of USDM zone A (queue zone) in the internal RAM.
48982 …UL //Access:RW DataWidth:0x13 // Start offset of USDM zone B (legacy zone) in the internal RAM.
48983 …4UL //Access:RW DataWidth:0x9 // Offset mask of USDM zone B (legacy zone) in the internal RAM.
48984 …a1d8UL //Access:RW DataWidth:0x5 // VF Shift of USDM zone B (legacy zone) in the internal RAM.
48985 …cUL //Access:RW DataWidth:0x13 // Start offset of XSDM zone A (queue zone) in the internal RAM.
48986 …e0UL //Access:RW DataWidth:0x5 // Offset mask of XSDM zone A (queue zone) in the internal RAM.
48987 …UL //Access:RW DataWidth:0x13 // Start offset of XSDM zone B (legacy zone) in the internal RAM.
48988 …8UL //Access:RW DataWidth:0x9 // Offset mask of XSDM zone B (legacy zone) in the internal RAM.
48989 …a1ecUL //Access:RW DataWidth:0x5 // VF Shift of XSDM zone B (legacy zone) in the internal RAM.
48990 …0UL //Access:RW DataWidth:0x13 // Start offset of ysdm zone A (queue zone) in the internal RAM.
48991 …f4UL //Access:RW DataWidth:0x5 // Offset mask of ysdm zone A (queue zone) in the internal RAM.
48992 …UL //Access:RW DataWidth:0x13 // Start offset of ysdm zone B (legacy zone) in the internal RAM.
48993 …cUL //Access:RW DataWidth:0x9 // Offset mask of ysdm zone B (legacy zone) in the internal RAM.
48994 …a200UL //Access:RW DataWidth:0x5 // VF Shift of ysdm zone B (legacy zone) in the internal RAM.
48995 …4UL //Access:RW DataWidth:0x13 // Start offset of psdm zone A (queue zone) in the internal RAM.
48996 …08UL //Access:RW DataWidth:0x5 // Offset mask of psdm zone A (queue zone) in the internal RAM.
48997 …UL //Access:RW DataWidth:0x13 // Start offset of psdm zone B (legacy zone) in the internal RAM.
48998 …0UL //Access:RW DataWidth:0x9 // Offset mask of psdm zone B (legacy zone) in the internal RAM.
48999 …a214UL //Access:RW DataWidth:0x5 // VF Shift of psdm zone B (legacy zone) in the internal RAM.
49000 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49001 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49002 …B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start addr…
49003 …B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start addr…
49004 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49005 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49006 …B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start addr…
49007 …B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start addr…
49008 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49009 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49010 …B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start addr…
49011 …B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start addr…
49012 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49013 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49014 …B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start addr…
49015 …B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start addr…
49016 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49017 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49018 …B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start addr…
49019 …B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start addr…
49020 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49021 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49022 …B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start addr…
49023 …B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start addr…
49024 … 0x2aa318UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49025 … 0x2aa31cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49026 … 0x2aa320UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49027 … 0x2aa324UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49028 … 0x2aa328UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49029 … 0x2aa32cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49030 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49031 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49032 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49033 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49034 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49035 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49036 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49037 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49038 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49039 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49040 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49041 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49042 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49043 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49044 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49045 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49046 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49047 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49048 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49049 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49050 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49051 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49052 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49053 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49054 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49055 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49056 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49057 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49058 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49059 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49060 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49061 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49062 …ny DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address). [14:13] BAR. [22:15] …
49063 …st with length violation (too many DWs) accessing BAR0. [5:0] - Length in DWs. [6] valid - indica…
49064 …ermission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. [23:16] VFID. [27:24] - PFID. [28…
49065 …in this register clears a corresponding error details register and enables logging new error detai…
49067 … 0x2aa3c4UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates t…
49068 … 0x2aa3c8UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates t…
49069 … 0x2aa3ccUL //Access:RW DataWidth:0x1 // 1 - Do not discard IGU m…
49070 …- Accesses to the first 8KB of IGU in BAR0 (MSIX table and PBA) are not allowed. When this value i…
49071 …in two rcbs (packets). Logging is triggered by a Translation Completion with length different than…
49072 …in pxp2 is set. 0 - Unsupported Request or Completer Abort on User RX Interface. 1 - Reception of …
49073 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49074 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49075 …- Enable the fix for CQ45220. If a Function receives a Translation Completion with a Translation S…
49076 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49077 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49079 …e to this PCIE address will cause a GRC write access to the address that's in t this register. E4:…
49080 …e to this PCIE address will cause a GRC write access to the address that's in t this register. E4:…
49081 …e to this PCIE address will cause a GRC write access to the address that's in t this register. E4:…
49082 …e to this PCIE address will cause a GRC write access to the address that's in t this register. E4:…
49083 … DataWidth:0x19 // The address to be read from expansion rom (address is in bytes according to r…
49085 … 0x2aa41cUL //Access:R DataWidth:0x2 // The size in dwords to be read fr…
49094 …In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of …
49096 …In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of …
49098 …In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of …
49100 …In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of …
49102 …In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of …
49104 …In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of …
49106 …In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of …
49108 …In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of …
49110 …in this read-only register reflects the value of the corresponding 'PF trusted' config bit on the …
49113 …. 1 - Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFI…
49114 …- PGLUE will submit the request with TPH info. PXP will take care of aligning it correctly when se…
49115 …9:0] Address in DWs (bits [11:2] of byte address). [13:10] BE first. [17:14] BE last. [21:18] - PF…
49116 …- original PFID. [7:4] Pretend PFID. [15:8] Pretend VFID. [16] Pretend vf_valid. [20:17] Pretend r…
49118 …2aa560UL //Access:RW DataWidth:0x1 // 0 - Work with external BAR0 mechanism as defined in E4 …
49125 …annel enable configuration per-VF. Controls Target read/write access to specific locations in Zon…
49126 …led for that SDM. One bit per SDM. Bit 0 - TSDM. Bit 1 - MSDM. Bit 2 - USDM. Bit 3 - XSDM. Bit 4 -…
49127 …3 // Window size for VF to PF channel. 0 - NA; 1 - 8B; 2 - 16B; 3 - 32B; 4 - 64B; 5 - 128B; 6 -…
49128 …aWidth:0x6 // Defines the start offset of the VF to PF window within VF ZoneB in 8B granularity.
49130 … (0x1<<0) // Decision bit for PF master requests when BME is cleared: 0 - block; 1 - discard.
49132 …(0x1<<1) // Decision bit for PF master requests when fid_enable is cleared: 0 - block; 1 - discard.
49134 … (0x1<<2) // Decision bit for PF master requests when was_error is set: 0 - block; 1 - discard.
49136 … (0x1<<3) // Decision bit for VF master requests when BME is cleared: 0 - block; 1 - discard.
49138 …(0x1<<4) // Decision bit for VF master requests when fid_enable is cleared: 0 - block; 1 - discard.
49140 … (0x1<<5) // Decision bit for VF master requests when was_error is set: 0 - block; 1 - discard.
49143 …s cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and…
49145 …s cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and…
49147 …or is set: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and…
49149 …s cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and…
49151 …s cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and…
49153 …or is set: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and…
49155 …ill not generate an attention. This bit will allow SW to extend the period in which attention is m…
49156 …ill not generate an attention. This bit will allow SW to extend the period in which attention is m…
49157 …des the content of the corresponding entry in PGLUE master write FIFO. The structure of every entr…
49159 …des the content of the corresponding entry in PGLUE master read FIFO. The structure of every entry…
49161 … 0x2aae00UL //Access:R DataWidth:0x5 // Debug only: Occupancy level in PGLUE master write F…
49162 … // A value of '1' instructs PGLUE to use the client ID value in the 'tag' field of non-TPH maste…
49163 …eld is an enable bit for 'detection of out-of-range requests' debug feature. It should be initiali…
49165 … is (the log of ) the minimal legal address value. It is used in the 'detection of out-of-range re…
49167 … is (the log of ) the maximal legal address value. It is used in the 'detection of out-of-range re…
49171 …th illegal address. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49172 …- address was smaller than minimal_address_log; 1 - address was bigger than maximal_address_log. …
49175 …th TPH information. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49176 …nt ID. [6:5] PH. [14:7] Steering Tag. [15] - write_n_read: 0 - read; 1 - write. [16] - last SR. […
49177 …x1 // 0 - never pad write sub-requests with zeros. 1 - Pad write sub-requests with zeros and al…
49178 …/Access:RW DataWidth:0x3 // Cache line size for padding. 0 - 32B. 1 - 64B. 2 - 128B. 3 - 256B.
49179 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49180 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49181 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49182 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49183 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49184 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49185 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49186 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49189 …ming. The driver should read BAR1_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_CONFI…
49190 …in PCIE_REG_PCIER_REG_BAR2_CONFIG) and configure to this register. Decoding: 0 disabled; 1 64K; 2 …
49191 …he driver should read BAR2_SIZE_OF_VF from PCIe IP config space (bits 11:8 in PCIE_REG_PCIER_REG_V…
49192 …ue to bus number change detected by PCIe IP. MCP writes 1 to this register in order to clear the l…
49196 …t error indication. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49197 …[15:0] Request ID. [20:16] client ID. [21] - write_n_read: 0 - read; 1 - write. [22] - last SR. […
49199 … for engine 1. Set by PXP. Reset by MCP writing 1 to the corresponding bit in expansion_rom_attn_c…
49200 … and bit 1 for engine 1. MCP writes 1 to a bit in this register in order to clear the correspondin…
49201 …S attention dirty bit. Set by PXP. Reset by MCP writing 1 to the corresponding bit in mps_attn_clr.
49202 …tention dirty bit clear. MCP writes 1 to a bit in this register in order to clear the correspondin…
49204 …ister controls the path_in_d3 output to CPMU. Each bit corresponds to a PF in the path. A value of…
49210 …he driver should read BAR2_SIZE_OF_VF from PCIe IP config space (bits 11:8 in PCIE_REG_PCIER_REG_V…
49211 …The driver should read ROM_SIZE_OF_PF from PCIe IP config space (bits 11:8 in PCIE_REG_PCIER_REG_V…
49229 … 0x2aaf00UL //Access:R DataWidth:0x20 // Indicates there was an error in DBI Dbi_error_attn …
49233 … 0x2aaf10UL //Access:R DataWidth:0x10 // pm_dstate 47-032
49235 … 0x2aaf60UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 31-0
49236 … 0x2aaf64UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 63 -32
49237 … 0x2aaf68UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 95 - 64
49238 … 0x2aaf6cUL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 127 - 96
49239 … 0x2aaf70UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 159-128
49240 … 0x2aaf74UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 191 to 1…
49241 … 0x2aaf78UL //Access:R DataWidth:0x10 // FLR Invalidate in progress pf 31 to 0
49243 …h:0x20 // Indicates there was an error in MCTP BIt 21-30 Message code Bit 7-22 Vender ID Bit 3-…
49244 … DataWidth:0x20 // Indicates there was an error in MCTP Bit 21-30 Length Bit 5-20 PCIE REQ ID B…
49248 … 0x2aaf94UL //Access:RW DataWidth:0x1 // Disable vendorid check in MCTP
49249 …e to this PCIE address will cause a GRC write access to the address that's in t this register. E4:…
49250 …e to this PCIE address will cause a GRC write access to the address that's in t this register. E4:…
49251 …e to this PCIE address will cause a GRC write access to the address that's in t this register. E4:…
49252 …e to this PCIE address will cause a GRC write access to the address that's in t this register. E4:…
49256 …0x2aafb4UL //Access:RW DataWidth:0x1 // 0 - Don't discard target request with unknown header …
49257 …th:0x1 // 0 - Don't compare the function received in the completion to the original MRD functio…
49258 …ess:RW DataWidth:0x1 // 0 - Enable b2b pop from sync fifos in pgl_pci_core_rx. 1 - Disable b2…
49259 … 0x2aafc0UL //Access:RW DataWidth:0x1 // 0 - Don't discard master request during FLR 1 …
49260 … DataWidth:0x4 // 0 - TXCPL sync fifo push overflow 1 - TXR sync fifo push overflow 2 - TXW hea…
49261 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo pop underflow 1 - RX header syn…
49262 …x2aafccUL //Access:R DataWidth:0x12 // 8:0 - RX target read and config sync fifo pop status …
49273 …Width:0x1 // When set, the self init for the context memory is done. TBD - need to change to re…
49282 … 0x2c0028UL //Access:RW DataWidth:0x1 // When set init the CLIENT IN PBF FIFO.
49283 … 0x2c002cUL //Access:RW DataWidth:0x1 // When set init the CLIENT IN XCM FIFO.
49284 … 0x2c0030UL //Access:RW DataWidth:0x1 // When set init the CLIENT IN TCM FIFO.
49285 … 0x2c0034UL //Access:RW DataWidth:0x1 // When set init the CLIENT IN UCM FIFO.
49291 … 0x2c006cUL //Access:RW DataWidth:0x1 // Enable client in interfaces (XCM, UCM…
49324 … (0x1<<13) // CLIENT IN PBF FIFO Overflow.
49326 … (0x1<<14) // CLIENT IN PBF FIFO Underrun.
49328 … (0x1<<15) // CLIENT IN UCM FIFO Overflow.
49330 … (0x1<<16) // CLIENT IN UCM FIFO Underun.
49332 … (0x1<<17) // CLIENT IN TCM FIFO Overflow.
49334 … (0x1<<18) // CLIENT IN TCM FIFO Underrun.
49336 … (0x1<<19) // CLIENT IN XCM FIFO Overflow.
49338 … (0x1<<20) // CLIENT IN XCM FIFO Underrun.
49454 … (0x1<<13) // CLIENT IN PBF FIFO Overflow.
49456 … (0x1<<14) // CLIENT IN PBF FIFO Underrun.
49458 … (0x1<<15) // CLIENT IN UCM FIFO Overflow.
49460 …N (0x1<<16) // CLIENT IN UCM FIFO Underun.
49462 … (0x1<<17) // CLIENT IN TCM FIFO Overflow.
49464 … (0x1<<18) // CLIENT IN TCM FIFO Underrun.
49466 … (0x1<<19) // CLIENT IN XCM FIFO Overflow.
49468 … (0x1<<20) // CLIENT IN XCM FIFO Underrun.
49519 …V (0x1<<13) // CLIENT IN PBF FIFO Overflow.
49521 …N (0x1<<14) // CLIENT IN PBF FIFO Underrun.
49523 …V (0x1<<15) // CLIENT IN UCM FIFO Overflow.
49525 …UN (0x1<<16) // CLIENT IN UCM FIFO Underun.
49527 …V (0x1<<17) // CLIENT IN TCM FIFO Overflow.
49529 …N (0x1<<18) // CLIENT IN TCM FIFO Underrun.
49531 …V (0x1<<19) // CLIENT IN XCM FIFO Overflow.
49533 …N (0x1<<20) // CLIENT IN XCM FIFO Underrun.
49562 … (0x1<<2) // Context Read with Last indication de-asserted.
49564 … (0x1<<3) // Context Write with Last indication de-asserted.
49608 … (0x1<<2) // Context Read with Last indication de-asserted.
49610 … (0x1<<3) // Context Write with Last indication de-asserted.
49631 … (0x1<<2) // Context Read with Last indication de-asserted.
49633 … (0x1<<3) // Context Write with Last indication de-asserted.
49713 … (0x1<<0) // Enable ECC for memory ecc instance tm.i_tm_context_mem.i_ecc in module tm_context_mem
49715 …(0x1<<0) // Enable ECC for memory ecc instance tm.i_tm_context_mem.i_ecc_0 in module tm_context_mem
49717 …(0x1<<1) // Enable ECC for memory ecc instance tm.i_tm_context_mem.i_ecc_1 in module tm_context_mem
49719 …or memory ecc instance tm.TM_PRE_SCAN_2048_ROWS_IF.i_tm_pre_scan_mem.i_ecc in module tm_pre_scan_2…
49722 …1<<0) // Set parity only for memory ecc instance tm.i_tm_context_mem.i_ecc in module tm_context_mem
49724 …<0) // Set parity only for memory ecc instance tm.i_tm_context_mem.i_ecc_0 in module tm_context_mem
49726 …<1) // Set parity only for memory ecc instance tm.i_tm_context_mem.i_ecc_1 in module tm_context_mem
49728 …or memory ecc instance tm.TM_PRE_SCAN_2048_ROWS_IF.i_tm_pre_scan_mem.i_ecc in module tm_pre_scan_2…
49731 …orrectable error occurred on memory ecc instance tm.i_tm_context_mem.i_ecc in module tm_context_mem
49733 …rectable error occurred on memory ecc instance tm.i_tm_context_mem.i_ecc_0 in module tm_context_mem
49735 …rectable error occurred on memory ecc instance tm.i_tm_context_mem.i_ecc_1 in module tm_context_mem
49737 …on memory ecc instance tm.TM_PRE_SCAN_2048_ROWS_IF.i_tm_pre_scan_mem.i_ecc in module tm_pre_scan_2…
49744 …0UL //Access:RW DataWidth:0x3 // Almost full threshold for the CLIENT IN PBF FIFO, which its …
49745 …4UL //Access:RW DataWidth:0x3 // Almost full threshold for the CLIENT IN XCM FIFO, which its …
49746 …8UL //Access:RW DataWidth:0x3 // Almost full threshold for the CLIENT IN TCM FIFO, which its …
49747 …cUL //Access:RW DataWidth:0x3 // Almost full threshold for the CLIENT IN UCM FIFO, which its …
49770 …x2 // Number of timers per connection group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49771 …idth:0x2 // Number of timers per task group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49772 …- the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each gr…
49773 …- the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each gr…
49776 …g first block in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 …
49777 …ng last block in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 …
49778 …iddle blockss in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 …
49779 …eld for writes; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49780 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49781 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49782 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49783 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49784 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49785 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49786 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49787 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49788 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49789 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49790 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49791 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49792 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49793 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49809 …L //Access:R DataWidth:0x20 // Number of SET commands received on the client in PBF interface.
49810 …//Access:R DataWidth:0x20 // Number of CLEAR commands received on the client in PBF interface.
49811 …ss:R DataWidth:0x20 // Number of FORCE CLEAR commands received on the client in PBF interface.
49812 … //Access:R DataWidth:0x20 // Number of INIT commands received on the client in PBF interface.
49813 …ccess:R DataWidth:0x20 // Number of STOP ALL commands received on the client in PBF interface.
49814 …L //Access:R DataWidth:0x20 // Number of SET commands received on the client in TCM interface.
49815 …//Access:R DataWidth:0x20 // Number of CLEAR commands received on the client in TCM interface.
49816 …ss:R DataWidth:0x20 // Number of FORCE CLEAR commands received on the client in TCM interface.
49817 … //Access:R DataWidth:0x20 // Number of INIT commands received on the client in TCM interface.
49818 …ccess:R DataWidth:0x20 // Number of STOP ALL commands received on the client in TCM interface.
49819 …L //Access:R DataWidth:0x20 // Number of SET commands received on the client in UCM interface.
49820 …//Access:R DataWidth:0x20 // Number of CLEAR commands received on the client in UCM interface.
49821 …ss:R DataWidth:0x20 // Number of FORCE CLEAR commands received on the client in UCM interface.
49822 … //Access:R DataWidth:0x20 // Number of INIT commands received on the client in UCM interface.
49823 …ccess:R DataWidth:0x20 // Number of STOP ALL commands received on the client in UCM interface.
49824 …L //Access:R DataWidth:0x20 // Number of SET commands received on the client in XCM interface.
49825 …//Access:R DataWidth:0x20 // Number of CLEAR commands received on the client in XCM interface.
49826 …ss:R DataWidth:0x20 // Number of FORCE CLEAR commands received on the client in XCM interface.
49827 … //Access:R DataWidth:0x20 // Number of INIT commands received on the client in XCM interface.
49828 …ccess:R DataWidth:0x20 // Number of STOP ALL commands received on the client in XCM interface.
49847 …724UL //Access:R DataWidth:0x4 // Indicates the status of the CLIENT IN PBF FIFO, number of …
49848 …728UL //Access:R DataWidth:0x3 // Indicates the status of the CLIENT In PBF FIFO, number of …
49849 …72cUL //Access:R DataWidth:0x3 // Indicates the status of the CLIENT IN XCM FIFO, number of …
49850 …730UL //Access:R DataWidth:0x3 // Indicates the status of the CLIENT IN TCM FIFO, number of …
49851 …734UL //Access:R DataWidth:0x3 // Indicates the status of the CLIENT IN UCM FIFO, number of …
49854 …type is enabled, if the error took place, the errored command data is kept in the debug_0 register…
49855 …rror took place, only a command with error for the fid in the register debug_0_fid_mask is kept in…
49856 …, only a command with error for the fid identical to this regsiter is kept in the debug_0 register…
49857 …ook place, only a command with error from the source in the register debug_0_source_mask is kept i…
49858 …regsiter is kept in the debug_0 registers. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expir…
49859 …tes that the debug_0 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49863 …- SET TIMER, 1 - CLEAR TIMER, 2 - STOP ALL TIMERS, 3 - INIT, 4 - FORCE CLEAR TIMER, 5 - reserved,…
49866 …s:R DataWidth:0x1 // The Leader Type field for the errored command: 0 - connection, 1 - task.
49867 …r the errored command. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved,…
49870 …tes that the debug_1 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49872 …-0: LCID, Bit 9: scan type (0 - connection, 1 - task), Bits 12-10: type (3 LSbits), Bit 13: Load E…
49873 …tes that the debug_2 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49874 …last indication de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 10…
49875 …tes that the debug_3 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49876 …ion de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 11-10: Qward V…
49877 …-0: cmd_handler. Bit 3: reserved. Bits 7-4: writ…
49878 …tes that the debug_4 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49879 …-0: function # (0-239 VFs, 240 and above PFs / segments) . Bit 9: type (0 - connection, 1 - task).…
49881 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
49889 …- number of connections, the value should be multiplies of group_size_resolution_conn register (fo…
49893 …- number of tasks, the value should be multiplies of group_size_resolution_task register (for exam…
49897 …r connections, the last 512 rows contain the scan rate fields for tasks. TBD - describe the fields.
49908 … (0x1<<10) // When set link list ram will be initialized - all LCIDs will be located in the em…
49912 …TID Lock RAM to be initialized. This cannot be set during normal operation -- the block must be id…
49952 … // Enable ECC for memory ecc instance tcfc.i_cfc_core.i_lc_que_ram.i_ecc1 in module cfc_lc_que_ram
49954 … // Enable ECC for memory ecc instance tcfc.i_cfc_core.i_lc_que_ram.i_ecc2 in module cfc_lc_que_ram
49957 …et parity only for memory ecc instance tcfc.i_cfc_core.i_lc_que_ram.i_ecc1 in module cfc_lc_que_ram
49959 …et parity only for memory ecc instance tcfc.i_cfc_core.i_lc_que_ram.i_ecc2 in module cfc_lc_que_ram
49962 … error occurred on memory ecc instance tcfc.i_cfc_core.i_lc_que_ram.i_ecc1 in module cfc_lc_que_ram
49964 … error occurred on memory ecc instance tcfc.i_cfc_core.i_lc_que_ram.i_ecc2 in module cfc_lc_que_ram
49968 …L //Access:RC DataWidth:0x20 // Statistics register that counts cycles in which load context r…
49969 …in which a Primary Lock condition exists when it was caused by an Increment command on a previousl…
49970 …in which a Primary Lock condition exists when it was caused by an Lock command on a previously loc…
49981 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
49989 …ved. bit0: Chicken bit for CQ73536 fix. When '0' takes into account LCIDs in the pipe. When '1' b…
49990 …ternal error it will set one of these bits. the bit description can be found in CFC specifications.
49991 …idth:0x11 // Masking for error logging. if a bit in this field is set then the corresponding bit…
49992 … 0x2d0554UL //Access:RW DataWidth:0x11 // Indicates per error (in CFC_REGISTERS_CFC_ER…
49993 …-- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Not…
49994 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
49995 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
49996 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
49998 … (0x1<<0) // When set CFC arbiter1 will work in strict priority.
50000 … (0x1<<1) // When set load context arbiter will work in strict priority.
50002 … (0x1<<2) // When set CFC arbiter2 will work in strict priority.
50004 … (0x1<<3) // When set CFC arbiter3 will work in strict priority.
50006 … (0x1<<4) // When set activity counter decrement arbiter will work in strict priority.
50008 … (0x1<<5) // When set activity counter increment arbiter will work in strict priority.
50010 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50020 … (0xf<<10) // This register is not used in BB-B0. Reduced width t…
50048 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50049 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50050 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50051 …quest is processed do not move the LCID to Inactive state if any of the regions are in error state.
50067 … 0x2d0600UL //Access:R DataWidth:0x9 // Number of Empty LCIDs in Link List Block (not…
50068 … 0x2d0604UL //Access:R DataWidth:0x9 // Number of Inside not active LCIDs in Link List Block.
50069 … 0x2d0608UL //Access:R DataWidth:0x9 // Number of inside/outside LCIDs in Link List Block.
50070 … 0x2d060cUL //Access:R DataWidth:0x9 // Number of LCIDs in the EMPTY state.
50071 … 0x2d0610UL //Access:R DataWidth:0x9 // Number of LCIDs in the ARRIVING state.
50072 … 0x2d0614UL //Access:R DataWidth:0x9 // Number of LCIDs in the INSIDE state.
50073 … 0x2d0618UL //Access:R DataWidth:0x9 // Number of LCIDs in the INSIDE_NA state.
50074 … 0x2d061cUL //Access:R DataWidth:0x9 // Number of LCIDs in the LEAVING state.
50075 … 0x2d0620UL //Access:R DataWidth:0x9 // Number of LCIDs in the I_AND_O state.
50076 … 0x2d0624UL //Access:R DataWidth:0x9 // Number of LCIDs in the BDELETED state.
50078 …00UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a …
50079 …04UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a …
50080 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50081 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50084 …x3ff<<0) // The Threshold of EmptyLCIDs which must be in the Empty State to enable the MiniCache i…
50086 … (0x1<<10) // This field is not used in BB-B0. When set, this …
50088 … 0x2d0718UL //Access:RW DataWidth:0x1 // Enables MiniCache in Load Clients.
50096 …ad On Error. if this bit is set and there is a load request region that is in error state then a n…
50112 …L //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if les…
50113 … Array of indirect registers defines the forced load regions per type. Applicable only in the TCFC.
50120 …0x2d0804UL //Access:R DataWidth:0x9 // Reserved: This register is no longer needed in E4 B0.
50121 …0x2d0808UL //Access:R DataWidth:0x9 // Reserved: This register is no longer needed in E4 b0.
50123 …lements in empty list and in IO list is bigger than the value of this register, LC controller can …
50138 … DataWidth:0x9 // This is threshold register to disable Direct messages in the DORQ. When the n…
50139 …ill restart the Timer in each Generator. At this time, the output of the Generator will be set to …
50167 …8 // Mask vector for enabling caching on various string types. Each bit in this register matche…
50169 …will be used to cache results from the Searcher that did not match an entry in the external tables.
50173 …earches and Writes to the CID CAM. Setting a bit to 0 will ignore that bit in a search. Setting a …
50186 …:0xa // {HIT;LCID}. HIT - if set then previous CAM seach item (either CCAM or SCAM) was found. …
50187 …in E4B0. 0 - tid is not included in hash calculation (like in A0). 1 - tid is included in hash cal…
50188 …in E4B0. 0 - vlan is not included in hash calculation (like in A0). 1 - vlan is included in hash c…
50192 … 0x2d0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CI…
50196 … 0x2d0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the ST…
50207 … 0x2db000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
50211 …idth:0xc // TID Lock RAM Access Register [11] = Locked [10] = In Use [09:00] = Usag…
50224 … (0x1<<10) // When set link list ram will be initialized - all LCIDs will be located in the em…
50228 …TID Lock RAM to be initialized. This cannot be set during normal operation -- the block must be id…
50272 … // Enable ECC for memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc1 in module cfc_lc_que_ram
50274 … // Enable ECC for memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc2 in module cfc_lc_que_ram
50276 …mory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram
50278 …mory ecc instance ccfc.i_cfc_core.CFC_RFE_QUE_GEN.i_rfe_que_ctrl_ram.i_ecc in module cfc_rfe_que_r…
50280 …emory ecc instance ccfc.i_cfc_core.CFC_RFE_QUE_GEN.i_rfe_que_upd_ram.i_ecc in module cfc_rfe_que_r…
50282 …mory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram
50285 …et parity only for memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc1 in module cfc_lc_que_ram
50287 …et parity only for memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc2 in module cfc_lc_que_ram
50289 …mory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram
50291 …mory ecc instance ccfc.i_cfc_core.CFC_RFE_QUE_GEN.i_rfe_que_ctrl_ram.i_ecc in module cfc_rfe_que_r…
50293 …emory ecc instance ccfc.i_cfc_core.CFC_RFE_QUE_GEN.i_rfe_que_upd_ram.i_ecc in module cfc_rfe_que_r…
50295 …mory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram
50298 … error occurred on memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc1 in module cfc_lc_que_ram
50300 … error occurred on memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc2 in module cfc_lc_que_ram
50302 …mory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram
50304 …mory ecc instance ccfc.i_cfc_core.CFC_RFE_QUE_GEN.i_rfe_que_ctrl_ram.i_ecc in module cfc_rfe_que_r…
50306 …emory ecc instance ccfc.i_cfc_core.CFC_RFE_QUE_GEN.i_rfe_que_upd_ram.i_ecc in module cfc_rfe_que_r…
50308 …mory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram
50311 …L //Access:RC DataWidth:0x20 // Statistics register that counts cycles in which load context r…
50312 …in which a Primary Lock condition exists when it was caused by an Increment command on a previousl…
50313 …in which a Primary Lock condition exists when it was caused by an Lock command on a previously loc…
50324 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
50332 …ved. bit0: Chicken bit for CQ73536 fix. When '0' takes into account LCIDs in the pipe. When '1' b…
50333 …ternal error it will set one of these bits. the bit description can be found in CFC specifications.
50334 …idth:0x11 // Masking for error logging. if a bit in this field is set then the corresponding bit…
50335 … 0x2e0554UL //Access:RW DataWidth:0x11 // Indicates per error (in CFC_REGISTERS_CFC_ER…
50336 …-- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Not…
50337 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
50338 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
50339 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
50341 … (0x1<<0) // When set CFC arbiter1 will work in strict priority.
50343 … (0x1<<1) // When set load context arbiter will work in strict priority.
50345 … (0x1<<2) // When set CFC arbiter2 will work in strict priority.
50347 … (0x1<<3) // When set CFC arbiter3 will work in strict priority.
50349 … (0x1<<4) // When set activity counter decrement arbiter will work in strict priority.
50351 … (0x1<<5) // When set activity counter increment arbiter will work in strict priority.
50353 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50363 … (0xf<<10) // This register is not used in BB-B0. Reduced width t…
50391 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50392 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50393 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50394 …quest is processed do not move the LCID to Inactive state if any of the regions are in error state.
50410 … 0x2e0600UL //Access:R DataWidth:0x9 // Number of Empty LCIDs in Link List Block (not…
50411 … 0x2e0604UL //Access:R DataWidth:0x9 // Number of Inside not active LCIDs in Link List Block.
50412 … 0x2e0608UL //Access:R DataWidth:0x9 // Number of inside/outside LCIDs in Link List Block.
50413 … 0x2e060cUL //Access:R DataWidth:0x9 // Number of LCIDs in the EMPTY state.
50414 … 0x2e0610UL //Access:R DataWidth:0x9 // Number of LCIDs in the ARRIVING state.
50415 … 0x2e0614UL //Access:R DataWidth:0x9 // Number of LCIDs in the INSIDE state.
50416 … 0x2e0618UL //Access:R DataWidth:0x9 // Number of LCIDs in the INSIDE_NA state.
50417 … 0x2e061cUL //Access:R DataWidth:0x9 // Number of LCIDs in the LEAVING state.
50418 … 0x2e0620UL //Access:R DataWidth:0x9 // Number of LCIDs in the I_AND_O state.
50419 … 0x2e0624UL //Access:R DataWidth:0x9 // Number of LCIDs in the BDELETED state.
50421 …00UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a …
50422 …04UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a …
50423 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50424 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50427 …x3ff<<0) // The Threshold of EmptyLCIDs which must be in the Empty State to enable the MiniCache i…
50429 … (0x1<<10) // This field is not used in BB-B0. When set, this …
50431 … 0x2e0718UL //Access:RW DataWidth:0x1 // Enables MiniCache in Load Clients.
50439 …ad On Error. if this bit is set and there is a load request region that is in error state then a n…
50455 …L //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if les…
50456 … Array of indirect registers defines the forced load regions per type. Applicable only in the TCFC.
50463 …0x2e0804UL //Access:R DataWidth:0x9 // Reserved: This register is no longer needed in E4 B0.
50464 …0x2e0808UL //Access:R DataWidth:0x9 // Reserved: This register is no longer needed in E4 b0.
50466 …lements in empty list and in IO list is bigger than the value of this register, LC controller can …
50481 … DataWidth:0x9 // This is threshold register to disable Direct messages in the DORQ. When the n…
50482 …ill restart the Timer in each Generator. At this time, the output of the Generator will be set to …
50510 …8 // Mask vector for enabling caching on various string types. Each bit in this register matche…
50512 …will be used to cache results from the Searcher that did not match an entry in the external tables.
50516 …earches and Writes to the CID CAM. Setting a bit to 0 will ignore that bit in a search. Setting a …
50529 …:0xa // {HIT;LCID}. HIT - if set then previous CAM seach item (either CCAM or SCAM) was found. …
50530 …in E4B0. 0 - tid is not included in hash calculation (like in A0). 1 - tid is included in hash cal…
50531 …in E4B0. 0 - vlan is not included in hash calculation (like in A0). 1 - vlan is included in hash c…
50535 … 0x2e0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CI…
50539 … 0x2e0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the ST…
50550 … 0x2eb000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
50555 …idth:0xc // TID Lock RAM Access Register [11] = Locked [10] = In Use [09:00] = Usag…
50594 … (0x1<<15) // Overflow or underflow error in one of FIFOs.
50684 … (0x1<<15) // Overflow or underflow error in one of FIFOs.
50729 … (0x1<<15) // Overflow or underflow error in one of FIFOs.
51104 …ory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_0 in module qm_mem_bigram…
51106 …ory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_1 in module qm_mem_bigram…
51108 …nstance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_0 in module qm_mem_bigram…
51110 …nstance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_1 in module qm_mem_bigram…
51112 …c instance qm.QM_MEM_PTR_TBL_TX_PQ_512PQTX_IF.i_qm_mem_ptr_tbl_tx_pq.i_ecc in module qm_mem_ptr_tb…
51114 …ory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_0 in module qm_mem_bigram…
51116 …ory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_1 in module qm_mem_bigram…
51118 …nstance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_0 in module qm_mem_bigram…
51120 …nstance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_1 in module qm_mem_bigram…
51122 …c instance qm.QM_MEM_PTR_TBL_TX_PQ_512PQTX_IF.i_qm_mem_ptr_tbl_tx_pq.i_ecc in module qm_mem_ptr_tb…
51125 …ory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_0 in module qm_mem_bigram…
51127 …ory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_1 in module qm_mem_bigram…
51129 …nstance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_0 in module qm_mem_bigram…
51131 …nstance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_1 in module qm_mem_bigram…
51133 …c instance qm.QM_MEM_PTR_TBL_TX_PQ_512PQTX_IF.i_qm_mem_ptr_tbl_tx_pq.i_ecc in module qm_mem_ptr_tb…
51135 …ory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_0 in module qm_mem_bigram…
51137 …ory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_1 in module qm_mem_bigram…
51139 …nstance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_0 in module qm_mem_bigram…
51141 …nstance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_1 in module qm_mem_bigram…
51143 …c instance qm.QM_MEM_PTR_TBL_TX_PQ_512PQTX_IF.i_qm_mem_ptr_tbl_tx_pq.i_ecc in module qm_mem_ptr_tb…
51146 …ory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_0 in module qm_mem_bigram…
51148 …ory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_1 in module qm_mem_bigram…
51150 …nstance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_0 in module qm_mem_bigram…
51152 …nstance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_1 in module qm_mem_bigram…
51154 …c instance qm.QM_MEM_PTR_TBL_TX_PQ_512PQTX_IF.i_qm_mem_ptr_tbl_tx_pq.i_ecc in module qm_mem_ptr_tb…
51156 …ory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_0 in module qm_mem_bigram…
51158 …ory ecc instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_ecc_1 in module qm_mem_bigram…
51160 …nstance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_0 in module qm_mem_bigram…
51162 …nstance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_1 in module qm_mem_bigram…
51164 …c instance qm.QM_MEM_PTR_TBL_TX_PQ_512PQTX_IF.i_qm_mem_ptr_tbl_tx_pq.i_ecc in module qm_mem_ptr_tb…
51180 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51181 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51182 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51183 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51184 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51185 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51186 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51187 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51188 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51189 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51190 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51191 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51192 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51193 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51194 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51195 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51196 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51197 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51198 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51199 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51200 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51201 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51202 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51203 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51204 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51205 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51206 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51207 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51208 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51209 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51210 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51211 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51212 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51213 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51214 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51215 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51216 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51217 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51218 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51219 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51220 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51221 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51222 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51223 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51224 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51225 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51226 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51227 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51228 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51229 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51230 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51231 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51232 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51233 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51234 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51235 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51236 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51237 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51238 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51239 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51240 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51241 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51242 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51243 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51244 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51245 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51246 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51247 … 0x2f0600UL //Access:RW DataWidth:0x14 // The base logical address (in 4096 bytes) of each …
51254 …L //Access:WB DataWidth:0x36 // Pointer Table Memory for Other queues 63-0; The mapping is as …
51260 … 0x2f1010UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards…
51264 … 0x2f1030UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards…
51265 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51266 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51267 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51268 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51269 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51270 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51271 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51272 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51273 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51274 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51275 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51276 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51277 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51278 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51279 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51280 …rent TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; …
51281 …:0x20 // Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 …
51282 …:0x20 // Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 …
51283 …:0x20 // Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 …
51284 …:0x20 // Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 …
51285 … 0x2f1220UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51286 … 0x2f1224UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51287 … 0x2f1228UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51288 … 0x2f122cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51289 … 0x2f1230UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51290 … 0x2f1234UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51291 … 0x2f1238UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51292 … 0x2f123cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51293 … 0x2f1240UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51294 … 0x2f1244UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51295 … 0x2f1248UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51296 … 0x2f124cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51297 … 0x2f1250UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51298 … 0x2f1254UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51299 … 0x2f1258UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51300 … 0x2f125cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51301 … 0x2f1260UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51302 … 0x2f1264UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51303 … 0x2f1268UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51304 … 0x2f126cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51305 … 0x2f1270UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51306 … 0x2f1274UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51307 … 0x2f1278UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51308 … 0x2f127cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51309 … 0x2f1280UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51310 … 0x2f1284UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51311 … 0x2f1288UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51312 … 0x2f128cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51313 … 0x2f1290UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51314 … 0x2f1294UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51315 … 0x2f1298UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51316 … 0x2f129cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51317 … 0x2f12a0UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51318 … 0x2f12a4UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51319 … 0x2f12a8UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51320 … 0x2f12acUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51321 … 0x2f12b0UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51322 … 0x2f12b4UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51323 … 0x2f12b8UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51324 … 0x2f12bcUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load reques…
51325 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51326 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51327 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51328 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51329 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51330 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51331 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51332 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51333 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51334 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51335 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51336 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51337 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51338 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51339 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51340 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51341 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51342 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51343 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51344 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51345 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51346 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51347 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51348 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51349 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51350 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51351 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51352 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51353 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51354 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51355 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51356 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51357 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51358 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51359 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51360 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51361 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51362 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51363 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51364 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51365 … 0x2f1520UL //Access:RW DataWidth:0x5 // The virtual Queue ID used in the PCI request.
51366 … 0x2f1524UL //Access:RW DataWidth:0x2 // The PCI attributes field used in the PCI request.
51367 …in the PCI request. b2-b0: rd first bank in page; b3: reserved (zero); b6-b4: wr first bank in pag…
51368 …al STU within the PXP (there is STU per PF). 0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
51369 …0x10 // The PCI TPH field used in the PCI request. Per PF value. bits: 8-0 TPH Steering Tag Inde…
51372 …cess:RC DataWidth:0x1 // A flag to indicate that overflow error occurred in one of the queues.
51374 …cess:RC DataWidth:0x1 // A flag to indicate that overflow error occurred in one of the queues.
51375 …- VOQs [0..31] VoqCrdLineFull_msb - VOQs [32..35] Some VOQs are "not used" depending on the…
51376 …t per every task in the QM. must be smaller or equal to the matched Voq line credit (relevant onl…
51377 …- VOQs [0..31]. VoqCrdByteFull_msb - VOQs [32..35]. Some VOQs are "not used" depending on t…
51378 …in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 -…
51379 …in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 -…
51380 …in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 -…
51381 …in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 -…
51382 …in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 -…
51383 …- VOQs [0..31]. AFullQmBypThrLineVoqMask_msb - VOQs [32..35]. Some VOQs are "not used" depe…
51388 …- resource is required to be more than the almost full threshold. 0 - resource value is do not car…
51391 …ost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_3
51392 …ost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_4
51395 …- resource is required to be more than the almost full threshold. 0 - resource value is do not car…
51396 … 0x2f1948UL //Access:RW DataWidth:0x1 // Allows the QM to work in qm bypass mode. i.e.…
51398 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51399 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51400 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51401 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51402 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51403 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51404 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51405 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51406 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51407 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51408 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51409 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51410 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51411 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51412 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51413 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51414 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51415 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51416 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51417 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51418 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51419 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51420 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51421 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51422 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51423 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51424 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b01. NOTE: weight update is allowed only to queues w…
51425 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b11. NOTE: weight update is allowed only to queues w…
51436 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51437 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51438 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51439 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51440 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51441 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51442 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51443 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51444 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51445 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51446 …is masked. i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51447 …-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM se…
51450 …g is used for sending SDM command through the RBC. See command description in the QM EAS section S…
51451 …g is used for sending SDM command through the RBC. See command description in the QM EAS section S…
51452 …g is used for sending SDM command through the RBC. See command description in the QM EAS section S…
51453 …g is used for sending SDM command through the RBC. See command description in the QM EAS section S…
51454 …g is used for sending SDM command through the RBC. See command description in the QM EAS section S…
51462 …0x2f2800UL //Access:R DataWidth:0x1 // The status of the Other PQ-s: bit0 - PQ paused. Shoul…
51466 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51467 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51468 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51469 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51470 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51471 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51472 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51473 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51474 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51475 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51476 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51477 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51478 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51479 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51480 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51481 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51482 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51483 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51484 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51485 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51486 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51487 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51488 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51489 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51490 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51491 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51492 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51493 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51494 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51495 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51496 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51497 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51498 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51499 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51500 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51501 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51502 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51503 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51504 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51505 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51506 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51507 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51508 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51509 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51510 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51511 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51512 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51513 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51514 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51515 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51516 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51517 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51518 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51519 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51520 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51521 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51522 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51523 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51524 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51525 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51526 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51527 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51528 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51529 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51530 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51531 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51532 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51533 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51534 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51535 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51536 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51537 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51538 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51539 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51540 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51541 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51542 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51543 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51544 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51545 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51550 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for selecting a line…
51551 …or dbgmux usage (debug data that goes from QM to the DBG block) - for enabling dwords in the selec…
51552 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for circular right s…
51553 … // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing valid.
51554 … // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing frame.
51555 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 lsb data that…
51556 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 msb data that…
51557 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 frame bits tha…
51558 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 valid bits tha…
51571 …h:0x20 // The RL timeout period in 25Mhz clock cycles for the global. VP/QCN RL-s. 0 - Global VP…
51572 …h:0x20 // The RL timeout period in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/…
51573 …r in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. Upon init shoul…
51574 … // The RL timeout period counter in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/…
51575 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51576 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51577 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51578 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51579 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51580 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51581 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51582 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51585 …b is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bi…
51587 …in non-init mode. In init mode should be written with the same value of RlGlblUpperBound. Sign: th…
51591 …x1 // when 1 - force cam search and update sts_rlglbl_pq_blocked vector even when the rlglblcrd…
51592 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51593 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51594 …o). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51595 …ector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlGlblCrd; b1 …
51596 …L //Access:RW DataWidth:0x20 // The RL timeout period in 25Mhz clock cycles for the PF RL-s. N…
51597 …ss:RW DataWidth:0x20 // The RL timeout period counter in 25Mhz clock cycles for the PF RL-s. U…
51601 …b is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bi…
51604 …in non-init mode. In init mode should be written with the same value of RlPfUpperBound. Sign: the …
51608 … the PF RL mechanism per VOQ. RlPfVoqEnable (This one) - VOQs [0..31]. RlPfVoqEnable_msb - …
51609 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51610 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51611 …ero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51612 … vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlPfCrd; b1 …
51616 …b is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bi…
51619 …- VOQ0..VOQ15. WfqPfCrd_msb - VOQ16..VOQ35. Should be read only access in non-init mode. In init m…
51624 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51625 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51626 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51627 …vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqPfCrd; b1 …
51629 …0x1 // when 1 - force cam search and update sts_wfqvp_pq_blocked vector even when the wfqvpcrd …
51630 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51631 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51632 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51633 …vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqVpCrd; b1 …
51634 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51635 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51636 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51637 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51638 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51639 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51640 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51641 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51642 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51643 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51644 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51645 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51646 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51647 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51648 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51649 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51650 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51651 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51652 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51653 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51654 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51655 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51656 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51657 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51659 …-idle state, trying to start new TX arbitration depends on the GO mode as follows: 0 - start new T…
51662 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51663 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51664 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51665 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51666 …when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqLineCrd; b1 - Err_…
51667 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51668 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51669 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51670 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51671 …when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqByteCrd; b1 - Err_…
51678 …o verify that prior to sending go command. (b) Go command can be sent only in init mode (i.e. no f…
51680 … mem is initiazlied. when reset the mem in not initiazlied. There is mask bit per mem, the followi…
51681 … mem is initiazlied. when reset the mem in not initiazlied. There is mask bit per mem, the followi…
51682 …d with all ones. when reset the mem in initialized with all zeroes. There is bit per mem, the foll…
51683 …d with all ones. when reset the mem in initialized with all zeroes. There is bit per mem, the foll…
51684 …ly being initialized. There is status bit per mem, the following are mems 31-0: b0: qm_mem_bigram_…
51685 …ly being initialized. There is status bit per mem, the following are mems 63-32: b32: qm_mem_cfc_l…
51689 … 0x2f5da8UL //Access:R DataWidth:0x16 // Provides read-only access to the BI…
51690 … 0x2f6000UL //Access:RW DataWidth:0x14 // The base logical address (in 4096 bytes) of each …
51693 … 0x2f1120UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51694 … 0x2f6800UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51695 … 0x2f1124UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51696 … 0x2f6804UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51697 … 0x2f1128UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51698 … 0x2f6808UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51699 … 0x2f112cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51700 … 0x2f680cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51701 … 0x2f1130UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51702 … 0x2f6810UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51703 … 0x2f1134UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51704 … 0x2f6814UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51705 … 0x2f1138UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51706 … 0x2f6818UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51707 … 0x2f113cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51708 … 0x2f681cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51709 … 0x2f1140UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51710 … 0x2f6820UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51711 … 0x2f1144UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51712 … 0x2f6824UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51713 … 0x2f1148UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51714 … 0x2f6828UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51715 … 0x2f114cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51716 … 0x2f682cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51717 … 0x2f1150UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51718 … 0x2f6830UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51719 … 0x2f1154UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51720 … 0x2f6834UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51721 … 0x2f1158UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51722 … 0x2f6838UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51723 … 0x2f115cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51724 … 0x2f683cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51725 … 0x2f1160UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51726 … 0x2f6840UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51727 … 0x2f1164UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51728 … 0x2f6844UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51729 … 0x2f1168UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51730 … 0x2f6848UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51731 … 0x2f116cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51732 … 0x2f684cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51733 … 0x2f1170UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51734 … 0x2f6850UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51735 … 0x2f1174UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51736 … 0x2f6854UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51737 … 0x2f1178UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51738 … 0x2f6858UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51739 … 0x2f117cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51740 … 0x2f685cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51741 … 0x2f1180UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51742 … 0x2f6860UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51743 … 0x2f1184UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51744 … 0x2f6864UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51745 … 0x2f1188UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51746 … 0x2f6868UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51747 … 0x2f118cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51748 … 0x2f686cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51749 … 0x2f1190UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51750 … 0x2f6870UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51751 … 0x2f1194UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51752 … 0x2f6874UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51753 … 0x2f1198UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51754 … 0x2f6878UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51755 … 0x2f119cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51756 … 0x2f687cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51757 … 0x2f11a0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51758 … 0x2f6880UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51759 … 0x2f11a4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51760 … 0x2f6884UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51761 … 0x2f11a8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51762 … 0x2f6888UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51763 … 0x2f11acUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51764 … 0x2f688cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51765 … 0x2f11b0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51766 … 0x2f6890UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51767 … 0x2f11b4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51768 … 0x2f6894UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51769 … 0x2f11b8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51770 … 0x2f6898UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51771 … 0x2f11bcUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51772 … 0x2f689cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51773 … 0x2f68a0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51774 … 0x2f68a4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51775 … 0x2f68a8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51776 … 0x2f68acUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51777 … 0x2f68b0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51778 … 0x2f68b4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51779 … 0x2f68b8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51780 … 0x2f68bcUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51781 … 0x2f68c0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51782 … 0x2f68c4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51783 … 0x2f68c8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51784 … 0x2f68ccUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51785 … 0x2f68d0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51786 … 0x2f68d4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51787 … 0x2f68d8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51788 … 0x2f68dcUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51789 … 0x2f68e0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51790 … 0x2f68e4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51791 … 0x2f68e8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51792 … 0x2f68ecUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51793 … 0x2f68f0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51794 … 0x2f68f4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51795 … 0x2f68f8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51796 … 0x2f68fcUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51797 … 0x2f6900UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51798 … 0x2f6904UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51799 … 0x2f6908UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51800 … 0x2f690cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51801 … 0x2f6910UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51802 … 0x2f6914UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51803 … 0x2f6918UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51804 … 0x2f691cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51805 … 0x2f6920UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51806 … 0x2f6924UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51807 … 0x2f6928UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51808 … 0x2f692cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51809 … 0x2f6930UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51810 … 0x2f6934UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51811 … 0x2f6938UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51812 … 0x2f693cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load reques…
51813 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51814 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51815 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51816 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51817 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51818 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51819 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51820 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51821 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51822 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51823 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51824 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51825 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51826 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51827 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51828 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51829 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51830 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51831 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51832 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51833 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51834 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51835 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51836 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51837 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51838 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51839 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51840 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51841 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51842 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51843 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51844 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51845 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51846 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51847 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51848 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51849 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51850 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51851 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51852 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51853 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51854 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51855 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51856 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51857 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51858 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51859 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51860 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51861 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51862 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51863 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51864 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51865 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51866 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51867 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51868 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51869 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51870 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51871 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51872 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51873 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51874 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51875 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51876 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51877 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51878 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51879 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51880 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51881 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51882 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51883 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51884 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51885 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51886 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51887 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51888 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51889 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51890 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51891 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51892 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51893 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51894 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51895 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51896 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51897 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51898 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51899 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51900 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51901 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51902 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51903 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51904 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51905 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51906 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51907 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51908 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51909 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51910 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51911 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51912 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51913 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51914 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51915 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51916 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51917 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51918 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51919 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51920 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51921 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51922 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51923 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51924 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51925 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51926 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51927 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51928 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51929 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51930 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51931 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51932 …RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM…
51936 …th:0x4 // The status of the TX PQ-s: bit0 - PQ global VP/QCN RL block; bit1 - PQ active; bit2 -…
51939 …- PQ valid; bits 8:1 - RL id; bits 17:9 - VP id (value of all ones is reserved for pure-LB VOQ …
51945 …b is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bi…
51948 …in non-init mode. In init mode should be written with the same value of WfqVpUpperBound. Sign: the…
51951 … between VP WFQ counter and its resources as follows: bit 5:0 - Voq id; bit 9:6 - Pf id; Som…
51954 …0UL //Access:WB DataWidth:0x36 // Pointer Table Memory for TX queues 447-0; The mapping is as …
51957 …in non-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the…
51958 …in non-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the…
51961 …-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM se…
51962 …-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM se…
51964 …/ The actual line credit for each VOQ. Should be read only access in non-init mode. In init mode s…
51965 …/ The actual line credit for each VOQ. Should be read only access in non-init mode. In init mode s…
51969 …it and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of …
51970 …it and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of …
51974 …/ The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mode s…
51975 …/ The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mode s…
51979 …0x18 // The init and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16.
51980 …it and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16. Some VOQs are …
51984 …- VOQs [0..31]. AFullQmBypThrLineVoqMask_msb (This one) - VOQs [32..35]. Some VOQs are "not used" …
51985 …F RL mechanism per VOQ. RlPfVoqEnable - VOQs [0..31]. RlPfVoqEnable_msb (This one) …
51986 …- VOQs [0..31]. VoqCrdLineFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51987 …- VOQs [0..31]. VoqCrdByteFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51988 …write zero to all L1 entries. When the command is complete zero will be indicated in this register.
51989 …dth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
51990 …ataWidth:0x1 // If set allow bypass the pipline on pass through commands and in an empty system.
51994 …ataWidth:0x1 // Writing to this register (any value) will copy the data in buffer 0 to the debu…
51996 …ataWidth:0x1 // Writing to this register (any value) will copy the data in buffer 0 to the debu…
52001 … 0x30007cUL //Access:RW DataWidth:0x8 // If bit i is set; the data in the debug_error_info…
52004 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52005 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52006 … 0x300090UL //Access:R DataWidth:0x20 // DEBUG: Buffer information. Calculated offset in IO.
52007 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52008 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52013 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52014 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52015 … 0x3000b4UL //Access:R DataWidth:0x20 // DEBUG: Buffer information. Calculated offset in IO.
52016 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52017 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52021 … 0x3000ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52022 … 0x3000d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52024 … 0x3000d8UL //Access:R DataWidth:0x1 // DEBUG: if set there is no valid data in the pipeline.
52026 …ir E4 place and used accordingly. When reset E5 functionality is in effect
52040 …or is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The d…
52078 …or is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The d…
52097 …or is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The d…
52106 …in the IO will be logged. In bits [5:3] of the address represent the error number (0-7). Do not re…
52109 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
52117 …-Initial reference tag Address offset-0 bits [31:0]; Field name-Application tag value Address offs…
52118 …In TDIF - Has 8 QWORDs per task allocated (All are valid). In RDIF - Has 8 QWORDs per task allocat…
52121 …write zero to all L1 entries. When the command is complete zero will be indicated in this register.
52122 …dth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
52124 …ataWidth:0x1 // If set allow bypass the pipline on pass through commands and in an empty system.
52128 …ataWidth:0x1 // Writing to this register (any value) will copy the data in buffer 0 to the debu…
52130 …ataWidth:0x1 // Writing to this register (any value) will copy the data in buffer 0 to the debu…
52135 … 0x31007cUL //Access:RW DataWidth:0x8 // If bit i is set; the data in the debug_error_info…
52138 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52139 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52140 … 0x310090UL //Access:R DataWidth:0x20 // DEBUG: Buffer information. Calculated offset in IO.
52141 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52142 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52147 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52148 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52149 … 0x3100b4UL //Access:R DataWidth:0x20 // DEBUG: Buffer information. Calculated offset in IO.
52150 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52151 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52155 … 0x3100ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52156 … 0x3100d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52158 … 0x3100d8UL //Access:R DataWidth:0x1b // [3:0] - error type ([0] Writ…
52159 … 0x3100dcUL //Access:R DataWidth:0x1 // DEBUG: if set there is no valid data in the pipeline.
52176 …ir E4 place and used accordingly. When reset E5 functionality is in effect
52190 …or is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The d…
52228 …or is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The d…
52247 …or is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The d…
52284 …<0) // Enable ECC for memory ecc instance tdif.i_tdif_l1_sector0_mem.i_ecc in module tdif_l1_secto…
52286 …<1) // Enable ECC for memory ecc instance tdif.i_tdif_l1_sector4_mem.i_ecc in module tdif_l1_secto…
52288 …<2) // Enable ECC for memory ecc instance tdif.i_tdif_l1_sector5_mem.i_ecc in module tdif_l1_secto…
52290 …<3) // Enable ECC for memory ecc instance tdif.i_tdif_l1_sector6_mem.i_ecc in module tdif_l1_secto…
52293 …/ Set parity only for memory ecc instance tdif.i_tdif_l1_sector0_mem.i_ecc in module tdif_l1_secto…
52295 …/ Set parity only for memory ecc instance tdif.i_tdif_l1_sector4_mem.i_ecc in module tdif_l1_secto…
52297 …/ Set parity only for memory ecc instance tdif.i_tdif_l1_sector5_mem.i_ecc in module tdif_l1_secto…
52299 …/ Set parity only for memory ecc instance tdif.i_tdif_l1_sector6_mem.i_ecc in module tdif_l1_secto…
52302 …ble error occurred on memory ecc instance tdif.i_tdif_l1_sector0_mem.i_ecc in module tdif_l1_secto…
52304 …ble error occurred on memory ecc instance tdif.i_tdif_l1_sector4_mem.i_ecc in module tdif_l1_secto…
52306 …ble error occurred on memory ecc instance tdif.i_tdif_l1_sector5_mem.i_ecc in module tdif_l1_secto…
52308 …ble error occurred on memory ecc instance tdif.i_tdif_l1_sector6_mem.i_ecc in module tdif_l1_secto…
52311 …in the IO will be logged. In bits [5:3] of the address represent the error number (0-7). Do not re…
52314 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
52322 …In TDIF - Has 8 QWORDs per task allocated (All are valid). In RDIF - Has 8 QWORDs per task allocat…
52326 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
52353 …<<0) // Enable ECC for memory ecc instance rgsrc.i_rgsrc_reqfifo_mem.i_ecc in module rgsrc_reqfifo…
52355 …1) // Enable ECC for memory ecc instance rgsrc.i_rgsrc_pswrdfifo_mem.i_ecc in module rgsrc_pswrdfi…
52358 …// Set parity only for memory ecc instance rgsrc.i_rgsrc_reqfifo_mem.i_ecc in module rgsrc_reqfifo…
52360 … Set parity only for memory ecc instance rgsrc.i_rgsrc_pswrdfifo_mem.i_ecc in module rgsrc_pswrdfi…
52363 …able error occurred on memory ecc instance rgsrc.i_rgsrc_reqfifo_mem.i_ecc in module rgsrc_reqfifo…
52365 …le error occurred on memory ecc instance rgsrc.i_rgsrc_pswrdfifo_mem.i_ecc in module rgsrc_pswrdfi…
52373 …in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_…
52374 …in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_…
52389 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52400 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
52427 …<<0) // Enable ECC for memory ecc instance tgsrc.i_tgsrc_reqfifo_mem.i_ecc in module tgsrc_reqfifo…
52429 …1) // Enable ECC for memory ecc instance tgsrc.i_tgsrc_pswrdfifo_mem.i_ecc in module tgsrc_pswrdfi…
52432 …// Set parity only for memory ecc instance tgsrc.i_tgsrc_reqfifo_mem.i_ecc in module tgsrc_reqfifo…
52434 … Set parity only for memory ecc instance tgsrc.i_tgsrc_pswrdfifo_mem.i_ecc in module tgsrc_pswrdfi…
52437 …able error occurred on memory ecc instance tgsrc.i_tgsrc_reqfifo_mem.i_ecc in module tgsrc_reqfifo…
52439 …le error occurred on memory ecc instance tgsrc.i_tgsrc_pswrdfifo_mem.i_ecc in module tgsrc_pswrdfi…
52447 …in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_…
52448 …in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_…
52463 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52473 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
52474 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
52479 …uested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
52481 …t is not really first packet block RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
52483 …r when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
52485 …or when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR0…
52487 …r when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
52489 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
52491 … is not really first packet block RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
52493 … when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
52495 …r when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR1/…
52497 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
52499 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
52501 … is not really first packet block RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
52503 … when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
52505 …r when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR2/…
52507 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
52509 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
52511 …s not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
52513 …hen requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
52515 … when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/p…
52517 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
52521 … // One of uncoplient lossless counters is bigger than threshold PAUSE_EN::/PAUSE_EN/d in Comments.
52525 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
52527 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
52529 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
52531 … (0x1<<27) // Link list arbiter prefetch SOP error RX_INT::/RX_INT/d in Comments.
52535 …29) // Packet counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
52537 …<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
52539 …31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. When unifi…
52609 …uested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
52611 …t is not really first packet block RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
52613 …r when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
52615 …or when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR0…
52617 …r when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
52619 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
52621 … is not really first packet block RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
52623 … when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
52625 …r when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR1/…
52627 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
52629 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
52631 … is not really first packet block RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
52633 … when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
52635 …r when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR2/…
52637 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
52639 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
52641 …s not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
52643 …hen requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
52645 … when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/p…
52647 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
52651 … // One of uncoplient lossless counters is bigger than threshold PAUSE_EN::/PAUSE_EN/d in Comments.
52655 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
52657 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
52659 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
52661 … (0x1<<27) // Link list arbiter prefetch SOP error RX_INT::/RX_INT/d in Comments.
52665 …29) // Packet counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
52667 …<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
52669 …31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. When unifi…
52674 …uested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
52676 …t is not really first packet block RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
52678 …r when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
52680 …or when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR0…
52682 …r when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
52684 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
52686 … is not really first packet block RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
52688 … when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
52690 …r when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR1/…
52692 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
52694 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
52696 … is not really first packet block RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
52698 … when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
52700 …r when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR2/…
52702 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
52704 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
52706 …s not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
52708 …hen requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
52710 … when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/p…
52712 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
52716 … // One of uncoplient lossless counters is bigger than threshold PAUSE_EN::/PAUSE_EN/d in Comments.
52720 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
52722 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
52724 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
52726 … (0x1<<27) // Link list arbiter prefetch SOP error RX_INT::/RX_INT/d in Comments.
52730 …29) // Packet counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
52732 …<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
52734 …31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. When unifi…
52737 …<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments. When unifi…
52739 … (0x1<<1) // Calculations error in LL arbiter block.
52741 … (0x1<<3) // Input FIFO error in write client 0.
52743 … (0x1<<4) // SOP FIFO error in write client 0.
52745 … (0x1<<6) // EOP FIFO error in write client 0.
52747 … (0x1<<7) // Queue FIFO error in write client 0.
52749 … (0x1<<8) // Free ointer FIFO error in write client 0.
52751 … (0x1<<9) // Next pointer FIFO error in write client 0.
52753 … (0x1<<10) // Start FIFO error in write client 0.
52755 … (0x1<<11) // Second descriptor FIFO error in write client 0.
52757 … (0x1<<12) // Packet available FIFO error in write client 0.
52759 … (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Co…
52761 … (0x1<<14) // Notify FIFO error in write client 0.
52763 … (0x1<<15) // LL req error in write client 0.
52769 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/R…
52771 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX…
52773 … Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 1 RX_INT::/RX…
52775 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/R…
52777 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT:…
52779 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT:…
52781 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/R…
52783 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_I…
52785 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_IN…
52787 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT:…
52789 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/R…
52791 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_…
52793 … bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to l…
52795 …nection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram o…
52859 …<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments. When unifi…
52861 … (0x1<<1) // Calculations error in LL arbiter block.
52863 … (0x1<<3) // Input FIFO error in write client 0.
52865 … (0x1<<4) // SOP FIFO error in write client 0.
52867 … (0x1<<6) // EOP FIFO error in write client 0.
52869 … (0x1<<7) // Queue FIFO error in write client 0.
52871 … (0x1<<8) // Free ointer FIFO error in write client 0.
52873 … (0x1<<9) // Next pointer FIFO error in write client 0.
52875 … (0x1<<10) // Start FIFO error in write client 0.
52877 … (0x1<<11) // Second descriptor FIFO error in write client 0.
52879 … (0x1<<12) // Packet available FIFO error in write client 0.
52881 … (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Co…
52883 … (0x1<<14) // Notify FIFO error in write client 0.
52885 … (0x1<<15) // LL req error in write client 0.
52891 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/R…
52893 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX…
52895 … Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 1 RX_INT::/RX…
52897 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/R…
52899 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT:…
52901 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT:…
52903 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/R…
52905 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_I…
52907 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_IN…
52909 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT:…
52911 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/R…
52913 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_…
52915 … bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to l…
52917 …nection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram o…
52920 …<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments. When unifi…
52922 … (0x1<<1) // Calculations error in LL arbiter block.
52924 … (0x1<<3) // Input FIFO error in write client 0.
52926 … (0x1<<4) // SOP FIFO error in write client 0.
52928 … (0x1<<6) // EOP FIFO error in write client 0.
52930 … (0x1<<7) // Queue FIFO error in write client 0.
52932 … (0x1<<8) // Free ointer FIFO error in write client 0.
52934 … (0x1<<9) // Next pointer FIFO error in write client 0.
52936 … (0x1<<10) // Start FIFO error in write client 0.
52938 … (0x1<<11) // Second descriptor FIFO error in write client 0.
52940 … (0x1<<12) // Packet available FIFO error in write client 0.
52942 … (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Co…
52944 … (0x1<<14) // Notify FIFO error in write client 0.
52946 … (0x1<<15) // LL req error in write client 0.
52952 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/R…
52954 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX…
52956 … Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 1 RX_INT::/RX…
52958 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/R…
52960 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT:…
52962 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT:…
52964 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/R…
52966 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_I…
52968 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_IN…
52970 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT:…
52972 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/R…
52974 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_…
52976 … bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to l…
52978 …nection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram o…
52981 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/R…
52983 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX…
52985 … Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 2 RX_INT::/RX…
52987 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/R…
52989 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT:…
52991 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT:…
52993 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/R…
52995 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_I…
52997 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_IN…
52999 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT:…
53001 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/R…
53003 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_…
53005 …ection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list …
53007 …or E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP des…
53009 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/R…
53011 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX…
53013 … Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 3 RX_INT::/RX…
53015 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/R…
53017 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT:…
53019 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT:…
53021 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/R…
53023 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_I…
53025 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_IN…
53027 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT:…
53029 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/R…
53031 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_…
53033 …ection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list …
53035 …or E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP des…
53095 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/R…
53097 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX…
53099 … Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 2 RX_INT::/RX…
53101 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/R…
53103 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT:…
53105 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT:…
53107 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/R…
53109 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_I…
53111 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_IN…
53113 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT:…
53115 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/R…
53117 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_…
53119 …ection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list …
53121 …or E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP des…
53123 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/R…
53125 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX…
53127 … Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 3 RX_INT::/RX…
53129 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/R…
53131 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT:…
53133 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT:…
53135 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/R…
53137 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_I…
53139 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_IN…
53141 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT:…
53143 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/R…
53145 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_…
53147 …ection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list …
53149 …or E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP des…
53152 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/R…
53154 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX…
53156 … Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 2 RX_INT::/RX…
53158 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/R…
53160 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT:…
53162 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT:…
53164 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/R…
53166 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_I…
53168 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_IN…
53170 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT:…
53172 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/R…
53174 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_…
53176 …ection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list …
53178 …or E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP des…
53180 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/R…
53182 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX…
53184 … Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 3 RX_INT::/RX…
53186 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/R…
53188 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT:…
53190 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT:…
53192 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/R…
53194 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_I…
53196 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_IN…
53198 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT:…
53200 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/R…
53202 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_…
53204 …ection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list …
53206 …or E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP des…
53209 … (0x1<<1) // Read packet client PRM side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53211 … (0x1<<2) // Read packet client PRM request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53213 … (0x1<<3) // Read packet client PRM block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53215 … (0x1<<4) // Read packet client PRM releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53217 … (0x1<<5) // Read packet client PRM start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53219 … (0x1<<6) // Read packet client PRM second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53221 … (0x1<<7) // Read packet client PRM response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53223 … (0x1<<8) // Read packet client PRM descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53225 … (0x1<<9) // Read packet client MSDM side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53227 … (0x1<<10) // Read packet client MSDM request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53229 … (0x1<<11) // Read packet client MSDM block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53231 … (0x1<<12) // Read packet client MSDM releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53233 … (0x1<<13) // Read packet client MSDM start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53235 …(0x1<<14) // Read packet client MSDM second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53237 … (0x1<<15) // Read packet client MSDM response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53239 … (0x1<<16) // Read packet client MSDM descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53241 … (0x1<<17) // Read packet client TSDM side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53243 … (0x1<<18) // Read packet client TSDM request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53245 … (0x1<<19) // Read packet client TSDM block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53247 … (0x1<<20) // Read packet client TSDM releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53249 … (0x1<<21) // Read packet client TSDM start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53251 …(0x1<<22) // Read packet client TSDM second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53253 … (0x1<<23) // Read packet client TSDM response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53255 … (0x1<<24) // Read packet client TSDM descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53257 … (0x1<<25) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53259 … (0x1<<26) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53261 … (0x1<<27) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53263 …1<<28) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53265 …1<<29) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53267 …<<30) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53269 … (0x1<<31) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53335 … (0x1<<1) // Read packet client PRM side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53337 … (0x1<<2) // Read packet client PRM request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53339 … (0x1<<3) // Read packet client PRM block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53341 … (0x1<<4) // Read packet client PRM releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53343 … (0x1<<5) // Read packet client PRM start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53345 … (0x1<<6) // Read packet client PRM second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53347 … (0x1<<7) // Read packet client PRM response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53349 … (0x1<<8) // Read packet client PRM descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53351 … (0x1<<9) // Read packet client MSDM side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53353 … (0x1<<10) // Read packet client MSDM request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53355 … (0x1<<11) // Read packet client MSDM block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53357 … (0x1<<12) // Read packet client MSDM releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53359 … (0x1<<13) // Read packet client MSDM start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53361 …(0x1<<14) // Read packet client MSDM second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53363 … (0x1<<15) // Read packet client MSDM response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53365 … (0x1<<16) // Read packet client MSDM descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53367 … (0x1<<17) // Read packet client TSDM side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53369 … (0x1<<18) // Read packet client TSDM request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53371 … (0x1<<19) // Read packet client TSDM block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53373 … (0x1<<20) // Read packet client TSDM releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53375 … (0x1<<21) // Read packet client TSDM start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53377 …(0x1<<22) // Read packet client TSDM second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53379 … (0x1<<23) // Read packet client TSDM response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53381 … (0x1<<24) // Read packet client TSDM descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53383 … (0x1<<25) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53385 … (0x1<<26) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53387 … (0x1<<27) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53389 …1<<28) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53391 …1<<29) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53393 …<<30) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53395 … (0x1<<31) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53398 … (0x1<<1) // Read packet client PRM side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53400 … (0x1<<2) // Read packet client PRM request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53402 … (0x1<<3) // Read packet client PRM block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53404 … (0x1<<4) // Read packet client PRM releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53406 … (0x1<<5) // Read packet client PRM start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53408 … (0x1<<6) // Read packet client PRM second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53410 … (0x1<<7) // Read packet client PRM response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53412 … (0x1<<8) // Read packet client PRM descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
53414 … (0x1<<9) // Read packet client MSDM side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53416 … (0x1<<10) // Read packet client MSDM request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53418 … (0x1<<11) // Read packet client MSDM block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53420 … (0x1<<12) // Read packet client MSDM releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53422 … (0x1<<13) // Read packet client MSDM start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53424 …(0x1<<14) // Read packet client MSDM second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53426 … (0x1<<15) // Read packet client MSDM response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53428 … (0x1<<16) // Read packet client MSDM descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
53430 … (0x1<<17) // Read packet client TSDM side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53432 … (0x1<<18) // Read packet client TSDM request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53434 … (0x1<<19) // Read packet client TSDM block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53436 … (0x1<<20) // Read packet client TSDM releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53438 … (0x1<<21) // Read packet client TSDM start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53440 …(0x1<<22) // Read packet client TSDM second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53442 … (0x1<<23) // Read packet client TSDM response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53444 … (0x1<<24) // Read packet client TSDM descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
53446 … (0x1<<25) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53448 … (0x1<<26) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53450 … (0x1<<27) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53452 …1<<28) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53454 …1<<29) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53456 …<<30) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53458 … (0x1<<31) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53461 … (0x1<<0) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53463 … (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
53465 … (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
53467 … (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
53471 … (0x1<<5) // Read EOP client 0 request FIFO error RX_INT::/RX_INT/d in Comments.
53473 … (0x1<<6) // Read EOP client 1 request FIFO error RX_INT::/RX_INT/d in Comments.
53489 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
53491 …s not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
53493 …hen requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
53495 … when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/p…
53497 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
53499 … (0x1<<24) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53501 … (0x1<<25) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53503 … (0x1<<26) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53505 …1<<27) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53507 …1<<28) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53509 …<<29) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53511 … (0x1<<30) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53513 …(0x1<<31) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53571 … (0x1<<0) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53573 … (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
53575 … (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
53577 … (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
53581 … (0x1<<5) // Read EOP client 0 request FIFO error RX_INT::/RX_INT/d in Comments.
53583 … (0x1<<6) // Read EOP client 1 request FIFO error RX_INT::/RX_INT/d in Comments.
53599 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
53601 …s not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
53603 …hen requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
53605 … when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/p…
53607 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
53609 … (0x1<<24) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53611 … (0x1<<25) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53613 … (0x1<<26) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53615 …1<<27) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53617 …1<<28) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53619 …<<29) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53621 … (0x1<<30) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53623 …(0x1<<31) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53626 … (0x1<<0) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53628 … (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
53630 … (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
53632 … (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
53636 … (0x1<<5) // Read EOP client 0 request FIFO error RX_INT::/RX_INT/d in Comments.
53638 … (0x1<<6) // Read EOP client 1 request FIFO error RX_INT::/RX_INT/d in Comments.
53654 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
53656 …s not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
53658 …hen requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
53660 … when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/p…
53662 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
53664 … (0x1<<24) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53666 … (0x1<<25) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53668 … (0x1<<26) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53670 …1<<27) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53672 …1<<28) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53674 …<<29) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53676 … (0x1<<30) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53678 …(0x1<<31) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
53695 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
53697 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
53699 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
53701 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
53703 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/R…
53705 … (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
53707 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
53729 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
53731 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
53733 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
53735 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
53737 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/R…
53739 … (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
53741 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
53746 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
53748 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
53750 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
53752 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
53754 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/R…
53756 … (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
53758 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
53761 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
53763 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
53765 … (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
53767 …(0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
53769 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
53771 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
53773 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
53775 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
53777 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
53779 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
53781 … (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
53783 … (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
53785 … (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
53787 … (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
53789 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
53791 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
53793 …0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
53795 …0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
53797 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
53799 … (0x1<<19) // Notify FIFO error in write client 5
53801 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
53803 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
53805 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
53807 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
53809 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
53811 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
53813 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
53815 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
53817 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
53819 …0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
53821 …0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
53823 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
53891 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
53893 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
53895 … (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
53897 …(0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
53899 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
53901 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
53903 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
53905 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
53907 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
53909 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
53911 … (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
53913 … (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
53915 … (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
53917 … (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
53919 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
53921 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
53923 …0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
53925 …0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
53927 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
53929 … (0x1<<19) // Notify FIFO error in write client 5
53931 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
53933 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
53935 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
53937 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
53939 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
53941 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
53943 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
53945 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
53947 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
53949 …0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
53951 …0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
53953 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
53956 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
53958 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
53960 … (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
53962 …(0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
53964 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
53966 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
53968 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
53970 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
53972 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
53974 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
53976 … (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
53978 … (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
53980 … (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
53982 … (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
53984 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
53986 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
53988 …0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
53990 …0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
53992 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
53994 … (0x1<<19) // Notify FIFO error in write client 5
53996 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
53998 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
54000 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
54002 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
54004 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
54006 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
54008 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
54010 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
54012 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
54014 …0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
54016 …0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
54018 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
54021 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
54023 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
54025 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
54027 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
54029 … (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
54031 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
54033 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
54035 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
54037 … (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
54039 … (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
54041 …0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
54043 …0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
54045 … (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
54047 … (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
54049 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
54051 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
54053 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
54091 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
54093 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
54095 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
54097 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
54099 … (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
54101 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
54103 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
54105 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
54107 … (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
54109 … (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
54111 …0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
54113 …0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
54115 … (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
54117 … (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
54119 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
54121 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
54123 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
54126 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
54128 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
54130 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
54132 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
54134 … (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
54136 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
54138 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
54140 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
54142 … (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
54144 … (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
54146 …0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
54148 …0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
54150 … (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
54152 … (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
54154 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
54156 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
54158 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
54161 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
54167 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
54170 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
54329 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write cl…
54331 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write cl…
54333 … (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write cl…
54335 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write cl…
54363 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write cl…
54365 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write cl…
54367 … (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write cl…
54369 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write cl…
54380 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write cl…
54382 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write cl…
54384 … (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write cl…
54386 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write cl…
54683 …y ecc instance brb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54685 …y ecc instance brb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54687 …y ecc instance brb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54689 …y ecc instance brb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54691 …y ecc instance brb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54693 …y ecc instance brb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54695 …y ecc instance brb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54697 …y ecc instance brb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54699 …y ecc instance brb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54701 …y ecc instance brb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54703 … ecc instance brb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54705 … ecc instance brb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54707 … ecc instance brb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54709 … ecc instance brb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54711 … ecc instance brb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54713 … ecc instance brb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54715 …cc instance brb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module brb_link_list…
54717 …cc instance brb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module brb_link_list…
54719 …cc instance brb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module brb_link_list…
54721 …cc instance brb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module brb_link_list…
54723 …cc instance brb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module brb_link_list…
54725 …cc instance brb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module brb_link_list…
54727 …cc instance brb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module brb_link_list…
54729 …cc instance brb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module brb_link_list…
54735 …y ecc instance brb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54737 …y ecc instance brb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54739 …y ecc instance brb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54741 …y ecc instance brb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54743 …y ecc instance brb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54745 …y ecc instance brb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54747 …y ecc instance brb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54749 …y ecc instance brb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54751 …y ecc instance brb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54753 …y ecc instance brb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54755 … ecc instance brb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54757 … ecc instance brb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54759 … ecc instance brb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54761 … ecc instance brb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54763 … ecc instance brb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54765 … ecc instance brb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54767 …cc instance brb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module brb_link_list…
54769 …cc instance brb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module brb_link_list…
54771 …cc instance brb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module brb_link_list…
54773 …cc instance brb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module brb_link_list…
54775 …cc instance brb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module brb_link_list…
54777 …cc instance brb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module brb_link_list…
54779 …cc instance brb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module brb_link_list…
54781 …cc instance brb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module brb_link_list…
54787 …y ecc instance brb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54789 …y ecc instance brb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54791 …y ecc instance brb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54793 …y ecc instance brb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54795 …y ecc instance brb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54797 …y ecc instance brb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54799 …y ecc instance brb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54801 …y ecc instance brb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54803 …y ecc instance brb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54805 …y ecc instance brb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54807 … ecc instance brb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54809 … ecc instance brb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54811 … ecc instance brb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54813 … ecc instance brb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54815 … ecc instance brb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54817 … ecc instance brb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_k2
54819 …cc instance brb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module brb_link_list…
54821 …cc instance brb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module brb_link_list…
54823 …cc instance brb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module brb_link_list…
54825 …cc instance brb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module brb_link_list…
54827 …cc instance brb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module brb_link_list…
54829 …cc instance brb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module brb_link_list…
54831 …cc instance brb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module brb_link_list…
54833 …cc instance brb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module brb_link_list…
54848 …f big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data…
54849 …in header in 16-bytes resolution. After this number of bytes will input to BRTB will be sent packe…
54850 …s:RW DataWidth:0xe // Head pointer to each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
54852 …s:RW DataWidth:0xe // Tail pointer of each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
54854 …ccess:RW DataWidth:0xe // Number of free blocks in each one of 4 free lists::s/BLK_WDTH/13/g …
54856 …MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_REQ/required/g in R…
54857 …till reset in a case of length error other way it will continue to work as usual.::s/STOP_LEN_ERR_…
54858 …- SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for…
54861 …s. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/TOTAL_MAC_RST/240…
54864 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54865 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54866 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54867 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54868 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54869 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54870 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54871 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54872 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54873 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54874 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54875 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54876 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54877 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54878 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54879 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54880 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54881 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54882 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54883 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
54884 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54885 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54886 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54887 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54888 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54889 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54890 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54891 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54892 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54893 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54894 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54895 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54896 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54897 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54898 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54899 …in each main port.Reset value is right for 128B block size only. It should be twice smaller for 25…
54900 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54901 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54902 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54903 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54904 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54905 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54906 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54907 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54908 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54909 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54910 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54911 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54912 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54913 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54914 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54915 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54916 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54917 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54918 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54919 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
54920 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54921 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54922 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54923 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54924 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54925 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54926 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54927 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54928 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54929 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54930 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54931 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54932 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54933 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54934 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54935 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54936 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54937 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54938 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54939 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54940 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54941 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54942 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54943 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54944 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54945 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54946 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54947 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54948 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54949 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54950 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54951 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54952 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54953 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54954 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54955 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
54956 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54957 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54958 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54959 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54960 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54961 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54962 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54963 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54964 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54965 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54966 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54967 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54968 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54969 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54970 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54971 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54972 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54973 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54974 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54975 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54976 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54977 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54978 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54979 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54980 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54981 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54982 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54983 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54984 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54985 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54986 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54987 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54988 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54989 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54990 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54991 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
54992 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54993 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54994 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54995 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54996 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54997 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54998 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
54999 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55000 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55001 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55002 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55003 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55004 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55005 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55006 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55007 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55008 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55009 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55010 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55011 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55012 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55013 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55014 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55015 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55016 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55017 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55018 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55019 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55020 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55021 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55022 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55023 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55024 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55025 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55026 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55027 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
55028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55033 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55034 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55035 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55036 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55037 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55038 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55039 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55040 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55041 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55042 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55043 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55044 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55045 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55046 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55047 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55048 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55049 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55050 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55051 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55052 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55053 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55054 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55055 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55056 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55057 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55058 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55059 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55060 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55061 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55062 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55063 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55064 …in each TC after asserting pause upper whih full to that TC or interrupt will be asserted dependin…
55065 …n number of allocated blocks in TC bigger lossless_threshold, if 0 - then full to that TC will be…
55066 …which EMPTY[0] is asserted for this MAC port::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Exista…
55067 …which EMPTY[1] is asserted for this MAC port::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Exista…
55068 …rsing interface is asserted::s/BLK_NUM/4800/g in Reset Value::s/BLK_WDTH/13/g in Data Width::/PAUS…
55069 …rface is asserted::s/BLK_WDTH_PLUS_7/20/g in Data Width::s/BYTE_CNT_RST/614400/g in Reset Value::/…
55070 …-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE_RST/1/g in Reset Value::s/NO_DEAD_CYCLE_DS…
55072 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
55074 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
55076 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
55078 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
55080 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
55082 …ritten without intra packet dead cycles .B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE…
55083 …is enabled for the corresponding client. B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE…
55084 …ad client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_SOP_PRI_RST/5/g…
55085 …G RAM arbiters. Possible values are 0-7. Priority 7 is highest::s/RC_EOP_PRI_RST/4/g in Reset Valu…
55086 …ient group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7/g…
55087 …ntical priority is supported. Possible values are 1-3. Priority 3 is highest::s/RC_MULT_PRI_RST/6/…
55094 …ient upper which full outputs to this write client interface.::s/DSCR_FIFO_RST/12/g in Reset Value.
55095 …ient upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.
55097 …d to power management block::s/BLK_NUM/4800/g in Reset Value::s/BLK_WDTH/13/g in Data Width::/EMPT…
55098 …_mac_n is asserted to power management block::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Exista…
55099 …ger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g i…
55100 …ger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g i…
55101 …ger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g i…
55102 …ger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g i…
55103 …dth:0x4 // Debug only: If more than this Number of entries are occupied in the dbgsyn clock syn…
55107 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
55116 …-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When…
55118 …- IF0, B1- IF1. When bit is set then appropriate interface is enabled. When bit is reset then requ…
55122 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
55125 …-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When…
55127 …- IF0, B1- IF1. When bit is set then appropriate interface is enabled.When bit is reset then valid…
55131 …fter init procedure. ::s/SHARE_GRP_CNT/2/g in Data Width::s/SHARE_GRP_INIT/3/g in Reset Value::/PA…
55133 …nit procedure. ::s/MAX_SHARE_GRP_CNT/2/g in Data Width::s/MAX_SHARE_GRP_INIT/3/g in Reset Value::/…
55137 …erface will never be set. This bit should be set after init procedure. ::/PAUSE_EN/d in Existance.
55139 …erface will never be set. This bit should be set after init procedure. ::/EMPTY_EN/d in Existance.
55141 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55142 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55143 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55144 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55145 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55146 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55147 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55148 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55149 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55150 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55151 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55152 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55153 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55154 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55155 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55156 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55157 …ch write client because of temporal bandwidth problem on interface::s/WC_NUM_MAX/4/g in Data Width.
55158 …/ Debug register. Full status of each read packet client interface::s/PKT_RC_NUM/5/g in Data Width.
55159 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
55160 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
55161 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
55162 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
55163 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
55164 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
55165 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
55166 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
55167 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
55168 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
55169 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55170 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55171 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55172 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55173 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55174 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55175 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55176 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
55177 …tatus of input FIFO for EOP client 1[1]::s/SHARE_GRP_CNT/2/g in Data Width::/EOP_RC_EN/d in Exista…
55178 …tatus of input FIFO for EOP client 1[1]::s/SHARE_GRP_CNT/2/g in Data Width::/EOP_RC_EN/d in Exista…
55179 … of input FIFO for EOP client 1[6:3]::s/RC_EOP_STAT_WDTH/6/g in Data Width::/EOP_RC_EN/d in Exista…
55183 …egister. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Exista…
55184 …egister. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Exista…
55185 …egister. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Exista…
55186 …egister. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Exista…
55206 …er is used for stop parsing interface logic.::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Exista…
55207 …sed for stop parsing interface logic.::s/BLK_WDTH_PLUS_7/20/g in Data Width::/PAUSE_EN/d in Exista…
55208 …/ Debug register. This is state machine for each read client. ::s/PKT_RC_NUM_ST/20/g in Data Width.
55209 … areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g …
55210 … areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g …
55211 … areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g …
55212 … areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g …
55213 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55214 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55215 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55216 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55217 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55218 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55219 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55220 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55221 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55222 …of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55223 …of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55224 …of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55225 …of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55226 …of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55227 …of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55228 …of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55229 …of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55230 …of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55231 …of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55232 …of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55233 …of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55234 …of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55235 …of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55236 …of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55237 …of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55238 …of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55239 …of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55240 …of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
55241 …valid. ::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g …
55242 …valid. ::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g …
55243 …valid. ::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g …
55244 …valid. ::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g …
55245 … pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g …
55246 … pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g …
55247 … pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g …
55248 … pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g …
55249 …put pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in…
55250 …put pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in…
55251 …put pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in…
55252 …put pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in…
55253 …t full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g …
55254 …t full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g …
55255 …t full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g …
55256 …t full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g …
55257 …tput full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in…
55258 …tput full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in…
55259 …tput full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in…
55260 …tput full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in…
55261 …or each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55262 …or each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55263 …or each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55264 …or each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55265 …or each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55266 …or each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55267 …or each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55268 …or each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55269 …or each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55270 …or each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55271 …or each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55272 …or each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55273 …or each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55274 …or each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55275 …or each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55276 …or each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55277 …or each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55278 …or each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55279 …or each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55280 …or each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55281 …or each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55282 …or each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55283 …or each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55284 …or each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE…
55285 …ch TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAU…
55286 …ch TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAU…
55287 …ch TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAU…
55288 …ch TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAU…
55289 …is written in big_ram_address register. Read from 32 LSB bits of this register will generate read …
55291 …- valid; b30:16 - queue size; b15:0 - queue start pointer::s/SOP_STATUS_RST/536805376/g in Reset V…
55294 …ister for each erad packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelli…
55296 …ister for each read packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelli…
55298 …-port per-TC counters. In BigBear, entries 0-7 are port 0 (main 0) TCs 0-7. Entries 8-16 are port …
55301 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55303 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55305 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55307 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55309 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55311 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55313 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55315 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55330 …ry that contains per-block descriptor::s/BLK_NUM/4800/g in memory size::s/BLK_WDTH_PLUS_SOP_EN/14/…
55331 …ry that contains per-block descriptor::s/BLK_NUM/4800/g in memory size::s/BLK_WDTH_PLUS_SOP_EN/14/…
55337 …h:0x2 // Initial credit for the PCI interface::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
55338 …64 slots of 64 bytes; 7=64/128 slots of 32 bytes::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
55346 …e segment messages can be mapped::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/…
55365 … //Access:R DataWidth:0x20 // Logging in case of minicache failure.bits 31:0 CID Valid only i…
55366 … //Access:R DataWidth:0x20 // Logging in case of minicache failure.bits 31:0 TID Valid only i…
55367 … //Access:R DataWidth:0xe // Logging in case of minicache failure.bits 12:0 CID load respons…
55368 … //Access:R DataWidth:0xe // Logging in case of minicache failure.bits 12:0 TID load respons…
55370 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55371 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55372 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55373 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55374 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55375 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55376 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55377 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55378 …0x4c00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55379 …0x4c00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55380 …0x4c00bcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55381 …0x4c00c0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55383 …ge error: bits 3:0 - header len; bits 7:4 - number of iteration::/MULD_DISCARD/d in MULD::/TMLD_DI…
55384 … error: bits 31:0 - bits 31:0 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_…
55385 …error: bits 31:0 - bits 63:32 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_…
55386 …error: bits 31:0 - bits 95:64 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_…
55387 …nables logging new error details::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/…
55388 …g_msg logging registers is valid::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/…
55392 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55401 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55403 … (0x1<<3) // Mini cache error - meaning that A load …
55405 … (0x1<<4) // Mini cache error - meaning that A load …
55427 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55429 … (0x1<<3) // Mini cache error - meaning that A load …
55431 … (0x1<<4) // Mini cache error - meaning that A load …
55440 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55442 … (0x1<<3) // Mini cache error - meaning that A load …
55444 … (0x1<<4) // Mini cache error - meaning that A load …
55494 … (0x1<<0) // Enable ECC for memory ecc instance xyld.i_msgq_ram.i_ecc in module xyld_i_msgq_r…
55496 …x1<<1) // Enable ECC for memory ecc instance xyld.i_pci_rsep_buf_ram.i_ecc in module xyld_i_pci_rs…
55498 … (0x1<<0) // Enable ECC for memory ecc instance xyld.i_msgq_ram.i_ecc in module xyld_i_msgq_r…
55500 …x1<<1) // Enable ECC for memory ecc instance xyld.i_pci_rsep_buf_ram.i_ecc in module xyld_i_pci_rs…
55503 … (0x1<<0) // Set parity only for memory ecc instance xyld.i_msgq_ram.i_ecc in module xyld_i_msgq_r…
55505 …) // Set parity only for memory ecc instance xyld.i_pci_rsep_buf_ram.i_ecc in module xyld_i_pci_rs…
55507 … (0x1<<0) // Set parity only for memory ecc instance xyld.i_msgq_ram.i_ecc in module xyld_i_msgq_r…
55509 …) // Set parity only for memory ecc instance xyld.i_pci_rsep_buf_ram.i_ecc in module xyld_i_pci_rs…
55512 … a correctable error occurred on memory ecc instance xyld.i_msgq_ram.i_ecc in module xyld_i_msgq_r…
55514 …ctable error occurred on memory ecc instance xyld.i_pci_rsep_buf_ram.i_ecc in module xyld_i_pci_rs…
55516 … a correctable error occurred on memory ecc instance xyld.i_msgq_ram.i_ecc in module xyld_i_msgq_r…
55518 …ctable error occurred on memory ecc instance xyld.i_pci_rsep_buf_ram.i_ecc in module xyld_i_pci_rs…
55521 … 0x4c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55523 … 0x4c0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55528 …in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this config…
55530 … (0x1<<2) // defines that only back-to-back aggregation is …
55539 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
55541 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
55543 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
55545 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
55547 …0x4c0908UL //Access:RW DataWidth:0x10 // Limit the number of �packets� in the Loader according…
55549 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
55551 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
55553 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
55555 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
55558 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
55560 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
55562 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
55564 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
55567 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
55569 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
55571 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
55573 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
55576 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
55578 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
55580 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
55582 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
55585 … (0xf<<0) // length in 32b units from the s…
55587 … (0xf<<4) // length in 32b units from the s…
55589 … (0xf<<8) // length in 32b units from the s…
55591 … (0xf<<12) // length in 32b units from the s…
55593 … (0xf<<16) // length in 32b units from the s…
55595 … (0xf<<20) // length in 32b units from the s…
55597 … (0xf<<24) // length in 32b units from the s…
55599 … (0xf<<28) // length in 32b units from the s…
55602 … (0xf<<0) // length in 32b units from the s…
55604 … (0xf<<4) // length in 32b units from the s…
55606 … (0xf<<8) // length in 32b units from the s…
55608 … (0xf<<12) // length in 32b units from the s…
55610 … (0xf<<16) // length in 32b units from the s…
55612 … (0xf<<20) // length in 32b units from the s…
55614 … (0xf<<24) // length in 32b units from the s…
55616 … (0xf<<28) // length in 32b units from the s…
55618 … 0x4c0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55619 … 0x4c0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55620 … 0x4c092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55621 … 0x4c0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55622 … 0x4c0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55623 … 0x4c0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55624 … 0x4c093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55625 … 0x4c0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55626 … 0x4c0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55627 … 0x4c0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55628 … 0x4c094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55629 … 0x4c0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55630 … 0x4c0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55631 … 0x4c0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55632 … 0x4c095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55633 … 0x4c0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55634 … 0x4c0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55635 … 0x4c0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55636 … 0x4c096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55637 … 0x4c0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55638 … 0x4c0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55639 … 0x4c0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55640 … 0x4c097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55641 … 0x4c0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55642 … 0x4c0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55643 … 0x4c0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55644 … 0x4c098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55645 … 0x4c0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55646 … 0x4c0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55647 … 0x4c0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55648 … 0x4c099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55649 … 0x4c09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55651 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
55653 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
55655 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
55657 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
55660 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
55662 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
55664 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
55666 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
55669 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
55671 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
55673 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
55675 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
55678 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
55680 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
55682 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
55684 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
55687 … (0x3f<<0) // length in 32b units from the d…
55689 … (0x3f<<6) // length in 32b units from the d…
55691 … (0x3f<<12) // length in 32b units from the d…
55693 … (0x3f<<18) // length in 32b units from the d…
55696 … (0x3f<<0) // length in 32b units from the d…
55698 … (0x3f<<6) // length in 32b units from the d…
55700 … (0x3f<<12) // length in 32b units from the d…
55702 … (0x3f<<18) // length in 32b units from the d…
55705 … (0x3f<<0) // length in 32b units from the d…
55707 … (0x3f<<6) // length in 32b units from the d…
55709 … (0x3f<<12) // length in 32b units from the d…
55711 … (0x3f<<18) // length in 32b units from the d…
55714 … (0x3f<<0) // length in 32b units from the d…
55716 … (0x3f<<6) // length in 32b units from the d…
55718 … (0x3f<<12) // length in 32b units from the d…
55720 … (0x3f<<18) // length in 32b units from the d…
55723 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
55725 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
55727 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
55729 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
55731 … (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
55733 … (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
55735 … (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
55737 … (0x1f<<19) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
55740 … (0xff<<0) // offset in 32b units from the beginning of the message…
55742 … (0xff<<8) // offset in 32b units from the beginning of the message…
55744 … (0xff<<16) // offset in 32b units from the beginning of the message…
55746 … (0xff<<24) // offset in 32b units from the beginning of the message…
55749 … (0xf<<0) // the maximal number of children in a specific aggregati…
55751 … (0xf<<4) // the maximal number of children in a specific aggregati…
55753 … (0xf<<8) // the maximal number of children in a specific aggregati…
55755 … (0xf<<12) // the maximal number of children in a specific aggregati…
55758 … (0xff<<0) // The value by which to increment the event-ID in case of successful…
55760 … (0xff<<8) // The value by which to increment the event-ID in case of successful…
55762 … (0xff<<16) // The value by which to increment the event-ID in case of successful…
55764 … (0xff<<24) // The value by which to increment the event-ID in case of successful…
55766 … 0x4c09d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
55767 …ss:RW DataWidth:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is rese…
55768 …ss:RW DataWidth:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is rese…
55769 …ss:RW DataWidth:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit is rese…
55770 …ss:RW DataWidth:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit is rese…
55771 …RR arbiteration, in case its bit is reset at scbd_strict_prio reg::/TMLD_DISCARD/d in TMLD::/XYLD_…
55772 …RR arbiteration, in case its bit is reset at scbd_strict_prio reg::/TMLD_DISCARD/d in TMLD::/XYLD_…
55774 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
55787 …ss:RW DataWidth:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is rese…
55788 …ss:RW DataWidth:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit is rese…
55811 … //Access:R DataWidth:0x20 // Logging in case of minicache failure.bits 31:0 CID Valid only i…
55812 … //Access:R DataWidth:0x20 // Logging in case of minicache failure.bits 31:0 TID Valid only i…
55813 … //Access:R DataWidth:0xe // Logging in case of minicache failure.bits 12:0 CID load respons…
55814 … //Access:R DataWidth:0xe // Logging in case of minicache failure.bits 12:0 TID load respons…
55816 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55817 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55818 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55819 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55820 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55821 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55822 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55823 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55824 …0x4c8098UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55825 …0x4c809cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55826 …0x4c80a0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55827 …0x4c80a4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55832 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55841 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55843 … (0x1<<3) // Mini cache error - meaning that A load …
55845 … (0x1<<4) // Mini cache error - meaning that A load …
55867 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55869 … (0x1<<3) // Mini cache error - meaning that A load …
55871 … (0x1<<4) // Mini cache error - meaning that A load …
55880 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55882 … (0x1<<3) // Mini cache error - meaning that A load …
55884 … (0x1<<4) // Mini cache error - meaning that A load …
55902 … 0x4c8400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55904 … 0x4c8800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55907 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
55925 … size would be the BRB-response-buffer-size/number-of-slots.::/MULD_DISCARD/d in MULD::/XYLD_DISCA…
55928 …ta returning from the BRB is swapped. meaning that bytes 0-3 is swapped with bytes 4-7 in ea…
55929 …redit number for the BRB request-resonse interface::/MULD_DISCARD/d in MULD::/XYLD_DISCARD/d in XY…
55947 … //Access:R DataWidth:0x20 // Logging in case of minicache failure.bits 31:0 CID Valid only i…
55948 … //Access:R DataWidth:0x20 // Logging in case of minicache failure.bits 31:0 TID Valid only i…
55949 … //Access:R DataWidth:0xe // Logging in case of minicache failure.bits 12:0 CID load respons…
55950 … //Access:R DataWidth:0xe // Logging in case of minicache failure.bits 12:0 TID load respons…
55952 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55953 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55954 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55955 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55956 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55957 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55958 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55959 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55960 …0x4d00acUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55961 …0x4d00b0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55962 …0x4d00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55963 …0x4d00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55968 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55977 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55979 … (0x1<<3) // Mini cache error - meaning that A load …
55981 … (0x1<<4) // Mini cache error - meaning that A load …
56003 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56005 … (0x1<<3) // Mini cache error - meaning that A load …
56007 … (0x1<<4) // Mini cache error - meaning that A load …
56016 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56018 … (0x1<<3) // Mini cache error - meaning that A load …
56020 … (0x1<<4) // Mini cache error - meaning that A load …
56062 … (0x1<<0) // Enable ECC for memory ecc instance tmld.i_msgq_ram.i_ecc in module tmld_i_msgq_r…
56064 …x1<<1) // Enable ECC for memory ecc instance tmld.i_brb_resp_buf_ram.i_ecc in module tmld_i_brb_re…
56066 … (0x1<<0) // Enable ECC for memory ecc instance tmld.i_msgq_ram.i_ecc in module tmld_i_msgq_r…
56069 … (0x1<<0) // Set parity only for memory ecc instance tmld.i_msgq_ram.i_ecc in module tmld_i_msgq_r…
56071 …) // Set parity only for memory ecc instance tmld.i_brb_resp_buf_ram.i_ecc in module tmld_i_brb_re…
56073 … (0x1<<0) // Set parity only for memory ecc instance tmld.i_msgq_ram.i_ecc in module tmld_i_msgq_r…
56076 … a correctable error occurred on memory ecc instance tmld.i_msgq_ram.i_ecc in module tmld_i_msgq_r…
56078 …ctable error occurred on memory ecc instance tmld.i_brb_resp_buf_ram.i_ecc in module tmld_i_brb_re…
56080 … a correctable error occurred on memory ecc instance tmld.i_msgq_ram.i_ecc in module tmld_i_msgq_r…
56083 … 0x4d0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56085 … 0x4d0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56090 …in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this config…
56092 … (0x1<<2) // defines that only back-to-back aggregation is …
56101 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
56103 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
56105 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
56107 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
56109 …0x4d0908UL //Access:RW DataWidth:0x10 // Limit the number of �packets� in the Loader according…
56111 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
56113 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
56115 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
56117 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
56120 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
56122 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
56124 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
56126 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
56129 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
56131 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
56133 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
56135 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
56138 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
56140 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
56142 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
56144 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
56147 … (0xf<<0) // length in 32b units from the s…
56149 … (0xf<<4) // length in 32b units from the s…
56151 … (0xf<<8) // length in 32b units from the s…
56153 … (0xf<<12) // length in 32b units from the s…
56155 … (0xf<<16) // length in 32b units from the s…
56157 … (0xf<<20) // length in 32b units from the s…
56159 … (0xf<<24) // length in 32b units from the s…
56161 … (0xf<<28) // length in 32b units from the s…
56164 … (0xf<<0) // length in 32b units from the s…
56166 … (0xf<<4) // length in 32b units from the s…
56168 … (0xf<<8) // length in 32b units from the s…
56170 … (0xf<<12) // length in 32b units from the s…
56172 … (0xf<<16) // length in 32b units from the s…
56174 … (0xf<<20) // length in 32b units from the s…
56176 … (0xf<<24) // length in 32b units from the s…
56178 … (0xf<<28) // length in 32b units from the s…
56180 … 0x4d0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56181 … 0x4d0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56182 … 0x4d092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56183 … 0x4d0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56184 … 0x4d0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56185 … 0x4d0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56186 … 0x4d093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56187 … 0x4d0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56188 … 0x4d0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56189 … 0x4d0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56190 … 0x4d094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56191 … 0x4d0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56192 … 0x4d0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56193 … 0x4d0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56194 … 0x4d095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56195 … 0x4d0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56196 … 0x4d0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56197 … 0x4d0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56198 … 0x4d096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56199 … 0x4d0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56200 … 0x4d0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56201 … 0x4d0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56202 … 0x4d097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56203 … 0x4d0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56204 … 0x4d0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56205 … 0x4d0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56206 … 0x4d098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56207 … 0x4d0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56208 … 0x4d0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56209 … 0x4d0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56210 … 0x4d099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56211 … 0x4d09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56213 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
56215 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
56217 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
56219 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
56222 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
56224 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
56226 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
56228 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
56231 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
56233 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
56235 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
56237 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
56240 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
56242 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
56244 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
56246 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
56249 … (0x3f<<0) // length in 32b units from the d…
56251 … (0x3f<<6) // length in 32b units from the d…
56253 … (0x3f<<12) // length in 32b units from the d…
56255 … (0x3f<<18) // length in 32b units from the d…
56258 … (0x3f<<0) // length in 32b units from the d…
56260 … (0x3f<<6) // length in 32b units from the d…
56262 … (0x3f<<12) // length in 32b units from the d…
56264 … (0x3f<<18) // length in 32b units from the d…
56267 … (0x3f<<0) // length in 32b units from the d…
56269 … (0x3f<<6) // length in 32b units from the d…
56271 … (0x3f<<12) // length in 32b units from the d…
56273 … (0x3f<<18) // length in 32b units from the d…
56276 … (0x3f<<0) // length in 32b units from the d…
56278 … (0x3f<<6) // length in 32b units from the d…
56280 … (0x3f<<12) // length in 32b units from the d…
56282 … (0x3f<<18) // length in 32b units from the d…
56285 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
56287 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
56289 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
56291 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
56293 … (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
56295 … (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
56297 … (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
56299 … (0x1f<<19) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
56302 … (0xff<<0) // offset in 32b units from the beginning of the message…
56304 … (0xff<<8) // offset in 32b units from the beginning of the message…
56306 … (0xff<<16) // offset in 32b units from the beginning of the message…
56308 … (0xff<<24) // offset in 32b units from the beginning of the message…
56311 … (0xf<<0) // the maximal number of children in a specific aggregati…
56313 … (0xf<<4) // the maximal number of children in a specific aggregati…
56315 … (0xf<<8) // the maximal number of children in a specific aggregati…
56317 … (0xf<<12) // the maximal number of children in a specific aggregati…
56320 … (0xff<<0) // The value by which to increment the event-ID in case of successful…
56322 … (0xff<<8) // The value by which to increment the event-ID in case of successful…
56324 … (0xff<<16) // The value by which to increment the event-ID in case of successful…
56326 … (0xff<<24) // The value by which to increment the event-ID in case of successful…
56328 … 0x4d09d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
56329 …ss:RW DataWidth:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is rese…
56330 …ss:RW DataWidth:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is rese…
56331 …ss:RW DataWidth:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit is rese…
56332 …ss:RW DataWidth:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit is rese…
56333 …RR arbiteration, in case its bit is reset at scbd_strict_prio reg::/TMLD_DISCARD/d in TMLD::/XYLD_…
56334 …RR arbiteration, in case its bit is reset at scbd_strict_prio reg::/TMLD_DISCARD/d in TMLD::/XYLD_…
56336 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
56349 …ss:RW DataWidth:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is rese…
56350 …ss:RW DataWidth:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit is rese…
56351 …RR arbiteration, in case its bit is reset at scbd_strict_prio reg::/TMLD_DISCARD/d in TMLD::/XYLD_…
56352 …RR arbiteration, in case its bit is reset at scbd_strict_prio reg::/TMLD_DISCARD/d in TMLD::/XYLD_…
56353 …ze in bytes - 2:BD size is 4bytes; 3:BD size is 8bytes; 4:BD size is 16bytes etc::/TMLD_DISCARD/d …
56354 …ven page of the next page's address (in bytes)::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::…
56355 … in bytes - 2:SGE size is 4bytes; 3:SGE size is 8bytes; 4:SGE size is 16bytes etc::/TMLD_DISCARD/d…
56356 …ven page of the next page's address (in bytes)::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::…
56358 …h:0x2 // Initial credit for the PCI interface::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
56359 …64 slots of 64 bytes; 7=64/128 slots of 32 bytes::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
56387 … //Access:R DataWidth:0x20 // Logging in case of minicache failure.bits 31:0 CID Valid only i…
56388 … //Access:R DataWidth:0x20 // Logging in case of minicache failure.bits 31:0 TID Valid only i…
56389 … //Access:R DataWidth:0xe // Logging in case of minicache failure.bits 12:0 CID load respons…
56390 … //Access:R DataWidth:0xe // Logging in case of minicache failure.bits 12:0 TID load respons…
56392 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56393 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56394 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56395 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56396 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56397 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56398 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56399 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56400 …0x4e00d0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56401 …0x4e00d4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56402 …0x4e00d8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56403 …0x4e00dcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56408 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
56417 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56419 … (0x1<<3) // Mini cache error - meaning that A load …
56421 … (0x1<<4) // Mini cache error - meaning that A load …
56443 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56445 … (0x1<<3) // Mini cache error - meaning that A load …
56447 … (0x1<<4) // Mini cache error - meaning that A load …
56456 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56458 … (0x1<<3) // Mini cache error - meaning that A load …
56460 … (0x1<<4) // Mini cache error - meaning that A load …
56512 … (0x1<<0) // Enable ECC for memory ecc instance muld.i_msgq_ram.i_ecc in module muld_i_msgq_r…
56514 … (0x1<<1) // Enable ECC for memory ecc instance muld.i_bd_db_ram.i_ecc in module muld_i_bd_db_…
56516 … (0x1<<2) // Enable ECC for memory ecc instance muld.i_sge_db_ram.i_ecc in module muld_i_sge_db…
56518 …x1<<3) // Enable ECC for memory ecc instance muld.i_pci_rsep_buf_ram.i_ecc in module muld_i_pci_rs…
56520 … (0x1<<0) // Enable ECC for memory ecc instance muld.i_msgq_ram.i_ecc in module muld_i_msgq_r…
56522 … (0x1<<2) // Enable ECC for memory ecc instance muld.i_sge_db_ram.i_ecc in module muld_i_sge_db…
56524 …x1<<3) // Enable ECC for memory ecc instance muld.i_pci_rsep_buf_ram.i_ecc in module muld_i_pci_rs…
56527 … (0x1<<0) // Set parity only for memory ecc instance muld.i_msgq_ram.i_ecc in module muld_i_msgq_r…
56529 …(0x1<<1) // Set parity only for memory ecc instance muld.i_bd_db_ram.i_ecc in module muld_i_bd_db_…
56531 …0x1<<2) // Set parity only for memory ecc instance muld.i_sge_db_ram.i_ecc in module muld_i_sge_db…
56533 …) // Set parity only for memory ecc instance muld.i_pci_rsep_buf_ram.i_ecc in module muld_i_pci_rs…
56535 … (0x1<<0) // Set parity only for memory ecc instance muld.i_msgq_ram.i_ecc in module muld_i_msgq_r…
56537 …0x1<<2) // Set parity only for memory ecc instance muld.i_sge_db_ram.i_ecc in module muld_i_sge_db…
56539 …) // Set parity only for memory ecc instance muld.i_pci_rsep_buf_ram.i_ecc in module muld_i_pci_rs…
56542 … a correctable error occurred on memory ecc instance muld.i_msgq_ram.i_ecc in module muld_i_msgq_r…
56544 …a correctable error occurred on memory ecc instance muld.i_bd_db_ram.i_ecc in module muld_i_bd_db_…
56546 … correctable error occurred on memory ecc instance muld.i_sge_db_ram.i_ecc in module muld_i_sge_db…
56548 …ctable error occurred on memory ecc instance muld.i_pci_rsep_buf_ram.i_ecc in module muld_i_pci_rs…
56550 … a correctable error occurred on memory ecc instance muld.i_msgq_ram.i_ecc in module muld_i_msgq_r…
56552 … correctable error occurred on memory ecc instance muld.i_sge_db_ram.i_ecc in module muld_i_sge_db…
56554 …ctable error occurred on memory ecc instance muld.i_pci_rsep_buf_ram.i_ecc in module muld_i_pci_rs…
56557 … 0x4e0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56559 … 0x4e0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56561 …:0x23 // Descriptor FIFO queue2 - Debug access::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD…
56563 …:0x23 // Descriptor FIFO queue3 - Debug access::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD…
56568 …in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this config…
56570 … (0x1<<2) // defines that only back-to-back aggregation is …
56579 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
56581 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
56583 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
56585 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
56587 …0x4e1408UL //Access:RW DataWidth:0x10 // Limit the number of �packets� in the Loader according…
56589 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
56591 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
56593 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
56595 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
56598 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
56600 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
56602 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
56604 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
56607 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
56609 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
56611 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
56613 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
56616 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
56618 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
56620 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
56622 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
56625 … (0xf<<0) // length in 32b units from the s…
56627 … (0xf<<4) // length in 32b units from the s…
56629 … (0xf<<8) // length in 32b units from the s…
56631 … (0xf<<12) // length in 32b units from the s…
56633 … (0xf<<16) // length in 32b units from the s…
56635 … (0xf<<20) // length in 32b units from the s…
56637 … (0xf<<24) // length in 32b units from the s…
56639 … (0xf<<28) // length in 32b units from the s…
56642 … (0xf<<0) // length in 32b units from the s…
56644 … (0xf<<4) // length in 32b units from the s…
56646 … (0xf<<8) // length in 32b units from the s…
56648 … (0xf<<12) // length in 32b units from the s…
56650 … (0xf<<16) // length in 32b units from the s…
56652 … (0xf<<20) // length in 32b units from the s…
56654 … (0xf<<24) // length in 32b units from the s…
56656 … (0xf<<28) // length in 32b units from the s…
56658 … 0x4e1424UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56659 … 0x4e1428UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56660 … 0x4e142cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56661 … 0x4e1430UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56662 … 0x4e1434UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56663 … 0x4e1438UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56664 … 0x4e143cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56665 … 0x4e1440UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56666 … 0x4e1444UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56667 … 0x4e1448UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56668 … 0x4e144cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56669 … 0x4e1450UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56670 … 0x4e1454UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56671 … 0x4e1458UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56672 … 0x4e145cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56673 … 0x4e1460UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56674 … 0x4e1464UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56675 … 0x4e1468UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56676 … 0x4e146cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56677 … 0x4e1470UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56678 … 0x4e1474UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56679 … 0x4e1478UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56680 … 0x4e147cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56681 … 0x4e1480UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56682 … 0x4e1484UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56683 … 0x4e1488UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56684 … 0x4e148cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56685 … 0x4e1490UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56686 … 0x4e1494UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56687 … 0x4e1498UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56688 … 0x4e149cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56689 … 0x4e14a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56691 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
56693 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
56695 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
56697 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
56700 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
56702 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
56704 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
56706 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
56709 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
56711 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
56713 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
56715 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
56718 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
56720 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
56722 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
56724 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
56727 … (0x3f<<0) // length in 32b units from the d…
56729 … (0x3f<<6) // length in 32b units from the d…
56731 … (0x3f<<12) // length in 32b units from the d…
56733 … (0x3f<<18) // length in 32b units from the d…
56736 … (0x3f<<0) // length in 32b units from the d…
56738 … (0x3f<<6) // length in 32b units from the d…
56740 … (0x3f<<12) // length in 32b units from the d…
56742 … (0x3f<<18) // length in 32b units from the d…
56745 … (0x3f<<0) // length in 32b units from the d…
56747 … (0x3f<<6) // length in 32b units from the d…
56749 … (0x3f<<12) // length in 32b units from the d…
56751 … (0x3f<<18) // length in 32b units from the d…
56754 … (0x3f<<0) // length in 32b units from the d…
56756 … (0x3f<<6) // length in 32b units from the d…
56758 … (0x3f<<12) // length in 32b units from the d…
56760 … (0x3f<<18) // length in 32b units from the d…
56763 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
56765 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
56767 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
56769 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
56771 … (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
56773 … (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
56775 … (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
56777 … (0x1f<<19) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
56780 … (0xff<<0) // offset in 32b units from the beginning of the message…
56782 … (0xff<<8) // offset in 32b units from the beginning of the message…
56784 … (0xff<<16) // offset in 32b units from the beginning of the message…
56786 … (0xff<<24) // offset in 32b units from the beginning of the message…
56789 … (0xf<<0) // the maximal number of children in a specific aggregati…
56791 … (0xf<<4) // the maximal number of children in a specific aggregati…
56793 … (0xf<<8) // the maximal number of children in a specific aggregati…
56795 … (0xf<<12) // the maximal number of children in a specific aggregati…
56798 … (0xff<<0) // The value by which to increment the event-ID in case of successful…
56800 … (0xff<<8) // The value by which to increment the event-ID in case of successful…
56802 … (0xff<<16) // The value by which to increment the event-ID in case of successful…
56804 … (0xff<<24) // The value by which to increment the event-ID in case of successful…
56806 … 0x4e14d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
56807 … 0x4e14d8UL //Access:RW DataWidth:0x20 // page size in bytes
56809 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
56819 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
56823 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
56832 … (0x1<<1) // FIFO error in debug traffic FIFO.
56834 … (0x1<<2) // FIFO error in DORQ FIFO.
56836 … (0x1<<3) // FIFO error in debug traffic sync F…
56838 … (0x1<<4) // FIFO error in DORQ sync FIFO.
56840 … (0x1<<5) // FIFO error in STORM sync FIFO.
56842 … (0x1<<6) // FIFO error in DBGMUX sync FIFO.
56844 … (0x1<<7) // FIFO error in MSDM sync FIFO.
56846 … (0x1<<8) // FIFO error in TSDM sync FIFO.
56848 … (0x1<<9) // FIFO error in USDM sync FIFO.
56850 … (0x1<<10) // FIFO error in XSDM sync FIFO.
56852 … (0x1<<11) // FIFO error in YSDM sync FIFO.
56854 … (0x1<<12) // FIFO error in Out of order RFIFO F…
56856 … (0x1<<13) // FIFO error in Out of order RFIFO F…
56890 … (0x1<<1) // FIFO error in debug traffic FIFO.
56892 … (0x1<<2) // FIFO error in DORQ FIFO.
56894 … (0x1<<3) // FIFO error in debug traffic sync F…
56896 …WR (0x1<<4) // FIFO error in DORQ sync FIFO.
56898 …WR (0x1<<5) // FIFO error in STORM sync FIFO.
56900 …WR (0x1<<6) // FIFO error in DBGMUX sync FIFO.
56902 …WR (0x1<<7) // FIFO error in MSDM sync FIFO.
56904 …WR (0x1<<8) // FIFO error in TSDM sync FIFO.
56906 …WR (0x1<<9) // FIFO error in USDM sync FIFO.
56908 …R (0x1<<10) // FIFO error in XSDM sync FIFO.
56910 …R (0x1<<11) // FIFO error in YSDM sync FIFO.
56912 … (0x1<<12) // FIFO error in Out of order RFIFO F…
56914 … (0x1<<13) // FIFO error in Out of order RFIFO F…
56919 … (0x1<<1) // FIFO error in debug traffic FIFO.
56921 …R (0x1<<2) // FIFO error in DORQ FIFO.
56923 … (0x1<<3) // FIFO error in debug traffic sync F…
56925 …_WR (0x1<<4) // FIFO error in DORQ sync FIFO.
56927 …_WR (0x1<<5) // FIFO error in STORM sync FIFO.
56929 …_WR (0x1<<6) // FIFO error in DBGMUX sync FIFO.
56931 …_WR (0x1<<7) // FIFO error in MSDM sync FIFO.
56933 …_WR (0x1<<8) // FIFO error in TSDM sync FIFO.
56935 …_WR (0x1<<9) // FIFO error in USDM sync FIFO.
56937 …WR (0x1<<10) // FIFO error in XSDM sync FIFO.
56939 …WR (0x1<<11) // FIFO error in YSDM sync FIFO.
56941 … (0x1<<12) // FIFO error in Out of order RFIFO F…
56943 … (0x1<<13) // FIFO error in Out of order RFIFO F…
56946 … (0x1<<0) // Error in the TX SOPQ.
56948 … (0x1<<1) // Error in the TX SOPQ.
56950 … (0x1<<2) // Error in the TX SOPQ.
56952 … (0x1<<3) // Error in the TX SOPQ.
56954 … (0x1<<4) // Error in the TX SOPQ.
56956 … (0x1<<5) // Error in the TX SOPQ.
56958 … (0x1<<6) // Error in the TX SOPQ.
56960 … (0x1<<7) // Error in the TX SOPQ.
56962 … (0x1<<8) // Error in the TX SOPQ.
56964 … (0x1<<9) // Error in the TX SOPQ.
56966 … (0x1<<10) // Error in the TX SOPQ.
56968 … (0x1<<11) // Error in the TX SOPQ.
56970 … (0x1<<12) // Error in the TX SOPQ.
56972 … (0x1<<13) // Error in the TX SOPQ.
56974 … (0x1<<14) // Error in the TX SOPQ.
56976 … (0x1<<15) // Error in the TX SOPQ.
56978 … (0x1<<16) // Error in the LB SOPQ.
56980 … (0x1<<17) // Error in the LB SOPQ.
56982 … (0x1<<18) // Error in the LB SOPQ.
56984 … (0x1<<19) // Error in the LB SOPQ.
56986 … (0x1<<20) // Error in the LB SOPQ.
56988 … (0x1<<21) // Error in the LB SOPQ.
56990 … (0x1<<22) // Error in the LB SOPQ.
56992 … (0x1<<23) // Error in the LB SOPQ.
56994 … (0x1<<24) // Error in the LB SOPQ.
56996 … (0x1<<25) // Error in the LB SOPQ.
56998 … (0x1<<26) // Error in the LB SOPQ.
57000 … (0x1<<27) // Error in the LB SOPQ.
57002 … (0x1<<28) // Error in the LB SOPQ.
57004 … (0x1<<29) // Error in the LB SOPQ.
57006 … (0x1<<30) // Error in the LB SOPQ.
57008 … (0x1<<31) // Error in the LB SOPQ.
57076 …OR (0x1<<0) // Error in the TX SOPQ.
57078 …OR (0x1<<1) // Error in the TX SOPQ.
57080 …OR (0x1<<2) // Error in the TX SOPQ.
57082 …OR (0x1<<3) // Error in the TX SOPQ.
57084 …OR (0x1<<4) // Error in the TX SOPQ.
57086 …OR (0x1<<5) // Error in the TX SOPQ.
57088 …OR (0x1<<6) // Error in the TX SOPQ.
57090 …OR (0x1<<7) // Error in the TX SOPQ.
57092 …OR (0x1<<8) // Error in the TX SOPQ.
57094 …OR (0x1<<9) // Error in the TX SOPQ.
57096 …OR (0x1<<10) // Error in the TX SOPQ.
57098 …OR (0x1<<11) // Error in the TX SOPQ.
57100 …OR (0x1<<12) // Error in the TX SOPQ.
57102 …OR (0x1<<13) // Error in the TX SOPQ.
57104 …OR (0x1<<14) // Error in the TX SOPQ.
57106 …OR (0x1<<15) // Error in the TX SOPQ.
57108 …R (0x1<<16) // Error in the LB SOPQ.
57110 …R (0x1<<17) // Error in the LB SOPQ.
57112 …R (0x1<<18) // Error in the LB SOPQ.
57114 …R (0x1<<19) // Error in the LB SOPQ.
57116 …R (0x1<<20) // Error in the LB SOPQ.
57118 …R (0x1<<21) // Error in the LB SOPQ.
57120 …R (0x1<<22) // Error in the LB SOPQ.
57122 …R (0x1<<23) // Error in the LB SOPQ.
57124 …R (0x1<<24) // Error in the LB SOPQ.
57126 …R (0x1<<25) // Error in the LB SOPQ.
57128 …OR (0x1<<26) // Error in the LB SOPQ.
57130 …OR (0x1<<27) // Error in the LB SOPQ.
57132 …OR (0x1<<28) // Error in the LB SOPQ.
57134 …OR (0x1<<29) // Error in the LB SOPQ.
57136 …OR (0x1<<30) // Error in the LB SOPQ.
57138 …OR (0x1<<31) // Error in the LB SOPQ.
57141 …ROR (0x1<<0) // Error in the TX SOPQ.
57143 …ROR (0x1<<1) // Error in the TX SOPQ.
57145 …ROR (0x1<<2) // Error in the TX SOPQ.
57147 …ROR (0x1<<3) // Error in the TX SOPQ.
57149 …ROR (0x1<<4) // Error in the TX SOPQ.
57151 …ROR (0x1<<5) // Error in the TX SOPQ.
57153 …ROR (0x1<<6) // Error in the TX SOPQ.
57155 …ROR (0x1<<7) // Error in the TX SOPQ.
57157 …ROR (0x1<<8) // Error in the TX SOPQ.
57159 …ROR (0x1<<9) // Error in the TX SOPQ.
57161 …ROR (0x1<<10) // Error in the TX SOPQ.
57163 …ROR (0x1<<11) // Error in the TX SOPQ.
57165 …ROR (0x1<<12) // Error in the TX SOPQ.
57167 …ROR (0x1<<13) // Error in the TX SOPQ.
57169 …ROR (0x1<<14) // Error in the TX SOPQ.
57171 …ROR (0x1<<15) // Error in the TX SOPQ.
57173 …OR (0x1<<16) // Error in the LB SOPQ.
57175 …OR (0x1<<17) // Error in the LB SOPQ.
57177 …OR (0x1<<18) // Error in the LB SOPQ.
57179 …OR (0x1<<19) // Error in the LB SOPQ.
57181 …OR (0x1<<20) // Error in the LB SOPQ.
57183 …OR (0x1<<21) // Error in the LB SOPQ.
57185 …OR (0x1<<22) // Error in the LB SOPQ.
57187 …OR (0x1<<23) // Error in the LB SOPQ.
57189 …OR (0x1<<24) // Error in the LB SOPQ.
57191 …OR (0x1<<25) // Error in the LB SOPQ.
57193 …ROR (0x1<<26) // Error in the LB SOPQ.
57195 …ROR (0x1<<27) // Error in the LB SOPQ.
57197 …ROR (0x1<<28) // Error in the LB SOPQ.
57199 …ROR (0x1<<29) // Error in the LB SOPQ.
57201 …ROR (0x1<<30) // Error in the LB SOPQ.
57203 …ROR (0x1<<31) // Error in the LB SOPQ.
57206 … (0x1<<0) // Error in the pure-loopback SOPQ.
57208 …RROR (0x1<<1) // Error in RX MAC FIFO.
57210 …RROR (0x1<<2) // Error in TX MAC FIFO.
57212 … (0x1<<3) // FIFO error in TX BMB FIFO.
57214 … (0x1<<4) // FIFO error in LB BMB FIFO.
57216 … (0x1<<5) // Error in BTB FIFO for TX path.
57218 … (0x1<<6) // Error in BTB FIFO for LB path.
57220 …RROR (0x1<<7) // Error in LLH Data FIFO.
57222 …RROR (0x1<<8) // Error in LLH Data FIFO.
57224 …RROR (0x1<<9) // Error in LLH Data FIFO.
57226 …R (0x1<<10) // Error in LLH Header FIFO.
57228 …R (0x1<<11) // Error in LLH Header FIFO.
57230 …R (0x1<<12) // Error in LLH Header FIFO.
57232 …R (0x1<<13) // Error in LLH Result FIFO.
57234 …R (0x1<<14) // Error in LLH Result FIFO.
57236 …R (0x1<<15) // Error in LLH Result FIFO.
57238 … (0x1<<16) // FIFO error in STORM message FIFO.
57240 … (0x1<<17) // FIFO error in STORM descriptor FIF…
57242 …ERROR (0x1<<18) // Error in grant FIFO.
57244 …ERROR (0x1<<19) // Error in grant FIFO.
57246 …ROR_E5 (0x1<<20) // Error in LLH order FIFO.
57248 …ROR_E5 (0x1<<21) // Error in LLH order FIFO.
57296 … (0x1<<0) // Error in the pure-loopback SOPQ.
57298 …O_ERROR (0x1<<1) // Error in RX MAC FIFO.
57300 …O_ERROR (0x1<<2) // Error in TX MAC FIFO.
57302 …ROR (0x1<<3) // FIFO error in TX BMB FIFO.
57304 …ROR (0x1<<4) // FIFO error in LB BMB FIFO.
57306 … (0x1<<5) // Error in BTB FIFO for TX path.
57308 … (0x1<<6) // Error in BTB FIFO for LB path.
57310 …O_ERROR (0x1<<7) // Error in LLH Data FIFO.
57312 …O_ERROR (0x1<<8) // Error in LLH Data FIFO.
57314 …O_ERROR (0x1<<9) // Error in LLH Data FIFO.
57316 …RROR (0x1<<10) // Error in LLH Header FIFO.
57318 …RROR (0x1<<11) // Error in LLH Header FIFO.
57320 …RROR (0x1<<12) // Error in LLH Header FIFO.
57322 …RROR (0x1<<13) // Error in LLH Result FIFO.
57324 …RROR (0x1<<14) // Error in LLH Result FIFO.
57326 …RROR (0x1<<15) // Error in LLH Result FIFO.
57328 … (0x1<<16) // FIFO error in STORM message FIFO.
57330 … (0x1<<17) // FIFO error in STORM descriptor FIF…
57332 …FO_ERROR (0x1<<18) // Error in grant FIFO.
57334 …FO_ERROR (0x1<<19) // Error in grant FIFO.
57336 …_ERROR_E5 (0x1<<20) // Error in LLH order FIFO.
57338 …_ERROR_E5 (0x1<<21) // Error in LLH order FIFO.
57341 … (0x1<<0) // Error in the pure-loopback SOPQ.
57343 …FO_ERROR (0x1<<1) // Error in RX MAC FIFO.
57345 …FO_ERROR (0x1<<2) // Error in TX MAC FIFO.
57347 …RROR (0x1<<3) // FIFO error in TX BMB FIFO.
57349 …RROR (0x1<<4) // FIFO error in LB BMB FIFO.
57351 … (0x1<<5) // Error in BTB FIFO for TX path.
57353 … (0x1<<6) // Error in BTB FIFO for LB path.
57355 …FO_ERROR (0x1<<7) // Error in LLH Data FIFO.
57357 …FO_ERROR (0x1<<8) // Error in LLH Data FIFO.
57359 …FO_ERROR (0x1<<9) // Error in LLH Data FIFO.
57361 …ERROR (0x1<<10) // Error in LLH Header FIFO.
57363 …ERROR (0x1<<11) // Error in LLH Header FIFO.
57365 …ERROR (0x1<<12) // Error in LLH Header FIFO.
57367 …ERROR (0x1<<13) // Error in LLH Result FIFO.
57369 …ERROR (0x1<<14) // Error in LLH Result FIFO.
57371 …ERROR (0x1<<15) // Error in LLH Result FIFO.
57373 … (0x1<<16) // FIFO error in STORM message FIFO.
57375 … (0x1<<17) // FIFO error in STORM descriptor FIF…
57377 …IFO_ERROR (0x1<<18) // Error in grant FIFO.
57379 …IFO_ERROR (0x1<<19) // Error in grant FIFO.
57381 …O_ERROR_E5 (0x1<<20) // Error in LLH order FIFO.
57383 …O_ERROR_E5 (0x1<<21) // Error in LLH order FIFO.
57534 … (0x1<<0) // Error in the pure-loopback SOPQ.
57536 …RROR (0x1<<1) // Error in RX MAC FIFO.
57538 …RROR (0x1<<2) // Error in TX MAC FIFO.
57540 … (0x1<<3) // FIFO error in TX BMB FIFO.
57542 … (0x1<<4) // FIFO error in LB BMB FIFO.
57544 … (0x1<<5) // Error in BTB FIFO for TX path.
57546 … (0x1<<6) // Error in BTB FIFO for LB path.
57548 …RROR (0x1<<7) // Error in LLH Data FIFO.
57550 …RROR (0x1<<8) // Error in LLH Data FIFO.
57552 …RROR (0x1<<9) // Error in LLH Data FIFO.
57554 …R (0x1<<10) // Error in LLH Header FIFO.
57556 …R (0x1<<11) // Error in LLH Header FIFO.
57558 …R (0x1<<12) // Error in LLH Header FIFO.
57560 …R (0x1<<13) // Error in LLH Result FIFO.
57562 …R (0x1<<14) // Error in LLH Result FIFO.
57564 …R (0x1<<15) // Error in LLH Result FIFO.
57566 … (0x1<<16) // FIFO error in STORM message FIFO.
57568 … (0x1<<17) // FIFO error in STORM descriptor FIF…
57570 …ERROR (0x1<<18) // Error in grant FIFO.
57572 …ERROR (0x1<<19) // Error in grant FIFO.
57574 …ROR_E5 (0x1<<20) // Error in LLH order FIFO.
57576 …ROR_E5 (0x1<<21) // Error in LLH order FIFO.
57624 … (0x1<<0) // Error in the pure-loopback SOPQ.
57626 …O_ERROR (0x1<<1) // Error in RX MAC FIFO.
57628 …O_ERROR (0x1<<2) // Error in TX MAC FIFO.
57630 …ROR (0x1<<3) // FIFO error in TX BMB FIFO.
57632 …ROR (0x1<<4) // FIFO error in LB BMB FIFO.
57634 … (0x1<<5) // Error in BTB FIFO for TX path.
57636 … (0x1<<6) // Error in BTB FIFO for LB path.
57638 …O_ERROR (0x1<<7) // Error in LLH Data FIFO.
57640 …O_ERROR (0x1<<8) // Error in LLH Data FIFO.
57642 …O_ERROR (0x1<<9) // Error in LLH Data FIFO.
57644 …RROR (0x1<<10) // Error in LLH Header FIFO.
57646 …RROR (0x1<<11) // Error in LLH Header FIFO.
57648 …RROR (0x1<<12) // Error in LLH Header FIFO.
57650 …RROR (0x1<<13) // Error in LLH Result FIFO.
57652 …RROR (0x1<<14) // Error in LLH Result FIFO.
57654 …RROR (0x1<<15) // Error in LLH Result FIFO.
57656 … (0x1<<16) // FIFO error in STORM message FIFO.
57658 … (0x1<<17) // FIFO error in STORM descriptor FIF…
57660 …FO_ERROR (0x1<<18) // Error in grant FIFO.
57662 …FO_ERROR (0x1<<19) // Error in grant FIFO.
57664 …_ERROR_E5 (0x1<<20) // Error in LLH order FIFO.
57666 …_ERROR_E5 (0x1<<21) // Error in LLH order FIFO.
57669 … (0x1<<0) // Error in the pure-loopback SOPQ.
57671 …FO_ERROR (0x1<<1) // Error in RX MAC FIFO.
57673 …FO_ERROR (0x1<<2) // Error in TX MAC FIFO.
57675 …RROR (0x1<<3) // FIFO error in TX BMB FIFO.
57677 …RROR (0x1<<4) // FIFO error in LB BMB FIFO.
57679 … (0x1<<5) // Error in BTB FIFO for TX path.
57681 … (0x1<<6) // Error in BTB FIFO for LB path.
57683 …FO_ERROR (0x1<<7) // Error in LLH Data FIFO.
57685 …FO_ERROR (0x1<<8) // Error in LLH Data FIFO.
57687 …FO_ERROR (0x1<<9) // Error in LLH Data FIFO.
57689 …ERROR (0x1<<10) // Error in LLH Header FIFO.
57691 …ERROR (0x1<<11) // Error in LLH Header FIFO.
57693 …ERROR (0x1<<12) // Error in LLH Header FIFO.
57695 …ERROR (0x1<<13) // Error in LLH Result FIFO.
57697 …ERROR (0x1<<14) // Error in LLH Result FIFO.
57699 …ERROR (0x1<<15) // Error in LLH Result FIFO.
57701 … (0x1<<16) // FIFO error in STORM message FIFO.
57703 … (0x1<<17) // FIFO error in STORM descriptor FIF…
57705 …IFO_ERROR (0x1<<18) // Error in grant FIFO.
57707 …IFO_ERROR (0x1<<19) // Error in grant FIFO.
57709 …O_ERROR_E5 (0x1<<20) // Error in LLH order FIFO.
57711 …O_ERROR_E5 (0x1<<21) // Error in LLH order FIFO.
57862 … (0x1<<0) // Error in the pure-loopback SOPQ.
57864 …RROR_K2_E5 (0x1<<1) // Error in RX MAC FIFO.
57866 …RROR_K2_E5 (0x1<<2) // Error in TX MAC FIFO.
57868 …_K2_E5 (0x1<<3) // FIFO error in TX BMB FIFO.
57870 …_K2_E5 (0x1<<4) // FIFO error in LB BMB FIFO.
57872 …E5 (0x1<<5) // Error in BTB FIFO for TX path.
57874 …E5 (0x1<<6) // Error in BTB FIFO for LB path.
57876 …RROR_K2_E5 (0x1<<7) // Error in LLH Data FIFO.
57878 …RROR_K2_E5 (0x1<<8) // Error in LLH Data FIFO.
57880 …RROR_K2_E5 (0x1<<9) // Error in LLH Data FIFO.
57882 …R_K2_E5 (0x1<<10) // Error in LLH Header FIFO.
57884 …R_K2_E5 (0x1<<11) // Error in LLH Header FIFO.
57886 …R_K2_E5 (0x1<<12) // Error in LLH Header FIFO.
57888 …R_K2_E5 (0x1<<13) // Error in LLH Result FIFO.
57890 …R_K2_E5 (0x1<<14) // Error in LLH Result FIFO.
57892 …R_K2_E5 (0x1<<15) // Error in LLH Result FIFO.
57894 … (0x1<<16) // FIFO error in STORM message FIFO.
57896 … (0x1<<17) // FIFO error in STORM descriptor FIF…
57898 …ERROR_K2_E5 (0x1<<18) // Error in grant FIFO.
57900 …ERROR_K2_E5 (0x1<<19) // Error in grant FIFO.
57902 …ROR_E5 (0x1<<20) // Error in LLH order FIFO.
57904 …ROR_E5 (0x1<<21) // Error in LLH order FIFO.
57952 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
57954 …O_ERROR_K2_E5 (0x1<<1) // Error in RX MAC FIFO.
57956 …O_ERROR_K2_E5 (0x1<<2) // Error in TX MAC FIFO.
57958 …ROR_K2_E5 (0x1<<3) // FIFO error in TX BMB FIFO.
57960 …ROR_K2_E5 (0x1<<4) // FIFO error in LB BMB FIFO.
57962 …K2_E5 (0x1<<5) // Error in BTB FIFO for TX path.
57964 …K2_E5 (0x1<<6) // Error in BTB FIFO for LB path.
57966 …O_ERROR_K2_E5 (0x1<<7) // Error in LLH Data FIFO.
57968 …O_ERROR_K2_E5 (0x1<<8) // Error in LLH Data FIFO.
57970 …O_ERROR_K2_E5 (0x1<<9) // Error in LLH Data FIFO.
57972 …RROR_K2_E5 (0x1<<10) // Error in LLH Header FIFO.
57974 …RROR_K2_E5 (0x1<<11) // Error in LLH Header FIFO.
57976 …RROR_K2_E5 (0x1<<12) // Error in LLH Header FIFO.
57978 …RROR_K2_E5 (0x1<<13) // Error in LLH Result FIFO.
57980 …RROR_K2_E5 (0x1<<14) // Error in LLH Result FIFO.
57982 …RROR_K2_E5 (0x1<<15) // Error in LLH Result FIFO.
57984 … (0x1<<16) // FIFO error in STORM message FIFO.
57986 …_E5 (0x1<<17) // FIFO error in STORM descriptor FIF…
57988 …FO_ERROR_K2_E5 (0x1<<18) // Error in grant FIFO.
57990 …FO_ERROR_K2_E5 (0x1<<19) // Error in grant FIFO.
57992 …_ERROR_E5 (0x1<<20) // Error in LLH order FIFO.
57994 …_ERROR_E5 (0x1<<21) // Error in LLH order FIFO.
57997 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
57999 …FO_ERROR_K2_E5 (0x1<<1) // Error in RX MAC FIFO.
58001 …FO_ERROR_K2_E5 (0x1<<2) // Error in TX MAC FIFO.
58003 …RROR_K2_E5 (0x1<<3) // FIFO error in TX BMB FIFO.
58005 …RROR_K2_E5 (0x1<<4) // FIFO error in LB BMB FIFO.
58007 …_K2_E5 (0x1<<5) // Error in BTB FIFO for TX path.
58009 …_K2_E5 (0x1<<6) // Error in BTB FIFO for LB path.
58011 …FO_ERROR_K2_E5 (0x1<<7) // Error in LLH Data FIFO.
58013 …FO_ERROR_K2_E5 (0x1<<8) // Error in LLH Data FIFO.
58015 …FO_ERROR_K2_E5 (0x1<<9) // Error in LLH Data FIFO.
58017 …ERROR_K2_E5 (0x1<<10) // Error in LLH Header FIFO.
58019 …ERROR_K2_E5 (0x1<<11) // Error in LLH Header FIFO.
58021 …ERROR_K2_E5 (0x1<<12) // Error in LLH Header FIFO.
58023 …ERROR_K2_E5 (0x1<<13) // Error in LLH Result FIFO.
58025 …ERROR_K2_E5 (0x1<<14) // Error in LLH Result FIFO.
58027 …ERROR_K2_E5 (0x1<<15) // Error in LLH Result FIFO.
58029 …5 (0x1<<16) // FIFO error in STORM message FIFO.
58031 …2_E5 (0x1<<17) // FIFO error in STORM descriptor FIF…
58033 …IFO_ERROR_K2_E5 (0x1<<18) // Error in grant FIFO.
58035 …IFO_ERROR_K2_E5 (0x1<<19) // Error in grant FIFO.
58037 …O_ERROR_E5 (0x1<<20) // Error in LLH order FIFO.
58039 …O_ERROR_E5 (0x1<<21) // Error in LLH order FIFO.
58190 … (0x1<<0) // Error in the pure-loopback SOPQ.
58192 …RROR_K2_E5 (0x1<<1) // Error in RX MAC FIFO.
58194 …RROR_K2_E5 (0x1<<2) // Error in TX MAC FIFO.
58196 …_K2_E5 (0x1<<3) // FIFO error in TX BMB FIFO.
58198 …_K2_E5 (0x1<<4) // FIFO error in LB BMB FIFO.
58200 …E5 (0x1<<5) // Error in BTB FIFO for TX path.
58202 …E5 (0x1<<6) // Error in BTB FIFO for LB path.
58204 …RROR_K2_E5 (0x1<<7) // Error in LLH Data FIFO.
58206 …RROR_K2_E5 (0x1<<8) // Error in LLH Data FIFO.
58208 …RROR_K2_E5 (0x1<<9) // Error in LLH Data FIFO.
58210 …R_K2_E5 (0x1<<10) // Error in LLH Header FIFO.
58212 …R_K2_E5 (0x1<<11) // Error in LLH Header FIFO.
58214 …R_K2_E5 (0x1<<12) // Error in LLH Header FIFO.
58216 …R_K2_E5 (0x1<<13) // Error in LLH Result FIFO.
58218 …R_K2_E5 (0x1<<14) // Error in LLH Result FIFO.
58220 …R_K2_E5 (0x1<<15) // Error in LLH Result FIFO.
58222 … (0x1<<16) // FIFO error in STORM message FIFO.
58224 … (0x1<<17) // FIFO error in STORM descriptor FIF…
58226 …ERROR_K2_E5 (0x1<<18) // Error in grant FIFO.
58228 …ERROR_K2_E5 (0x1<<19) // Error in grant FIFO.
58230 …ROR_E5 (0x1<<20) // Error in LLH order FIFO.
58232 …ROR_E5 (0x1<<21) // Error in LLH order FIFO.
58280 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58282 …O_ERROR_K2_E5 (0x1<<1) // Error in RX MAC FIFO.
58284 …O_ERROR_K2_E5 (0x1<<2) // Error in TX MAC FIFO.
58286 …ROR_K2_E5 (0x1<<3) // FIFO error in TX BMB FIFO.
58288 …ROR_K2_E5 (0x1<<4) // FIFO error in LB BMB FIFO.
58290 …K2_E5 (0x1<<5) // Error in BTB FIFO for TX path.
58292 …K2_E5 (0x1<<6) // Error in BTB FIFO for LB path.
58294 …O_ERROR_K2_E5 (0x1<<7) // Error in LLH Data FIFO.
58296 …O_ERROR_K2_E5 (0x1<<8) // Error in LLH Data FIFO.
58298 …O_ERROR_K2_E5 (0x1<<9) // Error in LLH Data FIFO.
58300 …RROR_K2_E5 (0x1<<10) // Error in LLH Header FIFO.
58302 …RROR_K2_E5 (0x1<<11) // Error in LLH Header FIFO.
58304 …RROR_K2_E5 (0x1<<12) // Error in LLH Header FIFO.
58306 …RROR_K2_E5 (0x1<<13) // Error in LLH Result FIFO.
58308 …RROR_K2_E5 (0x1<<14) // Error in LLH Result FIFO.
58310 …RROR_K2_E5 (0x1<<15) // Error in LLH Result FIFO.
58312 … (0x1<<16) // FIFO error in STORM message FIFO.
58314 …_E5 (0x1<<17) // FIFO error in STORM descriptor FIF…
58316 …FO_ERROR_K2_E5 (0x1<<18) // Error in grant FIFO.
58318 …FO_ERROR_K2_E5 (0x1<<19) // Error in grant FIFO.
58320 …_ERROR_E5 (0x1<<20) // Error in LLH order FIFO.
58322 …_ERROR_E5 (0x1<<21) // Error in LLH order FIFO.
58325 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58327 …FO_ERROR_K2_E5 (0x1<<1) // Error in RX MAC FIFO.
58329 …FO_ERROR_K2_E5 (0x1<<2) // Error in TX MAC FIFO.
58331 …RROR_K2_E5 (0x1<<3) // FIFO error in TX BMB FIFO.
58333 …RROR_K2_E5 (0x1<<4) // FIFO error in LB BMB FIFO.
58335 …_K2_E5 (0x1<<5) // Error in BTB FIFO for TX path.
58337 …_K2_E5 (0x1<<6) // Error in BTB FIFO for LB path.
58339 …FO_ERROR_K2_E5 (0x1<<7) // Error in LLH Data FIFO.
58341 …FO_ERROR_K2_E5 (0x1<<8) // Error in LLH Data FIFO.
58343 …FO_ERROR_K2_E5 (0x1<<9) // Error in LLH Data FIFO.
58345 …ERROR_K2_E5 (0x1<<10) // Error in LLH Header FIFO.
58347 …ERROR_K2_E5 (0x1<<11) // Error in LLH Header FIFO.
58349 …ERROR_K2_E5 (0x1<<12) // Error in LLH Header FIFO.
58351 …ERROR_K2_E5 (0x1<<13) // Error in LLH Result FIFO.
58353 …ERROR_K2_E5 (0x1<<14) // Error in LLH Result FIFO.
58355 …ERROR_K2_E5 (0x1<<15) // Error in LLH Result FIFO.
58357 …5 (0x1<<16) // FIFO error in STORM message FIFO.
58359 …2_E5 (0x1<<17) // FIFO error in STORM descriptor FIF…
58361 …IFO_ERROR_K2_E5 (0x1<<18) // Error in grant FIFO.
58363 …IFO_ERROR_K2_E5 (0x1<<19) // Error in grant FIFO.
58365 …O_ERROR_E5 (0x1<<20) // Error in LLH order FIFO.
58367 …O_ERROR_E5 (0x1<<21) // Error in LLH order FIFO.
58522 …R_E5 (0x1<<0) // Error in the TX SOPQ.
58524 …R_E5 (0x1<<1) // Error in the TX SOPQ.
58526 …R_E5 (0x1<<2) // Error in the TX SOPQ.
58528 …R_E5 (0x1<<3) // Error in the TX SOPQ.
58530 …R_E5 (0x1<<4) // Error in the TX SOPQ.
58532 …R_E5 (0x1<<5) // Error in the TX SOPQ.
58534 …R_E5 (0x1<<6) // Error in the TX SOPQ.
58536 …R_E5 (0x1<<7) // Error in the TX SOPQ.
58538 …R_E5 (0x1<<8) // Error in the LB SOPQ.
58540 …R_E5 (0x1<<9) // Error in the LB SOPQ.
58542 …_E5 (0x1<<10) // Error in the LB SOPQ.
58544 …_E5 (0x1<<11) // Error in the LB SOPQ.
58546 …_E5 (0x1<<12) // Error in the LB SOPQ.
58548 …_E5 (0x1<<13) // Error in the LB SOPQ.
58550 …_E5 (0x1<<14) // Error in the LB SOPQ.
58552 …_E5 (0x1<<15) // Error in the LB SOPQ.
58588 …RROR_E5 (0x1<<0) // Error in the TX SOPQ.
58590 …RROR_E5 (0x1<<1) // Error in the TX SOPQ.
58592 …RROR_E5 (0x1<<2) // Error in the TX SOPQ.
58594 …RROR_E5 (0x1<<3) // Error in the TX SOPQ.
58596 …RROR_E5 (0x1<<4) // Error in the TX SOPQ.
58598 …RROR_E5 (0x1<<5) // Error in the TX SOPQ.
58600 …RROR_E5 (0x1<<6) // Error in the TX SOPQ.
58602 …RROR_E5 (0x1<<7) // Error in the TX SOPQ.
58604 …RROR_E5 (0x1<<8) // Error in the LB SOPQ.
58606 …RROR_E5 (0x1<<9) // Error in the LB SOPQ.
58608 …ROR_E5 (0x1<<10) // Error in the LB SOPQ.
58610 …ROR_E5 (0x1<<11) // Error in the LB SOPQ.
58612 …ROR_E5 (0x1<<12) // Error in the LB SOPQ.
58614 …ROR_E5 (0x1<<13) // Error in the LB SOPQ.
58616 …ROR_E5 (0x1<<14) // Error in the LB SOPQ.
58618 …ROR_E5 (0x1<<15) // Error in the LB SOPQ.
58621 …ERROR_E5 (0x1<<0) // Error in the TX SOPQ.
58623 …ERROR_E5 (0x1<<1) // Error in the TX SOPQ.
58625 …ERROR_E5 (0x1<<2) // Error in the TX SOPQ.
58627 …ERROR_E5 (0x1<<3) // Error in the TX SOPQ.
58629 …ERROR_E5 (0x1<<4) // Error in the TX SOPQ.
58631 …ERROR_E5 (0x1<<5) // Error in the TX SOPQ.
58633 …ERROR_E5 (0x1<<6) // Error in the TX SOPQ.
58635 …ERROR_E5 (0x1<<7) // Error in the TX SOPQ.
58637 …ERROR_E5 (0x1<<8) // Error in the LB SOPQ.
58639 …ERROR_E5 (0x1<<9) // Error in the LB SOPQ.
58641 …RROR_E5 (0x1<<10) // Error in the LB SOPQ.
58643 …RROR_E5 (0x1<<11) // Error in the LB SOPQ.
58645 …RROR_E5 (0x1<<12) // Error in the LB SOPQ.
58647 …RROR_E5 (0x1<<13) // Error in the LB SOPQ.
58649 …RROR_E5 (0x1<<14) // Error in the LB SOPQ.
58651 …RROR_E5 (0x1<<15) // Error in the LB SOPQ.
59324 …-gate function disable bit: 0 - egress drain mode is enabled when close-gate input from MISC to N…
59331 … 0x50081cUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, o…
59332 … 0x500820UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, o…
59333 … 0x500824UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, o…
59334 … 0x500828UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, o…
59335 … 0x50082cUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, o…
59336 … 0x500830UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, o…
59338 …RX packets. 0 is for XSTORM; 1 is for YSTORM. This configuration should be static during run-time.
59339 …get the current credit count on the interface. This configuration should be static during run-time.
59341 … (0xff<<0) // Event ID to be used in CM header for packet…
59343 … (0x1<<8) // T-bit to be used in CM header fo…
59345 … (0x1<<9) // DstStormFlg to be used in CM header for packet…
59347 … (0x1<<10) // ConnectionDomainExist to be used in CM header for packet…
59349 …-PF drop and per-VPORT drop packets or forward the packet to the destination with the error bit se…
59350 … 0x500848UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59351 … 0x50084cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59352 … 0x500850UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59353 … 0x500854UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59354 … 0x500858UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59355 … 0x50085cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59356 … 0x500860UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59357 … 0x500864UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59358 … 0x500868UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59359 … 0x50086cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59360 … 0x500870UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59361 … 0x500874UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59362 … 0x500878UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59363 … 0x50087cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59364 … 0x500880UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59365 … 0x500884UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59366 … 0x500888UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59367 … 0x50088cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59368 … 0x500890UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59369 … 0x500894UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59370 … 0x500898UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59371 … 0x50089cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59372 … 0x5008a0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59373 … 0x5008a4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59374 … 0x5008a8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59375 … 0x5008acUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59376 … 0x5008b0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59377 … 0x5008b4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59378 … 0x5008b8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59379 … 0x5008bcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59380 … 0x5008c0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59381 … 0x5008c4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59382 … 0x5008c8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59383 … 0x5008ccUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59384 … 0x5008d0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59385 … 0x5008d4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59386 … 0x5008d8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59387 … 0x5008dcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59388 … 0x5008e0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59389 … 0x5008e4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59390 … 0x5008e8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59391 … 0x5008ecUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59392 … 0x5008f0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59393 … 0x5008f4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59394 … 0x5008f8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59395 … 0x5008fcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59396 … 0x500900UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59397 … 0x500904UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59398 … 0x500908UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59399 … 0x50090cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59400 … 0x500910UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59401 … 0x500914UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59402 … 0x500918UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59403 … 0x50091cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59404 … 0x500920UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59405 … 0x500924UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59406 … 0x500928UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59407 … 0x50092cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59408 … 0x500930UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59409 … 0x500934UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59410 … 0x500938UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59411 … 0x50093cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59412 … 0x500940UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59413 … 0x500944UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59414 … 0x500948UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59415 … 0x50094cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59416 … 0x500950UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59417 … 0x500954UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59418 … 0x500958UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59419 … 0x50095cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59420 … 0x500960UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59421 … 0x500964UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59422 … 0x500968UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59423 … 0x50096cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59424 … 0x500970UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59425 … 0x500974UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59426 … 0x500978UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59427 … 0x50097cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59428 … 0x500980UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59429 … 0x500984UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59430 … 0x500988UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59431 … 0x50098cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59432 … 0x500990UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59433 … 0x500994UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59434 … 0x500998UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59435 … 0x50099cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59436 … 0x5009a0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59437 … 0x5009a4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59438 … 0x5009a8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59439 … 0x5009acUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59440 … 0x5009b0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59441 … 0x5009b4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59442 … 0x5009b8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59443 … 0x5009bcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59444 … 0x5009c0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59445 … 0x5009c4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59446 … 0x5009c8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59447 … 0x5009ccUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59448 … 0x5009d0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59449 … 0x5009d4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59450 … 0x5009d8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59451 … 0x5009dcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59452 … 0x5009e0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59453 … 0x5009e4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59454 … 0x5009e8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59455 … 0x5009ecUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59456 … 0x5009f0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59457 … 0x5009f4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59458 … 0x5009f8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59459 … 0x5009fcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59460 … 0x500a00UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59461 … 0x500a04UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59462 … 0x500a08UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59463 … 0x500a0cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59464 … 0x500a10UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59465 … 0x500a14UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59466 … 0x500a18UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59467 … 0x500a1cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59468 … 0x500a20UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59469 … 0x500a24UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59470 … 0x500a28UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59471 … 0x500a2cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59472 … 0x500a30UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59473 … 0x500a34UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59474 … 0x500a38UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59475 … 0x500a3cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59476 … 0x500a40UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59477 … 0x500a44UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59478 … 0x500a48UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59479 … 0x500a4cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59480 … 0x500a50UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59481 … 0x500a54UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59482 … 0x500a58UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59483 … 0x500a5cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59484 … 0x500a60UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59485 … 0x500a64UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59486 … 0x500a68UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59487 … 0x500a6cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59488 … 0x500a70UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59489 … 0x500a74UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59490 … 0x500a78UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59491 … 0x500a7cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59492 … 0x500a80UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59493 … 0x500a84UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59494 … 0x500a88UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59495 … 0x500a8cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59496 … 0x500a90UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59497 … 0x500a94UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59498 … 0x500a98UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59499 … 0x500a9cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59500 … 0x500aa0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59501 … 0x500aa4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59502 … 0x500aa8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59503 … 0x500aacUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59504 … 0x500ab0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59505 … 0x500ab4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59506 … 0x500ab8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59507 … 0x500abcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59508 … 0x500ac0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59509 … 0x500ac4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59510 … 0x500ac8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59511 … 0x500accUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59512 … 0x500ad0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59513 … 0x500ad4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59514 … 0x500ad8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59515 … 0x500adcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59516 … 0x500ae0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59517 … 0x500ae4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59518 … 0x500ae8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59519 … 0x500aecUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59520 … 0x500af0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59521 … 0x500af4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59522 … 0x500af8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59523 … 0x500afcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59524 … 0x500b00UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59525 … 0x500b04UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59526 … 0x500b08UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59527 … 0x500b0cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59528 … 0x500b10UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59529 … 0x500b14UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59530 … 0x500b18UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59531 … 0x500b1cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59532 … 0x500b20UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59533 … 0x500b24UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59534 … 0x500b28UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59535 … 0x500b2cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59536 … 0x500b30UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59537 … 0x500b34UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59538 … 0x500b38UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59539 … 0x500b3cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59540 … 0x500b40UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59541 … 0x500b44UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59542 … 0x500b48UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59543 … 0x500b4cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59544 … 0x500b50UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59545 … 0x500b54UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59546 … 0x500b58UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59547 … 0x500b5cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59548 … 0x500b60UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59549 … 0x500b64UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59550 … 0x500b68UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59551 … 0x500b6cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59552 … 0x500b70UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59553 … 0x500b74UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59554 … 0x500b78UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59555 … 0x500b7cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59556 … 0x500b80UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59557 … 0x500b84UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59558 … 0x500c00UL //Access:RW DataWidth:0x1 // Per-PF drop configuration…
59561 …0cUL //Access:R DataWidth:0x18 // TX SOP descriptor queue empty status - for main traffic que…
59562 …c10UL //Access:R DataWidth:0x18 // TX SOP descriptor queue full status - for main traffic que…
59563 … DataWidth:0x40 // Addresses for TimeSync related registers in the timesync generator sub-module.
59567 …1 // Output enable for the STORM interface. This configuration should be static during run-time.
59580 …in 32-bit words, that is present at the start of the packet. This configuration applies to all pa…
59581 …th:0xa // The number of bytes in the header, counting from the start of the packet, to pass to …
59586 …-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer tag);…
59587 … 0x50101cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59588 … 0x501020UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59589 … 0x501024UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59590 … 0x501028UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59591 … 0x50102cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59592 … 0x501030UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59593 … 0x501034UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59594 …-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer tag);…
59595 … 0x50103cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59596 … 0x501040UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59597 … 0x501044UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59598 … 0x501048UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59599 … 0x50104cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59600 … 0x501050UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59601 … 0x501054UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59603 … (0x1<<0) // Enable bit for Ethernet-over-GRE (L2 GRE) encaps…
59605 … (0x1<<1) // Enable bit for IP-over-GRE (IP GRE) encaps…
59612 … 0x501068UL //Access:RW DataWidth:0x10 // FCOE Ethertype - default is 0x8906.
59617 … 0x50107cUL //Access:RW DataWidth:0x8 // IPv4 protocol field for ICMPv4 - defaults to 0x01.
59618 … 0x501080UL //Access:RW DataWidth:0x8 // IPv6 next header field for ICMPv6 - defaults to 0x3A.
59620 …th:0x20 // Destination MAC address 1; The LLH will look for this address in all incoming packets.
59621 …th:0x10 // Destination MAC address 1; The LLH will look for this address in all incoming packets.
59622 …dth:0x20 // Destination MAC address 2;The LLH will look for this address in all incoming packets.
59623 …dth:0x10 // Destination MAC address 2;The LLH will look for this address in all incoming packets.
59624 …dth:0x20 // Destination MAC address 3;The LLH will look for this address in all incoming packets.
59625 …dth:0x10 // Destination MAC address 3;The LLH will look for this address in all incoming packets.
59626 …Width:0x20 // Destination MAC address 3. LLH will look for this address in all incoming packets.
59627 …Width:0x10 // Destination MAC address 3. LLH will look for this address in all incoming packets.
59628 …Width:0x20 // Destination MAC address 4. LLH will look for this address in all incoming packets.
59629 …Width:0x10 // Destination MAC address 4. LLH will look for this address in all incoming packets.
59630 …Width:0x20 // Destination MAC address 5. LLH will look for this address in all incoming packets.
59631 …Width:0x10 // Destination MAC address 5. LLH will look for this address in all incoming packets.
59634 … 0x5010c0UL //Access:RW DataWidth:0xc // Inner VLAN ID 0 used in NCSI filtering.
59635 … 0x5010c4UL //Access:RW DataWidth:0xc // Inner VLAN ID 1 used in NCSI filtering.
59636 … 0x5010c8UL //Access:RW DataWidth:0xc // Inner VLAN ID 2 used in NCSI filtering.
59639 …// Destination IP address 1;The LLH will look for this address in all incoming packets. In case of…
59640 …// Destination IP address 1;The LLH will look for this address in all incoming packets. In case of…
59641 …// Destination IP address 1;The LLH will look for this address in all incoming packets. In case of…
59642 …// Destination IP address 1;The LLH will look for this address in all incoming packets. In case of…
59643 …// Destination IP address 2;The LLH will look for this address in all incoming packets. In case of…
59644 …// Destination IP address 2;The LLH will look for this address in all incoming packets. In case of…
59645 …// Destination IP address 2;The LLH will look for this address in all incoming packets. In case of…
59646 …// Destination IP address 2;The LLH will look for this address in all incoming packets. In case of…
59647 …// Destination IP address 3;The LLH will look for this address in all incoming packets. In case of…
59648 …// Destination IP address 3;The LLH will look for this address in all incoming packets. In case of…
59649 …// Destination IP address 3;The LLH will look for this address in all incoming packets. In case of…
59650 …// Destination IP address 3;The LLH will look for this address in all incoming packets. In case of…
59651 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_0: 0 - IPv6; 1-IPv4.
59652 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_1: 0 - IPv6; 1-IPv4.
59653 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_2: 0 - IPv6; 1-IPv4.
59654 …h:0x10 // Destination TCP address 1. The LLH will look for this address in all incoming packets.
59655 …h:0x10 // Destination TCP address 2. The LLH will look for this address in all incoming packets.
59656 …h:0x10 // Destination TCP address 3. The LLH will look for this address in all incoming packets.
59657 …th:0x10 // Destination UDP address 1 The LLH will look for this address in all incoming packets.
59658 …h:0x10 // Destination UDP address 2 The LLH will look for this address in all incoming packets.
59659 …h:0x10 // Destination UDP address 3 The LLH will look for this address in all incoming packets.
59760 …ackets from all PFs, including packets that failed PF classification, to MCP in multifunction mode.
59761 … // Enable bit for forwarding packets for each PF to MCP in multifunction mode. This is a per-PF …
59862 …s from all PFs, including packets that failed PF classification, to the host in multifunction mode.
59863 …le bit for not forwarding packets for the PF to the host in multifunction mode. This is a per-PF …
59889 …for comparison. A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-80-C2-00-00-0F.
60009 … for comparison. A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-80-C2-00-00-0F.
60126 …t with classification failed status is forwarded to BRB when this bit is set in multifunction mode.
60127 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60147 …- message FIFO empty. Bit 1 - descriptor FIFO empty. Bit 2 - message FIFO has more than 32 entries…
60148 …-to-send data remaining below which ETS arbiter for the LB path should start selecting the next pa…
60150 … 0x501508UL //Access:RW DataWidth:0x1 // Zero-padding enable for LB…
60152 … (0x1<<0) // Enable bit for the BRB interface rate limiter to be used in pacing LB traffic. …
60156 … DataWidth:0x20 // Increment PERIOD for the BRB interface rate limiter - in term of 25MHz clock…
60157 … rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration…
60158 … bound VALUE for the BRB interface rate limiter - in term of bytes, cycles, or packets (as select…
60159 …ize for the BRB interface rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
60161 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing…
60163 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60166 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing…
60168 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60171 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing…
60173 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60176 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing…
60178 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60181 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing…
60183 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60186 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing…
60188 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60191 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing…
60193 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60196 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing…
60198 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60200 …UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25…
60201 …UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25…
60202 …UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25…
60203 …UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25…
60204 …UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25…
60205 …UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25…
60206 …UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25…
60207 …UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25…
60208 …he per-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type conf…
60209 …he per-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type conf…
60210 …he per-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type conf…
60211 …he per-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type conf…
60212 …he per-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type conf…
60213 …he per-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type conf…
60214 …he per-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type conf…
60215 …he per-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type conf…
60216 …:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of bytes, cycles, or packets (…
60217 …:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of bytes, cycles, or packets (…
60218 …:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of bytes, cycles, or packets (…
60219 …:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of bytes, cycles, or packets (…
60220 …:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of bytes, cycles, or packets (…
60221 …:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of bytes, cycles, or packets (…
60222 …:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of bytes, cycles, or packets (…
60223 …:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of bytes, cycles, or packets (…
60224 …o the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
60225 …o the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
60226 …o the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
60227 …o the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
60228 …o the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
60229 …o the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
60230 …o the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
60231 …o the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
60232 …in the strict priority arbiter. The bits are mapped according to client ID (client IDs are defin…
60233 …in *_arb_priority_client): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffi…
60234 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60235 …g IDs: 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6…
60237 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
60238 … bytes to be deducted from the client credit register at the time of grant in additional to the no…
60239 … 0x5015e0UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbitration mo…
60250 … 0x50160cUL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60251 … 0x501610UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60252 … 0x501614UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60253 … 0x501618UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60254 … 0x50161cUL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60255 … 0x501620UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60256 … 0x501624UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60257 … 0x501628UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60258 … 0x50162cUL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60259 … 0x501630UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60260 …34UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
60261 …38UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
60262 …3cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
60263 …40UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
60264 …44UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
60265 …48UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
60266 …4cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
60267 …50UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
60268 …54UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
60269 …58UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter cre…
60271 …t with classification failed status is forwarded to BRB when this bit is set in multifunction mode.
60272 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60289 …RX side. Bit 1 enables V1 frame format in timesync event detection on RX side. Bit 2 enables V2 …
60290 …TX side. Bit 1 enables V1 frame format in timesync event detection on TX side. Bit 2 enables V2 …
60293 … 0x501910UL //Access:RW DataWidth:0x1 // Enable for SW-specified packet time…
60297 …in determining PTP packet presence. Set each bit to 1 to mask out the particular parameter. 0-IP…
60298 …in detecting PTP packets. Set each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP…
60299 …in determining PTP packet presence. Set each bit to 1 to mask out the particular parameter. 0-IP…
60300 …in detecting PTP packets. Set each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP…
60301 … is buffered in 1-deep FIFOs for the host. Bits [15:0] return the sequence ID of the packet. Bit…
60302 …ess:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the …
60303 …ess:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the …
60304 …hat is buffered in 1-deep FIFOs for MCP. Bits [15:0] return the sequence ID of the packet. Bit 1…
60305 …ess:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP.…
60306 …ess:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP.…
60307 … is buffered in 1-deep FIFOs for TX side. Bits [15:0] reflect the sequence ID of the packet. Bit…
60308 …ess:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the T…
60309 …ess:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the T…
60310 …in adjustment of the upper 32-bit time for the 64-bit timestamp value. Error occurs when bits [31…
60311 …in adjustment of the upper 32-bit time for the 64-bit timestamp value. Error occurs when bits [31…
60312 …cation before sending the packet to the BRB and performing WOL detection. In single function mode…
60313 …l. 3: dual-stage classification. When no classification is performed in multifunction mode, PPFID …
60314 …in dual-stage classification mode; value of 0: AND the hit vectors; value of 1: OR the hit vectors…
60315 …Default per-port value to be used when protocol-based classification fails. This is the per-port …
60316 …lt per-port value to be used when outer-tag/inner VLAN/MAC classification fails. This is the per…
60317 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60318 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60319 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60320 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60321 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60322 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60323 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60324 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60325 …-bit field immediately following the Ethertype to be used for each of the outer tag value bit. The…
60330 …-port per-PF register. This register selects the classification type for the tag/VLAN/MAC mode. …
60331 … 0x5019b0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60333 …-port per-PF register. Per-function select bit for choosing between the tunnel and encapsulated h…
60335 … 0x5019d0UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. Per-function…
60337 … 0x5019e0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60338 …er-port per-PF register. Per-function MAC addresses to be matched with for MAC-address-based clas…
60340 … 0x501a80UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60342 …-port per-PF register. Per-function mode select bit to indicate whether the filter is to be used …
60344 …7 // This is a per-port per-PF register. Per-function select bits for the different protocol t…
60346 …-port per-PF register. Per-function select bit for choosing between the tunnel and encapsulated h…
60348 …e. 0 selects connection-based classification. 1 selects the PF-based classification. This regist…
60349 …-tuple search for TCP packets. Set this bit to use the TCP 4-tuple (TCP source and destination po…
60350 …-tuple search for UDP packets. Set this bit to use the UDP 4-tuple (UDP source and destination po…
60351 …tion used to hash the data string in connection-based engine classification. This register is use…
60352 …-entry Engine ID lookup table, with 1 bit per entry. Set the bit to 1 to have packets associated …
60354 …ts one of the 24-bit destination QP bits to be used as the engine ID. Valid values are 0-23. Thi…
60355 …-global-PF engine ID to be used in PF-based engine classification. Set the bit to 1 to have packe…
60356 …ss:RW DataWidth:0x3 // Flow control mode. 0 - disable; 1 - PFC; 2 - LLFC; 3 - PPP; 4 - PAUSE…
60357 … 0x501ba4UL //Access:RW DataWidth:0x20 // Eight 4-bit configurations for specifying which TC (…
60359 … Valid values are 2-5 for selecting one of the L2 tags 2-5. This field is evaluated only when th…
60361 … (0xf<<3) // Bit offset in the outer tag starting from which to extract t…
60363 … (0xf<<7) // Bit offset in the selected tag starting from which to extract…
60365 …-TC full signals. This register may change during run time. Packet truncation/discarding affects…
60367 … // Per-TC flow control enable for received XOFF requests to pause transmit queues. Set a bit to…
60368 … DataWidth:0x8 // Per-TC flow control enable for XOFF messages sent to the MAC. Set a bit to …
60369 …Width:0x9 // Per-TC flow control enable for received XOFF requests to pause LB queues. Set a b…
60370 …DataWidth:0x1 // Enable bit for the no-drop-hdr-ind field of the LB-only-header. When set, the…
60371 …-drop of LB packets with the no-drop-hdr-ind bit set due to per-TC full backpressure from the BRB.…
60372 …cifies the number of 256-bit cycles, starting from the SOP cycle, of the packet not to be dropped …
60373 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60374 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60375 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60376 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60377 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60378 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60379 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60380 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60381 … 0x501becUL //Access:RW DataWidth:0x10 // Bit-map indicating which …
60382 … 0x501bf0UL //Access:RW DataWidth:0x10 // Bit-map indicating which …
60383 … 0x501bf4UL //Access:RW DataWidth:0x10 // Bit-map indicating which …
60384 … 0x501bf8UL //Access:RW DataWidth:0x10 // Bit-map indicating which …
60385 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60386 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60387 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60388 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60393 …ain mode starts immediately upon assertion and stops at the next packet boundary upon de-assertion.
60394 …rts immediately upon assertion and stops at the next packet boundary upon de-assertion. Note that…
60395 …hen enabled -- draining of the corrresponding TC starts immediately - packet data are dropped and…
60396 …hen enabled -- draining of the corrresponding TC starts immediately - packet data are dropped and…
60397 …in the TX direction for sending refresh LLFC messages to the MAC. The value is in term of the num…
60407 … 0x501c54UL //Access:RW DataWidth:0x10 // Address to be used in the header of the fl…
60410 … 0x501c60UL //Access:RW DataWidth:0x4 // Trigger value to be used in the header of the fl…
60435 …rrors, and filtering. Note that statistics for packets with 32B or less are in stat_*1cyc_pkt_drop.
60436 … // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statist…
60454 …dropped due to buffer full. This is an RF generated RC statistics register - reading this registe…
60455 …uncated due to buffer full. This is an RF generated RC statistics register - reading this registe…
60496 …rrors, and filtering. Note that statistics for packets with 32B or less are in stat_*1cyc_pkt_drop.
60497 … // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statist…
60498 …the TX packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the MCP/per…
60499 …-PF drop or per-VPORT drop configuration set. These packets may be dropped or forwarded to the des…
60500 …f the LB packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the per-T…
60501 …-PF drop or per-VPORT drop configuration set while the no-drop-hdr-ind in the packet is cleared. T…
60568 …ets from BMB to be forwarded to the host that got truncated due to BRB LB per-TC full backpressure.
60569 …ckets from BMB to be forwarded to the host that got dropped due to BRB LB per-TC full backpressure.
60570 … 0x501f08UL //Access:RW DataWidth:0x1 // Zero-padding enable for TX…
60574 … (0xff<<1) // TC enable for EDPM. There is one bit per TC. This is used in the generation of th…
60576 …-to-transmit data remaining below which ETS arbiter for the transmit path should start selecting …
60580 … (0x1<<0) // Enable bit for the global rate limiter to be used in pacing TX and LB tra…
60584 …ess:RW DataWidth:0x20 // Increment PERIOD for the global rate limiter - in term of 25MHz clock…
60585 …l rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration…
60586 …// Upper bound VALUE for the global rate limiter - in term of bytes, cycles, or packets (as select…
60587 …o the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.
60589 …in the strict priority arbiter. The bits are mapped according to client ID (client IDs are defin…
60590 …in *_arb_priority_client): 0-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic f…
60591 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60592 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60594 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
60595 … bytes to be deducted from the client credit register at the time of grant in additional to the no…
60596 … 0x501f50UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbitration mo…
60610 … 0x501f88UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60611 … 0x501f8cUL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60612 … 0x501f90UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60613 … 0x501f94UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60614 … 0x501f98UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60615 … 0x501f9cUL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60616 … 0x501fa0UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60617 … 0x501fa4UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60618 … 0x501fa8UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60619 … 0x501facUL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60620 … 0x501fb0UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60621 … 0x501fb4UL //Access:RW DataWidth:0x20 // Specify the weight (in bytes) to be added t…
60622 …b8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter cre…
60623 …bcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter cre…
60624 …c0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter cre…
60625 …c4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter cre…
60626 …c8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter cre…
60627 …ccUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter cre…
60628 …d0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter cre…
60629 …d4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter cre…
60630 …d8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter cre…
60631 …dcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter cre…
60632 …e0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter cre…
60633 …e4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter cre…
60871 …LAN tag to be used in tag insertion/override for management packets. This field consists of {3-bi…
60872 …LAN tag to be used in tag insertion/override for management packets. This field consists of {3-bi…
60889 …sed in the BMC-to-host path to BRB. This is also used in the TX management path (when enabled by …
60891 … 0x50209cUL //Access:RW DataWidth:0x1 // Host-to-MCP path enable. Se…
60894 …UL //Access:RW DataWidth:0x9 // Maximum length of management packets, in term of the number o…
60895 … 0x5020acUL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
60900 … 0x5020c0UL //Access:RW DataWidth:0x7 // Almost-full threshold for DO…
60904 …- send debug traffic through port 0. 1 - send debug traffic through port 1. 2 - send debug traffi…
60905 …020d4UL //Access:RW DataWidth:0x9 // Maximum length of debug packets, in term of the number o…
60907 … 0x5020dcUL //Access:RW DataWidth:0x8 // Almost-full threshold for de…
60910 …- the number of valid bytes in the last cycle (0=all bytes are valid); [261]eop - active on the la…
60913 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
60922 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
60927 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
60932 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
60937 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
60942 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
60947 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
60953 …-port per-PF register. L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L…
60954 …-port per-PF register. Proprietary header removal configuration for ACPI. Set this bit to 1 to e…
60955 …it to enable ACPI pattern matching and TCP SYN matching in multi-function mode even when the per-f…
60957 … 0x508080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
60959 … 0x508100UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Whe…
60960 … 0x508104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60961 …8UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
60962 … 0x50810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60963 …0UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
60964 … 0x508114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60965 …8UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
60966 … 0x50811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60967 …0UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
60968 … 0x508124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60969 …8UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
60970 … 0x50812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60971 …0UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
60972 … 0x508134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60973 …8UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
60974 … 0x50813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60975 …0UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
60976 … 0x508144UL //Access:RW DataWidth:0x2 // This is a per-port per-PF register. Set…
60977 …-port per-PF register. Enable bits for fields to be compared if IPv6 is present in the packet. B…
60978 …-port per-PF register. Enable bits for fields to be compared if IPv4 is present in the packet. B…
60979 … 0x508150UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60980 … 0x508154UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60981 … 0x508158UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60982 … 0x50815cUL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60983 … 0x508160UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60985 … 0x508170UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60987 … 0x508180UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60988 … 0x508184UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60989 … 0x508188UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Whe…
60990 … 0x508190UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
60992 … 0x508198UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high …
60993 … 0x5081a0UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wa…
60995 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
60996 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
60997 … //Access:R DataWidth:0xe // Wake packet length - the actual length of the 'wake' packet, in…
60998 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
60999 …ess:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFOs for the …
61001 …ess:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFO for the T…
61005 … 0x508828UL //Access:RW DataWidth:0x1 // Enable TS update for one step packets in the TX path.
61019 …4_STANDARD � insert timestamp using standard IPv4 Timestamp option. In this mode 32-bit timestamp …
61021 … user protocol packets. the offset is relative to the configured value field in user_one_step_type.
61022 …RW DataWidth:0x5 // Global timestamp shift for the free running counter. Legal values are 0-16
61026 …in 1-deep FIFOs. Bits [15:0] return the sequence ID of the packet which is set by free running co…
61027 … DataWidth:0x40 // RX user protocol Packet information that is buffered in 1-deep FIFO. Timestam…
61029 … DataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Source a…
61031 …in 1-deep FIFOs. Bits [15:0] return the sequence ID of the packet which is set by free running co…
61032 … DataWidth:0x40 // TX user protocol Packet information that is buffered in 1-deep FIFO. Timestam…
61034 … DataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Destinat…
61039 …Since offset width is 64 bits, tsgen_offset_value_lsb should be read first in order to latch the o…
61041 …ince free counter width is 64 bits, tsgen_freecnt_lsb should be read first in order to latch the c…
61043 …nchronized time width is 64 bits, tsgen_sync_time_lsb should be read first in order to latch the c…
61044 … 0x5088c8UL //Access:RW DataWidth:0x1 // In this mode, Start ti…
61045 … 0x5088ccUL //Access:RW DataWidth:0x1 // In this mode, whenever…
61050 … 0x5088e0UL //Access:RW DataWidth:0x4 // Bits 3:0 are the active-low output enables fo…
61052 …pancy is higher than this threshold nig_dorq_edpm_en is de-asserted. The value is configured in 32…
61053 …8ecUL //Access:RW DataWidth:0x8 // This field sets message type value in ICMP header to ident…
61055 … 0x5088f4UL //Access:RW DataWidth:0x2 // This field selects engine ID in case that PF classif…
61056 …x1 // This field enables the feature that maps DSCP to TC in case that there is no TC in one of…
61059 …>> 2) 6 bits to 6 bits: bits 5:3 - priority bits 2:0 - TC This configuration is used when there is…
61065 …-port register L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L2 tags 0…
61066 …-port register. Proprietary header removal configuration for ACPI. Set this bit to 1 to enable t…
61067 …/Access:RW DataWidth:0x1 // This is a per-port register. When enabled, NIG will check Ethern…
61068 … 0x508b1cUL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61069 …-port register. When enabled, it indicates that the CNIG will add ethernet CRC to the packet. In …
61070 … 0x508b24UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61071 … 0x508b28UL //Access:RW DataWidth:0x1 // This is a per-port register. Enabl…
61072 … 0x508b2cUL //Access:RW DataWidth:0x1 // This is a per-port register. Enable…
61073 … 0x508b30UL //Access:RW DataWidth:0x1 // This is a per-port register. Perfo…
61074 …Access:RW DataWidth:0x10 // This is a per-port register. Next protocol value to be used for E…
61075 … 0x508b38UL //Access:RW DataWidth:0x10 // This is a per-port register. Destin…
61076 … 0x508b3cUL //Access:RW DataWidth:0x18 // This is a per-port register which d…
61077 … 0x508b40UL //Access:RW DataWidth:0x8 // This is the first opcode in the BTH header for f…
61078 … 0x508b44UL //Access:RW DataWidth:0x8 // This is the second opcode in the BTH header for f…
61152 …g mux Were not written as the FIFO was full. This indication will be valid In the next entry which…
61160 …mount of time that the interface to the CNIG will be closed in case a parity error occured in the …
61161 …nables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.
61162 …nables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.
61163 …t reisters. This enables credit sharing with one of the BTB TCs. 0: MNG. 1-8: BTB per TC. 9: B…
61166 …x1 // When this bit is configured to 1, NIG trasmits ports 0 and 1 data in TDM manner. If 0, th…
61167 …x1 // When this bit is configured to 1, NIG trasmits ports 2 and 2 data in TDM manner. If 0, th…
61188 …Width:0x20 // Destination MAC address 6. LLH will look for this address in all incoming packets.
61189 …Width:0x10 // Destination MAC address 6. LLH will look for this address in all incoming packets.
61190 …Width:0x20 // Destination MAC address 7. LLH will look for this address in all incoming packets.
61191 …Width:0x10 // Destination MAC address 7. LLH will look for this address in all incoming packets.
61192 …ther to use the MPA CRC calculation on one fully contained PDU (legacy mode - 0) or on multiple PD…
61193 …MAC addresses to be matched with for MAC-address-based classification. This register is also used…
61197 …ter is to be used for MAC-addresss based classification or protocol-based classification. Set thi…
61199 …l of 512 select bits for the different protocol types to be evaluated in protocol-based classifica…
61201 …sulated header from which to take the MAC address to be compared with that in llh_func_filter_valu…
61205 …t the packet will be sent to MCP and not BMC. The bits in this register correspond to the bits in …
61206 …t the packet will be sent to MCP and not BMC. The bits in this register correspond to the bits in …
61207 … 0x50d400UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
61209 … 0x50d800UL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
61212 …/Access:R DataWidth:0x1 // This register marks that the out of order FIFO in the LLH is full.
61213 …/Access:R DataWidth:0x1 // This register marks that the out of order FIFO in the LLH is full.
61253 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
61254 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
61259 …uested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
61261 …r when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
61263 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
61265 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
61267 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
61269 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
61271 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
61273 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
61279 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
61281 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
61283 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
61287 …31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. When unifi…
61325 …uested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
61327 …r when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
61329 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
61331 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
61333 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
61335 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
61337 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
61339 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
61345 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
61347 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
61349 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
61353 …31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. When unifi…
61358 …uested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
61360 …r when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
61362 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
61364 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
61366 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
61368 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
61370 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
61372 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
61378 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
61380 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
61382 …it connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write in…
61386 …31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. When unifi…
61389 … (0x1<<1) // Calculations error in LL arbiter block.
61391 … (0x1<<3) // Input FIFO error in write client 0.
61393 … (0x1<<4) // SOP FIFO error in write client 0.
61395 … (0x1<<5) // LEN FIFO error in write client 0.
61397 … (0x1<<7) // Queue FIFO error in write client 0.
61399 … (0x1<<8) // Free ointer FIFO error in write client 0.
61401 … (0x1<<9) // Next pointer FIFO error in write client 0.
61403 … (0x1<<10) // Start FIFO error in write client 0.
61405 … (0x1<<11) // Second descriptor FIFO error in write client 0.
61407 … (0x1<<12) // Packet available FIFO error in write client 0.
61409 … (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Co…
61411 … (0x1<<14) // Notify FIFO error in write client 0.
61413 … (0x1<<15) // LL req error in write client 0.
61419 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/R…
61421 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX…
61423 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/R…
61425 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT:…
61427 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT:…
61429 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/R…
61431 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_I…
61433 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_IN…
61435 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT:…
61437 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/R…
61439 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_…
61441 … bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to l…
61443 …nection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram o…
61503 … (0x1<<1) // Calculations error in LL arbiter block.
61505 … (0x1<<3) // Input FIFO error in write client 0.
61507 … (0x1<<4) // SOP FIFO error in write client 0.
61509 … (0x1<<5) // LEN FIFO error in write client 0.
61511 … (0x1<<7) // Queue FIFO error in write client 0.
61513 … (0x1<<8) // Free ointer FIFO error in write client 0.
61515 … (0x1<<9) // Next pointer FIFO error in write client 0.
61517 … (0x1<<10) // Start FIFO error in write client 0.
61519 … (0x1<<11) // Second descriptor FIFO error in write client 0.
61521 … (0x1<<12) // Packet available FIFO error in write client 0.
61523 … (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Co…
61525 … (0x1<<14) // Notify FIFO error in write client 0.
61527 … (0x1<<15) // LL req error in write client 0.
61533 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/R…
61535 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX…
61537 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/R…
61539 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT:…
61541 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT:…
61543 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/R…
61545 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_I…
61547 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_IN…
61549 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT:…
61551 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/R…
61553 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_…
61555 … bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to l…
61557 …nection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram o…
61560 … (0x1<<1) // Calculations error in LL arbiter block.
61562 … (0x1<<3) // Input FIFO error in write client 0.
61564 … (0x1<<4) // SOP FIFO error in write client 0.
61566 … (0x1<<5) // LEN FIFO error in write client 0.
61568 … (0x1<<7) // Queue FIFO error in write client 0.
61570 … (0x1<<8) // Free ointer FIFO error in write client 0.
61572 … (0x1<<9) // Next pointer FIFO error in write client 0.
61574 … (0x1<<10) // Start FIFO error in write client 0.
61576 … (0x1<<11) // Second descriptor FIFO error in write client 0.
61578 … (0x1<<12) // Packet available FIFO error in write client 0.
61580 … (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Co…
61582 … (0x1<<14) // Notify FIFO error in write client 0.
61584 … (0x1<<15) // LL req error in write client 0.
61590 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/R…
61592 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX…
61594 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/R…
61596 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT:…
61598 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT:…
61600 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/R…
61602 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_I…
61604 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_IN…
61606 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT:…
61608 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/R…
61610 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_…
61612 … bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to l…
61614 …nection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram o…
61617 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/R…
61619 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX…
61621 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/R…
61623 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT:…
61625 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT:…
61627 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/R…
61629 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_I…
61631 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_IN…
61633 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT:…
61635 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/R…
61637 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_…
61639 …ection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list …
61641 …or E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP des…
61643 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/R…
61645 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX…
61647 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/R…
61649 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT:…
61651 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT:…
61653 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/R…
61655 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_I…
61657 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_IN…
61659 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT:…
61661 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/R…
61663 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_…
61665 …ection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list …
61667 …or E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP des…
61723 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/R…
61725 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX…
61727 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/R…
61729 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT:…
61731 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT:…
61733 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/R…
61735 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_I…
61737 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_IN…
61739 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT:…
61741 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/R…
61743 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_…
61745 …ection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list …
61747 …or E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP des…
61749 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/R…
61751 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX…
61753 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/R…
61755 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT:…
61757 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT:…
61759 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/R…
61761 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_I…
61763 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_IN…
61765 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT:…
61767 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/R…
61769 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_…
61771 …ection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list …
61773 …or E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP des…
61776 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/R…
61778 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX…
61780 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/R…
61782 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT:…
61784 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT:…
61786 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/R…
61788 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_I…
61790 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_IN…
61792 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT:…
61794 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/R…
61796 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_…
61798 …ection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list …
61800 …or E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP des…
61802 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/R…
61804 … Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX…
61806 …Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/R…
61808 …ning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT:…
61810 …ing! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT:…
61812 …Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/R…
61814 …g! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_I…
61816 …g! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_IN…
61818 …ning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT:…
61820 …arning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/R…
61822 …/ Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_…
61824 …ection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list …
61826 …or E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP des…
61829 … (0x1<<1) // Read packet client rc0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61831 … (0x1<<2) // Read packet client rc0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61833 … (0x1<<3) // Read packet client rc0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61835 … (0x1<<4) // Read packet client rc0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61837 … (0x1<<5) // Read packet client rc0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61839 … (0x1<<6) // Read packet client rc0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61841 … (0x1<<7) // Read packet client rc0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61843 … (0x1<<8) // Read packet client rc0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61845 … (0x1<<9) // Read packet client rc1 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61847 … (0x1<<10) // Read packet client rc1 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61849 … (0x1<<11) // Read packet client rc1 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61851 … (0x1<<12) // Read packet client rc1 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61853 … (0x1<<13) // Read packet client rc1 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61855 … (0x1<<14) // Read packet client rc1 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61857 … (0x1<<15) // Read packet client rc1 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61859 … (0x1<<16) // Read packet client rc1 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61861 … (0x1<<17) // Read packet client rc2 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61863 … (0x1<<18) // Read packet client rc2 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61865 … (0x1<<19) // Read packet client rc2 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61867 … (0x1<<20) // Read packet client rc2 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61869 … (0x1<<21) // Read packet client rc2 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61871 … (0x1<<22) // Read packet client rc2 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61873 … (0x1<<23) // Read packet client rc2 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61875 … (0x1<<24) // Read packet client rc2 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61877 … (0x1<<25) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61879 … (0x1<<26) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61881 … (0x1<<27) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61883 …(0x1<<28) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61885 …(0x1<<29) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61887 …0x1<<30) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61889 … (0x1<<31) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61955 … (0x1<<1) // Read packet client rc0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61957 … (0x1<<2) // Read packet client rc0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61959 … (0x1<<3) // Read packet client rc0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61961 … (0x1<<4) // Read packet client rc0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61963 … (0x1<<5) // Read packet client rc0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61965 … (0x1<<6) // Read packet client rc0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61967 … (0x1<<7) // Read packet client rc0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61969 … (0x1<<8) // Read packet client rc0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61971 … (0x1<<9) // Read packet client rc1 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61973 … (0x1<<10) // Read packet client rc1 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61975 … (0x1<<11) // Read packet client rc1 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61977 … (0x1<<12) // Read packet client rc1 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61979 … (0x1<<13) // Read packet client rc1 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61981 … (0x1<<14) // Read packet client rc1 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61983 … (0x1<<15) // Read packet client rc1 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61985 … (0x1<<16) // Read packet client rc1 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61987 … (0x1<<17) // Read packet client rc2 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61989 … (0x1<<18) // Read packet client rc2 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61991 … (0x1<<19) // Read packet client rc2 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61993 … (0x1<<20) // Read packet client rc2 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61995 … (0x1<<21) // Read packet client rc2 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61997 … (0x1<<22) // Read packet client rc2 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61999 … (0x1<<23) // Read packet client rc2 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
62001 … (0x1<<24) // Read packet client rc2 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
62003 … (0x1<<25) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62005 … (0x1<<26) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62007 … (0x1<<27) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62009 …(0x1<<28) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62011 …(0x1<<29) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62013 …0x1<<30) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62015 … (0x1<<31) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62018 … (0x1<<1) // Read packet client rc0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
62020 … (0x1<<2) // Read packet client rc0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
62022 … (0x1<<3) // Read packet client rc0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
62024 … (0x1<<4) // Read packet client rc0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
62026 … (0x1<<5) // Read packet client rc0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
62028 … (0x1<<6) // Read packet client rc0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
62030 … (0x1<<7) // Read packet client rc0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
62032 … (0x1<<8) // Read packet client rc0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
62034 … (0x1<<9) // Read packet client rc1 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
62036 … (0x1<<10) // Read packet client rc1 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
62038 … (0x1<<11) // Read packet client rc1 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
62040 … (0x1<<12) // Read packet client rc1 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
62042 … (0x1<<13) // Read packet client rc1 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
62044 … (0x1<<14) // Read packet client rc1 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
62046 … (0x1<<15) // Read packet client rc1 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
62048 … (0x1<<16) // Read packet client rc1 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
62050 … (0x1<<17) // Read packet client rc2 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
62052 … (0x1<<18) // Read packet client rc2 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
62054 … (0x1<<19) // Read packet client rc2 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
62056 … (0x1<<20) // Read packet client rc2 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
62058 … (0x1<<21) // Read packet client rc2 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
62060 … (0x1<<22) // Read packet client rc2 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
62062 … (0x1<<23) // Read packet client rc2 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
62064 … (0x1<<24) // Read packet client rc2 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
62066 … (0x1<<25) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62068 … (0x1<<26) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62070 … (0x1<<27) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62072 …(0x1<<28) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62074 …(0x1<<29) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62076 …0x1<<30) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62078 … (0x1<<31) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62081 … (0x1<<0) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62083 … (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
62085 … (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
62087 … (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
62115 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
62117 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
62119 … (0x1<<24) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62121 … (0x1<<25) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62123 … (0x1<<26) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62125 …(0x1<<27) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62127 …(0x1<<28) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62129 …0x1<<29) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62131 … (0x1<<30) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62133 … (0x1<<31) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62191 … (0x1<<0) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62193 … (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
62195 … (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
62197 … (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
62225 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
62227 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
62229 … (0x1<<24) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62231 … (0x1<<25) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62233 … (0x1<<26) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62235 …(0x1<<27) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62237 …(0x1<<28) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62239 …0x1<<29) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62241 … (0x1<<30) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62243 … (0x1<<31) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62246 … (0x1<<0) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62248 … (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
62250 … (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
62252 … (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
62280 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
62282 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
62284 … (0x1<<24) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62286 … (0x1<<25) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62288 … (0x1<<26) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62290 …(0x1<<27) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62292 …(0x1<<28) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62294 …0x1<<29) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62296 … (0x1<<30) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62298 … (0x1<<31) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
62579 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62581 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62583 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62585 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62587 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62589 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62591 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/R…
62593 … (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
62595 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
62701 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62703 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62705 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62707 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62709 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62711 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62713 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/R…
62715 … (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
62717 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
62762 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62764 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62766 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62768 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62770 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62772 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Write packet er…
62774 …Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/R…
62776 … (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
62778 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
62781 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
62783 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
62785 … (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
62787 …(0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
62789 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
62791 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
62793 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
62795 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
62797 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
62799 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
62801 … (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
62803 … (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
62805 … (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
62807 … (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
62809 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
62811 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
62813 …0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
62815 …0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
62817 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
62819 … (0x1<<19) // Notify FIFO error in write client 5
62821 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
62823 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
62825 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
62827 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
62829 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
62831 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
62833 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
62835 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
62837 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
62839 …0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
62841 …0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
62843 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
62911 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
62913 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
62915 … (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
62917 …(0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
62919 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
62921 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
62923 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
62925 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
62927 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
62929 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
62931 … (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
62933 … (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
62935 … (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
62937 … (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
62939 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
62941 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
62943 …0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
62945 …0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
62947 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
62949 … (0x1<<19) // Notify FIFO error in write client 5
62951 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
62953 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
62955 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
62957 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
62959 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
62961 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
62963 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
62965 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
62967 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
62969 …0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
62971 …0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
62973 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
62976 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
62978 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
62980 … (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
62982 …(0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
62984 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
62986 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
62988 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
62990 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
62992 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
62994 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
62996 … (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
62998 … (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
63000 … (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
63002 … (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
63004 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
63006 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
63008 …0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
63010 …0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
63012 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
63014 … (0x1<<19) // Notify FIFO error in write client 5
63016 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
63018 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
63020 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
63022 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
63024 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
63026 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
63028 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
63030 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
63032 … (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
63034 …0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
63036 …0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
63038 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
63041 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
63043 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
63045 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
63047 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
63049 … (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
63051 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
63053 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
63055 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
63057 … (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
63059 … (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
63061 …0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
63063 …0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
63065 … (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
63067 … (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
63069 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
63071 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
63073 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
63075 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
63077 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
63079 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
63081 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
63083 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
63085 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
63087 …0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
63089 …0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
63091 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
63093 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
63095 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
63097 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
63099 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
63101 … (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
63103 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
63171 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
63173 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
63175 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
63177 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
63179 … (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
63181 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
63183 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
63185 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
63187 … (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
63189 … (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
63191 …0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
63193 …0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
63195 … (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
63197 … (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
63199 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
63201 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
63203 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
63205 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
63207 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
63209 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
63211 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
63213 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
63215 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
63217 …0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
63219 …0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
63221 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
63223 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
63225 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
63227 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
63229 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
63231 … (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
63233 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
63236 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
63238 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
63240 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
63242 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
63244 … (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
63246 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
63248 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
63250 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
63252 … (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
63254 … (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
63256 …0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
63258 …0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
63260 … (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
63262 … (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
63264 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
63266 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
63268 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
63270 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
63272 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
63274 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
63276 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
63278 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
63280 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
63282 …0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
63284 …0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
63286 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
63288 … (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
63290 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
63292 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
63294 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
63296 … (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write c…
63298 … (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write cl…
63301 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
63303 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
63305 … (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
63307 … (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
63309 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
63311 …(0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
63313 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
63315 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
63317 … (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
63319 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
63321 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
63451 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
63453 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
63455 … (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
63457 … (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
63459 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
63461 …(0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
63463 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
63465 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
63467 … (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
63469 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
63471 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
63526 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
63528 … (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in writ…
63530 … (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in writ…
63532 … (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write c…
63534 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in w…
63536 …(0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in wr…
63538 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in writ…
63540 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
63542 … (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write cli…
63544 …heck this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requ…
63546 …s bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to …
63645 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC F…
63647 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC F…
63667 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC F…
63669 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC F…
63678 … (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC F…
63680 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC F…
63886 … // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[0].i_bb_bank.i_ecc in module bmb_bb_bank
63888 … // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[1].i_bb_bank.i_ecc in module bmb_bb_bank
63890 … // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[2].i_bb_bank.i_ecc in module bmb_bb_bank
63892 … // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[3].i_bb_bank.i_ecc in module bmb_bb_bank
63894 … // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[4].i_bb_bank.i_ecc in module bmb_bb_bank
63896 … // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[5].i_bb_bank.i_ecc in module bmb_bb_bank
63898 … // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[6].i_bb_bank.i_ecc in module bmb_bb_bank
63900 … // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[7].i_bb_bank.i_ecc in module bmb_bb_bank
63902 … // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[8].i_bb_bank.i_ecc in module bmb_bb_bank
63904 … // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[9].i_bb_bank.i_ecc in module bmb_bb_bank
63906 …// Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[10].i_bb_bank.i_ecc in module bmb_bb_bank
63908 …// Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[11].i_bb_bank.i_ecc in module bmb_bb_bank
63910 …// Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[12].i_bb_bank.i_ecc in module bmb_bb_bank
63912 …// Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[13].i_bb_bank.i_ecc in module bmb_bb_bank
63914 …// Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[14].i_bb_bank.i_ecc in module bmb_bb_bank
63916 …// Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[15].i_bb_bank.i_ecc in module bmb_bb_bank
63919 …et parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[0].i_bb_bank.i_ecc in module bmb_bb_bank
63921 …et parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[1].i_bb_bank.i_ecc in module bmb_bb_bank
63923 …et parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[2].i_bb_bank.i_ecc in module bmb_bb_bank
63925 …et parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[3].i_bb_bank.i_ecc in module bmb_bb_bank
63927 …et parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[4].i_bb_bank.i_ecc in module bmb_bb_bank
63929 …et parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[5].i_bb_bank.i_ecc in module bmb_bb_bank
63931 …et parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[6].i_bb_bank.i_ecc in module bmb_bb_bank
63933 …et parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[7].i_bb_bank.i_ecc in module bmb_bb_bank
63935 …et parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[8].i_bb_bank.i_ecc in module bmb_bb_bank
63937 …et parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[9].i_bb_bank.i_ecc in module bmb_bb_bank
63939 …t parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[10].i_bb_bank.i_ecc in module bmb_bb_bank
63941 …t parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[11].i_bb_bank.i_ecc in module bmb_bb_bank
63943 …t parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[12].i_bb_bank.i_ecc in module bmb_bb_bank
63945 …t parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[13].i_bb_bank.i_ecc in module bmb_bb_bank
63947 …t parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[14].i_bb_bank.i_ecc in module bmb_bb_bank
63949 …t parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[15].i_bb_bank.i_ecc in module bmb_bb_bank
63952 … error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[0].i_bb_bank.i_ecc in module bmb_bb_bank
63954 … error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[1].i_bb_bank.i_ecc in module bmb_bb_bank
63956 … error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[2].i_bb_bank.i_ecc in module bmb_bb_bank
63958 … error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[3].i_bb_bank.i_ecc in module bmb_bb_bank
63960 … error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[4].i_bb_bank.i_ecc in module bmb_bb_bank
63962 … error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[5].i_bb_bank.i_ecc in module bmb_bb_bank
63964 … error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[6].i_bb_bank.i_ecc in module bmb_bb_bank
63966 … error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[7].i_bb_bank.i_ecc in module bmb_bb_bank
63968 … error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[8].i_bb_bank.i_ecc in module bmb_bb_bank
63970 … error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[9].i_bb_bank.i_ecc in module bmb_bb_bank
63972 …error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[10].i_bb_bank.i_ecc in module bmb_bb_bank
63974 …error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[11].i_bb_bank.i_ecc in module bmb_bb_bank
63976 …error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[12].i_bb_bank.i_ecc in module bmb_bb_bank
63978 …error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[13].i_bb_bank.i_ecc in module bmb_bb_bank
63980 …error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[14].i_bb_bank.i_ecc in module bmb_bb_bank
63982 …error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[15].i_bb_bank.i_ecc in module bmb_bb_bank
63985 …f big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data…
63986 …in header in 16-bytes resolution. After this number of bytes will input to BRTB will be sent packe…
63987 …s:RW DataWidth:0xb // Head pointer to each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
63989 …s:RW DataWidth:0xb // Tail pointer of each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
63991 …ccess:RW DataWidth:0xb // Number of free blocks in each one of 4 free lists::s/BLK_WDTH/13/g …
63993 …MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_REQ/required/g in R…
63994 …till reset in a case of length error other way it will continue to work as usual.::s/STOP_LEN_ERR_…
63995 …- SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for…
63996 …s. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/TOTAL_MAC_RST/240…
63997 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
63998 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
63999 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
64000 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
64001 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
64002 …in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B bl…
64003 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
64004 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
64005 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
64006 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
64007 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
64008 …in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256…
64009 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64010 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64011 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64012 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64013 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64014 …- the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the…
64015 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64016 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64017 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64018 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64019 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64020 …- the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for …
64021 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64022 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64023 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64024 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64025 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64026 …- the number of free blocks in the shared and headroom areas below which FULL is asserted for the …
64027 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64033 …O_DEAD_CYCLE_RST/1/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/…
64035 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
64037 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
64039 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
64041 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
64043 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
64045 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
64047 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
64049 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
64051 …ed in link list and big ram arbiters. If all read clients have identical priority then selection b…
64053 …ed in link list and big ram arbiters. If all read clients have identical priority then selection b…
64055 …hen packet will be written without intra packet dead cycles .TBD ::s/NO_DEAD_CYCLE_RST/1/g in Reset
64056 … priority mechanism is enabled for the corresponding client. TBD ::s/NO_DEAD_CYCLE_RST/1/g in Reset
64057 …ad client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_SOP_PRI_RST/5/g…
64058 …ient group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7/g…
64059 …ntical priority is supported. Possible values are 1-3. Priority 3 is highest::s/RC_MULT_PRI_RST/6/…
64066 …ient upper which full outputs to this write client interface.::s/DSCR_FIFO_RST/12/g in Reset Value.
64067 …ient upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.
64069 …ger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g i…
64076 …dth:0x4 // Debug only: If more than this Number of entries are occupied in the dbgsyn clock syn…
64080 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
64089 …INUS_SOP_EN/4/g in Data Width::s/RC_PKT_INP_IF_RST/15/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PR…
64093 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
64096 …_PKT_OUT_IF_RST/31/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/…
64100 …fter init procedure. ::s/SHARE_GRP_CNT/2/g in Data Width::s/SHARE_GRP_INIT/3/g in Reset Value::/PA…
64104 …erface will never be set. This bit should be set after init procedure. ::/EMPTY_EN/d in Existance.
64106 …0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits s…
64107 …0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits s…
64108 …0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits s…
64109 …0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits s…
64110 …0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits s…
64111 …0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits s…
64112 …0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits s…
64113 …0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits s…
64114 …0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits s…
64115 …0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits s…
64126 …ch write client because of temporal bandwidth problem on interface::s/WC_NUM_MAX/4/g in Data Width.
64127 …/ Debug register. Full status of each read packet client interface::s/PKT_RC_NUM/5/g in Data Width.
64128 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
64129 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
64130 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
64131 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
64132 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
64133 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
64134 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
64135 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
64136 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
64137 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
64138 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
64139 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
64140 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
64141 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
64142 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
64143 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
64144 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
64145 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
64146 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
64147 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
64148 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64149 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64150 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64151 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64152 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64153 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64154 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64155 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64156 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64157 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64158 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64159 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64160 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
64238 …/ Debug register. This is state machine for each read client. ::s/PKT_RC_NUM_ST/20/g in Data Width.
64240 … areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g …
64241 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
64242 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
64243 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
64244 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
64245 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
64246 …of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in …
64247 …valid. ::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g …
64248 …put pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in…
64249 …tput full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in…
64250 …is written in big_ram_address register. Read from 32 LSB bits of this register will generate read …
64252 …- valid; b30:16 - queue size; b15:0 - queue start pointer::s/SOP_STATUS_RST/536805376/g in Reset V…
64254 …s register for each erad packet client interface: TBD. Message spelling (MSB->LSB): rest_size_erro…
64257 …s register for each read packet client interface: TBD. Message spelling (MSB->LSB): opaque[1:0]; r…
64280 …ry that contains per-block descriptor::s/BLK_NUM/4800/g in memory size::s/BLK_WDTH_PLUS_SOP_EN/14/…
64285 … 0x560000UL //Access:RW DataWidth:0x1 // Initiate the ATC array - reset all the valid …
64287 …taWidth:0x20 // Logging register for reuse miss on transpend entry [31:0] - TID of the problemat…
64288 …taWidth:0x1c // Logging register for reuse miss on transpend entry [27:0] - ATC page index of th…
64289 …reuse miss on transpend entry [11:0] - Reuse count of the problematic lookuprequest [23:12] - Reus…
64290 …ster for the case of invalidation halt (lkpres of invalidated range) [31:0] - TID of the problemat…
64291 …ster for the case of invalidation halt (lkpres of invalidated range) [27:0] - ATC page index of th…
64292 …ster for the case of invalidation halt (lkpres of invalidated range) [11:0] - Reuse count of the p…
64294 …s of the PXP read requests issued by the PTU logic. [0:8] - ST index; [10:9] - ST hint; [11] - ST …
64298 … 0x56006cUL //Access:RW DataWidth:0x5 // Page size in the PBL table, neede…
64301 … 0x560078UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per PF.
64302 …sk for the invalidated TID. Shows which of the TID bits should be compared in the invalidation flo…
64303 …the data in inv_tid and inv_tid_mask is valid and invalidation should take place. When invalidatio…
64304 …aWidth:0x1 // Bit per PF. Indicates that the marked invalidation is done - when read it is also…
64305 …in case it gets PTU requests to an address belongs to a range which is currently invalidated; if r…
64306 … 0x56008cUL //Access:RW DataWidth:0x1 // When set - the block will halt in case reus…
64307 … 0x560090UL //Access:RW DataWidth:0x3 // Max credits of the PBF->PXP interface.
64308 … 0x560094UL //Access:RW DataWidth:0x3 // Max credits of the PRM->PXP interface.
64309 … 0x560098UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64310 … 0x56009cUL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64311 … 0x5600a0UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64320 …-asserted then low priority request will replace a high priority entry only if there are no low pr…
64328 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
64339 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64341 … (0x1<<2) // Several hits in the GPA for the same…
64373 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64375 … (0x1<<2) // Several hits in the GPA for the same…
64390 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64392 … (0x1<<2) // Several hits in the GPA for the same…
64473 … DataWidth:0x1 // Enable ECC for memory ecc instance ptu.i_ram_spa.i_ecc in module ptu_spa_ram
64474 …taWidth:0x1 // Set parity only for memory ecc instance ptu.i_ram_spa.i_ecc in module ptu_spa_ram
64475 …rd if a correctable error occurred on memory ecc instance ptu.i_ram_spa.i_ecc in module ptu_spa_ram
64477 …00UL //Access:RW DataWidth:0x2 // Defines the number of sets - 3 - 512 ;2- 256; 1- 128; 0- 64.
64483 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64484 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64485 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64486 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64487 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64488 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64489 …tall in case of 2 consecutive accesses to the same set (on the second event). The order of the vec…
64490 …tall in case of 2 consecutive accesses to the same set (on the second event). The order of the vec…
64491 …tall in case of 2 consecutive accesses to the same set (on the second event). The order of the vec…
64492 …tall in case of 2 consecutive accesses to the same set (on the second event). The order of the vec…
64493 …tall in case of 2 consecutive accesses to the same set (on the second event). The order of the vec…
64494 …tall in case of 2 consecutive accesses to the same set (on the second event). The order of the vec…
64496 … 0x56044cUL //Access:RW DataWidth:0x1 // Issue event once in four cycles (instead…
64508 …dth:0x7 // Defines the number of entries in the OTB when 31 indicates 32 entries (entries count…
64509 … 0x560480UL //Access:RW DataWidth:0x1 // CheckTags configuration bit - when set the availab…
64510 … 0x560484UL //Access:RW DataWidth:0x8 // TAG threshold - for the checkTags fe…
64523 … 0x5604b8UL //Access:RC DataWidth:0x20 // Number of hits for Main-lookups in the ATC.
64524 … 0x5604bcUL //Access:RC DataWidth:0x20 // Number of Main lookups in the ATC.
64525 … 0x5604c0UL //Access:RC DataWidth:0x20 // Number of treqs issued due to pre-lookup.
64526 … 0x5604c4UL //Access:RC DataWidth:0x20 // Number of Pre Lookps in the ATC.
64569 … 0x560570UL //Access:RW DataWidth:0x5 // In case of TCPL with er…
64570 … 0x560574UL //Access:RW DataWidth:0x5 // In case of TCPL with er…
64572 … //Access:R DataWidth:0x20 // Data belongs to an erroneous TCPL: [31:0]-bits [31:0] of the ad…
64573 … //Access:R DataWidth:0x14 // Data belongs to an erroneous TCPL: [19:0]-bits [51:32] of the a…
64578 … 0x560594UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 31-0.
64579 … 0x560598UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 63-32.
64580 … 0x56059cUL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 95-64.
64581 … 0x5605a0UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 127-96.
64582 … 0x5605a4UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 159-128.
64583 … 0x5605a8UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 191-160.
64584 … 0x5605acUL //Access:R DataWidth:0x10 // Indicates the end of FLI flow for PF 15-0.
64585 …b0UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 31-0 accordingly.
64586 …b4UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 63-32 accordingly.
64587 …8UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 95-64 accordingly.
64588 …cUL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 127-96 accordingly.
64589 …L //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 159-128 accordingly.
64590 …UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 191-160 accordingly.
64591 …c8UL //Access:RW DataWidth:0x10 // Clears the FLI done indication for PF bits 15-0 accordingly.
64592 …dth:0x4 // Debug only: If more than this Number of entries are occupied in the dbgsyn clock syn…
64610 …605e4UL //Access:RW DataWidth:0x8 // Resource Type of the invalidated range - register per PF.
64611 … invalidated RSC Type. Shows which of the RSC Type bits should be compared in the invalidation flo…
64612 …er for the case of invalidation halt (lkpres of invalidated range) [7:0] - Resource type of the…
64614 …x8 // Logging register for reuse miss on transpend entry bits [35:28] - of the problematic r…
64615 …Width:0x8 // Logging register for reuse miss on transpend entry [7:0] - Resource type of the…
64617 … 0x560600UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per Strom.
64619 …sk for the invalidated TID. Shows which of the TID bits should be compared in the invalidation flo…
64621 … 0x560640UL //Access:RW DataWidth:0x8 // TID of the invalidated range - register per Storm.
64623 …sk for the invalidated TID. Shows which of the TID bits should be compared in the invalidation flo…
64625 …the data in inv_tid and inv_tid_mask is valid and invalidation should take place. When invalidatio…
64627 …dth:0x1 // Bit per Storm. Indicates that the marked invalidation is done - when read it is also…
64629 …in case it gets PTU requests to an address belongs to a range which is currently invalidated; if r…
64631 …x40 // Access the GPA table way 0; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64633 …x40 // Access the GPA table way 1; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64635 …x40 // Access the GPA table way 2; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64639 …h:0x40 // Access the GPA table way3; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID-…
64641 …- {par - [51]; NS bit - [50]; W bit - [49]; R bit - [48]; U bit - [47]; Priority bit - [46]; PLRU …
64643 … // Access the GPA table way 0; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64645 … // Access the GPA table way 1; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64647 … // Access the GPA table way 2; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64649 … // Access the GPA table way3; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64651 …- { Priority bit - [23]; PLRU - [22]; Err bit - [21]; invpend bit [20]; transpend bit - [19]; vali…
64658 … (0x1<<1) // Enables CDU Inputs -- Must be set for norm…
64660 … (0x1<<2) // Enables CDU Outputs -- Must be set for nor…
64668 …<6) // Masks all PCIE Errors for Load transactions. NOTE -- This is not connected in E4 A0.
64673 …CFC Load Request exceeds total number of L1s allowed. Error data is logged in the ccfc_ld_l1_num_e…
64675 …CFC Load Request exceeds total number of L1s allowed. Error data is logged in the tcfc_ld_l1_num_e…
64677 …riteBack Request exceeds total number of L1s allowed. Error data is logged in the ccfc_wb_l1_num_e…
64679 …riteBack Request exceeds total number of L1s allowed. Error data is logged in the tcfc_wb_l1_num_e…
64681 … (0x1<<5) // Context or Active Validation error in CCFC Load Datapath. Error data is logged i…
64683 … (0x1<<6) // Context or Active Validation error in CCFC Load Datapath. Error data is logged i…
64690 …CFC Load Request exceeds total number of L1s allowed. Error data is logged in the ccfc_ld_l1_num_e…
64692 …CFC Load Request exceeds total number of L1s allowed. Error data is logged in the tcfc_ld_l1_num_e…
64694 …riteBack Request exceeds total number of L1s allowed. Error data is logged in the ccfc_wb_l1_num_e…
64696 …riteBack Request exceeds total number of L1s allowed. Error data is logged in the tcfc_wb_l1_num_e…
64698 … (0x1<<5) // Context or Active Validation error in CCFC Load Datapath. Error data is logged i…
64700 … (0x1<<6) // Context or Active Validation error in CCFC Load Datapath. Error data is logged i…
64707 …CFC Load Request exceeds total number of L1s allowed. Error data is logged in the ccfc_ld_l1_num_e…
64709 …CFC Load Request exceeds total number of L1s allowed. Error data is logged in the tcfc_ld_l1_num_e…
64711 …riteBack Request exceeds total number of L1s allowed. Error data is logged in the ccfc_wb_l1_num_e…
64713 …riteBack Request exceeds total number of L1s allowed. Error data is logged in the tcfc_wb_l1_num_e…
64715 … (0x1<<5) // Context or Active Validation error in CCFC Load Datapath. Error data is logged i…
64717 … (0x1<<6) // Context or Active Validation error in CCFC Load Datapath. Error data is logged i…
64755 …n for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64757 …n for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64759 …n for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64761 …n for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64764 …n for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64766 …n for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64768 …n for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64770 …n for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64773 …n for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64775 …n for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64777 …n for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64779 …n for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64782 …n for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64784 …n for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64786 …n for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64788 …n for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64790 …l signal to PXP. This register must never be set higher than 8 -- doing so will result in FIFO ove…
64791 …ast this limit. This register must never be set higher than 13 -- doing so will result in data cor…
64850 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
64865 … 0x580808UL //Access:R DataWidth:0x19 // Logging of error data in case of a CCFC Load …
64866 … 0x58080cUL //Access:R DataWidth:0x19 // Logging of error data in case of a TCFC Load …
64867 … 0x580810UL //Access:R DataWidth:0x19 // Logging of error data in case of a CCFC Write…
64868 … 0x580814UL //Access:R DataWidth:0x19 // Logging of error data in case of a TCFC Write…
64872 … (0xfff<<12) // Block waste within a page. this number equals to PageSize-NCIB*ContextSize.
64874 … (0xff<<24) // Number of CIDs in Block.
64881 … (0xff<<16) // Number of Waste locations per TID Block (in Qwords) (Type0).
64883 … (0xff<<24) // Size of TID (in Qwords) (Type0).
64890 … (0xff<<16) // Number of Waste locations per TID Block (in Qwords) (Type1).
64892 … (0xff<<24) // Size of TID (in Qwords) (Type1).
64894 … 0x58090cUL //Access:RW DataWidth:0x12 // Start Offset for this Segment (in 32KB pages).
64895 … 0x580910UL //Access:RW DataWidth:0x12 // Start Offset for this Segment (in 32KB pages).
64896 … 0x580914UL //Access:RW DataWidth:0x12 // Start Offset for this Segment (in 32KB pages).
64897 … 0x580918UL //Access:RW DataWidth:0x12 // Start Offset for this Segment (in 32KB pages).
64898 …8091cUL //Access:RW DataWidth:0x12 // Force Load Start Offset for this Segment (in 32KB pages).
64899 …80920UL //Access:RW DataWidth:0x12 // Force Load Start Offset for this Segment (in 32KB pages).
64900 …80924UL //Access:RW DataWidth:0x12 // Force Load Start Offset for this Segment (in 32KB pages).
64901 …80928UL //Access:RW DataWidth:0x12 // Force Load Start Offset for this Segment (in 32KB pages).
64902 … 0x58092cUL //Access:RW DataWidth:0x12 // VF Start Offset for this Segment (in 32KB pages).
64903 …30UL //Access:RW DataWidth:0xd // VF Force Load Start Offset for this Segment (in 32KB pages).
64904 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64910 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64911 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64922 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64923 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64924 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64925 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64926 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64927 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64928 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64929 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64930 …0x5a0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64931 …0x5a0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64932 …0x5a0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64933 …0x5a003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64936 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
64945 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64947 … (0x1<<3) // Mini cache error - meaning that A load …
64949 … (0x1<<4) // Mini cache error - meaning that A load …
64971 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64973 … (0x1<<3) // Mini cache error - meaning that A load …
64975 … (0x1<<4) // Mini cache error - meaning that A load …
64984 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64986 … (0x1<<3) // Mini cache error - meaning that A load …
64988 … (0x1<<4) // Mini cache error - meaning that A load …
65009 …taWidth:0x1 // Enable ECC for memory ecc instance ptld.i_msgq_ram.i_ecc in module ptld_i_msgq_r…
65010 …th:0x1 // Set parity only for memory ecc instance ptld.i_msgq_ram.i_ecc in module ptld_i_msgq_r…
65011 … a correctable error occurred on memory ecc instance ptld.i_msgq_ram.i_ecc in module ptld_i_msgq_r…
65013 … 0x5a0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65018 …in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this config…
65020 … (0x1<<2) // defines that only back-to-back aggregation is …
65029 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
65031 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
65033 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
65035 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
65037 …0x5a0808UL //Access:RW DataWidth:0x10 // Limit the number of �packets� in the Loader according…
65039 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
65041 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
65043 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
65045 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
65048 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
65050 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
65052 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
65054 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
65057 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
65059 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
65061 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
65063 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
65066 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
65068 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
65070 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
65072 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
65075 … (0xf<<0) // length in 32b units from the s…
65077 … (0xf<<4) // length in 32b units from the s…
65079 … (0xf<<8) // length in 32b units from the s…
65081 … (0xf<<12) // length in 32b units from the s…
65083 … (0xf<<16) // length in 32b units from the s…
65085 … (0xf<<20) // length in 32b units from the s…
65087 … (0xf<<24) // length in 32b units from the s…
65089 … (0xf<<28) // length in 32b units from the s…
65092 … (0xf<<0) // length in 32b units from the s…
65094 … (0xf<<4) // length in 32b units from the s…
65096 … (0xf<<8) // length in 32b units from the s…
65098 … (0xf<<12) // length in 32b units from the s…
65100 … (0xf<<16) // length in 32b units from the s…
65102 … (0xf<<20) // length in 32b units from the s…
65104 … (0xf<<24) // length in 32b units from the s…
65106 … (0xf<<28) // length in 32b units from the s…
65108 … 0x5a0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65109 … 0x5a0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65110 … 0x5a082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65111 … 0x5a0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65112 … 0x5a0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65113 … 0x5a0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65114 … 0x5a083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65115 … 0x5a0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65116 … 0x5a0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65117 … 0x5a0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65118 … 0x5a084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65119 … 0x5a0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65120 … 0x5a0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65121 … 0x5a0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65122 … 0x5a085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65123 … 0x5a0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65124 … 0x5a0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65125 … 0x5a0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65126 … 0x5a086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65127 … 0x5a0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65128 … 0x5a0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65129 … 0x5a0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65130 … 0x5a087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65131 … 0x5a0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65132 … 0x5a0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65133 … 0x5a0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65134 … 0x5a088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65135 … 0x5a0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65136 … 0x5a0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65137 … 0x5a0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65138 … 0x5a089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65139 … 0x5a08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65141 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
65143 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
65145 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
65147 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
65150 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
65152 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
65154 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
65156 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
65159 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
65161 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
65163 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
65165 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
65168 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
65170 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
65172 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
65174 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
65177 … (0x3f<<0) // length in 32b units from the d…
65179 … (0x3f<<6) // length in 32b units from the d…
65181 … (0x3f<<12) // length in 32b units from the d…
65183 … (0x3f<<18) // length in 32b units from the d…
65186 … (0x3f<<0) // length in 32b units from the d…
65188 … (0x3f<<6) // length in 32b units from the d…
65190 … (0x3f<<12) // length in 32b units from the d…
65192 … (0x3f<<18) // length in 32b units from the d…
65195 … (0x3f<<0) // length in 32b units from the d…
65197 … (0x3f<<6) // length in 32b units from the d…
65199 … (0x3f<<12) // length in 32b units from the d…
65201 … (0x3f<<18) // length in 32b units from the d…
65204 … (0x3f<<0) // length in 32b units from the d…
65206 … (0x3f<<6) // length in 32b units from the d…
65208 … (0x3f<<12) // length in 32b units from the d…
65210 … (0x3f<<18) // length in 32b units from the d…
65213 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
65215 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
65217 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
65219 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
65221 … (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
65223 … (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
65225 … (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
65227 … (0x1f<<19) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
65230 … (0xff<<0) // offset in 32b units from the beginning of the message…
65232 … (0xff<<8) // offset in 32b units from the beginning of the message…
65234 … (0xff<<16) // offset in 32b units from the beginning of the message…
65236 … (0xff<<24) // offset in 32b units from the beginning of the message…
65239 … (0xf<<0) // the maximal number of children in a specific aggregati…
65241 … (0xf<<4) // the maximal number of children in a specific aggregati…
65243 … (0xf<<8) // the maximal number of children in a specific aggregati…
65245 … (0xf<<12) // the maximal number of children in a specific aggregati…
65248 … (0xff<<0) // The value by which to increment the event-ID in case of successful…
65250 … (0xff<<8) // The value by which to increment the event-ID in case of successful…
65252 … (0xff<<16) // The value by which to increment the event-ID in case of successful…
65254 … (0xff<<24) // The value by which to increment the event-ID in case of successful…
65256 … 0x5a08d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
65258 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
65274 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65275 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65276 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65277 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65278 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65279 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65280 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65281 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65282 …0x5c0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65283 …0x5c0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65284 …0x5c0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65285 …0x5c003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65288 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
65297 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65299 … (0x1<<3) // Mini cache error - meaning that A load …
65301 … (0x1<<4) // Mini cache error - meaning that A load …
65323 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65325 … (0x1<<3) // Mini cache error - meaning that A load …
65327 … (0x1<<4) // Mini cache error - meaning that A load …
65336 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65338 … (0x1<<3) // Mini cache error - meaning that A load …
65340 … (0x1<<4) // Mini cache error - meaning that A load …
65361 …taWidth:0x1 // Enable ECC for memory ecc instance ypld.i_msgq_ram.i_ecc in module ypld_i_msgq_r…
65362 …th:0x1 // Set parity only for memory ecc instance ypld.i_msgq_ram.i_ecc in module ypld_i_msgq_r…
65363 … a correctable error occurred on memory ecc instance ypld.i_msgq_ram.i_ecc in module ypld_i_msgq_r…
65365 … 0x5c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65370 …in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this config…
65372 … (0x1<<2) // defines that only back-to-back aggregation is …
65381 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
65383 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
65385 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
65387 …/ the size of the message associated with each child in number of 128b units for set 0(should be i…
65389 …0x5c0808UL //Access:RW DataWidth:0x10 // Limit the number of �packets� in the Loader according…
65391 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
65393 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
65395 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
65397 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
65400 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
65402 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
65404 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
65406 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
65409 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
65411 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
65413 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
65415 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
65418 … (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter…
65420 … (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter…
65422 … (0xff<<16) // Offset in 32b units from the beginning of the message to same parameter…
65424 … (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter…
65427 … (0xf<<0) // length in 32b units from the s…
65429 … (0xf<<4) // length in 32b units from the s…
65431 … (0xf<<8) // length in 32b units from the s…
65433 … (0xf<<12) // length in 32b units from the s…
65435 … (0xf<<16) // length in 32b units from the s…
65437 … (0xf<<20) // length in 32b units from the s…
65439 … (0xf<<24) // length in 32b units from the s…
65441 … (0xf<<28) // length in 32b units from the s…
65444 … (0xf<<0) // length in 32b units from the s…
65446 … (0xf<<4) // length in 32b units from the s…
65448 … (0xf<<8) // length in 32b units from the s…
65450 … (0xf<<12) // length in 32b units from the s…
65452 … (0xf<<16) // length in 32b units from the s…
65454 … (0xf<<20) // length in 32b units from the s…
65456 … (0xf<<24) // length in 32b units from the s…
65458 … (0xf<<28) // length in 32b units from the s…
65460 … 0x5c0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65461 … 0x5c0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65462 … 0x5c082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65463 … 0x5c0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65464 … 0x5c0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65465 … 0x5c0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65466 … 0x5c083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65467 … 0x5c0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65468 … 0x5c0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65469 … 0x5c0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65470 … 0x5c084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65471 … 0x5c0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65472 … 0x5c0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65473 … 0x5c0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65474 … 0x5c085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65475 … 0x5c0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65476 … 0x5c0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65477 … 0x5c0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65478 … 0x5c086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65479 … 0x5c0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65480 … 0x5c0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65481 … 0x5c0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65482 … 0x5c087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65483 … 0x5c0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65484 … 0x5c0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65485 … 0x5c0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65486 … 0x5c088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65487 … 0x5c0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65488 … 0x5c0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65489 … 0x5c0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65490 … 0x5c089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65491 … 0x5c08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65493 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
65495 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
65497 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
65499 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
65502 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
65504 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
65506 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
65508 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
65511 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
65513 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
65515 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
65517 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
65520 … (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter…
65522 … (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter…
65524 … (0xff<<16) // Offset in 32b units from the beginning of the message to dup parameter…
65526 … (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter…
65529 … (0x3f<<0) // length in 32b units from the d…
65531 … (0x3f<<6) // length in 32b units from the d…
65533 … (0x3f<<12) // length in 32b units from the d…
65535 … (0x3f<<18) // length in 32b units from the d…
65538 … (0x3f<<0) // length in 32b units from the d…
65540 … (0x3f<<6) // length in 32b units from the d…
65542 … (0x3f<<12) // length in 32b units from the d…
65544 … (0x3f<<18) // length in 32b units from the d…
65547 … (0x3f<<0) // length in 32b units from the d…
65549 … (0x3f<<6) // length in 32b units from the d…
65551 … (0x3f<<12) // length in 32b units from the d…
65553 … (0x3f<<18) // length in 32b units from the d…
65556 … (0x3f<<0) // length in 32b units from the d…
65558 … (0x3f<<6) // length in 32b units from the d…
65560 … (0x3f<<12) // length in 32b units from the d…
65562 … (0x3f<<18) // length in 32b units from the d…
65565 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
65567 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
65569 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
65571 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
65573 … (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
65575 … (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
65577 … (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
65579 … (0x1f<<19) // offset of the flow-ID, in 32b units, from the beginning of the message. Shoul…
65582 … (0xff<<0) // offset in 32b units from the beginning of the message…
65584 … (0xff<<8) // offset in 32b units from the beginning of the message…
65586 … (0xff<<16) // offset in 32b units from the beginning of the message…
65588 … (0xff<<24) // offset in 32b units from the beginning of the message…
65591 … (0xf<<0) // the maximal number of children in a specific aggregati…
65593 … (0xf<<4) // the maximal number of children in a specific aggregati…
65595 … (0xf<<8) // the maximal number of children in a specific aggregati…
65597 … (0xf<<12) // the maximal number of children in a specific aggregati…
65600 … (0xff<<0) // The value by which to increment the event-ID in case of successful…
65602 … (0xff<<8) // The value by which to increment the event-ID in case of successful…
65604 … (0xff<<16) // The value by which to increment the event-ID in case of successful…
65606 … (0xff<<24) // The value by which to increment the event-ID in case of successful…
65608 … 0x5c08d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
65610 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
65635 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
65693 …-port per-PF register. L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L…
65695 … 0x608080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
65697 … 0x608100UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
65698 … 0x608104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65699 …8UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
65700 … 0x60810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65701 …0UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
65702 … 0x608114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65703 …8UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
65704 … 0x60811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65705 …0UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
65706 … 0x608124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65707 …8UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
65708 … 0x60812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65709 …0UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
65710 … 0x608134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65711 …8UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
65712 … 0x60813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65713 …0UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Length of ACPI Pattern,…
65714 … 0x608144UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Whe…
65715 … 0x608148UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
65717 … 0x608150UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high …
65718 … 0x608160UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wa…
65720 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
65721 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
65722 … //Access:R DataWidth:0xe // Wake packet length - the actual length of the 'wake' packet, in…
65723 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
65725 …election - acpi_default_pf_sel. 2: Select the first of each: 2 ports (quad_port_mode is 0) - use o…
65726 … 0x608198UL //Access:RW DataWidth:0x2 // This is a per-PF register. Set bit…
65727 … 0x60819cUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, o…
65728 … 0x6081a0UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, o…
65729 … 0x6081a4UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, o…
65730 … 0x6081a8UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, o…
65731 … 0x6081acUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, o…
65732 … 0x6081b0UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, o…
65733 …/Access:R DataWidth:0x3 // This is the current offset of the read pointer in the wake buffer.
65752 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
65764 …LAN tag to be used in tag insertion/override for management packets. This field consists of {3-bi…
65765 …LAN tag to be used in tag insertion/override for management packets. This field consists of {3-bi…
65766 … 0x6101f8UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, o…
65877 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
65884 … (0x1<<1) // Active low. Can be asserted on CMU0 in multiple CMU PHYs to…
65886 …in reset mode for increased power savings. Cannot be asserted on CMU0 in multiple CMU PHYs if ther…
65911 …- rxsig_det_mask_i 16 - rxeii_exit_type_i 15 - rxei_infer_i 14 - bslip_req_i 13 - data_width_i - 0…
65915 …pcs_sdet 0 - ln1_stat_o[2] (RX Locked indicator) 1 - ln1_astat_o[5] (Raw signal detext indicator)…
65923 …- not used 12 - ln1_ok_o 11 - ln1_runlen_err_o 10:4 - not used 3:2 - ln1_rx_locked_o - bit 3 =rxda…
65925 …(0x3f<<14) // 19 - Raw signal detect - Bit Slip Ack 18 - ln1_bitslip_ack_o - Bit Slip Ack 17 - not…
65936 … (0x1<<7) // Output enables for bidirectional CML refclk buffers.
65938 … (0x1<<8) // Output enables for bidirectional CML refclk buffers.
65958 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
65962 …dth:0x4 // Debug only: If more than this Number of entries are occupied in the dbgsyn clock syn…
65968 …-0x1ff. Reserved = 0x200-0x3ff. LANE1 registers = 0x400-0x5ff. Reserved = 0x600-0x7f…
65977 …to set0 1: Using registers belonging to set1 SETS_W-1: Using set of registers belonging to set SET…
65979 …responding bit in the AVSC_FLOW_CTRL is enabled. Bit [0] : corresponds to FLOW 1 Bit [1] : corresp…
65984 … (0x3<<1) // It replicates the mode-sel value when voltag…
65986 … (0x7<<3) // It replicates the set-sel value when voltag…
66029 …_TRAFFIC bit bit is also set; the LED will blink with blink rate specified in LED_CONTROL_BLINK_RA…
66031 …_TRAFFIC LED bit; the Traffic LED will blink with the blink rate specified in LED_CONTROL_BLINK_RA…
66039 …-> MAC; 1-2 -> PHY1; 3 -> PHY3; 4 -> MAC2; 5-6 -> PHY4; 7 -> PHY6; 8 -> MAC3; …
66040 …08UL //Access:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66041 …0cUL //Access:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66042 …10UL //Access:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66043 …14UL //Access:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66045 …In a typical setup, Physical function 0 is connected to Network Port 0, PF1 to NW1 and so on. Howe…
66047 … corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connects to PF1 2 -> NW1 co…
66049 … corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1 2 -> NW2 co…
66051 … corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1 2 -> NW3 co…
66053 …1cUL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66054 …20UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66055 …24UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66056 …28UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66057 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
66073 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66075 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66077 … (0x1<<3) // Unknown signal, not in users guide
66079 … (0x1<<4) // Unknown signal, not in users guide
66081 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66084 …<0) // 0x0 - Select reference clock from Bump 0x1 - Select inter-macro refrence clock from the lef…
66086 … (0x3<<2) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro ref…
66088 … (0x3<<4) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro re…
66090 …l is used for nws_nwm_sd_energy_detect. 0 - use ~lnX_stat_los_o 1 - use ~lnX_stat_los_deglitch_o (…
66094 … being written, and the serdes is being configured. This holds the SerDes in Reset. Once the memo…
66096 …signal into the SerDes. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to th…
66098 …signal into the SerDes. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to th…
66100 … signal into the SerDes. This should be 0 (Reset value) This holds the ln0 in Reset. write 1 to be…
66102 … signal into the SerDes. This should be 0 (Reset value) This holds the ln1 in Reset. write 1 to be…
66104 … signal into the SerDes. This should be 0 (Reset value) This holds the ln2 in Reset. write 1 to be…
66106 … signal into the SerDes. This should be 0 (Reset value) This holds the ln3 in Reset. write 1 to be…
66108 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66110 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66112 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66114 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66116 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66118 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66121 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66128 … (0x1f<<0) // Sets phy_ctrl_refclk_i used for CMU0 0x09 - refclk is 257.8125Mhz
66130 … Sets phy_ctrl_rate1_i used for CMU0 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66132 … Sets phy_ctrl_rate1_i used for CMU1 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66148 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66150 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66152 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66154 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66157 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66164 … (0x1<<0) // 0x0 - No error 0x1 - Phy has inter…
66166 … (0x1<<1) // 0x1 - Indicates CMU0 PLL h…
66168 … (0x1<<2) // 0x1 - Indicates CMU1 PLL h…
66170 … (0x1<<3) // 0x0 - PHY is not ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. The signal…
66172 … (0x1<<4) // 0x0 - PHY is not ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. The signal…
66174 … (0x1<<5) // 0x0 - PHY is not ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. The signal…
66176 … (0x1<<6) // 0x0 - PHY is not ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. The signal…
66178 … (0x1<<7) // 0x0 - PHY is not ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. The signal…
66180 … (0x1<<8) // 0x0 - PHY is not ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. The signal…
66196 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66198 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66200 …in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon pro…
66204 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66207 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66209 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66211 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66213 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66215 …- Inactive. No new status information is available for any RX links in the core. 0x1 - Active. New…
66218 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66220 … (0x1<<1) // 0x0 - data on ln0_rxdata_o is invalid. 0x1 - d…
66222 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66224 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. …
66226 …wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal dete…
66231 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66233 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66235 … (0x1<<3) // Unknown signal, not in users guide
66237 … (0x1<<4) // Unknown signal, not in users guide
66239 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66261 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66268 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66270 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66272 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66274 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66276 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66278 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66280 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66282 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66284 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66286 … // This signal detect output corresponds to the sigdet variable described in the Ethernet LT spec…
66288 …in instances where the PMD output is optically or magnetically coupled, and a changing signal is a…
66290 …he negotiated enable signal to allow pause control packets to be generated in the MAC and transmit…
66292 …ed in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control …
66294 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66296 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66314 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66316 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66318 …in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon pro…
66322 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66325 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66332 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66334 … (0x1<<1) // 0x0 - data on ln1_rxdata_o is invalid. 0x1 - d…
66336 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66338 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. …
66340 …wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal dete…
66375 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66377 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66379 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66381 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66383 …- Inactive. No new status information is available for any RX links in the core. 0x1 - Active. New…
66386 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66388 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66390 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66392 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66394 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66396 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66398 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66400 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66402 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66404 … // This signal detect output corresponds to the sigdet variable described in the Ethernet LT spec…
66406 …in instances where the PMD output is optically or magnetically coupled, and a changing signal is a…
66408 …he negotiated enable signal to allow pause control packets to be generated in the MAC and transmit…
66410 …ed in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control …
66412 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66414 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66421 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66423 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66425 … (0x1<<3) // Unknown signal, not in users guide
66427 … (0x1<<4) // Unknown signal, not in users guide
66429 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66432 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66434 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66436 …in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon pro…
66440 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66443 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66450 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66452 … (0x1<<1) // 0x0 - data on ln2_rxdata_o is invalid. 0x1 - d…
66454 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66456 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. …
66458 …wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal dete…
66493 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66500 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66502 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66504 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66506 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66508 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66510 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66512 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66514 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66516 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66518 … // This signal detect output corresponds to the sigdet variable described in the Ethernet LT spec…
66520 …in instances where the PMD output is optically or magnetically coupled, and a changing signal is a…
66522 …he negotiated enable signal to allow pause control packets to be generated in the MAC and transmit…
66524 …ed in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control …
66526 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66528 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66546 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66548 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66550 …in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon pro…
66554 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66557 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66559 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66561 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66563 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66565 …- Inactive. No new status information is available for any RX links in the core. 0x1 - Active. New…
66568 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66570 … (0x1<<1) // 0x0 - data on ln3_rxdata_o is invalid. 0x1 - d…
66572 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66574 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. …
66576 …wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal dete…
66581 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66583 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66585 … (0x1<<3) // Unknown signal, not in users guide
66587 … (0x1<<4) // Unknown signal, not in users guide
66589 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66611 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66618 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66620 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66622 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66624 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66626 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66628 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66630 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66632 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66634 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66636 … // This signal detect output corresponds to the sigdet variable described in the Ethernet LT spec…
66638 …in instances where the PMD output is optically or magnetically coupled, and a changing signal is a…
66640 …he negotiated enable signal to allow pause control packets to be generated in the MAC and transmit…
66642 …ed in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control …
66644 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66646 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66664 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66684 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66686 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66688 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66690 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66692 …- Inactive. No new status information is available for any RX links in the core. 0x1 - Active. New…
66697 …in a 1-bit alignment adjustment. This signal must maintain a level for a minimum of one C16 cycle …
66699 …Based on the setting of the Internal/External Early/Late Selection Control in the Receiver Phase R…
66701 …Based on the setting of the Internal/External Early/Late Selection Control in Receiver Phase Rotat…
66712 …in a 1-bit alignment adjustment. This signal must maintain a level for a minimum of one C16 cycle …
66714 …Based on the setting of the Internal/External Early/Late Selection Control in the Receiver Phase R…
66716 …Based on the setting of the Internal/External Early/Late Selection Control in Receiver Phase Rotat…
66727 …in a 1-bit alignment adjustment. This signal must maintain a level for a minimum of one C16 cycle …
66729 …Based on the setting of the Internal/External Early/Late Selection Control in the Receiver Phase R…
66731 …Based on the setting of the Internal/External Early/Late Selection Control in Receiver Phase Rotat…
66742 …in a 1-bit alignment adjustment. This signal must maintain a level for a minimum of one C16 cycle …
66744 …Based on the setting of the Internal/External Early/Late Selection Control in the Receiver Phase R…
66746 …Based on the setting of the Internal/External Early/Late Selection Control in Receiver Phase Rotat…
66757 …. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient up…
66771 …les the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.)…
66777 … follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Re…
66781 …. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient up…
66795 …les the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.)…
66801 … follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Re…
66805 …. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient up…
66819 …les the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.)…
66825 … follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Re…
66829 …. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient up…
66843 …les the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.)…
66849 … follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Re…
66862 …o the Controller to indicate a link status change or other events outlined in the XENPAK MSA stand…
66864 …o the Controller to indicate a link status change or other events outlined in the XENPAK MSA stand…
66866 …o the Controller to indicate a link status change or other events outlined in the XENPAK MSA stand…
66868 …o the Controller to indicate a link status change or other events outlined in the XENPAK MSA stand…
66877 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
66881 …dth:0x4 // Debug only: If more than this Number of entries are occupied in the dbgsyn clock syn…
67211 …10 // PHY instance0 = 0x000-0x1fff. PHY instance1 = 0x2000-0x3fff. PHY instance2 = 0x4000-0x5fff…
67213 …-0x7ff. CMU0 registers = 0x0800-0x0bff. CMU1 registers = 0x0c00-0x0fff. Reserved = …
67215 … to load operating tables into data ram. Each register location is 4 bytes in ram. bits[31:24] = r…
67217 …oad operating firmware into program ram. Each register location is 4 bytes in ram. bits[31:24] = r…
67359 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67360 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67361 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67362 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67364 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67380 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67396 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67412 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67440 … (0x1<<1) // Auto-Negotiation status. Set to '1' when the Auto…
67444 … (0x1<<3) // Auto-Negotiation status. Set to '1' when the Auto…
67448 … (0x1<<5) // Auto-Negotiation status. Set to '1' when the Auto…
67452 … (0x1<<7) // Auto-Negotiation status. Set to '1' when the Auto…
67470 … 0x800058UL //Access:RW DataWidth:0x1 // Controls the fast-wake mode for the LPI…
67480 …n value that is set true (1) when the receive is in a low power state and set to false (0) when it…
67491 …n value that is set true (1) when the receive is in a low power state and set to false (0) when it…
67502 …n value that is set true (1) when the receive is in a low power state and set to false (0) when it…
67513 …n value that is set true (1) when the receive is in a low power state and set to false (0) when it…
67522 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67531 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67540 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67549 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67554 …(1) the block synchronization state machines could successfully lock onto 66-bit block boundaries …
67556 …in a 1.25ms measurement period (40G) or 16 invalid headers within 125�s (10G), indicating a high b…
67558 …in its normal operational state. It is the result of an asserted block-lock or align-done status, …
67568 … any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc f…
67570 …er frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem f…
67572 …her frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li f…
67574 … any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc f…
67576 …er frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem f…
67578 …her frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li f…
67580 … any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc f…
67582 …er frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem f…
67584 …her frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li f…
67586 … any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc f…
67588 …er frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem f…
67590 …her frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li f…
67592 …ss:RW DataWidth:0x9 // This field controls the minimum amount of time in which idle character…
67593 …ss:RW DataWidth:0x9 // This field controls the minimum amount of time in which idle character…
67594 …ss:RW DataWidth:0x9 // This field controls the minimum amount of time in which idle character…
67595 …ss:RW DataWidth:0x9 // This field controls the minimum amount of time in which idle character…
67600 …orrected error indication. The FEC could detect and correct receive errors in a block. count of th…
67601 …orrected error indication. The FEC could detect and correct receive errors in a block. count of th…
67602 …orrected error indication. The FEC could detect and correct receive errors in a block. count of th…
67603 …orrected error indication. The FEC could detect and correct receive errors in a block. count of th…
67604 …orrected error indication. The FEC could detect and correct receive errors in a block. count of th…
67605 …orrected error indication. The FEC could detect and correct receive errors in a block. count of th…
67606 …orrected error indication. The FEC could detect and correct receive errors in a block. count of th…
67607 …orrected error indication. The FEC could detect and correct receive errors in a block. count of th…
67609 …able error indication. The FEC could detect but not correct receive errors in a block. count of th…
67610 …able error indication. The FEC could detect but not correct receive errors in a block. count of th…
67611 …able error indication. The FEC could detect but not correct receive errors in a block. count of th…
67612 …able error indication. The FEC could detect but not correct receive errors in a block. count of th…
67613 …able error indication. The FEC could detect but not correct receive errors in a block. count of th…
67614 …able error indication. The FEC could detect but not correct receive errors in a block. count of th…
67615 …able error indication. The FEC could detect but not correct receive errors in a block. count of th…
67618 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
67774 …//Access:RW DataWidth:0x20 // Register space for MAC port 0. Registers defined in MAC64.1.0.xml
67776 …//Access:RW DataWidth:0x20 // Register space for MAC port 1. Registers defined in MAC64.1.0.xml
67778 …//Access:RW DataWidth:0x20 // Register space for MAC port 2. Registers defined in MAC64.1.0.xml
67780 …//Access:RW DataWidth:0x20 // Register space for MAC port 3. Registers defined in MAC64.1.0.xml
67782 …h:0x10 // Register space for 10/25/40/50G PCS RS FEC port 0. Registers defined in rsfec91.1.0.xml
67784 …h:0x10 // Register space for 10/25/40/50G PCS RS FEC port 1. Registers defined in rsfec91.1.0.xml
67786 …taWidth:0x10 // Register space for 10/25G PCS RS FEC port 2. Registers defined in rsfec91.1.0.xml
67788 …taWidth:0x10 // Register space for 10/25G PCS RS FEC port 3. Registers defined in rsfec91.1.0.xml
67790 … DataWidth:0x10 // Register space for 1G PCS port 0. Registers defined in PCS_1000basex_sgmii.…
67792 … DataWidth:0x10 // Register space for 1G PCS port 1. Registers defined in PCS_1000basex_sgmii.…
67794 … DataWidth:0x10 // Register space for 1G PCS port 2. Registers defined in PCS_1000basex_sgmii.…
67796 … DataWidth:0x10 // Register space for 1G PCS port 3. Registers defined in PCS_1000basex_sgmii.…
67798 …idth:0x10 // Register space for 10/25/40/50G PCS port 0. Registers defined in pcs10254050.1.0.xml
67800 …idth:0x10 // Register space for 10/25/40/50G PCS port 1. Registers defined in pcs10254050.1.0.xml
67802 …RW DataWidth:0x10 // Register space for 10/25G PCS port 2. Registers defined in pcs1025.1.0.xml
67804 …RW DataWidth:0x10 // Register space for 10/25G PCS port 3. Registers defined in pcs1025.1.0.xml
67809 …Width:0x1 // When set to 1 the cam hit parity scrubbing feature is enabled in the SAL cache CAM.
67810 …idth:0x1 // When set to 1 the cam miss parity scrubbing feature is enabled in the SAL cache CAM.
67857 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
67866 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
67869 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
68160 …ble ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_…
68162 …able ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_…
68164 …) // Enable ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_hdr.i_ecc in module pbf_mem_ycmd_…
68166 … memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsi…
68168 … (0x1<<3) // Enable ECC for memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_d…
68170 … (0x1<<4) // Enable ECC for memory ecc instance pbf.i_pb1_db_new.i_ecc in module pbf_mem_pb1_d…
68172 …ECC for memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_heade…
68174 … (0x1<<6) // Enable ECC for memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1
68176 … (0x1<<7) // Enable ECC for memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1
68178 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif…
68180 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif…
68182 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif…
68184 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif…
68186 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif…
68188 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif…
68190 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif…
68192 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif…
68194 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif…
68196 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif…
68198 …/ Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif…
68200 …/ Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif…
68202 …/ Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif…
68204 …/ Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif…
68206 …/ Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif…
68208 …/ Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif…
68210 …ble ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_…
68212 …able ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_…
68214 … memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsi…
68216 …ECC for memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_heade…
68218 … (0x1<<5) // Enable ECC for memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1
68220 … (0x1<<6) // Enable ECC for memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1
68222 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif…
68224 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif…
68226 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif…
68228 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif…
68230 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif…
68232 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif…
68234 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif…
68236 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif…
68238 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif…
68240 …// Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif…
68242 …/ Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif…
68244 …/ Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif…
68246 …/ Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif…
68248 …/ Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif…
68250 …/ Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif…
68252 …/ Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif…
68256 …ty only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_…
68258 …ity only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_…
68260 …Set parity only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_hdr.i_ecc in module pbf_mem_ycmd_…
68262 … memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsi…
68264 … (0x1<<3) // Set parity only for memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_d…
68266 …(0x1<<4) // Set parity only for memory ecc instance pbf.i_pb1_db_new.i_ecc in module pbf_mem_pb1_d…
68268 …nly for memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_heade…
68270 … (0x1<<6) // Set parity only for memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1
68272 … (0x1<<7) // Set parity only for memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1
68274 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif…
68276 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif…
68278 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif…
68280 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif…
68282 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif…
68284 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif…
68286 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif…
68288 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif…
68290 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif…
68292 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif…
68294 … parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif…
68296 … parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif…
68298 … parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif…
68300 … parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif…
68302 … parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif…
68304 … parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif…
68306 …ty only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_…
68308 …ity only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_…
68310 … memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsi…
68312 …nly for memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_heade…
68314 … (0x1<<5) // Set parity only for memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1
68316 … (0x1<<6) // Set parity only for memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1
68318 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif…
68320 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif…
68322 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif…
68324 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif…
68326 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif…
68328 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif…
68330 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif…
68332 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif…
68334 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif…
68336 …t parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif…
68338 … parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif…
68340 … parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif…
68342 … parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif…
68344 … parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif…
68346 … parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif…
68348 … parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif…
68352 …occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_…
68354 … occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_…
68356 …e error occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_hdr.i_ecc in module pbf_mem_ycmd_…
68358 … memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsi…
68360 … if a correctable error occurred on memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_d…
68362 …a correctable error occurred on memory ecc instance pbf.i_pb1_db_new.i_ecc in module pbf_mem_pb1_d…
68364 …rred on memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_heade…
68366 …f a correctable error occurred on memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1
68368 …f a correctable error occurred on memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1
68370 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif…
68372 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif…
68374 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif…
68376 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif…
68378 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif…
68380 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif…
68382 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif…
68384 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif…
68386 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif…
68388 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif…
68390 …rror occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif…
68392 …rror occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif…
68394 …rror occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif…
68396 …rror occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif…
68398 …rror occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif…
68400 …rror occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif…
68402 …occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_…
68404 … occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_…
68406 … memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsi…
68408 …rred on memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_heade…
68410 …f a correctable error occurred on memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1
68412 …f a correctable error occurred on memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1
68414 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif…
68416 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif…
68418 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif…
68420 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif…
68422 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif…
68424 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif…
68426 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif…
68428 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif…
68430 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif…
68432 …error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif…
68434 …rror occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif…
68436 …rror occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif…
68438 …rror occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif…
68440 …rror occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif…
68442 …rror occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif…
68444 …rror occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif…
68448 …0400UL //Access:RW DataWidth:0x3 // PXP read request interface initial credit - transoriented.
68449 … 0xd80404UL //Access:RW DataWidth:0x6 // TDIF pass-through command inter…
68450 … 0xd80408UL //Access:RW DataWidth:0x6 // TDIF non_pass-through command inter…
68452 …10UL //Access:RW DataWidth:0x2 // PXP internal write interface initial credit - transoriented.
68453 … 0xd80414UL //Access:RW DataWidth:0x3 // TM interface initial credit - transoriented.
68476 …// The length of the info field for L2 tag 0. The length is between 2B and 14B; in 2B granularity.
68477 …// The length of the info field for L2 tag 1. The length is between 2B and 14B; in 2B granularity.
68478 …// The length of the info field for L2 tag 2. The length is between 2B and 14B; in 2B granularity.
68479 …// The length of the info field for L2 tag 3. The length is between 2B and 14B; in 2B granularity.
68480 …// The length of the info field for L2 tag 4. The length is between 2B and 14B; in 2B granularity.
68481 …// The length of the info field for L2 tag 5. The length is between 2B and 14B; in 2B granularity.
68482 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
68483 …-port: Bit-map indicating which L2 hdrs may appear after the LLC header on this port. This applie…
68484 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
68485 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
68486 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
68487 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
68488 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
68489 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
68490 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
68491 … 0xd804d4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68492 … 0xd804d8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68493 … 0xd804dcUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68494 … 0xd804e0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68495 … 0xd804e4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68496 … 0xd804e8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68497 … 0xd804ecUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68498 … 0xd804f0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68499 … 0xd804f4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating which headers must appe…
68502 …L //Access:RW DataWidth:0x10 // Ethertype for encapsulated ethernet used in GRE header parsing.
68505 … 0xd8050cUL //Access:RW DataWidth:0x8 // Value used to designate TCP in the IPv4 Protocol an…
68506 … 0xd80510UL //Access:RW DataWidth:0x8 // Value used to designate UDP in the IPv4 Protocol an…
68507 … 0xd80514UL //Access:RW DataWidth:0x8 // Value used to designate GRE in the IPv4 Protocol an…
68510 …L //Access:RW DataWidth:0x10 // Ethertype for encapsulated ethernet used in NGE header parsing.
68511 … 0xd80524UL //Access:RW DataWidth:0x1 // Per-port: Flag to compar…
68513 … (0x1<<0) // When high, it resets plru bits and invalidates all entries in the cache
68515 … (0x1<<1) // Enables inclusion of the VPORT ID in lookup tuple. If dis…
68517 … (0x1<<2) // Enables inclusion of the First VLAN ID in lookup tuple. If dis…
68519 … (0x1<<3) // Enables inclusion of the First Destination MAC in lookup tuple. If dis…
68521 … (0x1<<4) // Enables inclusion of the inner VLAN ID in lookup tuple. If dis…
68523 …in lookup tuple, and has following options: 0: None, the corresponding field in tuple is 0 1: Sour…
68525 … (0x1<<7) // Enables inclusion of Tunnel Extended Type in lookup tuple. If dis…
68527 … (0x1<<8) // Enables inclusion of Tenant ID in lookup tuple. If dis…
68529 … (0x1<<9) // Enables inclusion of Tenant ID Exist bit in lookup tuple. If dis…
68544 …used only if sal_flex_upper_bytes is not 0, and number of bytes selected = 8 - sal_flex_upper_bytes
68550 …W DataWidth:0x20 // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in each bit …
68551 …W DataWidth:0x20 // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in each bit …
68552 … 0xd80538UL //Access:ST DataWidth:0x38 // Number of hits in Same as Last Lookup
68640 …W DataWidth:0x3 // PORT SPLIT. Size of the Propriatery/HiGig header. (in 4B increments). If H…
68641 …egular inband TAG order. Reset value is in the order from left to right: tag0; tag1; tag2; tag3; t…
68642 …//Access:RW DataWidth:0x4 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. T…
68645 …tion address match value. A zero in this register will cause the corresponding bit…
68646 …tion address match value. A zero in this register will cause the corresponding bit…
68651 … (0xffff<<0) // Mask for Error flags in Event ID modificatio…
68653 … (0x1<<16) // Mask for First Global Destination Mac Address Match in Event ID modificatio…
68655 … (0x1f<<17) // Mask for Parsing Result in Event ID modificatio…
68658 …ASK_E5 (0xff<<0) // Mask for First L2 Tags Exist field in Event ID modificatio…
68660 …ASK_E5 (0xff<<8) // Mask for Inner L2 Tags Exist field in Event ID modificatio…
68662 …Access:RW DataWidth:0x1 // If set, enables inclusion of Future Header in the TGFS message ins…
68663 …DataWidth:0xb // Number of shared BTB 256 byte blocks which can be used by all TC-s in the port.
68664 …ess:R DataWidth:0xc // Number of blocks that are currently allocated in the shared area of t…
68665 … 0xd805c8UL //Access:RW DataWidth:0x6 // Jumbo packet threshold in 256 byte blocks to d…
68666 … 0xd805ccUL //Access:RW DataWidth:0x20 // Each nibble in the register from LS…
68667 …in the ycommand arbiter. A value of 0 means no strict priority cycles; i.e. the strict-priority w/…
68668 …05d4UL //Access:RW DataWidth:0x8 // L2 EDPM threshold in 256 byte blocks. Only if all TC-s ha…
68669 …805d8UL //Access:RW DataWidth:0xb // CPMU threshold in 256 byte blocks. Only if all TC-s in p…
68670 …dcUL //Access:RW DataWidth:0xb // RDMA EDPM threshold in 256 byte blocks. Only if all TC-s ha…
68671 … 1st bit mask used to control the rollover when increasing the IP ID field in the packet. Selected…
68672 … 2nd bit mask used to control the rollover when increasing the IP ID field in the packet. Selected…
68673 … 3rd bit mask used to control the rollover when increasing the IP ID field in the packet. Selected…
68674 … 4th bit mask used to control the rollover when increasing the IP ID field in the packet. Selected…
68685 … 0xd80640UL //Access:RW DataWidth:0x5 // PCI VOQ ID used in read request to PCI.
68687 …:RW DataWidth:0x20 // per VOQ indication if it should be accounted for in bytes/packet statist…
68694 …:RW DataWidth:0x4 // per VOQ indication if it should be accounted for in bytes/packet statist…
68705 … 0xd806a0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68706 …ccess:RW DataWidth:0x5 // Almost full threshold for VOQ 0 in the YSTORM command Q in 32 byte …
68707 …// Disable processing further Y commands from VOQ 0 (after ending the current command in process).
68709 … 0xd806b0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68711 …06b8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68714 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68720 …4UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 0 in both guar…
68723 … 0xd806e0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68724 …ccess:RW DataWidth:0x5 // Almost full threshold for VOQ 1 in the YSTORM command Q in 32 byte …
68725 …// Disable processing further Y commands from VOQ 1 (after ending the current command in process).
68727 … 0xd806f0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68729 …06f8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68732 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68738 …4UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 1 in both guar…
68741 … 0xd80720UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68742 …ccess:RW DataWidth:0x5 // Almost full threshold for VOQ 2 in the YSTORM command Q in 32 byte …
68743 …// Disable processing further Y commands from VOQ 2 (after ending the current command in process).
68745 … 0xd80730UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68747 …0738UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68750 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68756 …4UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 2 in both guar…
68759 … 0xd80760UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68760 …ccess:RW DataWidth:0x5 // Almost full threshold for VOQ 3 in the YSTORM command Q in 32 byte …
68761 …// Disable processing further Y commands from VOQ 3 (after ending the current command in process).
68763 … 0xd80770UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68765 …0778UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68768 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68774 …4UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 3 in both guar…
68777 … 0xd807a0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68778 …ccess:RW DataWidth:0x5 // Almost full threshold for VOQ 4 in the YSTORM command Q in 32 byte …
68779 …// Disable processing further Y commands from VOQ 4 (after ending the current command in process).
68781 … 0xd807b0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68783 …07b8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68786 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68792 …4UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 4 in both guar…
68795 … 0xd807e0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68796 …ccess:RW DataWidth:0x5 // Almost full threshold for VOQ 5 in the YSTORM command Q in 32 byte …
68797 …// Disable processing further Y commands from VOQ 5 (after ending the current command in process).
68799 … 0xd807f0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68801 …07f8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68804 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68810 …4UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 5 in both guar…
68813 … 0xd80820UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68814 …ccess:RW DataWidth:0x5 // Almost full threshold for VOQ 6 in the YSTORM command Q in 32 byte …
68815 …// Disable processing further Y commands from VOQ 6 (after ending the current command in process).
68817 … 0xd80830UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68819 …0838UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68822 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68828 …4UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 6 in both guar…
68831 … 0xd80860UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68832 …ccess:RW DataWidth:0x5 // Almost full threshold for VOQ 7 in the YSTORM command Q in 32 byte …
68833 …// Disable processing further Y commands from VOQ 7 (after ending the current command in process).
68835 … 0xd80870UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68837 …0878UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68840 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68846 …4UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 7 in both guar…
68849 … 0xd808a0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68850 …ccess:RW DataWidth:0x5 // Almost full threshold for VOQ 8 in the YSTORM command Q in 32 byte …
68851 …// Disable processing further Y commands from VOQ 8 (after ending the current command in process).
68853 … 0xd808b0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68855 …08b8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68858 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68864 …4UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 8 in both guar…
68867 … 0xd808e0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68868 …ccess:RW DataWidth:0x5 // Almost full threshold for VOQ 9 in the YSTORM command Q in 32 byte …
68869 …// Disable processing further Y commands from VOQ 9 (after ending the current command in process).
68871 … 0xd808f0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68873 …08f8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68876 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68882 …4UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 9 in both guar…
68885 … 0xd80920UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68886 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 10 in the YSTORM command Q in 32 byte …
68887 …/ Disable processing further Y commands from VOQ 10 (after ending the current command in process).
68889 … 0xd80930UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68891 …0938UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68894 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68900 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 10 in both guar…
68903 … 0xd80960UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68904 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 11 in the YSTORM command Q in 32 byte …
68905 …/ Disable processing further Y commands from VOQ 11 (after ending the current command in process).
68907 … 0xd80970UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68909 …0978UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68912 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68918 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 11 in both guar…
68921 … 0xd809a0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68922 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 12 in the YSTORM command Q in 32 byte …
68923 …/ Disable processing further Y commands from VOQ 12 (after ending the current command in process).
68925 … 0xd809b0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68927 …09b8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68930 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68936 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 12 in both guar…
68939 … 0xd809e0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68940 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 13 in the YSTORM command Q in 32 byte …
68941 …/ Disable processing further Y commands from VOQ 13 (after ending the current command in process).
68943 … 0xd809f0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68945 …09f8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68948 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68954 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 13 in both guar…
68957 … 0xd80a20UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68958 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 14 in the YSTORM command Q in 32 byte …
68959 …/ Disable processing further Y commands from VOQ 14 (after ending the current command in process).
68961 … 0xd80a30UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68963 …0a38UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68966 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68972 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 14 in both guar…
68975 … 0xd80a60UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68976 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 15 in the YSTORM command Q in 32 byte …
68977 …/ Disable processing further Y commands from VOQ 15 (after ending the current command in process).
68979 … 0xd80a70UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68981 …0a78UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
68984 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
68990 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 15 in both guar…
68993 … 0xd80aa0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
68994 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 16 in the YSTORM command Q in 32 byte …
68995 …/ Disable processing further Y commands from VOQ 16 (after ending the current command in process).
68997 … 0xd80ab0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
68999 …0ab8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69002 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69008 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 16 in both guar…
69011 … 0xd80ae0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69012 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 17 in the YSTORM command Q in 32 byte …
69013 …/ Disable processing further Y commands from VOQ 17 (after ending the current command in process).
69015 … 0xd80af0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69017 …0af8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69020 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69026 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 17 in both guar…
69029 … 0xd80b20UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69030 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 18 in the YSTORM command Q in 32 byte …
69031 …/ Disable processing further Y commands from VOQ 18 (after ending the current command in process).
69033 … 0xd80b30UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69035 …0b38UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69038 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69044 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 18 in both guar…
69047 … 0xd80b60UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69048 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 19 in the YSTORM command Q in 32 byte …
69049 …/ Disable processing further Y commands from VOQ 19 (after ending the current command in process).
69051 … 0xd80b70UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69053 …0b78UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69056 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69062 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 19 in both guar…
69065 … 0xd80ba0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69066 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 20 in the YSTORM command Q in 32 byte …
69067 …/ Disable processing further Y commands from VOQ 20 (after ending the current command in process).
69069 … 0xd80bb0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69071 …0bb8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69074 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69080 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 20 in both guar…
69083 … 0xd80be0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69084 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 21 in the YSTORM command Q in 32 byte …
69085 …/ Disable processing further Y commands from VOQ 21 (after ending the current command in process).
69087 … 0xd80bf0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69089 …0bf8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69092 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69098 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 21 in both guar…
69101 … 0xd80c20UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69102 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 22 in the YSTORM command Q in 32 byte …
69103 …/ Disable processing further Y commands from VOQ 22 (after ending the current command in process).
69105 … 0xd80c30UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69107 …0c38UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69110 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69116 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 22 in both guar…
69119 … 0xd80c60UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69120 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 23 in the YSTORM command Q in 32 byte …
69121 …/ Disable processing further Y commands from VOQ 23 (after ending the current command in process).
69123 … 0xd80c70UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69125 …0c78UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69128 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69134 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 23 in both guar…
69137 … 0xd80ca0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69138 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 24 in the YSTORM command Q in 32 byte …
69139 …/ Disable processing further Y commands from VOQ 24 (after ending the current command in process).
69141 … 0xd80cb0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69143 …0cb8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69146 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69152 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 24 in both guar…
69155 … 0xd80ce0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69156 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 25 in the YSTORM command Q in 32 byte …
69157 …/ Disable processing further Y commands from VOQ 25 (after ending the current command in process).
69159 … 0xd80cf0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69161 …0cf8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69164 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69170 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 25 in both guar…
69173 … 0xd80d20UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69174 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 26 in the YSTORM command Q in 32 byte …
69175 …/ Disable processing further Y commands from VOQ 26 (after ending the current command in process).
69177 … 0xd80d30UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69179 …0d38UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69182 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69188 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 26 in both guar…
69191 … 0xd80d60UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69192 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 27 in the YSTORM command Q in 32 byte …
69193 …/ Disable processing further Y commands from VOQ 27 (after ending the current command in process).
69195 … 0xd80d70UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69197 …0d78UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69200 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69206 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 27 in both guar…
69209 … 0xd80da0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69210 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 28 in the YSTORM command Q in 32 byte …
69211 …/ Disable processing further Y commands from VOQ 28 (after ending the current command in process).
69213 … 0xd80db0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69215 …0db8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69218 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69224 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 28 in both guar…
69227 … 0xd80de0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69228 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 29 in the YSTORM command Q in 32 byte …
69229 …/ Disable processing further Y commands from VOQ 29 (after ending the current command in process).
69231 … 0xd80df0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69233 …0df8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69236 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69242 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 29 in both guar…
69245 … 0xd80e20UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69246 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 30 in the YSTORM command Q in 32 byte …
69247 …/ Disable processing further Y commands from VOQ 30 (after ending the current command in process).
69249 … 0xd80e30UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69251 …0e38UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69254 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69260 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 30 in both guar…
69263 … 0xd80e60UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69264 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 31 in the YSTORM command Q in 32 byte …
69265 …/ Disable processing further Y commands from VOQ 31 (after ending the current command in process).
69267 … 0xd80e70UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69269 …0e78UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69272 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69278 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 31 in both guar…
69281 … 0xd80ea0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69282 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 32 in the YSTORM command Q in 32 byte …
69283 …/ Disable processing further Y commands from VOQ 32 (after ending the current command in process).
69285 … 0xd80eb0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69287 …0eb8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69290 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69296 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 32 in both guar…
69299 … 0xd80ee0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69300 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 33 in the YSTORM command Q in 32 byte …
69301 …/ Disable processing further Y commands from VOQ 33 (after ending the current command in process).
69303 … 0xd80ef0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69305 …0ef8UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69308 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69314 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 33 in both guar…
69317 … 0xd80f20UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69318 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 34 in the YSTORM command Q in 32 byte …
69319 …/ Disable processing further Y commands from VOQ 34 (after ending the current command in process).
69321 … 0xd80f30UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69323 …0f38UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69326 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69332 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 34 in both guar…
69335 … 0xd80f60UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q…
69336 …cess:RW DataWidth:0x5 // Almost full threshold for VOQ 35 in the YSTORM command Q in 32 byte …
69337 …/ Disable processing further Y commands from VOQ 35 (after ending the current command in process).
69339 … 0xd80f70UL //Access:R DataWidth:0xa // Number of commands in the Y command queue …
69341 …0f78UL //Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue …
69344 …ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for …
69350 …UL //Access:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 35 in both guar…
69453 …an error received on the ingress interface will be masked for instructions in which the "dummy rea…
69476 …bug register. This register stores the calculated CRC value that resulted in the most recent CRC …
69477 …nstruction is the first instruction in the task. Bit 29 indicates whether the instruction is the …
69487 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
69491 … 0xda2000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
69593 …an error received on the ingress interface will be masked for instructions in which the "dummy rea…
69616 …bug register. This register stores the calculated CRC value that resulted in the most recent CRC …
69617 …nstruction is the first instruction in the task. Bit 29 indicates whether the instruction is the …
69627 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
69631 … 0xda6000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
69635 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
69636 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
69641 …uested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
69643 …r when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
69645 …r when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
69647 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
69649 … when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
69651 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
69653 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
69655 … when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
69657 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
69659 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
69661 …hen requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
69663 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
69707 …uested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
69709 …r when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
69711 …r when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
69713 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
69715 … when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
69717 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
69719 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
69721 … when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
69723 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
69725 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
69727 …hen requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
69729 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
69740 …uested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
69742 …r when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
69744 …r when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
69746 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
69748 … when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
69750 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
69752 …ested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
69754 … when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
69756 … when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
69758 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
69760 …hen requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
69762 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
69771 … (0x1<<1) // Calculations error in LL arbiter block.
69773 … (0x1<<2) // Calculations error in almost full counter block ALM_FULL_EN::/ALM_FULL…
69775 … (0x1<<3) // Input FIFO error in write client 0.
69777 … (0x1<<4) // SOP FIFO error in write client 0.
69779 … (0x1<<5) // LEN FIFO error in write client 0.
69781 … (0x1<<6) // EOP FIFO error in write client 0.
69783 … (0x1<<7) // Queue FIFO error in write client 0.
69785 … (0x1<<8) // Free ointer FIFO error in write client 0.
69787 … (0x1<<9) // Next pointer FIFO error in write client 0.
69789 … (0x1<<10) // Start FIFO error in write client 0.
69791 … (0x1<<11) // Second descriptor FIFO error in write client 0.
69793 … (0x1<<12) // Packet available FIFO error in write client 0.
69795 … (0x1<<14) // Notify FIFO error in write client 0.
69797 … (0x1<<15) // LL req error in write client 0.
69837 … (0x1<<1) // Calculations error in LL arbiter block.
69839 … (0x1<<2) // Calculations error in almost full counter block ALM_FULL_EN::/ALM_FULL…
69841 … (0x1<<3) // Input FIFO error in write client 0.
69843 … (0x1<<4) // SOP FIFO error in write client 0.
69845 … (0x1<<5) // LEN FIFO error in write client 0.
69847 … (0x1<<6) // EOP FIFO error in write client 0.
69849 … (0x1<<7) // Queue FIFO error in write client 0.
69851 … (0x1<<8) // Free ointer FIFO error in write client 0.
69853 … (0x1<<9) // Next pointer FIFO error in write client 0.
69855 … (0x1<<10) // Start FIFO error in write client 0.
69857 … (0x1<<11) // Second descriptor FIFO error in write client 0.
69859 … (0x1<<12) // Packet available FIFO error in write client 0.
69861 … (0x1<<14) // Notify FIFO error in write client 0.
69863 … (0x1<<15) // LL req error in write client 0.
69870 … (0x1<<1) // Calculations error in LL arbiter block.
69872 … (0x1<<2) // Calculations error in almost full counter block ALM_FULL_EN::/ALM_FULL…
69874 … (0x1<<3) // Input FIFO error in write client 0.
69876 … (0x1<<4) // SOP FIFO error in write client 0.
69878 … (0x1<<5) // LEN FIFO error in write client 0.
69880 … (0x1<<6) // EOP FIFO error in write client 0.
69882 … (0x1<<7) // Queue FIFO error in write client 0.
69884 … (0x1<<8) // Free ointer FIFO error in write client 0.
69886 … (0x1<<9) // Next pointer FIFO error in write client 0.
69888 … (0x1<<10) // Start FIFO error in write client 0.
69890 … (0x1<<11) // Second descriptor FIFO error in write client 0.
69892 … (0x1<<12) // Packet available FIFO error in write client 0.
69894 … (0x1<<14) // Notify FIFO error in write client 0.
69896 … (0x1<<15) // LL req error in write client 0.
69903 … (0x1<<28) // Updated data FIFO error in duplicated write client DUP_EN::/DUP_EN/d …
69905 … (0x1<<29) // Response descriptor FIFO error in duplicated write client DUP_EN::/DUP_EN/d …
69907 … (0x1<<30) // Updated pointer FIFO error in duplicated write client DUP_EN::/DUP_EN/d …
69909 … (0x1<<31) // Packet available FIFO error in duplicated write client DUP_EN::/DUP_EN/d …
69921 … (0x1<<28) // Updated data FIFO error in duplicated write client DUP_EN::/DUP_EN/d …
69923 … (0x1<<29) // Response descriptor FIFO error in duplicated write client DUP_EN::/DUP_EN/d …
69925 … (0x1<<30) // Updated pointer FIFO error in duplicated write client DUP_EN::/DUP_EN/d …
69927 … (0x1<<31) // Packet available FIFO error in duplicated write client DUP_EN::/DUP_EN/d …
69930 … (0x1<<28) // Updated data FIFO error in duplicated write client DUP_EN::/DUP_EN/d …
69932 … (0x1<<29) // Response descriptor FIFO error in duplicated write client DUP_EN::/DUP_EN/d …
69934 … (0x1<<30) // Updated pointer FIFO error in duplicated write client DUP_EN::/DUP_EN/d …
69936 … (0x1<<31) // Packet available FIFO error in duplicated write client DUP_EN::/DUP_EN/d …
69939 …0) // Packet available counter overflow or underflow in duplicated write client DUP_EN::/DUP_EN/d …
69941 …<<1) // Read packet client NIG main port 0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
69943 …x1<<2) // Read packet client NIG main port 0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
69945 …(0x1<<3) // Read packet client NIG main port 0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
69947 … // Read packet client NIG main port 0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
69949 … // Read packet client NIG main port 0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
69951 …// Read packet client NIG main port 0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
69953 …1<<7) // Read packet client NIG main port 0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
69955 …<8) // Read packet client NIG main port 0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
69957 …1<<9) // Read packet client NIG LB port 0 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
69959 …x1<<10) // Read packet client NIG LB port 0 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
69961 …(0x1<<11) // Read packet client NIG LB port 0 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
69963 …) // Read packet client NIG LB port 0 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
69965 …) // Read packet client NIG LB port 0 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
69967 … // Read packet client NIG LB port 0 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
69969 …1<<15) // Read packet client NIG LB port 0 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
69971 …<16) // Read packet client NIG LB port 0 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
69973 …17) // Read packet client NIG main port 1 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
69975 …<<18) // Read packet client NIG main port 1 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
69977 …x1<<19) // Read packet client NIG main port 1 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
69979 …// Read packet client NIG main port 1 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
69981 …// Read packet client NIG main port 1 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
69983 …/ Read packet client NIG main port 1 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
69985 …<23) // Read packet client NIG main port 1 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
69987 …4) // Read packet client NIG main port 1 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
69989 …25) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
69991 …<<26) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
69993 …x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
69995 …// Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
69997 …// Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
69999 …/ Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70001 …<31) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70069 …0) // Packet available counter overflow or underflow in duplicated write client DUP_EN::/DUP_EN/d …
70071 …<<1) // Read packet client NIG main port 0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70073 …x1<<2) // Read packet client NIG main port 0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70075 …(0x1<<3) // Read packet client NIG main port 0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70077 … // Read packet client NIG main port 0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70079 … // Read packet client NIG main port 0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70081 …// Read packet client NIG main port 0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70083 …1<<7) // Read packet client NIG main port 0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70085 …<8) // Read packet client NIG main port 0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70087 …1<<9) // Read packet client NIG LB port 0 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70089 …x1<<10) // Read packet client NIG LB port 0 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70091 …(0x1<<11) // Read packet client NIG LB port 0 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70093 …) // Read packet client NIG LB port 0 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70095 …) // Read packet client NIG LB port 0 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70097 … // Read packet client NIG LB port 0 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70099 …1<<15) // Read packet client NIG LB port 0 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70101 …<16) // Read packet client NIG LB port 0 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70103 …17) // Read packet client NIG main port 1 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70105 …<<18) // Read packet client NIG main port 1 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70107 …x1<<19) // Read packet client NIG main port 1 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70109 …// Read packet client NIG main port 1 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70111 …// Read packet client NIG main port 1 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70113 …/ Read packet client NIG main port 1 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70115 …<23) // Read packet client NIG main port 1 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70117 …4) // Read packet client NIG main port 1 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70119 …25) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70121 …<<26) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70123 …x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70125 …// Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70127 …// Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70129 …/ Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70131 …<31) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70134 …0) // Packet available counter overflow or underflow in duplicated write client DUP_EN::/DUP_EN/d …
70136 …<<1) // Read packet client NIG main port 0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70138 …x1<<2) // Read packet client NIG main port 0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70140 …(0x1<<3) // Read packet client NIG main port 0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70142 … // Read packet client NIG main port 0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70144 … // Read packet client NIG main port 0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70146 …// Read packet client NIG main port 0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70148 …1<<7) // Read packet client NIG main port 0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70150 …<8) // Read packet client NIG main port 0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
70152 …1<<9) // Read packet client NIG LB port 0 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70154 …x1<<10) // Read packet client NIG LB port 0 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70156 …(0x1<<11) // Read packet client NIG LB port 0 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70158 …) // Read packet client NIG LB port 0 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70160 …) // Read packet client NIG LB port 0 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70162 … // Read packet client NIG LB port 0 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70164 …1<<15) // Read packet client NIG LB port 0 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70166 …<16) // Read packet client NIG LB port 0 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
70168 …17) // Read packet client NIG main port 1 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70170 …<<18) // Read packet client NIG main port 1 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70172 …x1<<19) // Read packet client NIG main port 1 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70174 …// Read packet client NIG main port 1 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70176 …// Read packet client NIG main port 1 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70178 …/ Read packet client NIG main port 1 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70180 …<23) // Read packet client NIG main port 1 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70182 …4) // Read packet client NIG main port 1 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
70184 …25) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70186 …<<26) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70188 …x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70190 …// Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70192 …// Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70194 …/ Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70196 …<31) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70199 …0) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70223 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
70225 …hen requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
70227 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
70229 …24) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70231 …<<25) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70233 …x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70235 …// Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70237 …// Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70239 …/ Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70241 …<30) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70243 …1) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70293 …0) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70317 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
70319 …hen requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
70321 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
70323 …24) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70325 …<<25) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70327 …x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70329 …// Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70331 …// Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70333 …/ Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70335 …<30) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70337 …1) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70340 …0) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70364 …ted packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
70366 …hen requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
70368 …hen packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
70370 …24) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70372 …<<25) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70374 …x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70376 …// Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70378 …// Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70380 …/ Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70382 …<30) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70384 …1) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
70659 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
70665 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
70668 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write c…
70671 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
70677 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
70680 … (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write c…
70856 …y ecc instance btb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70858 …y ecc instance btb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70860 …y ecc instance btb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70862 …y ecc instance btb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70864 …y ecc instance btb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70866 …y ecc instance btb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70868 …y ecc instance btb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70870 …y ecc instance btb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70872 …y ecc instance btb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70874 …y ecc instance btb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70876 … ecc instance btb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70878 … ecc instance btb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70880 … ecc instance btb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70882 … ecc instance btb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70884 … ecc instance btb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70886 … ecc instance btb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70888 …cc instance btb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module btb_link_list…
70890 …cc instance btb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module btb_link_list…
70892 …cc instance btb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module btb_link_list…
70894 …cc instance btb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module btb_link_list…
70896 …cc instance btb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module btb_link_list…
70898 …cc instance btb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module btb_link_list…
70900 …cc instance btb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module btb_link_list…
70902 …cc instance btb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module btb_link_list…
70908 …y ecc instance btb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70910 …y ecc instance btb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70912 …y ecc instance btb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70914 …y ecc instance btb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70916 …y ecc instance btb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70918 …y ecc instance btb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70920 …y ecc instance btb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70922 …y ecc instance btb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70924 …y ecc instance btb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70926 …y ecc instance btb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70928 … ecc instance btb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70930 … ecc instance btb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70932 … ecc instance btb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70934 … ecc instance btb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70936 … ecc instance btb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70938 … ecc instance btb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70940 …cc instance btb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module btb_link_list…
70942 …cc instance btb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module btb_link_list…
70944 …cc instance btb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module btb_link_list…
70946 …cc instance btb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module btb_link_list…
70948 …cc instance btb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module btb_link_list…
70950 …cc instance btb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module btb_link_list…
70952 …cc instance btb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module btb_link_list…
70954 …cc instance btb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module btb_link_list…
70960 …y ecc instance btb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70962 …y ecc instance btb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70964 …y ecc instance btb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70966 …y ecc instance btb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70968 …y ecc instance btb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70970 …y ecc instance btb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70972 …y ecc instance btb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70974 …y ecc instance btb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70976 …y ecc instance btb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70978 …y ecc instance btb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70980 … ecc instance btb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70982 … ecc instance btb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70984 … ecc instance btb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70986 … ecc instance btb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70988 … ecc instance btb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70990 … ecc instance btb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_k2
70992 …cc instance btb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module btb_link_list…
70994 …cc instance btb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module btb_link_list…
70996 …cc instance btb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module btb_link_list…
70998 …cc instance btb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module btb_link_list…
71000 …cc instance btb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module btb_link_list…
71002 …cc instance btb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module btb_link_list…
71004 …cc instance btb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_ecc1 in module btb_link_list…
71006 …cc instance btb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_ecc2 in module btb_link_list…
71021 …f big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data…
71022 …in header in 16-bytes resolution. After this number of bytes will input to BRTB will be sent packe…
71023 …s:RW DataWidth:0xd // Head pointer to each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
71025 …s:RW DataWidth:0xd // Tail pointer of each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.
71027 …ccess:RW DataWidth:0xd // Number of free blocks in each one of 4 free lists::s/BLK_WDTH/13/g …
71029 …MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_REQ/required/g in R…
71030 …till reset in a case of length error other way it will continue to work as usual.::s/STOP_LEN_ERR_…
71031 …in BTB upper which ALMOST FULL is asserted and BTB stops writing new packets to BIG RAM from its i…
71032 …-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 ::s/NO_DEAD_CYCLE_RST/1/g in …
71034 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
71036 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
71038 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
71040 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
71042 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
71044 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
71046 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
71048 …in link list and big ram arbiters. If all read clients have identical priority then selection betw…
71050 …intra packet dead cycles .B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 :…
71051 …the corresponding client. B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 :…
71052 …ad client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_SOP_PRI_RST/5/g…
71053 …ient group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7/g…
71054 …ntical priority is supported. Possible values are 1-3. Priority 3 is highest::s/RC_MULT_PRI_RST/6/…
71061 …ient upper which full outputs to this write client interface.::s/DSCR_FIFO_RST/12/g in Reset Value.
71062 …ient upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.
71064 …dth:0x4 // Debug only: If more than this Number of entries are occupied in the dbgsyn clock syn…
71068 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
71077 …-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropr…
71081 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
71084 …-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropr…
71088 … set. All bits of this register should be set after init procedure. ::/ALM_FULL_EN/d in Existance.
71092 …nterface will never be set. This bit should be set after init procedure. ::/RLS_EN/d in Existance.
71094 …e clients: {pkt_avail_fifo ;upd_point_fifo ; rsp_dscr_fifo; upd_data_fifo}::/DUP_EN/d in Existance.
71095 …e clients: {pkt_avail_fifo ;upd_point_fifo ; rsp_dscr_fifo; upd_data_fifo}::/DUP_EN/d in Existance.
71096 …ite clients: {delayed_fifo ;upd_point_fifo ; rsp_dscr_fifo; upd_data_fifo}::/DUP_EN/d in Existance.
71097 …0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits s…
71099 …ch write client because of temporal bandwidth problem on interface::s/WC_NUM_MAX/4/g in Data Width.
71100 …/ Debug register. Full status of each read packet client interface::s/PKT_RC_NUM/5/g in Data Width.
71101 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
71102 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
71103 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
71104 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
71105 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
71106 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
71107 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
71108 …- read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - read client 3. 8 bits …
71109 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
71110 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
71111 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
71112 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
71113 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
71114 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
71115 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
71116 …- read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - read client 3. 8 bits …
71117 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71118 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71119 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71120 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71121 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71122 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71123 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71124 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71125 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71126 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71127 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
71131 …ister. This is number of allocated blocks ::s/BLK_WDTH/13/g in Data Width::/ALM_FULL_EN/d in Exist…
71132 …Width:0x1 // Debug register. This is almost full output IF to PBF::/ALM_FULL_EN/d in Existance.
71135 …/ Debug register. This is state machine for each read client. ::s/PKT_RC_NUM_ST/20/g in Data Width.
71136 …in power of 2, before sending new packet indication to read client. This should ensure no underflo…
71137 …from that queue in bits 11:0; b12: update enable status; b13: duplicated queue update enable; b14:…
71139 …is written in big_ram_address register. Read from 32 LSB bits of this register will generate read …
71141 …- valid; b30:16 - queue size; b15:0 - queue start pointer::s/SOP_STATUS_RST/536805376/g in Reset V…
71144 … erad packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1.…
71148 … read packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1.…
71155 …ry that contains per-block descriptor::s/BLK_NUM/4800/g in memory size::s/BLK_WDTH_PLUS_SOP_EN/14/…
71156 …ry that contains per-block descriptor::s/BLK_NUM/4800/g in memory size::s/BLK_WDTH_PLUS_SOP_EN/14/…
71170 … (0x1<<27) // Illegal transaction occurred in the MCP cache block.
71186 … (0x7ff<<0) // This value is written by the MCP and indicates (in ms) to the driver MC…
71190 … (0x1<<31) // When set this bit validates bits 10-0 of this register.
71193 …free running counter incremented roughly with the period that is specified in MCP_HEARTBEAT_STATUS…
71211 …0x1<<28) // When this bit is set, expiration of watchdog timer will result in MCP losing ability t…
71219 …/2 speed) core_clk. Using core clock should provide timeout period scaling in case where core/cpu …
71220 …/2 speed) core_clk. Using core clock should provide timeout period scaling in case where core/cpu …
71224 …in order to obtain the lock over the shared resources within the chip. The actual "lock" is implem…
71232 … (0x3fff<<0) // Offset (in 32-bit words) of the m…
71236 … (0xfff<<20) // Mailbox size in 32-bit words. Default …
71239 … (0x3fff<<0) // Offset (in 32-bit words) of the m…
71243 … (0xfff<<20) // Mailbox size in 32-bit words. Default …
71248 … to alert the MCP. Changing this register updates the corresponding per-PF bit in the MCP Doorbell…
71266 …taWidth:0x20 // Port mode for GRC Master transactions 0: 1-port mode, 1: 2-port mode, 2: 4-port …
71268 …W DataWidth:0x20 // EPIO mask for signal transitioning from high to low. 1 -> MASK the event
71269 …W DataWidth:0x20 // EPIO mask for signal transitioning from low to high. 1 -> MASK the event
71274 …/ When this bit is written to a 1, the processor will reset as if from power-up state. All "Reset"…
71292 …en this bit is set, the CPU will halt when any condition that causes bit 5 in the CPU state regist…
71294 …en this bit is set, the CPU will halt when any condition that causes bit 6 in the CPU state regist…
71303 …hile the processor is halted due reaching a hardware breakpoint as enabled in the mode register. T…
71315 …(0x1<<6) // This bit is set while the processor is halted due to bad value in the Program Counter …
71319 …ices within the CPU block. This will only happen if halt is enabled by bit 13 in the mode register.
71323 …// This bit is set while the processor is halted due to the setting of bit 10 in the mode register.
71366 …so clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. '…
71367 … //Access:RW DataWidth:0x20 // This register allows access instruction in the decode sate of t…
71369 …in mode register). This register is intended to allow a way to return from an interrupt service ro…
71377 … (0x3fffffff<<2) // This field sets the 32-bit word on which the…
71380 … (0x7ff<<0) // 11 bit set-1 debug visibility ve…
71382 …this bit is '0', then the debug visiblity mux is controlled by the setting in the misc. block and …
71384 … (0xf<<12) // 4 bit select for the peek value of the set-1 debug visibility ve…
71386 … (0x7ff<<16) // 11 bit set-2 debug visibility ve…
71388 …this bit is '0', then the debug visiblity mux is controlled by the setting in the misc. block and …
71390 … (0xf<<28) // 4 bit select for the peek value of the set-2 debug visibility ve…
71399 …/ While the processor is halted, the general purpose processor registers (r0-r31) can be read and …
71402 … specify the bit at the auto-polled address that indicates "link up". The bit which corresponds to…
71404 … (0xffff<<16) // This value is used to define the register address in MDIO auto-poll transactio…
71407 …In case of Clause 45, when the address transaction is executed, this value specifies the register …
71409 …ause 22. This selects what register within a PHY device is being accessed. In case of Clause 45 th…
71417 …in the emac_status register. Writing this bit as a '0' has no effect. This bit must be read as a '…
71420 …by the MDIO interface if auto-polling is enabled. The value of this bit is reflected by in the mai…
71427 … (0x1<<1) // If this bit is set, the 32-bit pre-amble will not be generated during au…
71431 …-polling. When auto-polling is on, the START_BUSY bit in the mdio_comm register must not be set. T…
71435 …is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the comma…
71453 …eaning of bits specified in bits [27:0] of the MDIO COMMAND register. This bit must be set to prop…
71471 …m_clk cycles will be driven when a new target is enabled based on a change in the access_mode fiel…
71476 …arpCore SERDES microcontroller program memory interfaces. This register auto-increments after each…
71479 …mory interfaces. Accessing this register will start the transaction specified in the mode register.
71516 …m_clk cycles will be driven when a new target is enabled based on a change in the access_mode fiel…
71521 … 2 PCIE SERDES microcontroller program memory interfaces. This register auto-increments after each…
71524 …mory interfaces. Accessing this register will start the transaction specified in the mode register.
71542 …address offset for the AVS RBUS program memory interface. This register auto-increments after each…
71545 …mory interfaces. Accessing this register will start the transaction specified in the mode register.
71547 … (0x1f<<0) // Number of bytes to be transfered in Read or Write operation. Valid lengths are …
71570 …ice ID of the Slave Device. This is a 7-bit field as defined by the I2C spec, but can be written h…
71600 … (0x1<<1) // This bit indicates that in In-Use Error has occur…
71604 …x1<<3) // This bit is set when the Length specified in the VDM header exceeded the amount of data …
71614 … (0x3f<<16) // This is the current count of locations used in the packet FIFO, for…
71617 … (0x1<<0) // Setting this bit will transmit the VDM that was already loaded in the packet FIFO.
71620 … (0x7f<<0) // This is the length of the VDM packet, in 32-bit DWords. 0x0 is …
71644 …aWidth:0x20 // Writing to this register will store the data in the Tx FIFO to be sent in the VDM.
71646 …0x7f<<0) // This field is a count of the number of Packet Headers currently stored in the P2M FIFO.
71650 …<<16) // This field is a count of the number of Packet Data Words currently stored in the P2M FIFO.
71680 … (0xff<<0) // This is the Tag Value to use in the Filter.
71687 …cepted. Packets smaller than this will be discarded. This length is in DWords, as in the VDM Heade…
71691 …ccepted. Packets larger than this will be discarded. This length is in DWords, as in the VDM Heade…
71696 …d due to the FIFO being full. This also counts packets being dropped while in Drain mode. Reading …
71698 …-bits of the current Header. The first access will give bits [31:0], then [63:32], then [95:64]. T…
71707 … 0xe06240UL //Access:R DataWidth:0x20 // 32-bit Packet Data.
71709 … (0x7f<<0) // 7-bit Length from VDM Header, in DWord…
71712 … (0xffff<<0) // 16-bit PCI Requester ID …
71715 … (0xffff<<0) // 16-bit Vendor ID from VD…
71718 … (0xffff<<0) // 16-bit FID from VDM Head…
71720 … 0xe06254UL //Access:R DataWidth:0x20 // 32-bit Vendor Defined DW…
71730 … (0xff<<16) // This is the 8-bit Tag from VDM Head…
71732 … 0xe06300UL //Access:RW DataWidth:0x20 // The start address of the PIM in the NVRAM.
71734 … (0x1<<0) // If this bit is cleared then the look-up is bypassed and th…
71740 … (0x1<<1) // The data is in use. If the valid bi…
71742 … (0x1<<2) // The data in this page is valid.
71744 …OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71749 … (0x1<<1) // The data is in use. If the valid bi…
71751 … (0x1<<2) // The data in this page is valid.
71753 …OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71758 … (0x1<<1) // The data is in use. If the valid bi…
71760 … (0x1<<2) // The data in this page is valid.
71762 …OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71767 … (0x1<<1) // The data is in use. If the valid bi…
71769 … (0x1<<2) // The data in this page is valid.
71771 …OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71776 … (0x1<<1) // The data is in use. If the valid bi…
71778 … (0x1<<2) // The data in this page is valid.
71780 …OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71785 … (0x1<<1) // The data is in use. If the valid bi…
71787 … (0x1<<2) // The data in this page is valid.
71789 …OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71794 … (0x1<<1) // The data is in use. If the valid bi…
71796 … (0x1<<2) // The data in this page is valid.
71798 …OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71803 … (0x1<<1) // The data is in use. If the valid bi…
71805 … (0x1<<2) // The data in this page is valid.
71807 …OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71812 … (0x1<<1) // The data is in use. If the valid bi…
71814 … (0x1<<2) // The data in this page is valid.
71816 …OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71821 … (0x1<<1) // The data is in use. If the valid bi…
71823 … (0x1<<2) // The data in this page is valid.
71825 …OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71830 … (0x1<<1) // The data is in use. If the valid bi…
71832 … (0x1<<2) // The data in this page is valid.
71834 …_OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71839 … (0x1<<1) // The data is in use. If the valid bi…
71841 … (0x1<<2) // The data in this page is valid.
71843 …_OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71848 … (0x1<<1) // The data is in use. If the valid bi…
71850 … (0x1<<2) // The data in this page is valid.
71852 …_OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71857 … (0x1<<1) // The data is in use. If the valid bi…
71859 … (0x1<<2) // The data in this page is valid.
71861 …_OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71866 … (0x1<<1) // The data is in use. If the valid bi…
71868 … (0x1<<2) // The data in this page is valid.
71870 …_OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71875 … (0x1<<1) // The data is in use. If the valid bi…
71877 … (0x1<<2) // The data in this page is valid.
71879 …_OFFSET (0x1ff<<3) // Offset in the PIM associated w…
71884 …r provides the GRC address of the Expansion ROM Engine Baddr register used in the cache fetch logi…
71889 …r provides the GRC address of the Expansion ROM Engine Gaddr register used in the cache fetch logi…
71894 …r provides the GRC address of the Expansion ROM Engine Caddr register used in the cache fetch logi…
71899 …r provides the GRC address of the Expansion ROM Engine Cdata register used in the cache fetch logi…
71904 …ter provides the GRC address of the Expansion ROM Engine Cfg register used in the cache fetch logi…
71906 … DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction hits in the pag…
71907 …DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction misses in the pa…
71909 … (0x1<<0) // The data in this register is val…
71913 … (0xf<<2) // Index in the page table assoc…
71915 … (0x1ff<<6) // Offset in the PIM associated w…
71918 … (0x1<<0) // The data in this register is val…
71922 … (0xf<<2) // Index in the page table assoc…
71924 … (0x1ff<<6) // Offset in the PIM associated w…
71930 …// If set, a read attempt to a second page was detected while a page fetch was already in progress.
71937 …n of the doit bit has completed. done Will be cleared while the command is in progress. done Will …
71949 … (0x1<<9) // When this bit is set, the address in the address register…
71953 …en_cmd to flash device through SPI interface to set Flash device to be write-enabled. Used for the…
71955 …di_cmd to flash device through SPI interface to set Flash device to be write-disabled. Used for th…
71965 …it is set, the 256B page mode is disabled for the next operation. It is self-clearing when both th…
71972 … (0xffffff<<0) // 24 bit address value used in read, write and erase operations. When in b…
71980 … (0x1<<2) // Enable pass-thru mode to the byte…
71982 … (0x1<<3) // Enable bit-bang mode to control …
71984 …in status command response to interpret as the "ready" flag. For Atmel, this defaults to 3'h7. For…
72013 … CSB deassertion. commands. Reset value is 0x1e in Legacy ST mode, 0x58 in Legacy Atmel mode, and …
72024 … (0xff<<16) // This is the fast read command. This command is used in Fast ST Mode. Follow…
72069 …rface state machine through SPI interface To flash device, and make the flash device write-enabled.
72071 …face state machine through SPI interface To flash device, and make the flash device write-disabled.
72082 …s not used by FLSH hardware. It is only used by software. This value is self-configured on reset b…
72084 … (0x1<<3) // This bit is self-configured on reset b…
72086 … address bit when MODE_256 is not set with Atmel devices. This value is self-configured on reset b…
72088 …or Atmel, this defaults to 1. For ST, this defaults to 0. This value is self-configured on reset b…
72090 …in ST mode, fast read command is used. In Atmel mode, this bit should be set when using the 0xE8 r…
72096 … (0x1<<10) // When this bit is set, a turnaround cycle is inserted in between the address …
72102 …ng f(SCLK) = f(core_clk)/(2*(SPI_SLOW_CLK_DIV +1)). [Ex: SPI_SLOW_CLK_DIV=0 -> f(SCLK) = f(core…
72104 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72106 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72108 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72110 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72112 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72114 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72116 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72118 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72120 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72122 … 0xe06430UL //Access:RW DataWidth:0x20 // NVM re-configuration registe…
72134 …pansion ROM engine will utilize the buffered mode address translation mode in the flash controller…
72167 …f the ROM BAR area, it will place the offset from the BAR value in this register and re-try the PC…
72181 …/ Image base address. This register provides the base address of the image in the NVRAM that the I…
72197 … (0x3fff<<2) // These bits indicate the transfer size in 4bytes (word) granul…
72201 …nquished. Using these bits, SW/FW can limit how many words get transferred in a single arbitration…
72218 …/ Image base address. This register provides the base address of the image in the NVRAM that the I…
72234 … (0x3fff<<2) // These bits indicate the transfer size in 4bytes (word) granul…
72238 …nquished. Using these bits, SW/FW can limit how many words get transferred in a single arbitration…
72255 …/ Image base address. This register provides the base address of the image in the NVRAM that the I…
72271 … (0x3fff<<2) // These bits indicate the transfer size in 4bytes (word) granul…
72275 …nquished. Using these bits, SW/FW can limit how many words get transferred in a single arbitration…
72289 … 0xe08000UL //Access:RW DataWidth:0x20 // All registers in the SMB block are sh…
72300 …r of retries in case where SMBUS block acted as a master and lost SMBUS arbitration. HW will retry…
72310 … bit is '1', the SMBUS block is placed into bit-bang mode. SMBUS interface pins are controlled usi…
72312 …led for operation. When set the SMBUS block will abort current transaction in compliance with the …
72323 …yte (that is ACK bit) when the SMBUS block acts as a slave. This is useful in "legacy mode" to all…
72325 …31) // When this bit is set the SMBUS block operates in 400KHz mode. When cleared SMBUS operates i…
72351 … (0x7f<<16) // Number of packets in the Master RX FIFO.
72366 … (0x7f<<16) // Number of packets in the Slave RX FIFO.
72377 … (0x1<<28) // When the SMBUS interface is configured for bit-bang mode, this bit c…
72381 … (0x1<<30) // When the SM Bus interface is configured for bit-bang mode, this bit c…
72402 …This is number of bytes that SMBUS block should read from the slave in Block Write - Block Read Pr…
72414 … at any time by the firmware or the driver in order to abort the transaction. The HW will abort tr…
72416 … has no effect. This bit must be read as a '0' before setting it to prevent un-predictable results.
72429 … at any time by the firmware or the driver in order to abort the transaction. The HW will abort tr…
72431 …as no effect. This bit must be read as a '0' before setting it to prevent un-predictable results. …
72471 …sition will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
72473 …sition will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
72475 …sition will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
72477 …sition will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
72479 …sition will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
72485 …sition will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
72489 …ion will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor. 0x
72491 …sition will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
72493 …sition will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
72495 …sition will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
72499 …ion will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor. 0x
72501 …sition will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
72503 …sition will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
72505 …sition will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
72512 … (0x1<<31) // 0 - Byte other then last in an WMBUS transaction …
72515 … (0xff<<0) // SMBUS Read Data in Network Byte Order (…
72519 …ndicates status of the PEC checking. HW will check the PEC only in case where PEC bit in SMBUS Mas…
72624 … (0x1<<0) // Setting this bit to '1' will flush the packet in the FIFO.
72649 … (0x1<<4) // Setting this bit to '1' will flush the current packet in the FIFO
72651 …x1<<5) // Setting this bit to '1' will clear all packet available counters in the BMB read client …
72668 … (0x3<<8) // These bits indicate the bytes that are valid in the 4byte data.
72684 … processor. This can be modified at any time and may be used for processor-to-processor communicat…
72690 … (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
72692 … (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
72694 … (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
72696 … (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
72698 … (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
72700 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
72702 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
72704 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
72706 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
72710 … (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
72712 … (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
72714 … (0x1<<13) // Enable for input completion message from PRM in prm_if block.
72720 … (0x1<<16) // Enable for input response from CCFC in CCFC block.
72726 … (0x1<<19) // Enable for input full from qm in SDM_INP block.
72729 … (0x1<<0) // Enable for input response from TCFC in TCFC block.
72731 … (0x1<<1) // Enable for input acknowledge from Cm in SDM_CM block.
72733 … (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
72750 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
72752 … (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
72754 … (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
72756 … (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
72758 … (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
72760 … (0x1<<12) // Enable for output write to pxp in DMA_DST block.
72762 … (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
72764 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
72772 … (0x1<<18) // Enable for output message to CM in SDM_CM block.
72774 … (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
72776 … (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
72779 … (0x1<<0) // Enable for output command to qm in SDM_INP block.
72781 … (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
72783 … (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
72800 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Asy…
72811 … (0x1<<2) // Delay fifo in INP_CMD block output…
72813 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
72815 … (0x1<<4) // FIFO in PRM interface sub-module repo…
72817 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
72819 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
72821 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
72823 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
72825 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
72827 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
72829 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
72831 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
72833 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
72835 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
72837 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
72839 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
72841 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
72843 … (0x1<<18) // Delay CM fifo error in CM block.
72845 … (0x1<<19) // Delay shared fifo error in CM block.
72847 … (0x1<<20) // Error in completion pending FIFO in intern…
72849 … (0x1<<21) // Error in completion parameter pending FIFO in i…
72851 … (0x1<<22) // Address fifo error in timer block.
72853 … (0x1<<23) // Pending fifo error in timer block.
72855 … (0x1<<24) // Dpm fifo error in dorq I/F block.
72857 … (0x1<<25) // PXP done fifo error in DMA_dst block.
72859 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
72861 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
72865 … (0x1<<29) // Last-cycle indication not …
72937 … (0x1<<2) // Delay fifo in INP_CMD block output…
72939 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
72941 … (0x1<<4) // FIFO in PRM interface sub-module repo…
72943 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
72945 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
72947 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
72949 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
72951 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
72953 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
72955 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
72957 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
72959 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
72961 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
72963 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
72965 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
72967 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
72969 … (0x1<<18) // Delay CM fifo error in CM block.
72971 … (0x1<<19) // Delay shared fifo error in CM block.
72973 … (0x1<<20) // Error in completion pending FIFO in intern…
72975 … (0x1<<21) // Error in completion parameter pending FIFO in i…
72977 … (0x1<<22) // Address fifo error in timer block.
72979 … (0x1<<23) // Pending fifo error in timer block.
72981 … (0x1<<24) // Dpm fifo error in dorq I/F block.
72983 … (0x1<<25) // PXP done fifo error in DMA_dst block.
72985 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
72987 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
72991 …E5 (0x1<<29) // Last-cycle indication not …
73000 … (0x1<<2) // Delay fifo in INP_CMD block output…
73002 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
73004 … (0x1<<4) // FIFO in PRM interface sub-module repo…
73006 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
73008 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
73010 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
73012 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
73014 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
73016 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
73018 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
73020 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
73022 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
73024 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
73026 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
73028 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
73030 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
73032 … (0x1<<18) // Delay CM fifo error in CM block.
73034 … (0x1<<19) // Delay shared fifo error in CM block.
73036 … (0x1<<20) // Error in completion pending FIFO in intern…
73038 … (0x1<<21) // Error in completion parameter pending FIFO in i…
73040 … (0x1<<22) // Address fifo error in timer block.
73042 … (0x1<<23) // Pending fifo error in timer block.
73044 … (0x1<<24) // Dpm fifo error in dorq I/F block.
73046 … (0x1<<25) // PXP done fifo error in DMA_dst block.
73048 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
73050 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
73054 …_E5 (0x1<<29) // Last-cycle indication not …
73099 … 0xf80414UL //Access:RW DataWidth:0xf // The start address in the internal RAM for…
73100 …ests in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC ma…
73101 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
73102 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
73103 …4UL //Access:R DataWidth:0x9 // This register is intended to be read in the event of an inp_…
73104 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
73107 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
73110 …nitial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.
73111 …l number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.
73124 …700UL //Access:RW DataWidth:0x5 // Almost full signal for read data from BRB in DMA_RSP block.
73125 …704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block.
73126 …8UL //Access:RW DataWidth:0x6 // Almost full signal for read data from DORQ in SDM_DORQ block.
73127 …in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,…
73133 … 0xf80c00UL //Access:R DataWidth:0x9 // Input queue fifo full in sdm_inp block.
73134 …L //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block.
73135 …:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block.
73136 … 0xf80c0cUL //Access:R DataWidth:0x1 // QM IF full in sdm_inp block.
73137 … 0xf80c10UL //Access:R DataWidth:0x1 // Delay FIFO full in sdm_inp block.
73138 … 0xf80c14UL //Access:R DataWidth:0x1 // Pending FIFO full in sdm_timers block.
73139 … 0xf80c18UL //Access:R DataWidth:0x1 // Address FIFO full in sdm_timers block.
73140 … 0xf80c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full in sdm_dma_rsp block.
73141 … 0xf80c20UL //Access:R DataWidth:0x1 // BRB read data fifo full in sdm_dma_rsp block.
73142 … 0xf80c24UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo full in sdm_dma_rsp block.
73143 … 0xf80c28UL //Access:R DataWidth:0x1 // BRB pending fifo full in sdm_dma_rsp block.
73144 … 0xf80c2cUL //Access:R DataWidth:0x1 // Int_ram pending fifo full in sdm_dma_rsp block.
73145 … 0xf80c30UL //Access:R DataWidth:0x1 // BRB interface is full in sdm_dma_rsp block.
73146 … 0xf80c34UL //Access:R DataWidth:0x1 // PXP interface is full in sdm_dma_rsp block.
73147 … 0xf80c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full in sdm_dma_dst block.
73148 …xf80c3cUL //Access:R DataWidth:0x1 // PXP destination pending fifo full in sdm_dma_dst block.
73149 … 0xf80c40UL //Access:R DataWidth:0x1 // PXP source pending fifo full in sdm_dma_dst block.
73150 … 0xf80c44UL //Access:R DataWidth:0x1 // BRB source pending fifo full in sdm_dma_dst block.
73151 … 0xf80c48UL //Access:R DataWidth:0x1 // BRB source address fifo full in sdm_dma_dst block.
73152 … 0xf80c4cUL //Access:R DataWidth:0x1 // PXP link list full in sdm_dma_dst block.
73153 … 0xf80c50UL //Access:R DataWidth:0x1 // Int_ram_wait fifo full in sdm_dma_dst block.
73154 … 0xf80c54UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo full in sdm_dma_dst block.
73155 … 0xf80c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_dst block.
73156 … 0xf80c5cUL //Access:R DataWidth:0x1 // Int_ram if full in sdm_dma_dst block.
73157 … 0xf80c60UL //Access:R DataWidth:0x1 // Pas_buf if full in sdm_dma_dst block.
73158 … 0xf80c64UL //Access:R DataWidth:0x1 // Shared delay FIFO full in SDM completion manag…
73159 … 0xf80c68UL //Access:R DataWidth:0x1 // CM delay FIFO full in SDM completion manag…
73160 … 0xf80c6cUL //Access:R DataWidth:0x1 // Completion message queue fifo full in sdm_cm block.
73161 … 0xf80c70UL //Access:R DataWidth:0x1 // CCFC load pending fifo full in the CCFC interface …
73162 … 0xf80c74UL //Access:R DataWidth:0x1 // TCFC load pending fifo full in the TCFC interface b…
73163 … 0xf80c78UL //Access:R DataWidth:0x1 // Async fifo full in sdm_async block.
73164 … 0xf80c7cUL //Access:R DataWidth:0x1 // PRM FIFO full in PRM interface block.
73165 …80c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM interfac…
73166 …80c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM interfac…
73167 … //Access:R DataWidth:0x1 // Internal write completion pending empty in internal write block.
73168 …R DataWidth:0x1 // Internal write completion parameter pending empty in internal write block.
73169 … 0xf80d08UL //Access:R DataWidth:0x9 // Input queue fifo empty in sdm_inp block.
73170 … 0xf80d0cUL //Access:R DataWidth:0x1 // Delay FIFO empty in sdm_inp block.
73171 … 0xf80d10UL //Access:R DataWidth:0x1 // Pending FIFO empty in sdm_timers block.
73172 … 0xf80d14UL //Access:R DataWidth:0x1 // Address FIFO empty in sdm_timers block.
73173 … 0xf80d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty in sdm_dma_rsp block.
73174 … 0xf80d1cUL //Access:R DataWidth:0x1 // BRB read data fifo empty in sdm_dma_rsp block.
73175 … 0xf80d20UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo empty in sdm_dma_rsp block.
73176 … 0xf80d24UL //Access:R DataWidth:0x1 // BRB pending fifo empty in sdm_dma_rsp block.
73177 … 0xf80d28UL //Access:R DataWidth:0x1 // Int_ram pending fifo empty in sdm_dma_rsp block.
73178 … 0xf80d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empty in sdm_dma_dst block.
73179 …f80d30UL //Access:R DataWidth:0x1 // PXP destination pending fifo empty in sdm_dma_dst block.
73180 … 0xf80d34UL //Access:R DataWidth:0x1 // PXP source pending fifo empty in sdm_dma_dst block.
73181 … 0xf80d38UL //Access:R DataWidth:0x1 // BRB source pending fifo empty in sdm_dma_dst block.
73182 … 0xf80d3cUL //Access:R DataWidth:0x1 // BRB source address fifo empty in sdm_dma_dst block.
73183 … 0xf80d40UL //Access:R DataWidth:0x1 // PXP link list empty in sdm_dma_dst block.
73184 … 0xf80d44UL //Access:R DataWidth:0x1 // Int_ram_wait fifo empty in sdm_dma_dst block.
73185 … 0xf80d48UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo empty in sdm_dma_dst block.
73186 … 0xf80d4cUL //Access:R DataWidth:0x1 // Shared delay FIFO empty in SDM completion manag…
73187 … 0xf80d50UL //Access:R DataWidth:0x1 // CM delay FIFO empty in SDM completion manag…
73188 …80d54UL //Access:R DataWidth:0x1 // Completion message queue fifo empty in sdm_dma_dst block.
73189 … 0xf80d58UL //Access:R DataWidth:0x1 // CCFC load pending fifo empty in sdm_ccfc block.
73190 … 0xf80d5cUL //Access:R DataWidth:0x1 // TCFC load pending fifo empty in sdm_tcfc block.
73191 … 0xf80d60UL //Access:R DataWidth:0x1 // Async fifo empty in sdm_async block.
73192 … 0xf80d64UL //Access:R DataWidth:0x1 // PRM FIFO empty in sdm_prm_if block.
73200 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
73204 … 0xf82000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73206 … 0xf82400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
73208 … 0xf82800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
73210 … 0xf82c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
73212 … 0xf83000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
73214 … 0xf83400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
73216 … 0xf83800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
73218 … 0xf83c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
73220 … 0xf84000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
73231 … (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
73233 … (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
73235 … (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
73237 … (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
73239 … (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
73241 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
73243 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
73245 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
73247 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73251 … (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
73253 … (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
73255 … (0x1<<13) // Enable for input completion message from PRM in prm_if block.
73261 … (0x1<<16) // Enable for input response from CCFC in CCFC block.
73267 … (0x1<<19) // Enable for input full from qm in SDM_INP block.
73270 … (0x1<<0) // Enable for input response from TCFC in TCFC block.
73272 … (0x1<<1) // Enable for input acknowledge from Cm in SDM_CM block.
73274 … (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
73291 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
73293 … (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
73295 … (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
73297 … (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
73299 … (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
73301 … (0x1<<12) // Enable for output write to pxp in DMA_DST block.
73303 … (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
73305 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
73313 … (0x1<<18) // Enable for output message to CM in SDM_CM block.
73315 … (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
73317 … (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
73320 … (0x1<<0) // Enable for output command to qm in SDM_INP block.
73322 … (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
73324 … (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
73341 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Asy…
73352 … (0x1<<2) // Delay fifo in INP_CMD block output…
73354 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
73356 … (0x1<<4) // FIFO in PRM interface sub-module repo…
73358 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
73360 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
73362 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
73364 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
73366 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
73368 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
73370 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
73372 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
73374 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
73376 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
73378 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
73380 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
73382 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
73384 … (0x1<<18) // Delay CM fifo error in CM block.
73386 … (0x1<<19) // Delay shared fifo error in CM block.
73388 … (0x1<<20) // Error in completion pending FIFO in intern…
73390 … (0x1<<21) // Error in completion parameter pending FIFO in i…
73392 … (0x1<<22) // Address fifo error in timer block.
73394 … (0x1<<23) // Pending fifo error in timer block.
73396 … (0x1<<24) // Dpm fifo error in dorq I/F block.
73398 … (0x1<<25) // PXP done fifo error in DMA_dst block.
73400 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
73402 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
73406 … (0x1<<29) // Last-cycle indication not …
73478 … (0x1<<2) // Delay fifo in INP_CMD block output…
73480 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
73482 … (0x1<<4) // FIFO in PRM interface sub-module repo…
73484 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
73486 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
73488 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
73490 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
73492 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
73494 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
73496 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
73498 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
73500 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
73502 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
73504 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
73506 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
73508 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
73510 … (0x1<<18) // Delay CM fifo error in CM block.
73512 … (0x1<<19) // Delay shared fifo error in CM block.
73514 … (0x1<<20) // Error in completion pending FIFO in intern…
73516 … (0x1<<21) // Error in completion parameter pending FIFO in i…
73518 … (0x1<<22) // Address fifo error in timer block.
73520 … (0x1<<23) // Pending fifo error in timer block.
73522 … (0x1<<24) // Dpm fifo error in dorq I/F block.
73524 … (0x1<<25) // PXP done fifo error in DMA_dst block.
73526 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
73528 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
73532 …E5 (0x1<<29) // Last-cycle indication not …
73541 … (0x1<<2) // Delay fifo in INP_CMD block output…
73543 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
73545 … (0x1<<4) // FIFO in PRM interface sub-module repo…
73547 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
73549 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
73551 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
73553 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
73555 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
73557 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
73559 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
73561 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
73563 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
73565 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
73567 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
73569 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
73571 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
73573 … (0x1<<18) // Delay CM fifo error in CM block.
73575 … (0x1<<19) // Delay shared fifo error in CM block.
73577 … (0x1<<20) // Error in completion pending FIFO in intern…
73579 … (0x1<<21) // Error in completion parameter pending FIFO in i…
73581 … (0x1<<22) // Address fifo error in timer block.
73583 … (0x1<<23) // Pending fifo error in timer block.
73585 … (0x1<<24) // Dpm fifo error in dorq I/F block.
73587 … (0x1<<25) // PXP done fifo error in DMA_dst block.
73589 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
73591 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
73595 …_E5 (0x1<<29) // Last-cycle indication not …
73636 … 0xf90414UL //Access:RW DataWidth:0xf // The start address in the internal RAM for…
73637 …ests in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC ma…
73638 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
73639 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
73640 …4UL //Access:R DataWidth:0x9 // This register is intended to be read in the event of an inp_…
73641 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
73644 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
73647 …nitial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.
73648 …l number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.
73662 …700UL //Access:RW DataWidth:0x5 // Almost full signal for read data from BRB in DMA_RSP block.
73663 …704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block.
73664 …8UL //Access:RW DataWidth:0x6 // Almost full signal for read data from DORQ in SDM_DORQ block.
73665 …in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,…
73671 … 0xf90c00UL //Access:R DataWidth:0x9 // Input queue fifo full in sdm_inp block.
73672 …L //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block.
73673 …:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block.
73674 … 0xf90c0cUL //Access:R DataWidth:0x1 // QM IF full in sdm_inp block.
73675 … 0xf90c10UL //Access:R DataWidth:0x1 // Delay FIFO full in sdm_inp block.
73676 … 0xf90c14UL //Access:R DataWidth:0x1 // Pending FIFO full in sdm_timers block.
73677 … 0xf90c18UL //Access:R DataWidth:0x1 // Address FIFO full in sdm_timers block.
73678 … 0xf90c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full in sdm_dma_rsp block.
73679 … 0xf90c20UL //Access:R DataWidth:0x1 // BRB read data fifo full in sdm_dma_rsp block.
73680 … 0xf90c24UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo full in sdm_dma_rsp block.
73681 … 0xf90c28UL //Access:R DataWidth:0x1 // BRB pending fifo full in sdm_dma_rsp block.
73682 … 0xf90c2cUL //Access:R DataWidth:0x1 // Int_ram pending fifo full in sdm_dma_rsp block.
73683 … 0xf90c30UL //Access:R DataWidth:0x1 // BRB interface is full in sdm_dma_rsp block.
73684 … 0xf90c34UL //Access:R DataWidth:0x1 // PXP interface is full in sdm_dma_rsp block.
73685 … 0xf90c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full in sdm_dma_dst block.
73686 …xf90c3cUL //Access:R DataWidth:0x1 // PXP destination pending fifo full in sdm_dma_dst block.
73687 … 0xf90c40UL //Access:R DataWidth:0x1 // PXP source pending fifo full in sdm_dma_dst block.
73688 … 0xf90c44UL //Access:R DataWidth:0x1 // BRB source pending fifo full in sdm_dma_dst block.
73689 … 0xf90c48UL //Access:R DataWidth:0x1 // BRB source address fifo full in sdm_dma_dst block.
73690 … 0xf90c4cUL //Access:R DataWidth:0x1 // PXP link list full in sdm_dma_dst block.
73691 … 0xf90c50UL //Access:R DataWidth:0x1 // Int_ram_wait fifo full in sdm_dma_dst block.
73692 … 0xf90c54UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo full in sdm_dma_dst block.
73693 … 0xf90c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_dst block.
73694 … 0xf90c5cUL //Access:R DataWidth:0x1 // Int_ram if full in sdm_dma_dst block.
73695 … 0xf90c60UL //Access:R DataWidth:0x1 // Pas_buf if full in sdm_dma_dst block.
73696 … 0xf90c64UL //Access:R DataWidth:0x1 // Shared delay FIFO full in SDM completion manag…
73697 … 0xf90c68UL //Access:R DataWidth:0x1 // CM delay FIFO full in SDM completion manag…
73698 … 0xf90c6cUL //Access:R DataWidth:0x1 // Completion message queue fifo full in sdm_cm block.
73699 … 0xf90c70UL //Access:R DataWidth:0x1 // CCFC load pending fifo full in the CCFC interface …
73700 … 0xf90c74UL //Access:R DataWidth:0x1 // TCFC load pending fifo full in the TCFC interface b…
73701 … 0xf90c78UL //Access:R DataWidth:0x1 // Async fifo full in sdm_async block.
73702 … 0xf90c7cUL //Access:R DataWidth:0x1 // PRM FIFO full in PRM interface block.
73703 …90c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM interfac…
73704 …90c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM interfac…
73705 … //Access:R DataWidth:0x1 // Internal write completion pending empty in internal write block.
73706 …R DataWidth:0x1 // Internal write completion parameter pending empty in internal write block.
73707 … 0xf90d08UL //Access:R DataWidth:0x9 // Input queue fifo empty in sdm_inp block.
73708 … 0xf90d0cUL //Access:R DataWidth:0x1 // Delay FIFO empty in sdm_inp block.
73709 … 0xf90d10UL //Access:R DataWidth:0x1 // Pending FIFO empty in sdm_timers block.
73710 … 0xf90d14UL //Access:R DataWidth:0x1 // Address FIFO empty in sdm_timers block.
73711 … 0xf90d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty in sdm_dma_rsp block.
73712 … 0xf90d1cUL //Access:R DataWidth:0x1 // BRB read data fifo empty in sdm_dma_rsp block.
73713 … 0xf90d20UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo empty in sdm_dma_rsp block.
73714 … 0xf90d24UL //Access:R DataWidth:0x1 // BRB pending fifo empty in sdm_dma_rsp block.
73715 … 0xf90d28UL //Access:R DataWidth:0x1 // Int_ram pending fifo empty in sdm_dma_rsp block.
73716 … 0xf90d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empty in sdm_dma_dst block.
73717 …f90d30UL //Access:R DataWidth:0x1 // PXP destination pending fifo empty in sdm_dma_dst block.
73718 … 0xf90d34UL //Access:R DataWidth:0x1 // PXP source pending fifo empty in sdm_dma_dst block.
73719 … 0xf90d38UL //Access:R DataWidth:0x1 // BRB source pending fifo empty in sdm_dma_dst block.
73720 … 0xf90d3cUL //Access:R DataWidth:0x1 // BRB source address fifo empty in sdm_dma_dst block.
73721 … 0xf90d40UL //Access:R DataWidth:0x1 // PXP link list empty in sdm_dma_dst block.
73722 … 0xf90d44UL //Access:R DataWidth:0x1 // Int_ram_wait fifo empty in sdm_dma_dst block.
73723 … 0xf90d48UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo empty in sdm_dma_dst block.
73724 … 0xf90d4cUL //Access:R DataWidth:0x1 // Shared delay FIFO empty in SDM completion manag…
73725 … 0xf90d50UL //Access:R DataWidth:0x1 // CM delay FIFO empty in SDM completion manag…
73726 …90d54UL //Access:R DataWidth:0x1 // Completion message queue fifo empty in sdm_dma_dst block.
73727 … 0xf90d58UL //Access:R DataWidth:0x1 // CCFC load pending fifo empty in sdm_ccfc block.
73728 … 0xf90d5cUL //Access:R DataWidth:0x1 // TCFC load pending fifo empty in sdm_tcfc block.
73729 … 0xf90d60UL //Access:R DataWidth:0x1 // Async fifo empty in sdm_async block.
73730 … 0xf90d64UL //Access:R DataWidth:0x1 // PRM FIFO empty in sdm_prm_if block.
73738 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
73742 … 0xf92000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73744 … 0xf92400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
73746 … 0xf92800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
73748 … 0xf92c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
73750 … 0xf93000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
73752 … 0xf93400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
73754 … 0xf93800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
73756 … 0xf93c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
73758 … 0xf94000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
73769 … (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
73771 … (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
73773 … (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
73775 … (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
73777 … (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
73779 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
73781 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
73783 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
73785 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73789 … (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
73791 … (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
73793 … (0x1<<13) // Enable for input completion message from PRM in prm_if block.
73799 … (0x1<<16) // Enable for input response from CCFC in CCFC block.
73805 … (0x1<<19) // Enable for input full from qm in SDM_INP block.
73808 … (0x1<<0) // Enable for input response from TCFC in TCFC block.
73810 … (0x1<<1) // Enable for input acknowledge from Cm in SDM_CM block.
73812 … (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
73829 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
73831 … (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
73833 … (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
73835 … (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
73837 … (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
73839 … (0x1<<12) // Enable for output write to pxp in DMA_DST block.
73841 … (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
73843 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
73851 … (0x1<<18) // Enable for output message to CM in SDM_CM block.
73853 … (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
73855 … (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
73858 … (0x1<<0) // Enable for output command to qm in SDM_INP block.
73860 … (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
73862 … (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
73879 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Asy…
73890 … (0x1<<2) // Delay fifo in INP_CMD block output…
73892 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
73894 … (0x1<<4) // FIFO in PRM interface sub-module repo…
73896 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
73898 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
73900 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
73902 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
73904 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
73906 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
73908 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
73910 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
73912 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
73914 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
73916 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
73918 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
73920 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
73922 … (0x1<<18) // Delay CM fifo error in CM block.
73924 … (0x1<<19) // Delay shared fifo error in CM block.
73926 … (0x1<<20) // Error in completion pending FIFO in intern…
73928 … (0x1<<21) // Error in completion parameter pending FIFO in i…
73930 … (0x1<<22) // Address fifo error in timer block.
73932 … (0x1<<23) // Pending fifo error in timer block.
73934 … (0x1<<24) // Dpm fifo error in dorq I/F block.
73936 … (0x1<<25) // PXP done fifo error in DMA_dst block.
73938 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
73940 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
73944 … (0x1<<29) // Last-cycle indication not …
74016 … (0x1<<2) // Delay fifo in INP_CMD block output…
74018 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
74020 … (0x1<<4) // FIFO in PRM interface sub-module repo…
74022 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
74024 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
74026 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
74028 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
74030 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
74032 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
74034 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
74036 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
74038 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
74040 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
74042 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
74044 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
74046 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
74048 … (0x1<<18) // Delay CM fifo error in CM block.
74050 … (0x1<<19) // Delay shared fifo error in CM block.
74052 … (0x1<<20) // Error in completion pending FIFO in intern…
74054 … (0x1<<21) // Error in completion parameter pending FIFO in i…
74056 … (0x1<<22) // Address fifo error in timer block.
74058 … (0x1<<23) // Pending fifo error in timer block.
74060 … (0x1<<24) // Dpm fifo error in dorq I/F block.
74062 … (0x1<<25) // PXP done fifo error in DMA_dst block.
74064 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
74066 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
74070 …E5 (0x1<<29) // Last-cycle indication not …
74079 … (0x1<<2) // Delay fifo in INP_CMD block output…
74081 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
74083 … (0x1<<4) // FIFO in PRM interface sub-module repo…
74085 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
74087 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
74089 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
74091 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
74093 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
74095 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
74097 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
74099 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
74101 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
74103 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
74105 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
74107 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
74109 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
74111 … (0x1<<18) // Delay CM fifo error in CM block.
74113 … (0x1<<19) // Delay shared fifo error in CM block.
74115 … (0x1<<20) // Error in completion pending FIFO in intern…
74117 … (0x1<<21) // Error in completion parameter pending FIFO in i…
74119 … (0x1<<22) // Address fifo error in timer block.
74121 … (0x1<<23) // Pending fifo error in timer block.
74123 … (0x1<<24) // Dpm fifo error in dorq I/F block.
74125 … (0x1<<25) // PXP done fifo error in DMA_dst block.
74127 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
74129 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
74133 …_E5 (0x1<<29) // Last-cycle indication not …
74177 …ue_ram_wrap.PSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_even.i_ecc in module sdm_comp_msg_…
74179 …que_ram_wrap.PSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_odd.i_ecc in module sdm_comp_msg_…
74182 …ue_ram_wrap.PSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_even.i_ecc in module sdm_comp_msg_…
74184 …que_ram_wrap.PSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_odd.i_ecc in module sdm_comp_msg_…
74187 …ue_ram_wrap.PSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_even.i_ecc in module sdm_comp_msg_…
74189 …que_ram_wrap.PSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_odd.i_ecc in module sdm_comp_msg_…
74198 … 0xfa0414UL //Access:RW DataWidth:0xf // The start address in the internal RAM for…
74199 …ests in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC ma…
74200 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
74201 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
74202 …4UL //Access:R DataWidth:0x9 // This register is intended to be read in the event of an inp_…
74203 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
74206 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
74209 …nitial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.
74210 …l number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.
74224 …700UL //Access:RW DataWidth:0x5 // Almost full signal for read data from BRB in DMA_RSP block.
74225 …704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block.
74226 …8UL //Access:RW DataWidth:0x6 // Almost full signal for read data from DORQ in SDM_DORQ block.
74227 …in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,…
74233 … 0xfa0c00UL //Access:R DataWidth:0x9 // Input queue fifo full in sdm_inp block.
74234 …L //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block.
74235 …:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block.
74236 … 0xfa0c0cUL //Access:R DataWidth:0x1 // QM IF full in sdm_inp block.
74237 … 0xfa0c10UL //Access:R DataWidth:0x1 // Delay FIFO full in sdm_inp block.
74238 … 0xfa0c14UL //Access:R DataWidth:0x1 // Pending FIFO full in sdm_timers block.
74239 … 0xfa0c18UL //Access:R DataWidth:0x1 // Address FIFO full in sdm_timers block.
74240 … 0xfa0c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full in sdm_dma_rsp block.
74241 … 0xfa0c20UL //Access:R DataWidth:0x1 // BRB read data fifo full in sdm_dma_rsp block.
74242 … 0xfa0c24UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo full in sdm_dma_rsp block.
74243 … 0xfa0c28UL //Access:R DataWidth:0x1 // BRB pending fifo full in sdm_dma_rsp block.
74244 … 0xfa0c2cUL //Access:R DataWidth:0x1 // Int_ram pending fifo full in sdm_dma_rsp block.
74245 … 0xfa0c30UL //Access:R DataWidth:0x1 // BRB interface is full in sdm_dma_rsp block.
74246 … 0xfa0c34UL //Access:R DataWidth:0x1 // PXP interface is full in sdm_dma_rsp block.
74247 … 0xfa0c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full in sdm_dma_dst block.
74248 …xfa0c3cUL //Access:R DataWidth:0x1 // PXP destination pending fifo full in sdm_dma_dst block.
74249 … 0xfa0c40UL //Access:R DataWidth:0x1 // PXP source pending fifo full in sdm_dma_dst block.
74250 … 0xfa0c44UL //Access:R DataWidth:0x1 // BRB source pending fifo full in sdm_dma_dst block.
74251 … 0xfa0c48UL //Access:R DataWidth:0x1 // BRB source address fifo full in sdm_dma_dst block.
74252 … 0xfa0c4cUL //Access:R DataWidth:0x1 // PXP link list full in sdm_dma_dst block.
74253 … 0xfa0c50UL //Access:R DataWidth:0x1 // Int_ram_wait fifo full in sdm_dma_dst block.
74254 … 0xfa0c54UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo full in sdm_dma_dst block.
74255 … 0xfa0c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_dst block.
74256 … 0xfa0c5cUL //Access:R DataWidth:0x1 // Int_ram if full in sdm_dma_dst block.
74257 … 0xfa0c60UL //Access:R DataWidth:0x1 // Pas_buf if full in sdm_dma_dst block.
74258 … 0xfa0c64UL //Access:R DataWidth:0x1 // Shared delay FIFO full in SDM completion manag…
74259 … 0xfa0c68UL //Access:R DataWidth:0x1 // CM delay FIFO full in SDM completion manag…
74260 … 0xfa0c6cUL //Access:R DataWidth:0x1 // Completion message queue fifo full in sdm_cm block.
74261 … 0xfa0c70UL //Access:R DataWidth:0x1 // CCFC load pending fifo full in the CCFC interface …
74262 … 0xfa0c74UL //Access:R DataWidth:0x1 // TCFC load pending fifo full in the TCFC interface b…
74263 … 0xfa0c78UL //Access:R DataWidth:0x1 // Async fifo full in sdm_async block.
74264 … 0xfa0c7cUL //Access:R DataWidth:0x1 // PRM FIFO full in PRM interface block.
74265 …a0c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM interfac…
74266 …a0c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM interfac…
74267 … //Access:R DataWidth:0x1 // Internal write completion pending empty in internal write block.
74268 …R DataWidth:0x1 // Internal write completion parameter pending empty in internal write block.
74269 … 0xfa0d08UL //Access:R DataWidth:0x9 // Input queue fifo empty in sdm_inp block.
74270 … 0xfa0d0cUL //Access:R DataWidth:0x1 // Delay FIFO empty in sdm_inp block.
74271 … 0xfa0d10UL //Access:R DataWidth:0x1 // Pending FIFO empty in sdm_timers block.
74272 … 0xfa0d14UL //Access:R DataWidth:0x1 // Address FIFO empty in sdm_timers block.
74273 … 0xfa0d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty in sdm_dma_rsp block.
74274 … 0xfa0d1cUL //Access:R DataWidth:0x1 // BRB read data fifo empty in sdm_dma_rsp block.
74275 … 0xfa0d20UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo empty in sdm_dma_rsp block.
74276 … 0xfa0d24UL //Access:R DataWidth:0x1 // BRB pending fifo empty in sdm_dma_rsp block.
74277 … 0xfa0d28UL //Access:R DataWidth:0x1 // Int_ram pending fifo empty in sdm_dma_rsp block.
74278 … 0xfa0d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empty in sdm_dma_dst block.
74279 …fa0d30UL //Access:R DataWidth:0x1 // PXP destination pending fifo empty in sdm_dma_dst block.
74280 … 0xfa0d34UL //Access:R DataWidth:0x1 // PXP source pending fifo empty in sdm_dma_dst block.
74281 … 0xfa0d38UL //Access:R DataWidth:0x1 // BRB source pending fifo empty in sdm_dma_dst block.
74282 … 0xfa0d3cUL //Access:R DataWidth:0x1 // BRB source address fifo empty in sdm_dma_dst block.
74283 … 0xfa0d40UL //Access:R DataWidth:0x1 // PXP link list empty in sdm_dma_dst block.
74284 … 0xfa0d44UL //Access:R DataWidth:0x1 // Int_ram_wait fifo empty in sdm_dma_dst block.
74285 … 0xfa0d48UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo empty in sdm_dma_dst block.
74286 … 0xfa0d4cUL //Access:R DataWidth:0x1 // Shared delay FIFO empty in SDM completion manag…
74287 … 0xfa0d50UL //Access:R DataWidth:0x1 // CM delay FIFO empty in SDM completion manag…
74288 …a0d54UL //Access:R DataWidth:0x1 // Completion message queue fifo empty in sdm_dma_dst block.
74289 … 0xfa0d58UL //Access:R DataWidth:0x1 // CCFC load pending fifo empty in sdm_ccfc block.
74290 … 0xfa0d5cUL //Access:R DataWidth:0x1 // TCFC load pending fifo empty in sdm_tcfc block.
74291 … 0xfa0d60UL //Access:R DataWidth:0x1 // Async fifo empty in sdm_async block.
74292 … 0xfa0d64UL //Access:R DataWidth:0x1 // PRM FIFO empty in sdm_prm_if block.
74300 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
74304 … 0xfa2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74306 … 0xfa2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
74308 … 0xfa2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
74310 … 0xfa2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
74312 … 0xfa3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
74314 … 0xfa3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
74316 … 0xfa3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
74318 … 0xfa3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
74320 … 0xfa4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
74331 … (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
74333 … (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
74335 … (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
74337 … (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
74339 … (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
74341 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
74343 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
74345 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
74347 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74351 … (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
74353 … (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
74355 … (0x1<<13) // Enable for input completion message from PRM in prm_if block.
74361 … (0x1<<16) // Enable for input response from CCFC in CCFC block.
74367 … (0x1<<19) // Enable for input full from qm in SDM_INP block.
74370 … (0x1<<0) // Enable for input response from TCFC in TCFC block.
74372 … (0x1<<1) // Enable for input acknowledge from Cm in SDM_CM block.
74374 … (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
74391 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
74393 … (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
74395 … (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
74397 … (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
74399 … (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
74401 … (0x1<<12) // Enable for output write to pxp in DMA_DST block.
74403 … (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
74405 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
74413 … (0x1<<18) // Enable for output message to CM in SDM_CM block.
74415 … (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
74417 … (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
74420 … (0x1<<0) // Enable for output command to qm in SDM_INP block.
74422 … (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
74424 … (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
74441 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Asy…
74452 … (0x1<<2) // Delay fifo in INP_CMD block output…
74454 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
74456 … (0x1<<4) // FIFO in PRM interface sub-module repo…
74458 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
74460 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
74462 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
74464 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
74466 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
74468 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
74470 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
74472 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
74474 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
74476 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
74478 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
74480 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
74482 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
74484 … (0x1<<18) // Delay CM fifo error in CM block.
74486 … (0x1<<19) // Delay shared fifo error in CM block.
74488 … (0x1<<20) // Error in completion pending FIFO in intern…
74490 … (0x1<<21) // Error in completion parameter pending FIFO in i…
74492 … (0x1<<22) // Address fifo error in timer block.
74494 … (0x1<<23) // Pending fifo error in timer block.
74496 … (0x1<<24) // Dpm fifo error in dorq I/F block.
74498 … (0x1<<25) // PXP done fifo error in DMA_dst block.
74500 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
74502 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
74506 … (0x1<<29) // Last-cycle indication not …
74578 … (0x1<<2) // Delay fifo in INP_CMD block output…
74580 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
74582 … (0x1<<4) // FIFO in PRM interface sub-module repo…
74584 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
74586 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
74588 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
74590 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
74592 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
74594 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
74596 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
74598 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
74600 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
74602 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
74604 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
74606 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
74608 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
74610 … (0x1<<18) // Delay CM fifo error in CM block.
74612 … (0x1<<19) // Delay shared fifo error in CM block.
74614 … (0x1<<20) // Error in completion pending FIFO in intern…
74616 … (0x1<<21) // Error in completion parameter pending FIFO in i…
74618 … (0x1<<22) // Address fifo error in timer block.
74620 … (0x1<<23) // Pending fifo error in timer block.
74622 … (0x1<<24) // Dpm fifo error in dorq I/F block.
74624 … (0x1<<25) // PXP done fifo error in DMA_dst block.
74626 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
74628 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
74632 …E5 (0x1<<29) // Last-cycle indication not …
74641 … (0x1<<2) // Delay fifo in INP_CMD block output…
74643 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
74645 … (0x1<<4) // FIFO in PRM interface sub-module repo…
74647 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
74649 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
74651 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
74653 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
74655 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
74657 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
74659 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
74661 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
74663 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
74665 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
74667 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
74669 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
74671 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
74673 … (0x1<<18) // Delay CM fifo error in CM block.
74675 … (0x1<<19) // Delay shared fifo error in CM block.
74677 … (0x1<<20) // Error in completion pending FIFO in intern…
74679 … (0x1<<21) // Error in completion parameter pending FIFO in i…
74681 … (0x1<<22) // Address fifo error in timer block.
74683 … (0x1<<23) // Pending fifo error in timer block.
74685 … (0x1<<24) // Dpm fifo error in dorq I/F block.
74687 … (0x1<<25) // PXP done fifo error in DMA_dst block.
74689 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
74691 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
74695 …_E5 (0x1<<29) // Last-cycle indication not …
74740 … 0xfb0414UL //Access:RW DataWidth:0xf // The start address in the internal RAM for…
74741 …ests in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC ma…
74742 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
74743 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
74744 …4UL //Access:R DataWidth:0x9 // This register is intended to be read in the event of an inp_…
74745 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
74748 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
74751 …nitial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.
74752 …l number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.
74765 …700UL //Access:RW DataWidth:0x5 // Almost full signal for read data from BRB in DMA_RSP block.
74766 …704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block.
74767 …8UL //Access:RW DataWidth:0x6 // Almost full signal for read data from DORQ in SDM_DORQ block.
74768 …in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,…
74774 … 0xfb0c00UL //Access:R DataWidth:0x9 // Input queue fifo full in sdm_inp block.
74775 …L //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block.
74776 …:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block.
74777 … 0xfb0c0cUL //Access:R DataWidth:0x1 // QM IF full in sdm_inp block.
74778 … 0xfb0c10UL //Access:R DataWidth:0x1 // Delay FIFO full in sdm_inp block.
74779 … 0xfb0c14UL //Access:R DataWidth:0x1 // Pending FIFO full in sdm_timers block.
74780 … 0xfb0c18UL //Access:R DataWidth:0x1 // Address FIFO full in sdm_timers block.
74781 … 0xfb0c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full in sdm_dma_rsp block.
74782 … 0xfb0c20UL //Access:R DataWidth:0x1 // BRB read data fifo full in sdm_dma_rsp block.
74783 … 0xfb0c24UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo full in sdm_dma_rsp block.
74784 … 0xfb0c28UL //Access:R DataWidth:0x1 // BRB pending fifo full in sdm_dma_rsp block.
74785 … 0xfb0c2cUL //Access:R DataWidth:0x1 // Int_ram pending fifo full in sdm_dma_rsp block.
74786 … 0xfb0c30UL //Access:R DataWidth:0x1 // BRB interface is full in sdm_dma_rsp block.
74787 … 0xfb0c34UL //Access:R DataWidth:0x1 // PXP interface is full in sdm_dma_rsp block.
74788 … 0xfb0c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full in sdm_dma_dst block.
74789 …xfb0c3cUL //Access:R DataWidth:0x1 // PXP destination pending fifo full in sdm_dma_dst block.
74790 … 0xfb0c40UL //Access:R DataWidth:0x1 // PXP source pending fifo full in sdm_dma_dst block.
74791 … 0xfb0c44UL //Access:R DataWidth:0x1 // BRB source pending fifo full in sdm_dma_dst block.
74792 … 0xfb0c48UL //Access:R DataWidth:0x1 // BRB source address fifo full in sdm_dma_dst block.
74793 … 0xfb0c4cUL //Access:R DataWidth:0x1 // PXP link list full in sdm_dma_dst block.
74794 … 0xfb0c50UL //Access:R DataWidth:0x1 // Int_ram_wait fifo full in sdm_dma_dst block.
74795 … 0xfb0c54UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo full in sdm_dma_dst block.
74796 … 0xfb0c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_dst block.
74797 … 0xfb0c5cUL //Access:R DataWidth:0x1 // Int_ram if full in sdm_dma_dst block.
74798 … 0xfb0c60UL //Access:R DataWidth:0x1 // Pas_buf if full in sdm_dma_dst block.
74799 … 0xfb0c64UL //Access:R DataWidth:0x1 // Shared delay FIFO full in SDM completion manag…
74800 … 0xfb0c68UL //Access:R DataWidth:0x1 // CM delay FIFO full in SDM completion manag…
74801 … 0xfb0c6cUL //Access:R DataWidth:0x1 // Completion message queue fifo full in sdm_cm block.
74802 … 0xfb0c70UL //Access:R DataWidth:0x1 // CCFC load pending fifo full in the CCFC interface …
74803 … 0xfb0c74UL //Access:R DataWidth:0x1 // TCFC load pending fifo full in the TCFC interface b…
74804 … 0xfb0c78UL //Access:R DataWidth:0x1 // Async fifo full in sdm_async block.
74805 … 0xfb0c7cUL //Access:R DataWidth:0x1 // PRM FIFO full in PRM interface block.
74806 …b0c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM interfac…
74807 …b0c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM interfac…
74808 … //Access:R DataWidth:0x1 // Internal write completion pending empty in internal write block.
74809 …R DataWidth:0x1 // Internal write completion parameter pending empty in internal write block.
74810 … 0xfb0d08UL //Access:R DataWidth:0x9 // Input queue fifo empty in sdm_inp block.
74811 … 0xfb0d0cUL //Access:R DataWidth:0x1 // Delay FIFO empty in sdm_inp block.
74812 … 0xfb0d10UL //Access:R DataWidth:0x1 // Pending FIFO empty in sdm_timers block.
74813 … 0xfb0d14UL //Access:R DataWidth:0x1 // Address FIFO empty in sdm_timers block.
74814 … 0xfb0d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty in sdm_dma_rsp block.
74815 … 0xfb0d1cUL //Access:R DataWidth:0x1 // BRB read data fifo empty in sdm_dma_rsp block.
74816 … 0xfb0d20UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo empty in sdm_dma_rsp block.
74817 … 0xfb0d24UL //Access:R DataWidth:0x1 // BRB pending fifo empty in sdm_dma_rsp block.
74818 … 0xfb0d28UL //Access:R DataWidth:0x1 // Int_ram pending fifo empty in sdm_dma_rsp block.
74819 … 0xfb0d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empty in sdm_dma_dst block.
74820 …fb0d30UL //Access:R DataWidth:0x1 // PXP destination pending fifo empty in sdm_dma_dst block.
74821 … 0xfb0d34UL //Access:R DataWidth:0x1 // PXP source pending fifo empty in sdm_dma_dst block.
74822 … 0xfb0d38UL //Access:R DataWidth:0x1 // BRB source pending fifo empty in sdm_dma_dst block.
74823 … 0xfb0d3cUL //Access:R DataWidth:0x1 // BRB source address fifo empty in sdm_dma_dst block.
74824 … 0xfb0d40UL //Access:R DataWidth:0x1 // PXP link list empty in sdm_dma_dst block.
74825 … 0xfb0d44UL //Access:R DataWidth:0x1 // Int_ram_wait fifo empty in sdm_dma_dst block.
74826 … 0xfb0d48UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo empty in sdm_dma_dst block.
74827 … 0xfb0d4cUL //Access:R DataWidth:0x1 // Shared delay FIFO empty in SDM completion manag…
74828 … 0xfb0d50UL //Access:R DataWidth:0x1 // CM delay FIFO empty in SDM completion manag…
74829 …b0d54UL //Access:R DataWidth:0x1 // Completion message queue fifo empty in sdm_dma_dst block.
74830 … 0xfb0d58UL //Access:R DataWidth:0x1 // CCFC load pending fifo empty in sdm_ccfc block.
74831 … 0xfb0d5cUL //Access:R DataWidth:0x1 // TCFC load pending fifo empty in sdm_tcfc block.
74832 … 0xfb0d60UL //Access:R DataWidth:0x1 // Async fifo empty in sdm_async block.
74833 … 0xfb0d64UL //Access:R DataWidth:0x1 // PRM FIFO empty in sdm_prm_if block.
74841 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
74845 … 0xfb2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74847 … 0xfb2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
74849 … 0xfb2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
74851 … 0xfb2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
74853 … 0xfb3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
74855 … 0xfb3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
74857 … 0xfb3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
74859 … 0xfb3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
74861 … 0xfb4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
74872 … (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
74874 … (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
74876 … (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
74878 … (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
74880 … (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
74882 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
74884 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
74886 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
74888 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74892 … (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
74894 … (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
74896 … (0x1<<13) // Enable for input completion message from PRM in prm_if block.
74902 … (0x1<<16) // Enable for input response from CCFC in CCFC block.
74908 … (0x1<<19) // Enable for input full from qm in SDM_INP block.
74911 … (0x1<<0) // Enable for input response from TCFC in TCFC block.
74913 … (0x1<<1) // Enable for input acknowledge from Cm in SDM_CM block.
74915 … (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
74932 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
74934 … (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
74936 … (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
74938 … (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
74940 … (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
74942 … (0x1<<12) // Enable for output write to pxp in DMA_DST block.
74944 … (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
74946 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
74954 … (0x1<<18) // Enable for output message to CM in SDM_CM block.
74956 … (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
74958 … (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
74961 … (0x1<<0) // Enable for output command to qm in SDM_INP block.
74963 … (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
74965 … (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
74982 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Asy…
74993 … (0x1<<2) // Delay fifo in INP_CMD block output…
74995 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
74997 … (0x1<<4) // FIFO in PRM interface sub-module repo…
74999 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
75001 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
75003 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
75005 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
75007 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
75009 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
75011 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
75013 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
75015 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
75017 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
75019 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
75021 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
75023 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
75025 … (0x1<<18) // Delay CM fifo error in CM block.
75027 … (0x1<<19) // Delay shared fifo error in CM block.
75029 … (0x1<<20) // Error in completion pending FIFO in intern…
75031 … (0x1<<21) // Error in completion parameter pending FIFO in i…
75033 … (0x1<<22) // Address fifo error in timer block.
75035 … (0x1<<23) // Pending fifo error in timer block.
75037 … (0x1<<24) // Dpm fifo error in dorq I/F block.
75039 … (0x1<<25) // PXP done fifo error in DMA_dst block.
75041 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
75043 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
75047 … (0x1<<29) // Last-cycle indication not …
75119 … (0x1<<2) // Delay fifo in INP_CMD block output…
75121 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
75123 … (0x1<<4) // FIFO in PRM interface sub-module repo…
75125 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
75127 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
75129 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
75131 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
75133 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
75135 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
75137 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
75139 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
75141 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
75143 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
75145 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
75147 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
75149 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
75151 … (0x1<<18) // Delay CM fifo error in CM block.
75153 … (0x1<<19) // Delay shared fifo error in CM block.
75155 … (0x1<<20) // Error in completion pending FIFO in intern…
75157 … (0x1<<21) // Error in completion parameter pending FIFO in i…
75159 … (0x1<<22) // Address fifo error in timer block.
75161 … (0x1<<23) // Pending fifo error in timer block.
75163 … (0x1<<24) // Dpm fifo error in dorq I/F block.
75165 … (0x1<<25) // PXP done fifo error in DMA_dst block.
75167 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
75169 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
75173 …E5 (0x1<<29) // Last-cycle indication not …
75182 … (0x1<<2) // Delay fifo in INP_CMD block output…
75184 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
75186 … (0x1<<4) // FIFO in PRM interface sub-module repo…
75188 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
75190 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
75192 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
75194 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
75196 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
75198 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
75200 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
75202 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
75204 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
75206 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
75208 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
75210 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
75212 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
75214 … (0x1<<18) // Delay CM fifo error in CM block.
75216 … (0x1<<19) // Delay shared fifo error in CM block.
75218 … (0x1<<20) // Error in completion pending FIFO in intern…
75220 … (0x1<<21) // Error in completion parameter pending FIFO in i…
75222 … (0x1<<22) // Address fifo error in timer block.
75224 … (0x1<<23) // Pending fifo error in timer block.
75226 … (0x1<<24) // Dpm fifo error in dorq I/F block.
75228 … (0x1<<25) // PXP done fifo error in DMA_dst block.
75230 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
75232 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
75236 …_E5 (0x1<<29) // Last-cycle indication not …
75288 …ue_ram_wrap.MSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_even.i_ecc in module sdm_comp_msg_…
75290 …que_ram_wrap.MSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_odd.i_ecc in module sdm_comp_msg_…
75293 …ue_ram_wrap.MSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_even.i_ecc in module sdm_comp_msg_…
75295 …que_ram_wrap.MSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_odd.i_ecc in module sdm_comp_msg_…
75298 …ue_ram_wrap.MSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_even.i_ecc in module sdm_comp_msg_…
75300 …que_ram_wrap.MSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_odd.i_ecc in module sdm_comp_msg_…
75309 … 0xfc0414UL //Access:RW DataWidth:0xf // The start address in the internal RAM for…
75310 …ests in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC ma…
75311 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
75312 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
75313 …4UL //Access:R DataWidth:0x9 // This register is intended to be read in the event of an inp_…
75314 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
75317 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
75320 …nitial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.
75321 …l number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.
75336 …700UL //Access:RW DataWidth:0x5 // Almost full signal for read data from BRB in DMA_RSP block.
75337 …704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block.
75338 …8UL //Access:RW DataWidth:0x6 // Almost full signal for read data from DORQ in SDM_DORQ block.
75339 …in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,…
75345 … 0xfc0c00UL //Access:R DataWidth:0x9 // Input queue fifo full in sdm_inp block.
75346 …L //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block.
75347 …:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block.
75348 … 0xfc0c0cUL //Access:R DataWidth:0x1 // QM IF full in sdm_inp block.
75349 … 0xfc0c10UL //Access:R DataWidth:0x1 // Delay FIFO full in sdm_inp block.
75350 … 0xfc0c14UL //Access:R DataWidth:0x1 // Pending FIFO full in sdm_timers block.
75351 … 0xfc0c18UL //Access:R DataWidth:0x1 // Address FIFO full in sdm_timers block.
75352 … 0xfc0c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full in sdm_dma_rsp block.
75353 … 0xfc0c20UL //Access:R DataWidth:0x1 // BRB read data fifo full in sdm_dma_rsp block.
75354 … 0xfc0c24UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo full in sdm_dma_rsp block.
75355 … 0xfc0c28UL //Access:R DataWidth:0x1 // BRB pending fifo full in sdm_dma_rsp block.
75356 … 0xfc0c2cUL //Access:R DataWidth:0x1 // Int_ram pending fifo full in sdm_dma_rsp block.
75357 … 0xfc0c30UL //Access:R DataWidth:0x1 // BRB interface is full in sdm_dma_rsp block.
75358 … 0xfc0c34UL //Access:R DataWidth:0x1 // PXP interface is full in sdm_dma_rsp block.
75359 … 0xfc0c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full in sdm_dma_dst block.
75360 …xfc0c3cUL //Access:R DataWidth:0x1 // PXP destination pending fifo full in sdm_dma_dst block.
75361 … 0xfc0c40UL //Access:R DataWidth:0x1 // PXP source pending fifo full in sdm_dma_dst block.
75362 … 0xfc0c44UL //Access:R DataWidth:0x1 // BRB source pending fifo full in sdm_dma_dst block.
75363 … 0xfc0c48UL //Access:R DataWidth:0x1 // BRB source address fifo full in sdm_dma_dst block.
75364 … 0xfc0c4cUL //Access:R DataWidth:0x1 // PXP link list full in sdm_dma_dst block.
75365 … 0xfc0c50UL //Access:R DataWidth:0x1 // Int_ram_wait fifo full in sdm_dma_dst block.
75366 … 0xfc0c54UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo full in sdm_dma_dst block.
75367 … 0xfc0c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_dst block.
75368 … 0xfc0c5cUL //Access:R DataWidth:0x1 // Int_ram if full in sdm_dma_dst block.
75369 … 0xfc0c60UL //Access:R DataWidth:0x1 // Pas_buf if full in sdm_dma_dst block.
75370 … 0xfc0c64UL //Access:R DataWidth:0x1 // Shared delay FIFO full in SDM completion manag…
75371 … 0xfc0c68UL //Access:R DataWidth:0x1 // CM delay FIFO full in SDM completion manag…
75372 … 0xfc0c6cUL //Access:R DataWidth:0x1 // Completion message queue fifo full in sdm_cm block.
75373 … 0xfc0c70UL //Access:R DataWidth:0x1 // CCFC load pending fifo full in the CCFC interface …
75374 … 0xfc0c74UL //Access:R DataWidth:0x1 // TCFC load pending fifo full in the TCFC interface b…
75375 … 0xfc0c78UL //Access:R DataWidth:0x1 // Async fifo full in sdm_async block.
75376 … 0xfc0c7cUL //Access:R DataWidth:0x1 // PRM FIFO full in PRM interface block.
75377 …c0c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM interfac…
75378 …c0c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM interfac…
75379 … //Access:R DataWidth:0x1 // Internal write completion pending empty in internal write block.
75380 …R DataWidth:0x1 // Internal write completion parameter pending empty in internal write block.
75381 … 0xfc0d08UL //Access:R DataWidth:0x9 // Input queue fifo empty in sdm_inp block.
75382 … 0xfc0d0cUL //Access:R DataWidth:0x1 // Delay FIFO empty in sdm_inp block.
75383 … 0xfc0d10UL //Access:R DataWidth:0x1 // Pending FIFO empty in sdm_timers block.
75384 … 0xfc0d14UL //Access:R DataWidth:0x1 // Address FIFO empty in sdm_timers block.
75385 … 0xfc0d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty in sdm_dma_rsp block.
75386 … 0xfc0d1cUL //Access:R DataWidth:0x1 // BRB read data fifo empty in sdm_dma_rsp block.
75387 … 0xfc0d20UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo empty in sdm_dma_rsp block.
75388 … 0xfc0d24UL //Access:R DataWidth:0x1 // BRB pending fifo empty in sdm_dma_rsp block.
75389 … 0xfc0d28UL //Access:R DataWidth:0x1 // Int_ram pending fifo empty in sdm_dma_rsp block.
75390 … 0xfc0d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empty in sdm_dma_dst block.
75391 …fc0d30UL //Access:R DataWidth:0x1 // PXP destination pending fifo empty in sdm_dma_dst block.
75392 … 0xfc0d34UL //Access:R DataWidth:0x1 // PXP source pending fifo empty in sdm_dma_dst block.
75393 … 0xfc0d38UL //Access:R DataWidth:0x1 // BRB source pending fifo empty in sdm_dma_dst block.
75394 … 0xfc0d3cUL //Access:R DataWidth:0x1 // BRB source address fifo empty in sdm_dma_dst block.
75395 … 0xfc0d40UL //Access:R DataWidth:0x1 // PXP link list empty in sdm_dma_dst block.
75396 … 0xfc0d44UL //Access:R DataWidth:0x1 // Int_ram_wait fifo empty in sdm_dma_dst block.
75397 … 0xfc0d48UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo empty in sdm_dma_dst block.
75398 … 0xfc0d4cUL //Access:R DataWidth:0x1 // Shared delay FIFO empty in SDM completion manag…
75399 … 0xfc0d50UL //Access:R DataWidth:0x1 // CM delay FIFO empty in SDM completion manag…
75400 …c0d54UL //Access:R DataWidth:0x1 // Completion message queue fifo empty in sdm_dma_dst block.
75401 … 0xfc0d58UL //Access:R DataWidth:0x1 // CCFC load pending fifo empty in sdm_ccfc block.
75402 … 0xfc0d5cUL //Access:R DataWidth:0x1 // TCFC load pending fifo empty in sdm_tcfc block.
75403 … 0xfc0d60UL //Access:R DataWidth:0x1 // Async fifo empty in sdm_async block.
75404 … 0xfc0d64UL //Access:R DataWidth:0x1 // PRM FIFO empty in sdm_prm_if block.
75412 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
75416 … 0xfc2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75418 … 0xfc2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
75420 … 0xfc2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
75422 … 0xfc2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
75424 … 0xfc3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
75426 … 0xfc3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
75428 … 0xfc3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
75430 … 0xfc3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
75432 … 0xfc4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
75443 … (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
75445 … (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
75447 … (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
75449 … (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
75451 … (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
75453 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
75455 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
75457 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
75459 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
75463 … (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
75465 … (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
75467 … (0x1<<13) // Enable for input completion message from PRM in prm_if block.
75473 … (0x1<<16) // Enable for input response from CCFC in CCFC block.
75479 … (0x1<<19) // Enable for input full from qm in SDM_INP block.
75482 … (0x1<<0) // Enable for input response from TCFC in TCFC block.
75484 … (0x1<<1) // Enable for input acknowledge from Cm in SDM_CM block.
75486 … (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
75503 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
75505 … (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
75507 … (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
75509 … (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
75511 … (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
75513 … (0x1<<12) // Enable for output write to pxp in DMA_DST block.
75515 … (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
75517 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
75525 … (0x1<<18) // Enable for output message to CM in SDM_CM block.
75527 … (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
75529 … (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
75532 … (0x1<<0) // Enable for output command to qm in SDM_INP block.
75534 … (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
75536 … (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
75553 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Asy…
75564 … (0x1<<2) // Delay fifo in INP_CMD block output…
75566 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
75568 … (0x1<<4) // FIFO in PRM interface sub-module repo…
75570 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
75572 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
75574 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
75576 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
75578 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
75580 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
75582 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
75584 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
75586 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
75588 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
75590 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
75592 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
75594 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
75596 … (0x1<<18) // Delay CM fifo error in CM block.
75598 … (0x1<<19) // Delay shared fifo error in CM block.
75600 … (0x1<<20) // Error in completion pending FIFO in intern…
75602 … (0x1<<21) // Error in completion parameter pending FIFO in i…
75604 … (0x1<<22) // Address fifo error in timer block.
75606 … (0x1<<23) // Pending fifo error in timer block.
75608 … (0x1<<24) // Dpm fifo error in dorq I/F block.
75610 … (0x1<<25) // PXP done fifo error in DMA_dst block.
75612 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
75614 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
75618 … (0x1<<29) // Last-cycle indication not …
75690 … (0x1<<2) // Delay fifo in INP_CMD block output…
75692 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
75694 … (0x1<<4) // FIFO in PRM interface sub-module repo…
75696 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
75698 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
75700 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
75702 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
75704 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
75706 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
75708 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
75710 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
75712 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
75714 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
75716 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
75718 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
75720 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
75722 … (0x1<<18) // Delay CM fifo error in CM block.
75724 … (0x1<<19) // Delay shared fifo error in CM block.
75726 … (0x1<<20) // Error in completion pending FIFO in intern…
75728 … (0x1<<21) // Error in completion parameter pending FIFO in i…
75730 … (0x1<<22) // Address fifo error in timer block.
75732 … (0x1<<23) // Pending fifo error in timer block.
75734 … (0x1<<24) // Dpm fifo error in dorq I/F block.
75736 … (0x1<<25) // PXP done fifo error in DMA_dst block.
75738 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
75740 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
75744 …E5 (0x1<<29) // Last-cycle indication not …
75753 … (0x1<<2) // Delay fifo in INP_CMD block output…
75755 … (0x1<<3) // PXP_HOST fifo in ASYNC block outputs …
75757 … (0x1<<4) // FIFO in PRM interface sub-module repo…
75759 … (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs e…
75761 … (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs e…
75763 … (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
75765 … (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
75767 … (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
75769 … (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
75771 … (0x1<<11) // BRB src pend fifo error in DMA_DST block.
75773 … (0x1<<12) // BRB src addr fifo error in DMA_DST block.
75775 … (0x1<<13) // Pend data fifo in DMA_RSP block for BR…
75777 … (0x1<<14) // Pend data fifo in DMA_RSP block for in…
75779 … (0x1<<15) // Read data firo in DMA_RSP block for BR…
75781 … (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
75783 … (0x1<<17) // PXP read data fifo error in DMA_RSP block.
75785 … (0x1<<18) // Delay CM fifo error in CM block.
75787 … (0x1<<19) // Delay shared fifo error in CM block.
75789 … (0x1<<20) // Error in completion pending FIFO in intern…
75791 … (0x1<<21) // Error in completion parameter pending FIFO in i…
75793 … (0x1<<22) // Address fifo error in timer block.
75795 … (0x1<<23) // Pending fifo error in timer block.
75797 … (0x1<<24) // Dpm fifo error in dorq I/F block.
75799 … (0x1<<25) // PXP done fifo error in DMA_dst block.
75801 … (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
75803 … (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and…
75807 …_E5 (0x1<<29) // Last-cycle indication not …
75852 … 0xfd0414UL //Access:RW DataWidth:0xf // The start address in the internal RAM for…
75853 …ests in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC ma…
75854 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
75855 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
75856 …4UL //Access:R DataWidth:0x9 // This register is intended to be read in the event of an inp_…
75857 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
75860 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
75863 …nitial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.
75864 …l number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.
75878 …700UL //Access:RW DataWidth:0x5 // Almost full signal for read data from BRB in DMA_RSP block.
75879 …704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block.
75880 …8UL //Access:RW DataWidth:0x6 // Almost full signal for read data from DORQ in SDM_DORQ block.
75881 …in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,…
75887 … 0xfd0c00UL //Access:R DataWidth:0x9 // Input queue fifo full in sdm_inp block.
75888 …L //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block.
75889 …:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block.
75890 … 0xfd0c0cUL //Access:R DataWidth:0x1 // QM IF full in sdm_inp block.
75891 … 0xfd0c10UL //Access:R DataWidth:0x1 // Delay FIFO full in sdm_inp block.
75892 … 0xfd0c14UL //Access:R DataWidth:0x1 // Pending FIFO full in sdm_timers block.
75893 … 0xfd0c18UL //Access:R DataWidth:0x1 // Address FIFO full in sdm_timers block.
75894 … 0xfd0c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full in sdm_dma_rsp block.
75895 … 0xfd0c20UL //Access:R DataWidth:0x1 // BRB read data fifo full in sdm_dma_rsp block.
75896 … 0xfd0c24UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo full in sdm_dma_rsp block.
75897 … 0xfd0c28UL //Access:R DataWidth:0x1 // BRB pending fifo full in sdm_dma_rsp block.
75898 … 0xfd0c2cUL //Access:R DataWidth:0x1 // Int_ram pending fifo full in sdm_dma_rsp block.
75899 … 0xfd0c30UL //Access:R DataWidth:0x1 // BRB interface is full in sdm_dma_rsp block.
75900 … 0xfd0c34UL //Access:R DataWidth:0x1 // PXP interface is full in sdm_dma_rsp block.
75901 … 0xfd0c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full in sdm_dma_dst block.
75902 …xfd0c3cUL //Access:R DataWidth:0x1 // PXP destination pending fifo full in sdm_dma_dst block.
75903 … 0xfd0c40UL //Access:R DataWidth:0x1 // PXP source pending fifo full in sdm_dma_dst block.
75904 … 0xfd0c44UL //Access:R DataWidth:0x1 // BRB source pending fifo full in sdm_dma_dst block.
75905 … 0xfd0c48UL //Access:R DataWidth:0x1 // BRB source address fifo full in sdm_dma_dst block.
75906 … 0xfd0c4cUL //Access:R DataWidth:0x1 // PXP link list full in sdm_dma_dst block.
75907 … 0xfd0c50UL //Access:R DataWidth:0x1 // Int_ram_wait fifo full in sdm_dma_dst block.
75908 … 0xfd0c54UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo full in sdm_dma_dst block.
75909 … 0xfd0c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_dst block.
75910 … 0xfd0c5cUL //Access:R DataWidth:0x1 // Int_ram if full in sdm_dma_dst block.
75911 … 0xfd0c60UL //Access:R DataWidth:0x1 // Pas_buf if full in sdm_dma_dst block.
75912 … 0xfd0c64UL //Access:R DataWidth:0x1 // Shared delay FIFO full in SDM completion manag…
75913 … 0xfd0c68UL //Access:R DataWidth:0x1 // CM delay FIFO full in SDM completion manag…
75914 … 0xfd0c6cUL //Access:R DataWidth:0x1 // Completion message queue fifo full in sdm_cm block.
75915 … 0xfd0c70UL //Access:R DataWidth:0x1 // CCFC load pending fifo full in the CCFC interface …
75916 … 0xfd0c74UL //Access:R DataWidth:0x1 // TCFC load pending fifo full in the TCFC interface b…
75917 … 0xfd0c78UL //Access:R DataWidth:0x1 // Async fifo full in sdm_async block.
75918 … 0xfd0c7cUL //Access:R DataWidth:0x1 // PRM FIFO full in PRM interface block.
75919 …d0c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM interfac…
75920 …d0c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM interfac…
75921 … //Access:R DataWidth:0x1 // Internal write completion pending empty in internal write block.
75922 …R DataWidth:0x1 // Internal write completion parameter pending empty in internal write block.
75923 … 0xfd0d08UL //Access:R DataWidth:0x9 // Input queue fifo empty in sdm_inp block.
75924 … 0xfd0d0cUL //Access:R DataWidth:0x1 // Delay FIFO empty in sdm_inp block.
75925 … 0xfd0d10UL //Access:R DataWidth:0x1 // Pending FIFO empty in sdm_timers block.
75926 … 0xfd0d14UL //Access:R DataWidth:0x1 // Address FIFO empty in sdm_timers block.
75927 … 0xfd0d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty in sdm_dma_rsp block.
75928 … 0xfd0d1cUL //Access:R DataWidth:0x1 // BRB read data fifo empty in sdm_dma_rsp block.
75929 … 0xfd0d20UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo empty in sdm_dma_rsp block.
75930 … 0xfd0d24UL //Access:R DataWidth:0x1 // BRB pending fifo empty in sdm_dma_rsp block.
75931 … 0xfd0d28UL //Access:R DataWidth:0x1 // Int_ram pending fifo empty in sdm_dma_rsp block.
75932 … 0xfd0d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empty in sdm_dma_dst block.
75933 …fd0d30UL //Access:R DataWidth:0x1 // PXP destination pending fifo empty in sdm_dma_dst block.
75934 … 0xfd0d34UL //Access:R DataWidth:0x1 // PXP source pending fifo empty in sdm_dma_dst block.
75935 … 0xfd0d38UL //Access:R DataWidth:0x1 // BRB source pending fifo empty in sdm_dma_dst block.
75936 … 0xfd0d3cUL //Access:R DataWidth:0x1 // BRB source address fifo empty in sdm_dma_dst block.
75937 … 0xfd0d40UL //Access:R DataWidth:0x1 // PXP link list empty in sdm_dma_dst block.
75938 … 0xfd0d44UL //Access:R DataWidth:0x1 // Int_ram_wait fifo empty in sdm_dma_dst block.
75939 … 0xfd0d48UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo empty in sdm_dma_dst block.
75940 … 0xfd0d4cUL //Access:R DataWidth:0x1 // Shared delay FIFO empty in SDM completion manag…
75941 … 0xfd0d50UL //Access:R DataWidth:0x1 // CM delay FIFO empty in SDM completion manag…
75942 …d0d54UL //Access:R DataWidth:0x1 // Completion message queue fifo empty in sdm_dma_dst block.
75943 … 0xfd0d58UL //Access:R DataWidth:0x1 // CCFC load pending fifo empty in sdm_ccfc block.
75944 … 0xfd0d5cUL //Access:R DataWidth:0x1 // TCFC load pending fifo empty in sdm_tcfc block.
75945 … 0xfd0d60UL //Access:R DataWidth:0x1 // Async fifo empty in sdm_async block.
75946 … 0xfd0d64UL //Access:R DataWidth:0x1 // PRM FIFO empty in sdm_prm_if block.
75954 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
75958 … 0xfd2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75960 … 0xfd2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
75962 … 0xfd2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
75964 … 0xfd2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
75966 … 0xfd3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
75968 … 0xfd3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
75970 … 0xfd3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
75972 … 0xfd3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
75974 … 0xfd4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
75982 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
75986 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
76026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76027 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76029 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76031 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76033 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76035 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76037 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76039 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76041 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76042 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76043 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76044 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76045 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76046 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76047 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76048 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76049 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76050 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76051 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76052 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76053 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76054 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76055 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76056 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76057 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76058 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76059 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76060 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76061 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76062 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76063 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76064 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76065 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76066 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76067 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76068 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76069 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76070 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76071 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76073 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76074 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76262 … (0x1<<19) // In-process Table overfl…
76364 … (0x1<<19) // In-process Table overfl…
76415 …L (0x1<<19) // In-process Table overfl…
76428 …0x1<<0) // QM Active State Counter underrun interrupt in case of message processing. Can happen in…
76430 …0x1<<1) // QM Active State Counter overflow interrupt in case of message processing. Can happen in…
76432 … (0x1<<2) // QM Active State Counter underrun interrupt in case of External load. Can happen in c…
76434 … (0x1<<3) // QM Active State Counter overflow interrupt in case of External load. Can happen in c…
76436 … (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen in cas…
76438 … (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen in cas…
76440 … (0x1<<6) // QM Active State Counter underrun interrupt in case of drop. Can happen in case o…
76442 … (0x1<<7) // Access to illegal PQ number in QM Active State Coun…
76462 …0x1<<0) // QM Active State Counter underrun interrupt in case of message processing. Can happen in…
76464 …0x1<<1) // QM Active State Counter overflow interrupt in case of message processing. Can happen in…
76466 … (0x1<<2) // QM Active State Counter underrun interrupt in case of External load. Can happen in c…
76468 … (0x1<<3) // QM Active State Counter overflow interrupt in case of External load. Can happen in c…
76470 … (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen in cas…
76472 … (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen in cas…
76474 … (0x1<<6) // QM Active State Counter underrun interrupt in case of drop. Can happen in case o…
76476 … (0x1<<7) // Access to illegal PQ number in QM Active State Coun…
76479 …0x1<<0) // QM Active State Counter underrun interrupt in case of message processing. Can happen in…
76481 …0x1<<1) // QM Active State Counter overflow interrupt in case of message processing. Can happen in…
76483 … (0x1<<2) // QM Active State Counter underrun interrupt in case of External load. Can happen in c…
76485 … (0x1<<3) // QM Active State Counter overflow interrupt in case of External load. Can happen in c…
76487 … (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen in cas…
76489 … (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen in cas…
76491 … (0x1<<6) // QM Active State Counter underrun interrupt in case of drop. Can happen in case o…
76493 … (0x1<<7) // Access to illegal PQ number in QM Active State Coun…
76670 … (0x1<<0) // Enable ECC for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_ms…
76672 … (0x1<<0) // Enable ECC for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_ms…
76674 …x1<<1) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_0 in module xcm_mem_agg_c…
76676 …x1<<2) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_1 in module xcm_mem_agg_c…
76678 …x1<<3) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_2 in module xcm_mem_agg_c…
76680 …x1<<4) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_3 in module xcm_mem_agg_c…
76682 …x1<<5) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_8_9.i_ecc_0 in module xcm_mem_agg_c…
76684 …x1<<6) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_8_9.i_ecc_1 in module xcm_mem_agg_c…
76686 …x1<<6) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_co…
76688 … (0x1<<7) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx.i_ecc_0 in module xcm_mem_sm_co…
76690 …x1<<7) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_co…
76692 … (0x1<<8) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx.i_ecc_1 in module xcm_mem_sm_co…
76694 … (0x1<<0) // Enable ECC for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_ms…
76696 … (0x1<<5) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_c…
76698 … (0x1<<8) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_co…
76700 …x1<<6) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_co…
76702 …x1<<7) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_co…
76704 … (0x1<<8) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_co…
76707 …(0x1<<0) // Set parity only for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_ms…
76709 …(0x1<<0) // Set parity only for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_ms…
76711 …) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_0 in module xcm_mem_agg_c…
76713 …) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_1 in module xcm_mem_agg_c…
76715 …) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_2 in module xcm_mem_agg_c…
76717 …) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_3 in module xcm_mem_agg_c…
76719 …) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_8_9.i_ecc_0 in module xcm_mem_agg_c…
76721 …) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_8_9.i_ecc_1 in module xcm_mem_agg_c…
76723 …) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_co…
76725 …x1<<7) // Set parity only for memory ecc instance xcm.i_sm_con_ctx.i_ecc_0 in module xcm_mem_sm_co…
76727 …) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_co…
76729 …x1<<8) // Set parity only for memory ecc instance xcm.i_sm_con_ctx.i_ecc_1 in module xcm_mem_sm_co…
76731 …(0x1<<0) // Set parity only for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_ms…
76733 …1<<5) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_c…
76735 …1<<8) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_co…
76737 …) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_co…
76739 …) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_co…
76741 …1<<8) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_co…
76744 …a correctable error occurred on memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_ms…
76746 …a correctable error occurred on memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_ms…
76748 …ctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_0 in module xcm_mem_agg_c…
76750 …ctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_1 in module xcm_mem_agg_c…
76752 …ctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_2 in module xcm_mem_agg_c…
76754 …ctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_3 in module xcm_mem_agg_c…
76756 …ctable error occurred on memory ecc instance xcm.i_agg_con_ctx_8_9.i_ecc_0 in module xcm_mem_agg_c…
76758 …ctable error occurred on memory ecc instance xcm.i_agg_con_ctx_8_9.i_ecc_1 in module xcm_mem_agg_c…
76760 …ctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_co…
76762 …correctable error occurred on memory ecc instance xcm.i_sm_con_ctx.i_ecc_0 in module xcm_mem_sm_co…
76764 …ctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_co…
76766 …correctable error occurred on memory ecc instance xcm.i_sm_con_ctx.i_ecc_1 in module xcm_mem_sm_co…
76768 …a correctable error occurred on memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_ms…
76770 …orrectable error occurred on memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_c…
76772 …orrectable error occurred on memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_co…
76774 …ctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_co…
76776 …ctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_co…
76778 …orrectable error occurred on memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_co…
76781 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
76782 … 0x10004c4UL //Access:RW DataWidth:0x8 // The Event ID in case one of errors is set in QM in…
76783 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76784 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76785 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76786 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76787 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76788 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76789 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76790 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76791 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76792 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76793 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76794 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76795 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76796 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76797 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76798 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76799 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76800 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76801 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76802 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76803 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76804 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76805 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76806 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76807 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76808 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76810 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76812 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76814 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76816 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76817 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76818 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76819 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76820 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76821 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76822 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76823 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76824 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76825 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76826 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76827 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76828 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76829 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76830 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76831 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76832 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76833 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76834 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76835 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76836 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
76837 …04UL //Access:RW DataWidth:0x3 // The weight of the local Storm input in the Input Arbiter WR…
76838 …0x1000608UL //Access:RW DataWidth:0x3 // The weight of the input Msem in the Input Arbiter WR…
76839 …0x100060cUL //Access:RW DataWidth:0x3 // The weight of the input Usem in the Input Arbiter WR…
76840 …0x1000614UL //Access:RW DataWidth:0x3 // The weight of the input Dorq in the Input Arbiter WR…
76841 … 0x1000618UL //Access:RW DataWidth:0x3 // The weight of the input Pbf in the Input Arbiter WR…
76842 … 0x100061cUL //Access:RW DataWidth:0x3 // The weight of the GRC input in the Input Arbiter WR…
76843 …0x1000624UL //Access:RW DataWidth:0x3 // The weight of the XSDM input in the Input Arbiter WR…
76844 …0x1000628UL //Access:RW DataWidth:0x3 // The weight of the YSDM input in the Input Arbiter WR…
76845 …0x100062cUL //Access:RW DataWidth:0x3 // The weight of the input USDM in the Input Arbiter WR…
76846 …0UL //Access:RW DataWidth:0x3 // The weight of the QM (primary) input in the Input Arbiter WR…
76847 …L //Access:RW DataWidth:0x3 // The weight of the QM (secondary) input in the Input Arbiter WR…
76848 …1000638UL //Access:RW DataWidth:0x3 // The weight of the Timers input in the Input Arbiter WR…
76849 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76850 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76851 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76852 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76853 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76854 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76855 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
76856 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76857 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76858 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76859 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76860 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76861 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76862 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76863 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76864 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76865 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76866 …680UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable erro…
76868 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
76869 …s:R DataWidth:0x3 // Input Arbiter Aggregation Connection part FIFO fill level (in messages).
76870 …/Access:R DataWidth:0x3 // Input Arbiter Storm Connection part FIFO fill level (in messages).
76871 …4UL //Access:R DataWidth:0x3 // Input Arbiter Transparent part FIFO fill level (in messages).
76872 …1000698UL //Access:R DataWidth:0x2 // External read buffer FIFO fill level (in FIFO entries).
76873 …Width:0x7 // The maximum number of Xx RAM messages; which may be stored in XX protection. Is re…
76874 …/Access:RW DataWidth:0x2 // The size of Xx protected message in Xx Messages RAM in QREGs. Upp…
76875 …070cUL //Access:RW DataWidth:0x7 // The maximum number of connections in the XX protection LC…
76877 …en unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.
76879 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
76880 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
76881 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
76882 …ataWidth:0x7 // Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global ena…
76883 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
76888 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76889 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76890 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76891 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
76892 …UL //Access:RW DataWidth:0x7 // Xx free messages threshold high. Used in Xx Bypass global ena…
76893 …54UL //Access:RW DataWidth:0x7 // Xx free messages threshold low Used in Xx Bypass global ena…
76894 …1000758UL //Access:R DataWidth:0x4 // Xx Connection Bypass Table fill level (in connections).
76898 …8UL //Access:R DataWidth:0x3 // Xx LCID Arbiter direct prefetch FIFO fill level (in entries).
76899 …s:R DataWidth:0x3 // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries).
76900 …0UL //Access:R DataWidth:0x3 // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries).
76901 …taWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
76902 … 0x1000798UL //Access:RW DataWidth:0x2 // Affinity type in case of input messag…
76903 … 0x100079cUL //Access:RW DataWidth:0x1 // Exclusive type in case of input messag…
76904 … 0x10007a0UL //Access:RW DataWidth:0x3 // Source affinity in case of input messag…
76905 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76906 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76907 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76908 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76909 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76910 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76911 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76912 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76913 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76914 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76915 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76916 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76917 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76918 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76919 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76920 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76921 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76922 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76923 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76924 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76925 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76926 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76927 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76928 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
76931 …82cUL //Access:R DataWidth:0x4 // Aggregation Connection FIC buffer fill level (in messages).
76932 …0x1000830UL //Access:R DataWidth:0x5 // Storm Connection FIC buffer fill level (in messages).
76933 …/Access:RW DataWidth:0x2 // Aggregation Connection FIC buffer credit (in full message out par…
76934 …38UL //Access:RW DataWidth:0x2 // Storm Connection FIC buffer credit (in full message out par…
76935 … group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than…
76936 …re group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than A…
76937 …torm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTER…
76938 …dth:0x2 // Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTER…
76939 …DataWidth:0x2 // Storm Connection command buffer credit (Direct group). In sum with CM_REGISTER…
76941 …ccess:RW DataWidth:0x3 // The size of AGG Connection context region 0 in REGQ. Is used to det…
76942 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
76943 … 0x1000904UL //Access:RW DataWidth:0xa // [9]: PQ Type (0-Other PQ; 1-TX PQ); if bit[…
76944 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST…
76945 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_…
76946 … 0x1000a0cUL //Access:R DataWidth:0x4 // In-process Table fill level (in messa…
76947 … 0x1000a10UL //Access:R DataWidth:0x1 // In-process Table almost…
76952 …:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM ou…
76969 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
76970 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
76971 …th:0x5 // QM output initial credit (XCM TX queues). Max credit available - 16.Write writes the …
76972 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
76973 … 0x1000a94UL //Access:RW DataWidth:0x5 // FIC output initial credit in REGQ pairs. Write wr…
76994 …1000b00UL //Access:R DataWidth:0x4 // Number of QREGs (128b) of data in QM Primary Input Sta…
76995 …1000b04UL //Access:R DataWidth:0x4 // Number of QREGs (128b) of data in QM Secondary Input S…
76996 … 0x1000b08UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in TM Input Stage.
76997 …UL //Access:R DataWidth:0x6 // Number of entries (2 QREGs each) of data in STORM Input Stage.
76998 … 0x1000b14UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in XSDM Input Stage.
76999 … 0x1000b18UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in YSDM Input Stage.
77000 … 0x1000b1cUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in USDM Input Stage.
77001 …cess:R DataWidth:0x4 // Number of QREGs (128b) in TCM, YCM or 2 QREGs (256b) in XCM of data …
77002 … 0x1000b24UL //Access:R DataWidth:0x4 // Number of QREGs (128b) of data in USEM Input Stage.
77003 … 0x1000b2cUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in DORQ Input Stage.
77004 … 0x1000b30UL //Access:R DataWidth:0x4 // Number of QREGs (128b) of data in PBF Input Stage.
77008 …tive counter overflow/uder-run. Is reset on read. [0] - If set, there was under-run; [1] - If set,…
77025 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
77028 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
77030 …ess:R DataWidth:0x20 // Debug read from XSEM Input stage buffer with 32-bits granularity. Rea…
77032 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
77034 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
77036 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
77038 …ess:R DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Rea…
77040 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
77042 …ss:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (…
77043 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
77044 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
77047 …//Access:R DataWidth:0xa // Debug only. Read only access to LCID CAM in XX protection mechan…
77050 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
77053 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
77079 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77080 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77081 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77082 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77083 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77084 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77085 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77086 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77087 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77088 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77089 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77090 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77091 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77092 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77093 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77094 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77095 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77096 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77097 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77098 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77099 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77100 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77101 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77102 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
77103 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77104 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77105 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77106 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77107 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77108 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77109 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77110 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77111 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77112 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77113 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77114 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77115 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77116 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77117 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77118 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77119 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77120 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77121 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77122 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77123 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77124 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77125 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77126 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
77247 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77248 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77249 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77250 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77251 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77252 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77253 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77254 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77255 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77256 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77257 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77258 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77259 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77260 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77261 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77262 …aWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0…
77263 …0x1000620UL //Access:RW DataWidth:0x3 // The weight of the MSDM input in the Input Arbiter WR…
77264 …0x1001e40UL //Access:RW DataWidth:0x3 // The weight of the input MSDM in the Input Arbiter WR…
77269 … 0x1000b10UL //Access:R DataWidth:0x4 // Number of QREGs (128b) of data in MSDM Input Stage.
77270 … 0x1001e4cUL //Access:R DataWidth:0x4 // Number of QREGs (128b) of data in MSDM Input Stage.
77273 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
77275 …0x1000610UL //Access:RW DataWidth:0x3 // The weight of the input Ysem in the Input Arbiter WR…
77276 …0x1001f00UL //Access:RW DataWidth:0x3 // The weight of the input Ysem in the Input Arbiter WR…
77279 … 0x1000b28UL //Access:R DataWidth:0x4 // Number of QREGs (128b) of data in YSEM Input Stage.
77280 …x4 // Number of QREGs (128b) for TCM, XCM or 2 QREGs (256b) for MCM of data in YSEM Input Stage.
77283 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
77284 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
77286 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
77288 …alue. [28:20] PQ number. [29:29] Reserved. [31:30] Command type: 0 - SET; 1 - DEC; 2 - INC; The ad…
77291 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
77293 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
77333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77334 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
77335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77336 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
77337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77338 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
77492 … (0x1<<14) // In-process Table overfl…
77586 … (0x1<<14) // In-process Table overfl…
77633 …L (0x1<<14) // In-process Table overfl…
77872 … (0x1<<0) // Enable ECC for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_ms…
77874 … (0x1<<1) // Enable ECC for memory ecc instance ycm.i_agg_con_ctx.i_ecc_0 in module ycm_mem_agg_c…
77876 … (0x1<<2) // Enable ECC for memory ecc instance ycm.i_agg_con_ctx.i_ecc_1 in module ycm_mem_agg_c…
77878 … (0x1<<3) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx.i_ecc_0 in module ycm_mem_sm_co…
77880 … (0x1<<4) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx.i_ecc_1 in module ycm_mem_sm_co…
77882 … (0x1<<6) // Enable ECC for memory ecc instance ycm.i_agg_task_ctx.i_ecc_0 in module ycm_mem_agg_t…
77884 …1<<5) // Enable ECC for memory ecc instance ycm.i_agg_task_ctx_0_1.i_ecc_0 in module ycm_mem_agg_t…
77886 … (0x1<<7) // Enable ECC for memory ecc instance ycm.i_agg_task_ctx.i_ecc_1 in module ycm_mem_agg_t…
77888 …1<<6) // Enable ECC for memory ecc instance ycm.i_agg_task_ctx_0_1.i_ecc_1 in module ycm_mem_agg_t…
77890 … (0x1<<7) // Enable ECC for memory ecc instance ycm.i_agg_task_ctx_2.i_ecc in module ycm_mem_agg_t…
77892 … (0x1<<8) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_ta…
77894 … (0x1<<9) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_ta…
77896 … (0x1<<0) // Enable ECC for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_ms…
77898 …0x1<<3) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_co…
77900 …0x1<<4) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_co…
77902 … (0x1<<5) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_co…
77904 … (0x1<<8) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_ta…
77906 … (0x1<<9) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_ta…
77908 … (0x1<<0) // Enable ECC for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_ms…
77910 …0x1<<3) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_co…
77912 …0x1<<4) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_co…
77914 … (0x1<<5) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_co…
77916 … (0x1<<8) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_ta…
77918 … (0x1<<9) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_ta…
77922 …(0x1<<0) // Set parity only for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_ms…
77924 …1<<1) // Set parity only for memory ecc instance ycm.i_agg_con_ctx.i_ecc_0 in module ycm_mem_agg_c…
77926 …1<<2) // Set parity only for memory ecc instance ycm.i_agg_con_ctx.i_ecc_1 in module ycm_mem_agg_c…
77928 …x1<<3) // Set parity only for memory ecc instance ycm.i_sm_con_ctx.i_ecc_0 in module ycm_mem_sm_co…
77930 …x1<<4) // Set parity only for memory ecc instance ycm.i_sm_con_ctx.i_ecc_1 in module ycm_mem_sm_co…
77932 …<<6) // Set parity only for memory ecc instance ycm.i_agg_task_ctx.i_ecc_0 in module ycm_mem_agg_t…
77934 … // Set parity only for memory ecc instance ycm.i_agg_task_ctx_0_1.i_ecc_0 in module ycm_mem_agg_t…
77936 …<<7) // Set parity only for memory ecc instance ycm.i_agg_task_ctx.i_ecc_1 in module ycm_mem_agg_t…
77938 … // Set parity only for memory ecc instance ycm.i_agg_task_ctx_0_1.i_ecc_1 in module ycm_mem_agg_t…
77940 …<<7) // Set parity only for memory ecc instance ycm.i_agg_task_ctx_2.i_ecc in module ycm_mem_agg_t…
77942 …1<<8) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_ta…
77944 …1<<9) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_ta…
77946 …(0x1<<0) // Set parity only for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_ms…
77948 …3) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_co…
77950 …4) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_co…
77952 …x1<<5) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_co…
77954 …1<<8) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_ta…
77956 …1<<9) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_ta…
77958 …(0x1<<0) // Set parity only for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_ms…
77960 …3) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_co…
77962 …4) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_co…
77964 …x1<<5) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_co…
77966 …1<<8) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_ta…
77968 …1<<9) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_ta…
77972 …a correctable error occurred on memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_ms…
77974 …orrectable error occurred on memory ecc instance ycm.i_agg_con_ctx.i_ecc_0 in module ycm_mem_agg_c…
77976 …orrectable error occurred on memory ecc instance ycm.i_agg_con_ctx.i_ecc_1 in module ycm_mem_agg_c…
77978 …correctable error occurred on memory ecc instance ycm.i_sm_con_ctx.i_ecc_0 in module ycm_mem_sm_co…
77980 …correctable error occurred on memory ecc instance ycm.i_sm_con_ctx.i_ecc_1 in module ycm_mem_sm_co…
77982 …rrectable error occurred on memory ecc instance ycm.i_agg_task_ctx.i_ecc_0 in module ycm_mem_agg_t…
77984 …table error occurred on memory ecc instance ycm.i_agg_task_ctx_0_1.i_ecc_0 in module ycm_mem_agg_t…
77986 …rrectable error occurred on memory ecc instance ycm.i_agg_task_ctx.i_ecc_1 in module ycm_mem_agg_t…
77988 …table error occurred on memory ecc instance ycm.i_agg_task_ctx_0_1.i_ecc_1 in module ycm_mem_agg_t…
77990 …rrectable error occurred on memory ecc instance ycm.i_agg_task_ctx_2.i_ecc in module ycm_mem_agg_t…
77992 …orrectable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_ta…
77994 …orrectable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_ta…
77996 …a correctable error occurred on memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_ms…
77998 …ectable error occurred on memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_co…
78000 …ectable error occurred on memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_co…
78002 …correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_co…
78004 …orrectable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_ta…
78006 …orrectable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_ta…
78008 …a correctable error occurred on memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_ms…
78010 …ectable error occurred on memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_co…
78012 …ectable error occurred on memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_co…
78014 …correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_co…
78016 …orrectable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_ta…
78018 …orrectable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_ta…
78022 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
78031 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
78032 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
78033 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
78034 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
78035 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
78036 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
78037 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
78038 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
78063 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
78064 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
78065 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
78066 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
78067 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
78068 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
78069 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
78071 … 0x1080564UL //Access:RW DataWidth:0x8 // The Event ID in case one of errors is set in QM in…
78072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78073 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
78074 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78075 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
78076 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78077 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
78078 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78079 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
78080 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78081 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
78082 …04UL //Access:RW DataWidth:0x3 // The weight of the local Storm input in the Input Arbiter WR…
78083 …0x1080608UL //Access:RW DataWidth:0x3 // The weight of the input Msem in the Input Arbiter WR…
78084 …0x108060cUL //Access:RW DataWidth:0x3 // The weight of the input Usem in the Input Arbiter WR…
78085 … 0x1080610UL //Access:RW DataWidth:0x3 // The weight of the input Pbf in the Input Arbiter WR…
78086 … 0x1080614UL //Access:RW DataWidth:0x3 // The weight of the GRC input in the Input Arbiter WR…
78087 …0x108061cUL //Access:RW DataWidth:0x3 // The weight of the YSDM input in the Input Arbiter WR…
78088 …0x1080620UL //Access:RW DataWidth:0x3 // The weight of the input XYLD in the Input Arbiter WR…
78089 …4UL //Access:RW DataWidth:0x3 // The weight of the QM (primary) input in the Input Arbiter WR…
78090 …L //Access:RW DataWidth:0x3 // The weight of the QM (secondary) input in the Input Arbiter WR…
78091 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78092 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78093 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78094 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78095 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78096 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78097 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
78098 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78099 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78100 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78101 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78102 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78103 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78104 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78105 …664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable erro…
78107 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78108 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78109 …s:R DataWidth:0x3 // Input Arbiter Aggregation Connection part FIFO fill level (in messages).
78110 …/Access:R DataWidth:0x3 // Input Arbiter Storm Connection part FIFO fill level (in messages).
78111 …/Access:R DataWidth:0x3 // Input Arbiter Aggregation Task part FIFO fill level (in messages).
78112 …80UL //Access:R DataWidth:0x3 // Input Arbiter Storm Task part FIFO fill level (in messages).
78113 …4UL //Access:R DataWidth:0x3 // Input Arbiter Transparent part FIFO fill level (in messages).
78114 …1080688UL //Access:R DataWidth:0x2 // External read buffer FIFO fill level (in FIFO entries).
78115 …Width:0x7 // The maximum number of Xx RAM messages; which may be stored in XX protection. Is re…
78116 …/Access:RW DataWidth:0x6 // The size of Xx protected message in Xx Messages RAM in QREGs. Upp…
78117 …070cUL //Access:RW DataWidth:0x7 // The maximum number of connections in the XX protection LC…
78119 …en unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.
78121 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
78122 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
78123 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
78124 …ataWidth:0x7 // Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global ena…
78125 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
78130 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78131 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78132 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78133 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
78134 …UL //Access:RW DataWidth:0x7 // Xx free messages threshold high. Used in Xx Bypass global ena…
78135 …54UL //Access:RW DataWidth:0x7 // Xx free messages threshold low Used in Xx Bypass global ena…
78136 …1080758UL //Access:R DataWidth:0x4 // Xx Connection Bypass Table fill level (in connections).
78139 … 0x1080764UL //Access:R DataWidth:0x7 // Xx Task Bypass Table fill level (in tasks).
78143 …4UL //Access:R DataWidth:0x6 // Xx LCID Arbiter direct prefetch FIFO fill level (in entries).
78144 …s:R DataWidth:0x6 // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries).
78145 …cUL //Access:R DataWidth:0x6 // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries).
78146 …taWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
78147 … 0x10807a4UL //Access:RW DataWidth:0x2 // Affinity type in case of input messag…
78148 … 0x10807a8UL //Access:RW DataWidth:0x1 // Exclusive type in case of input messag…
78149 … 0x10807acUL //Access:RW DataWidth:0x3 // Source affinity in case of input messag…
78150 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78151 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78152 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78153 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78154 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78155 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78156 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78157 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78158 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78159 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78160 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78161 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78162 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78163 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78164 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78165 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78166 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78167 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78168 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78169 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78170 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78171 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78172 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78173 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
78178 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
78179 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
78180 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
78181 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
78182 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
78183 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
78184 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
78185 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
78186 …854UL //Access:R DataWidth:0x2 // Aggregation Connection FIC buffer fill level (in messages).
78187 …0x1080858UL //Access:R DataWidth:0x4 // Storm Connection FIC buffer fill level (in messages).
78188 …/Access:RW DataWidth:0x2 // Aggregation Connection FIC buffer credit (in full message out par…
78189 …60UL //Access:RW DataWidth:0x2 // Storm Connection FIC buffer credit (in full message out par…
78190 … group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than…
78191 …re group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than A…
78192 …torm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTER…
78193 …dth:0x2 // Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTER…
78194 …DataWidth:0x2 // Storm Connection command buffer credit (Direct group). In sum with CM_REGISTER…
78195 …0x1080878UL //Access:R DataWidth:0x2 // Aggregation Task FIC buffer fill level (in messages).
78196 … 0x108087cUL //Access:R DataWidth:0x5 // Storm Task FIC buffer fill level (in messages).
78197 …80UL //Access:RW DataWidth:0x2 // Aggregation Task FIC buffer credit (in full message out par…
78198 …x1080884UL //Access:RW DataWidth:0x2 // Storm Task FIC buffer credit (in full message out par…
78199 …on group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more …
78200 …tore group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG need be no more th…
78201 … // Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTER…
78202 …DataWidth:0x2 // Aggregation Task command buffer credit (Direct group). In sum with CM_REGISTER…
78203 …:RW DataWidth:0x2 // Storm Task command buffer credit (Direct group). In sum with CM_REGISTER…
78205 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
78206 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
78207 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
78208 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
78209 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
78210 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
78211 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
78212 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
78213 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
78214 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
78219 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78220 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78221 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78222 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78223 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78224 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78225 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78226 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78227 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78228 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78229 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78230 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78231 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78232 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78233 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78242 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST…
78243 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_…
78244 … 0x1080a0cUL //Access:R DataWidth:0x4 // In-process Table fill level (in messa…
78245 … 0x1080a10UL //Access:R DataWidth:0x1 // In-process Table almost…
78251 …:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM ou…
78252 …Access:RW DataWidth:0x1 // If set, Xx task bypass state will be added in calculation of CM ou…
78269 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
78270 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
78271 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
78272 …1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the i…
78273 …th:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the i…
78274 … 0x1080a98UL //Access:RW DataWidth:0x5 // FIC output initial credit in REGQ pairs. Write wr…
78290 …1080ae8UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in QM Primary Input Sta…
78291 …1080aecUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in QM Secondary Input S…
78292 …UL //Access:R DataWidth:0x5 // Number of entries (2 QREGs each) of data in STORM Input Stage.
78293 … 0x1080af8UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in YSDM Input Stage.
78294 … 0x1080afcUL //Access:R DataWidth:0x5 // Number of QREGs (128b) of data in XYLD Input Stage.
78295 …cess:R DataWidth:0x4 // Number of QREGs (128b) in TCM, YCM or 2 QREGs (256b) in XCM of data …
78296 … 0x1080b04UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in USEM Input Stage.
78297 … 0x1080b08UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in PBF Input Stage.
78312 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
78314 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
78316 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
78318 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
78320 …ss:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (…
78321 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
78322 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
78323 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
78324 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
78330 …//Access:R DataWidth:0xa // Debug only. Read only access to LCID CAM in XX protection mechan…
78333 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
78336 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
78338 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78339 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78340 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78341 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78342 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78343 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78344 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78345 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78346 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78347 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78348 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78349 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78350 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78351 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78352 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78353 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78354 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78355 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78356 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78357 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78358 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78359 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78360 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78361 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
78362 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78363 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78364 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78365 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78366 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78367 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78368 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78369 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78370 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78371 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78372 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78373 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78374 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78375 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78376 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78377 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78378 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78379 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78380 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78381 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78382 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78383 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78384 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78385 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
78506 …0x1080618UL //Access:RW DataWidth:0x3 // The weight of the MSDM input in the Input Arbiter WR…
78507 …0x1081ec0UL //Access:RW DataWidth:0x3 // The weight of the input MSDM in the Input Arbiter WR…
78512 … 0x1080af4UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in MSDM Input Stage.
78513 … 0x1081eccUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in MSDM Input Stage.
78516 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
78517 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
78519 …ess:R DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Rea…
78520 …ess:R DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Rea…
78525 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
78526 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
78529 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78535 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
78536 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
78539 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
78541 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
78658 …_K2 (0x1<<10) // In-process Table overfl…
78660 …5 (0x1<<8) // In-process Table overfl…
78764 …_BB_K2 (0x1<<10) // In-process Table overfl…
78766 …L_E5 (0x1<<8) // In-process Table overfl…
78817 …L_BB_K2 (0x1<<10) // In-process Table overfl…
78819 …FL_E5 (0x1<<8) // In-process Table overfl…
78941 … (0x1<<0) // Enable ECC for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_ms…
78943 … (0x1<<1) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_co…
78945 … (0x1<<2) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_co…
78947 … (0x1<<0) // Enable ECC for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_ms…
78949 … (0x1<<1) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_co…
78951 … (0x1<<2) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_co…
78953 … (0x1<<0) // Enable ECC for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_ms…
78955 … (0x1<<1) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_co…
78957 … (0x1<<2) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_co…
78960 …(0x1<<0) // Set parity only for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_ms…
78962 …x1<<1) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_co…
78964 …x1<<2) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_co…
78966 …(0x1<<0) // Set parity only for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_ms…
78968 …x1<<1) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_co…
78970 …x1<<2) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_co…
78972 …(0x1<<0) // Set parity only for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_ms…
78974 …x1<<1) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_co…
78976 …x1<<2) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_co…
78979 …a correctable error occurred on memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_ms…
78981 …correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_co…
78983 …correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_co…
78985 …a correctable error occurred on memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_ms…
78987 …correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_co…
78989 …correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_co…
78991 …a correctable error occurred on memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_ms…
78993 …correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_co…
78995 …correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_co…
78998 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
78999 … 0x1100404UL //Access:RW DataWidth:0x8 // The Event ID in case one of errors is set in QM in…
79000 …04UL //Access:RW DataWidth:0x3 // The weight of the local Storm input in the Input Arbiter WR…
79001 … 0x1100608UL //Access:RW DataWidth:0x3 // The weight of the input Pbf in the Input Arbiter WR…
79002 … 0x110060cUL //Access:RW DataWidth:0x3 // The weight of the GRC input in the Input Arbiter WR…
79003 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79004 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79005 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79006 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79007 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79008 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79009 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
79010 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79011 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79012 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79013 …63cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable erro…
79015 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
79016 …/Access:R DataWidth:0x3 // Input Arbiter Storm Connection part FIFO fill level (in messages).
79017 …cUL //Access:R DataWidth:0x3 // Input Arbiter Transparent part FIFO fill level (in messages).
79018 …1100650UL //Access:R DataWidth:0x2 // External read buffer FIFO fill level (in FIFO entries).
79019 …Width:0x3 // The maximum number of Xx RAM messages; which may be stored in XX protection. Is re…
79020 …/Access:RW DataWidth:0x6 // The size of Xx protected message in Xx Messages RAM in QREGs. Upp…
79021 …070cUL //Access:RW DataWidth:0x2 // The maximum number of connections in the XX protection LC…
79023 …en unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.
79025 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
79026 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
79027 … DataWidth:0x2 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
79028 …ataWidth:0x2 // Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global ena…
79029 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
79034 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79035 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79036 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79037 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
79038 …UL //Access:RW DataWidth:0x3 // Xx free messages threshold high. Used in Xx Bypass global ena…
79039 …54UL //Access:RW DataWidth:0x3 // Xx free messages threshold low Used in Xx Bypass global ena…
79040 …8UL //Access:R DataWidth:0x6 // Xx LCID Arbiter direct prefetch FIFO fill level (in entries).
79041 …s:R DataWidth:0x6 // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries).
79042 …taWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
79043 … 0x1100764UL //Access:RW DataWidth:0x2 // Affinity type in case of input messag…
79044 … 0x1100768UL //Access:RW DataWidth:0x1 // Exclusive type in case of input messag…
79045 … 0x110076cUL //Access:RW DataWidth:0x3 // Source affinity in case of input messag…
79047 …0x1100828UL //Access:R DataWidth:0x5 // Storm Connection FIC buffer fill level (in messages).
79048 …2cUL //Access:RW DataWidth:0x2 // Storm Connection FIC buffer credit (in full message out par…
79049 …torm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTER…
79050 …DataWidth:0x2 // Storm Connection command buffer credit (Direct group). In sum with CM_REGISTER…
79052 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
79053 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST…
79054 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_…
79055 … 0x1100a0cUL //Access:R DataWidth:0x4 // In-process Table fill level (in messa…
79056 … 0x1100a10UL //Access:R DataWidth:0x1 // In-process Table almost…
79059 …:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM ou…
79060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
79061 … 0x1100a88UL //Access:RW DataWidth:0x5 // FIC output initial credit in REGQ pairs. Write wr…
79069 …UL //Access:R DataWidth:0x4 // Number of entries (2 QREGs each) of data in STORM Input Stage.
79070 … 0x1100ad0UL //Access:R DataWidth:0x6 // Number of QREGs (128b) of data in PBF Input Stage.
79076 …ess:R DataWidth:0x20 // Debug read from PSEM Input stage buffer with 32-bits granularity. Rea…
79079 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
79081 …ss:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (…
79082 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
79083 …//Access:R DataWidth:0xa // Debug only. Read only access to LCID CAM in XX protection mechan…
79085 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
79087 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
79089 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79090 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79091 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79092 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79093 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79094 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79095 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79096 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79097 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79098 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79099 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79100 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79101 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79102 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79103 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79104 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79105 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79106 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79107 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79108 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79109 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79110 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79111 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79112 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
79113 …0x1100610UL //Access:RW DataWidth:0x3 // The weight of the input PSDM in the Input Arbiter WR…
79114 …0x1101750UL //Access:RW DataWidth:0x3 // The weight of the input PSDM in the Input Arbiter WR…
79119 … 0x1100accUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in PSDM Input Stage.
79120 … 0x110175cUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in PSDM Input Stage.
79123 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
79124 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
79126 …0x11017c0UL //Access:RW DataWidth:0x3 // The weight of the input YPLD in the Input Arbiter WR…
79129 … 0x11017ccUL //Access:R DataWidth:0x5 // Number of QREGs (128b) of data in YPLD Input Stage.
79131 …ess:R DataWidth:0x20 // Debug read from YPLD Input stage buffer with 32-bits granularity. Rea…
79133 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
79135 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
79137 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
79177 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79178 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
79179 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79180 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
79181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79182 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
79183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79184 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
79185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79186 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
79187 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79188 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
79189 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79190 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
79191 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79192 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
79193 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79194 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
79195 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79196 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
79197 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79198 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
79199 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
79399 … (0x1<<21) // In-process Table overfl…
79537 … (0x1<<21) // In-process Table overfl…
79606 …L (0x1<<21) // In-process Table overfl…
79847 … (0x1<<0) // Enable ECC for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_ms…
79849 …x1<<1) // Enable ECC for memory ecc instance tcm.i_agg_con_ctx_0_3.i_ecc_0 in module tcm_mem_agg_c…
79851 …x1<<2) // Enable ECC for memory ecc instance tcm.i_agg_con_ctx_0_3.i_ecc_1 in module tcm_mem_agg_c…
79853 … (0x1<<3) // Enable ECC for memory ecc instance tcm.i_agg_con_ctx_4.i_ecc in module tcm_mem_agg_c…
79855 … (0x1<<4) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_co…
79857 … (0x1<<5) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_co…
79859 … (0x1<<6) // Enable ECC for memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_t…
79861 … (0x1<<7) // Enable ECC for memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_t…
79863 … (0x1<<8) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_ta…
79865 … (0x1<<9) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_ta…
79867 … (0x1<<0) // Enable ECC for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_ms…
79869 … (0x1<<3) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_co…
79871 … (0x1<<4) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_co…
79873 … (0x1<<5) // Enable ECC for memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_t…
79875 … (0x1<<6) // Enable ECC for memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_t…
79877 … (0x1<<7) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_ta…
79879 … (0x1<<8) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_ta…
79881 … (0x1<<0) // Enable ECC for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_ms…
79883 … (0x1<<3) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_co…
79885 … (0x1<<4) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_co…
79887 … (0x1<<7) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_ta…
79889 … (0x1<<8) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_ta…
79892 …(0x1<<0) // Set parity only for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_ms…
79894 …) // Set parity only for memory ecc instance tcm.i_agg_con_ctx_0_3.i_ecc_0 in module tcm_mem_agg_c…
79896 …) // Set parity only for memory ecc instance tcm.i_agg_con_ctx_0_3.i_ecc_1 in module tcm_mem_agg_c…
79898 …1<<3) // Set parity only for memory ecc instance tcm.i_agg_con_ctx_4.i_ecc in module tcm_mem_agg_c…
79900 …x1<<4) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_co…
79902 …x1<<5) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_co…
79904 …<<6) // Set parity only for memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_t…
79906 …<<7) // Set parity only for memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_t…
79908 …1<<8) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_ta…
79910 …1<<9) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_ta…
79912 …(0x1<<0) // Set parity only for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_ms…
79914 …x1<<3) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_co…
79916 …x1<<4) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_co…
79918 …<<5) // Set parity only for memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_t…
79920 …<<6) // Set parity only for memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_t…
79922 …1<<7) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_ta…
79924 …1<<8) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_ta…
79926 …(0x1<<0) // Set parity only for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_ms…
79928 …x1<<3) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_co…
79930 …x1<<4) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_co…
79932 …1<<7) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_ta…
79934 …1<<8) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_ta…
79937 …a correctable error occurred on memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_ms…
79939 …ctable error occurred on memory ecc instance tcm.i_agg_con_ctx_0_3.i_ecc_0 in module tcm_mem_agg_c…
79941 …ctable error occurred on memory ecc instance tcm.i_agg_con_ctx_0_3.i_ecc_1 in module tcm_mem_agg_c…
79943 …orrectable error occurred on memory ecc instance tcm.i_agg_con_ctx_4.i_ecc in module tcm_mem_agg_c…
79945 …correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_co…
79947 …correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_co…
79949 …rrectable error occurred on memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_t…
79951 …rrectable error occurred on memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_t…
79953 …orrectable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_ta…
79955 …orrectable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_ta…
79957 …a correctable error occurred on memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_ms…
79959 …correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_co…
79961 …correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_co…
79963 …rrectable error occurred on memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_t…
79965 …rrectable error occurred on memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_t…
79967 …orrectable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_ta…
79969 …orrectable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_ta…
79971 …a correctable error occurred on memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_ms…
79973 …correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_co…
79975 …correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_co…
79977 …orrectable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_ta…
79979 …orrectable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_ta…
79982 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
79991 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
79992 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
79993 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
79994 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
79995 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
79996 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
79997 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
79998 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
80007 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
80008 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
80009 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
80010 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
80011 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
80012 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
80013 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
80023 … 0x1180564UL //Access:RW DataWidth:0x8 // The Event ID in case one of errors is set in QM in…
80024 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80025 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80027 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80029 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80031 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80033 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80035 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80037 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80039 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80041 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80042 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80043 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80044 …04UL //Access:RW DataWidth:0x3 // The weight of the local Storm input in the Input Arbiter WR…
80045 …0x1180608UL //Access:RW DataWidth:0x3 // The weight of the input Msem in the Input Arbiter WR…
80046 …0x1180610UL //Access:RW DataWidth:0x3 // The weight of the input Dorq in the Input Arbiter WR…
80047 … 0x1180614UL //Access:RW DataWidth:0x3 // The weight of the input Pbf in the Input Arbiter WR…
80048 … 0x1180618UL //Access:RW DataWidth:0x3 // The weight of the input PRS in the Input Arbiter WR…
80049 … 0x118061cUL //Access:RW DataWidth:0x3 // The weight of the GRC input in the Input Arbiter WR…
80050 …4UL //Access:RW DataWidth:0x3 // The weight of the QM (primary) input in the Input Arbiter WR…
80051 …L //Access:RW DataWidth:0x3 // The weight of the QM (secondary) input in the Input Arbiter WR…
80052 …118062cUL //Access:RW DataWidth:0x3 // The weight of the Timers input in the Input Arbiter WR…
80053 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80054 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80055 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80056 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80057 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80058 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80059 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
80060 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80061 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80062 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80063 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80064 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80065 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80066 …664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable erro…
80068 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80069 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80070 …s:R DataWidth:0x3 // Input Arbiter Aggregation Connection part FIFO fill level (in messages).
80071 …/Access:R DataWidth:0x3 // Input Arbiter Storm Connection part FIFO fill level (in messages).
80072 …/Access:R DataWidth:0x3 // Input Arbiter Aggregation Task part FIFO fill level (in messages).
80073 …80UL //Access:R DataWidth:0x3 // Input Arbiter Storm Task part FIFO fill level (in messages).
80074 …4UL //Access:R DataWidth:0x3 // Input Arbiter Transparent part FIFO fill level (in messages).
80075 …1180688UL //Access:R DataWidth:0x2 // External read buffer FIFO fill level (in FIFO entries).
80076 …Width:0x7 // The maximum number of Xx RAM messages; which may be stored in XX protection. Is re…
80077 …/Access:RW DataWidth:0x5 // The size of Xx protected message in Xx Messages RAM in QREGs. Upp…
80078 …070cUL //Access:RW DataWidth:0x7 // The maximum number of connections in the XX protection LC…
80080 …en unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.
80082 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
80083 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
80084 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
80085 …ataWidth:0x7 // Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global ena…
80086 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
80091 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80092 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80093 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80094 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
80095 …UL //Access:RW DataWidth:0x7 // Xx free messages threshold high. Used in Xx Bypass global ena…
80096 …54UL //Access:RW DataWidth:0x7 // Xx free messages threshold low Used in Xx Bypass global ena…
80097 …1180758UL //Access:R DataWidth:0x4 // Xx Connection Bypass Table fill level (in connections).
80100 … 0x1180764UL //Access:R DataWidth:0x7 // Xx Task Bypass Table fill level (in tasks).
80104 …4UL //Access:R DataWidth:0x5 // Xx LCID Arbiter direct prefetch FIFO fill level (in entries).
80105 …s:R DataWidth:0x5 // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries).
80106 …cUL //Access:R DataWidth:0x5 // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries).
80107 …taWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
80108 … 0x11807a4UL //Access:RW DataWidth:0x2 // Affinity type in case of input messag…
80109 … 0x11807a8UL //Access:RW DataWidth:0x1 // Exclusive type in case of input messag…
80110 … 0x11807acUL //Access:RW DataWidth:0x3 // Source affinity in case of input messag…
80111 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80112 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80113 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80114 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80115 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80116 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80117 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80118 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80119 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80120 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80121 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80122 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80123 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80124 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80125 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80126 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80127 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80128 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80129 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80130 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80131 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80132 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80133 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80134 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
80139 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
80140 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
80141 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
80142 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
80143 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
80144 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
80145 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
80146 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
80147 …854UL //Access:R DataWidth:0x3 // Aggregation Connection FIC buffer fill level (in messages).
80148 …0x1180858UL //Access:R DataWidth:0x5 // Storm Connection FIC buffer fill level (in messages).
80149 …/Access:RW DataWidth:0x2 // Aggregation Connection FIC buffer credit (in full message out par…
80150 …60UL //Access:RW DataWidth:0x2 // Storm Connection FIC buffer credit (in full message out par…
80151 … group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than…
80152 …re group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than A…
80153 …torm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTER…
80154 …dth:0x2 // Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTER…
80155 …DataWidth:0x2 // Storm Connection command buffer credit (Direct group). In sum with CM_REGISTER…
80156 …0x1180878UL //Access:R DataWidth:0x2 // Aggregation Task FIC buffer fill level (in messages).
80157 … 0x118087cUL //Access:R DataWidth:0x4 // Storm Task FIC buffer fill level (in messages).
80158 …80UL //Access:RW DataWidth:0x2 // Aggregation Task FIC buffer credit (in full message out par…
80159 …x1180884UL //Access:RW DataWidth:0x2 // Storm Task FIC buffer credit (in full message out par…
80160 …on group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more …
80161 …tore group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG need be no more th…
80162 … // Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTER…
80163 …DataWidth:0x2 // Aggregation Task command buffer credit (Direct group). In sum with CM_REGISTER…
80164 …:RW DataWidth:0x2 // Storm Task command buffer credit (Direct group). In sum with CM_REGISTER…
80166 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
80167 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
80168 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
80169 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
80170 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
80171 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
80172 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
80173 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
80174 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
80175 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
80180 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80182 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80184 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80194 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST…
80195 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_…
80196 … 0x1180a0cUL //Access:R DataWidth:0x4 // In-process Table fill level (in messa…
80197 … 0x1180a10UL //Access:R DataWidth:0x1 // In-process Table almost…
80205 …:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM ou…
80206 …Access:RW DataWidth:0x1 // If set, Xx task bypass state will be added in calculation of CM ou…
80223 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
80224 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
80225 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
80226 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
80227 … 0x1180a94UL //Access:RW DataWidth:0x5 // FIC output initial credit in REGQ pairs. Write wr…
80243 …1180aecUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in QM Primary Input Sta…
80244 …1180af0UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in QM Secondary Input S…
80245 … 0x1180af4UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in TM Input Stage.
80246 …UL //Access:R DataWidth:0x5 // Number of entries (2 QREGs each) of data in STORM Input Stage.
80247 …cess:R DataWidth:0x3 // Number of QREGs (128b) in TCM, YCM or 2 QREGs (256b) in XCM of data …
80248 … 0x1180b08UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in DORQ Input Stage.
80249 … 0x1180b0cUL //Access:R DataWidth:0x4 // Number of QREGs (128b) of data in PBF Input Stage.
80250 … 0x1180b10UL //Access:R DataWidth:0x4 // Number of QREGs (128b) of data in PRS Input Stage.
80264 …ess:R DataWidth:0x20 // Debug read from TSEM Input stage buffer with 32-bits granularity. Rea…
80267 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
80269 …cess:R DataWidth:0x20 // Debug read from PRS Input stage buffer with 32-bits granularity. Rea…
80271 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
80273 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
80275 …ss:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (…
80276 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
80277 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
80278 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
80279 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
80285 …//Access:R DataWidth:0xa // Debug only. Read only access to LCID CAM in XX protection mechan…
80288 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
80291 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
80317 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80318 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80319 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80320 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80321 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80322 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80323 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80324 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80325 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80326 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80327 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80328 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80329 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80330 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80331 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80332 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80333 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80334 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80335 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80336 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80337 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80338 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80339 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80340 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
80341 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80342 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80343 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80344 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80345 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80346 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80347 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80348 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80349 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80350 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80351 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80352 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80353 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80354 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80355 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80356 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80357 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80358 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80359 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80360 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80361 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80362 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80363 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80364 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
80485 …0x1180620UL //Access:RW DataWidth:0x3 // The weight of the input TSDM in the Input Arbiter WR…
80486 …0x1181b00UL //Access:RW DataWidth:0x3 // The weight of the input TSDM in the Input Arbiter WR…
80491 … 0x1180afcUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in TSDM Input Stage.
80492 … 0x1181b0cUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in TSDM Input Stage.
80495 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
80496 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
80498 …0x1181b80UL //Access:RW DataWidth:0x3 // The weight of the input PSDM in the Input Arbiter WR…
80501 … 0x1181b8cUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in PSDM Input Stage.
80503 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
80505 …0x1181c00UL //Access:RW DataWidth:0x3 // The weight of the input MSDM in the Input Arbiter WR…
80508 … 0x1181c0cUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in MSDM Input Stage.
80510 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
80512 …0x118060cUL //Access:RW DataWidth:0x3 // The weight of the input Ysem in the Input Arbiter WR…
80513 …0x1181c80UL //Access:RW DataWidth:0x3 // The weight of the input Ysem in the Input Arbiter WR…
80516 … 0x1180b04UL //Access:R DataWidth:0x4 // Number of QREGs (128b) of data in YSEM Input Stage.
80517 …x4 // Number of QREGs (128b) for TCM, XCM or 2 QREGs (256b) for MCM of data in YSEM Input Stage.
80520 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
80521 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
80523 …0x1181e00UL //Access:RW DataWidth:0x3 // The weight of the input PTLD in the Input Arbiter WR…
80526 … 0x1181e0cUL //Access:R DataWidth:0x6 // Number of QREGs (128b) of data in PTLD Input Stage.
80528 …ess:R DataWidth:0x20 // Debug read from PTLD Input stage buffer with 32-bits granularity. Rea…
80530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80535 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80536 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80537 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80538 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80539 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80540 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80541 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80542 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80543 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80544 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80545 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80546 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
80549 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
80551 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
80591 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80592 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80593 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80594 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80595 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80596 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
80848 … (0x1<<15) // In-process Table overfl…
80954 … (0x1<<15) // In-process Table overfl…
81007 …L (0x1<<15) // In-process Table overfl…
81190 … (0x1<<0) // Enable ECC for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_ms…
81192 … (0x1<<1) // Enable ECC for memory ecc instance mcm.i_agg_con_ctx.i_ecc in module mcm_mem_agg_c…
81194 … (0x1<<2) // Enable ECC for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_co…
81196 … (0x1<<3) // Enable ECC for memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_co…
81198 …1<<4) // Enable ECC for memory ecc instance mcm.i_agg_task_ctx_0_1.i_ecc_0 in module mcm_mem_agg_t…
81200 …1<<5) // Enable ECC for memory ecc instance mcm.i_agg_task_ctx_0_1.i_ecc_1 in module mcm_mem_agg_t…
81202 … (0x1<<6) // Enable ECC for memory ecc instance mcm.i_agg_task_ctx_2.i_ecc in module mcm_mem_agg_t…
81204 … (0x1<<7) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx.i_ecc_0 in module mcm_mem_sm_ta…
81206 … (0x1<<8) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx.i_ecc_1 in module mcm_mem_sm_ta…
81208 … (0x1<<0) // Enable ECC for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_ms…
81210 … (0x1<<2) // Enable ECC for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_co…
81212 … (0x1<<3) // Enable ECC for memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_co…
81214 …x1<<6) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_0 in module mcm_mem_sm_ta…
81216 …x1<<7) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_1 in module mcm_mem_sm_ta…
81218 … (0x1<<8) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx_6.i_ecc in module mcm_mem_sm_ta…
81221 …(0x1<<0) // Set parity only for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_ms…
81223 …0x1<<1) // Set parity only for memory ecc instance mcm.i_agg_con_ctx.i_ecc in module mcm_mem_agg_c…
81225 …x1<<2) // Set parity only for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_co…
81227 …x1<<3) // Set parity only for memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_co…
81229 … // Set parity only for memory ecc instance mcm.i_agg_task_ctx_0_1.i_ecc_0 in module mcm_mem_agg_t…
81231 … // Set parity only for memory ecc instance mcm.i_agg_task_ctx_0_1.i_ecc_1 in module mcm_mem_agg_t…
81233 …<<6) // Set parity only for memory ecc instance mcm.i_agg_task_ctx_2.i_ecc in module mcm_mem_agg_t…
81235 …1<<7) // Set parity only for memory ecc instance mcm.i_sm_task_ctx.i_ecc_0 in module mcm_mem_sm_ta…
81237 …1<<8) // Set parity only for memory ecc instance mcm.i_sm_task_ctx.i_ecc_1 in module mcm_mem_sm_ta…
81239 …(0x1<<0) // Set parity only for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_ms…
81241 …x1<<2) // Set parity only for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_co…
81243 …x1<<3) // Set parity only for memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_co…
81245 …) // Set parity only for memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_0 in module mcm_mem_sm_ta…
81247 …) // Set parity only for memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_1 in module mcm_mem_sm_ta…
81249 …1<<8) // Set parity only for memory ecc instance mcm.i_sm_task_ctx_6.i_ecc in module mcm_mem_sm_ta…
81252 …a correctable error occurred on memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_ms…
81254 … correctable error occurred on memory ecc instance mcm.i_agg_con_ctx.i_ecc in module mcm_mem_agg_c…
81256 …correctable error occurred on memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_co…
81258 …correctable error occurred on memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_co…
81260 …table error occurred on memory ecc instance mcm.i_agg_task_ctx_0_1.i_ecc_0 in module mcm_mem_agg_t…
81262 …table error occurred on memory ecc instance mcm.i_agg_task_ctx_0_1.i_ecc_1 in module mcm_mem_agg_t…
81264 …rrectable error occurred on memory ecc instance mcm.i_agg_task_ctx_2.i_ecc in module mcm_mem_agg_t…
81266 …orrectable error occurred on memory ecc instance mcm.i_sm_task_ctx.i_ecc_0 in module mcm_mem_sm_ta…
81268 …orrectable error occurred on memory ecc instance mcm.i_sm_task_ctx.i_ecc_1 in module mcm_mem_sm_ta…
81270 …a correctable error occurred on memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_ms…
81272 …correctable error occurred on memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_co…
81274 …correctable error occurred on memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_co…
81276 …ctable error occurred on memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_0 in module mcm_mem_sm_ta…
81278 …ctable error occurred on memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_1 in module mcm_mem_sm_ta…
81280 …orrectable error occurred on memory ecc instance mcm.i_sm_task_ctx_6.i_ecc in module mcm_mem_sm_ta…
81283 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
81292 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
81293 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
81294 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
81295 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
81296 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
81297 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
81298 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
81299 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
81324 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
81325 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
81326 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
81327 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
81328 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
81329 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
81330 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
81332 … 0x1200564UL //Access:RW DataWidth:0x8 // The Event ID in case one of errors is set in QM in…
81333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81334 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
81335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81336 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
81337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81338 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
81339 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81340 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
81341 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81342 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
81343 …04UL //Access:RW DataWidth:0x3 // The weight of the local Storm input in the Input Arbiter WR…
81344 …0x1200608UL //Access:RW DataWidth:0x3 // The weight of the input Usem in the Input Arbiter WR…
81345 … 0x1200610UL //Access:RW DataWidth:0x3 // The weight of the input Pbf in the Input Arbiter WR…
81346 … 0x1200614UL //Access:RW DataWidth:0x3 // The weight of the GRC input in the Input Arbiter WR…
81347 …0x120061cUL //Access:RW DataWidth:0x3 // The weight of the YSDM input in the Input Arbiter WR…
81348 …0x1200620UL //Access:RW DataWidth:0x3 // The weight of the input USDM in the Input Arbiter WR…
81349 …0x1200624UL //Access:RW DataWidth:0x3 // The weight of the input TMLD in the Input Arbiter WR…
81350 …8UL //Access:RW DataWidth:0x3 // The weight of the QM (primary) input in the Input Arbiter WR…
81351 …L //Access:RW DataWidth:0x3 // The weight of the QM (secondary) input in the Input Arbiter WR…
81352 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81353 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81354 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81355 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81356 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81357 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81358 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
81359 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81360 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81361 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81362 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81363 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81364 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81365 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81366 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81367 …66cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable erro…
81369 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81370 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81371 …s:R DataWidth:0x3 // Input Arbiter Aggregation Connection part FIFO fill level (in messages).
81372 …/Access:R DataWidth:0x3 // Input Arbiter Storm Connection part FIFO fill level (in messages).
81373 …/Access:R DataWidth:0x3 // Input Arbiter Aggregation Task part FIFO fill level (in messages).
81374 …88UL //Access:R DataWidth:0x3 // Input Arbiter Storm Task part FIFO fill level (in messages).
81375 …cUL //Access:R DataWidth:0x3 // Input Arbiter Transparent part FIFO fill level (in messages).
81376 …1200690UL //Access:R DataWidth:0x2 // External read buffer FIFO fill level (in FIFO entries).
81377 …Width:0x7 // The maximum number of Xx RAM messages; which may be stored in XX protection. Is re…
81378 …/Access:RW DataWidth:0x6 // The size of Xx protected message in Xx Messages RAM in QREGs. Upp…
81379 …070cUL //Access:RW DataWidth:0x7 // The maximum number of connections in the XX protection LC…
81381 …en unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.
81383 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
81384 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
81385 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
81386 …ataWidth:0x7 // Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global ena…
81387 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
81392 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81393 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81394 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81395 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
81396 …UL //Access:RW DataWidth:0x7 // Xx free messages threshold high. Used in Xx Bypass global ena…
81397 …54UL //Access:RW DataWidth:0x7 // Xx free messages threshold low Used in Xx Bypass global ena…
81398 …1200758UL //Access:R DataWidth:0x4 // Xx Connection Bypass Table fill level (in connections).
81401 … 0x1200764UL //Access:R DataWidth:0x7 // Xx Task Bypass Table fill level (in tasks).
81405 …4UL //Access:R DataWidth:0x6 // Xx LCID Arbiter direct prefetch FIFO fill level (in entries).
81406 …s:R DataWidth:0x6 // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries).
81407 …cUL //Access:R DataWidth:0x6 // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries).
81408 …taWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
81409 … 0x12007a4UL //Access:RW DataWidth:0x2 // Affinity type in case of input messag…
81410 … 0x12007a8UL //Access:RW DataWidth:0x1 // Exclusive type in case of input messag…
81411 … 0x12007acUL //Access:RW DataWidth:0x3 // Source affinity in case of input messag…
81412 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81413 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81414 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81415 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81416 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81417 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81418 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81419 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81420 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81421 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81422 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81423 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81424 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81425 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81426 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81427 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81428 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81429 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81430 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81431 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81432 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81433 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81434 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81435 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
81440 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
81441 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
81442 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
81443 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
81444 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
81445 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
81446 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
81447 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
81448 …854UL //Access:R DataWidth:0x1 // Aggregation Connection FIC buffer fill level (in messages).
81449 …0x1200858UL //Access:R DataWidth:0x5 // Storm Connection FIC buffer fill level (in messages).
81450 …/Access:RW DataWidth:0x2 // Aggregation Connection FIC buffer credit (in full message out par…
81451 …60UL //Access:RW DataWidth:0x2 // Storm Connection FIC buffer credit (in full message out par…
81452 … group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than…
81453 …re group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than A…
81454 …torm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTER…
81455 …dth:0x2 // Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTER…
81456 …DataWidth:0x2 // Storm Connection command buffer credit (Direct group). In sum with CM_REGISTER…
81457 …0x1200878UL //Access:R DataWidth:0x2 // Aggregation Task FIC buffer fill level (in messages).
81458 … 0x120087cUL //Access:R DataWidth:0x5 // Storm Task FIC buffer fill level (in messages).
81459 …80UL //Access:RW DataWidth:0x2 // Aggregation Task FIC buffer credit (in full message out par…
81460 …x1200884UL //Access:RW DataWidth:0x2 // Storm Task FIC buffer credit (in full message out par…
81461 …on group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more …
81462 …tore group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG need be no more th…
81463 … // Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTER…
81464 …DataWidth:0x2 // Aggregation Task command buffer credit (Direct group). In sum with CM_REGISTER…
81465 …:RW DataWidth:0x2 // Storm Task command buffer credit (Direct group). In sum with CM_REGISTER…
81467 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
81468 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
81469 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
81470 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
81471 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
81472 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
81473 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
81474 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
81475 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
81476 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
81481 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81482 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81483 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81484 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81485 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81486 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81487 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81488 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81497 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST…
81498 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_…
81499 … 0x1200a0cUL //Access:R DataWidth:0x4 // In-process Table fill level (in messa…
81500 … 0x1200a10UL //Access:R DataWidth:0x1 // In-process Table almost…
81506 …:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM ou…
81507 …Access:RW DataWidth:0x1 // If set, Xx task bypass state will be added in calculation of CM ou…
81524 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
81525 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
81526 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
81527 …1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the i…
81528 …th:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the i…
81529 … 0x1200a98UL //Access:RW DataWidth:0x5 // FIC output initial credit in REGQ pairs. Write wr…
81546 …1200af0UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in QM Primary Input Sta…
81547 …1200af4UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in QM Secondary Input S…
81548 …UL //Access:R DataWidth:0x5 // Number of entries (2 QREGs each) of data in STORM Input Stage.
81549 … 0x1200b00UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in YSDM Input Stage.
81550 … 0x1200b04UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in USDM Input Stage.
81551 …0x1200b08UL //Access:R DataWidth:0x6 // Number of 2 QREGs (256b) of data in TMLD Input Stage.
81552 … 0x1200b0cUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in USEM Input Stage.
81553 … 0x1200b14UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in PBF Input Stage.
81568 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
81571 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
81573 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
81575 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
81577 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
81579 …ss:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (…
81580 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
81581 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
81582 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
81583 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
81589 …//Access:R DataWidth:0xa // Debug only. Read only access to LCID CAM in XX protection mechan…
81592 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
81595 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
81597 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81598 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81599 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81600 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81601 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81602 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81603 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81604 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81605 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81606 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81607 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81608 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81609 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81610 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81611 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81612 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81613 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81614 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81615 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81616 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81617 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81618 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81619 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81620 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
81621 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81622 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81623 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81624 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81625 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81626 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81627 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81628 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81629 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81630 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81631 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81632 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81633 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81634 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81635 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81636 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81637 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81638 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81639 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81640 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81641 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81642 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81643 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81644 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
81765 …ess:R DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Rea…
81766 …ess:R DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Rea…
81769 …0x1202800UL //Access:RW DataWidth:0x3 // The weight of the input TSDM in the Input Arbiter WR…
81772 … 0x120280cUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in TSDM Input Stage.
81774 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
81776 …0x1202880UL //Access:RW DataWidth:0x3 // The weight of the input PSDM in the Input Arbiter WR…
81779 … 0x120288cUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in PSDM Input Stage.
81781 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
81783 …0x1200618UL //Access:RW DataWidth:0x3 // The weight of the MSDM input in the Input Arbiter WR…
81784 …0x1202900UL //Access:RW DataWidth:0x3 // The weight of the input MSDM in the Input Arbiter WR…
81789 … 0x1200afcUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in MSDM Input Stage.
81790 … 0x120290cUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in MSDM Input Stage.
81793 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
81794 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
81796 …0x120060cUL //Access:RW DataWidth:0x3 // The weight of the input Ysem in the Input Arbiter WR…
81797 …0x1202a00UL //Access:RW DataWidth:0x3 // The weight of the input Ysem in the Input Arbiter WR…
81800 … 0x1200b10UL //Access:R DataWidth:0x5 // Number of QREGs (128b) of data in YSEM Input Stage.
81801 …x4 // Number of QREGs (128b) for TCM, XCM or 2 QREGs (256b) for MCM of data in YSEM Input Stage.
81804 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
81805 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
81808 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81810 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81812 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81814 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81816 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
81817 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
81820 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
81826 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
81866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81867 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
81868 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81869 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
81870 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81871 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
81872 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81873 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
81874 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81875 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
81876 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81877 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
81878 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81879 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
81880 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
81881 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
82121 …_K2 (0x1<<18) // In-process Table overfl…
82123 … (0x1<<19) // In-process Table overfl…
82359 …_BB_K2 (0x1<<18) // In-process Table overfl…
82361 …_E5 (0x1<<19) // In-process Table overfl…
82478 …L_BB_K2 (0x1<<18) // In-process Table overfl…
82480 …L_E5 (0x1<<19) // In-process Table overfl…
82685 … (0x1<<0) // Enable ECC for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_ms…
82687 … (0x1<<1) // Enable ECC for memory ecc instance ucm.i_agg_con_ctx.i_ecc_0 in module ucm_mem_agg_c…
82689 … (0x1<<2) // Enable ECC for memory ecc instance ucm.i_agg_con_ctx.i_ecc_1 in module ucm_mem_agg_c…
82691 … (0x1<<3) // Enable ECC for memory ecc instance ucm.i_agg_con_ctx_2.i_ecc in module ucm_mem_agg_c…
82693 … (0x1<<4) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx.i_ecc_0 in module ucm_mem_sm_co…
82695 … (0x1<<5) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx.i_ecc_1 in module ucm_mem_sm_co…
82697 … (0x1<<6) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx.i_ecc_0 in module ucm_mem_agg_t…
82699 … (0x1<<7) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx.i_ecc_1 in module ucm_mem_agg_t…
82701 …x1<<9) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_ta…
82703 … (0x1<<8) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx.i_ecc_0 in module ucm_mem_sm_ta…
82705 …1<<10) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_ta…
82707 … (0x1<<9) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx.i_ecc_1 in module ucm_mem_sm_ta…
82709 … (0x1<<0) // Enable ECC for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_ms…
82711 …x1<<3) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_0 in module ucm_mem_sm_co…
82713 …x1<<4) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_1 in module ucm_mem_sm_co…
82715 … (0x1<<5) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx_12.i_ecc in module ucm_mem_sm_co…
82717 …1<<6) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_0 in module ucm_mem_agg_t…
82719 …1<<7) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_1 in module ucm_mem_agg_t…
82721 … (0x1<<8) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx_2.i_ecc in module ucm_mem_agg_t…
82723 … (0x1<<11) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_2.i_ecc in module ucm_mem_sm_ta…
82726 …(0x1<<0) // Set parity only for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_ms…
82728 …1<<1) // Set parity only for memory ecc instance ucm.i_agg_con_ctx.i_ecc_0 in module ucm_mem_agg_c…
82730 …1<<2) // Set parity only for memory ecc instance ucm.i_agg_con_ctx.i_ecc_1 in module ucm_mem_agg_c…
82732 …1<<3) // Set parity only for memory ecc instance ucm.i_agg_con_ctx_2.i_ecc in module ucm_mem_agg_c…
82734 …x1<<4) // Set parity only for memory ecc instance ucm.i_sm_con_ctx.i_ecc_0 in module ucm_mem_sm_co…
82736 …x1<<5) // Set parity only for memory ecc instance ucm.i_sm_con_ctx.i_ecc_1 in module ucm_mem_sm_co…
82738 …<<6) // Set parity only for memory ecc instance ucm.i_agg_task_ctx.i_ecc_0 in module ucm_mem_agg_t…
82740 …<<7) // Set parity only for memory ecc instance ucm.i_agg_task_ctx.i_ecc_1 in module ucm_mem_agg_t…
82742 …) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_ta…
82744 …1<<8) // Set parity only for memory ecc instance ucm.i_sm_task_ctx.i_ecc_0 in module ucm_mem_sm_ta…
82746 …) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_ta…
82748 …1<<9) // Set parity only for memory ecc instance ucm.i_sm_task_ctx.i_ecc_1 in module ucm_mem_sm_ta…
82750 …(0x1<<0) // Set parity only for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_ms…
82752 …) // Set parity only for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_0 in module ucm_mem_sm_co…
82754 …) // Set parity only for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_1 in module ucm_mem_sm_co…
82756 …1<<5) // Set parity only for memory ecc instance ucm.i_sm_con_ctx_12.i_ecc in module ucm_mem_sm_co…
82758 … // Set parity only for memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_0 in module ucm_mem_agg_t…
82760 … // Set parity only for memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_1 in module ucm_mem_agg_t…
82762 …<<8) // Set parity only for memory ecc instance ucm.i_agg_task_ctx_2.i_ecc in module ucm_mem_agg_t…
82764 …<<11) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_2.i_ecc in module ucm_mem_sm_ta…
82767 …a correctable error occurred on memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_ms…
82769 …orrectable error occurred on memory ecc instance ucm.i_agg_con_ctx.i_ecc_0 in module ucm_mem_agg_c…
82771 …orrectable error occurred on memory ecc instance ucm.i_agg_con_ctx.i_ecc_1 in module ucm_mem_agg_c…
82773 …orrectable error occurred on memory ecc instance ucm.i_agg_con_ctx_2.i_ecc in module ucm_mem_agg_c…
82775 …correctable error occurred on memory ecc instance ucm.i_sm_con_ctx.i_ecc_0 in module ucm_mem_sm_co…
82777 …correctable error occurred on memory ecc instance ucm.i_sm_con_ctx.i_ecc_1 in module ucm_mem_sm_co…
82779 …rrectable error occurred on memory ecc instance ucm.i_agg_task_ctx.i_ecc_0 in module ucm_mem_agg_t…
82781 …rrectable error occurred on memory ecc instance ucm.i_agg_task_ctx.i_ecc_1 in module ucm_mem_agg_t…
82783 …ctable error occurred on memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_ta…
82785 …orrectable error occurred on memory ecc instance ucm.i_sm_task_ctx.i_ecc_0 in module ucm_mem_sm_ta…
82787 …ctable error occurred on memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_ta…
82789 …orrectable error occurred on memory ecc instance ucm.i_sm_task_ctx.i_ecc_1 in module ucm_mem_sm_ta…
82791 …a correctable error occurred on memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_ms…
82793 …ctable error occurred on memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_0 in module ucm_mem_sm_co…
82795 …ctable error occurred on memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_1 in module ucm_mem_sm_co…
82797 …orrectable error occurred on memory ecc instance ucm.i_sm_con_ctx_12.i_ecc in module ucm_mem_sm_co…
82799 …table error occurred on memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_0 in module ucm_mem_agg_t…
82801 …table error occurred on memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_1 in module ucm_mem_agg_t…
82803 …rrectable error occurred on memory ecc instance ucm.i_agg_task_ctx_2.i_ecc in module ucm_mem_agg_t…
82805 …orrectable error occurred on memory ecc instance ucm.i_sm_task_ctx_2.i_ecc in module ucm_mem_sm_ta…
82808 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
82817 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
82818 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
82819 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
82820 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
82821 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
82822 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
82823 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
82824 …tion task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 i…
82833 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
82834 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
82835 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
82836 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
82837 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
82838 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
82839 …idth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
82849 … 0x1280564UL //Access:RW DataWidth:0x8 // The Event ID in case one of errors is set in QM in…
82850 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82851 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
82852 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82853 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
82854 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82855 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
82856 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82857 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
82858 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82859 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
82860 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82861 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
82862 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82863 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
82864 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82865 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
82866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82867 …ion rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable;…
82868 …04UL //Access:RW DataWidth:0x3 // The weight of the local Storm input in the Input Arbiter WR…
82869 …0x1280608UL //Access:RW DataWidth:0x3 // The weight of the input Dorq in the Input Arbiter WR…
82870 … 0x128060cUL //Access:RW DataWidth:0x3 // The weight of the input Pbf in the Input Arbiter WR…
82871 … 0x1280610UL //Access:RW DataWidth:0x3 // The weight of the GRC input in the Input Arbiter WR…
82872 …0x1280614UL //Access:RW DataWidth:0x3 // The weight of the XSDM input in the Input Arbiter WR…
82873 …0x1280618UL //Access:RW DataWidth:0x3 // The weight of the YSDM input in the Input Arbiter WR…
82874 …0x128061cUL //Access:RW DataWidth:0x3 // The weight of the input USDM in the Input Arbiter WR…
82875 …0x1280620UL //Access:RW DataWidth:0x3 // The weight of the input RDIF in the Input Arbiter WR…
82876 …0x1280624UL //Access:RW DataWidth:0x3 // The weight of the input RDIF in the Input Arbiter WR…
82877 …0x1280628UL //Access:RW DataWidth:0x3 // The weight of the input MULD in the Input Arbiter WR…
82878 …0x128062cUL //Access:RW DataWidth:0x3 // The weight of the input YULD in the Input Arbiter WR…
82879 …0UL //Access:RW DataWidth:0x3 // The weight of the QM (primary) input in the Input Arbiter WR…
82880 …L //Access:RW DataWidth:0x3 // The weight of the QM (secondary) input in the Input Arbiter WR…
82881 …1280638UL //Access:RW DataWidth:0x3 // The weight of the Timers input in the Input Arbiter WR…
82882 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82883 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82884 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82885 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82886 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82887 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82888 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
82889 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82890 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82891 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82892 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82893 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82894 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82895 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82896 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82897 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82898 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82899 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82900 …684UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable erro…
82902 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82903 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82904 …s:R DataWidth:0x3 // Input Arbiter Aggregation Connection part FIFO fill level (in messages).
82905 …/Access:R DataWidth:0x3 // Input Arbiter Storm Connection part FIFO fill level (in messages).
82906 …/Access:R DataWidth:0x3 // Input Arbiter Aggregation Task part FIFO fill level (in messages).
82907 …a0UL //Access:R DataWidth:0x3 // Input Arbiter Storm Task part FIFO fill level (in messages).
82908 …4UL //Access:R DataWidth:0x3 // Input Arbiter Transparent part FIFO fill level (in messages).
82909 …12806a8UL //Access:R DataWidth:0x2 // External read buffer FIFO fill level (in FIFO entries).
82910 …Width:0x7 // The maximum number of Xx RAM messages; which may be stored in XX protection. Is re…
82911 …/Access:RW DataWidth:0x5 // The size of Xx protected message in Xx Messages RAM in QREGs. Upp…
82912 …070cUL //Access:RW DataWidth:0x7 // The maximum number of connections in the XX protection LC…
82914 …en unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.
82916 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
82917 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
82918 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
82919 …ataWidth:0x7 // Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global ena…
82920 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
82925 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82926 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82927 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82928 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
82929 …UL //Access:RW DataWidth:0x7 // Xx free messages threshold high. Used in Xx Bypass global ena…
82930 …54UL //Access:RW DataWidth:0x7 // Xx free messages threshold low Used in Xx Bypass global ena…
82931 …1280758UL //Access:R DataWidth:0x4 // Xx Connection Bypass Table fill level (in connections).
82934 … 0x1280764UL //Access:R DataWidth:0x7 // Xx Task Bypass Table fill level (in tasks).
82938 …4UL //Access:R DataWidth:0x5 // Xx LCID Arbiter direct prefetch FIFO fill level (in entries).
82939 …s:R DataWidth:0x5 // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries).
82940 …cUL //Access:R DataWidth:0x5 // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries).
82941 …taWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
82942 … 0x12807a4UL //Access:RW DataWidth:0x2 // Affinity type in case of input messag…
82943 … 0x12807a8UL //Access:RW DataWidth:0x1 // Exclusive type in case of input messag…
82944 … 0x12807acUL //Access:RW DataWidth:0x3 // Source affinity in case of input messag…
82945 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82946 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82947 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82948 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82949 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82950 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82951 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82952 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82953 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82954 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82955 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82956 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82957 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82958 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82959 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82960 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82961 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82962 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82963 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82964 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82965 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82966 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82967 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82968 … // Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked …
82973 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
82974 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
82975 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
82976 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
82977 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
82978 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
82979 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
82980 …text and sent to STORM; for a specific task type. The offset of these data in the STORM context is…
82981 …854UL //Access:R DataWidth:0x2 // Aggregation Connection FIC buffer fill level (in messages).
82982 …0x1280858UL //Access:R DataWidth:0x5 // Storm Connection FIC buffer fill level (in messages).
82983 …/Access:RW DataWidth:0x2 // Aggregation Connection FIC buffer credit (in full message out par…
82984 …60UL //Access:RW DataWidth:0x2 // Storm Connection FIC buffer credit (in full message out par…
82985 … group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than…
82986 …re group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than A…
82987 …torm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTER…
82988 …dth:0x2 // Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTER…
82989 …DataWidth:0x2 // Storm Connection command buffer credit (Direct group). In sum with CM_REGISTER…
82990 …0x1280878UL //Access:R DataWidth:0x3 // Aggregation Task FIC buffer fill level (in messages).
82991 … 0x128087cUL //Access:R DataWidth:0x4 // Storm Task FIC buffer fill level (in messages).
82992 …80UL //Access:RW DataWidth:0x2 // Aggregation Task FIC buffer credit (in full message out par…
82993 …x1280884UL //Access:RW DataWidth:0x2 // Storm Task FIC buffer credit (in full message out par…
82994 …on group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more …
82995 …tore group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG need be no more th…
82996 … // Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTER…
82997 …DataWidth:0x2 // Aggregation Task command buffer credit (Direct group). In sum with CM_REGISTER…
82998 …:RW DataWidth:0x2 // Storm Task command buffer credit (Direct group). In sum with CM_REGISTER…
83000 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
83001 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
83002 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
83003 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
83004 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
83005 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
83006 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
83007 …regation task context size to be read/written back per task type (measured in REGQ). Minimum conte…
83008 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
83009 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
83014 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83015 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83016 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83017 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83018 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83019 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83020 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83021 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83022 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83031 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST…
83032 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_…
83033 … 0x1280a0cUL //Access:R DataWidth:0x4 // In-process Table fill level (in messa…
83034 … 0x1280a10UL //Access:R DataWidth:0x1 // In-process Table almost…
83042 …:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM ou…
83043 …Access:RW DataWidth:0x1 // If set, Xx task bypass state will be added in calculation of CM ou…
83060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
83061 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
83062 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
83063 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
83064 … 0x1280a94UL //Access:RW DataWidth:0x5 // FIC output initial credit in REGQ pairs. Write wr…
83091 …1280b0cUL //Access:R DataWidth:0x5 // Number of QREGs (128b) of data in QM Primary Input Sta…
83092 …1280b10UL //Access:R DataWidth:0x5 // Number of QREGs (128b) of data in QM Secondary Input S…
83093 … 0x1280b14UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in TM Input Stage.
83094 …UL //Access:R DataWidth:0x5 // Number of entries (2 QREGs each) of data in STORM Input Stage.
83095 … 0x1280b1cUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in XSDM Input Stage.
83096 … 0x1280b20UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in YSDM Input Stage.
83097 … 0x1280b24UL //Access:R DataWidth:0x4 // Number of QREGs (128b) of data in USDM Input Stage.
83098 … 0x1280b28UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in RDIF Input Stage.
83099 … 0x1280b2cUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in TDIF Input Stage.
83100 … 0x1280b30UL //Access:R DataWidth:0x6 // Number of QREGs (128b) of data in MULD Input Stage.
83101 … 0x1280b34UL //Access:R DataWidth:0x4 // Number of QREGs (128b) of data in YULD Input Stage.
83102 … 0x1280b38UL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in DORQ Input Stage.
83103 … 0x1280b3cUL //Access:R DataWidth:0x3 // Number of QREGs (128b) of data in PBF Input Stage.
83124 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
83127 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
83129 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
83131 …ess:R DataWidth:0x20 // Debug read from RDIF Input stage buffer with 32-bits granularity. Rea…
83133 …ess:R DataWidth:0x20 // Debug read from TDIF Input stage buffer with 32-bits granularity. Rea…
83135 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
83137 …ess:R DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Rea…
83139 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
83141 …ess:R DataWidth:0x20 // Debug read from YULD Input stage buffer with 32-bits granularity. Rea…
83143 …ss:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (…
83144 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
83145 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
83146 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
83147 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
83153 …//Access:R DataWidth:0xa // Debug only. Read only access to LCID CAM in XX protection mechan…
83156 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
83159 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
83185 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83186 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83187 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83188 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83189 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83190 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83191 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83192 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83193 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83194 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83195 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83196 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83197 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83198 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83199 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83200 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83201 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83202 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83203 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83204 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83205 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83206 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83207 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83208 …nd sent to STORM; for a specific connection type. The offset of these data in the STORM context is…
83209 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83210 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83211 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83212 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83213 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83214 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83215 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83216 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83217 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83218 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83219 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83220 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83221 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83222 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83223 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83224 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83225 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83226 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83227 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83228 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83229 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83230 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83231 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83232 …nection context size to be read/written back per connection type (measured in REGQ). Minimum conte…
83353 …ess:R DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Rea…
83354 …ess:R DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Rea…
83359 …0x1282808UL //Access:RW DataWidth:0x3 // The weight of the input Ysem in the Input Arbiter WR…
83361 …x4 // Number of QREGs (128b) for TCM, XCM or 2 QREGs (256b) for MCM of data in YSEM Input Stage.
83363 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
83365 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83366 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83367 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83368 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83369 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83370 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83371 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83372 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83373 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83374 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83375 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83376 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
83424 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
83435 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
83438 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
83440 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
83442 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
83444 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
83446 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
83449 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
83451 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
83453 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
83455 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83458 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
83460 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
83462 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
83464 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83494 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83496 … (0x1<<3) // Error in any one of the FIC F…
83502 …R_A_E5 (0x1<<6) // Error in external store slow …
83504 …R_B_E5 (0x1<<7) // Error in external store slow …
83506 …R_A_E5 (0x1<<8) // Error in external load sync s…
83508 …R_B_E5 (0x1<<9) // Error in external load sync s…
83510 …R_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
83512 … (0x1<<10) // Error in slow LS_SYNC_POP FIF…
83514 …R_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
83516 …5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
83518 … (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
83520 … (0x1<<13) // Error in slow LS_SYNC_POP FIF…
83522 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83524 … (0x1<<15) // Error detected in the ext Stroe interf…
83528 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
83530 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
83536 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
83538 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
83556 …2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
83558 …2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
83560 …BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
83562 …B_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
83564 …BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
83566 …B_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
83568 …2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
83570 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83572 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
83574 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
83576 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
83578 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
83580 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
83584 …R_BB_K2 (0x1<<18) // Error in external store sync …
83586 …_BB_K2 (0x1<<19) // Error in external store sync …
83588 …_BB_K2 (0x1<<20) // Error in external load sync F…
83590 …BB_K2 (0x1<<21) // Error in external load sync F…
83592 …R_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
83594 …R_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
83596 …B_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
83598 …B_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
83600 …2 (0x1<<28) // Error in slow debug fifo.
83602 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
83604 … (0x1<<30) // Error interrupt in VFC block.
83606 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
83732 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83734 … (0x1<<3) // Error in any one of the FIC F…
83740 …RROR_A_E5 (0x1<<6) // Error in external store slow …
83742 …RROR_B_E5 (0x1<<7) // Error in external store slow …
83744 …RROR_A_E5 (0x1<<8) // Error in external load sync s…
83746 …RROR_B_E5 (0x1<<9) // Error in external load sync s…
83748 …RROR_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
83750 …_E5 (0x1<<10) // Error in slow LS_SYNC_POP FIF…
83752 …RROR_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
83754 …R_E5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
83756 …E5 (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
83758 …E5 (0x1<<13) // Error in slow LS_SYNC_POP FIF…
83760 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83762 … (0x1<<15) // Error detected in the ext Stroe interf…
83766 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
83768 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
83774 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
83776 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
83794 …B_K2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
83796 …B_K2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
83798 …OR_BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
83800 …R_BB_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
83802 …OR_BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
83804 …R_BB_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
83806 …B_K2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
83808 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83810 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
83812 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
83814 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
83816 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
83818 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
83822 …RROR_BB_K2 (0x1<<18) // Error in external store sync …
83824 …ROR_BB_K2 (0x1<<19) // Error in external store sync …
83826 …ROR_BB_K2 (0x1<<20) // Error in external load sync F…
83828 …OR_BB_K2 (0x1<<21) // Error in external load sync F…
83830 …RROR_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
83832 …RROR_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
83834 …R_BB_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
83836 …R_BB_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
83838 …B_K2 (0x1<<28) // Error in slow debug fifo.
83840 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
83842 … (0x1<<30) // Error interrupt in VFC block.
83844 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
83851 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83853 … (0x1<<3) // Error in any one of the FIC F…
83859 …ERROR_A_E5 (0x1<<6) // Error in external store slow …
83861 …ERROR_B_E5 (0x1<<7) // Error in external store slow …
83863 …ERROR_A_E5 (0x1<<8) // Error in external load sync s…
83865 …ERROR_B_E5 (0x1<<9) // Error in external load sync s…
83867 …ERROR_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
83869 …R_E5 (0x1<<10) // Error in slow LS_SYNC_POP FIF…
83871 …ERROR_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
83873 …OR_E5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
83875 …_E5 (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
83877 …_E5 (0x1<<13) // Error in slow LS_SYNC_POP FIF…
83879 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83881 … (0x1<<15) // Error detected in the ext Stroe interf…
83885 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
83887 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
83893 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
83895 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
83913 …BB_K2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
83915 …BB_K2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
83917 …ROR_BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
83919 …OR_BB_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
83921 …ROR_BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
83923 …OR_BB_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
83925 …BB_K2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
83927 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83929 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
83931 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
83933 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
83935 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
83937 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
83941 …ERROR_BB_K2 (0x1<<18) // Error in external store sync …
83943 …RROR_BB_K2 (0x1<<19) // Error in external store sync …
83945 …RROR_BB_K2 (0x1<<20) // Error in external load sync F…
83947 …ROR_BB_K2 (0x1<<21) // Error in external load sync F…
83949 …ERROR_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
83951 …ERROR_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
83953 …OR_BB_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
83955 …OR_BB_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
83957 …BB_K2 (0x1<<28) // Error in slow debug fifo.
83959 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
83961 … (0x1<<30) // Error interrupt in VFC block.
83963 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
84018 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
84020 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
84022 … (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
84024 … (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
84026 … (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
84028 … (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
84030 … (0x1<<0) // An underflow error was detected in the Storm stack.
84032 … (0x1<<1) // An overflow error was detected in the Storm stack.
84038 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84040 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84044 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84046 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
84050 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
84054 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84200 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
84202 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
84204 … (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
84206 … (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
84208 … (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
84210 … (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
84212 … (0x1<<0) // An underflow error was detected in the Storm stack.
84214 … (0x1<<1) // An overflow error was detected in the Storm stack.
84220 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84222 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84226 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84228 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
84232 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
84236 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84291 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
84293 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
84295 …5 (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
84297 …5 (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
84299 …5 (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
84301 …5 (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
84303 … (0x1<<0) // An underflow error was detected in the Storm stack.
84305 … (0x1<<1) // An overflow error was detected in the Storm stack.
84311 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84313 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84317 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84319 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
84323 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
84327 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84338 … (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
84340 … (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
84346 …_A_E5 (0x1<<8) // Error in FOC error of Storm A.
84348 …_B_E5 (0x1<<9) // Error in FOC error of Storm B.
84356 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84358 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84464 …E5 (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
84466 …E5 (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
84472 …ROR_A_E5 (0x1<<8) // Error in FOC error of Storm A.
84474 …ROR_B_E5 (0x1<<9) // Error in FOC error of Storm B.
84482 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84484 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84527 …_E5 (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
84529 …_E5 (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
84535 …RROR_A_E5 (0x1<<8) // Error in FOC error of Storm A.
84537 …RROR_B_E5 (0x1<<9) // Error in FOC error of Storm B.
84545 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84547 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84612 …pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_…
84614 …pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_…
84617 …pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_…
84619 …pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_…
84622 …pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_…
84624 …pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_…
84627 … 0x1400400UL //Access:RW DataWidth:0x5 // The number of time_slots in the arbitration cycl…
84628 … 0x1400408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
84629 … 0x140040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
84630 … 0x1400420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
84633 … 0x1400440UL //Access:R DataWidth:0x10 // This read-only register provide…
84635 …e handler in the event that the PRAM address retrieved from the interrupt table is out of range wi…
84636 … 0x140044cUL //Access:R DataWidth:0x6 // Number of free entries in the external STORE s…
84640 …x1 // When set, this bit is used to allow low-power mode to be activated while threads are slee…
84641 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
84642 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
84643 …in which write to a thread address section passive buffer may occur simultaneously with read (as l…
84647 …0600UL //Access:RW DataWidth:0x6 // Per-FIC interface register array defines minimum number o…
84649 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
84650 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
84653 …transaction. The transfer will stall only when a transfer cycle is reached in which there are no i…
84654 …_R DataWidth:0x164 // Last fin command that was read from fifo. Its spelling in FIN_FIFO register.
84656 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
84659 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84660 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84662 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
84664 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
84666 …400b00UL //Access:R DataWidth:0x6 // The number of currently free threads (in invalid state).
84667 …0x1400b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
84673 …400b18UL //Access:RW DataWidth:0x6 // Defines the maixmum number of supported threads in SEMI.
84674 …1400b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
84675 …red for the FOC transfer to start. The values define in this register represents the number of Qua…
84677 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
84681 … 0x1400d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
84683 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
84685 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
84686 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
84689 … 0x1401004UL //Access:RW DataWidth:0x5 // The number of free entries in the sync FIFO betwee…
84690 …01008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DRA WR FIFO credit (in SEM_PD_CORE).
84696 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
84697 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 A queue. If FIC…
84698 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 X queue. If FIC…
84699 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 B queue. If FIC…
84700 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC1 A queue. If FIC…
84701 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
84703 … 0x1401104UL //Access:R DataWidth:0x1 // EXT_PAS FIFO empty in sem_slow.
84704 …ess:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
84706 … 0x1401140UL //Access:R DataWidth:0x1 // DBG FIFO is empty in sem_slow_ls_dbg.
84707 … 0x1401144UL //Access:R DataWidth:0x1 // FIN fifo is empty in sem_slow_dra_sync.
84708 … 0x1401148UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is empty in sem_slow_dra_sync.
84709 … 0x140114cUL //Access:R DataWidth:0x1 // DRA_WR push fifo is empty in sem_slow_dra_sync.
84710 … 0x1401150UL //Access:R DataWidth:0x2 // EXT_STORE FIFO is empty in sem_slow_ls_ext.
84711 … 0x1401154UL //Access:R DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit…
84712 … 0x1401158UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
84713 … 0x140115cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
84714 …taWidth:0x2 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A…
84715 …164UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is empty in sem_slow_dra_wr.
84716 …8UL //Access:R DataWidth:0x1 // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
84717 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
84720 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
84721 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
84722 … 0x1401200UL //Access:R DataWidth:0x1 // EXT_PAS FIFO Full in sem_slow.
84723 … 0x1401204UL //Access:R DataWidth:0x1 // EXT_STORE IF is full in sem_slow_ls_ext.
84724 …cess:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
84727 … 0x1401244UL //Access:R DataWidth:0x1 // EXT_RAM IF is full in sem_slow_ls_ram.
84728 … 0x1401248UL //Access:R DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg acco…
84729 … 0x140124cUL //Access:R DataWidth:0x1 // DBG FIFO is full in sem_slow_ls_dbg.
84730 … 0x1401250UL //Access:R DataWidth:0x1 // FIN fifo is full in sem_slow_dra_sync (n…
84731 … 0x1401254UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is full in sem_slow_dra_sync.
84732 … 0x1401258UL //Access:R DataWidth:0x1 // DRA_WR push fifo is full in sem_slow_dra_sync.
84733 …cess:R DataWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 …
84734 … 0x1401260UL //Access:R DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit…
84735 … 0x1401264UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
84736 … 0x1401268UL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
84737 … 0x140126cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
84738 …DataWidth:0x2 // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A…
84739 …1274UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
84740 …1278UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
84746 … 0x1401308UL //Access:R DataWidth:0x18 // Threads are sleeping in passive buffer more …
84749 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
84751 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
84752 … 0x1401414UL //Access:R DataWidth:0x1 // DBG IF is full in sem_slow_ls_dbg.
84754 … 0x140141cUL //Access:RW DataWidth:0x5 // In case DebugMode0Confi…
84756 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
84760 …ue (according to passive_buffer_performance_mon_stat value) of the stored threads in the FOC queue.
84761 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 A queue.
84762 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC1 A queue.
84763 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 A queue.
84764 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 A queue.
84765 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 X queue.
84766 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 X queue.
84767 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 X queue.
84768 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 B queue.
84769 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 B queue.
84770 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 B queue.
84771 … value (according to passive_buffer_performance_mon_stat value) of allocated threads in the system.
84772 …ng for ready indication to be run on Storm. Note -this statistic does not include the threads pend…
84778 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
84782 … 0x1408000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
84788 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
84793 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84794 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84847 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
84858 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
84861 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
84863 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
84865 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
84867 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
84869 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
84872 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
84874 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
84876 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
84878 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84881 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
84883 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
84885 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
84887 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84917 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
84919 … (0x1<<3) // Error in any one of the FIC F…
84925 …R_A_E5 (0x1<<6) // Error in external store slow …
84927 …R_B_E5 (0x1<<7) // Error in external store slow …
84929 …R_A_E5 (0x1<<8) // Error in external load sync s…
84931 …R_B_E5 (0x1<<9) // Error in external load sync s…
84933 …R_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
84935 … (0x1<<10) // Error in slow LS_SYNC_POP FIF…
84937 …R_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
84939 …5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
84941 … (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
84943 … (0x1<<13) // Error in slow LS_SYNC_POP FIF…
84945 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84947 … (0x1<<15) // Error detected in the ext Stroe interf…
84951 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
84953 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
84959 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
84961 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
84979 …2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
84981 …2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
84983 …BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
84985 …B_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
84987 …BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
84989 …B_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
84991 …2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
84993 … (0x1<<11) // Signals an unknown address in the fast-memory window.
84995 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
84997 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
84999 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
85001 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
85003 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
85007 …R_BB_K2 (0x1<<18) // Error in external store sync …
85009 …_BB_K2 (0x1<<19) // Error in external store sync …
85011 …_BB_K2 (0x1<<20) // Error in external load sync F…
85013 …BB_K2 (0x1<<21) // Error in external load sync F…
85015 …R_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
85017 …R_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
85019 …B_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
85021 …B_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
85023 …2 (0x1<<28) // Error in slow debug fifo.
85025 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
85027 … (0x1<<30) // Error interrupt in VFC block.
85029 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
85155 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85157 … (0x1<<3) // Error in any one of the FIC F…
85163 …RROR_A_E5 (0x1<<6) // Error in external store slow …
85165 …RROR_B_E5 (0x1<<7) // Error in external store slow …
85167 …RROR_A_E5 (0x1<<8) // Error in external load sync s…
85169 …RROR_B_E5 (0x1<<9) // Error in external load sync s…
85171 …RROR_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
85173 …_E5 (0x1<<10) // Error in slow LS_SYNC_POP FIF…
85175 …RROR_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
85177 …R_E5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
85179 …E5 (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
85181 …E5 (0x1<<13) // Error in slow LS_SYNC_POP FIF…
85183 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85185 … (0x1<<15) // Error detected in the ext Stroe interf…
85189 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
85191 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
85197 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
85199 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
85217 …B_K2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
85219 …B_K2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
85221 …OR_BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
85223 …R_BB_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
85225 …OR_BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
85227 …R_BB_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
85229 …B_K2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
85231 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85233 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
85235 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
85237 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
85239 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
85241 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
85245 …RROR_BB_K2 (0x1<<18) // Error in external store sync …
85247 …ROR_BB_K2 (0x1<<19) // Error in external store sync …
85249 …ROR_BB_K2 (0x1<<20) // Error in external load sync F…
85251 …OR_BB_K2 (0x1<<21) // Error in external load sync F…
85253 …RROR_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
85255 …RROR_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
85257 …R_BB_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
85259 …R_BB_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
85261 …B_K2 (0x1<<28) // Error in slow debug fifo.
85263 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
85265 … (0x1<<30) // Error interrupt in VFC block.
85267 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
85274 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85276 … (0x1<<3) // Error in any one of the FIC F…
85282 …ERROR_A_E5 (0x1<<6) // Error in external store slow …
85284 …ERROR_B_E5 (0x1<<7) // Error in external store slow …
85286 …ERROR_A_E5 (0x1<<8) // Error in external load sync s…
85288 …ERROR_B_E5 (0x1<<9) // Error in external load sync s…
85290 …ERROR_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
85292 …R_E5 (0x1<<10) // Error in slow LS_SYNC_POP FIF…
85294 …ERROR_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
85296 …OR_E5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
85298 …_E5 (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
85300 …_E5 (0x1<<13) // Error in slow LS_SYNC_POP FIF…
85302 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85304 … (0x1<<15) // Error detected in the ext Stroe interf…
85308 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
85310 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
85316 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
85318 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
85336 …BB_K2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
85338 …BB_K2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
85340 …ROR_BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
85342 …OR_BB_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
85344 …ROR_BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
85346 …OR_BB_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
85348 …BB_K2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
85350 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85352 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
85354 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
85356 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
85358 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
85360 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
85364 …ERROR_BB_K2 (0x1<<18) // Error in external store sync …
85366 …RROR_BB_K2 (0x1<<19) // Error in external store sync …
85368 …RROR_BB_K2 (0x1<<20) // Error in external load sync F…
85370 …ROR_BB_K2 (0x1<<21) // Error in external load sync F…
85372 …ERROR_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
85374 …ERROR_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
85376 …OR_BB_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
85378 …OR_BB_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
85380 …BB_K2 (0x1<<28) // Error in slow debug fifo.
85382 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
85384 … (0x1<<30) // Error interrupt in VFC block.
85386 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
85441 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
85443 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
85445 … (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
85447 … (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
85449 … (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
85451 … (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
85453 … (0x1<<0) // An underflow error was detected in the Storm stack.
85455 … (0x1<<1) // An overflow error was detected in the Storm stack.
85461 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85463 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85467 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85469 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
85473 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
85477 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85623 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
85625 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
85627 … (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
85629 … (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
85631 … (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
85633 … (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
85635 … (0x1<<0) // An underflow error was detected in the Storm stack.
85637 … (0x1<<1) // An overflow error was detected in the Storm stack.
85643 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85645 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85649 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85651 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
85655 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
85659 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85714 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
85716 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
85718 …5 (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
85720 …5 (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
85722 …5 (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
85724 …5 (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
85726 … (0x1<<0) // An underflow error was detected in the Storm stack.
85728 … (0x1<<1) // An overflow error was detected in the Storm stack.
85734 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85736 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85740 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85742 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
85746 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
85750 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85761 … (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
85763 … (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
85769 …_A_E5 (0x1<<8) // Error in FOC error of Storm A.
85771 …_B_E5 (0x1<<9) // Error in FOC error of Storm B.
85779 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85781 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85887 …E5 (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
85889 …E5 (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
85895 …ROR_A_E5 (0x1<<8) // Error in FOC error of Storm A.
85897 …ROR_B_E5 (0x1<<9) // Error in FOC error of Storm B.
85905 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85907 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85950 …_E5 (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
85952 …_E5 (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
85958 …RROR_A_E5 (0x1<<8) // Error in FOC error of Storm A.
85960 …RROR_B_E5 (0x1<<9) // Error in FOC error of Storm B.
85968 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85970 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
86035 …s_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_0 in module sem_slow_pas_…
86037 …s_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_1 in module sem_slow_pas_…
86040 …s_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_0 in module sem_slow_pas_…
86042 …s_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_1 in module sem_slow_pas_…
86045 …s_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_0 in module sem_slow_pas_…
86047 …s_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_1 in module sem_slow_pas_…
86050 … 0x1500400UL //Access:RW DataWidth:0x5 // The number of time_slots in the arbitration cycl…
86051 … 0x1500408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
86052 … 0x150040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
86053 … 0x1500420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
86056 … 0x1500440UL //Access:R DataWidth:0x10 // This read-only register provide…
86058 …e handler in the event that the PRAM address retrieved from the interrupt table is out of range wi…
86059 … 0x150044cUL //Access:R DataWidth:0x6 // Number of free entries in the external STORE s…
86063 …x1 // When set, this bit is used to allow low-power mode to be activated while threads are slee…
86064 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
86065 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
86066 …in which write to a thread address section passive buffer may occur simultaneously with read (as l…
86070 …0600UL //Access:RW DataWidth:0x6 // Per-FIC interface register array defines minimum number o…
86072 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
86073 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
86076 …transaction. The transfer will stall only when a transfer cycle is reached in which there are no i…
86077 …_R DataWidth:0x164 // Last fin command that was read from fifo. Its spelling in FIN_FIFO register.
86079 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
86082 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86083 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86085 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
86087 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
86089 …500b00UL //Access:R DataWidth:0x6 // The number of currently free threads (in invalid state).
86090 …0x1500b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
86096 …500b18UL //Access:RW DataWidth:0x6 // Defines the maixmum number of supported threads in SEMI.
86097 …1500b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
86098 …red for the FOC transfer to start. The values define in this register represents the number of Qua…
86100 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
86104 … 0x1500d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
86106 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
86108 …L //Access:RW DataWidth:0xe // Provides access to the thread ordering queue pop-enable vector.
86109 … //Access:RW DataWidth:0xe // Provides access to the thread ordering queue wake-enable vector.
86112 … 0x1501004UL //Access:RW DataWidth:0x5 // The number of free entries in the sync FIFO betwee…
86113 …01008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DRA WR FIFO credit (in SEM_PD_CORE).
86119 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
86120 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 A queue. If FIC…
86121 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 X queue. If FIC…
86122 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 B queue. If FIC…
86123 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC1 A queue. If FIC…
86124 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
86126 … 0x1501104UL //Access:R DataWidth:0x1 // EXT_PAS FIFO empty in sem_slow.
86127 …ess:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
86129 … 0x1501140UL //Access:R DataWidth:0x1 // DBG FIFO is empty in sem_slow_ls_dbg.
86130 … 0x1501144UL //Access:R DataWidth:0x1 // FIN fifo is empty in sem_slow_dra_sync.
86131 … 0x1501148UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is empty in sem_slow_dra_sync.
86132 … 0x150114cUL //Access:R DataWidth:0x1 // DRA_WR push fifo is empty in sem_slow_dra_sync.
86133 … 0x1501150UL //Access:R DataWidth:0x2 // EXT_STORE FIFO is empty in sem_slow_ls_ext.
86134 … 0x1501154UL //Access:R DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit…
86135 … 0x1501158UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
86136 … 0x150115cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
86137 …taWidth:0x2 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A…
86138 …164UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is empty in sem_slow_dra_wr.
86139 …8UL //Access:R DataWidth:0x1 // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
86140 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
86143 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
86144 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
86145 … 0x1501200UL //Access:R DataWidth:0x1 // EXT_PAS FIFO Full in sem_slow.
86146 … 0x1501204UL //Access:R DataWidth:0x1 // EXT_STORE IF is full in sem_slow_ls_ext.
86147 …cess:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
86150 … 0x1501244UL //Access:R DataWidth:0x1 // EXT_RAM IF is full in sem_slow_ls_ram.
86151 … 0x1501248UL //Access:R DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg acco…
86152 … 0x150124cUL //Access:R DataWidth:0x1 // DBG FIFO is full in sem_slow_ls_dbg.
86153 … 0x1501250UL //Access:R DataWidth:0x1 // FIN fifo is full in sem_slow_dra_sync (n…
86154 … 0x1501254UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is full in sem_slow_dra_sync.
86155 … 0x1501258UL //Access:R DataWidth:0x1 // DRA_WR push fifo is full in sem_slow_dra_sync.
86156 …cess:R DataWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 …
86157 … 0x1501260UL //Access:R DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit…
86158 … 0x1501264UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
86159 … 0x1501268UL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
86160 … 0x150126cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
86161 …DataWidth:0x2 // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A…
86162 …1274UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
86163 …1278UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
86169 … 0x1501308UL //Access:R DataWidth:0xe // Threads are sleeping in passive buffer more …
86172 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
86174 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
86175 … 0x1501414UL //Access:R DataWidth:0x1 // DBG IF is full in sem_slow_ls_dbg.
86177 … 0x150141cUL //Access:RW DataWidth:0x5 // In case DebugMode0Confi…
86179 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
86183 …ue (according to passive_buffer_performance_mon_stat value) of the stored threads in the FOC queue.
86184 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 A queue.
86185 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC1 A queue.
86186 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 A queue.
86187 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 A queue.
86188 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 X queue.
86189 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 X queue.
86190 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 X queue.
86191 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 B queue.
86192 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 B queue.
86193 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 B queue.
86194 … value (according to passive_buffer_performance_mon_stat value) of allocated threads in the system.
86195 …ng for ready indication to be run on Storm. Note -this statistic does not include the threads pend…
86201 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
86205 … 0x1508000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the ex…
86211 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
86216 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86217 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86271 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
86282 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
86285 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
86287 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
86289 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
86291 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
86293 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
86296 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
86298 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
86300 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
86302 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86305 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
86307 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
86309 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
86311 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86341 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86343 … (0x1<<3) // Error in any one of the FIC F…
86349 …R_A_E5 (0x1<<6) // Error in external store slow …
86351 …R_B_E5 (0x1<<7) // Error in external store slow …
86353 …R_A_E5 (0x1<<8) // Error in external load sync s…
86355 …R_B_E5 (0x1<<9) // Error in external load sync s…
86357 …R_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
86359 … (0x1<<10) // Error in slow LS_SYNC_POP FIF…
86361 …R_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
86363 …5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
86365 … (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
86367 … (0x1<<13) // Error in slow LS_SYNC_POP FIF…
86369 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86371 … (0x1<<15) // Error detected in the ext Stroe interf…
86375 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
86377 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
86383 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
86385 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
86403 …2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
86405 …2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
86407 …BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
86409 …B_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
86411 …BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
86413 …B_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
86415 …2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
86417 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86419 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
86421 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
86423 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
86425 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
86427 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
86431 …R_BB_K2 (0x1<<18) // Error in external store sync …
86433 …_BB_K2 (0x1<<19) // Error in external store sync …
86435 …_BB_K2 (0x1<<20) // Error in external load sync F…
86437 …BB_K2 (0x1<<21) // Error in external load sync F…
86439 …R_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
86441 …R_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
86443 …B_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
86445 …B_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
86447 …2 (0x1<<28) // Error in slow debug fifo.
86449 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
86451 … (0x1<<30) // Error interrupt in VFC block.
86453 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
86579 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86581 … (0x1<<3) // Error in any one of the FIC F…
86587 …RROR_A_E5 (0x1<<6) // Error in external store slow …
86589 …RROR_B_E5 (0x1<<7) // Error in external store slow …
86591 …RROR_A_E5 (0x1<<8) // Error in external load sync s…
86593 …RROR_B_E5 (0x1<<9) // Error in external load sync s…
86595 …RROR_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
86597 …_E5 (0x1<<10) // Error in slow LS_SYNC_POP FIF…
86599 …RROR_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
86601 …R_E5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
86603 …E5 (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
86605 …E5 (0x1<<13) // Error in slow LS_SYNC_POP FIF…
86607 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86609 … (0x1<<15) // Error detected in the ext Stroe interf…
86613 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
86615 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
86621 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
86623 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
86641 …B_K2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
86643 …B_K2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
86645 …OR_BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
86647 …R_BB_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
86649 …OR_BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
86651 …R_BB_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
86653 …B_K2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
86655 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86657 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
86659 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
86661 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
86663 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
86665 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
86669 …RROR_BB_K2 (0x1<<18) // Error in external store sync …
86671 …ROR_BB_K2 (0x1<<19) // Error in external store sync …
86673 …ROR_BB_K2 (0x1<<20) // Error in external load sync F…
86675 …OR_BB_K2 (0x1<<21) // Error in external load sync F…
86677 …RROR_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
86679 …RROR_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
86681 …R_BB_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
86683 …R_BB_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
86685 …B_K2 (0x1<<28) // Error in slow debug fifo.
86687 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
86689 … (0x1<<30) // Error interrupt in VFC block.
86691 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
86698 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86700 … (0x1<<3) // Error in any one of the FIC F…
86706 …ERROR_A_E5 (0x1<<6) // Error in external store slow …
86708 …ERROR_B_E5 (0x1<<7) // Error in external store slow …
86710 …ERROR_A_E5 (0x1<<8) // Error in external load sync s…
86712 …ERROR_B_E5 (0x1<<9) // Error in external load sync s…
86714 …ERROR_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
86716 …R_E5 (0x1<<10) // Error in slow LS_SYNC_POP FIF…
86718 …ERROR_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
86720 …OR_E5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
86722 …_E5 (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
86724 …_E5 (0x1<<13) // Error in slow LS_SYNC_POP FIF…
86726 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86728 … (0x1<<15) // Error detected in the ext Stroe interf…
86732 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
86734 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
86740 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
86742 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
86760 …BB_K2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
86762 …BB_K2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
86764 …ROR_BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
86766 …OR_BB_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
86768 …ROR_BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
86770 …OR_BB_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
86772 …BB_K2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
86774 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86776 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
86778 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
86780 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
86782 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
86784 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
86788 …ERROR_BB_K2 (0x1<<18) // Error in external store sync …
86790 …RROR_BB_K2 (0x1<<19) // Error in external store sync …
86792 …RROR_BB_K2 (0x1<<20) // Error in external load sync F…
86794 …ROR_BB_K2 (0x1<<21) // Error in external load sync F…
86796 …ERROR_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
86798 …ERROR_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
86800 …OR_BB_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
86802 …OR_BB_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
86804 …BB_K2 (0x1<<28) // Error in slow debug fifo.
86806 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
86808 … (0x1<<30) // Error interrupt in VFC block.
86810 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
86865 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
86867 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
86869 … (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
86871 … (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
86873 … (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
86875 … (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
86877 … (0x1<<0) // An underflow error was detected in the Storm stack.
86879 … (0x1<<1) // An overflow error was detected in the Storm stack.
86885 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
86887 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
86891 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86893 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
86897 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
86901 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87047 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
87049 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
87051 … (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
87053 … (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
87055 … (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
87057 … (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
87059 … (0x1<<0) // An underflow error was detected in the Storm stack.
87061 … (0x1<<1) // An overflow error was detected in the Storm stack.
87067 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
87069 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
87073 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87075 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
87079 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
87083 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87138 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
87140 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
87142 …5 (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
87144 …5 (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
87146 …5 (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
87148 …5 (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
87150 … (0x1<<0) // An underflow error was detected in the Storm stack.
87152 … (0x1<<1) // An overflow error was detected in the Storm stack.
87158 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
87160 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
87164 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87166 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
87170 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
87174 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87185 … (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
87187 … (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
87193 …_A_E5 (0x1<<8) // Error in FOC error of Storm A.
87195 …_B_E5 (0x1<<9) // Error in FOC error of Storm B.
87203 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87205 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87311 …E5 (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
87313 …E5 (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
87319 …ROR_A_E5 (0x1<<8) // Error in FOC error of Storm A.
87321 …ROR_B_E5 (0x1<<9) // Error in FOC error of Storm B.
87329 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87331 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87374 …_E5 (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
87376 …_E5 (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
87382 …RROR_A_E5 (0x1<<8) // Error in FOC error of Storm A.
87384 …RROR_B_E5 (0x1<<9) // Error in FOC error of Storm B.
87392 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87394 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87457 …s_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_0 in module sem_slow_pas_…
87459 …s_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_1 in module sem_slow_pas_…
87462 …s_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_0 in module sem_slow_pas_…
87464 …s_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_1 in module sem_slow_pas_…
87467 …s_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_0 in module sem_slow_pas_…
87469 …s_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_1 in module sem_slow_pas_…
87472 … 0x1600400UL //Access:RW DataWidth:0x5 // The number of time_slots in the arbitration cycl…
87473 … 0x1600408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
87474 … 0x160040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
87475 … 0x1600420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
87478 … 0x1600440UL //Access:R DataWidth:0x10 // This read-only register provide…
87480 …e handler in the event that the PRAM address retrieved from the interrupt table is out of range wi…
87481 … 0x160044cUL //Access:R DataWidth:0x6 // Number of free entries in the external STORE s…
87485 …x1 // When set, this bit is used to allow low-power mode to be activated while threads are slee…
87486 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
87487 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
87488 …in which write to a thread address section passive buffer may occur simultaneously with read (as l…
87492 …0600UL //Access:RW DataWidth:0x6 // Per-FIC interface register array defines minimum number o…
87493 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
87494 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
87497 …transaction. The transfer will stall only when a transfer cycle is reached in which there are no i…
87498 …_R DataWidth:0x164 // Last fin command that was read from fifo. Its spelling in FIN_FIFO register.
87500 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
87503 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87504 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87506 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
87508 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
87510 …600b00UL //Access:R DataWidth:0x6 // The number of currently free threads (in invalid state).
87511 …0x1600b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
87517 …600b18UL //Access:RW DataWidth:0x6 // Defines the maixmum number of supported threads in SEMI.
87518 …1600b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
87519 …red for the FOC transfer to start. The values define in this register represents the number of Qua…
87521 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
87525 … 0x1600d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
87527 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
87529 …L //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue pop-enable vector.
87530 … //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue wake-enable vector.
87533 … 0x1601004UL //Access:RW DataWidth:0x5 // The number of free entries in the sync FIFO betwee…
87534 …01008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DRA WR FIFO credit (in SEM_PD_CORE).
87540 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
87541 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 A queue. If FIC…
87542 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 X queue. If FIC…
87543 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 B queue. If FIC…
87544 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC1 A queue. If FIC…
87545 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
87547 … 0x1601104UL //Access:R DataWidth:0x1 // EXT_PAS FIFO empty in sem_slow.
87548 …ess:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
87549 … 0x1601140UL //Access:R DataWidth:0x1 // DBG FIFO is empty in sem_slow_ls_dbg.
87550 … 0x1601144UL //Access:R DataWidth:0x1 // FIN fifo is empty in sem_slow_dra_sync.
87551 … 0x1601148UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is empty in sem_slow_dra_sync.
87552 … 0x160114cUL //Access:R DataWidth:0x1 // DRA_WR push fifo is empty in sem_slow_dra_sync.
87553 … 0x1601150UL //Access:R DataWidth:0x2 // EXT_STORE FIFO is empty in sem_slow_ls_ext.
87554 … 0x1601154UL //Access:R DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit…
87555 … 0x1601158UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
87556 … 0x160115cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
87557 …taWidth:0x2 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A…
87558 …164UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is empty in sem_slow_dra_wr.
87559 …8UL //Access:R DataWidth:0x1 // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
87560 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
87563 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
87564 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
87565 … 0x1601200UL //Access:R DataWidth:0x1 // EXT_PAS FIFO Full in sem_slow.
87566 … 0x1601204UL //Access:R DataWidth:0x1 // EXT_STORE IF is full in sem_slow_ls_ext.
87567 …cess:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
87569 … 0x1601244UL //Access:R DataWidth:0x1 // EXT_RAM IF is full in sem_slow_ls_ram.
87570 … 0x1601248UL //Access:R DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg acco…
87571 … 0x160124cUL //Access:R DataWidth:0x1 // DBG FIFO is full in sem_slow_ls_dbg.
87572 … 0x1601250UL //Access:R DataWidth:0x1 // FIN fifo is full in sem_slow_dra_sync (n…
87573 … 0x1601254UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is full in sem_slow_dra_sync.
87574 … 0x1601258UL //Access:R DataWidth:0x1 // DRA_WR push fifo is full in sem_slow_dra_sync.
87575 …cess:R DataWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 …
87576 … 0x1601260UL //Access:R DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit…
87577 … 0x1601264UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
87578 … 0x1601268UL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
87579 … 0x160126cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
87580 …DataWidth:0x2 // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A…
87581 …1274UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
87582 …1278UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
87588 … 0x1601308UL //Access:R DataWidth:0x4 // Threads are sleeping in passive buffer more …
87591 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
87593 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
87594 … 0x1601414UL //Access:R DataWidth:0x1 // DBG IF is full in sem_slow_ls_dbg.
87596 … 0x160141cUL //Access:RW DataWidth:0x5 // In case DebugMode0Confi…
87598 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
87602 …ue (according to passive_buffer_performance_mon_stat value) of the stored threads in the FOC queue.
87603 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 A queue.
87604 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC1 A queue.
87605 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 A queue.
87606 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 A queue.
87607 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 X queue.
87608 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 X queue.
87609 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 X queue.
87610 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 B queue.
87611 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 B queue.
87612 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 B queue.
87613 … value (according to passive_buffer_performance_mon_stat value) of allocated threads in the system.
87614 …ng for ready indication to be run on Storm. Note -this statistic does not include the threads pend…
87620 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
87624 … 0x1608000UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the ex…
87630 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
87635 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87636 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87690 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
87701 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
87704 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
87706 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
87708 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
87710 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
87712 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
87715 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
87717 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
87719 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
87721 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87724 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
87726 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
87728 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
87730 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87760 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
87762 … (0x1<<3) // Error in any one of the FIC F…
87768 …R_A_E5 (0x1<<6) // Error in external store slow …
87770 …R_B_E5 (0x1<<7) // Error in external store slow …
87772 …R_A_E5 (0x1<<8) // Error in external load sync s…
87774 …R_B_E5 (0x1<<9) // Error in external load sync s…
87776 …R_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
87778 … (0x1<<10) // Error in slow LS_SYNC_POP FIF…
87780 …R_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
87782 …5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
87784 … (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
87786 … (0x1<<13) // Error in slow LS_SYNC_POP FIF…
87788 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87790 … (0x1<<15) // Error detected in the ext Stroe interf…
87794 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
87796 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
87802 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
87804 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
87822 …2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
87824 …2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
87826 …BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
87828 …B_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
87830 …BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
87832 …B_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
87834 …2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
87836 … (0x1<<11) // Signals an unknown address in the fast-memory window.
87838 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
87840 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
87842 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
87844 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
87846 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
87850 …R_BB_K2 (0x1<<18) // Error in external store sync …
87852 …_BB_K2 (0x1<<19) // Error in external store sync …
87854 …_BB_K2 (0x1<<20) // Error in external load sync F…
87856 …BB_K2 (0x1<<21) // Error in external load sync F…
87858 …R_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
87860 …R_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
87862 …B_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
87864 …B_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
87866 …2 (0x1<<28) // Error in slow debug fifo.
87868 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
87870 … (0x1<<30) // Error interrupt in VFC block.
87872 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
87998 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88000 … (0x1<<3) // Error in any one of the FIC F…
88006 …RROR_A_E5 (0x1<<6) // Error in external store slow …
88008 …RROR_B_E5 (0x1<<7) // Error in external store slow …
88010 …RROR_A_E5 (0x1<<8) // Error in external load sync s…
88012 …RROR_B_E5 (0x1<<9) // Error in external load sync s…
88014 …RROR_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
88016 …_E5 (0x1<<10) // Error in slow LS_SYNC_POP FIF…
88018 …RROR_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
88020 …R_E5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
88022 …E5 (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
88024 …E5 (0x1<<13) // Error in slow LS_SYNC_POP FIF…
88026 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88028 … (0x1<<15) // Error detected in the ext Stroe interf…
88032 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
88034 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
88040 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
88042 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
88060 …B_K2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
88062 …B_K2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
88064 …OR_BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
88066 …R_BB_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
88068 …OR_BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
88070 …R_BB_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
88072 …B_K2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
88074 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88076 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
88078 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
88080 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
88082 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
88084 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
88088 …RROR_BB_K2 (0x1<<18) // Error in external store sync …
88090 …ROR_BB_K2 (0x1<<19) // Error in external store sync …
88092 …ROR_BB_K2 (0x1<<20) // Error in external load sync F…
88094 …OR_BB_K2 (0x1<<21) // Error in external load sync F…
88096 …RROR_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
88098 …RROR_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
88100 …R_BB_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
88102 …R_BB_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
88104 …B_K2 (0x1<<28) // Error in slow debug fifo.
88106 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
88108 … (0x1<<30) // Error interrupt in VFC block.
88110 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
88117 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88119 … (0x1<<3) // Error in any one of the FIC F…
88125 …ERROR_A_E5 (0x1<<6) // Error in external store slow …
88127 …ERROR_B_E5 (0x1<<7) // Error in external store slow …
88129 …ERROR_A_E5 (0x1<<8) // Error in external load sync s…
88131 …ERROR_B_E5 (0x1<<9) // Error in external load sync s…
88133 …ERROR_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
88135 …R_E5 (0x1<<10) // Error in slow LS_SYNC_POP FIF…
88137 …ERROR_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
88139 …OR_E5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
88141 …_E5 (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
88143 …_E5 (0x1<<13) // Error in slow LS_SYNC_POP FIF…
88145 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88147 … (0x1<<15) // Error detected in the ext Stroe interf…
88151 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
88153 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
88159 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
88161 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
88179 …BB_K2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
88181 …BB_K2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
88183 …ROR_BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
88185 …OR_BB_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
88187 …ROR_BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
88189 …OR_BB_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
88191 …BB_K2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
88193 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88195 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
88197 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
88199 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
88201 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
88203 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
88207 …ERROR_BB_K2 (0x1<<18) // Error in external store sync …
88209 …RROR_BB_K2 (0x1<<19) // Error in external store sync …
88211 …RROR_BB_K2 (0x1<<20) // Error in external load sync F…
88213 …ROR_BB_K2 (0x1<<21) // Error in external load sync F…
88215 …ERROR_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
88217 …ERROR_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
88219 …OR_BB_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
88221 …OR_BB_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
88223 …BB_K2 (0x1<<28) // Error in slow debug fifo.
88225 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
88227 … (0x1<<30) // Error interrupt in VFC block.
88229 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
88284 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
88286 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
88288 … (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
88290 … (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
88292 … (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
88294 … (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
88296 … (0x1<<0) // An underflow error was detected in the Storm stack.
88298 … (0x1<<1) // An overflow error was detected in the Storm stack.
88304 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88306 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88310 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88312 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
88316 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
88320 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88466 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
88468 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
88470 … (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
88472 … (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
88474 … (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
88476 … (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
88478 … (0x1<<0) // An underflow error was detected in the Storm stack.
88480 … (0x1<<1) // An overflow error was detected in the Storm stack.
88486 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88488 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88492 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88494 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
88498 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
88502 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88557 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
88559 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
88561 …5 (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
88563 …5 (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
88565 …5 (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
88567 …5 (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
88569 … (0x1<<0) // An underflow error was detected in the Storm stack.
88571 … (0x1<<1) // An overflow error was detected in the Storm stack.
88577 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88579 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88583 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88585 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
88589 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
88593 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88604 … (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
88606 … (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
88612 …_A_E5 (0x1<<8) // Error in FOC error of Storm A.
88614 …_B_E5 (0x1<<9) // Error in FOC error of Storm B.
88622 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88624 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88730 …E5 (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
88732 …E5 (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
88738 …ROR_A_E5 (0x1<<8) // Error in FOC error of Storm A.
88740 …ROR_B_E5 (0x1<<9) // Error in FOC error of Storm B.
88748 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88750 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88793 …_E5 (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
88795 …_E5 (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
88801 …RROR_A_E5 (0x1<<8) // Error in FOC error of Storm A.
88803 …RROR_B_E5 (0x1<<9) // Error in FOC error of Storm B.
88811 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88813 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88876 …pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_…
88878 …pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_…
88881 …pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_…
88883 …pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_…
88886 …pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_…
88888 …pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_…
88891 … 0x1700400UL //Access:RW DataWidth:0x5 // The number of time_slots in the arbitration cycl…
88892 … 0x1700408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
88893 … 0x170040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
88894 … 0x1700420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
88897 … 0x1700440UL //Access:R DataWidth:0x10 // This read-only register provide…
88899 …e handler in the event that the PRAM address retrieved from the interrupt table is out of range wi…
88900 … 0x170044cUL //Access:R DataWidth:0x6 // Number of free entries in the external STORE s…
88904 …x1 // When set, this bit is used to allow low-power mode to be activated while threads are slee…
88905 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
88906 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
88907 …in which write to a thread address section passive buffer may occur simultaneously with read (as l…
88911 …0600UL //Access:RW DataWidth:0x6 // Per-FIC interface register array defines minimum number o…
88912 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
88913 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
88916 …transaction. The transfer will stall only when a transfer cycle is reached in which there are no i…
88917 …_R DataWidth:0x164 // Last fin command that was read from fifo. Its spelling in FIN_FIFO register.
88919 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
88922 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88923 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88925 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
88927 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
88929 …700b00UL //Access:R DataWidth:0x6 // The number of currently free threads (in invalid state).
88930 …0x1700b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
88936 …700b18UL //Access:RW DataWidth:0x6 // Defines the maixmum number of supported threads in SEMI.
88937 …1700b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
88938 …red for the FOC transfer to start. The values define in this register represents the number of Qua…
88940 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
88944 … 0x1700d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
88946 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
88948 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
88949 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
88952 … 0x1701004UL //Access:RW DataWidth:0x5 // The number of free entries in the sync FIFO betwee…
88953 …01008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DRA WR FIFO credit (in SEM_PD_CORE).
88959 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
88960 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 A queue. If FIC…
88961 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 X queue. If FIC…
88962 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 B queue. If FIC…
88963 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC1 A queue. If FIC…
88964 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
88966 … 0x1701104UL //Access:R DataWidth:0x1 // EXT_PAS FIFO empty in sem_slow.
88967 …ess:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
88968 … 0x1701140UL //Access:R DataWidth:0x1 // DBG FIFO is empty in sem_slow_ls_dbg.
88969 … 0x1701144UL //Access:R DataWidth:0x1 // FIN fifo is empty in sem_slow_dra_sync.
88970 … 0x1701148UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is empty in sem_slow_dra_sync.
88971 … 0x170114cUL //Access:R DataWidth:0x1 // DRA_WR push fifo is empty in sem_slow_dra_sync.
88972 … 0x1701150UL //Access:R DataWidth:0x2 // EXT_STORE FIFO is empty in sem_slow_ls_ext.
88973 … 0x1701154UL //Access:R DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit…
88974 … 0x1701158UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
88975 … 0x170115cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
88976 …taWidth:0x2 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A…
88977 …164UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is empty in sem_slow_dra_wr.
88978 …8UL //Access:R DataWidth:0x1 // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
88979 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
88982 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
88983 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
88984 … 0x1701200UL //Access:R DataWidth:0x1 // EXT_PAS FIFO Full in sem_slow.
88985 … 0x1701204UL //Access:R DataWidth:0x1 // EXT_STORE IF is full in sem_slow_ls_ext.
88986 …cess:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
88988 … 0x1701244UL //Access:R DataWidth:0x1 // EXT_RAM IF is full in sem_slow_ls_ram.
88989 … 0x1701248UL //Access:R DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg acco…
88990 … 0x170124cUL //Access:R DataWidth:0x1 // DBG FIFO is full in sem_slow_ls_dbg.
88991 … 0x1701250UL //Access:R DataWidth:0x1 // FIN fifo is full in sem_slow_dra_sync (n…
88992 … 0x1701254UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is full in sem_slow_dra_sync.
88993 … 0x1701258UL //Access:R DataWidth:0x1 // DRA_WR push fifo is full in sem_slow_dra_sync.
88994 …cess:R DataWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 …
88995 … 0x1701260UL //Access:R DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit…
88996 … 0x1701264UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
88997 … 0x1701268UL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
88998 … 0x170126cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
88999 …DataWidth:0x2 // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A…
89000 …1274UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
89001 …1278UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
89007 … 0x1701308UL //Access:R DataWidth:0x18 // Threads are sleeping in passive buffer more …
89010 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
89012 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
89013 … 0x1701414UL //Access:R DataWidth:0x1 // DBG IF is full in sem_slow_ls_dbg.
89015 … 0x170141cUL //Access:RW DataWidth:0x5 // In case DebugMode0Confi…
89017 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
89021 …ue (according to passive_buffer_performance_mon_stat value) of the stored threads in the FOC queue.
89022 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 A queue.
89023 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC1 A queue.
89024 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 A queue.
89025 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 A queue.
89026 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 X queue.
89027 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 X queue.
89028 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 X queue.
89029 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 B queue.
89030 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 B queue.
89031 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 B queue.
89032 … value (according to passive_buffer_performance_mon_stat value) of allocated threads in the system.
89033 …ng for ready indication to be run on Storm. Note -this statistic does not include the threads pend…
89039 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
89043 … 0x1708000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
89049 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
89054 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89055 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89108 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
89119 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
89122 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
89124 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
89126 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
89128 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
89130 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
89133 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
89135 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
89137 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
89139 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89142 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
89144 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
89146 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
89148 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89178 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89180 … (0x1<<3) // Error in any one of the FIC F…
89186 …R_A_E5 (0x1<<6) // Error in external store slow …
89188 …R_B_E5 (0x1<<7) // Error in external store slow …
89190 …R_A_E5 (0x1<<8) // Error in external load sync s…
89192 …R_B_E5 (0x1<<9) // Error in external load sync s…
89194 …R_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
89196 … (0x1<<10) // Error in slow LS_SYNC_POP FIF…
89198 …R_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
89200 …5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
89202 … (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
89204 … (0x1<<13) // Error in slow LS_SYNC_POP FIF…
89206 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89208 … (0x1<<15) // Error detected in the ext Stroe interf…
89212 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
89214 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
89220 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
89222 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
89240 …2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
89242 …2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
89244 …BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
89246 …B_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
89248 …BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
89250 …B_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
89252 …2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
89254 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89256 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
89258 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
89260 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
89262 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
89264 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
89268 …R_BB_K2 (0x1<<18) // Error in external store sync …
89270 …_BB_K2 (0x1<<19) // Error in external store sync …
89272 …_BB_K2 (0x1<<20) // Error in external load sync F…
89274 …BB_K2 (0x1<<21) // Error in external load sync F…
89276 …R_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
89278 …R_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
89280 …B_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
89282 …B_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
89284 …2 (0x1<<28) // Error in slow debug fifo.
89286 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
89288 … (0x1<<30) // Error interrupt in VFC block.
89290 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
89416 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89418 … (0x1<<3) // Error in any one of the FIC F…
89424 …RROR_A_E5 (0x1<<6) // Error in external store slow …
89426 …RROR_B_E5 (0x1<<7) // Error in external store slow …
89428 …RROR_A_E5 (0x1<<8) // Error in external load sync s…
89430 …RROR_B_E5 (0x1<<9) // Error in external load sync s…
89432 …RROR_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
89434 …_E5 (0x1<<10) // Error in slow LS_SYNC_POP FIF…
89436 …RROR_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
89438 …R_E5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
89440 …E5 (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
89442 …E5 (0x1<<13) // Error in slow LS_SYNC_POP FIF…
89444 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89446 … (0x1<<15) // Error detected in the ext Stroe interf…
89450 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
89452 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
89458 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
89460 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
89478 …B_K2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
89480 …B_K2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
89482 …OR_BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
89484 …R_BB_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
89486 …OR_BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
89488 …R_BB_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
89490 …B_K2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
89492 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89494 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
89496 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
89498 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
89500 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
89502 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
89506 …RROR_BB_K2 (0x1<<18) // Error in external store sync …
89508 …ROR_BB_K2 (0x1<<19) // Error in external store sync …
89510 …ROR_BB_K2 (0x1<<20) // Error in external load sync F…
89512 …OR_BB_K2 (0x1<<21) // Error in external load sync F…
89514 …RROR_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
89516 …RROR_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
89518 …R_BB_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
89520 …R_BB_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
89522 …B_K2 (0x1<<28) // Error in slow debug fifo.
89524 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
89526 … (0x1<<30) // Error interrupt in VFC block.
89528 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
89535 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89537 … (0x1<<3) // Error in any one of the FIC F…
89543 …ERROR_A_E5 (0x1<<6) // Error in external store slow …
89545 …ERROR_B_E5 (0x1<<7) // Error in external store slow …
89547 …ERROR_A_E5 (0x1<<8) // Error in external load sync s…
89549 …ERROR_B_E5 (0x1<<9) // Error in external load sync s…
89551 …ERROR_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
89553 …R_E5 (0x1<<10) // Error in slow LS_SYNC_POP FIF…
89555 …ERROR_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
89557 …OR_E5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
89559 …_E5 (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
89561 …_E5 (0x1<<13) // Error in slow LS_SYNC_POP FIF…
89563 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89565 … (0x1<<15) // Error detected in the ext Stroe interf…
89569 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
89571 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
89577 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
89579 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
89597 …BB_K2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
89599 …BB_K2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
89601 …ROR_BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
89603 …OR_BB_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
89605 …ROR_BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
89607 …OR_BB_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
89609 …BB_K2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
89611 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89613 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
89615 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
89617 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
89619 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
89621 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
89625 …ERROR_BB_K2 (0x1<<18) // Error in external store sync …
89627 …RROR_BB_K2 (0x1<<19) // Error in external store sync …
89629 …RROR_BB_K2 (0x1<<20) // Error in external load sync F…
89631 …ROR_BB_K2 (0x1<<21) // Error in external load sync F…
89633 …ERROR_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
89635 …ERROR_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
89637 …OR_BB_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
89639 …OR_BB_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
89641 …BB_K2 (0x1<<28) // Error in slow debug fifo.
89643 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
89645 … (0x1<<30) // Error interrupt in VFC block.
89647 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
89702 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
89704 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
89706 … (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
89708 … (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
89710 … (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
89712 … (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
89714 … (0x1<<0) // An underflow error was detected in the Storm stack.
89716 … (0x1<<1) // An overflow error was detected in the Storm stack.
89722 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89724 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89728 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89730 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
89734 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
89738 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
89884 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
89886 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
89888 … (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
89890 … (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
89892 … (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
89894 … (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
89896 … (0x1<<0) // An underflow error was detected in the Storm stack.
89898 … (0x1<<1) // An overflow error was detected in the Storm stack.
89904 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89906 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89910 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89912 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
89916 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
89920 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
89975 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
89977 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
89979 …5 (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
89981 …5 (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
89983 …5 (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
89985 …5 (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
89987 … (0x1<<0) // An underflow error was detected in the Storm stack.
89989 … (0x1<<1) // An overflow error was detected in the Storm stack.
89995 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89997 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
90001 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90003 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
90007 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
90011 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
90022 … (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
90024 … (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
90030 …_A_E5 (0x1<<8) // Error in FOC error of Storm A.
90032 …_B_E5 (0x1<<9) // Error in FOC error of Storm B.
90040 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90042 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90148 …E5 (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
90150 …E5 (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
90156 …ROR_A_E5 (0x1<<8) // Error in FOC error of Storm A.
90158 …ROR_B_E5 (0x1<<9) // Error in FOC error of Storm B.
90166 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90168 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90211 …_E5 (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
90213 …_E5 (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
90219 …RROR_A_E5 (0x1<<8) // Error in FOC error of Storm A.
90221 …RROR_B_E5 (0x1<<9) // Error in FOC error of Storm B.
90229 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90231 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90322 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_0 in module sem_pb_pas_bu…
90324 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_1 in module sem_pb_pas_bu…
90326 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_2 in module sem_pb_pas_bu…
90328 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_3 in module sem_pb_pas_bu…
90330 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_4 in module sem_pb_pas_bu…
90332 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_5 in module sem_pb_pas_bu…
90334 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_6 in module sem_pb_pas_bu…
90336 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_7 in module sem_pb_pas_bu…
90339 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_0 in module sem_pb_pas_bu…
90341 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_1 in module sem_pb_pas_bu…
90343 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_2 in module sem_pb_pas_bu…
90345 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_3 in module sem_pb_pas_bu…
90347 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_4 in module sem_pb_pas_bu…
90349 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_5 in module sem_pb_pas_bu…
90351 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_6 in module sem_pb_pas_bu…
90353 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_7 in module sem_pb_pas_bu…
90356 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_0 in module sem_pb_pas_bu…
90358 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_1 in module sem_pb_pas_bu…
90360 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_2 in module sem_pb_pas_bu…
90362 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_3 in module sem_pb_pas_bu…
90364 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_4 in module sem_pb_pas_bu…
90366 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_5 in module sem_pb_pas_bu…
90368 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_6 in module sem_pb_pas_bu…
90370 …_sem_passive_buffer.i_sem_pb_pas_buf_ram_wrap.i_sem_pb_pas_buf_ram.i_ecc_7 in module sem_pb_pas_bu…
90373 … 0x1800400UL //Access:RW DataWidth:0x5 // The number of time_slots in the arbitration cycl…
90374 … 0x1800408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
90375 … 0x180040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
90376 … 0x1800420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
90379 … 0x1800440UL //Access:R DataWidth:0x10 // This read-only register provide…
90381 …e handler in the event that the PRAM address retrieved from the interrupt table is out of range wi…
90382 … 0x180044cUL //Access:R DataWidth:0x6 // Number of free entries in the external STORE s…
90386 …x1 // When set, this bit is used to allow low-power mode to be activated while threads are slee…
90387 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
90388 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
90389 …in which write to a thread address section passive buffer may occur simultaneously with read (as l…
90393 …0600UL //Access:RW DataWidth:0x6 // Per-FIC interface register array defines minimum number o…
90394 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
90395 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
90398 …transaction. The transfer will stall only when a transfer cycle is reached in which there are no i…
90399 …_R DataWidth:0x164 // Last fin command that was read from fifo. Its spelling in FIN_FIFO register.
90401 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
90404 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90405 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90407 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
90409 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
90411 …800b00UL //Access:R DataWidth:0x6 // The number of currently free threads (in invalid state).
90412 …0x1800b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
90418 …800b18UL //Access:RW DataWidth:0x6 // Defines the maixmum number of supported threads in SEMI.
90419 …1800b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
90420 …red for the FOC transfer to start. The values define in this register represents the number of Qua…
90422 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
90426 … 0x1800d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
90428 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
90430 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
90431 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
90434 … 0x1801004UL //Access:RW DataWidth:0x5 // The number of free entries in the sync FIFO betwee…
90435 …01008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DRA WR FIFO credit (in SEM_PD_CORE).
90441 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
90442 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 A queue. If FIC…
90443 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 X queue. If FIC…
90444 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 B queue. If FIC…
90445 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC1 A queue. If FIC…
90446 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
90448 … 0x1801104UL //Access:R DataWidth:0x1 // EXT_PAS FIFO empty in sem_slow.
90449 …ess:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
90450 … 0x1801140UL //Access:R DataWidth:0x1 // DBG FIFO is empty in sem_slow_ls_dbg.
90451 … 0x1801144UL //Access:R DataWidth:0x1 // FIN fifo is empty in sem_slow_dra_sync.
90452 … 0x1801148UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is empty in sem_slow_dra_sync.
90453 … 0x180114cUL //Access:R DataWidth:0x1 // DRA_WR push fifo is empty in sem_slow_dra_sync.
90454 … 0x1801150UL //Access:R DataWidth:0x2 // EXT_STORE FIFO is empty in sem_slow_ls_ext.
90455 … 0x1801154UL //Access:R DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit…
90456 … 0x1801158UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
90457 … 0x180115cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
90458 …taWidth:0x2 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A…
90459 …164UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is empty in sem_slow_dra_wr.
90460 …8UL //Access:R DataWidth:0x1 // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
90461 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
90464 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
90465 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
90466 … 0x1801200UL //Access:R DataWidth:0x1 // EXT_PAS FIFO Full in sem_slow.
90467 … 0x1801204UL //Access:R DataWidth:0x1 // EXT_STORE IF is full in sem_slow_ls_ext.
90468 …cess:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
90470 … 0x1801244UL //Access:R DataWidth:0x1 // EXT_RAM IF is full in sem_slow_ls_ram.
90471 … 0x1801248UL //Access:R DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg acco…
90472 … 0x180124cUL //Access:R DataWidth:0x1 // DBG FIFO is full in sem_slow_ls_dbg.
90473 … 0x1801250UL //Access:R DataWidth:0x1 // FIN fifo is full in sem_slow_dra_sync (n…
90474 … 0x1801254UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is full in sem_slow_dra_sync.
90475 … 0x1801258UL //Access:R DataWidth:0x1 // DRA_WR push fifo is full in sem_slow_dra_sync.
90476 …cess:R DataWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 …
90477 … 0x1801260UL //Access:R DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit…
90478 … 0x1801264UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
90479 … 0x1801268UL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
90480 … 0x180126cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
90481 …DataWidth:0x2 // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A…
90482 …1274UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
90483 …1278UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
90489 … 0x1801308UL //Access:R DataWidth:0x18 // Threads are sleeping in passive buffer more …
90492 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
90494 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
90495 … 0x1801414UL //Access:R DataWidth:0x1 // DBG IF is full in sem_slow_ls_dbg.
90497 … 0x180141cUL //Access:RW DataWidth:0x5 // In case DebugMode0Confi…
90499 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
90503 …ue (according to passive_buffer_performance_mon_stat value) of the stored threads in the FOC queue.
90504 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 A queue.
90505 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC1 A queue.
90506 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 A queue.
90507 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 A queue.
90508 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 X queue.
90509 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 X queue.
90510 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 X queue.
90511 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 B queue.
90512 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 B queue.
90513 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 B queue.
90514 … value (according to passive_buffer_performance_mon_stat value) of allocated threads in the system.
90515 …ng for ready indication to be run on Storm. Note -this statistic does not include the threads pend…
90521 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
90525 … 0x1808000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
90531 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
90536 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90537 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90591 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
90602 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
90605 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
90607 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
90609 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
90611 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
90613 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
90616 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
90618 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
90620 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
90622 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90625 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
90627 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
90629 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
90631 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90661 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90663 … (0x1<<3) // Error in any one of the FIC F…
90669 …R_A_E5 (0x1<<6) // Error in external store slow …
90671 …R_B_E5 (0x1<<7) // Error in external store slow …
90673 …R_A_E5 (0x1<<8) // Error in external load sync s…
90675 …R_B_E5 (0x1<<9) // Error in external load sync s…
90677 …R_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
90679 … (0x1<<10) // Error in slow LS_SYNC_POP FIF…
90681 …R_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
90683 …5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
90685 … (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
90687 … (0x1<<13) // Error in slow LS_SYNC_POP FIF…
90689 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90691 … (0x1<<15) // Error detected in the ext Stroe interf…
90695 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
90697 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
90703 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
90705 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
90723 …2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
90725 …2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
90727 …BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
90729 …B_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
90731 …BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
90733 …B_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
90735 …2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
90737 … (0x1<<11) // Signals an unknown address in the fast-memory window.
90739 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
90741 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
90743 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
90745 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
90747 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
90751 …R_BB_K2 (0x1<<18) // Error in external store sync …
90753 …_BB_K2 (0x1<<19) // Error in external store sync …
90755 …_BB_K2 (0x1<<20) // Error in external load sync F…
90757 …BB_K2 (0x1<<21) // Error in external load sync F…
90759 …R_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
90761 …R_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
90763 …B_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
90765 …B_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
90767 …2 (0x1<<28) // Error in slow debug fifo.
90769 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
90771 … (0x1<<30) // Error interrupt in VFC block.
90773 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
90899 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90901 … (0x1<<3) // Error in any one of the FIC F…
90907 …RROR_A_E5 (0x1<<6) // Error in external store slow …
90909 …RROR_B_E5 (0x1<<7) // Error in external store slow …
90911 …RROR_A_E5 (0x1<<8) // Error in external load sync s…
90913 …RROR_B_E5 (0x1<<9) // Error in external load sync s…
90915 …RROR_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
90917 …_E5 (0x1<<10) // Error in slow LS_SYNC_POP FIF…
90919 …RROR_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
90921 …R_E5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
90923 …E5 (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
90925 …E5 (0x1<<13) // Error in slow LS_SYNC_POP FIF…
90927 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90929 … (0x1<<15) // Error detected in the ext Stroe interf…
90933 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
90935 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
90941 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
90943 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
90961 …B_K2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
90963 …B_K2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
90965 …OR_BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
90967 …R_BB_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
90969 …OR_BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
90971 …R_BB_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
90973 …B_K2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
90975 … (0x1<<11) // Signals an unknown address in the fast-memory window.
90977 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
90979 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
90981 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
90983 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
90985 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
90989 …RROR_BB_K2 (0x1<<18) // Error in external store sync …
90991 …ROR_BB_K2 (0x1<<19) // Error in external store sync …
90993 …ROR_BB_K2 (0x1<<20) // Error in external load sync F…
90995 …OR_BB_K2 (0x1<<21) // Error in external load sync F…
90997 …RROR_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
90999 …RROR_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
91001 …R_BB_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
91003 …R_BB_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
91005 …B_K2 (0x1<<28) // Error in slow debug fifo.
91007 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
91009 … (0x1<<30) // Error interrupt in VFC block.
91011 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
91018 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
91020 … (0x1<<3) // Error in any one of the FIC F…
91026 …ERROR_A_E5 (0x1<<6) // Error in external store slow …
91028 …ERROR_B_E5 (0x1<<7) // Error in external store slow …
91030 …ERROR_A_E5 (0x1<<8) // Error in external load sync s…
91032 …ERROR_B_E5 (0x1<<9) // Error in external load sync s…
91034 …ERROR_BB_K2 (0x1<<23) // Error in LS_SYNC_POP FIFO.
91036 …R_E5 (0x1<<10) // Error in slow LS_SYNC_POP FIF…
91038 …ERROR_BB_K2 (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
91040 …OR_E5 (0x1<<11) // Error in slow LS_SYNC_PUSH FI…
91042 …_E5 (0x1<<12) // Error in slow LS_SYNC_PUSH FI…
91044 …_E5 (0x1<<13) // Error in slow LS_SYNC_POP FIF…
91046 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91048 … (0x1<<15) // Error detected in the ext Stroe interf…
91052 … (0x1<<17) // Indicates that the Storm requested an external load transfer in which the length was…
91054 … Passive Buffer State machine has unexpectedly received a ready indication in the following cases:…
91060 … (0x1<<21) // Marks that the indirect register of MOVRIND is located in the storm bar region.
91062 … (0x1<<22) // Marks that the indirect register of MOVRIND is located in the storm bar region.
91080 …BB_K2 (0x1<<4) // Error in Ext PAS_FIFO is acti…
91082 …BB_K2 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIF…
91084 …ROR_BB_K2 (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIF…
91086 …OR_BB_K2 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO…
91088 …ROR_BB_K2 (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIF…
91090 …OR_BB_K2 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO…
91092 …BB_K2 (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO i…
91094 … (0x1<<11) // Signals an unknown address in the fast-memory window.
91096 … (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
91098 … (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
91100 … (0x1<<14) // Error in CAM_OUT fifo in cam block.
91102 … (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast bl…
91104 … (0x1<<16) // Error in thread fifo in sem_slow_dra…
91108 …ERROR_BB_K2 (0x1<<18) // Error in external store sync …
91110 …RROR_BB_K2 (0x1<<19) // Error in external store sync …
91112 …RROR_BB_K2 (0x1<<20) // Error in external load sync F…
91114 …ROR_BB_K2 (0x1<<21) // Error in external load sync F…
91116 …ERROR_BB_K2 (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
91118 …ERROR_BB_K2 (0x1<<24) // Error in LS_SYNC_POP FIFO.
91120 …OR_BB_K2 (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
91122 …OR_BB_K2 (0x1<<27) // Error in LS_SYNC_POP FIFO.
91124 …BB_K2 (0x1<<28) // Error in slow debug fifo.
91126 … (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
91128 … (0x1<<30) // Error interrupt in VFC block.
91130 … (0x1<<31) // Error interrupt in output VFC FIFO insi…
91185 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
91187 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
91189 … (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
91191 … (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
91193 … (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
91195 … (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
91197 … (0x1<<0) // An underflow error was detected in the Storm stack.
91199 … (0x1<<1) // An overflow error was detected in the Storm stack.
91205 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91207 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91211 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91213 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
91217 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
91221 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91367 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
91369 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
91371 … (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
91373 … (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
91375 … (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
91377 … (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
91379 … (0x1<<0) // An underflow error was detected in the Storm stack.
91381 … (0x1<<1) // An overflow error was detected in the Storm stack.
91387 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91389 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91393 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91395 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
91399 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
91403 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91458 … (0x1<<26) // Error in CAM_OUT fifo in cam block of…
91460 … (0x1<<27) // Error in CAM_OUT fifo in cam block of…
91462 …5 (0x1<<28) // Error in CAM_MSB_INP fifo in cam block …
91464 …5 (0x1<<29) // Error in CAM_MSB_INP fifo in cam block …
91466 …5 (0x1<<30) // Error in CAM_LSB_INP fifo in cam block …
91468 …5 (0x1<<31) // Error in CAM_LSB_INP fifo in cam block …
91470 … (0x1<<0) // An underflow error was detected in the Storm stack.
91472 … (0x1<<1) // An overflow error was detected in the Storm stack.
91478 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91480 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91484 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91486 … (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of…
91490 … (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was…
91494 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91505 … (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
91507 … (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
91513 …_A_E5 (0x1<<8) // Error in FOC error of Storm A.
91515 …_B_E5 (0x1<<9) // Error in FOC error of Storm B.
91523 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91525 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91631 …E5 (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
91633 …E5 (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
91639 …ROR_A_E5 (0x1<<8) // Error in FOC error of Storm A.
91641 …ROR_B_E5 (0x1<<9) // Error in FOC error of Storm B.
91649 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91651 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91694 …_E5 (0x1<<4) // Error in CAM_MSB_INP fifo in cam block …
91696 …_E5 (0x1<<5) // Error in CAM_MSB_INP fifo in cam block …
91702 …RROR_A_E5 (0x1<<8) // Error in FOC error of Storm A.
91704 …RROR_B_E5 (0x1<<9) // Error in FOC error of Storm B.
91712 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91714 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91777 …s_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_0 in module sem_slow_pas_…
91779 …s_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_1 in module sem_slow_pas_…
91782 …s_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_0 in module sem_slow_pas_…
91784 …s_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_1 in module sem_slow_pas_…
91787 …s_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_0 in module sem_slow_pas_…
91789 …s_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_1 in module sem_slow_pas_…
91792 … 0x1900400UL //Access:RW DataWidth:0x5 // The number of time_slots in the arbitration cycl…
91793 … 0x1900408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
91794 … 0x190040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
91795 … 0x1900420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
91798 … 0x1900440UL //Access:R DataWidth:0x10 // This read-only register provide…
91800 …e handler in the event that the PRAM address retrieved from the interrupt table is out of range wi…
91801 … 0x190044cUL //Access:R DataWidth:0x6 // Number of free entries in the external STORE s…
91805 …x1 // When set, this bit is used to allow low-power mode to be activated while threads are slee…
91806 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
91807 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
91808 …in which write to a thread address section passive buffer may occur simultaneously with read (as l…
91812 …0600UL //Access:RW DataWidth:0x6 // Per-FIC interface register array defines minimum number o…
91813 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
91814 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
91817 …transaction. The transfer will stall only when a transfer cycle is reached in which there are no i…
91818 …_R DataWidth:0x164 // Last fin command that was read from fifo. Its spelling in FIN_FIFO register.
91820 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
91823 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91824 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91826 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
91828 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
91830 …900b00UL //Access:R DataWidth:0x6 // The number of currently free threads (in invalid state).
91831 …0x1900b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
91837 …900b18UL //Access:RW DataWidth:0x6 // Defines the maixmum number of supported threads in SEMI.
91838 …1900b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
91839 …red for the FOC transfer to start. The values define in this register represents the number of Qua…
91841 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
91845 … 0x1900d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
91847 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
91849 …L //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue pop-enable vector.
91850 … //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue wake-enable vector.
91853 … 0x1901004UL //Access:RW DataWidth:0x5 // The number of free entries in the sync FIFO betwee…
91854 …01008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DRA WR FIFO credit (in SEM_PD_CORE).
91860 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
91861 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 A queue. If FIC…
91862 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 X queue. If FIC…
91863 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC0 B queue. If FIC…
91864 …idth:0x6 // Defines the maximum supported threads that may be contained in FIC1 A queue. If FIC…
91865 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
91867 … 0x1901104UL //Access:R DataWidth:0x1 // EXT_PAS FIFO empty in sem_slow.
91868 …ess:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
91869 … 0x1901140UL //Access:R DataWidth:0x1 // DBG FIFO is empty in sem_slow_ls_dbg.
91870 … 0x1901144UL //Access:R DataWidth:0x1 // FIN fifo is empty in sem_slow_dra_sync.
91871 … 0x1901148UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is empty in sem_slow_dra_sync.
91872 … 0x190114cUL //Access:R DataWidth:0x1 // DRA_WR push fifo is empty in sem_slow_dra_sync.
91873 … 0x1901150UL //Access:R DataWidth:0x2 // EXT_STORE FIFO is empty in sem_slow_ls_ext.
91874 … 0x1901154UL //Access:R DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit…
91875 … 0x1901158UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
91876 … 0x190115cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
91877 …taWidth:0x2 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A…
91878 …164UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is empty in sem_slow_dra_wr.
91879 …8UL //Access:R DataWidth:0x1 // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
91880 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
91883 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
91884 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
91885 … 0x1901200UL //Access:R DataWidth:0x1 // EXT_PAS FIFO Full in sem_slow.
91886 … 0x1901204UL //Access:R DataWidth:0x1 // EXT_STORE IF is full in sem_slow_ls_ext.
91887 …cess:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
91889 … 0x1901244UL //Access:R DataWidth:0x1 // EXT_RAM IF is full in sem_slow_ls_ram.
91890 … 0x1901248UL //Access:R DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg acco…
91891 … 0x190124cUL //Access:R DataWidth:0x1 // DBG FIFO is full in sem_slow_ls_dbg.
91892 … 0x1901250UL //Access:R DataWidth:0x1 // FIN fifo is full in sem_slow_dra_sync (n…
91893 … 0x1901254UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is full in sem_slow_dra_sync.
91894 … 0x1901258UL //Access:R DataWidth:0x1 // DRA_WR push fifo is full in sem_slow_dra_sync.
91895 …cess:R DataWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 …
91896 … 0x1901260UL //Access:R DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit…
91897 … 0x1901264UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
91898 … 0x1901268UL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
91899 … 0x190126cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
91900 …DataWidth:0x2 // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A…
91901 …1274UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
91902 …1278UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
91908 … 0x1901308UL //Access:R DataWidth:0x10 // Threads are sleeping in passive buffer more …
91911 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
91913 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
91914 … 0x1901414UL //Access:R DataWidth:0x1 // DBG IF is full in sem_slow_ls_dbg.
91916 … 0x190141cUL //Access:RW DataWidth:0x5 // In case DebugMode0Confi…
91918 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
91922 …ue (according to passive_buffer_performance_mon_stat value) of the stored threads in the FOC queue.
91923 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 A queue.
91924 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC1 A queue.
91925 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 A queue.
91926 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 A queue.
91927 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 X queue.
91928 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 X queue.
91929 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 X queue.
91930 …(according to passive_buffer_performance_mon_stat value) of the stored threads in the FIC0 B queue.
91931 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO0 B queue.
91932 …according to passive_buffer_performance_mon_stat value) of the stored threads in the PRIO1 B queue.
91933 … value (according to passive_buffer_performance_mon_stat value) of allocated threads in the system.
91934 …ng for ready indication to be run on Storm. Note -this statistic does not include the threads pend…
91940 …abling dword (128bit line) / qword (256bit line) in the selected line (b…
91944 … 0x1908000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the ex…
91950 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
91955 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
91956 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…