Lines Matching full:rbc
10295 …f an independent stall source. This is the first of three provided via the RBC. The value written …
10296 … an independent stall source. This is the second of three provided via the RBC. The value written …
10297 …of an independent stall source. This is the last of three provided via the RBC. The value written …
10313 … ECC error injection the next time there is a write to the internal RAM by RBC. For this, any set …
10338 …ing register assigns bits 31:0 of the CAM mask in preparation for upcoming RBC requested SEARCH an…
10339 …ng register assigns bits 63:31 of the CAM mask in preparation for upcoming RBC requested SEARCH an…
10340 …ng register assigns bits 67:64 of the CAM mask in preparation for upcoming RBC requested SEARCH an…
10341 …ng register assigns bits 31:0 of the CAM value in preparation for upcoming RBC requested SEARCH, A…
10342 …g register assigns bits 63:32 of the CAM value in preparation for upcoming RBC requested SEARCH, A…
10343 …g register assigns bits 67:64 of the CAM value in preparation for upcoming RBC requested SEARCH, A…
10344 … This register delivers the LSB read data from the CAM for the most recent RBC read request issued…
10345 …/ This register delivers middle read data from the CAM for the most recent RBC read request issued…
10346 … This register delivers the MSB read data from the CAM for the most recent RBC read request issued…
10347 …x1 // This register delivers the valid bit from CAM for the most recent RBC read request issued…
10348 …is register delivers CAM search response data from CAM for the most recent RBC search request issu…
10357 …registers returns the 128-bit CAM match vector returned in the most recent RBC-initiaged search re…
10425 … when it was done write to vfc_addr register. New command may be sent from RBC when all 3 bits of …
10437 …ATE, 0x3=READ. Reading this register returns the OpCode of the most recent RBC-initiated CAM reque…
10471 … (0x1<<8) // This is error interrupt. It may be asserted when it was RBC command with addres…
10513 … (0x1<<16) // Indicates if RBC response is ready.
10553 …n set then it disables selecting of commands from STORM. It will allow for RBC to configurate bloc…
10567 … (0xff<<8) // Number of transactions from SEM_PD for last RBC command.
10571 … (0x1<<17) // Ready indication from RBC to input arbiter.
36420 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36429 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36438 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36447 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36456 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36465 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36474 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36483 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36492 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36501 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36510 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36519 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36528 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36537 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36546 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36555 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36564 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36573 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36582 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36591 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36600 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36609 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36618 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36627 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
36638 …ws: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW in…
37840 …ented when tick counter reaches timestamp_tick value. It may be reset from RBC or set to any init …
42249 …ion) priority for the input clients: bits 1:0 PXP input commands. bits 3:2 RBC cleanup. bits 5:4 T…
44728 …e PRM completion message queue. Intended for test/debug purposes. When the RBC read is done at the…
45070 …dth:0x80 // RSS RAM bit enable. It will be used for write operation from RBC. If it equals to 1 …
45075 …rted when RSS got request from RBC that is still not done; B1 is asserted when RSS executed read o…
46177 …/ FOR DBG: enable reading from the hoq ram; when set hoq rbc read is enabled; when reset hoq rbc r…
46201 … 0x24088cUL //Access:W DataWidth:0x1 // Write Only register. RBC write command to th…
49188 …rbc access to PCI config space register 0x78. There are certain flows (like FLR) where 0x78 should…
51450 … SDM command address. This reg is used for sending SDM command through the RBC. See command descri…
51451 …SDM command data lsb. This reg is used for sending SDM command through the RBC. See command descri…
51452 …SDM command data msb. This reg is used for sending SDM command through the RBC. See command descri…
51453 …// SDM command Ready. This reg is used for sending SDM command through the RBC. See command descri…
51454 …// SDM command Ready. This reg is used for sending SDM command through the RBC. See command descri…
51561 …r can clear this bit (through RBC) based on the functional flows (e.g. FLR). It is also possible t…
51591 …TE: this is valid only for rf_qm_ind_rlglblcrd* command (i.e. access the global RL through the RBC)
51629 …OTE: this is valid only for rf_qm_ind_wfqvpcrd* command (i.e. access the global RL through the RBC)
51678 …allowed). (c) Upon Go command and until the init is done (Mem_Init_Ready), RBC access to the mems …
52118 …"12.3.3 Low Level" NOTE : RD/WR to reserved QWORDS will not return an ack causing an RBC timeout!!!
52322 …"12.3.3 Low Level" NOTE : RD/WR to reserved QWORDS will not return an ack causing an RBC timeout!!!
54848 …W DataWidth:0xd // Debug register. It contains address to Big RAM for RBC operations. Value o…
60910 …taWidth:0x108 // Data register for loading debug packet to RX LLH through RBC. The bits are mapp…
63985 …W DataWidth:0xa // Debug register. It contains address to Big RAM for RBC operations. Value o…
71021 …W DataWidth:0xc // Debug register. It contains address to Big RAM for RBC operations. Value o…
73100 …: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; …
73637 …: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; …
74199 …: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; …
74741 …: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; …
75310 …: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; …
75853 …: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; …
76436 … (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen …
76438 … (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen …
76470 … (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen …
76472 … (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen …
76487 … (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen …
76489 … (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen …
77042 … 0x1001800UL //Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base…
78320 … 0x1081800UL //Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base…
79081 … 0x1101440UL //Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base…
80275 … 0x11814c0UL //Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base…
81579 … 0x1201800UL //Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base…
83143 … 0x1281700UL //Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base…