Lines Matching +full:led +full:- +full:7 +full:seg
2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
85 …USE_NUM_E::CHIP_TYPE() fuses, and as enumerated by PCC_PROD_E::CNXXXX. _ <7:0> is typically set …
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
112 …_E5 (0x1<<7) // IDSEL stepping/w…
113 …CIEIP_REG_PCIEEP_CMD_IDS_WCC_E5_SHIFT 7
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
147 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
159 …EG_PCI_TYPE_IDSEL_STEPPING_K2 (0x1<<7) // IDSEL Stepping.
160 …CIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2_SHIFT 7
185 …2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
189 …20 // This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)
204 …PPING_BB (0x1<<7) // Does not apply t…
205 …CIEIP_REG_STATUS_COMMAND_STEPPING_BB_SHIFT 7
210 …s (de-asserted) regardless of any internal chip logic. Setting this bit has no effect on the INT_S…
250 …n Revision ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
252 …ing Interface. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
254 …t Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
256 …t Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
261 … (0xffffff<<8) // The 24-bit Class Code regist…
281 …multifunction. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
290 …ADER_TYPE_BB (0xff<<16) // The 8-bit Header Type regis…
292 … (0xff<<24) // The 8-bit BIST register is used to initiate and report the results o…
297 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
304 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
306 … (0x3<<1) // BAR0 32-bit or 64-bit. Note: The access attributes of this field a…
308 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
310 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
312 …-bit BAR_1 register programs the base address for the memory space mapped by the card onto the PCI…
315 …icate that BAR_1 may be programmed to map this adapter to anywhere in the 64-bit address space. Pa…
317 … (0x1<<3) // This bit indicates that the area mapped by BAR_1 may be pre-fetched or cached by …
319 … (0xfffffff<<4) // These bits set the address within a 32-bit address space tha…
323 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
325 … (0x3<<1) // BAR1 32-bit or 64-bit. Note: The access attributes of this field a…
327 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
329 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
331 … 0x000014UL //Access:RW DataWidth:0x20 // The 32-bit BAR_2 register pr…
335 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
342 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
344 … (0x3<<1) // BAR2 32-bit or 64-bit. Note: The access attributes of this field a…
346 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
348 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
350 …-bit BAR_3 register programs the 2nd base address for the memory space mapped by the card onto the…
353 …icate that BAR_2 may be programmed to map this adapter to anywhere in the 64-bit address space. Pa…
355 … (0x1<<3) // This bit indicates that the area mapped by BAR_2 may be pre-fetched or cached by …
357 … (0xfffffff<<4) // These bits set the address within a 32-bit address space tha…
361 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
363 … (0x3<<1) // BAR3 32-bit or 64-bit. Note: The access attributes of this field a…
365 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
367 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
369 … 0x00001cUL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register pr…
373 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
380 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
382 … (0x3<<1) // BAR4 32-bit or 64-bit. Note: The access attributes of this field a…
384 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
386 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
388 …-bit BAR_5 register programs the 3rd base address for the memory space mapped by the card onto the…
391 …icate that BAR_3 may be programmed to map this adapter to anywhere in the 64-bit address space. Pa…
393 … (0x1<<3) // This bit indicates that the area mapped by BAR_3 may be pre-fetched or cached by …
395 … (0xfffffff<<4) // These bits set the address within a 32-bit address space tha…
399 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
401 … (0x3<<1) // BAR5 32-bit or 64-bit. Note: The access attributes of this field a…
403 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
405 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
407 … 0x000024UL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register pr…
412 … (0xffff<<0) // Subsystem vendor ID. Assigned by PCI-SIG, writable through…
414 … (0xffff<<16) // Subsystem ID. Assigned by PCI-SIG, writable through…
417 …tem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
419 …tem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
422 …VENDOR_ID_BB (0xffff<<0) // The 16-bit Subsystem Vendor …
424 …D_BB (0xffff<<16) // The 16-bit Subsystem ID regi…
432 …<<0) // Expansion ROM Enable. Note: The access attributes of this field are as follows: - Dbi: R
434 …Expansion ROM Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W
436 … 0x000030UL //Access:RW DataWidth:0x20 // The 32-bit Expansion ROM BAR…
449 …ity Structure. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
452 …-bit Capabilities Pointer register specifies an offset in the PCI address space of a linked list o…
466 …egister Field. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
469 …_INT_LINE_BB (0xff<<0) // The 8-bit Interrupt Line re…
471 …_INT_PIN_BB (0xff<<8) // The 8-bit Interrupt Pin reg…
499 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
501 … Spec Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
505 … Return to D0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
507 …alization Bit. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
509 … Requirements. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
511 …State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
513 …State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
515 …tion parameter. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
537 …owever, the read-back value is the actual power state, not the write value. Note: The access attr…
539 …No soft Reset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
556 … (0xff<<0) // The 8-bit Power Management …
558 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
568 …a specific initialization (DSI) sequence following a transition to the D0 un-initialized state. Th…
601 …erted low. This bit is cleared by writing a 1 in this bit position. At power-up, the chip must cle…
610 … Next Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
614 …ssage Capable. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
618 … (0x1<<23) // MSI 64-bit Address Capable. Note: The access attributes of this fiel…
623 … (0xff<<0) // The 8-bit VPD Capability ID…
625 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
629 …// This value is the 32-bit word address of the VPD value being accessed in the vpd_data register.…
631 …bit is used to control passing of data between the vpd_data register and Non-Volatile memory. To r…
634 …essage Lower Address Field. Note: The access attributes of this field are as follows: - Dbi: R/W
638 …-bit MSI Message, this field contains Data. For 64-bit it contains lower 16 bits of the Upper Addr…
640 …is reserved. For 64-bit it contains upper 16 bits of the Upper Address. Note: The access attribut…
643 … (0xff<<0) // The 8-bit MSI Capability ID…
645 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
658 …-bit MSI Message, this field contains Data. For 32-bit, it contains the lower Mask Bits if PVM is …
660 …-bit MSI Message, this field contains Data. For 32-bit, it contains the upper Mask Bits if PVM is …
676 … (0xff<<8) // Next capability pointer. Points to the MSI-X Capabilities by def…
689 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
695 …emented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
697 …essage Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
712 … (0x1<<15) // Role-based error reporting…
718 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core.
721 …ize Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
723 …ons Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
725 …eld Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
727 …table latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
729 …table latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
731 … (0x1<<15) // Role-based Error Reporting Implemented. Note: The access attributes of th…
737 …dpoints only). Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
764 …if we receive any of the errors in PCIEEP_COR_ERR_STAT, for example a replay-timer timeout. Also,…
770 …ests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message shoul…
779 …S_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting…
789 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
791 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
795 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
803 …_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
837 …In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The …
839 …In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The …
841 …ment) Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
843 …- CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1…
845 …- CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1…
847 …er Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
855 …ty Compliance. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
857 …/ Port Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
870 …ES_E5 (0x1<<7) // Extended synch.
871 …CIEIP_REG_PCIEEP_LINK_CTL_ES_E5_SHIFT 7
899 …d Completion Boundary (RCB). Note: The access attributes of this field are as follows: - Dbi: R/W
901 …_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_EN…
903 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
907 …K_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2 (0x1<<7) // Extended Synch.
908 …CIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2_SHIFT 7
909 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
911 …e Autonomous Width Disable. Note: The access attributes of this field are as follows: - Dbi: R/W
913 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
915 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
923 …figuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
925 …Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
929 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
931 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
942 …S_E5 (0x1<<7) // 32-bit AtomicOp supp…
943 …CIEIP_REG_PCIEEP_DEV_CAP2_ATOM32S_E5_SHIFT 7
944 … (0x1<<8) // 64-bit AtomicOp supporte…
946 … (0x1<<9) // 128-bit AtomicOp supporte…
948 … (0x1<<10) // No RO-enabled PR-PR passing. (Thi…
956 …SUPP_E5 (0x1<<16) // 10-bit tag completer sup…
958 …SUPP_E5 (0x1<<17) // 10-bit tag requestor sup…
964 … (0x1<<21) // End-end TLP prefix suppor…
966 … (0x3<<22) // Max end-end TLP prefixes. 0x…
977 …S2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2 (0x1<<7) // 32 Bit AtomicOp …
978 …CIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2_SHIFT 7
983 …R2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
1002 …OM_OP_EB_E5 (0x1<<7) // AtomicOp egress …
1003 …CIEIP_REG_PCIEEP_DEV_CTL2_ATOM_OP_EB_E5_SHIFT 7
1010 …EN_E5 (0x1<<12) // 10-bit tag requester ena…
1014 … (0x1<<15) // End-end TLP prefix blocki…
1017 …/ Completion Timeout Value. Note: The access attributes of this field are as follows: - Dbi: R/W
1025 …VICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2 (0x1<<7) // AtomicOp Egress …
1026 …CIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2_SHIFT 7
1036 …s. _ Bit <2> = 5.0 GT/s. _ Bit <3> = 8.0 GT/s. _ Bit <4> = 16.0 GT/s _ Bits <7:5> are reserved.
1049 …DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1056 …he application must disable hardware from changing the link speed for device-specific reasons othe…
1060 …7) // Transmit margin. This field controls the value of the non-deemphasized voltage level at the …
1061 …CIEIP_REG_PCIEEP_LINK_CTL2_TM_E5_SHIFT 7
1066 …ntry occurred due to the TX compliance receive bit being one. 0x0 = -6 dB. 0x1 = -3.5 dB. When…
1068 …ting at 5 GT/s speed, this bit reflects the level of deemphasis. 0 = -6 dB. 1 = -3.5 dB. The v…
1091 …K_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the conten…
1095 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1097 …EMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
1099 …_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2 (0x7<<7) // Controls Transmi…
1100 …CIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2_SHIFT 7
1101 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1103 … transmission. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1105 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
1107 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
1126 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
1128 …f<<16) // System sw reads this field to determine the MSI-X table size N, which is encoded as N-1 …
1137 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X table into memory s…
1142 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X PBA into memory spa…
1157 …-X vector is used for the interrupt message generated in association with any of the status bits o…
1160 …MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
1164 … (0x7ff<<16) // MSI-X table size encoded as (table size - 1)…
1166 …ctors associated with the function are masked, regardless of their respective per-vector mask bits.
1168 … (0x1<<31) // MSI-X enable. If MSI-X is enabled,…
1170 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
1171 …TRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
1173 … (0xff<<8) // MSI-X Next Capability Pointer. Note: The access attributes of this f…
1175 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
1177 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
1179 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
1205 … (0x7<<0) // MSI-X table BAR indicator register (BIR). Indicates which BAR is u…
1207 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
1209 … 0x0000b4UL //Access:RW DataWidth:0x20 // MSI-X Table Offset and BI…
1210 … (0x7<<0) // MSI-X Table Bar Indicator Register Field. Note: The access attributes of …
1212 … (0x1fffffff<<3) // MSI-X Table Offset. Note: The access attributes of this field …
1217 …L_ERR_REPORT_EN_BB (0x1<<1) // Non-Fatal Error Reporting…
1241 …TAL_ERR_DET_BB (0x1<<17) // Non-Fatal Error Detected.…
1249 … (0x1<<21) // This is bit is read back a 1, whenever a non-posted request initia…
1252 … (0x7<<0) // MSI-X PBA BAR indicator register (BIR). Indicates which BAR is us…
1254 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
1256 … 0x0000b8UL //Access:RW DataWidth:0x20 // MSI-X PBA Offset and BIR …
1257 … (0x7<<0) // MSI-X PBA BIR. Note: The access attributes of this field are…
1259 … (0x1fffffff<<3) // MSI-X PBA Offset. Note: The access attributes of this field a…
1297 …L_LINK_CR_EXT_SYNC_BB (0x1<<7) // Extended Synch. …
1298 …CIEIP_REG_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_BB_SHIFT 7
1317 … (0x1<<28) // Slot Clock configuration. This bit is read-only by host, but rea…
1324 …LOT_POWER_LIMIT_VALUE_BB (0xff<<7) // Not implemented
1325 …CIEIP_REG_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_BB_SHIFT 7
1355 …xt Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1357 …0x7fff<<16) // VPD Address. Note: The access attributes of this field are as follows: - Dbi: R/W
1359 … (0x1<<31) // VPD Flag. Note: The access attributes of this field are as follows: - Dbi: R/W
1387 …EVICE_STATUS_CONTROL_2_UNUSED1_BB (0x1<<7) //
1388 …CIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED1_BB_SHIFT 7
1411 …6) // When link is operating at Gen2 rates, this bit selects the level of de-emphasis. Path= i_cfg…
1413 …L_2_CFG_TX_MARGIN_BB (0x7<<7) // Value used by lo…
1414 …CIEIP_REG_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_BB_SHIFT 7
1425 … (0x1<<17) // Equalization Complete - when set, this indic…
1427 … (0x1<<18) // Equalization Phase 1 Successful - when set, this indic…
1429 … (0x1<<19) // Equalization Phase 2 Successful - when set, this indic…
1431 … (0x1<<20) // Equalization Phase 3 Successful - when set, this indic…
1451 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1453 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1455 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1597 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1603 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1605 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1686 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1692 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1694 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1728 …AT_BDLLPS_E5 (0x1<<7) // Bad DLLP status.
1729 …CIEIP_REG_PCIEEP_COR_ERR_STAT_BDLLPS_E5_SHIFT 7
1745 …FF_BAD_DLLP_STATUS_K2 (0x1<<7) // Bad DLLP Status.
1746 …CIEIP_REG_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_K2_SHIFT 7
1751 …ATAL_ERR_STATUS_K2 (0x1<<13) // Advisory Non-Fatal Error Status.
1764 …AD_DLLP_STATUS_BB (0x1<<7) // Bad DLLP Status.
1765 …CIEIP_REG_CORR_ERR_STATUS_BAD_DLLP_STATUS_BB_SHIFT 7
1779 …MSK_BDLLPM_E5 (0x1<<7) // Bad DLLP mask.
1780 …CIEIP_REG_PCIEEP_COR_ERR_MSK_BDLLPM_E5_SHIFT 7
1796 …BAD_DLLP_MASK_K2 (0x1<<7) // Bad DLLP Mask. …
1797 …CIEIP_REG_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_K2_SHIFT 7
1802 …ERR_MASK_K2 (0x1<<13) // Advisory Non-Fatal Error Mask. N…
1815 …DLLPS_BB (0x1<<7) // Bad DLLP Mask.
1816 …CIEIP_REG_CORR_ERR_MASK_BDLLPS_BB_SHIFT 7
1832 …_CNTRL_CC_E5 (0x1<<7) // ECRC check capab…
1833 …CIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_CC_E5_SHIFT 7
1849 …FF_ECRC_CHECK_CAP_K2 (0x1<<7) // ECRC Check Capab…
1850 …CIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_K2_SHIFT 7
1858 … (0x1f<<0) // First Error Pointer - These bits correspon…
1864 …L_ECRCCAP_BB (0x1<<7) // ECRC Check Capab…
1865 …CIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCCAP_BB_SHIFT 7
1972 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1974 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1976 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1982 …nded VC Count. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1990 …on Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1999 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
2021 …// Reject Snoop Transactions. Note: The access attributes of this field are as follows: - Dbi: R
2023 … (0x3f<<16) // Maximum Time Slots-1 supported. Note: The access attributes of this field ar…
2046 …_VC0_BIT1_K2 (0x7f<<1) // Bits 7:1 of TC to VC Mappin…
2077 … 0x000160UL //Access:R DataWidth:0x20 // The read-back value of this re…
2096 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2098 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2100 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2124 … 0x000174UL //Access:RW DataWidth:0x20 // The read-back value of this re…
2141 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2143 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2145 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2176 … 0x000180UL //Access:R DataWidth:0x20 // The read-only value of this re…
2201 … Allocated PB. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2203 … 0x000184UL //Access:R DataWidth:0x20 // The read-only value of this re…
2204 … (0xffff<<0) // VSEC ID. This field is a vendor-defined ID number tha…
2206 … (0xf<<16) // VSEC Rev. This field is a vendor-defined version numbe…
2208 …uding the PCI Express Enhanced Capability header, the Vendor-Specific header, and the Vendor-Speci…
2228 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2230 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2232 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2279 … (0xf<<16) // Lane 7 downstream port tran…
2281 … (0x7<<20) // Lane 7 downstream port rece…
2283 … (0xf<<24) // Lane 7 upstream port transm…
2285 … (0x7<<28) // Lane 7 upstream port receiv…
2328 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2330 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2332 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2357 …0) // Perform Equalization. Note: The access attributes of this field are as follows: - Dbi: R/W
2359 …n Request Interrupt Enable. Note: The access attributes of this field are as follows: - Dbi: R/W
2382 …tter Preset 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2384 …Preset Hint 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2386 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2388 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2390 …tter Preset 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2392 …Preset Hint 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2394 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2396 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2405 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2406 …itter Preset2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2408 … Preset Hint2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2410 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2412 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2414 …itter Preset3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2416 … Preset Hint3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2418 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2420 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2423 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2424 …itter Preset4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2426 … Preset Hint4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2428 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2430 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2432 …itter Preset5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2434 … Preset Hint5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2436 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2438 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2441 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2442 …itter Preset6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2444 … Preset Hint6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2446 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2448 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2450 …itter Preset7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2452 … Preset Hint7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2454 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2456 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2458 …-only value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP, By default,…
2477 …g with Max snoop latency scale field, this register specifies the maximum no-snoop latency that a …
2483 …ith Max No snoop latency scale field, this register specifies the maximum no-snoop latency that a …
2490 … 0x0001b8UL //Access:RW DataWidth:0x20 // SR-IOV Capability Header…
2491 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2493 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2495 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2497 … 0x0001b8UL //Access:R DataWidth:0x20 // The read-only value of this re…
2507 … 0x0001bcUL //Access:RW DataWidth:0x20 // SR-IOV Capability Regist…
2510 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2528 … 0x0001c0UL //Access:RW DataWidth:0x20 // SR-IOV Control and Statu…
2537 …access attributes of this field are as follows: - Dbi: R/W but read-value is not always same as w…
2539 …c0UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by setti…
2547 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2549 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2575 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2576 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: STATUS_CONTROL_…
2608 … (0xf<<24) // Downstream port 16.0 GT/s transmitter preset 7.
2610 … (0xf<<28) // Upstream port 16.0 GT/s transmitter preset 7.
2613 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register" det…
2615 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register". de…
2640 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2692 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2693 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2695 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2697 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2717 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2718 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2720 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2722 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2742 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2743 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2745 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2747 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2749 …-bit VF_BAR0 register programs the base address for the memory space mapped by the VFs belonging t…
2752 …ate that VF_BAR0 may be programmed to map this adapter to anywhere in the 64-bit address space. Bi…
2754 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR0 may be pre-fetched or cached by …
2758 … (0xfffff<<12) // These bits set the address within a 32-bit address space tha…
2777 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2778 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2780 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2782 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2784 … 0x0001e8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR1 register …
2802 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2803 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2805 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2807 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2809 …-bit VF_BAR2 register programs the base address for the memory space mapped by the VFs belonging t…
2812 …ate that VF_BAR2 may be programmed to map this adapter to anywhere in the 64-bit address space(reg…
2814 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR2 may be pre-fetched or cached by …
2818 … (0xfffff<<12) // These bits set the address within a 32-bit address space tha…
2837 …d to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in th…
2838 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2840 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2842 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2844 … 0x0001f0UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR3 register …
2867 …-bit VF_BAR4 register programs the base address for the memory space mapped by the VFs belonging t…
2870 …ate that VF_BAR4 may be programmed to map this adapter to anywhere in the 64-bit address space(reg…
2872 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR4 may be pre-fetched or cached by …
2876 … (0xfffff<<12) // These bits set the address within a 32-bit address space tha…
2896 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2898 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2900 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2902 … 0x0001f8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR5 register …
2923 …ode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2925 …ode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2927 …ter Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2929 …ocation Bit 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2931 …ocation Bit 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2933 …ST Table Size. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2953 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
2957 … 0x000200UL //Access:R DataWidth:0x20 // The read-only value of this re…
2982 … 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
2984 … 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
3049 … 0x000210UL //Access:R DataWidth:0x20 // The read-only value of this re…
3127 … 0x000220UL //Access:R DataWidth:0x20 // The read-only value of this re…
3139 …5 (0x1<<2) // VF 10-bit tag requester sup…
3152 …APABILITY_BB (0x1<<7) // when Set, it ind…
3153 …CIEIP_REG_RBAR_CAP_SIZE_8M_CAPABILITY_BB_SHIFT 7
3179 … (0x1<<4) // ARI capable hierarchy. 0 = All PFs have non-ARI capable hierarchy…
3181 …5 (0x1<<5) // VF 10-bit Tag Requester Ena…
3197 … (0xffff<<16) // Total VFs. Read-only copy of PCIEEP_S…
3204 … 0x000230UL //Access:R DataWidth:0x20 // The read-only value of this re…
3212 …-ARI capable hierarchies. The PCIEEP_SRIOV_CTL[ACH] determines which one is being used for SR-IOV…
3214 …-ARI: 0x1. There are two VF stride registers; one for each ARI capable and non-ARI capable…
3231 …ware reads this field to determine the STTable Size N, whihc is encoded as N-1. So a returned valu…
3245 …-only value of this register is controlled by setting bit 2 of the EXT2_CAP_ENA for EP, By default…
3255 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3274 … (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
3307 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3324 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3356 … (0x7ff<<16) // ST table size (limited by MSI-X table size).
3369 …d Capacity ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3371 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3373 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3375 … 0x000288UL //Access:RW DataWidth:0x20 // LTR Max Snoop and No-Snoop Latency Registe…
3380 …T_K2 (0x3ff<<16) // Max No-Snoop Latency Value.
3382 …LAT_SCALE_K2 (0x7<<26) // Max No-Snoop Latency Scale.
3384 … 0x00028cUL //Access:RW DataWidth:0x20 // Vendor-Specific Extended Cap…
3385 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3387 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3389 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3391 … 0x000290UL //Access:R DataWidth:0x20 // Vendor-Specific Header.
3398 …- Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register det…
3399 …ear' code. The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11:…
3401 …ays '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no…
3403 …7) // Event Counter Status. This register returns the current value of the Event Counter selected …
3404 …CIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_K2_SHIFT 7
3405 …a returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - ..…
3407 …- 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the Group For e…
3409 …s the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTRO…
3410 …idth:0x20 // Time-based Analysis Control. Used for controlling the measurement of RX/TX data thr…
3411 … (0x1<<0) // Timer Start. - 0: Start/Restart - 1: Stop Th…
3413 …-based Duration Select. Selects the duration of time-based analysis. When "manual control" is sele…
3415 …-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_…
3417 …ataWidth:0x20 // Time-based Analysis Data. Contains the measurement results of RX/TX data throug…
3418 …- 0: CRC Error: EINJ0_CRC_REG - 1: Sequence Number Error: EINJ1_SEQNUM_REG - 2: DLLP Error: EINJ…
3433 …- LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link …
3434 …have been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE…
3436 …- 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b:…
3438 …- ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 409…
3439 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE …
3441 …nce number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - …
3443 …-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. …
3445 …- If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the trans…
3446 … being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABL…
3448 … inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block …
3450 …- If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeo…
3451 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE …
3453 …- Mask K symbol. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set)…
3455 … - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Po…
3456 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE …
3458 …-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Po…
3462 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is repr…
3464 … - For Duplicate TLP, the core initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These …
3465 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE …
3467 …Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as N…
3469 …sider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], T…
3470 …sider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], T…
3471 …sider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], T…
3472 …sider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], T…
3473 …sider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], T…
3481 …sider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], T…
3513 …sider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], T…
3519 …sider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], T…
3527 …sider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], T…
3533 … (0x3ff<<16) // Max no-snoop latency value.
3535 … (0x7<<26) // Max no-snoop latency scale.
3537 …sider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], T…
3545 …sider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], T…
3546 … 0x000300UL //Access:R DataWidth:0x20 // The read-only value of this re…
3554 …PCIPM_SUP_E5 (0x1<<0) // PCI-PM L12 supported.
3556 …PCIPM_SUP_E5 (0x1<<1) // PCI-PM L11 supported.
3570 …sider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], T…
3577 …1_2_PCIPM_EN_E5 (0x1<<0) // PCI-PM L12 enable.
3579 …1_1_PCIPM_EN_E5 (0x1<<1) // PCI-PM L11 enable.
3589 …s. 0x2 = 1024 ns. 0x3 = 32,768 ns. 0x4 = 1,048,575 ns. 0x5 = 33,554,432 ns. 0x6-7 = Reserved.
3591 …sider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], T…
3600 …sider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], T…
3625 …sider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], T…
3656 …sider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], T…
3681 …remote device when all of the following conditions are true. - Using 128b/130b encoding - Inject…
3682 …are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE …
3684 …ror Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EI…
3686 …e TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Pref…
3734 …EV_CNTR_STAT_E5 (0x1<<7) // Event counter st…
3735 …CIEIP_REG_PCIEEP_RAS_EC_CTL_EV_CNTR_STAT_E5_SHIFT 7
3736 …ter data returned in the PCIEEP_RAS_EC_DATA[EV_CNTR_DATA]. 0x0-0x7 = Lane number. 0x8-0xF = Res…
3778 …-based duration select. Selects the duration of time-based analysis. 0x0 = Manual control. Ana…
3780 …EL_E5 (0xff<<24) // Time-based report select. …
3801 …uring LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. -…
3805 …-reset exit. The core selects the greater value between this register and the value defined by the…
3807 …m receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - …
3812 …rts transitioning to Recovery State. This request does not cause a speed change or re-equalization.
3824 … // Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the…
3825 …er for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 …
3840 …- 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When …
3842 …REG_FRAMING_ERR_K2 (0x1<<7) // Framing Error. …
3843 …CIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_K2_SHIFT 7
3848 …-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negoti…
3851 …- 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDL…
3853 …- 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 08h: L1 - 09h: L1_BLOCK_…
3855 … Re-send flag. When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host soft…
3879 … (0x3<<24) // DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 1…
3888 …-FC DLLP. 0x3 = New TLP's ECRC error injection. 0x4 = TLP's FCRC error injection (128b/130b). 0…
3890 …LP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL…
3891 …ort-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data …
3893 …IT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CRE…
3895 …iewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 d…
3897 …TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_D…
3899 …TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value …
3901 …YPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value …
3908 …-assigned sequence numbers. This value is represented by two's complement. 0x0FFF = +4095. 0x0…
3911 …- 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: T…
3913 …FTLP_STATUS_K2 (0x1<<7) // Malformed TLP St…
3914 …CIEIP_REG_SD_STATUS_L3_REG_MFTLP_STATUS_K2_SHIFT 7
3923 …ng - Mask K symbol. 0x0 = Reserved. 0x1 = COM/PAD(TS1 Order Set). 0x2 = COM/PAD(TS2 Order Set)…
3928 …-FC type. Selects the credit type. 0x0 = Posted TLP header credit value control. 0x1 = Non-Pos…
3932 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. The value is rep…
3934 …ng the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ…
3935 …-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] view…
3937 …the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/…
3939 …al Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11:…
3951 … (0x3f<<0) // Force Local Transmitter Pre-cursor. Indicates th…
3955 … (0x3f<<12) // Force Local Transmitter Post-Cursor. Indicates th…
3961 …fficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CUR…
3969 … (0x3f<<0) // Force Remote Transmitter Pre-Cursor. Indicates th…
3973 … (0x3f<<12) // Force Remote Transmitter Post-Cursor. Indicates th…
3975 …ficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CU…
3979 …ed unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_…
3982 …nformation. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x…
3990 …EQ_REJECT_EVENT_K2 (0x1<<7) // EQ Reject Event.…
3991 …CIEIP_REG_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_K2_SHIFT 7
3994 …_K2 (0x3f<<0) // EQ Local Pre-Cursor. Indicates Lo…
3998 …K2 (0x3f<<12) // EQ Local Post-Cursor. Indicates Lo…
4006 …_K2 (0x3f<<0) // EQ Remote Pre-Cursor. Indicates Re…
4010 …K2 (0x3f<<12) // EQ Remote Post-Cursor. Indicates Re…
4023 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4025 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4027 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4039 …for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. …
4055 …mpletion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. …
4068 … 0x000398UL //Access:RW DataWidth:0x20 // Corrected error (1-bit ECC) counter sele…
4071 …) // Enable correctable errors counters. - 1: counters increment when the core detects a correcta…
4073 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4078 … 0x00039cUL //Access:R DataWidth:0x20 // Corrected error (1-bit ECC) counter data…
4081 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4086 … 0x0003a0UL //Access:RW DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) c…
4089 … Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correct…
4091 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4100 …ors into. 0x0 = TLP header. 0x1 = TLP prefix 1st 4-DWORDs. 0x2 = TLP prefix 2nd 4-DWORDs. 0x3…
4102 … 0x0003a4UL //Access:R DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) c…
4105 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4109 …he following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection mod…
4112 … (0x3<<4) // Error injection type: - 0: none - 1: 1-bit - 2: 2-bit
4114 … (0xff<<8) // Error injection count. - 0: errors are inserted in every TLP until you clear ERR…
4119 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4123 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4128 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4132 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4136 …_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are for…
4146 …-reset exit. The core selects the greater value between this register and the value defined by the…
4148 …ing EIOS to, RXELECIDLE assertion at the PHY 0x0 = 40ns. 0x1 = 160ns. 0x2 = 320ns. 0x3 - 640ns.
4168 …cUL //Access:R DataWidth:0x20 // RAM Address where a corrected error (1-bit ECC) has been det…
4169 … (0x7ffffff<<0) // RAM Address where a corrected error (1-bit ECC) has been det…
4171 … (0xf<<28) // RAM index where a corrected error (1-bit ECC) has been det…
4173 … //Access:R DataWidth:0x20 // RAM Address where an uncorrected error (2-bit ECC) has been det…
4174 … (0x7ffffff<<0) // RAM Address where an uncorrected error (2-bit ECC) has been det…
4176 … (0xf<<28) // RAM index where an uncorrected error (2-bit ECC) has been det…
4179 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4181 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4183 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4186 … silicon debug status register of Layer1-PerLane. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. 0x7 …
4201 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4203 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4205 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4207 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4210 …-STP/SDP/IDL token was received and it was not in TLP/DLLP reception. 0x02 = When current token w…
4212 …SSM_FRAMING_ERR_E5 (0x1<<7) // Framing error. …
4213 …CIEIP_REG_PCIEEP_RAS_SD_L1LTSSM_FRAMING_ERR_E5_SHIFT 7
4218 …ualization_done_8GT_data_rate. 0x7 = equalization_done_16GT_data_rate. 0x8-0xF = idle_to_rlock_t…
4223 …s Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT
4225 …s Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT
4228 … 0x17 = L0S_BLOCK_TLP. 0x18 = WAIT_LAST_PMDLLP. 0x19 = WAIT_DSTATE_UPDATE. 0x20-0x1F = Reserved.
4230 …S_L23RDY_WAIT4ALIVE. 0x0F = S_L23RDY_WAIT4IDLE. 0x10 = S_WAIT_LAST_PMDLLP. 0x10-0x1F = Reserved.
4232 …_Status bit. If host software does not clear PME_Status bit for 100ms (+50%/-5%), the DUT resends …
4239 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4241 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4243 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4257 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4259 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4261 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4264 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields determi…
4266 …ith the [CREDIT_SEL_VC], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields determi…
4268 …] viewport-select fields determines that data that is returned by the [CREDIT_DATA0] and [CREDIT_D…
4270 …CREDIT_SEL_VC], [CREDIT_SEL_CREDIT_TYPE], and [CREDIT_SEL_TLP_TYPE] viewport-select fields determi…
4272 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = …
4274 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = …
4277 … (0x1<<0) // PTM Requester Auto Update Enabled - When enabled PTM Req…
4279 … (0x1<<1) // PTM Requester Start Update - When set the PTM Req…
4281 …K2 (0x1<<2) // PTM Fast Timers - Debug mode for PTM T…
4283 … (0xff<<8) // PTM Requester Long Timer - Determines the perio…
4286 …ion request rules. 0x0E = Invalid TLP type. 0x0F = Completion rules. 0x10-0x7E = Reserved. 0x7…
4288 …USL3_MFTLP_STATUS_E5 (0x1<<7) // Malformed TLP st…
4289 …CIEIP_REG_PCIEEP_RAS_SD_STATUSL3_MFTLP_STATUS_E5_SHIFT 7
4291 … (0x1<<0) // PTM Requester Context Valid - Indicate that the Ti…
4293 … (0x1<<1) // PTM Requester Manual Update Allowed - Indicates whether or…
4298 …-lane silicon debug EQ status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] view…
4300 …ct. Setting this field in conjunction with [EQ_LANE_SEL] determines the per-lane silicon debug EQ…
4330 … (0x3f<<0) // Force remote transmitter pre-cursor as selected by…
4351 …TAT1_EQ_REJECT_EVENT_E5 (0x1<<7) // EQ reject event.…
4352 …CIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_REJECT_EVENT_E5_SHIFT 7
4383 … (0x1<<4) // This bit enables the advertisement of bar_1 as a 32-bit address. The valu…
4385 … (0x1<<5) // This bit will force the PCI bus to re-try all cycles to the…
4387 … (0x1<<6) // This bit will force the PCI bus to re-try all cycles to the…
4389 …_DONE_BB (0x1<<7) // This bit will be…
4390 …CIEIP_REG_CONFIG_2_FIRST_CFG_DONE_BB_SHIFT 7
4391 …en this value is non-zero, the Expansion ROM attention must be handled by an internal processor to…
4393 …16) // This bit when set is reflected in bit 3 of bar_1 and indicates that the BAR is pre-fetchable
4399 …t by HARD Reset such that it can be used to detect initial power up if a non-zero value is written…
4439 …from the pm_data register when the DATA_SEL value in the PM_CSR register is 7. This is the power d…
4472 … (0xfff<<0) // PTM Requester TX Latency - Requester Transmit p…
4504 … (0xfff<<0) // PTM Requester RX Latency - Requester Receive pa…
4511 …). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved.
4516 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4518 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4520 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4525 …ot supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved.
4530 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4532 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4534 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4536 … (0x1<<7) // Up to 8MB BAR Supported. Note: The access attributes of this…
4537 …CIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_K2_SHIFT 7
4538 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4540 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4542 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4544 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4546 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4548 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4550 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4552 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4554 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4556 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4558 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4560 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4562 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4564 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4566 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4568 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4578 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4587 …) // BAR Size. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4599 …). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved.
4607 … (0x3<<4) // Error injection type. 0x0 = None. 0x1 = 1-bit. 0x2 = 2-bit. 0x3 = Re…
4609 … 0x0 = errors are injected in every TLP until [ERR_INJ_EN] is cleared. 0x1 - 0xFF = number of err…
4619 …ot supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved.
4623 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4633 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4637 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4642 …the read value of the class_code register of the configuration space. The 24-bit Class Code regist…
4724 … (0x7fffff<<0) // Only bit 0 is currently defined - remote scaled flow c…
4818 …orted resource sizes. PEM advertises the maximum allowable BAR size (512 GB - 0xF_FFFF) when the f…
4835 …ters located at 10h in configuration space is used to map the function's MSI-X table into memory s…
4837 … one of the functions Base address registers to point to the base of the MSI-X table. Value is con…
4847 …ters located at 10h in configuration space is used to map the function's MSI-X PBA into memory spa…
4849 … one of the functions Base address registers to point to the base of the MSI-X PBA Value is contro…
4859 …-zero values indicate some software-defined post-firmware loaded state information or failure code…
4918 … (0x1<<4) // This bit enables the advertisement of bar_3 as a 32-bit address. The valu…
4920 …<5) // This bit when set is reflected in bit 3 of bar_3 and indicates that the BAR is pre-fetchable
4925 … Timeout Ranges Supported. Controls value in same field in the config space 0xF- Ranges A,B,C and D
4951 … (0x1<<4) // This bit enables the advertisement of bar_5 as a 32-bit address. The valu…
4953 …it when set is reflected in bit 3 of bar_5 and indicates that the BAR is pre-fetchable. This regis…
5023 …_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 7. This value is stick…
5035 …_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 7. This value is stick…
5052 … (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
5084 …1_RC_USER_MEM_EN1_BB (0x1<<7) // Enable User Defi…
5085 …CIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_MEM_EN1_BB_SHIFT 7
5096 …2_RC_USER_MEM_EN2_BB (0x1<<7) // Enable User Defi…
5097 …CIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_MEM_EN2_BB_SHIFT 7
5116 … is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. Al…
5129 …SIZE_8M_CAPABILITY_BB (0x1<<7) // when Set, it ind…
5130 …CIEIP_REG_REG_RESIZEBAR_CAP_SIZE_8M_CAPABILITY_BB_SHIFT 7
5163 … (0x1<<4) // This bit enables the advertisement of VF BAR0 as a 64-bit address. The valu…
5165 … when set is reflected in bit 3 of VF BAR0 and indicates that the BAR is pre-fetchable. This regis…
5171 … (0x1<<12) // This bit enables the advertisement of VF BAR2 as a 64-bit address. The valu…
5173 … when set is reflected in bit 3 of VF BAR2 and indicates that the BAR is pre-fetchable. This regis…
5192 …bility structure of PF configuration space is used to map the function's MSI-X table into memory s…
5194 … one of the functions Base address registers to point to the base of the MSI-X table . All the VF'…
5197 …capability structure in PF configuration space is used to map the VF's's MSI-X PBA into memory spa…
5199 …ress contained by one of the functions Base address registers to point to the base of the MSI-X PBA
5209 … (0x1<<4) // This bit enables the advertisement of VF BAR4 as a 64-bit address. The valu…
5211 … when set is reflected in bit 3 of VF BAR4 and indicates that the BAR is pre-fetchable. This regis…
5235 … is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. Al…
5249 …-7, 3-8, and 3-9 of the PCIe 3.0 specification. The limit must reflect the round trip latency from…
5251 …-4, 3-5, and 3-6 of the PCIe 3.0 specification. If there is a change in the payload size or link s…
5267 … (0xff<<0) // Link Number. Not used for endpoint. Not used for M-PCIe. Note: This reg…
5271 …- Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the core to t…
5275 …many clock cycles for the associated completion of a CfgWr to D-state register to go low-power. Th…
5284 …o: 0x0 = 1 ms. 0x1 = 2 ms. 0x2 = 3 ms. 0x3 = 4 ms. 0x4 = 5 ms. 0x5 = 6 ms. 0x6 or 0x7 = 7 ms.
5290 … 0x00070cUL //Access:RW DataWidth:0x20 // Ack Frequency and L0-L1 ASPM Control Regis…
5291 …- 0: Indicates that this Ack frequency control feature is turned off. The core schedules a low-pri…
5293 …-sets that a component can request is 255. The core does not support a value of zero; a value of z…
5295 …-sets that a component can request is 255. This field is only writable (sticky) when all of the fo…
5297 … - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us…
5299 … Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 …
5301 … (0x1<<30) // ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has …
5308 … (0x1<<2) // Loopback enable. Initiate loopback mode as a master. On a 0->1 transition, the PC…
5318 …M_E5 (0x1<<7) // Fast link mode. …
5319 …CIEIP_REG_PCIEEP_PORT_CTL_FLM_E5_SHIFT 7
5335 … the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register fie…
5339 …-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during C…
5347 …7) // Fast Link Mode. Sets all internal timers to Fast Mode for speeding up simulation. Forces the…
5348 …CIEIP_REG_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_K2_SHIFT 7
5351 …". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supp…
5370 … (0xf<<27) // Set the implementation-specific number of la…
5372 … (0x1<<31) // Disable lane-to-lane deskew. Disables the internal lane-t…
5381 … (0x1<<31) // Disable Lane-to-Lane Deskew. Causes the core to disable the intern…
5384 … (0xff<<0) // Max number of functions supported. Used for SR-IOV.
5397 …-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in inc…
5403 …- 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Fa…
5451 …- 0: For RADM RC filter to not allow CFG transaction being received - 1: For RADM RC filter to al…
5468 …_PRS_E5 (0x1<<7) // Mask PRS message…
5469 …CIEIP_REG_PCIEEP_FILT_MSK2_M_PRS_E5_SHIFT 7
5492 … 0x000734UL //Access:R DataWidth:0x20 // Transmit Non-Posted FC Credit Stat…
5493 … (0xfff<<0) // Transmit Non-Posted Data FC Credits. The non-poste…
5495 … (0xff<<12) // Transmit Non-Posted Header FC Credits. The non-post…
5547 …xff<<0) // WRR Weight for VC0. Note: The access attributes of this field are as follows: - Dbi: R
5549 …xff<<8) // WRR Weight for VC1. Note: The access attributes of this field are as follows: - Dbi: R
5551 …ff<<16) // WRR Weight for VC2. Note: The access attributes of this field are as follows: - Dbi: R
5553 …ff<<24) // WRR Weight for VC3. Note: The access attributes of this field are as follows: - Dbi: R
5565 …xff<<0) // WRR Weight for VC4. Note: The access attributes of this field are as follows: - Dbi: R
5567 …xff<<8) // WRR Weight for VC5. Note: The access attributes of this field are as follows: - Dbi: R
5569 …ff<<16) // WRR Weight for VC6. Note: The access attributes of this field are as follows: - Dbi: R
5571 …ff<<24) // WRR Weight for VC7. Note: The access attributes of this field are as follows: - Dbi: R
5580 …-buffer configuration, writable through PEM()_CFG_WR. However, the application must not change thi…
5588 …he TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration,…
5590 …ines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration,…
5592 … 0x000748UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Posted Rec…
5593 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5595 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5603 …ly in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ord…
5605 …eues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs …
5614 …-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at a time: _ Bit 2…
5616 … (0x3<<24) // VC0 scale non-posted header credits.
5618 … (0x3<<26) // VC0 scale non-posted data credits.
5622 … 0x00074cUL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Non-Posted Receive…
5623 …-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segm…
5625 …-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the …
5640 …-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at a time: _ Bit 2…
5648 … 0x000750UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Completion…
5649 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5651 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5674 …_4DW_CHK_BB (0x1<<7) // Target mem Wr sh…
5675 …CIEIP_REG_TL_CONTROL_0_MEMWR_4DW_CHK_BB_SHIFT 7
5700 … (0x1<<21) // When set, it enables WAKE generation in any L-state, when PME_EN bi…
5706 … (0x1<<24) // When set, it prevents PM from re-entering L1 when programmed to non-D0 p…
5735 …E_CHK_BB (0x1<<7) // Enable Check to …
5736 …CIEIP_REG_TL_CONTROL_1_EN_RTE_CHK_BB_SHIFT 7
5755 … (0x1<<17) // This bit is used to disable function 7.
5759 … and not wait for LTR message to be sent first even though device state may have changed to non-D0.
5794 …0_MASK_BB (0x1<<7) // ECRC Error TLP S…
5795 …CIEIP_REG_TL_CONTROL_2_ECRCS0_MASK_BB_SHIFT 7
5845 …0x1 = 1 lane. 0x2 = 2 lanes. 0x3 = 3 lanes. _ ... 0x10 = 16 lanes. 0x11-0x1F = Reserved. Wh…
5847 …0x3 = Connect logical Lane0 to physical lane 7. 0x4 = Connect logical Lane0 to physical lane 15…
5857 … (0x1<<20) // Set the deemphasis level for upstream ports. 0 = -6 dB. 1 = -3.5 dB.
5862 …his field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as…
5864 …- 0x01: 1 lane - 0x02: 2 lanes - 0x03: 3 lanes - .. When you have unused lanes in your system, …
5866 …- 3'b000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8…
5868 …his field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as…
5870 …- Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deas…
5872 …ld. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe. Note: The …
5874 …his field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as…
5876 …-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at…
5878 …core by just detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Id…
5885 …t. When this bit is set, PH credits are not released by IP if FIFO at the DL-TL boundary reaches a…
5887 … (0x1<<3) // Indicates no non-posted credit is avai…
5897 … (0x1<<16) // This bit when set prevents DUT from entering L1 due to being in non-d0 state.
5899 … (0x7fff<<17) // Programmable delay to prevent link from re-entering L1, when lin…
5925 …ECRC_BB (0x1<<7) // This bit is set …
5926 …CIEIP_REG_TL_CTRLSTAT_5_ERR_ECRC_BB_SHIFT 7
5996 …FUNC_15_BB (0x1<<7) // This bit is used…
5997 …CIEIP_REG_TL_CONTROL_6_HIDE_FUNC_15_BB_SHIFT 7
6083 …RCS2_MASK_BB (0x1<<7) // ECRC Error TLP S…
6084 …CIEIP_REG_TL_FUNC345_MASK_ECRCS2_MASK_BB_SHIFT 7
6146 …R_ECRC2_BB (0x1<<7) // This bit is set …
6147 …CIEIP_REG_TL_FUNC345_STAT_ERR_ECRC2_BB_SHIFT 7
6209 …RCS5_MASK_BB (0x1<<7) // ECRC Error TLP S…
6210 …CIEIP_REG_TL_FUNC678_MASK_ECRCS5_MASK_BB_SHIFT 7
6272 …R_ECRC5_BB (0x1<<7) // ECRC Error TLP S…
6273 …CIEIP_REG_TL_FUNC678_STAT_ERR_ECRC5_BB_SHIFT 7
6298 … (0x1<<20) // Poisoned Error Status detected in function 7. If set, hw generate…
6300 … (0x1<<21) // Flow Control Protocol Error Status detected in function 7, if set, generate pc…
6302 … (0x1<<22) // Completer Timeout Status detected in function 7. If set, hw generate…
6304 … (0x1<<23) // Receive UR Status detectedin function 7. If set, generate pc…
6306 … (0x1<<24) // Unexpected Completion Status detected in function 7, if set, generate pc…
6308 … (0x1<<25) // Receiver Overflow Status detected in function 7. If set, hw generate…
6310 … (0x1<<26) // Malformed TLP Status detected in function 7. If set, hw generate…
6312 … (0x1<<27) // ECRC Error TLP Status detected in function 7. If set, hw generate…
6335 … (0x7<<21) // Route the interrupt pin for Function 7 to any of INTA to IN…
6380 …L_OBFF_CTRL_UNUSED0_BB (0x1<<7) //
6381 …CIEIP_REG_TL_OBFF_CTRL_UNUSED0_BB_SHIFT 7
6403 …FUNC_8_HIDDEN_BB (0x1<<7) // Set if func8 is …
6404 …CIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_8_HIDDEN_BB_SHIFT 7
6466 …ECRCS8_MASK_BB (0x1<<7) // ECRC Error TLP S…
6467 …CIEIP_REG_TL_FUNC8TO10_MASK_ECRCS8_MASK_BB_SHIFT 7
6529 …ERR_ECRC8_BB (0x1<<7) // ECRC Error TLP S…
6530 …CIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC8_BB_SHIFT 7
6592 …_ECRCS11_MASK_BB (0x1<<7) // ECRC Error TLP S…
6593 …CIEIP_REG_TL_FUNC11TO13_MASK_ECRCS11_MASK_BB_SHIFT 7
6641 …gating feature when there is no receive traffic, receive queues and pre/post-queue pipelines are e…
6658 …_ERR_ECRC11_BB (0x1<<7) // ECRC Error TLP S…
6659 …CIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC11_BB_SHIFT 7
6707 … (0x1<<0) // Gen3 receiver impedance ZRX-DC not compliant.
6735 …-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is us…
6736 …-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defin…
6740 …Gen4 data rate. Note: The access attributes of this field are as follows: - Dbi: see description…
6746 …-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the…
6748 …- 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. - 1: mac_phy_rxeq…
6773 …_ECRCS14_MASK_BB (0x1<<7) // ECRC Error TLP S…
6774 …CIEIP_REG_TL_FUNC14TO15_MASK_ECRCS14_MASK_BB_SHIFT 7
6816 …_ERR_ECRC14_BB (0x1<<7) // ECRC Error TLP S…
6817 …CIEIP_REG_TL_FUNC14TO15_STAT_ERR_ECRC14_BB_SHIFT 7
6845 … with a data payload of 0xFFFFFFFF. When the MSB of a PF's HIDE_PFn is non-zero, the PF is consi…
6911 … (0xf<<0) // Feedback mode. 0 = Direction of change. 1 = Figure of merit. 2-15 = Reserved.
6919 … Preset 6 req/evaluated in EQ master phase. _ 0b00000xxx1xxxxxxx = Preset 7 req/evaluated in EQ …
6925 … (0x1<<26) // Request core to send back-to-back EIEOS in Recove…
6927 …or Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP). M-PCIe doesn't have Con…
6928 … (0xf<<0) // Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserv…
6930 …- 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found then: …
6932 …Eval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settin…
6934 …- 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: P…
6936 …ter, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include…
6940 … core to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping …
6947 … (0xf<<10) // Convergence window aperture for C-1. Precursor coeffici…
6956 …TA_K2 (0xf<<10) // Convergence Window Aperture for C-1. Pre-cursor coefficient…
6958 …K2 (0xf<<14) // Convergence Window Aperture for C+1. Post-cursor coefficients m…
6961 …-Posted passing posted ordering rule control. Determines if a NP can pass halted P queue. 0x0 = …
6963 …lted P queue. 0x0 = CPL can not pass P (recommended). 0x1 = CPL can pass P. 0x2-0xFF = Reserved.
6966 …<0) // Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue…
6968 … Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1…
6971 … (0xffff<<0) // Loopback rxvalid (lane enable - 1 bit per lane).
6984 … (0x1<<31) // PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This reg…
6989 …error reporting). A completion with UR status will be generated for non-posted requests. 0x1…
6991 …e suppresses error logging, error message generation, and CPL generation (for non-posted requests).
6999 … 0x0008bcUL //Access:RW DataWidth:0x20 // DBI Read-Only Write Enable Reg…
7000 …he local application through the DBI. For more details, see "Writing to Read-Only Registers." Not…
7005 …e or autonomous width downsizing in the configuration state. The core self-clears this field whe…
7007 …C_SUPP_E5 (0x1<<7) // Upconfigure supp…
7008 …CIEIP_REG_PCIEEP_UPCONFIG_UPC_SUPP_E5_SHIFT 7
7009 … 0x0008c0UL //Access:RW DataWidth:0x20 // UpConfigure Multi-lane Control Register…
7010 …- 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration s…
7012 …- If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CO…
7014 …7) // Upconfigure Support. The core sends this value as the Link Upconfigure Capability in TS2 Or…
7015 …CIEIP_REG_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_K2_SHIFT 7
7017 …RxStandby/RxStandbyStatus handshake. 0x0 = Rx EIOS and subsequent T TX-IDLE-MIN. 0x1 = Rate …
7026 …- [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfig…
7028 …- 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Core wai…
7033 …This is a one-shot bit. Writing a one triggers the deletion of the target completion LUT entry tha…
7035 …lication completions (on XALI0/1/2) corresponding to previously received non-posted requests from …
7038 …mpletion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register fie…
7050 … (0x7<<7) // Split table cont…
7051 …CIEIP_REG_TL_STATUS_0_TC_BB_SHIFT 7
7096 … (0xff<<24) // Non-Posted Data credits available: bit[7:0].
7105 …BB (0xf<<28) // Non-Posted Data credits a…
7114 … (0xff<<24) // Non-Posted Data credits consumed: bit[7:0].
7123 …BB (0xf<<28) // Non-Posted Data credits c…
7128 …L_TGT_CRDT_ST_UNUSED0_BB (0x1<<7) //
7129 …CIEIP_REG_TL_TGT_CRDT_ST_UNUSED0_BB_SHIFT 7
7134 … (0x1<<16) // Available Non-posted credit for tar…
7137 …B (0xff<<0) // Non-Posted header credits…
7139 …B (0xff<<8) // Non-Posted data credits a…
7146 … (0xf<<0) // Target Non-Posted request State …
7182 …non-posted data credits since the last request for immediate update that are needed to force an im…
7184 … (0xff<<12) // The number of accumulated non-posted header credits…
7186 …-posted credits are flagged for immediate update. When clear, the credits may or not be updated un…
7188 …the forced update if there are outstanding non-posted credits to update. The resolution on the tim…
7190 …-posted credit updates are forwarded to the DLL as immediate updates after a given number of micro…
7199 … update if there are outstanding posted credits to update. The resolution on the timer is +/- 1 us.
7201 …w) elapses since the last update. This is typically used with non-immediate (threshold-based) upda…
7228 … field when set will prevent hardware from generating attention when PTM req- response handshake h…
7232 … (0x1<<30) // This field when set inidcates that the PTM req-response handshake in…
7234 … (0x1<<31) // This field when set inidcates that the PTM req-response handshake co…
7244 …cleared after the specified time if reg_ttx_tlp_stat_len is non-zero. All statistic read-back regi…
7248 …r the reg_ttx_tlp_stat_en bit to stop the operation. When it is set to a non-zero value, hardware …
7251 …register contains Enable bit and the TLP type that hardware can detect. Bit[7] is enable bit. If t…
7260 …7:0] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_ttx…
7262 …CIER_TL_STAT_TX_MASK_UNUSED0_BB (0x1<<7) //
7263 …CIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED0_BB_SHIFT 7
7268 …g_ttx_det_tlp_type_2 will be masked. Masking works only if Enable bit (bit [7] of reg_ttx_det_tlp_…
7272 …g_ttx_det_tlp_type_3 will be masked. Masking works only if Enable bit (bit [7] of reg_ttx_det_tlp_…
7277 …cleared after the specified time if reg_trx_tlp_stat_len is non-zero. All statistic read-back regi…
7281 …r the reg_trx_tlp_stat_en bit to stop the operation. When it is set to a non-zero value, hardware …
7284 …register contains Enable bit and the TLP type that hardware can detect. Bit[7] is enable bit. If t…
7293 …7:0] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_trx…
7295 …CIER_TL_STAT_RX_MASK_UNUSED0_BB (0x1<<7) //
7296 …CIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED0_BB_SHIFT 7
7301 …g_trx_det_tlp_type_2 will be masked. Masking works only if Enable bit (bit [7] of reg_trx_det_tlp_…
7305 …g_trx_det_tlp_type_3 will be masked. Masking works only if Enable bit (bit [7] of reg_trx_det_tlp_…
7323 …<<0) // Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7325 …<10) // Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7327 …/ Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7329 …) // No Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7331 …) // No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7333 …o Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7336 … This value is used to provide a 1 us reference for counting time during low-power states with aux…
7339 …-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are…
7389 …RETRIG_CNT_BB (0xff<<0) // When non-zero, indicates the m…
7403 …buffer is filled, the trig_addr field is used to determine the amount of pre-trigger data collected
7424 …- mask bits [319:0] for 0to1 trigger0 Register 10 :: IND_PCIE_DBG_TRIG0_1TO0_MASK - mask bits [319…
7430 …CIER_DBG_FIFO_DBG_CTL_RESERVED_7_BB (0x1<<7) //
7431 …CIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RESERVED_7_BB_SHIFT 7
7455 …- no FIFO selected to read by user if 001 - PL/DL FIFO is selected to read by user if 010 - TLDA…
7459 … (0x7<<12) // 000 - generic lane is selected 001 - predefined lane 1 010 - predefine…
7482 …T_FIFO_RADDR_DWSEL_BB (0x1<<7) // When set, indica…
7483 …CIEIP_REG_PCIER_TLDA0_CTLSTAT_FIFO_RADDR_DWSEL_BB_SHIFT 7
7490 …nterface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
7496 … (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read fr…
7498 … (0x7f<<15) // The number of pre-trigger samples to ke…
7523 …-- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 risi…
7525 … 0x000c50UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the FIFO
7526 … 0x000c54UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the FIFO
7527 … 0x000c58UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the FIFO
7528 … 0x000c5cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the FIFO
7532 …T_FIFO_RADDR_DWSEL_BB (0x1<<7) // When set, indica…
7533 …CIEIP_REG_PCIER_TLDA1_CTLSTAT_FIFO_RADDR_DWSEL_BB_SHIFT 7
7540 …nterface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
7546 … (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read fr…
7548 … (0x7f<<15) // The number of pre-trigger samples to ke…
7573 …-- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 risi…
7575 …000c70UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the second …
7576 …x000c74UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the second …
7577 …x000c78UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the second …
7578 …0x000c7cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the second …
7594 …DL_CONTROL_0_RESERVED_9_7_BB (0x7<<7) //
7595 …CIEIP_REG_PDL_CONTROL_0_RESERVED_9_7_BB_SHIFT 7
7621 …PDFC_P_LAT_SEL_BB (0x1<<7) // When this bit is…
7622 …CIEIP_REG_PDL_CONTROL_1_SW_UPDFC_P_LAT_SEL_BB_SHIFT 7
7625 …// When this bit is set, the software value will be used for UpdateFC Latency of Non-Posted credit.
7633 … (0x1<<14) // This initiates Link re-training by directing…
7664 …1<<17) // DL: Enable Non-Posted Latency Timer. If this timer reaches MAX_ACK_LAT_TIMER value, DL w…
7678 … (0xfff<<0) // DL: Non-Posted Data for INITFC
7700 … (0xffff<<16) // Reserved - always write 0
7703 …s selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calculated value is s…
7705 …he replay timeout in symbol time. This delay is only applied to the hardware-calculated replay tim…
7707 …_BB (0x7ff<<21) // Reserved - always write 0
7712 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7717 …s selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calculated value is s…
7719 …he replay timeout in symbol time. This delay is only applied to the hardware-calculated replay tim…
7734 …t from sending more Posted FC updates , potentially stall DMA requests, until the flag de-asserted.
7737 …s selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calculated value is s…
7739 …he replay timeout in symbol time. This delay is only applied to the hardware-calculated replay tim…
7744 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7751 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7781 … (0x1<<6) // Indicate un-decoded condition in de-framing l…
7783 …OR_STATUS_BB (0x1<<7) // Assert when LCRC…
7784 …CIEIP_REG_DLATTN_VEC_DLP_ERROR_STATUS_BB_SHIFT 7
7791 … (0x1<<11) // Set if DL detects impossible condition to de-allocate entries in R…
7801 … (0x1<<16) // Detect DLLP with mismatched CRC-16 on receiving side.
7844 …conditions occurs: - TLP ends in one entry. - The number of valid entries in T2D FIFO is greater t…
7881 …8-bit header information that is sent to TL logic to build a TLP. The header information is passed…
7911 …initiated, HW transmits number of TLPs equal to ATE_TLP_CNT (bits[7:0] of ate_tlp_cfg - offset 0x1…
7915 … (bits[7:0] of ate_tlp_cfg - offset 0x111c). This register value needs to be ignored until user wr…
7967 … (0x1<<0) // Request a width change (ie -make the link wider, …
7969 … (0x1<<1) // Request a speed change (ie -make the link fast or…
7975 … (0x1<<6) // For multi-lane links on a 2.0 c…
7977 …EG_PHY_CTL_0_UNUSED_2_BB (0x1<<7) //
7978 …CIEIP_REG_REG_PHY_CTL_0_UNUSED_2_BB_SHIFT 7
8005 …ate (this propagates to the PCIe Serdes via the TxDeemph signal. 0 == -6 dB, 1 == -3.5 dB (For Gen…
8015 … (0x1<<27) // Disable use of electrical idle in Recovery.Speed - only use inferred el…
8019 … (0x1<<29) // Disable the ability to compensate for lane reversal in multi-lane links.
8026 … (0x1<<0) // Force the PIPE interface to be 16-bit, even in Gen 1 So…
8030 … (0x1<<2) // Enable the PIPE-style powerdown of unused lanes in a multi-…
8032 … (0x1<<3) // Enable the auxilliary powerdown of unused lanes in a multi-lane link.
8034 … (0x1<<4) // Initiate PL changes required for a far-end loopback
8040 …IDL_DLY_BB (0x1f<<7) // Tuning field to …
8041 …CIEIP_REG_REG_PHY_CTL_1_REG_EIDL_DLY_BB_SHIFT 7
8068 … (0x1<<29) // Clear the LTSSM histogram. Not self-clearing
8070 … (0x1<<30) // Clear the Gen2 debug histogram. Not self-clearing
8072 … (0x1<<31) // Clear the recovery histogram. Not self-clearing
8077 …X_GOOD_CNT_MAX_BB (0x1ff<<7) // Minimum time (in…
8078 …CIEIP_REG_REG_PHY_CTL_2_EIDL_TX_GOOD_CNT_MAX_BB_SHIFT 7
8081 …erved - only write 0. Spare flops for the PL - train_ctl_in[1:0]. [29] (PL_FIX_19) Enable Phase 3 …
8083 …es elastic buffers will be prevented from adjusting - generating dynamic clock compensation events…
8085 … (0x1<<31) // Reserved - only write 0. Spare flop for the PL - t…
8092 … (0x1<<14) // Enable the "pins" gloopback - assumes an external …
8135 …ALLOW_LOCAL_SPD_CHG_BB (0x1<<7) // Allow locally in…
8136 …CIEIP_REG_REG_PHY_CTL_4_REG_ALLOW_LOCAL_SPD_CHG_BB_SHIFT 7
8143 …nimum time to wait in Detect.Quiet (in 32 ns increments) if the state is entered at non-Gen1 speeds
8149 … (0x1<<16) // Enable exit from Compliance on 1.1-compliant systems on …
8162 … (0xf<<5) // High 4 bits of the 10 bit-counter of 25 MHz clk…
8168 …erdes device type to minimize the PLL lock time (when set, don't reuse the old value - start over).
8170 … (0x3<<22) // Selects the low-frequency clock used …
8172 … (0x3f<<24) // Low 6 bits of the 10 bit-counter of 25 MHz clk…
8174 … (0x1<<30) // Reserved - only write 0
8181 …B (0x3<<6) // Reserved - only write 0
8185 … (0x3<<14) // Reserved - only write 0
8189 … (0x1<<17) // Use any PhyStatus to indicate the P0->P2 transition. De…
8195 … (0xfff<<20) // Reserved - only write 0
8198 … (0xf<<0) // b0000: select pseudo-random value between …
8202 …RR_INJ_LANE_BB (0x1f<<7) // This field selec…
8203 …CIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_LANE_BB_SHIFT 7
8212 … (0x1fff<<18) // Reserved - always write 0
8231 …C_ERR_STATUS_BB (0x1<<7) // Clock Compensati…
8232 …CIEIP_REG_PHY_ERR_ATTN_VEC_CC_ERR_STATUS_BB_SHIFT 7
8233 …1_BB (0xf<<8) // Reserved - only write 0
8252 …MASK_CC_ERR_STATUS_BB (0x1<<7) // If set, masks Cl…
8253 …CIEIP_REG_PHY_ERR_ATTN_MASK_MASK_CC_ERR_STATUS_BB_SHIFT 7
8254 …_1_BB (0xf<<8) // Reserved - only write 0
8269 … (0x1<<8) // *** Do not modify!! Enable 16-bit data for all rate…
8287 … (0x3<<17) // Reserved - only write 0
8312 … (0x1<<20) // Enable a bad/misplaced End-of-Data-Stream token as a…
8343 … (0x1<<5) // Software sets if it can disable data traffic during re-equalization.
8347 …_GEN3_DEFAULT_PRESET_BB (0xf<<7) // Default preset f…
8348 …CIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DEFAULT_PRESET_BB_SHIFT 7
8383 …B (0x1<<28) // Reserved - only write 0
8398 …_GEN3_MATCH_EQ_SYM1TO5_BB (0x1<<7) // For Gen3 TS1s in…
8399 …CIEIP_REG_REG_PHY_CTL_11_REG_GEN3_MATCH_EQ_SYM1TO5_BB_SHIFT 7
8406 … (0x1<<11) // Enable Gen3 redo deskew on framing/post-deskew alignment issu…
8428 … (0x1<<22) // (PL_FIX_05) Enable preset-coefficient lookup fo…
8447 …C_BB (0x1<<6) // SED read address auto-increment
8449 …_SEDCFG_CLR_ADDR_BB (0x1<<7) // SED clear read a…
8450 …CIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_CLR_ADDR_BB_SHIFT 7
8468 …ET_LUT_ENTRY_5_TO_0_BB (0x3f<<0) // Pre-cursor for the coeffi…
8472 …_LUT_ENTRY_17_TO_12_BB (0x3f<<12) // Post-cursor for the coeffi…
8480 …y the EP to the Link partner-RC Transmitter in Phase2 EQ programmable preset value advertized by t…
8495 …_GEN3_EN_EXTEND_EQ0_TO_BB (0x1<<7) // [SEMI_FUNCTIONAL…
8496 …CIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ0_TO_BB_SHIFT 7
8523 …eemphasis register control programming of coefficients for preset-0(-6dB) and preset-1(-3.5dB) in …
8525 …reset 0 and 1 0: points to the preset 0 coefficients(-6dB) 1: points to the preset 1 coefficients(…
8529 …0) // Gen2 deemphasis register select control bit to change from Preset-1(-3.5dB) to preset-0(-6dB)
8531 …/ Select control bit for the read status of the gen1/2 and gen2 lut entry 18-bit value poining to …
8554 …_GEN123_TX_DEEMPH_POSTCTRL_LSB_VAL_BB (0x3<<7) // AFE TX deemphasi…
8555 …CIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POSTCTRL_LSB_VAL_BB_SHIFT 7
8576 … (0x1<<31) // RX reset EIEOS control bit for TS1(SYM6-Bit2) in Recovery.Equ…
8581 … (0x3f<<1) // Registered programmed 6-bit FULL SWING value …
8583 …_GEN3_EQ_LF_EN_BB (0x1<<7) // Enable bit to co…
8584 …CIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_LF_EN_BB_SHIFT 7
8585 … (0x3f<<8) // Registered programmed 6-bit LOW FREQUENCY val…
8611 …<<26) // [DEBUG_BIT]: RC mode : Forces Gen3 equalization for every Speed change over from Gen1-Gen3
8613 … (0x1f<<27) // [DEBUG_BITS]: Equalization static debug 5-bit address control f…
8630 …_GEN3_ENA_DATA_AFTER_EDS_ERR_BB (0x1<<7) // Enable Data Afte…
8631 …CIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_DATA_AFTER_EDS_ERR_BB_SHIFT 7
8647 …L_LPBK_MASTER_CTL0_UNUSED_2_BB (0x1<<7) //
8648 …CIEIP_REG_PL_LPBK_MASTER_CTL0_UNUSED_2_BB_SHIFT 7
8653 …clear the lpbk_master_ena bit to stop the operation. When it is set to a non-zero value, hardware …
8666 …_BB (0x1<<7) // Loopback Master TS1 Use Preset. This value is sent i…
8667 …CIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_USEPRESET_BB_SHIFT 7
8668 …CURSOR_BB (0x3f<<8) // Loopback Master TS1 Pre-Cursor Coefficient. T…
8672 …URSOR_BB (0x3f<<20) // Loopback Master TS1 Post-cursor Coefficient. T…
8674 … (0x1<<26) // Loopback Master TS1 Selectable De-emphasis. This value …
8679 … used when loopback is in Gen2 rate. Notes that for Gen1 the TX deemphasis is always set to -3.5db.
8686 …ware is in control, the new state will be applied to LTSSM. This bit is self-cleared, so reading a…
8692 …-level State. This field specifies the state of the sub-level state machine that software wants LT…
8696 … (0x1ff<<20) // Software LTSSM Top-level State. This field specifies the state of th…
8703 …ally cleared after the specified time if pcie_statis_len is non-zero. All statistic read-back regi…
8707 …clear the pcie_statis_ena bit to stop the operation. When it is set to a non-zero value, hardware …
8773 …S_1512_MCP_LOCK_12_BB (0x1<<7) // For lane 12: Set…
8774 …CIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_12_BB_SHIFT 7
8775 … (0x7f<<8) // For lane 13 in a multi-lane system: The numb…
8777 … (0x1<<15) // For lane 13 in a multi-lane system: Set by t…
8783 … (0x7f<<24) // For lane 15 in a multi-lane system: The numb…
8785 … (0x1<<31) // For lane 15 in a multi-lane system: Set by t…
8790 …S_118_MCP_LOCK_8_BB (0x1<<7) // For lane 8: Set …
8791 …CIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_8_BB_SHIFT 7
8792 … (0x7f<<8) // For lane 9 in a multi-lane system: The numb…
8794 … (0x1<<15) // For lane 9 in a multi-lane system: Set by t…
8800 … (0x7f<<24) // For lane 11 in a multi-lane system: The numb…
8802 … (0x1<<31) // For lane 11 in a multi-lane system: Set by t…
8807 …S_74_MCP_LOCK_4_BB (0x1<<7) // For lane 4: Set …
8808 …CIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_4_BB_SHIFT 7
8809 … (0x7f<<8) // For lane 5 in a multi-lane system: The numb…
8811 … (0x1<<15) // For lane 5 in a multi-lane system: Set by t…
8817 … (0x7f<<24) // For lane 7 in a multi-lane system: Th…
8819 … (0x1<<31) // For lane 7 in a multi-lane system: Se…
8824 …S_30_MCP_LOCK_0_BB (0x1<<7) // For lane 0: Set …
8825 …CIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_0_BB_SHIFT 7
8826 … (0x7f<<8) // For lane 1 in a multi-lane system: The numb…
8828 … (0x1<<15) // For lane 1 in a multi-lane system: Set by t…
8834 … (0x7f<<24) // For lane 3 in a multi-lane system: The numb…
8836 … (0x1<<31) // For lane 3 in a multi-lane system: Set by t…
8841 …RORS_1512_TX_MCP_LOCK_12_BB (0x1<<7) // For lane 12: Set…
8842 …CIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_12_BB_SHIFT 7
8843 … (0x7f<<8) // For lane 13 in a multi-lane system: The numb…
8845 … (0x1<<15) // For lane 13 in a multi-lane system: Set by t…
8851 … (0x7f<<24) // For lane 15 in a multi-lane system: The numb…
8853 … (0x1<<31) // For lane 15 in a multi-lane system: Set by t…
8858 …RORS_118_TX_MCP_LOCK_8_BB (0x1<<7) // For lane 8: Set …
8859 …CIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_8_BB_SHIFT 7
8860 … (0x7f<<8) // For lane 9 in a multi-lane system: The numb…
8862 … (0x1<<15) // For lane 9 in a multi-lane system: Set by t…
8868 … (0x7f<<24) // For lane 11 in a multi-lane system: The numb…
8870 … (0x1<<31) // For lane 11 in a multi-lane system: Set by t…
8875 …RORS_74_TX_MCP_LOCK_4_BB (0x1<<7) // For lane 4: Set …
8876 …CIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_4_BB_SHIFT 7
8877 … (0x7f<<8) // For lane 5 in a multi-lane system: The numb…
8879 … (0x1<<15) // For lane 5 in a multi-lane system: Set by t…
8885 …B (0x7f<<24) // For lane 7 in a multi-lane system: Th…
8887 …BB (0x1<<31) // For lane 7 in a multi-lane system: Se…
8892 …RORS_30_TX_MCP_LOCK_0_BB (0x1<<7) // For lane 0: Set …
8893 …CIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_0_BB_SHIFT 7
8894 … (0x7f<<8) // For lane 1 in a multi-lane system: The numb…
8896 … (0x1<<15) // For lane 1 in a multi-lane system: Set by t…
8902 … (0x7f<<24) // For lane 3 in a multi-lane system: The numb…
8904 … (0x1<<31) // For lane 3 in a multi-lane system: Set by t…
8936 … (0xff<<24) // Gen2 Debug History 7 transitions ago (see…
8939 … (0xff<<0) // Gen2 Debug History - current. Changes are…
8954 … (0xff<<24) // Recovery History 7 transitions ago (see…
8957 … (0xff<<0) // Recovery History - current. Changes are…
8990 … (0xff<<24) // LTSSM state 7 transitions in the p…
9015 …) // The current state of the ATE loopback SM tracker: b00011 : IDLE state - not active b00101 : …
9021 …PBACK_INFO_UNUSED_BB (0x1ffffff<<7) //
9022 …CIEIP_REG_ATE_LOOPBACK_INFO_UNUSED_BB_SHIFT 7
9038 …_SET_GEN3_ERR_DATA_AFTER_EDS_BB (0x1<<7) // Data block occur…
9039 …CIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_DATA_AFTER_EDS_BB_SHIFT 7
9066 … 0x001d38UL //Access:R DataWidth:0x20 // PHY Debug - Polling Compliance s…
9067 … 0x001d3cUL //Access:R DataWidth:0x20 // PHY Debug - Equalization signals
9167 …G_7_BB (0xff<<24) // SED Extended Configuration 7.
9180 … (0xf<<0) // The state of the clock PM state machine and perstb 7 transitions in the p…
9248 … (0x1<<0) // Instantaneous value of the top-level user_allow_gen3…
9253 … (0xffff<<0) // Vendor ID. For SR-IOV VFs always 0xFFFF.
9255 … (0xffff<<16) // Device ID. For SR-IOV VFs always 0xFFFF.
9258 …ENDOR_ID_K2 (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufact…
9263 …E_E5 (0x1<<0) // VF read-only zero.
9265 …E_E5 (0x1<<1) // VF read-only zero.
9267 …)_PF()_DBG_INFO[P()_BMD_E bit. Transactions are dropped in the Client. Non-posted transactions r…
9277 …S_WCC_E5 (0x1<<7) // IDSEL stepping/w…
9278 …CIEIP_VF_REG_PCIEEPVF_CMD_IDS_WCC_E5_SHIFT 7
9281 … (0x1<<9) // Fast back-to-back transaction ena…
9283 …S_E5 (0x1<<10) // VF read-only zero.
9289 … (0x1<<19) // INTx status. Not applicable for SR-IOV. Hardwired to 0.
9295 … (0x1<<23) // Fast back-to-back capable. Not ap…
9312 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9314 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9326 …MAND_REG_PCI_TYPE_IDSEL_STEPPING_K2 (0x1<<7) // IDSEL Stepping.
9327 …CIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2_SHIFT 7
9352 …_ERR_K2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
9359 … (0xff<<8) // Read-only copy of the asso…
9361 … (0xff<<16) // Read-only copy of the asso…
9363 … (0xff<<24) // Read-only copy of the asso…
9375 … (0xff<<0) // Read-only copy of the asso…
9381 … (0x1<<23) // Read-only copy of the asso…
9400 …E_K2 (0x3<<1) // BAR0 32-bit or 64-bit.
9410 …E_K2 (0x3<<1) // BAR1 32-bit or 64-bit.
9420 …E_K2 (0x3<<1) // BAR2 32-bit or 64-bit.
9430 …E_K2 (0x3<<1) // BAR3 32-bit or 64-bit.
9440 …E_K2 (0x3<<1) // BAR4 32-bit or 64-bit.
9450 …E_K2 (0x3<<1) // BAR5 32-bit or 64-bit.
9459 … (0xffff<<0) // Read-only copy of the asso…
9461 … (0xffff<<16) // Read-only copy of the asso…
9464 …tem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9466 …tem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9469 … (0x1<<0) // Read-only copy of the asso…
9471 … (0x1fff<<19) // Read-only copy of the asso…
9480 … (0xff<<0) // VF's read-only zeros.
9482 … (0xff<<8) // VF's read-only zeros.
9484 … (0xff<<16) // VF's read-only zeros.
9486 … (0xff<<24) // VF's read-only zeros.
9496 … (0xff<<8) // Next capability pointer. Points to the MSI-X capabilities by def…
9498 …_E5 (0xf<<16) // Read-only copy of the asso…
9500 … (0xf<<20) // Read-only copy of the asso…
9502 … (0x1<<24) // Read-only copy of the asso…
9504 … (0x1f<<25) // Read-only copy of the asso…
9515 …emented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9522 … (0x7<<0) // Read-only copy of the asso…
9524 … (0x3<<3) // Read-only copy of the asso…
9526 … (0x1<<5) // Read-only copy of the asso…
9528 … (0x7<<6) // Read-only copy of the asso…
9530 … (0x7<<9) // Read-only copy of the asso…
9532 … (0x1<<15) // Read-only copy of the asso…
9538 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core.
9545 …eld Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9551 …_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2 (0x1<<15) // Role-based Error Reporting…
9584 …e receive any of the errors in PCIEEPVF()_COR_ERR_STAT, for example a replay-timer timeout. Also,…
9590 …ests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message shoul…
9592 …D_E5 (0x1<<20) // VF's read-only zeros.
9599 …_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting…
9609 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9611 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9615 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
9623 …STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
9634 … (0xf<<0) // Read-only copy of the asso…
9636 … (0x3f<<4) // Read-only copy of the asso…
9638 …5 (0x3<<10) // Read-only copy of the asso…
9640 … (0x7<<12) // Read-only copy of the asso…
9642 … (0x7<<15) // Read-only copy of the asso…
9644 … (0x1<<18) // Read-only copy of the asso…
9646 … (0x1<<19) // Read-only copy of the asso…
9648 …5 (0x1<<20) // Read-only copy of the asso…
9650 … (0x1<<21) // Read-only copy of the asso…
9652 … (0x1<<22) // Read-only copy of the asso…
9654 … (0xff<<24) // Read-only copy of the asso…
9657 …D_K2 (0xf<<0) // Maximum Link Speed. In M-PCIe mode, the reset …
9659 …_K2 (0x3f<<4) // Maximum Link Width. In M-PCIe mode, the reset …
9663 … following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_CO…
9665 … following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_CO…
9667 …er Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9675 … ASPM Optionality Compliance. Note: The access attributes of this field are as follows: - Dbi: R
9690 …F_LINK_CTL_ES_E5 (0x1<<7) // VF RsvdP.
9691 …CIEIP_VF_REG_PCIEEPVF_LINK_CTL_ES_E5_SHIFT 7
9721 …_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_EN…
9723 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
9727 …OL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2 (0x1<<7) // Extended Synch.
9728 …CIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2_SHIFT 7
9729 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9733 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9735 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9743 …figuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
9745 …Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9749 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9751 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9762 …TOM32S_E5 (0x1<<7) // 32-bit AtomicOp supp…
9763 …CIEIP_VF_REG_PCIEEPVF_DEV_CAP2_ATOM32S_E5_SHIFT 7
9764 …4S_E5 (0x1<<8) // 64-bit AtomicOp supporte…
9766 …8S_E5 (0x1<<9) // 128-bit AtomicOp supporte…
9768 … (0x1<<10) // No RO-enabled PR-PR passing. (Thi…
9776 …_CPL_SUPP_E5 (0x1<<16) // 10-bit tag completer sup…
9778 …_REQ_SUPP_E5 (0x1<<17) // 10-bit tag requestor sup…
9784 …5 (0x1<<21) // End-end TLP prefix suppor…
9786 … (0x3<<22) // Read-only copy of the asso…
9797 …ILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2 (0x1<<7) // 32 Bit AtomicOp …
9798 …CIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2_SHIFT 7
9803 …O_EN_PR2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
9828 …_REQ_EN_E5 (0x1<<12) // 10-bit tag requestor ena…
9832 … (0x1<<15) // Unsupported end-end TLP prefix blocki…
9843 …OL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2 (0x1<<7) // AtomicOp Egress …
9844 …CIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2_SHIFT 7
9854 … (0x7f<<1) // Read-only copy of the asso…
9867 …DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9870 …TLS_E5 (0xf<<0) // VF's read-only zeros.
9872 …EC_E5 (0x1<<4) // VF's read-only zeros.
9874 …HASD_E5 (0x1<<5) // VF's read-only zeros.
9876 …SDE_E5 (0x1<<6) // VF's read-only zeros.
9878 …TM_E5 (0x7<<7) // VF's read-only zeros.
9879 …CIEIP_VF_REG_PCIEEPVF_LINK_CTL2_TM_E5_SHIFT 7
9880 …MC_E5 (0x1<<10) // VF's read-only zeros.
9882 …SOS_E5 (0x1<<11) // VF's read-only zeros.
9884 …DE_E5 (0xf<<12) // VF's read-only zeros.
9886 … (0x1<<16) // Read-only copy of the asso…
9909 …ET_LINK_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the conten…
9913 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9915 …SEL_DEEMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
9917 …2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2 (0x7<<7) // Controls Transmi…
9918 …CIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2_SHIFT 7
9919 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9921 … transmission. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9923 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
9925 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
9942 …NTRL_MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
9946 … (0x7ff<<16) // MSI-X table size encoded as (table size - 1)…
9948 …ctors associated with the function are masked, regardless of their respective per-vector mask bits.
9950 …X_CAP_CNTRL_MSIXEN_E5 (0x1<<31) // MSI-X enable.
9952 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
9953 …NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
9955 …TRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2 (0xff<<8) // MSI-X Next Capability Poi…
9957 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
9959 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
9961 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
9964 …BIR_E5 (0x7<<0) // Read-only copy of the asso…
9966 … (0x1fffffff<<3) // Read-only copy of the asso…
9968 … 0x0000b4UL //Access:R DataWidth:0x20 // MSI-X Table Offset and BI…
9969 …_PCI_MSIX_BIR_K2 (0x7<<0) // MSI-X Table Bar Indicator…
9971 …_PCI_MSIX_TABLE_OFFSET_K2 (0x1fffffff<<3) // MSI-X Table Offset.
9974 …R_E5 (0x7<<0) // Read-only copy of the asso…
9976 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
9978 … 0x0000b8UL //Access:R DataWidth:0x20 // MSI-X PBA Offset and BIR …
9979 …OFFSET_REG_PCI_MSIX_PBA_K2 (0x7<<0) // MSI-X PBA BIR.
9981 …_PCI_MSIX_PBA_OFFSET_K2 (0x1fffffff<<3) // MSI-X PBA Offset.
9991 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9993 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9995 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10031 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10033 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10035 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10073 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
10083 … 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
10085 … 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
10132 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10134 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10138 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10140 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10154 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10156 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10160 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10162 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10170 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if RO…
10172 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if RO…
10174 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10175 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10177 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10180 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10182 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10185 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10187 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10190 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10192 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10195 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10197 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10200 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10202 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10205 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10207 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10210 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10212 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10244 …M007_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
10245 …EM_FAST_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 7
10290 …-only access of the GPRE registers. Register can be accessed only when storm is stalled. Address b…
10292 … 0x000480UL //Access:R DataWidth:0x20 // 15-0 STORM0 GPRE0 bits 15:0. 31-16 STOR…
10293 …- misc_local_mux_other_stall, 20 - ram_mux_bkpt_stall, 19 - mux_lock_stall, 18 - pram_mux_pipe_st…
10298 …ether or not the Storm is currently stalled. bit0- STORM A. bit1- STORM B. bit2- Pram Breakpoint. …
10303 …R DataWidth:0xf // This register delivers the PRAM address for the low-word instruction that…
10304 … DataWidth:0xf // This register delivers the PRAM address for the high-word instruction that…
10307 …en as a single bit , a value of 2 means that the PortID will be taken as a 2-bit field. A value of…
10308 …fines the offset (in bits) from the lsb of the CID in which to assign to bit-0 of the port ID. I.e…
10309 …dth:0x1 // Defines the Storm register file set that is currently active. 0 - STORM A 1 - STORM B
10310 …- DRA WR STM Core_A, 3:5 - DRA WR STM Core_B, 6:8 - DRA RD STM Core_A, 9:11 - DRA RD STM Core_B, …
10313 …- when set, invert bit on complementary index 4:0. bit 5 - when set, invert bit on index 4:0. …
10315 …th:0x20 // This register delivers the Storm PC for read-only debug access. 15-0 - STORM A. 31-16…
10316 …e access type defined in data_breakpoint_access_set), the STORMs bits 15:0 - IRAM stall start add…
10317 …efined in data_breakpoint_access_set), the STORMs will be stalled. bit15:0 - IRAM stall end addre…
10318 …- stall on read access. bit1 - stall on write access. bit3:2 - stall on write BE (bit2 -to IRAM'…
10319 …er defines the IRAM address for which the data breakpoint stall was set. bits 0:15 - IRAM address.
10323 … indirect registers defines the modulus (roll-over) values for the corresponding real time clocks.…
10326 …-time clock with regard to the associated RTClkTickValue. The Storm decode assignments used for th…
10329 …-time clocks. This value is assigned to the corresponding real-time clock only when the Storm corr…
10332 …-time clock with the value provided by the associated RTClkInitValue register. The Storm decode as…
10335 …direct registers provides read access to the real time clock values. The sub-address for this indi…
10337 … per RTC used to enable each of the ten real-time clocks. The bit index corresponds with the ID of…
10347 …or the most recent RBC read request issued. The valid bit is returned on bit-0 of the data. All ot…
10357 …0x20 // This array of registers returns the 128-bit CAM match vector returned in the most recent…
10360 …-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fas…
10361 …ources for modes 2 and 3 on the fast debug channel: b0-DRA write disable; b1-DRA read disable; b2-…
10362 …able any of the following debug sources for mode-4 on the fast debug channel: b0-store data disabl…
10363 …ces for mode-6 on the fast debug channel: b0-dra_in disable; b1-fin disable; b2-load disable; b3-t…
10364 …0 // Connection id that should compared with cid field of the data (in Dra-In message); Note: ap…
10365 …aWidth:0x8 // Event id that should compared with event id field of the data (in Dra-In message).
10366 …075cUL //Access:RW DataWidth:0x8 // Mask for event id. 1- specified bit is ignored; 0 - speci…
10367 …e event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active stat…
10368 …e event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active stat…
10370 …- Filter off; in that case all data should be transmitted to the DBG block without any filtering i…
10372 …- use the recorded connection id field which arrives from the DBG block (dbg_sem_cid interface) fo…
10378 … (0x3<<5) // Used to define the DRA-In source that should…
10380 …ABLE_REC_FILTER_DRA_SRC_EN (0x1<<7) // Used to enable D…
10381 …EM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_DRA_SRC_EN_SHIFT 7
10388 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
10402 … (0x3<<2) // Used to define the DRA-In source that should…
10408 … 0x000a44UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10409 … 0x000a44UL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10411 … 0x000a4cUL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10412 … 0x000a4cUL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10413 … 0x000a50UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10414 …- The accumulated number of Storm cycles in which the Storm has been idle due to having no threads…
10415 … 0x000a54UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10416 … 0x000a54UL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10417 … 0x000a58UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10418 … 0x000a5cUL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10419 … 0x000a60UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10420 … 0x000a64UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10425 …- response is ready. It is set when response cycle of 32 bit is ready from VFC block. It is reset …
10429 … 0x000c4cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
10437 …-address. Bits [3:0] of the data bus provide the OpCode for the request where the following numera…
10439 … 0x00a000UL //Access:RW DataWidth:0x20 // Provides a memory-mapped region for VFC…
10458 … DataWidth:0x8 // This register includes bit per ALU vector: 0-4 long vectors; 5-11 short vec…
10461 …asserted when there is attempt to write to read only register. It will be de-asserted aftre write …
10471 …ycle not equal 64 bit or number of data cycles bigger than 6. It will be de-asserted aftre write …
10473 …asserted when waitp is asserted and output FIFO is also full. It will be de-asserted aftre write …
10475 …asserted when it was address overflow of INFO part of RSS RAM. It will be de-asserted aftre write …
10477 …ted when it was address overflow of KEY LSB part of RSS RAM. It will be de-asserted aftre write …
10479 … (0x1<<7) // This is error interrupt. It may be asserted when it was address overflow of …
10480 …FC_REG_INTERRUPT_IND_RSS_KEY_MSB_INTERRUPT_BB_K2_SHIFT 7
10482 …ty interrupt. It may be asserted when it was CAM parity error. It will be de-asserted aftre write …
10484 …pt. It may be asserted when it was parity error inside TT RAM. It will be de-asserted aftre write …
10486 …terrupt. It may be asserted when it was RSS RAM parity error. It will be de-asserted aftre write …
10540 …:RW DataWidth:0x1 // REQUIRED -If this bit is set then background mechanism for parity check …
10542 … 0x000048UL //Access:RW DataWidth:0x3 // REQUIRED - 0 - parity is enabled;…
10543 … 0x00004cUL //Access:RW DataWidth:0xa // REQUIRED - 0 - interrupt is enabled;1- interr…
10556 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
10557 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
10565 …MPTY (0x1<<7) // Next message rea…
10566 …FC_REG_DEBUG_DATA_NEXT_MSG_EMPTY_SHIFT 7
10601 … 0x000114UL //Access:R DataWidth:0x9 // Last analyze offset for ALU vector 7.
10674 … (0x1<<7) // TQ read underflo…
10675 …B_REG_INT_STS_TQ_ERROR_RD_TH_SHIFT 7
10693 …H (0x1<<7) // This bit masks, …
10694 …B_REG_INT_MASK_TQ_ERROR_RD_TH_SHIFT 7
10712 …_TH (0x1<<7) // TQ read underflo…
10713 …B_REG_INT_STS_WR_TQ_ERROR_RD_TH_SHIFT 7
10731 …D_TH (0x1<<7) // TQ read underflo…
10732 …B_REG_INT_STS_CLR_TQ_ERROR_RD_TH_SHIFT 7
10753 …SELECT (0xf<<7) // Obsolete.
10754 …B_REG_CONTROL_DEBUG_SELECT_SHIFT 7
10795 … 0x002000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
10800 …_E5 (0xff<<0) // 8-bit value from packag…
10802 …E5 (0xff<<8) // 8-bit value from packag…
10820 …If set to '0' (Reset value), the CRC field is stripped from the frame. Note - If padding (Bit PAD_…
10822 …USE_FWD_K2_E5 (0x1<<7) // Terminate / Forw…
10823 …TH_MAC_REG_COMMAND_CONFIG_PAUSE_FWD_K2_E5_SHIFT 7
10832 …5 (0x1<<12) // Self-Clearing Software Res…
10860 …_K2_E5 (0x1<<26) // Self-Clearing TX FIFO rese…
10874 … (0xffff<<0) // Last 2 bytes: 5th is 7:0, 6th is 15:8
10913 … (0x1<<5) // MDIO transaction preamble disable. Shortens transaction but is non-standard.
10917 …O_CLOCK_DIVISOR_K2_E5 (0x1ff<<7) // MDIO clock divis…
10918 …TH_MAC_REG_MDIO_CFG_STATUS_MDIO_CLOCK_DIVISOR_K2_E5_SHIFT 7
10924 … (0x1<<14) // If written with 1, a read with address post-increment will be performed. Post-incr…
10929 …-bit data word. When written- Initiates a write transaction to the PHY. The MDIO_COMMAND register …
10931 …PHY device to read from or write to. After writing this register, an address-write transaction wil…
10939 … (0x1<<2) // PHY indicates loss-of-signal. Represents v…
10949 …ULT_K2_E5 (0x1<<7) // Special Link Int…
10950 …TH_MAC_REG_STATUS_RX_LINT_FAULT_K2_E5_SHIFT 7
10959 …E5 (0x1<<0) // Credit-based FIFO only: When…
10962 …5 (0xff<<0) // Credit-based FIFO only: Spec…
10970 …C quanta value for that class when a class XOFF is triggered. Each Quanta specifies a 512 bit-time.
10982 … 0x000060UL //Access:RW DataWidth:0x20 // Class 6 and 7 pause quanta
11002 … 0x000070UL //Access:RW DataWidth:0x20 // Class 6 and 7 refresh threshold
11012 … (0x1<<0) // Enable XGMII-64 (4byte alignment)
11016 … (0x1<<5) // Enable 1-step capable datapath…
11019 …/ Configure saturation behavior. When set to 1, the counters saturate at all-1. Otherwise counters…
11021 … (0x1<<1) // Configure clear-on-read behavior. When …
11023 … (0x1<<2) // Clear all counters command (self-clearing). When writt…
11167 …_K2_E5 (0xf<<8) // RS-FEC receive lane lock…
11169 … (0x1<<14) // Indicates, when 1 that the RS-FEC receiver has lock…
11173 …x20 // Counts number of corrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11174 …umber of corrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11176 …h:0x20 // Counts number of corrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11177 … (0xffff<<0) // Counts number of corrected FEC codewords upper 16-bits; None roll-over; Clears …
11179 …0 // Counts number of uncorrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11180 …ber of uncorrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11182 …0x20 // Counts number of uncorrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11183 … (0xffff<<0) // Counts number of uncorrected FEC codewords upper 16-bits; None roll-over; Clears …
11194 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 0; None roll-over whe…
11195 … (corrected) 10-bit symbol errors found in lane 0 for correctable codewords only; Lower 16-bit of …
11197 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11198 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 0; Clears o…
11200 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 1; None roll-over whe…
11201 … (corrected) 10-bit symbol errors found in lane 1 for correctable codewords only; Lower 16-bit of …
11203 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11204 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 1; Clears o…
11206 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 2; None roll-over whe…
11207 … (corrected) 10-bit symbol errors found in lane 2 for correctable codewords only; Lower 16-bit of …
11209 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11210 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 2; Clears o…
11212 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 3; None roll-over whe…
11213 … (corrected) 10-bit symbol errors found in lane 3 for correctable codewords only; Lower 16-bit of …
11215 … DataWidth:0x20 // Upper 16 bit of counter (with above register); Clears on read; None roll-over.
11216 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 3; Clears o…
11218 … 0x000200UL //Access:RW DataWidth:0x20 // Additional control to enable RS-FEC operation.
11232 …NFO1_TX_DATAPATH_RESTART_K2_E5 (0x1<<7) // TX datapath (syn…
11233 …TH_RSFEC_REG_RS_FEC_VENDOR_INFO1_TX_DATAPATH_RESTART_K2_E5_SHIFT 7
11240 …_EMPTY_K2_E5 (0xf<<12) // Real-time indication from …
11248 …210UL //Access:RW DataWidth:0x20 // Bits 7:0; Must be written with the 8-bit value of 0x57 to …
11249 … (0xff<<0) // Bits 7:0; Must be written with 8-bit value 0x57 to enab…
11251 … 0x000214UL //Access:RW DataWidth:0x20 // Bits 15:0. One bit per 10-bit Symbol; Each bit …
11252 … (0xffff<<0) // Bits 15:0. One bit per 10-bit Symbol; When a bi…
11254 … 0x000218UL //Access:RW DataWidth:0x20 // Bits 9:0; A 10-bit value which XORed…
11255 …N_TEST_PATTERN_K2_E5 (0x3ff<<0) // A 10-bit value which will …
11265 … (0x1<<8) // Indicate full-duplex operation; alw…
11279 … (0x1<<15) // PCS soft-reset command; self-clearing
11284 … (0x1<<2) // Indicate link status; latch-low
11296 …x20 // Local Device Abilities for Autonegotiation. Contents differs for 1000Base-X or SGMII mode.
11299 … (0x1<<5) // Indicate full-duplex support; SGMII…
11301 … (0x1<<6) // Indicate half-duplex support; SGMII…
11303 …_K2_E5 (0x1<<7) // Pause Support 1;…
11304 …TH_PCS1G_REG_DEV_ABILITY_PS1_K2_E5_SHIFT 7
11317 …/ Received Abilities during Autonegotiation. Contents differ depending on 1000Base-X or SGMII mode.
11320 … (0x1<<5) // Indicate full-duplex support; SGMII…
11322 … (0x1<<6) // Indicate half-duplex support; SGMII…
11324 …_PS1_K2_E5 (0x1<<7) // Pause Support 1;…
11325 …TH_PCS1G_REG_PARTNER_ABILITY_PS1_K2_E5_SHIFT 7
11341 … (0x1<<1) // Autoneg page received indication; latch-high
11392 … (0x1<<4) // Set SGMII half-duplex mode when not …
11417 …LT_K2_E5 (0x1<<7) // When 1, indicate…
11418 …TH_PCS10_50G_REG_STATUS1_FAULT_K2_E5_SHIFT 7
11436 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
11468 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11470 … (0x1<<1) // When 1, this PCS is 10GBase-X capable.
11472 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11474 … (0x1<<3) // When 1, this PCS is 10GBase-T capable.
11476 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11478 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11495 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11497 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11499 … (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
11502 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11512 … (0xff<<0) // Errored blocks counter; None roll-over.
11514 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11520 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11521 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11523 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11524 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11526 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11527 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11529 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11530 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11532 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11533 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11535 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11536 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11538 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11539 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11541 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11542 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11549 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11551 …ESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enable.
11553 …CONTROL_SELECT_RANDOM_K2_E5 (0x1<<7) // Select Random Id…
11554 …TH_PCS10_50G_REG_BASER_TEST_CONTROL_SELECT_RANDOM_K2_E5_SHIFT 7
11555 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11556 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11558 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11559 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11561 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11562 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11586 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11587 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11589 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11590 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11592 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11593 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11595 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11596 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11616 …x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
11617 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dis…
11620 …_THRESHOLD_K2_E5 (0xf<<0) // A 4-bit value to define t…
11622 …0010UL //Access:RW DataWidth:0x20 // Vendor Specific Reg; Define Reduced-XLAUI PMA mode using …
11623 …_K2_E5 (0x1<<0) // Enable Reduced-XLAUI PMA mode using …
11668 …2_E5 (0x1<<1) // When 0 PCS 4-lane MLD function is …
11692 …LT_K2_E5 (0x1<<7) // When 1, indicate…
11693 …TH_PCS10_25G_REG_STATUS1_FAULT_K2_E5_SHIFT 7
11711 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
11743 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11745 … (0x1<<1) // When 1, this PCS is 10GBase-X capable.
11747 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11749 … (0x1<<3) // When 1, this PCS is 10GBase-T capable.
11751 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11753 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11770 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11772 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11774 … (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
11777 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11787 … (0xff<<0) // Errored blocks counter; None roll-over.
11789 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11795 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11796 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11798 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11799 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11801 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11802 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11804 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11805 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11807 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11808 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11810 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11811 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11813 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11814 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11816 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11817 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11824 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11826 …ESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enable.
11828 …CONTROL_SELECT_RANDOM_K2_E5 (0x1<<7) // Select Random Id…
11829 …TH_PCS10_25G_REG_BASER_TEST_CONTROL_SELECT_RANDOM_K2_E5_SHIFT 7
11830 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11831 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11833 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11834 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11836 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11837 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11853 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11854 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11856 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11857 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11859 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11860 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11862 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11863 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11871 …x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
11872 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dis…
11875 …_THRESHOLD_K2_E5 (0xf<<0) // A 4-bit value to define t…
11912 …2_E5 (0x1<<1) // When 0 PCS 4-lane MLD function is …
11930 …OP_RESERVEDREGISTER3_RESERVEDFIELD4_K2_E5 (0x1<<7) // Reserved
11931 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER3_RESERVEDFIELD4_K2_E5_SHIFT 7
11935 …OP_RESERVEDREGISTER4_RESERVEDFIELD6_K2_E5 (0x1<<7) // Reserved
11936 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER4_RESERVEDFIELD6_K2_E5_SHIFT 7
11940 …OP_RESERVEDREGISTER5_RESERVEDFIELD8_K2_E5 (0x1<<7) // Reserved
11941 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER5_RESERVEDFIELD8_K2_E5_SHIFT 7
11962 …- off high-impedance 0x1 - CMU 0 0x3 - Lane 0 0x4 - Lane 1 0x5 - Lane 2 0x6 - Lane 3 0x15 - SoC ci…
12052 …OP_RESERVEDREGISTER17_RESERVEDFIELD56_K2_E5 (0x1<<7) // Reserved
12053 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD56_K2_E5_SHIFT 7
12057 …OP_RESERVEDREGISTER18_RESERVEDFIELD58_K2_E5 (0x1<<7) // Reserved
12058 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER18_RESERVEDFIELD58_K2_E5_SHIFT 7
12062 …OP_RESERVEDREGISTER19_RESERVEDFIELD60_K2_E5 (0x1<<7) // Reserved
12063 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER19_RESERVEDFIELD60_K2_E5_SHIFT 7
12067 …OP_RESERVEDREGISTER20_RESERVEDFIELD62_K2_E5 (0x1<<7) // Reserved
12068 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER20_RESERVEDFIELD62_K2_E5_SHIFT 7
12072 …OP_RESERVEDREGISTER21_RESERVEDFIELD64_K2_E5 (0x1<<7) // Reserved
12073 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER21_RESERVEDFIELD64_K2_E5_SHIFT 7
12079 …OP_RESERVEDREGISTER22_RESERVEDFIELD67_K2_E5 (0x1<<7) // Reserved
12080 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER22_RESERVEDFIELD67_K2_E5_SHIFT 7
12088 …OP_RESERVEDREGISTER23_RESERVEDFIELD71_K2_E5 (0x1<<7) // Reserved
12089 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD71_K2_E5_SHIFT 7
12100 …CM_LC0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN_K2_E5 (0x1<<7) // Clock gate enabl…
12101 …HY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN_K2_E5_SHIFT 7
12112 …CM_LC0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN_K2_E5 (0x1<<7) // Clock gate enabl…
12113 …HY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN_K2_E5_SHIFT 7
12119 …OP_RESERVEDREGISTER26_RESERVEDFIELD82_K2_E5 (0x1<<7) // Reserved
12120 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER26_RESERVEDFIELD82_K2_E5_SHIFT 7
12128 …OP_RESERVEDREGISTER27_RESERVEDFIELD86_K2_E5 (0x1<<7) // Reserved
12129 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD86_K2_E5_SHIFT 7
12140 …CM_R0_CLK_PLL2_CTRL1_TBUS_OUT_CG_EN_K2_E5 (0x1<<7) // Clock gate enabl…
12141 …HY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2_CTRL1_TBUS_OUT_CG_EN_K2_E5_SHIFT 7
12152 …CM_R0_CLK_PLL2DIV_CTRL1_TBUS_OUT_CG_EN_K2_E5 (0x1<<7) // Clock gate enabl…
12153 …HY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2DIV_CTRL1_TBUS_OUT_CG_EN_K2_E5_SHIFT 7
12164 …CM_R0_CLK_PLL3_CTRL1_TBUS_OUT_CG_EN_K2_E5 (0x1<<7) // Clock gate enabl…
12165 …HY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3_CTRL1_TBUS_OUT_CG_EN_K2_E5_SHIFT 7
12176 …CM_R0_CLK_PLL3DIV_CTRL1_TBUS_OUT_CG_EN_K2_E5 (0x1<<7) // Clock gate enabl…
12177 …HY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3DIV_CTRL1_TBUS_OUT_CG_EN_K2_E5_SHIFT 7
12185 …OP_CLOCK_LN0_CLK_TX_RESERVEDFIELD104_K2_E5 (0x1<<7) // Reserved
12186 …HY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_RESERVEDFIELD104_K2_E5_SHIFT 7
12194 …OP_RESERVEDREGISTER32_RESERVEDFIELD108_K2_E5 (0x1<<7) // Reserved
12195 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD108_K2_E5_SHIFT 7
12203 …OP_CLOCK_LN0_CLK_RX_RESERVEDFIELD110_K2_E5 (0x1<<7) // Reserved
12204 …HY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_RESERVEDFIELD110_K2_E5_SHIFT 7
12212 …OP_RESERVEDREGISTER33_RESERVEDFIELD114_K2_E5 (0x1<<7) // Reserved
12213 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD114_K2_E5_SHIFT 7
12227 …OP_CLOCK_LN1_CLK_TX_RESERVEDFIELD118_K2_E5 (0x1<<7) // Reserved
12228 …HY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_RESERVEDFIELD118_K2_E5_SHIFT 7
12236 …OP_RESERVEDREGISTER36_RESERVEDFIELD122_K2_E5 (0x1<<7) // Reserved
12237 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD122_K2_E5_SHIFT 7
12245 …OP_CLOCK_LN1_CLK_RX_RESERVEDFIELD124_K2_E5 (0x1<<7) // Reserved
12246 …HY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_RESERVEDFIELD124_K2_E5_SHIFT 7
12254 …OP_RESERVEDREGISTER37_RESERVEDFIELD128_K2_E5 (0x1<<7) // Reserved
12255 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD128_K2_E5_SHIFT 7
12269 …OP_CLOCK_LN2_CLK_TX_RESERVEDFIELD132_K2_E5 (0x1<<7) // Reserved
12270 …HY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_RESERVEDFIELD132_K2_E5_SHIFT 7
12278 …OP_RESERVEDREGISTER40_RESERVEDFIELD136_K2_E5 (0x1<<7) // Reserved
12279 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD136_K2_E5_SHIFT 7
12287 …OP_CLOCK_LN2_CLK_RX_RESERVEDFIELD138_K2_E5 (0x1<<7) // Reserved
12288 …HY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_RESERVEDFIELD138_K2_E5_SHIFT 7
12296 …OP_RESERVEDREGISTER41_RESERVEDFIELD142_K2_E5 (0x1<<7) // Reserved
12297 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD142_K2_E5_SHIFT 7
12311 …OP_CLOCK_LN3_CLK_TX_RESERVEDFIELD146_K2_E5 (0x1<<7) // Reserved
12312 …HY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_RESERVEDFIELD146_K2_E5_SHIFT 7
12320 …OP_RESERVEDREGISTER44_RESERVEDFIELD150_K2_E5 (0x1<<7) // Reserved
12321 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD150_K2_E5_SHIFT 7
12329 …OP_CLOCK_LN3_CLK_RX_RESERVEDFIELD152_K2_E5 (0x1<<7) // Reserved
12330 …HY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_RESERVEDFIELD152_K2_E5_SHIFT 7
12338 …OP_RESERVEDREGISTER45_RESERVEDFIELD156_K2_E5 (0x1<<7) // Reserved
12339 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD156_K2_E5_SHIFT 7
12362 … (0x1<<0) // PHY error status. 0x0 - no error 0x1 - PHY has an in…
12364 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12365 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12383 … 0x000680UL //Access:RW DataWidth:0x8 // lower 8-bits of the 16-bit digital te…
12384 … 0x000684UL //Access:RW DataWidth:0x8 // higher 8-bits of the 16-bit digital te…
12388 … 0x0006c0UL //Access:R DataWidth:0x8 // Digital test bus tbus output bits [7:0]
12411 … 0x000828UL //Access:RW DataWidth:0x8 // Command auxiliary data or argument 7
12423 … 0x000868UL //Access:RW DataWidth:0x8 // Response auxiliary data or argument 7
14398 …used in gearbox applications. 0x0 - DIV4 0x1 - DIV8 0x2 - DIV16 0x3 - DIV20 0x4 - DIV32 0x5 - DIV…
14414 …0_TOP_RESERVEDREGISTER700_RESERVEDFIELD210_K2_E5 (0x1<<7) // Reserved
14415 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER700_RESERVEDFIELD210_K2_E5_SHIFT 7
14429 …to the half-rate TX clock path to provide visibility at the TX driver output. 0x0 - mission mode …
14431 …CMU macro to all lanes macros. 0x0 - DIV1 0x1 - DIV2 0x2 - DIV4 0x3 - DIV5 0x4 - DIV8 0x5 - DIV10…
14473 … (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indica…
14477 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14478 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14480 … (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro…
14515 … (0x1<<0) // CMU PLL regulator vddha setting. 0x0 - vddha is 1.5V nominal 0x1 - vddha …
14639 …0_PLL_RESERVEDREGISTER755_RESERVEDFIELD282_K2_E5 (0x1<<7) // Reserved
14640 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER755_RESERVEDFIELD282_K2_E5_SHIFT 7
14667 …0_PLL_RESERVEDREGISTER765_RESERVEDFIELD290_K2_E5 (0x1<<7) // Reserved
14668 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER765_RESERVEDFIELD290_K2_E5_SHIFT 7
14670 … (0x1<<0) // CMU PLL lock detector status. 0x0 - CMU PLL is not locked 0x1 - CMU PL…
14701 …0_PLL_RESERVEDREGISTER776_RESERVEDFIELD306_K2_E5 (0x1<<7) // Reserved
14702 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER776_RESERVEDFIELD306_K2_E5_SHIFT 7
14910 … (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indica…
14914 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14915 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14917 … (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro…
14950 … (0x1<<0) // Select the reference clock. 0 - clk_ref 1- clk_pllref
15076 …_RPLL_RESERVEDREGISTER871_RESERVEDFIELD414_K2_E5 (0x1<<7) // Reserved
15077 …HY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER871_RESERVEDFIELD414_K2_E5_SHIFT 7
15110 …_RPLL_FRACN_CTRL4_RESERVEDFIELD417_K2_E5 (0x1<<7) // Reserved
15111 …HY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL4_RESERVEDFIELD417_K2_E5_SHIFT 7
15204 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
15206 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
15208 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
15210 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
15286 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
15290 …K2_E5 (0x1<<5) // Controls tx_en for Far-End-Digital FED loopbac…
15293 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
15336 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
15392 …P_RESERVEDREGISTER943_RESERVEDFIELD518_K2_E5 (0x1<<7) // Reserved
15393 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER943_RESERVEDFIELD518_K2_E5_SHIFT 7
15418 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15419 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15421 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
15488 … 0x0062fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
15490 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
15497 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
15595 …R_REFCLK_RESERVEDREGISTER1000_RESERVEDFIELD598_K2_E5 (0x1<<7) // Reserved
15596 …HY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1000_RESERVEDFIELD598_K2_E5_SHIFT 7
15600 …R_REFCLK_RESERVEDREGISTER1001_RESERVEDFIELD600_K2_E5 (0x1<<7) // Reserved
15601 …HY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1001_RESERVEDFIELD600_K2_E5_SHIFT 7
15655 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
15667 …EG_RESERVEDREGISTER1021_RESERVEDFIELD627_K2_E5 (0x1<<7) // Reserved
15668 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1021_RESERVEDFIELD627_K2_E5_SHIFT 7
15673 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
15677 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
15696 … 0x006650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
15697 … 0x006654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
15701 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
15704 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
15714 …G_BASE_PAGE1_NEXT_PAGE_K2_E5 (0x1<<7) // Next Page
15715 …HY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT 7
15720 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
15722 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
15724 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
15726 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
15728 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
15730 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
15732 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
15734 …H0_ABILITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology…
15735 …HY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT 7
15737 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
15739 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
15741 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
15743 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
15746 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
15753 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
15755 …x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
15758 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15760 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
15762 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15764 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
15766 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15768 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15770 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15772 …7) // Extended advertised FEC field 3. It requests Fire code FEC to be turned on when supported a…
15773 …HY_NW_IP_REG_LN0_ANEG_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT 7
15784 …EG_RESERVEDREGISTER1024_RESERVEDFIELD635_K2_E5 (0x1<<7) // Reserved
15785 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD635_K2_E5_SHIFT 7
15805 …EG_RESERVEDREGISTER1029_RESERVEDFIELD643_K2_E5 (0x1<<7) // Reserved
15806 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD643_K2_E5_SHIFT 7
15825 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
15828 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
15840 …E_PAGE1_NEXT_PAGE_K2_E5 (0x1<<7) // Link partner Nex…
15841 …HY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT 7
15846 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
15848 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
15850 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
15852 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
15854 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
15856 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
15858 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
15860 …BILITY_100G_KR4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 tech…
15861 …HY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT 7
15863 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
15865 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
15867 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
15869 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
15872 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
15879 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
15881 …k partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
15884 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15886 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
15888 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15890 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
15892 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15894 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15896 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15898 …7) // Link partner extended advertised FEC field 3. It requests Fire code FEC to be turned on whe…
15899 …HY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT 7
15910 …EG_RESERVEDREGISTER1032_RESERVEDFIELD655_K2_E5 (0x1<<7) // Reserved
15911 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD655_K2_E5_SHIFT 7
15931 …EG_RESERVEDREGISTER1037_RESERVEDFIELD663_K2_E5 (0x1<<7) // Reserved
15932 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD663_K2_E5_SHIFT 7
15949 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
15951 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
15953 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
15955 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
15957 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
15959 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
15961 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
15963 …_100G_KR4_K2_E5 (0x1<<7) // Resolution result for 100GBase-KR4…
15964 …HY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT 7
15966 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
15968 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
15970 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
15972 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
15974 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
15976 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
15978 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
15981 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
15994 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
15996 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
15998 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
16000 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
16002 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
16004 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
16006 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
16008 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
16009 …HY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_KR4_K2_E5_SHIFT 7
16011 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
16013 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
16015 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
16017 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
16019 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
16021 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
16130 …Q_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD717_K2_E5 (0x1<<7) // Reserved
16131 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD717_K2_E5_SHIFT 7
16165 …Q_REFCLK_RESERVEDREGISTER1075_RESERVEDFIELD733_K2_E5 (0x1<<7) // Reserved
16166 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1075_RESERVEDFIELD733_K2_E5_SHIFT 7
16210 …Q_REFCLK_RESERVEDREGISTER1086_RESERVEDFIELD750_K2_E5 (0x1<<7) // Reserved
16211 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1086_RESERVEDFIELD750_K2_E5_SHIFT 7
16369 …Q_REFCLK_RESERVEDREGISTER1116_RESERVEDFIELD813_K2_E5 (0x1<<7) // Reserved
16370 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1116_RESERVEDFIELD813_K2_E5_SHIFT 7
16405 …Q_REFCLK_RESERVEDREGISTER1121_RESERVEDFIELD824_K2_E5 (0x1<<7) // Reserved
16406 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1121_RESERVEDFIELD824_K2_E5_SHIFT 7
16442 …Q_REFCLK_RESERVEDREGISTER1130_RESERVEDFIELD838_K2_E5 (0x1<<7) // Reserved
16443 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1130_RESERVEDFIELD838_K2_E5_SHIFT 7
16627 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
16633 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
16739 …E_REFCLK_RESERVEDREGISTER1203_RESERVEDFIELD957_K2_E5 (0x1<<7) // Reserved
16740 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1203_RESERVEDFIELD957_K2_E5_SHIFT 7
16744 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
16748 …FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when…
16749 …HY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5_SHIFT 7
16777 …les updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
16779 …les updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
16781 …bles updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
16783 …bles updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
16785 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16787 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16789 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16791 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command execut…
16792 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP5_EN_K2_E5_SHIFT 7
16796 …TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16797 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT 7
16801 …TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16802 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT 7
16806 …TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16807 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT 7
16811 …TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16812 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT 7
16816 …TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16817 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT 7
16821 …TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16822 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT 7
16826 …TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16827 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT 7
16831 …TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16832 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT 7
16836 …TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16837 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT 7
16841 …TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16842 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT 7
16846 …TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16847 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT 7
16851 …TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16852 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT 7
16856 …TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16857 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT 7
16861 …TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16862 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT 7
16866 …TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16867 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT 7
16871 …TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16872 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT 7
16876 …TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16877 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT 7
16881 …TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16882 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT 7
16886 …TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16887 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5_SHIFT 7
16891 …TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16892 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5_SHIFT 7
16896 …TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16897 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5_SHIFT 7
16901 …TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16902 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5_SHIFT 7
16906 …TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16907 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5_SHIFT 7
16911 …TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
16912 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5_SHIFT 7
16928 …E_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD977_K2_E5 (0x1<<7) // Reserved
16929 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD977_K2_E5_SHIFT 7
16999 …E_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1003_K2_E5 (0x1<<7) // Reserved
17000 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1003_K2_E5_SHIFT 7
17023 …E_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1014_K2_E5 (0x1<<7) // Reserved
17024 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1014_K2_E5_SHIFT 7
17203 …2_E5 (0x1<<0) // Enables the run-length detection digi…
17205 … 0x007410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
17207 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
17209 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
17380 … 0x00781cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17381 … 0x007820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17416 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
17422 …L_FORCE_LFSR_WITH_RXDATA_K2_E5 (0x1<<7) // Forces the PRBS …
17423 …HY_NW_IP_REG_LN0_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_K2_E5_SHIFT 7
17439 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17440 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17441 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17442 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17444 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
17520 …ATURE_RESERVEDREGISTER1366_RESERVEDFIELD1191_K2_E5 (0x1<<7) // Reserved
17521 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1191_K2_E5_SHIFT 7
17590 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
17592 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
17613 …ATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1221_K2_E5 (0x1<<7) // Reserved
17614 …HY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1221_K2_E5_SHIFT 7
17651 …ATURE_RESERVEDREGISTER1378_RESERVEDFIELD1234_K2_E5 (0x1<<7) // Reserved
17652 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1234_K2_E5_SHIFT 7
17665 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
17794 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
17799 … 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + x^4 + x^6 + x^7 + x^11
17806 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
17810 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
17814 …ICIENT_UPDATE_CTRL_PRESET_K2_E5 (0x1<<7) // Coefficient upda…
17815 …HY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_K2_E5_SHIFT 7
17817 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
17821 …E5 (0x3<<4) // Status report field for pre-cursor tap.
17841 … 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + x^4 + x^6 + x^7 + x^11
17864 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
17868 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
17872 …ICIENT_UPDATE_STATUS_PRESET_K2_E5 (0x1<<7) // Received coeffic…
17873 …HY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_K2_E5_SHIFT 7
17875 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
17879 … (0x3<<4) // Received status report field for pre-cursor tap.
17883 …T_STATUS_DME_ERROR_K2_E5 (0x1<<7) // Indicates differ…
17884 …HY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_DME_ERROR_K2_E5_SHIFT 7
17886 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
17888 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
17890 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
17892 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
17968 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
17972 …K2_E5 (0x1<<5) // Controls tx_en for Far-End-Digital FED loopbac…
17975 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
18018 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
18074 …P_RESERVEDREGISTER1427_RESERVEDFIELD1332_K2_E5 (0x1<<7) // Reserved
18075 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1427_RESERVEDFIELD1332_K2_E5_SHIFT 7
18100 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18101 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18103 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
18170 … 0x0082fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
18172 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
18179 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
18277 …R_REFCLK_RESERVEDREGISTER1484_RESERVEDFIELD1412_K2_E5 (0x1<<7) // Reserved
18278 …HY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1484_RESERVEDFIELD1412_K2_E5_SHIFT 7
18282 …R_REFCLK_RESERVEDREGISTER1485_RESERVEDFIELD1414_K2_E5 (0x1<<7) // Reserved
18283 …HY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1485_RESERVEDFIELD1414_K2_E5_SHIFT 7
18337 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
18349 …EG_RESERVEDREGISTER1505_RESERVEDFIELD1441_K2_E5 (0x1<<7) // Reserved
18350 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1505_RESERVEDFIELD1441_K2_E5_SHIFT 7
18355 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
18359 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
18378 … 0x008650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
18379 … 0x008654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
18383 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
18386 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
18396 …G_BASE_PAGE1_NEXT_PAGE_K2_E5 (0x1<<7) // Next Page
18397 …HY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT 7
18402 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
18404 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
18406 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
18408 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
18410 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
18412 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
18414 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
18416 …H0_ABILITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology…
18417 …HY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT 7
18419 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
18421 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
18423 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
18425 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
18428 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
18435 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
18437 …x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
18440 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18442 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
18444 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18446 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
18448 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18450 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18452 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18454 …7) // Extended advertised FEC field 3. It requests Fire code FEC to be turned on when supported a…
18455 …HY_NW_IP_REG_LN1_ANEG_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT 7
18466 …EG_RESERVEDREGISTER1508_RESERVEDFIELD1449_K2_E5 (0x1<<7) // Reserved
18467 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1449_K2_E5_SHIFT 7
18487 …EG_RESERVEDREGISTER1513_RESERVEDFIELD1457_K2_E5 (0x1<<7) // Reserved
18488 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1457_K2_E5_SHIFT 7
18507 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
18510 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
18522 …E_PAGE1_NEXT_PAGE_K2_E5 (0x1<<7) // Link partner Nex…
18523 …HY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT 7
18528 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
18530 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
18532 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
18534 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
18536 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
18538 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
18540 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
18542 …BILITY_100G_KR4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 tech…
18543 …HY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT 7
18545 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
18547 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
18549 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
18551 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
18554 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
18561 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
18563 …k partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
18566 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18568 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
18570 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18572 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
18574 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18576 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18578 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18580 …7) // Link partner extended advertised FEC field 3. It requests Fire code FEC to be turned on whe…
18581 …HY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT 7
18592 …EG_RESERVEDREGISTER1516_RESERVEDFIELD1469_K2_E5 (0x1<<7) // Reserved
18593 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1469_K2_E5_SHIFT 7
18613 …EG_RESERVEDREGISTER1521_RESERVEDFIELD1477_K2_E5 (0x1<<7) // Reserved
18614 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1477_K2_E5_SHIFT 7
18631 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
18633 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
18635 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
18637 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
18639 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
18641 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
18643 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
18645 …_100G_KR4_K2_E5 (0x1<<7) // Resolution result for 100GBase-KR4…
18646 …HY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT 7
18648 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
18650 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
18652 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
18654 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
18656 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
18658 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
18660 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
18663 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
18676 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
18678 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
18680 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
18682 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
18684 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
18686 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
18688 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
18690 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
18691 …HY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_KR4_K2_E5_SHIFT 7
18693 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
18695 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
18697 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
18699 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
18701 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
18703 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
18812 …Q_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1531_K2_E5 (0x1<<7) // Reserved
18813 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1531_K2_E5_SHIFT 7
18847 …Q_REFCLK_RESERVEDREGISTER1559_RESERVEDFIELD1547_K2_E5 (0x1<<7) // Reserved
18848 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1559_RESERVEDFIELD1547_K2_E5_SHIFT 7
18892 …Q_REFCLK_RESERVEDREGISTER1570_RESERVEDFIELD1564_K2_E5 (0x1<<7) // Reserved
18893 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1570_RESERVEDFIELD1564_K2_E5_SHIFT 7
19051 …Q_REFCLK_RESERVEDREGISTER1600_RESERVEDFIELD1627_K2_E5 (0x1<<7) // Reserved
19052 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1600_RESERVEDFIELD1627_K2_E5_SHIFT 7
19087 …Q_REFCLK_RESERVEDREGISTER1605_RESERVEDFIELD1638_K2_E5 (0x1<<7) // Reserved
19088 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1605_RESERVEDFIELD1638_K2_E5_SHIFT 7
19124 …Q_REFCLK_RESERVEDREGISTER1614_RESERVEDFIELD1652_K2_E5 (0x1<<7) // Reserved
19125 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1614_RESERVEDFIELD1652_K2_E5_SHIFT 7
19309 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
19315 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
19421 …E_REFCLK_RESERVEDREGISTER1687_RESERVEDFIELD1771_K2_E5 (0x1<<7) // Reserved
19422 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1687_RESERVEDFIELD1771_K2_E5_SHIFT 7
19426 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
19430 …FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when…
19431 …HY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5_SHIFT 7
19459 …les updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
19461 …les updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
19463 …bles updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
19465 …bles updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
19467 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19469 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19471 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19473 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command execut…
19474 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP5_EN_K2_E5_SHIFT 7
19478 …TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19479 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT 7
19483 …TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19484 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT 7
19488 …TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19489 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT 7
19493 …TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19494 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT 7
19498 …TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19499 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT 7
19503 …TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19504 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT 7
19508 …TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19509 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT 7
19513 …TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19514 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT 7
19518 …TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19519 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT 7
19523 …TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19524 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT 7
19528 …TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19529 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT 7
19533 …TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19534 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT 7
19538 …TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19539 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT 7
19543 …TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19544 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT 7
19548 …TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19549 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT 7
19553 …TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19554 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT 7
19558 …TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19559 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT 7
19563 …TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19564 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT 7
19568 …TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19569 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5_SHIFT 7
19573 …TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19574 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5_SHIFT 7
19578 …TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19579 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5_SHIFT 7
19583 …TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19584 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5_SHIFT 7
19588 …TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19589 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5_SHIFT 7
19593 …TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
19594 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5_SHIFT 7
19610 …E_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1791_K2_E5 (0x1<<7) // Reserved
19611 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1791_K2_E5_SHIFT 7
19681 …E_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1817_K2_E5 (0x1<<7) // Reserved
19682 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1817_K2_E5_SHIFT 7
19705 …E_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1828_K2_E5 (0x1<<7) // Reserved
19706 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1828_K2_E5_SHIFT 7
19885 …2_E5 (0x1<<0) // Enables the run-length detection digi…
19887 … 0x009410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
19889 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
19891 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
20062 … 0x00981cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20063 … 0x009820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20098 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
20104 …L_FORCE_LFSR_WITH_RXDATA_K2_E5 (0x1<<7) // Forces the PRBS …
20105 …HY_NW_IP_REG_LN1_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_K2_E5_SHIFT 7
20121 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20122 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20123 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20124 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20126 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
20202 …ATURE_RESERVEDREGISTER1850_RESERVEDFIELD2005_K2_E5 (0x1<<7) // Reserved
20203 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2005_K2_E5_SHIFT 7
20272 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
20274 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
20295 …ATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2035_K2_E5 (0x1<<7) // Reserved
20296 …HY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2035_K2_E5_SHIFT 7
20333 …ATURE_RESERVEDREGISTER1862_RESERVEDFIELD2048_K2_E5 (0x1<<7) // Reserved
20334 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2048_K2_E5_SHIFT 7
20347 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
20476 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
20481 … 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + x^4 + x^6 + x^7 + x^11
20488 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
20492 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
20496 …ICIENT_UPDATE_CTRL_PRESET_K2_E5 (0x1<<7) // Coefficient upda…
20497 …HY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_K2_E5_SHIFT 7
20499 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
20503 …E5 (0x3<<4) // Status report field for pre-cursor tap.
20523 … 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + x^4 + x^6 + x^7 + x^11
20546 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
20550 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
20554 …ICIENT_UPDATE_STATUS_PRESET_K2_E5 (0x1<<7) // Received coeffic…
20555 …HY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_K2_E5_SHIFT 7
20557 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
20561 … (0x3<<4) // Received status report field for pre-cursor tap.
20565 …T_STATUS_DME_ERROR_K2_E5 (0x1<<7) // Indicates differ…
20566 …HY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_DME_ERROR_K2_E5_SHIFT 7
20568 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
20570 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
20572 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
20574 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
20650 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
20654 …K2_E5 (0x1<<5) // Controls tx_en for Far-End-Digital FED loopbac…
20657 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
20700 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
20756 …P_RESERVEDREGISTER1911_RESERVEDFIELD2146_K2_E5 (0x1<<7) // Reserved
20757 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1911_RESERVEDFIELD2146_K2_E5_SHIFT 7
20782 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20783 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20785 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
20852 … 0x00a2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
20854 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
20861 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
20959 …R_REFCLK_RESERVEDREGISTER1968_RESERVEDFIELD2226_K2_E5 (0x1<<7) // Reserved
20960 …HY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1968_RESERVEDFIELD2226_K2_E5_SHIFT 7
20964 …R_REFCLK_RESERVEDREGISTER1969_RESERVEDFIELD2228_K2_E5 (0x1<<7) // Reserved
20965 …HY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1969_RESERVEDFIELD2228_K2_E5_SHIFT 7
21019 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
21031 …EG_RESERVEDREGISTER1989_RESERVEDFIELD2255_K2_E5 (0x1<<7) // Reserved
21032 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1989_RESERVEDFIELD2255_K2_E5_SHIFT 7
21037 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
21041 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
21060 … 0x00a650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
21061 … 0x00a654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
21065 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
21068 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
21078 …G_BASE_PAGE1_NEXT_PAGE_K2_E5 (0x1<<7) // Next Page
21079 …HY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT 7
21084 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
21086 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
21088 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
21090 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
21092 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
21094 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
21096 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
21098 …H0_ABILITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology…
21099 …HY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT 7
21101 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
21103 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
21105 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
21107 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
21110 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
21117 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
21119 …x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
21122 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21124 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
21126 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21128 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
21130 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21132 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
21134 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21136 …7) // Extended advertised FEC field 3. It requests Fire code FEC to be turned on when supported a…
21137 …HY_NW_IP_REG_LN2_ANEG_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT 7
21148 …EG_RESERVEDREGISTER1992_RESERVEDFIELD2263_K2_E5 (0x1<<7) // Reserved
21149 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2263_K2_E5_SHIFT 7
21169 …EG_RESERVEDREGISTER1997_RESERVEDFIELD2271_K2_E5 (0x1<<7) // Reserved
21170 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2271_K2_E5_SHIFT 7
21189 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
21192 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
21204 …E_PAGE1_NEXT_PAGE_K2_E5 (0x1<<7) // Link partner Nex…
21205 …HY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT 7
21210 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
21212 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
21214 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
21216 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
21218 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
21220 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
21222 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
21224 …BILITY_100G_KR4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 tech…
21225 …HY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT 7
21227 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
21229 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
21231 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
21233 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
21236 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
21243 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
21245 …k partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
21248 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21250 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
21252 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21254 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
21256 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21258 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
21260 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21262 …7) // Link partner extended advertised FEC field 3. It requests Fire code FEC to be turned on whe…
21263 …HY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT 7
21274 …EG_RESERVEDREGISTER2000_RESERVEDFIELD2283_K2_E5 (0x1<<7) // Reserved
21275 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2283_K2_E5_SHIFT 7
21295 …EG_RESERVEDREGISTER2005_RESERVEDFIELD2291_K2_E5 (0x1<<7) // Reserved
21296 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2291_K2_E5_SHIFT 7
21313 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
21315 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
21317 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
21319 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
21321 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
21323 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
21325 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
21327 …_100G_KR4_K2_E5 (0x1<<7) // Resolution result for 100GBase-KR4…
21328 …HY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT 7
21330 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
21332 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
21334 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
21336 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
21338 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
21340 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
21342 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
21345 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
21358 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
21360 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
21362 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
21364 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
21366 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
21368 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
21370 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
21372 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
21373 …HY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_KR4_K2_E5_SHIFT 7
21375 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
21377 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
21379 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
21381 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
21383 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
21385 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
21494 …Q_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2345_K2_E5 (0x1<<7) // Reserved
21495 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2345_K2_E5_SHIFT 7
21529 …Q_REFCLK_RESERVEDREGISTER2043_RESERVEDFIELD2361_K2_E5 (0x1<<7) // Reserved
21530 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2043_RESERVEDFIELD2361_K2_E5_SHIFT 7
21574 …Q_REFCLK_RESERVEDREGISTER2054_RESERVEDFIELD2378_K2_E5 (0x1<<7) // Reserved
21575 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2054_RESERVEDFIELD2378_K2_E5_SHIFT 7
21733 …Q_REFCLK_RESERVEDREGISTER2084_RESERVEDFIELD2441_K2_E5 (0x1<<7) // Reserved
21734 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2084_RESERVEDFIELD2441_K2_E5_SHIFT 7
21769 …Q_REFCLK_RESERVEDREGISTER2089_RESERVEDFIELD2452_K2_E5 (0x1<<7) // Reserved
21770 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2089_RESERVEDFIELD2452_K2_E5_SHIFT 7
21806 …Q_REFCLK_RESERVEDREGISTER2098_RESERVEDFIELD2466_K2_E5 (0x1<<7) // Reserved
21807 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2098_RESERVEDFIELD2466_K2_E5_SHIFT 7
21991 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
21997 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
22103 …E_REFCLK_RESERVEDREGISTER2171_RESERVEDFIELD2585_K2_E5 (0x1<<7) // Reserved
22104 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2171_RESERVEDFIELD2585_K2_E5_SHIFT 7
22108 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
22112 …FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when…
22113 …HY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5_SHIFT 7
22141 …les updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
22143 …les updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
22145 …bles updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
22147 …bles updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
22149 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22151 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22153 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22155 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command execut…
22156 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP5_EN_K2_E5_SHIFT 7
22160 …TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22161 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT 7
22165 …TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22166 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT 7
22170 …TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22171 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT 7
22175 …TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22176 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT 7
22180 …TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22181 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT 7
22185 …TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22186 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT 7
22190 …TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22191 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT 7
22195 …TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22196 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT 7
22200 …TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22201 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT 7
22205 …TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22206 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT 7
22210 …TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22211 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT 7
22215 …TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22216 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT 7
22220 …TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22221 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT 7
22225 …TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22226 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT 7
22230 …TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22231 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT 7
22235 …TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22236 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT 7
22240 …TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22241 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT 7
22245 …TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22246 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT 7
22250 …TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22251 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5_SHIFT 7
22255 …TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22256 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5_SHIFT 7
22260 …TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22261 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5_SHIFT 7
22265 …TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22266 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5_SHIFT 7
22270 …TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22271 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5_SHIFT 7
22275 …TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
22276 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5_SHIFT 7
22292 …E_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2605_K2_E5 (0x1<<7) // Reserved
22293 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2605_K2_E5_SHIFT 7
22363 …E_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2631_K2_E5 (0x1<<7) // Reserved
22364 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2631_K2_E5_SHIFT 7
22387 …E_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2642_K2_E5 (0x1<<7) // Reserved
22388 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2642_K2_E5_SHIFT 7
22567 …2_E5 (0x1<<0) // Enables the run-length detection digi…
22569 … 0x00b410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
22571 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
22573 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
22744 … 0x00b81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22745 … 0x00b820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22780 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
22786 …L_FORCE_LFSR_WITH_RXDATA_K2_E5 (0x1<<7) // Forces the PRBS …
22787 …HY_NW_IP_REG_LN2_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_K2_E5_SHIFT 7
22803 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22804 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22805 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22806 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22808 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
22884 …ATURE_RESERVEDREGISTER2334_RESERVEDFIELD2819_K2_E5 (0x1<<7) // Reserved
22885 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2819_K2_E5_SHIFT 7
22954 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
22956 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
22977 …ATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2849_K2_E5 (0x1<<7) // Reserved
22978 …HY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2849_K2_E5_SHIFT 7
23015 …ATURE_RESERVEDREGISTER2346_RESERVEDFIELD2862_K2_E5 (0x1<<7) // Reserved
23016 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2862_K2_E5_SHIFT 7
23029 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
23158 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
23163 … 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + x^4 + x^6 + x^7 + x^11
23170 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
23174 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
23178 …ICIENT_UPDATE_CTRL_PRESET_K2_E5 (0x1<<7) // Coefficient upda…
23179 …HY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_K2_E5_SHIFT 7
23181 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
23185 …E5 (0x3<<4) // Status report field for pre-cursor tap.
23205 … 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + x^4 + x^6 + x^7 + x^11
23228 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
23232 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
23236 …ICIENT_UPDATE_STATUS_PRESET_K2_E5 (0x1<<7) // Received coeffic…
23237 …HY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_K2_E5_SHIFT 7
23239 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
23243 … (0x3<<4) // Received status report field for pre-cursor tap.
23247 …T_STATUS_DME_ERROR_K2_E5 (0x1<<7) // Indicates differ…
23248 …HY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_DME_ERROR_K2_E5_SHIFT 7
23250 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
23252 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
23254 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
23256 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission …
23332 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
23336 …K2_E5 (0x1<<5) // Controls tx_en for Far-End-Digital FED loopbac…
23339 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
23382 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
23438 …P_RESERVEDREGISTER2395_RESERVEDFIELD2960_K2_E5 (0x1<<7) // Reserved
23439 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2395_RESERVEDFIELD2960_K2_E5_SHIFT 7
23464 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23465 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23467 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
23534 … 0x00c2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
23536 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
23543 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
23641 …R_REFCLK_RESERVEDREGISTER2452_RESERVEDFIELD3040_K2_E5 (0x1<<7) // Reserved
23642 …HY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2452_RESERVEDFIELD3040_K2_E5_SHIFT 7
23646 …R_REFCLK_RESERVEDREGISTER2453_RESERVEDFIELD3042_K2_E5 (0x1<<7) // Reserved
23647 …HY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2453_RESERVEDFIELD3042_K2_E5_SHIFT 7
23701 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
23713 …EG_RESERVEDREGISTER2473_RESERVEDFIELD3069_K2_E5 (0x1<<7) // Reserved
23714 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2473_RESERVEDFIELD3069_K2_E5_SHIFT 7
23719 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
23723 …he ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks …
23742 … 0x00c650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
23743 … 0x00c654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
23747 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
23750 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
23760 …G_BASE_PAGE1_NEXT_PAGE_K2_E5 (0x1<<7) // Next Page
23761 …HY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT 7
23766 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
23768 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
23770 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
23772 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
23774 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
23776 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
23778 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
23780 …H0_ABILITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology…
23781 …HY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT 7
23783 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
23785 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
23787 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
23789 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
23792 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
23799 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
23801 …x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
23804 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23806 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
23808 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23810 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
23812 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23814 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
23816 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23818 …7) // Extended advertised FEC field 3. It requests Fire code FEC to be turned on when supported a…
23819 …HY_NW_IP_REG_LN3_ANEG_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT 7
23830 …EG_RESERVEDREGISTER2476_RESERVEDFIELD3077_K2_E5 (0x1<<7) // Reserved
23831 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3077_K2_E5_SHIFT 7
23851 …EG_RESERVEDREGISTER2481_RESERVEDFIELD3085_K2_E5 (0x1<<7) // Reserved
23852 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3085_K2_E5_SHIFT 7
23871 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
23874 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
23886 …E_PAGE1_NEXT_PAGE_K2_E5 (0x1<<7) // Link partner Nex…
23887 …HY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_NEXT_PAGE_K2_E5_SHIFT 7
23892 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
23894 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
23896 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
23898 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
23900 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
23902 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
23904 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
23906 …BILITY_100G_KR4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 tech…
23907 …HY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT 7
23909 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
23911 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
23913 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
23915 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
23918 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
23925 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. …
23927 …k partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25…
23930 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23932 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
23934 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23936 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
23938 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23940 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
23942 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23944 …7) // Link partner extended advertised FEC field 3. It requests Fire code FEC to be turned on whe…
23945 …HY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_FC_FEC_REQ_K2_E5_SHIFT 7
23956 …EG_RESERVEDREGISTER2484_RESERVEDFIELD3097_K2_E5 (0x1<<7) // Reserved
23957 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3097_K2_E5_SHIFT 7
23977 …EG_RESERVEDREGISTER2489_RESERVEDFIELD3105_K2_E5 (0x1<<7) // Reserved
23978 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3105_K2_E5_SHIFT 7
23995 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
23997 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
23999 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
24001 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
24003 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
24005 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
24007 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
24009 …_100G_KR4_K2_E5 (0x1<<7) // Resolution result for 100GBase-KR4…
24010 …HY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_K2_E5_SHIFT 7
24012 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
24014 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
24016 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
24018 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
24020 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
24022 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
24024 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
24027 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
24040 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
24042 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
24044 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
24046 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
24048 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
24050 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
24052 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
24054 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
24055 …HY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_KR4_K2_E5_SHIFT 7
24057 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
24059 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
24061 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
24063 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
24065 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
24067 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
24176 …Q_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3159_K2_E5 (0x1<<7) // Reserved
24177 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3159_K2_E5_SHIFT 7
24211 …Q_REFCLK_RESERVEDREGISTER2527_RESERVEDFIELD3175_K2_E5 (0x1<<7) // Reserved
24212 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2527_RESERVEDFIELD3175_K2_E5_SHIFT 7
24256 …Q_REFCLK_RESERVEDREGISTER2538_RESERVEDFIELD3192_K2_E5 (0x1<<7) // Reserved
24257 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2538_RESERVEDFIELD3192_K2_E5_SHIFT 7
24415 …Q_REFCLK_RESERVEDREGISTER2568_RESERVEDFIELD3255_K2_E5 (0x1<<7) // Reserved
24416 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2568_RESERVEDFIELD3255_K2_E5_SHIFT 7
24451 …Q_REFCLK_RESERVEDREGISTER2573_RESERVEDFIELD3266_K2_E5 (0x1<<7) // Reserved
24452 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2573_RESERVEDFIELD3266_K2_E5_SHIFT 7
24488 …Q_REFCLK_RESERVEDREGISTER2582_RESERVEDFIELD3280_K2_E5 (0x1<<7) // Reserved
24489 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2582_RESERVEDFIELD3280_K2_E5_SHIFT 7
24673 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
24679 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
24785 …E_REFCLK_RESERVEDREGISTER2655_RESERVEDFIELD3399_K2_E5 (0x1<<7) // Reserved
24786 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2655_RESERVEDFIELD3399_K2_E5_SHIFT 7
24790 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
24794 …FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when…
24795 …HY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_K2_E5_SHIFT 7
24823 …les updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
24825 …les updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
24827 …bles updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
24829 …bles updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
24831 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24833 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24835 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24837 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command execut…
24838 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP5_EN_K2_E5_SHIFT 7
24842 …TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24843 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT 7
24847 …TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24848 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT 7
24852 …TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24853 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT 7
24857 …TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24858 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT 7
24862 …TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24863 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT 7
24867 …TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24868 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT 7
24872 …TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24873 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT 7
24877 …TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24878 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT 7
24882 …TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24883 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT 7
24887 …TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24888 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT 7
24892 …TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24893 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_K2_E5_SHIFT 7
24897 …TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24898 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_K2_E5_SHIFT 7
24902 …TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24903 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_K2_E5_SHIFT 7
24907 …TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24908 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_K2_E5_SHIFT 7
24912 …TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24913 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_K2_E5_SHIFT 7
24917 …TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24918 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_K2_E5_SHIFT 7
24922 …TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24923 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_K2_E5_SHIFT 7
24927 …TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24928 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_K2_E5_SHIFT 7
24932 …TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24933 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_K2_E5_SHIFT 7
24937 …TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24938 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_K2_E5_SHIFT 7
24942 …TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24943 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_K2_E5_SHIFT 7
24947 …TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24948 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_K2_E5_SHIFT 7
24952 …TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24953 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_K2_E5_SHIFT 7
24957 …TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5 (0x1<<7) // polarity 0 = neg…
24958 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_K2_E5_SHIFT 7
24974 …E_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3419_K2_E5 (0x1<<7) // Reserved
24975 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3419_K2_E5_SHIFT 7
25045 …E_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3445_K2_E5 (0x1<<7) // Reserved
25046 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3445_K2_E5_SHIFT 7
25069 …E_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3456_K2_E5 (0x1<<7) // Reserved
25070 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3456_K2_E5_SHIFT 7
25249 …2_E5 (0x1<<0) // Enables the run-length detection digi…
25251 … 0x00d410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
25253 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
25255 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
25426 … 0x00d81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25427 … 0x00d820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25462 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
25468 …L_FORCE_LFSR_WITH_RXDATA_K2_E5 (0x1<<7) // Forces the PRBS …
25469 …HY_NW_IP_REG_LN3_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_K2_E5_SHIFT 7
25485 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25486 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25487 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25488 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25490 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
25566 …ATURE_RESERVEDREGISTER2818_RESERVEDFIELD3633_K2_E5 (0x1<<7) // Reserved
25567 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3633_K2_E5_SHIFT 7
25636 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
25638 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
25659 …ATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3663_K2_E5 (0x1<<7) // Reserved
25660 …HY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3663_K2_E5_SHIFT 7
25697 …ATURE_RESERVEDREGISTER2830_RESERVEDFIELD3676_K2_E5 (0x1<<7) // Reserved
25698 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3676_K2_E5_SHIFT 7
25711 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
25840 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
25845 … 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + x^4 + x^6 + x^7 + x^11
25852 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
25856 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
25860 …ICIENT_UPDATE_CTRL_PRESET_K2_E5 (0x1<<7) // Coefficient upda…
25861 …HY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_K2_E5_SHIFT 7
25863 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
25867 …E5 (0x3<<4) // Status report field for pre-cursor tap.
25887 … 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + x^4 + x^6 + x^7 + x^11
25910 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
25914 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
25918 …ICIENT_UPDATE_STATUS_PRESET_K2_E5 (0x1<<7) // Received coeffic…
25919 …HY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_K2_E5_SHIFT 7
25921 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
25925 … (0x3<<4) // Received status report field for pre-cursor tap.
25929 …T_STATUS_DME_ERROR_K2_E5 (0x1<<7) // Indicates differ…
25930 …HY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_DME_ERROR_K2_E5_SHIFT 7
25937 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
25943 …0_X1_BURNIN_REF_LIFE_CLK_SEL_O_K2_E5 (0x1<<7) // Reference clock …
25944 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_BURNIN_REF_LIFE_CLK_SEL_O_K2_E5_SHIFT 7
25950 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
25953 …AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
25965 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25966 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25967 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25969 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25971 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
25972 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
25973 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
25974 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
25975 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
25976 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
25977 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
25978 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
25979 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
25980 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
25981 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
25982 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
25983 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
25984 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
25985 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
25986 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
25999 …0_X27_GCFSM_CMU_PMA_READ_OVR_O_K2_E5 (0x1<<7) // GCFSM pma_read_o…
26000 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_READ_OVR_O_K2_E5_SHIFT 7
26004 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
26006 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
26008 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
26010 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26013 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
26015 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26017 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26019 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
26022 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26024 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26026 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26028 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26031 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
26033 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26035 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26037 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
26040 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
26042 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26044 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26096 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
26104 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
26115 …0_X95_AHB_PMA_CM_C1_SEL_O_K2_E5 (0x1<<7) // CMU LF C1 cap se…
26116 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_C1_SEL_O_K2_E5_SHIFT 7
26124 …0_X96_AHB_PMA_CM_BGSTART_BYP_O_K2_E5 (0x1<<7) // Bandgap startup …
26125 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_BGSTART_BYP_O_K2_E5_SHIFT 7
26138 …2_E5 (0x1<<2) // Override enable for overriding N-div value
26157 …1_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
26172 …0_X108_PMA_REFCLK_SEL_OVR_O_K2_E5 (0x1<<7) // Reference clock …
26173 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_SEL_OVR_O_K2_E5_SHIFT 7
26187 …0_X109_PMA_REFCLK_QFWD_R_O_K2_E5 (0x1<<7) // Override for pri…
26188 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_R_O_K2_E5_SHIFT 7
26207 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
26214 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
26216 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
26218 …0_X118_FRACN_FBK_CLK_DIV_SEL_O_K2_E5 (0x1<<7) // Clock divider fo…
26219 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_DIV_SEL_O_K2_E5_SHIFT 7
26227 …0_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_K2_E5 (0x1<<7) // override enable …
26228 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_K2_E5_SHIFT 7
26229 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
26231 …P_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
26261 … 0x000200UL //Access:RW DataWidth:0x8 // Bit 7:5 amux_ena[2:0] Bit …
26263 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
26267 … 0x000208UL //Access:R DataWidth:0x8 // Snapshot of digital test bus data [7:0]
26271 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
26273 …BUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
26287 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
26332 …0_X191_RESET_CMU_FL_IDDQ_SETVAL_O_K2_E5 (0x1<<7) // MSM Function IDD…
26333 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_RESET_CMU_FL_IDDQ_SETVAL_O_K2_E5_SHIFT 7
26349 …0_X192_LFI_EXTZERO_IDDQ_SETVAL_O_K2_E5 (0x1<<7) // MSM Function IDD…
26350 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_LFI_EXTZERO_IDDQ_SETVAL_O_K2_E5_SHIFT 7
26366 …_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_K2_E5 (0x1<<7) // Not used
26367 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_K2_E5_SHIFT 7
26383 …0_X194_RESET_CMU_FL_RST_SETVAL_O_K2_E5 (0x1<<7) // MSM Function RST…
26384 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_RESET_CMU_FL_RST_SETVAL_O_K2_E5_SHIFT 7
26400 …0_X195_LFI_EXTZERO_RST_SETVAL_O_K2_E5 (0x1<<7) // MSM Function RST…
26401 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_LFI_EXTZERO_RST_SETVAL_O_K2_E5_SHIFT 7
26417 …_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_K2_E5 (0x1<<7) // Not used
26418 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_K2_E5_SHIFT 7
26434 …0_X197_RESET_CMU_FL_NORM_SETVAL_O_K2_E5 (0x1<<7) // MSM Function NOR…
26435 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_RESET_CMU_FL_NORM_SETVAL_O_K2_E5_SHIFT 7
26451 …0_X198_LFI_EXTZERO_NORM_SETVAL_O_K2_E5 (0x1<<7) // MSM Function NOR…
26452 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_LFI_EXTZERO_NORM_SETVAL_O_K2_E5_SHIFT 7
26468 …_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_K2_E5 (0x1<<7) // Not used
26469 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_K2_E5_SHIFT 7
26485 …0_X200_RESET_CMU_FL_PD_SETVAL_O_K2_E5 (0x1<<7) // MSM Function POW…
26486 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_RESET_CMU_FL_PD_SETVAL_O_K2_E5_SHIFT 7
26502 …0_X201_LFI_EXTZERO_PD_SETVAL_O_K2_E5 (0x1<<7) // MSM Function POW…
26503 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_LFI_EXTZERO_PD_SETVAL_O_K2_E5_SHIFT 7
26519 …_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_K2_E5 (0x1<<7) // Not used
26520 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_K2_E5_SHIFT 7
26523 … 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b010 - pma_lX_rxb_iRecovered byte clock 3'b011 - ck_soc1_int…
26525 … (0x1<<3) // Clock divider for TX path branch 1 : 0-No division, 1- Divide by 2
26527 …h branch 2 clock : 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b011 - ck_soc1_int_root 3'b010,3'b100,3'b1…
26529 …_O_K2_E5 (0x1<<7) // Clock divider for TX path branch 2 : 0-No divi…
26530 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT 7
26532 …ck : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b0…
26534 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
26536 …ck : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b0…
26538 …_O_K2_E5 (0x1<<7) // Clock divider for RX path branch 2 : 0-No divi…
26539 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT 7
26541 …- qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmi…
26543 … (0x1<<3) // Clock divider for RX path branch 3 : 0-No division, 1- Divide by 2
26545 …- qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmi…
26547 …_O_K2_E5 (0x1<<7) // Clock divider for RX path branch 4 : 0-No divi…
26548 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5_SHIFT 7
26550 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
26552 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
26555 …0_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
26560 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
26562 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
26567 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
26569 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
26575 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
26577 … (0x1<<7) // Bist generator enable. 0 - Bist generator id…
26578 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_EN_O_K2_E5_SHIFT 7
26582 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
26584 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
26586 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26587 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26588 … 0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
26589 … 0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
26590 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
26592 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
26599 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
26605 …_1_X15_BIST_RX_CLOCK_ENABLE_K2_E5 (0x1<<7) // Active HIGH cloc…
26606 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_RX_CLOCK_ENABLE_K2_E5_SHIFT 7
26619 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
26620 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26621 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26622 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26623 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26631 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
26632 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
26633 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
26634 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
26635 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
26636 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
26637 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
26638 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
26639 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
26640 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
26641 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
26642 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
26643 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
26644 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
26645 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
26646 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
26647 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
26648 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
26649 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
26650 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
26655 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
26657 …E5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
26659 …_LOAD_OVR_K2_E5 (0x1<<7) // ICA Method PMA Load signal Override -…
26660 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5_SHIFT 7
26667 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
26673 …_1_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5 (0x1<<7) // GCFSM pma_read_o…
26674 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5_SHIFT 7
26684 … (0x3f<<2) // Bit 2: Override enable for msm_func Bits [7:3] : Override msm_fu…
26695 …_1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5 (0x1<<7) // Number of cycles…
26696 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5_SHIFT 7
26712 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
26714 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
26716 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
26720 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26721 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26722 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26724 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26726 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
26776 …_O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
26780 …_1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5 (0x1<<7) // RX FL calibratio…
26781 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5_SHIFT 7
26783 …_O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
26797 …_1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5 (0x1<<7) // CDR DivN clock d…
26798 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5_SHIFT 7
26810 …_1_X95_AHB_PMA_LN_RXDWN_O_K2_E5 (0x1<<7) // dfe_edge_by[0]. …
26811 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_RXDWN_O_K2_E5_SHIFT 7
26828 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
26830 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
26875 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
26877 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
26881 …_1_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5 (0x1<<7) // Debug feature, w…
26882 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5_SHIFT 7
26891 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
26894 … 0x0011f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
26906 …_1_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5 (0x1<<7) // This bit has sim…
26907 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5_SHIFT 7
26962 …_K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
26964 …K2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
26980 …_1_X145_CMP_OFFSET_AVG_EN_O_K2_E5 (0x1<<7) // CMP Offset Noise…
26981 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_EN_O_K2_E5_SHIFT 7
26990 …_1_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5 (0x1<<7) // Inverts the pola…
26991 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5_SHIFT 7
26995 …_1_X148_RXEQ_OVR_EN_O_K2_E5 (0x1<<7) // Override enable …
26996 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_EN_O_K2_E5_SHIFT 7
27000 …_1_X149_RXEQ_OVR_LATCH_O_K2_E5 (0x1<<7) // Override for DFE…
27001 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LATCH_O_K2_E5_SHIFT 7
27011 …_1_X150_DFE_TAP_OVR_EN_O_7_K2_E5 (0x1<<7) // DFE TAP override…
27012 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_OVR_EN_O_7_K2_E5_SHIFT 7
27020 …_1_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5 (0x1<<7) // DFE comparator c…
27021 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5_SHIFT 7
27046 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
27048 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
27060 …_1_X203_CDFE_LN_EI_EXIT_CAL_K2_E5 (0x1<<7) // EI exit cdfe cal…
27061 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_EI_EXIT_CAL_K2_E5_SHIFT 7
27073 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
27074 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
27075 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
27077 …_1_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5 (0x1<<7) // cdfe coarse dll …
27078 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5_SHIFT 7
27083 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
27084 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
27085 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
27086 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
27087 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
27214 …_1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5 (0x1<<7) // Register overrid…
27215 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5_SHIFT 7
27236 …_1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5 (0x1<<7) // Enables FW enabl…
27237 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5_SHIFT 7
27245 …_REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5 (0x1<<7) //
27246 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5_SHIFT 7
27359 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
27361 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27363 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27365 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27369 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
27372 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27374 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27376 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27378 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27380 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27382 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27387 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27389 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27397 …_1_X303_TXTERM_CAL_SEQ_EN_O_K2_E5 (0x1<<7) // Txterm calibrati…
27398 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_TXTERM_CAL_SEQ_EN_O_K2_E5_SHIFT 7
27407 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
27411 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
27415 …_1_X305_DEC_EN_O_K2_E5 (0x1<<7) // 8b/10b decoder e…
27416 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_DEC_EN_O_K2_E5_SHIFT 7
27425 …_1_X307_USB_MODE_K2_E5 (0x1<<7) // Signal Detect US…
27426 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_USB_MODE_K2_E5_SHIFT 7
27462 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
27464 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
27470 …_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5 (0x1<<7) // override value f…
27471 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5_SHIFT 7
27485 …_1_X326_LN_IN_OVR_O_49_K2_E5 (0x1<<7) // OOB detect enable
27486 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_49_K2_E5_SHIFT 7
27488 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
27498 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
27501 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
27503 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
27553 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
27554 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
27555 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
27556 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
27557 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
27558 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
27559 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
27560 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
27561 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
27562 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
27563 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
27564 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
27565 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
27566 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
27567 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
27568 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
27571 …nction. Varies depending on function number. Bits 15-7: Address of first command to run Bits: 6-…
27640 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
27641 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
27657 …CSR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O_K2_E5 (0x1<<7) // MSM Function IDD…
27658 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O_K2_E5_SHIFT 7
27674 …CSR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O_K2_E5 (0x1<<7) // MSM Function IDD…
27675 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O_K2_E5_SHIFT 7
27691 …CSR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MSM Function IDD…
27692 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
27717 …CSR_5_X147_MSM_SAPI_RST_PD_S2P_O_K2_E5 (0x1<<7) // MSM Function RES…
27718 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_S2P_O_K2_E5_SHIFT 7
27734 …CSR_5_X148_MSM_SAPI_RST_RESET_DFE_O_K2_E5 (0x1<<7) // MSM Function RES…
27735 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_DFE_O_K2_E5_SHIFT 7
27751 …CSR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MSM Function RES…
27752 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
27777 …CSR_5_X151_MSM_SAPI_NORM_PD_S2P_O_K2_E5 (0x1<<7) // MSM Function NOR…
27778 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_S2P_O_K2_E5_SHIFT 7
27794 …CSR_5_X152_MSM_SAPI_NORM_RESET_DFE_O_K2_E5 (0x1<<7) // MSM Function NOR…
27795 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_DFE_O_K2_E5_SHIFT 7
27811 …CSR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MSM Function NOR…
27812 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
27837 …CSR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O_K2_E5 (0x1<<7) // MSM Function PAR…
27838 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O_K2_E5_SHIFT 7
27854 …CSR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O_K2_E5 (0x1<<7) // MSM Function PAR…
27855 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O_K2_E5_SHIFT 7
27871 …CSR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MSM Function PAR…
27872 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
27897 …CSR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O_K2_E5 (0x1<<7) // MSM Function SLU…
27898 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O_K2_E5_SHIFT 7
27914 …CSR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O_K2_E5 (0x1<<7) // MSM Function SLU…
27915 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O_K2_E5_SHIFT 7
27931 …CSR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MSM Function SLU…
27932 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
27978 …_LOW_EN_O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a prog…
27980 …EQ_C1_FORCE_LOW_EN_O_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor do…
27981 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_C1_FORCE_LOW_EN_O_K2_E5_SHIFT 7
27998 … (0x1<<6) // Set all DFE calibration values to mid-scale instead of usin…
28000 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
28002 …ONT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
28004 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
28005 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
28006 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
28007 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
28008 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
28009 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
28010 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
28014 …ECAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration for { Tap…
28023 …ATE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
28054 …CSR_5_X234_QAHB_DFE_RAW_VALUE_O_K2_E5 (0x1<<7) // Testbus select f…
28055 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X234_QAHB_DFE_RAW_VALUE_O_K2_E5_SHIFT 7
28088 …CSR_5_X248_RXEQ_STEP_O_K2_E5 (0x1<<7) // Step calibration…
28089 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_O_K2_E5_SHIFT 7
28093 …CSR_5_X249_RXEQ_FLOOR_O_K2_E5 (0x1<<7) // Take the floor o…
28094 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_FLOOR_O_K2_E5_SHIFT 7
28133 …CSR_5_X261_DFE_SHADOW_OFST_RD_SEL_K2_E5 (0x1<<7) // DFE shadow offse…
28134 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_OFST_RD_SEL_K2_E5_SHIFT 7
28160 … 0x002c40UL //Access:RW DataWidth:0x8 // Training pattern for TxEQ adapt DFE tap1 cm1 [7:0]
28166 … 0x002c48UL //Access:RW DataWidth:0x8 // Training pattern for TxEQ adapt DFE tap1 c1 [7:0]
28173 …NE_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
28175 …ADAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
28356 …_REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O_K2_E5 (0x1<<7) //
28357 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O_K2_E5_SHIFT 7
28389 …CSR_5_X376_MSM_PIPE_RST_PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28390 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_S2P_O_K2_E5_SHIFT 7
28406 …CSR_5_X377_MSM_PIPE_RST_RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28407 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_DFE_O_K2_E5_SHIFT 7
28423 …CSR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28424 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
28449 …CSR_5_X380_MSM_PIPE_P0_PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28450 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_S2P_O_K2_E5_SHIFT 7
28466 …CSR_5_X381_MSM_PIPE_P0_RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28467 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_DFE_O_K2_E5_SHIFT 7
28483 …CSR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28484 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
28509 …CSR_5_X384_MSM_PIPE_P1_PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28510 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_S2P_O_K2_E5_SHIFT 7
28526 …CSR_5_X385_MSM_PIPE_P1_RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28527 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_DFE_O_K2_E5_SHIFT 7
28543 …CSR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28544 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
28569 …CSR_5_X388_MSM_PIPE_P2_PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28570 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_S2P_O_K2_E5_SHIFT 7
28586 …CSR_5_X389_MSM_PIPE_P2_RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28587 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_DFE_O_K2_E5_SHIFT 7
28603 …CSR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28604 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
28637 …E_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
28658 …_CSR_5_X407_LN3_OK_I_7_K2_E5 (0x1<<7) // Lane 3 OK Status
28659 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_OK_I_7_K2_E5_SHIFT 7
28723 …CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28724 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O_K2_E5_SHIFT 7
28740 …CSR_5_X484_MSM_PIPE_P1_0_PD_RA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28741 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_RA_O_K2_E5_SHIFT 7
28757 …CSR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28758 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O_K2_E5_SHIFT 7
28783 …CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28784 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O_K2_E5_SHIFT 7
28800 …CSR_5_X488_MSM_PIPE_P1_1_PD_RA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28801 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_RA_O_K2_E5_SHIFT 7
28817 …CSR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28818 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O_K2_E5_SHIFT 7
28843 …CSR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28844 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O_K2_E5_SHIFT 7
28860 …CSR_5_X492_MSM_PIPE_P1_2_PD_P2S_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28861 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_P2S_O_K2_E5_SHIFT 7
28877 …CSR_5_X493_MSM_PIPE_P1_2_CDR_EN_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
28878 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_CDR_EN_O_K2_E5_SHIFT 7
28901 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
28907 …_6_X1_BURNIN_REF_LIFE_CLK_SEL_O_K2_E5 (0x1<<7) // Reference clock …
28908 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_BURNIN_REF_LIFE_CLK_SEL_O_K2_E5_SHIFT 7
28914 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
28917 …_AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
28929 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28930 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28931 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28933 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28935 … 0x003028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
28936 … 0x00302cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
28937 … 0x003030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
28938 … 0x003034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
28939 … 0x003038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
28940 … 0x00303cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
28941 … 0x003040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
28942 … 0x003044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
28943 … 0x003048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
28944 … 0x00304cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
28945 … 0x003050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
28946 … 0x003054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
28947 … 0x003058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
28948 … 0x00305cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
28949 … 0x003060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
28950 … 0x003064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
28963 …_6_X27_GCFSM_CMU_PMA_READ_OVR_O_K2_E5 (0x1<<7) // GCFSM pma_read_o…
28964 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_READ_OVR_O_K2_E5_SHIFT 7
28968 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
28970 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
28972 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
28974 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28977 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
28979 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28981 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28983 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
28986 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28988 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28990 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28992 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28995 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
28997 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28999 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29001 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29004 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29006 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29008 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29060 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29068 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
29079 …_6_X95_AHB_PMA_CM_C1_SEL_O_K2_E5 (0x1<<7) // CMU LF C1 cap se…
29080 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_C1_SEL_O_K2_E5_SHIFT 7
29088 …_6_X96_AHB_PMA_CM_BGSTART_BYP_O_K2_E5 (0x1<<7) // Bandgap startup …
29089 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_BGSTART_BYP_O_K2_E5_SHIFT 7
29102 …K2_E5 (0x1<<2) // Override enable for overriding N-div value
29121 …01_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29136 …_6_X108_PMA_REFCLK_SEL_OVR_O_K2_E5 (0x1<<7) // Reference clock …
29137 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_PMA_REFCLK_SEL_OVR_O_K2_E5_SHIFT 7
29151 …_6_X109_PMA_REFCLK_QFWD_R_O_K2_E5 (0x1<<7) // Override for pri…
29152 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_QFWD_R_O_K2_E5_SHIFT 7
29171 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
29178 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29180 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29182 …_6_X118_FRACN_FBK_CLK_DIV_SEL_O_K2_E5 (0x1<<7) // Clock divider fo…
29183 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_FBK_CLK_DIV_SEL_O_K2_E5_SHIFT 7
29191 …_6_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_K2_E5 (0x1<<7) // override enable …
29192 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_K2_E5_SHIFT 7
29193 … 0x0031e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29195 …MP_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29227 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
29231 … 0x003208UL //Access:R DataWidth:0x8 // Snapshot of digital test bus data [7:0]
29235 … 0x003210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29237 …TBUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29251 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
29296 …_6_X191_RESET_CMU_FL_IDDQ_SETVAL_O_K2_E5 (0x1<<7) // MSM Function IDD…
29297 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_RESET_CMU_FL_IDDQ_SETVAL_O_K2_E5_SHIFT 7
29313 …_6_X192_LFI_EXTZERO_IDDQ_SETVAL_O_K2_E5 (0x1<<7) // MSM Function IDD…
29314 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_LFI_EXTZERO_IDDQ_SETVAL_O_K2_E5_SHIFT 7
29330 …_CMU1_CSR_6_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_K2_E5 (0x1<<7) // Not used
29331 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_K2_E5_SHIFT 7
29347 …_6_X194_RESET_CMU_FL_RST_SETVAL_O_K2_E5 (0x1<<7) // MSM Function RST…
29348 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_RESET_CMU_FL_RST_SETVAL_O_K2_E5_SHIFT 7
29364 …_6_X195_LFI_EXTZERO_RST_SETVAL_O_K2_E5 (0x1<<7) // MSM Function RST…
29365 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_LFI_EXTZERO_RST_SETVAL_O_K2_E5_SHIFT 7
29381 …_CMU1_CSR_6_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_K2_E5 (0x1<<7) // Not used
29382 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_K2_E5_SHIFT 7
29398 …_6_X197_RESET_CMU_FL_NORM_SETVAL_O_K2_E5 (0x1<<7) // MSM Function NOR…
29399 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_RESET_CMU_FL_NORM_SETVAL_O_K2_E5_SHIFT 7
29415 …_6_X198_LFI_EXTZERO_NORM_SETVAL_O_K2_E5 (0x1<<7) // MSM Function NOR…
29416 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_LFI_EXTZERO_NORM_SETVAL_O_K2_E5_SHIFT 7
29432 …_CMU1_CSR_6_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_K2_E5 (0x1<<7) // Not used
29433 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_K2_E5_SHIFT 7
29449 …_6_X200_RESET_CMU_FL_PD_SETVAL_O_K2_E5 (0x1<<7) // MSM Function POW…
29450 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_RESET_CMU_FL_PD_SETVAL_O_K2_E5_SHIFT 7
29466 …_6_X201_LFI_EXTZERO_PD_SETVAL_O_K2_E5 (0x1<<7) // MSM Function POW…
29467 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_LFI_EXTZERO_PD_SETVAL_O_K2_E5_SHIFT 7
29483 …_CMU1_CSR_6_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_K2_E5 (0x1<<7) // Not used
29484 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_K2_E5_SHIFT 7
29492 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
29498 …_X1_BURNIN_REF_LIFE_CLK_SEL_O_K2_E5 (0x1<<7) // Reference clock …
29499 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_BURNIN_REF_LIFE_CLK_SEL_O_K2_E5_SHIFT 7
29505 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
29508 …HB_PMA_CM_DIVNSEL_6_0_O_K2_E5 (0x7f<<0) // CMU N-divider setting
29520 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29521 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29522 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29524 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29526 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
29527 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
29528 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
29529 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
29530 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
29531 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
29532 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
29533 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
29534 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
29535 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
29536 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
29537 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
29538 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
29539 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
29540 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
29541 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
29554 …_X27_GCFSM_CMU_PMA_READ_OVR_O_K2_E5 (0x1<<7) // GCFSM pma_read_o…
29555 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_READ_OVR_O_K2_E5_SHIFT 7
29559 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
29561 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
29563 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
29565 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29568 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
29570 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29572 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29574 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
29577 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29579 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29581 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29583 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29586 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
29588 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29590 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29592 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29595 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29597 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29599 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29640 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29648 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
29659 …_X95_AHB_PMA_CM_C1_SEL_O_K2_E5 (0x1<<7) // CMU LF C1 cap se…
29660 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_C1_SEL_O_K2_E5_SHIFT 7
29668 …_X96_AHB_PMA_CM_BGSTART_BYP_O_K2_E5 (0x1<<7) // Bandgap startup …
29669 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_BGSTART_BYP_O_K2_E5_SHIFT 7
29682 …_E5 (0x1<<2) // Override enable for overriding N-div value
29701 …_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29711 …_X108_PMA_REFCLK_SEL_OVR_O_K2_E5 (0x1<<7) // Reference clock …
29712 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_SEL_OVR_O_K2_E5_SHIFT 7
29726 …_X109_PMA_REFCLK_QFWD_R_O_K2_E5 (0x1<<7) // Override for pri…
29727 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_R_O_K2_E5_SHIFT 7
29746 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
29753 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29755 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29757 …_X118_FRACN_FBK_CLK_DIV_SEL_O_K2_E5 (0x1<<7) // Clock divider fo…
29758 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_DIV_SEL_O_K2_E5_SHIFT 7
29766 …_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_K2_E5 (0x1<<7) // override enable …
29767 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_K2_E5_SHIFT 7
29768 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29770 …_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29802 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
29806 … 0x000208UL //Access:R DataWidth:0x8 // Snapshot of digital test bus data [7:0]
29810 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29812 …US_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29838 …_X137_AHB_PMA_CM_C1_SEL_GEN3_O_K2_E5 (0x1<<7) // CMU LF C1 cap se…
29839 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_C1_SEL_GEN3_O_K2_E5_SHIFT 7
29847 …_X138_AHB_PMA_CM_BGSTART_BYP_GEN3_O_K2_E5 (0x1<<7) // Bandgap startup …
29848 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_BGSTART_BYP_GEN3_O_K2_E5_SHIFT 7
29878 …A_CM_DIVPSEL_GEN3_O_K2_E5 (0x7f<<0) // CMU P-divider setting in ge…
29906 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
29949 …_X191_RESET_CMU_FL_IDDQ_SETVAL_O_K2_E5 (0x1<<7) // MSM Function IDD…
29950 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_RESET_CMU_FL_IDDQ_SETVAL_O_K2_E5_SHIFT 7
29966 …_X192_LFI_EXTZERO_IDDQ_SETVAL_O_K2_E5 (0x1<<7) // MSM Function IDD…
29967 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_LFI_EXTZERO_IDDQ_SETVAL_O_K2_E5_SHIFT 7
29983 …CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_K2_E5 (0x1<<7) // Not used
29984 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_K2_E5_SHIFT 7
30000 …_X194_RESET_CMU_FL_RST_SETVAL_O_K2_E5 (0x1<<7) // MSM Function RST…
30001 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_RESET_CMU_FL_RST_SETVAL_O_K2_E5_SHIFT 7
30017 …_X195_LFI_EXTZERO_RST_SETVAL_O_K2_E5 (0x1<<7) // MSM Function RST…
30018 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_LFI_EXTZERO_RST_SETVAL_O_K2_E5_SHIFT 7
30034 …CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_K2_E5 (0x1<<7) // Not used
30035 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_K2_E5_SHIFT 7
30051 …_X197_RESET_CMU_FL_NORM_SETVAL_O_K2_E5 (0x1<<7) // MSM Function NOR…
30052 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_RESET_CMU_FL_NORM_SETVAL_O_K2_E5_SHIFT 7
30068 …_X198_LFI_EXTZERO_NORM_SETVAL_O_K2_E5 (0x1<<7) // MSM Function NOR…
30069 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_LFI_EXTZERO_NORM_SETVAL_O_K2_E5_SHIFT 7
30085 …CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_K2_E5 (0x1<<7) // Not used
30086 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_K2_E5_SHIFT 7
30102 …_X200_RESET_CMU_FL_PD_SETVAL_O_K2_E5 (0x1<<7) // MSM Function POW…
30103 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_RESET_CMU_FL_PD_SETVAL_O_K2_E5_SHIFT 7
30119 …_X201_LFI_EXTZERO_PD_SETVAL_O_K2_E5 (0x1<<7) // MSM Function POW…
30120 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_LFI_EXTZERO_PD_SETVAL_O_K2_E5_SHIFT 7
30136 …CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_K2_E5 (0x1<<7) // Not used
30137 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_K2_E5_SHIFT 7
30153 …_X203_RESET_CMU_FL_NORM_REFCLK_SETVAL_O_K2_E5 (0x1<<7) // MSM Function NOR…
30154 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_RESET_CMU_FL_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT 7
30170 …_X204_LFI_EXTZERO_NORM_REFCLK_SETVAL_O_K2_E5 (0x1<<7) // MSM Function NOR…
30171 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_LFI_EXTZERO_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT 7
30187 …CMU_CSR_0_X205_PD_CLKDIV_REFCLK_RIGHT_NORM_REFCLK_SETVAL_O_K2_E5 (0x1<<7) // Not used
30188 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_REFCLK_RIGHT_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT 7
30204 …_X206_RESET_CMU_FL_P1_2_SETVAL_O_K2_E5 (0x1<<7) // MSM Function P1_…
30205 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_RESET_CMU_FL_P1_2_SETVAL_O_K2_E5_SHIFT 7
30221 …_X207_LFI_EXTZERO_P1_2_SETVAL_O_K2_E5 (0x1<<7) // MSM Function P1_…
30222 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_LFI_EXTZERO_P1_2_SETVAL_O_K2_E5_SHIFT 7
30238 …CMU_CSR_0_X208_PD_CLKDIV_REFCLK_RIGHT_P1_2_SETVAL_O_K2_E5 (0x1<<7) // Not used
30239 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_REFCLK_RIGHT_P1_2_SETVAL_O_K2_E5_SHIFT 7
30245 …O_K2_E5 (0x1<<7) // Clock divider for TX path branch 2 : 0-No divi…
30246 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT 7
30248 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
30250 …O_K2_E5 (0x1<<7) // Clock divider for RX path branch 2 : 0-No divi…
30251 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT 7
30253 …O_K2_E5 (0x1<<7) // Clock divider for RX path branch 4 : 0-No divi…
30254 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5_SHIFT 7
30256 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
30258 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
30261 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
30270 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
30272 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
30277 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
30279 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
30285 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
30287 … (0x1<<7) // Bist generator enable. 0 - Bist generator id…
30288 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_EN_O_K2_E5_SHIFT 7
30292 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
30294 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
30296 … 0x000824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30297 … 0x000828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30298 … 0x00082cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
30299 … 0x000830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
30300 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
30302 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
30309 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
30315 …1_X15_BIST_RX_CLOCK_ENABLE_K2_E5 (0x1<<7) // Active HIGH cloc…
30316 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_RX_CLOCK_ENABLE_K2_E5_SHIFT 7
30329 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
30330 … 0x000854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30331 … 0x000858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30332 … 0x00085cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30333 … 0x000860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30341 … 0x000880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
30342 … 0x000884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
30343 … 0x000888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
30344 … 0x00088cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
30345 … 0x000890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
30346 … 0x000894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
30347 … 0x000898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
30348 … 0x00089cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
30349 … 0x0008a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
30350 … 0x0008a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
30351 … 0x0008a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
30352 … 0x0008acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
30353 … 0x0008b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
30354 … 0x0008b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
30355 … 0x0008b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
30356 … 0x0008bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
30357 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
30358 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
30359 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
30360 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
30365 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
30367 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
30369 …LOAD_OVR_K2_E5 (0x1<<7) // ICA Method PMA Load signal Override -…
30370 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5_SHIFT 7
30377 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
30383 …1_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5 (0x1<<7) // GCFSM pma_read_o…
30384 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5_SHIFT 7
30394 … (0x3f<<2) // Bit 2: Override enable for msm_func Bits [7:3] : Override msm_fu…
30403 …1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5 (0x1<<7) // Number of cycles…
30404 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5_SHIFT 7
30421 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
30423 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
30425 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
30429 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30430 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30431 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30433 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30435 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
30485 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
30489 …1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5 (0x1<<7) // RX FL calibratio…
30490 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5_SHIFT 7
30492 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
30506 …1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5 (0x1<<7) // CDR DivN clock d…
30507 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5_SHIFT 7
30519 …1_X95_AHB_PMA_LN_RXDWN_O_K2_E5 (0x1<<7) // dfe_edge_by[0]. …
30520 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_RXDWN_O_K2_E5_SHIFT 7
30536 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
30538 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
30579 …1_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5 (0x1<<7) // CDR VCO frequenc…
30580 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5_SHIFT 7
30589 …1_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5 (0x1<<7) // CDR DivN clock d…
30590 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5_SHIFT 7
30602 …1_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5 (0x1<<7) // dfe_edge_by[0]. …
30603 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5_SHIFT 7
30627 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
30629 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
30633 …1_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5 (0x1<<7) // Debug feature, w…
30634 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5_SHIFT 7
30643 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
30646 … 0x0009f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
30658 …1_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5 (0x1<<7) // This bit has sim…
30659 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5_SHIFT 7
30714 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
30716 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
30732 …1_X145_CMP_OFFSET_AVG_EN_O_K2_E5 (0x1<<7) // CMP Offset Noise…
30733 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_EN_O_K2_E5_SHIFT 7
30742 …1_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5 (0x1<<7) // Inverts the pola…
30743 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5_SHIFT 7
30747 …1_X148_RXEQ_OVR_EN_O_K2_E5 (0x1<<7) // Override enable …
30748 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_EN_O_K2_E5_SHIFT 7
30752 …1_X149_RXEQ_OVR_LATCH_O_K2_E5 (0x1<<7) // Override for DFE…
30753 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LATCH_O_K2_E5_SHIFT 7
30763 …1_X150_DFE_TAP_OVR_EN_O_7_K2_E5 (0x1<<7) // DFE TAP override…
30764 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_OVR_EN_O_7_K2_E5_SHIFT 7
30772 …1_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5 (0x1<<7) // DFE comparator c…
30773 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5_SHIFT 7
30794 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
30800 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
30802 … 0x000a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
30804 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
30806 … 0x000a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
30824 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
30832 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
30834 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
30846 …1_X203_CDFE_LN_EI_EXIT_CAL_K2_E5 (0x1<<7) // EI exit cdfe cal…
30847 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_EI_EXIT_CAL_K2_E5_SHIFT 7
30859 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
30860 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
30861 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
30863 …1_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5 (0x1<<7) // cdfe coarse dll …
30864 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5_SHIFT 7
30865 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
30866 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
30867 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
30868 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
30869 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
30994 …1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5 (0x1<<7) // Register overrid…
30995 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5_SHIFT 7
31016 …1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5 (0x1<<7) // Enables FW enabl…
31017 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5_SHIFT 7
31025 …REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5 (0x1<<7) //
31026 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5_SHIFT 7
31139 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
31141 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31143 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31145 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31149 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
31152 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31154 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31156 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31158 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31160 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31162 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31167 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31169 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31177 …1_X303_TXTERM_CAL_SEQ_EN_O_K2_E5 (0x1<<7) // Txterm calibrati…
31178 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_TXTERM_CAL_SEQ_EN_O_K2_E5_SHIFT 7
31187 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
31191 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
31195 …1_X305_DEC_EN_O_K2_E5 (0x1<<7) // 8b/10b decoder e…
31196 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_DEC_EN_O_K2_E5_SHIFT 7
31209 …1_X307_USB_MODE_K2_E5 (0x1<<7) // Signal Detect US…
31210 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_USB_MODE_K2_E5_SHIFT 7
31218 …1_X308_BLOCK_DEC_CLR_ERR_O_K2_E5 (0x1<<7) // 130b/128b: clear…
31219 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_CLR_ERR_O_K2_E5_SHIFT 7
31241 …1_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5 (0x1<<7) // Disables the EIE…
31242 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5_SHIFT 7
31244 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
31289 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
31291 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
31297 …1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5 (0x1<<7) // override value f…
31298 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5_SHIFT 7
31314 …1_X326_LN_IN_OVR_O_49_K2_E5 (0x1<<7) // OOB detect enable
31315 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_49_K2_E5_SHIFT 7
31317 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
31325 …O_K2_E5 (0x1<<7) // Clock divider for TX path branch 2 : 0-No divi…
31326 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT 7
31328 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
31330 …O_K2_E5 (0x1<<7) // Clock divider for RX path branch 2 : 0-No divi…
31331 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT 7
31333 …O_K2_E5 (0x1<<7) // Clock divider for RX path branch 4 : 0-No divi…
31334 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5_SHIFT 7
31336 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
31338 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
31341 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
31350 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
31352 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
31357 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
31359 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
31365 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
31367 … (0x1<<7) // Bist generator enable. 0 - Bist generator id…
31368 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_EN_O_K2_E5_SHIFT 7
31372 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
31374 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
31376 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31377 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31378 … 0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
31379 … 0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
31380 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
31382 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
31389 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
31395 …2_X15_BIST_RX_CLOCK_ENABLE_K2_E5 (0x1<<7) // Active HIGH cloc…
31396 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_RX_CLOCK_ENABLE_K2_E5_SHIFT 7
31409 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
31410 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31411 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31412 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31413 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31421 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
31422 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
31423 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
31424 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
31425 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
31426 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
31427 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
31428 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
31429 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
31430 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
31431 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
31432 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
31433 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
31434 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
31435 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
31436 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
31437 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
31438 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
31439 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
31440 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
31445 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
31447 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
31449 …LOAD_OVR_K2_E5 (0x1<<7) // ICA Method PMA Load signal Override -…
31450 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5_SHIFT 7
31457 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
31463 …2_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5 (0x1<<7) // GCFSM pma_read_o…
31464 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5_SHIFT 7
31474 … (0x3f<<2) // Bit 2: Override enable for msm_func Bits [7:3] : Override msm_fu…
31483 …2_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5 (0x1<<7) // Number of cycles…
31484 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5_SHIFT 7
31501 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
31503 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
31505 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
31509 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31510 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31511 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31513 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31515 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
31565 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
31569 …2_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5 (0x1<<7) // RX FL calibratio…
31570 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5_SHIFT 7
31572 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
31586 …2_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5 (0x1<<7) // CDR DivN clock d…
31587 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5_SHIFT 7
31599 …2_X95_AHB_PMA_LN_RXDWN_O_K2_E5 (0x1<<7) // dfe_edge_by[0]. …
31600 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_RXDWN_O_K2_E5_SHIFT 7
31616 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
31618 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
31659 …2_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5 (0x1<<7) // CDR VCO frequenc…
31660 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5_SHIFT 7
31669 …2_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5 (0x1<<7) // CDR DivN clock d…
31670 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5_SHIFT 7
31682 …2_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5 (0x1<<7) // dfe_edge_by[0]. …
31683 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5_SHIFT 7
31707 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
31709 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
31713 …2_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5 (0x1<<7) // Debug feature, w…
31714 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5_SHIFT 7
31723 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
31726 … 0x0011f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
31738 …2_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5 (0x1<<7) // This bit has sim…
31739 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5_SHIFT 7
31794 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
31796 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
31812 …2_X145_CMP_OFFSET_AVG_EN_O_K2_E5 (0x1<<7) // CMP Offset Noise…
31813 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X145_CMP_OFFSET_AVG_EN_O_K2_E5_SHIFT 7
31822 …2_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5 (0x1<<7) // Inverts the pola…
31823 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5_SHIFT 7
31827 …2_X148_RXEQ_OVR_EN_O_K2_E5 (0x1<<7) // Override enable …
31828 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X148_RXEQ_OVR_EN_O_K2_E5_SHIFT 7
31832 …2_X149_RXEQ_OVR_LATCH_O_K2_E5 (0x1<<7) // Override for DFE…
31833 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X149_RXEQ_OVR_LATCH_O_K2_E5_SHIFT 7
31843 …2_X150_DFE_TAP_OVR_EN_O_7_K2_E5 (0x1<<7) // DFE TAP override…
31844 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_DFE_TAP_OVR_EN_O_7_K2_E5_SHIFT 7
31852 …2_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5 (0x1<<7) // DFE comparator c…
31853 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5_SHIFT 7
31874 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
31880 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
31882 … 0x001280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
31884 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
31886 … 0x001288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
31904 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
31912 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
31914 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
31926 …2_X203_CDFE_LN_EI_EXIT_CAL_K2_E5 (0x1<<7) // EI exit cdfe cal…
31927 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_EI_EXIT_CAL_K2_E5_SHIFT 7
31939 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
31940 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
31941 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
31943 …2_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5 (0x1<<7) // cdfe coarse dll …
31944 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5_SHIFT 7
31945 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
31946 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
31947 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
31948 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
31949 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
32074 …2_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5 (0x1<<7) // Register overrid…
32075 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5_SHIFT 7
32096 …2_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5 (0x1<<7) // Enables FW enabl…
32097 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5_SHIFT 7
32105 …REG_AHB_LANE_CSR_2_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5 (0x1<<7) //
32106 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5_SHIFT 7
32219 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
32221 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32223 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32225 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32229 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
32232 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32234 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32236 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32238 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32240 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32242 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32247 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32249 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32257 …2_X303_TXTERM_CAL_SEQ_EN_O_K2_E5 (0x1<<7) // Txterm calibrati…
32258 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_TXTERM_CAL_SEQ_EN_O_K2_E5_SHIFT 7
32267 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
32271 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
32275 …2_X305_DEC_EN_O_K2_E5 (0x1<<7) // 8b/10b decoder e…
32276 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_DEC_EN_O_K2_E5_SHIFT 7
32289 …2_X307_USB_MODE_K2_E5 (0x1<<7) // Signal Detect US…
32290 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_USB_MODE_K2_E5_SHIFT 7
32298 …2_X308_BLOCK_DEC_CLR_ERR_O_K2_E5 (0x1<<7) // 130b/128b: clear…
32299 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_CLR_ERR_O_K2_E5_SHIFT 7
32321 …2_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5 (0x1<<7) // Disables the EIE…
32322 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5_SHIFT 7
32324 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
32369 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
32371 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
32377 …2_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5 (0x1<<7) // override value f…
32378 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5_SHIFT 7
32394 …2_X326_LN_IN_OVR_O_49_K2_E5 (0x1<<7) // OOB detect enable
32395 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_LN_IN_OVR_O_49_K2_E5_SHIFT 7
32397 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
32405 …O_K2_E5 (0x1<<7) // Clock divider for TX path branch 2 : 0-No divi…
32406 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT 7
32408 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
32410 …O_K2_E5 (0x1<<7) // Clock divider for RX path branch 2 : 0-No divi…
32411 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT 7
32413 …O_K2_E5 (0x1<<7) // Clock divider for RX path branch 4 : 0-No divi…
32414 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5_SHIFT 7
32416 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
32418 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
32421 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
32430 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
32432 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
32437 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
32439 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
32445 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
32447 … (0x1<<7) // Bist generator enable. 0 - Bist generator id…
32448 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_EN_O_K2_E5_SHIFT 7
32452 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
32454 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
32456 … 0x001824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32457 … 0x001828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32458 … 0x00182cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
32459 … 0x001830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
32460 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
32462 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
32469 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
32475 …3_X15_BIST_RX_CLOCK_ENABLE_K2_E5 (0x1<<7) // Active HIGH cloc…
32476 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_RX_CLOCK_ENABLE_K2_E5_SHIFT 7
32489 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
32490 … 0x001854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32491 … 0x001858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32492 … 0x00185cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32493 … 0x001860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32501 … 0x001880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
32502 … 0x001884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
32503 … 0x001888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
32504 … 0x00188cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
32505 … 0x001890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
32506 … 0x001894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
32507 … 0x001898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
32508 … 0x00189cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
32509 … 0x0018a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
32510 … 0x0018a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
32511 … 0x0018a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
32512 … 0x0018acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
32513 … 0x0018b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
32514 … 0x0018b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
32515 … 0x0018b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
32516 … 0x0018bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
32517 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
32518 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
32519 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
32520 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
32525 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
32527 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
32529 …LOAD_OVR_K2_E5 (0x1<<7) // ICA Method PMA Load signal Override -…
32530 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5_SHIFT 7
32537 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
32543 …3_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5 (0x1<<7) // GCFSM pma_read_o…
32544 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5_SHIFT 7
32554 … (0x3f<<2) // Bit 2: Override enable for msm_func Bits [7:3] : Override msm_fu…
32563 …3_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5 (0x1<<7) // Number of cycles…
32564 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5_SHIFT 7
32581 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
32583 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
32585 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
32589 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32590 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32591 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32593 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32595 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
32645 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
32649 …3_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5 (0x1<<7) // RX FL calibratio…
32650 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5_SHIFT 7
32652 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
32666 …3_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5 (0x1<<7) // CDR DivN clock d…
32667 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5_SHIFT 7
32679 …3_X95_AHB_PMA_LN_RXDWN_O_K2_E5 (0x1<<7) // dfe_edge_by[0]. …
32680 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_RXDWN_O_K2_E5_SHIFT 7
32696 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
32698 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
32739 …3_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5 (0x1<<7) // CDR VCO frequenc…
32740 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5_SHIFT 7
32749 …3_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5 (0x1<<7) // CDR DivN clock d…
32750 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5_SHIFT 7
32762 …3_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5 (0x1<<7) // dfe_edge_by[0]. …
32763 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5_SHIFT 7
32787 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
32789 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
32793 …3_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5 (0x1<<7) // Debug feature, w…
32794 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5_SHIFT 7
32803 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
32806 … 0x0019f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
32818 …3_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5 (0x1<<7) // This bit has sim…
32819 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5_SHIFT 7
32874 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
32876 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
32892 …3_X145_CMP_OFFSET_AVG_EN_O_K2_E5 (0x1<<7) // CMP Offset Noise…
32893 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X145_CMP_OFFSET_AVG_EN_O_K2_E5_SHIFT 7
32902 …3_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5 (0x1<<7) // Inverts the pola…
32903 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5_SHIFT 7
32907 …3_X148_RXEQ_OVR_EN_O_K2_E5 (0x1<<7) // Override enable …
32908 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X148_RXEQ_OVR_EN_O_K2_E5_SHIFT 7
32912 …3_X149_RXEQ_OVR_LATCH_O_K2_E5 (0x1<<7) // Override for DFE…
32913 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X149_RXEQ_OVR_LATCH_O_K2_E5_SHIFT 7
32923 …3_X150_DFE_TAP_OVR_EN_O_7_K2_E5 (0x1<<7) // DFE TAP override…
32924 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_DFE_TAP_OVR_EN_O_7_K2_E5_SHIFT 7
32932 …3_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5 (0x1<<7) // DFE comparator c…
32933 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5_SHIFT 7
32954 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
32960 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
32962 … 0x001a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
32964 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
32966 … 0x001a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
32984 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
32992 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
32994 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
33006 …3_X203_CDFE_LN_EI_EXIT_CAL_K2_E5 (0x1<<7) // EI exit cdfe cal…
33007 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_EI_EXIT_CAL_K2_E5_SHIFT 7
33019 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
33020 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
33021 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
33023 …3_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5 (0x1<<7) // cdfe coarse dll …
33024 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5_SHIFT 7
33025 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
33026 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
33027 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
33028 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
33029 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
33154 …3_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5 (0x1<<7) // Register overrid…
33155 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5_SHIFT 7
33176 …3_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5 (0x1<<7) // Enables FW enabl…
33177 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5_SHIFT 7
33185 …REG_AHB_LANE_CSR_3_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5 (0x1<<7) //
33186 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5_SHIFT 7
33299 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
33301 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33303 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33305 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33309 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
33312 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33314 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33316 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33318 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33320 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33322 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33327 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33329 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33337 …3_X303_TXTERM_CAL_SEQ_EN_O_K2_E5 (0x1<<7) // Txterm calibrati…
33338 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_TXTERM_CAL_SEQ_EN_O_K2_E5_SHIFT 7
33347 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
33351 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
33355 …3_X305_DEC_EN_O_K2_E5 (0x1<<7) // 8b/10b decoder e…
33356 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_DEC_EN_O_K2_E5_SHIFT 7
33369 …3_X307_USB_MODE_K2_E5 (0x1<<7) // Signal Detect US…
33370 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_USB_MODE_K2_E5_SHIFT 7
33378 …3_X308_BLOCK_DEC_CLR_ERR_O_K2_E5 (0x1<<7) // 130b/128b: clear…
33379 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_CLR_ERR_O_K2_E5_SHIFT 7
33401 …3_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5 (0x1<<7) // Disables the EIE…
33402 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5_SHIFT 7
33404 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
33449 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
33451 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
33457 …3_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5 (0x1<<7) // override value f…
33458 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5_SHIFT 7
33474 …3_X326_LN_IN_OVR_O_49_K2_E5 (0x1<<7) // OOB detect enable
33475 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_LN_IN_OVR_O_49_K2_E5_SHIFT 7
33477 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
33485 …O_K2_E5 (0x1<<7) // Clock divider for TX path branch 2 : 0-No divi…
33486 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT 7
33488 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
33490 …O_K2_E5 (0x1<<7) // Clock divider for RX path branch 2 : 0-No divi…
33491 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_K2_E5_SHIFT 7
33493 …O_K2_E5 (0x1<<7) // Clock divider for RX path branch 4 : 0-No divi…
33494 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_K2_E5_SHIFT 7
33496 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
33498 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
33501 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
33510 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
33512 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
33517 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
33519 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
33525 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
33527 … (0x1<<7) // Bist generator enable. 0 - Bist generator id…
33528 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_EN_O_K2_E5_SHIFT 7
33532 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
33534 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
33536 … 0x002024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33537 … 0x002028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33538 … 0x00202cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
33539 … 0x002030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
33540 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
33542 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
33549 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
33555 …4_X15_BIST_RX_CLOCK_ENABLE_K2_E5 (0x1<<7) // Active HIGH cloc…
33556 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_RX_CLOCK_ENABLE_K2_E5_SHIFT 7
33569 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
33570 … 0x002054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33571 … 0x002058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33572 … 0x00205cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33573 … 0x002060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33581 … 0x002080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
33582 … 0x002084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
33583 … 0x002088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
33584 … 0x00208cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
33585 … 0x002090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
33586 … 0x002094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
33587 … 0x002098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
33588 … 0x00209cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
33589 … 0x0020a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
33590 … 0x0020a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
33591 … 0x0020a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
33592 … 0x0020acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
33593 … 0x0020b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
33594 … 0x0020b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
33595 … 0x0020b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
33596 … 0x0020bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
33597 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
33598 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
33599 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
33600 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
33605 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
33607 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
33609 …LOAD_OVR_K2_E5 (0x1<<7) // ICA Method PMA Load signal Override -…
33610 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_LANE_PMA_LOAD_OVR_K2_E5_SHIFT 7
33617 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
33623 …4_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5 (0x1<<7) // GCFSM pma_read_o…
33624 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_READ_OVR_O_K2_E5_SHIFT 7
33634 … (0x3f<<2) // Bit 2: Override enable for msm_func Bits [7:3] : Override msm_fu…
33643 …4_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5 (0x1<<7) // Number of cycles…
33644 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_K2_E5_SHIFT 7
33661 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
33663 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
33665 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
33669 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33670 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33671 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33673 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33675 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
33725 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
33729 …4_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5 (0x1<<7) // RX FL calibratio…
33730 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_K2_E5_SHIFT 7
33732 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
33746 …4_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5 (0x1<<7) // CDR DivN clock d…
33747 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_K2_E5_SHIFT 7
33759 …4_X95_AHB_PMA_LN_RXDWN_O_K2_E5 (0x1<<7) // dfe_edge_by[0]. …
33760 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_RXDWN_O_K2_E5_SHIFT 7
33776 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
33778 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
33819 …4_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5 (0x1<<7) // CDR VCO frequenc…
33820 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_K2_E5_SHIFT 7
33829 …4_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5 (0x1<<7) // CDR DivN clock d…
33830 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_K2_E5_SHIFT 7
33842 …4_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5 (0x1<<7) // dfe_edge_by[0]. …
33843 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_RXDWN_GEN3_O_K2_E5_SHIFT 7
33867 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
33869 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
33873 …4_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5 (0x1<<7) // Debug feature, w…
33874 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_TERM_EN_CAL_OVR_K2_E5_SHIFT 7
33883 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
33886 … 0x0021f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
33898 …4_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5 (0x1<<7) // This bit has sim…
33899 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_FORCE_CAL_O_6_K2_E5_SHIFT 7
33954 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
33956 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
33972 …4_X145_CMP_OFFSET_AVG_EN_O_K2_E5 (0x1<<7) // CMP Offset Noise…
33973 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X145_CMP_OFFSET_AVG_EN_O_K2_E5_SHIFT 7
33982 …4_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5 (0x1<<7) // Inverts the pola…
33983 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_SUPERBST_EN_INVERT_O_K2_E5_SHIFT 7
33987 …4_X148_RXEQ_OVR_EN_O_K2_E5 (0x1<<7) // Override enable …
33988 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X148_RXEQ_OVR_EN_O_K2_E5_SHIFT 7
33992 …4_X149_RXEQ_OVR_LATCH_O_K2_E5 (0x1<<7) // Override for DFE…
33993 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X149_RXEQ_OVR_LATCH_O_K2_E5_SHIFT 7
34003 …4_X150_DFE_TAP_OVR_EN_O_7_K2_E5 (0x1<<7) // DFE TAP override…
34004 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_DFE_TAP_OVR_EN_O_7_K2_E5_SHIFT 7
34012 …4_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5 (0x1<<7) // DFE comparator c…
34013 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_CMP_CAL_EN_OVR_O_2_K2_E5_SHIFT 7
34034 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
34040 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
34042 … 0x002280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
34044 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
34046 … 0x002288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
34064 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
34072 … to 0 8-bit or 10-bit mode. 2'b11: the word_…
34074 …o 0 10-bit or 20-bit mode. 2'b11: the mode_8b…
34086 …4_X203_CDFE_LN_EI_EXIT_CAL_K2_E5 (0x1<<7) // EI exit cdfe cal…
34087 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_EI_EXIT_CAL_K2_E5_SHIFT 7
34099 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
34100 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
34101 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
34103 …4_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5 (0x1<<7) // cdfe coarse dll …
34104 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X208_AHB_CDFE_COARSE_DLL_OV_EN_K2_E5_SHIFT 7
34105 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
34106 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
34107 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
34108 …es/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables …
34109 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
34234 …4_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5 (0x1<<7) // Register overrid…
34235 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_K2_E5_SHIFT 7
34256 …4_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5 (0x1<<7) // Enables FW enabl…
34257 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_K2_E5_SHIFT 7
34265 …REG_AHB_LANE_CSR_4_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5 (0x1<<7) //
34266 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_K2_E5_SHIFT 7
34379 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
34381 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34383 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34385 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34389 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
34392 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34394 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34396 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34398 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34400 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34402 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34407 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34409 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34417 …4_X303_TXTERM_CAL_SEQ_EN_O_K2_E5 (0x1<<7) // Txterm calibrati…
34418 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_TXTERM_CAL_SEQ_EN_O_K2_E5_SHIFT 7
34427 … included to handle the communication between the external 64-bit data and the internal 20-bit dat…
34431 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
34435 …4_X305_DEC_EN_O_K2_E5 (0x1<<7) // 8b/10b decoder e…
34436 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_DEC_EN_O_K2_E5_SHIFT 7
34449 …4_X307_USB_MODE_K2_E5 (0x1<<7) // Signal Detect US…
34450 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_USB_MODE_K2_E5_SHIFT 7
34458 …4_X308_BLOCK_DEC_CLR_ERR_O_K2_E5 (0x1<<7) // 130b/128b: clear…
34459 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_CLR_ERR_O_K2_E5_SHIFT 7
34481 …4_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5 (0x1<<7) // Disables the EIE…
34482 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_DIS_EIEOS_CHK_IN_LB_O_K2_E5_SHIFT 7
34484 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
34529 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
34531 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
34537 …4_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5 (0x1<<7) // override value f…
34538 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_K2_E5_SHIFT 7
34554 …4_X326_LN_IN_OVR_O_49_K2_E5 (0x1<<7) // OOB detect enable
34555 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_LN_IN_OVR_O_49_K2_E5_SHIFT 7
34557 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
34565 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
34568 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
34570 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
34602 … 0x00285cUL //Access:RW DataWidth:0x8 // Elastic buffer s0 [7:0]
34606 … 0x002864UL //Access:RW DataWidth:0x8 // Elastic buffer s1 [7:0]
34621 … 0x002880UL //Access:RW DataWidth:0x8 // SKP symbol for PCIe Gen3 SKP OS ---8'hAA
34631 … 0x002898UL //Access:RW DataWidth:0x8 // 10-bit align symbol for ebuf during PIPE loopback…
34633 …_S0_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for …
34635 … 0x0028a0UL //Access:RW DataWidth:0x8 // 10-bit align symbol for ebuf during PIPE loopback…
34637 …_S1_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for …
34702 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
34703 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
34704 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
34705 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
34706 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
34707 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
34708 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
34709 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
34710 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
34711 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
34712 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
34713 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
34714 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
34715 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
34716 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
34717 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
34720 …nction. Varies depending on function number. Bits 15-7: Address of first command to run Bits: 6-…
34789 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
34790 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
34806 …SR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O_K2_E5 (0x1<<7) // MSM Function IDD…
34807 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O_K2_E5_SHIFT 7
34823 …SR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O_K2_E5 (0x1<<7) // MSM Function IDD…
34824 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O_K2_E5_SHIFT 7
34840 …SR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MSM Function IDD…
34841 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
34866 …SR_5_X147_MSM_SAPI_RST_PD_S2P_O_K2_E5 (0x1<<7) // MSM Function RES…
34867 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_S2P_O_K2_E5_SHIFT 7
34883 …SR_5_X148_MSM_SAPI_RST_RESET_DFE_O_K2_E5 (0x1<<7) // MSM Function RES…
34884 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_DFE_O_K2_E5_SHIFT 7
34900 …SR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MSM Function RES…
34901 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
34926 …SR_5_X151_MSM_SAPI_NORM_PD_S2P_O_K2_E5 (0x1<<7) // MSM Function NOR…
34927 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_S2P_O_K2_E5_SHIFT 7
34943 …SR_5_X152_MSM_SAPI_NORM_RESET_DFE_O_K2_E5 (0x1<<7) // MSM Function NOR…
34944 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_DFE_O_K2_E5_SHIFT 7
34960 …SR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MSM Function NOR…
34961 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
34986 …SR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O_K2_E5 (0x1<<7) // MSM Function PAR…
34987 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O_K2_E5_SHIFT 7
35003 …SR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O_K2_E5 (0x1<<7) // MSM Function PAR…
35004 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O_K2_E5_SHIFT 7
35020 …SR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MSM Function PAR…
35021 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
35046 …SR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O_K2_E5 (0x1<<7) // MSM Function SLU…
35047 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O_K2_E5_SHIFT 7
35063 …SR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O_K2_E5 (0x1<<7) // MSM Function SLU…
35064 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O_K2_E5_SHIFT 7
35080 …SR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MSM Function SLU…
35081 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
35260 …LOW_EN_O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a prog…
35262 …Q_C1_FORCE_LOW_EN_O_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor do…
35263 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_C1_FORCE_LOW_EN_O_K2_E5_SHIFT 7
35280 … (0x1<<6) // Set all DFE calibration values to mid-scale instead of usin…
35282 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
35284 …NT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
35286 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
35287 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
35288 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
35289 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
35290 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
35291 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
35292 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
35296 …CAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration for { Tap…
35305 …TE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
35336 …SR_5_X234_QAHB_DFE_RAW_VALUE_O_K2_E5 (0x1<<7) // Testbus select f…
35337 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X234_QAHB_DFE_RAW_VALUE_O_K2_E5_SHIFT 7
35370 …SR_5_X248_RXEQ_STEP_O_K2_E5 (0x1<<7) // Step calibration…
35371 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_O_K2_E5_SHIFT 7
35375 …SR_5_X249_RXEQ_FLOOR_O_K2_E5 (0x1<<7) // Take the floor o…
35376 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_FLOOR_O_K2_E5_SHIFT 7
35415 …SR_5_X261_DFE_SHADOW_OFST_RD_SEL_K2_E5 (0x1<<7) // DFE shadow offse…
35416 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_OFST_RD_SEL_K2_E5_SHIFT 7
35442 … 0x002c40UL //Access:RW DataWidth:0x8 // Training pattern for TxEQ adapt DFE tap1 cm1 [7:0]
35448 … 0x002c48UL //Access:RW DataWidth:0x8 // Training pattern for TxEQ adapt DFE tap1 c1 [7:0]
35464 …E_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
35466 …DAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
35475 …2_E5 (0x1f<<0) // Bit 4 - latency check control enable Bit 3:0 - l…
35691 …REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O_K2_E5 (0x1<<7) //
35692 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O_K2_E5_SHIFT 7
35722 …SR_5_X376_MSM_PIPE_RST_PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
35723 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_S2P_O_K2_E5_SHIFT 7
35739 …SR_5_X377_MSM_PIPE_RST_RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
35740 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_DFE_O_K2_E5_SHIFT 7
35756 …SR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
35757 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
35782 …SR_5_X380_MSM_PIPE_P0_PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
35783 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_S2P_O_K2_E5_SHIFT 7
35799 …SR_5_X381_MSM_PIPE_P0_RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
35800 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_DFE_O_K2_E5_SHIFT 7
35816 …SR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
35817 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
35842 …SR_5_X384_MSM_PIPE_P1_PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
35843 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_S2P_O_K2_E5_SHIFT 7
35859 …SR_5_X385_MSM_PIPE_P1_RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
35860 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_DFE_O_K2_E5_SHIFT 7
35876 …SR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
35877 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
35902 …SR_5_X388_MSM_PIPE_P2_PD_S2P_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
35903 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_S2P_O_K2_E5_SHIFT 7
35919 …SR_5_X389_MSM_PIPE_P2_RESET_DFE_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
35920 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_DFE_O_K2_E5_SHIFT 7
35936 …SR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
35937 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O_K2_E5_SHIFT 7
35973 …_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
35994 …CSR_5_X407_LN3_OK_I_7_K2_E5 (0x1<<7) // Lane 3 OK Status
35995 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_OK_I_7_K2_E5_SHIFT 7
36023 …SR_5_X410_LANE_RATE_IS_GEN3_OVR_O_K2_E5 (0x1<<7) // Newly added for …
36024 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_IS_GEN3_OVR_O_K2_E5_SHIFT 7
36036 …X414_TXPRESET_COEFF_P0CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P0 C-1
36045 …X417_TXPRESET_COEFF_P1CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P1 C-1
36054 …X420_TXPRESET_COEFF_P2CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P2 C-1
36063 …X423_TXPRESET_COEFF_P3CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P3 C-1
36072 …X426_TXPRESET_COEFF_P4CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P4 C-1
36081 …X429_TXPRESET_COEFF_P5CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P5 C-1
36090 …X432_TXPRESET_COEFF_P6CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P6 C-1
36099 …X435_TXPRESET_COEFF_P7CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P7 C-1
36108 …X438_TXPRESET_COEFF_P8CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P8 C-1
36117 …X441_TXPRESET_COEFF_P9CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P9 C-1
36126 …444_TXPRESET_COEFF_P10CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P10 C-1
36183 …SR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
36184 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O_K2_E5_SHIFT 7
36200 …SR_5_X484_MSM_PIPE_P1_0_PD_RA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
36201 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_RA_O_K2_E5_SHIFT 7
36217 …SR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
36218 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O_K2_E5_SHIFT 7
36243 …SR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
36244 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O_K2_E5_SHIFT 7
36260 …SR_5_X488_MSM_PIPE_P1_1_PD_RA_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
36261 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_RA_O_K2_E5_SHIFT 7
36277 …SR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
36278 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O_K2_E5_SHIFT 7
36303 …SR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
36304 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O_K2_E5_SHIFT 7
36320 …SR_5_X492_MSM_PIPE_P1_2_PD_P2S_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
36321 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_P2S_O_K2_E5_SHIFT 7
36337 …SR_5_X493_MSM_PIPE_P1_2_CDR_EN_O_K2_E5 (0x1<<7) // MFSM's PMA pd/re…
36338 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_CDR_EN_O_K2_E5_SHIFT 7
36355 …- no auto deassertion; 1 - auto deassertion); [1] rst_pswrd_auto_mode (0- no auto deassertion; 1 -…
36356 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36358 …-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific bloc…
36360 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36362 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36364 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36366 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36387 … 0x00841cUL //Access:RW DataWidth:0x1 // Set/clr general attention 7; this will set/clr b…
36417 … 0x008494UL //Access:RW DataWidth:0x8 // [7:0] = mask 8 attentio…
36419 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36420 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36421 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36422 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36423 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36424 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36425 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36426 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36427 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36428 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36429 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36430 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36431 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36432 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36433 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36434 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36435 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36436 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36437 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36438 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36439 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36440 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36441 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36442 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36443 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36444 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36445 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36446 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36447 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36448 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36449 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36450 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36451 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36452 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36453 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36454 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36455 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36456 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36457 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36458 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36459 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36460 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36461 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36462 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36463 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36464 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36465 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36466 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36467 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36468 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36469 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36470 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36471 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36472 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36473 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36474 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36475 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36476 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36477 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36478 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36479 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36480 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36481 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36482 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36483 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36484 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36485 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36486 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36487 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36488 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36489 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36490 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36491 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36492 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36493 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36494 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36495 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36496 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36497 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36498 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36499 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36500 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36501 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36502 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36503 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36504 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36505 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36506 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36507 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36508 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36509 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36510 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36511 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36512 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36513 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36514 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36515 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36516 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36517 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36518 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36519 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36520 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36521 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36522 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36523 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36524 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36525 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36526 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36527 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36528 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36529 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36530 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36531 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36532 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36533 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36534 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36535 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36536 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36537 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36538 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36539 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36540 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36541 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36542 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36543 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36544 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36545 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36546 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36547 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36548 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36549 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36550 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36551 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36552 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36553 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36554 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36555 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36556 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36557 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36558 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36559 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36560 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36561 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36562 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36563 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36564 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36565 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36566 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36567 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36568 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36569 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36570 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36571 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36572 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36573 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36574 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36575 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36576 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36577 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36578 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36579 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36580 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36581 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36582 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36583 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36584 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36585 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36586 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36587 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36588 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36589 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36590 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36591 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36592 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36593 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36594 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36595 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36596 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36597 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36598 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36599 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36600 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36601 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36602 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36603 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36604 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36605 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36606 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36607 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36608 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36609 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36610 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36611 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36612 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36613 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36614 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36615 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36616 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36617 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36618 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36619 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36620 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36621 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36622 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36623 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36624 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36625 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36626 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36627 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36628 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36629 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36630 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36631 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36632 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36633 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36634 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36636 …0x008800UL //Access:RW DataWidth:0x1 // The System Kill enable: 0 - none; 1 - hard reset. Res…
36637 …] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9…
36638 …7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4;…
36639 …3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] …
36640 …7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop s…
36641 …B Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; […
36642 …7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XS…
36643 …rrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; […
36644 …7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PS…
36645 …terrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; …
36655 …_misc_exp_rom_attn; [6] one clears PERST_N assertion (goes 0); [7] one clears PERST_N de-assertion…
36657 …ister results with the clear of the latched signals; [0] - clears pglue_misc_vpd_attn[0], [1] - cl…
36659 … 0x00883cUL //Access:RW DataWidth:0x9 // Attention sticky number - latches first attent…
36660 … 0x008c00UL //Access:RW DataWidth:0x2 // Port mode. 0 - single port; 1 - 2 ports; 2 - 4 por…
36661 … Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 1x …
36662 …s is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 10 - Tri Port…
36663 …- disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port. Port…
36664 …IFOs should be bypassed in latency-critical paths. bit0 - clock mux control (Obsolete), bit1 - BRB…
36665 …igBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset. [0]- BRB; [1] - BTB, PBF;
36667 …- Storms stall is disallowed; AEU unifier bit[7] output to MCP is disabled; 1 - All Storms are for…
36668 …c20UL //Access:RW DataWidth:0x17 // 23 bit GRC address where the scratch-pad of the MCP that i…
36669 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36670 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36671 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36672 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36673 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36674 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36675 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36676 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36685 …t). [0] timer1; [1] timer2; [2] timer3; [3] timer4; [4] timer5; [5] timer6; [6] timer7; [7] timer8.
36686 …ero. [0] timer1; [1]timer2; [2] timer3; [3] timer4; [4] timer5; [5] timer6; [6] timer7; [7] timer8.
36701 …he counter for sw timers1-8. there are 8 addresses in this register. address 0 - timer 1; address …
36703 …- no auto deassertion; 1 - auto deassertion); [1] rst_umac_on_core_rst (0- no auto deassertion; 1 …
36704 …- is not reset on hard reset; 1 - is reset on hard reset); [1] rst_n_hard_misc_rbc_pcie (0 - is no…
36705 …-ignore; The order of the bits is: [0] rst_cgrc; [1] rst_mcp_n_reset_reg_hard_core; [2] rst_mcp_n_…
36707 …. addr 3-ignore; The order of the bits is: [0] rst_cnig; [1] rst_pglc; [2] rst_pxpv; [3] rst_crbch…
36711 …- source of privilege level, 0 - the source is external pin, 1 - the source are bits[2:1] of this …
36712 … // Privilege level as defined by external pin. 0 - non-secured mode; 1 - secured mode; 2 - full…
36713 …-disable to the NVM block is generated. '0' - PROTECT: This value protects the NVM from any writes…
36714 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36716 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36718 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36720 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36722 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36724 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36726 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36728 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36730 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36732 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36734 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36736 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36738 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36740 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36742 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36744 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36746 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36748 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36750 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36752 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36754 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36756 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36758 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36760 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
36762 …-ignore; The order of the bits is: [0] rst_nwm; [1] rst_nwm_mac0; [2] rst_nwm_mac1; [3] rst_nwm_ma…
36812 …IF0_FIFO_ERR_ENG0_BB (0x1<<7) // BTB_IF0 FIFO err…
36813 …ISCS_REG_INT_STS_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_BB_SHIFT 7
36835 …_IF0_FIFO_ERR_ENG0_BB (0x1<<7) // This bit masks, …
36836 …ISCS_REG_INT_MASK_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_BB_SHIFT 7
36858 …TB_IF0_FIFO_ERR_ENG0_BB (0x1<<7) // BTB_IF0 FIFO err…
36859 …ISCS_REG_INT_STS_WR_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_BB_SHIFT 7
36881 …BTB_IF0_FIFO_ERR_ENG0_BB (0x1<<7) // BTB_IF0 FIFO err…
36882 …ISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_BB_SHIFT 7
36892 …state of the ptw_miscs_pcie_link_up signal which is driven by the PCIE core - a pulse at the begin…
36893 …ate of the ptw_miscs_pcie_hot_reset signal which is driven by the PCIE core - a pulse at the begin…
36895 … DataWidth:0x10 // Accounts for HOT RESET assertion when the chip is in un-prepared state. Is re…
36897 …Width:0x1 // Set to 1 when main PLL lock indication is de-asserted when hard reset is de-assert…
36898 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36899 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36900 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36901 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36902 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36903 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36904 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36905 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36906 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36907 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36908 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36909 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36910 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36911 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36912 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36913 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36914 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36915 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36916 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36917 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36918 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36919 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36920 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36921 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36922 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36923 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36924 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36925 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36926 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36927 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36928 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36929 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
37029 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37031 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37033 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37035 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37037 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37039 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37041 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37043 …t will be asserted. All the requests for given resource participate in round-robin arbitration. Wr…
37046 … 0x009654UL //Access:RW DataWidth:0x3 // Bit[0]: PERST# IO de-assertion. If == 1, t…
37047 … PERST# de-assert. Bit[1]: WAKE control � direct MFW control of the WAKE# IO. Set to 1 to asserts …
37050 …0x0096b8UL //Access:R DataWidth:0x1 // Chip core_rst_n status. 0 - asserted; 1 - de-asserted.
37059 …- Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON. When set to 0 - vTMON is in reset. …
37061 …- spare RW register reset by por reset; [10:8] : PCIe Device Type: 3'b000 - Endpoint mode; 3'b010 …
37063 … DataWidth:0x2 // 0-bypass the Vmain PORBG. for Vmain POR; if sel=1 the output wil be MISC_REGI…
37064 …// Bypass to the FUNC_HIDE pin. Bit 0 - bypass select; Bits[15:1] - bypass value per function (1 -…
37069 … DataWidth:0x1 // NIG debug mux vector control. 0 - NIG0 debug vector is output to IFMUX; 1 -…
37070 …Drives misc_cnig_mux_4port_shared_mdio_en output. Applicable both in 2-port and 4-port mode. TBD: …
37071 …1 // NIG EMAC debug source selector. If 0 - path0 gmii/mii emac debug outputs are selected by N…
37072 …s:R DataWidth:0x2 // SEL_VAUX_B - Control to power switching logic. [0] - output value drive…
37078 …-chip PHY devices and MAC ports to the four MDIO domains. It is only used when MISC_REGISTERS_MDIO…
37079 … asserted (Hot Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state. Reset…
37082 …it as a '1' will cause the chip to do an internal reset exactly like a power-up reset. There is no…
37083 …e controls. Bit 0 - Vmain OTP reset; Bit 1 - isolation_logic_b; Bit 2 - unprepared_power_down_dete…
37084 …he controls. Bit 0 - Vmain OTP reset; Bit 1 - isolation_logic_b; Bit 2 - uprepared_power_down_dete…
37087 …-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bi…
37088 …0UL //Access:RW DataWidth:0x1 // [0]clock storm bypass: 0-select Storm SPLL clock; 1-select e…
37089 … by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset…
37090 … by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset…
37091 … the Driver to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset…
37092 … 0x009760UL //Access:R DataWidth:0x1 // 0 - VAUX is not present (external pin is 0); 1 …
37093 …7-6] RESERVED (FLOAT: these IOs are outputs only). [5-4] CLR: When any of these bits is written as…
37096 … the chip. This value starts at 0x0 for the A0 tape-out and increments by one for each all-layer t…
37097 …f the chip. This value starts at 0x00 for each all-layer tape-out and increments by one for each t…
37100 …nly. The PCI power will always read as '0' in this state; as if the chip is in Out-Of-Box WOL mode.
37103 … 0x00978cUL //Access:RW DataWidth:0x10 // Accounts for Hard reset de-assertion. Is reset o…
37105 … 0x009794UL //Access:RW DataWidth:0x10 // Accounts for Core de-reset assertion. Is r…
37107 … 0x00979cUL //Access:RW DataWidth:0x10 // Accounts for PERST_B reset de-assertion. Is reset o…
37109 … DataWidth:0x10 // Accounts for PCI_RST_N assertion when the chip is in un-prepared state. Is re…
37110 … 0x0097a8UL //Access:RW DataWidth:0x10 // Accounts for PCI_RST_N de-assertion. Is reset o…
37111 …-prepared state, hard reset is asserted. When =0, when ptw_miscs_pcie_hot_reset is asserted (Hot R…
37113 …UL //Access:RW DataWidth:0x20 // Eco reserved. Global register. [31:30] - used to programm loo…
37115 …s:RW DataWidth:0x9 // [31:9] Reserved [8] OTP_AVS_SRAM_MON_VALID [7:6] OTP_AVS_SRAM_MO…
37120 …r-ride: When set, over-ride DAC code from AVS monitor with on from this register [20:11] VMgmt DAC…
37121 …- Per-TC packet available status; [10] - STORM FIFO; [9] - BTB SOP FIFO for engine 0; [8] - BTB S…
37122 …- STORM FIFO almost full; [10] - STORM FIFO full; [9] - BTB SOP FIFO full for engine 0; [8] - …
37123 …7] - Received packet from BTB IF0 of engine 0; [6] - Received packet from BTB IF0 of engine 1; […
37124 …7:4] - storm_init_crd: Credits for the output STORM Packet interface. [3:2] - storm_pkt_dst: Sel…
37125 …-full Threshold. [29:25] - Btb_if0_fifo_almfull_thr: Almost-full threshold for BTB main traffic F…
37154 …R DataWidth:0x8 // This bit indicates that the data currently in bits 7:0 of this register w…
37167 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
37168 … enable. If 0 - the acknowledge input is disregarded; valid is deasserted; full is asserted; all o…
37169 …t;Master) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
37177 … 0x00c064UL //Access:RW DataWidth:0x1 // Command 7 go.
37231 … 0x00c400UL //Access:RW DataWidth:0x4 // DMAE- PCI Request Interfac…
37232 …404UL //Access:RW DataWidth:0x1 // Relaxed ordering. 0-strict PCI ordering is used;1-PCI-X re…
37233 … 0x00c408UL //Access:RW DataWidth:0x1 // 0-PCI type cache snoop protection is required;…
37234 …00c40cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 initial value is all zeroes; if 1 - t…
37235 …x1 // If 0 - the CRC-16 final calculation result isn't byte swapped; if 1 - the CRC-16 final ca…
37236 …0c414UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16c initial value is all zeroes; if 1 - t…
37237 …c418UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 T10 initial value is all zeroes; if 1 -…
37238 …00c41cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-32 initial value is all zeroes; if 1 - t…
37239 …x1 // If 0 - the CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final ca…
37240 …0c424UL //Access:RW DataWidth:0x1 // If 0 - the CRC-32c initial value is all zeroes; if 1 - t…
37241 …1 // If 0 - the CRC-32c final calculation result isn't byte swapped; if 1 - the CRC-32c final c…
37242 …0x00c42cUL //Access:RW DataWidth:0x1 // If 0 - the final checksum equal 0 won't be changed;if…
37243 …st ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; …
37244 …st ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; …
37245 … 0x00c438UL //Access:RW DataWidth:0x1 // When set discards 1- or 2-Dword PCI transact…
37246 … 0x00c43cUL //Access:RW DataWidth:0x14 // GRC address in case 1- or 2-Dword PCI transact…
37250 …- Bidirectional shared data structure; 01 - Device writes/reads then device reads/writes soon; 10 …
37255 …: 0 - VN Virtualized NIC (Used for VF access); 1 - PDA Physical Device Assignment (Assigned to VM-…
37272 …- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other e…
37273 …- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other e…
37281 …as follows: 0-NONE; 1-DoubleBwTx (DoubleBw the TX side); 2-DoubleBwRx (DoubleBw the RX side); 3-Cr…
37282 …dex for slot 0 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37283 …dex for slot 1 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37284 …dex for slot 2 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37285 …dex for slot 3 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37286 …dex for slot 4 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37287 …dex for slot 5 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37288 …dex for slot 6 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37289 …its are a client index for slot 7 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 …
37290 …dex for slot 8 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37291 …dex for slot 9 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37292 …ex for slot 10 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37293 …ex for slot 11 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37294 …ex for slot 12 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37295 …ex for slot 13 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37296 …ex for slot 14 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37297 …ex for slot 15 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37299 …- 128b STORM (A and B) data is logged 1 - 64b STORM (A and B) data + 4 different (in general case)…
37300 …only: These bits indicate the target of the debug data: 0 - internal buffer; 1 - NIG; 2 - PCI.
37301 …-one shot (newest data is thrown) as follows: (a) When DBG_REGISTERS_DEBUG_TARGET =0 (internal buf…
37322 …when DBG_REGISTERS_DEBUG_TARGET =1 (NIG) and DBG_REGISTERS_FULL_MODE =0 (one-shot); WB Read Only (…
37333 …rget_packet_size data byte each); Relevant only when debug_target=1 (NIG) & full_mode=0 (one-shot).
37340 …- no grants will be made to the storms when the internal buffer is almost full. When the buffer w…
37341 …r should be >= 12. Together with DBG_REG_BUFFER_THR_HIGH provides histerezis-like mechanism to set…
37342 …tes logical/physical address in PCI request as follows: (a) 1 - logical address; (b) 0 - physical…
37343 … to internal buffer to be output to IFMUX interface. 0 - bits[31:0] 1 - bits[63:32] 2:6 - etc. 7 -…
37344 …h:0x9 // Debug only: together with DBG_REG_BUFFER_THR provides histerezis-like mechanism to set…
37345 …on is done as follows: bits 255:0 - data; bits 263:256 - frame; bits 271:264 - valid; bits 303:272…
37347 …the pattern to be compared with the vector {sop[1:0]; id[31:0]; valid[7:0];frame[7:0]; data[255:0]…
37349 …tor as follows: (a) 1 - bit is masked. This bit won't be compared with the DBG_REGISTERS_EXPECTED…
37351 … pattern recognition feature is disabled/enabled as follows: (a) 1 - disabled; (b) 0 - enabled;.
37352 …nition feature as follows: (a) 1 - stop debug data storgae when the expected pattern is initially…
37353 …occurence as follows: (a) 1 - enable continuously data storage after/before first occurence of pat…
37354 … // (a) 0 - trigger machine is off (all data will bypass the triggering machine); dbg_sem_trgr_…
37355 …010550UL //Access:RW DataWidth:0x1 // (a) 0 - triggering interleaved messages is disabled. (b…
37356 … to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits…
37357 … to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits…
37358 … to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits…
37359 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37360 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37361 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37374 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37375 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37376 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37377 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37378 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37379 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37380 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37381 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37382 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37383 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37384 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37385 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37386 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37387 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37388 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37389 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37390 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37391 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37392 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37393 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37394 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37395 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37396 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37397 …r is determined as follows: data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*(trigger_state_s…
37446 … 0x0106bcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37447 … 0x0106c0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37448 … 0x0106c4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37449 … 0x0106c8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37450 … 0x0106ccUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37451 … 0x0106d0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37452 … 0x0106d4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37453 … 0x0106d8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37454 … 0x0106dcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37455 … 0x0106e0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37456 … 0x0106e4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37457 … 0x0106e8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37458 … 0x0106ecUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37459 … 0x0106f0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37460 … 0x0106f4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37461 … 0x0106f8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37462 … 0x0106fcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37463 … 0x010700UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37464 … 0x010704UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37465 … 0x010708UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37466 … 0x01070cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37467 … 0x010710UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37468 … 0x010714UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37469 … 0x010718UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37470 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37471 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37472 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37473 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37474 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37475 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37476 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37477 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37478 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37479 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37480 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37481 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37482 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37483 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37484 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37485 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37486 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37487 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37488 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37489 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37490 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37491 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37492 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37493 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37614 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37615 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37616 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37617 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37618 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37619 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37620 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37621 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37622 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37623 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37624 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37625 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37626 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37627 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37628 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37629 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37630 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37631 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37632 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37633 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37634 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37635 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37636 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37637 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37686 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37687 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37688 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37689 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37690 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37691 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37692 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37693 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37694 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37695 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37696 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37697 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37698 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37699 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37700 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37701 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37702 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37703 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37704 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37705 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37706 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37707 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37708 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37709 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37713 … 0x010968UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37714 … 0x01096cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37715 … 0x010970UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37718 …-1:32*trigger_indirect0_offseti[2:0]] in cycle trigger_indirect0_offseti[11:3] from the last messa…
37719 …-1:32*trigger_indirect0_offseti[2:0]] in cycle trigger_indirect0_offseti[11:3] from the last messa…
37720 …-1:32*trigger_indirect0_offseti[2:0]] in cycle trigger_indirect0_offseti[11:3] from the last messa…
37729 …-1:32*trigger_indirect1_offseti[2:0]] in cycle trigger_indirect1_offseti[11:3] from the last messa…
37730 …-1:32*trigger_indirect1_offseti[2:0]] in cycle trigger_indirect1_offseti[11:3] from the last messa…
37731 …-1:32*trigger_indirect1_offseti[2:0]] in cycle trigger_indirect1_offseti[11:3] from the last messa…
37739 …- Filter off; in that case all data should be transmitted to the internal buffer without any filte…
37740 … to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits…
37741 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37742 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37743 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37744 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37753 … 0x010a08UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37754 … 0x010a0cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37755 … 0x010a10UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37756 … 0x010a14UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37761 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37762 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37763 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37764 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37793 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37794 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37795 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37796 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37798 … 0x010a7cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37800 …cess:RW DataWidth:0x8 // The message length-1 of the recorded part size in terms of numbers o…
37801 …nt: (a) 00 - record from time=0; (b) 01 - record rcrd_on_window_pre_num_chunks chunks to internal…
37802 … (a) 0- enable recording data upon triggering event; in that case record for rcrd_on_window_post_…
37805 … 0x010a98UL //Access:RW DataWidth:0x10 // 16-bit opaque FID for pc…
37815 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37816 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37817 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37818 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37819 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37820 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37821 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37822 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37823 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37824 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37825 …- bits[31:0]; [5:3] - bits[63:32]; [8:6] - bits[95:64]; [11:9] - bits[127:96]; [14:12] - bits…
37826 …ll be added to trailer when STORM will be selected: B2:0 - TSEM; B5:3- MSEM; B8:6- USEM; B11:9- XS…
37835 …0x4 // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 M…
37836 … in granularity of chunks. The allowed range is 1-48 that suits to packet size of 256B-12KB. Value…
37842 … set and frame[5] is set or bit[5] is set and frame[6] is set or bit[6] is set and frame[7] is set.
37843 … set and valid[5] is set or bit[5] is set and valid[6] is set or bit[6] is set and valid[7] is set.
37844 …tput from DBG to SEM block as result of trigger event: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is …
37845 … // Current state machine status of trigger block in dbg_trigger.v: states 0-2 are functional stat…
37846 …ock in dbg_trigger_state.v: : state 0 - NOT_HNDLR_MSG; state 1- FRST_HNDLR_MSG; state 2- SCND_HNDL…
37849 …- constraint 0 set0; B1 - constraint 1 set0; B2 - constraint 2 set0; B3 - constraint 3 set0; B4 - …
37851 …DataWidth:0x20 // Debug only: These bits represent the total number of 128-bit cycles sent from …
37855 … status in trailer block : 0 - WAIT_FOR_NEW_LINE; 1- END_OF_CHUNK; 2 - SEND_ADDITIONAL_CHUNK; 3 - …
37857 … // Statistics. Match constraint status. B0 - constraint 0; B1 - constraint 1; B2 - constraint …
37863 …1 // When set to 0 - only client which HW ID is defined in DBG_REGISTERS_FILTER_ID_NUM.FILTER_I…
37864 …ccess:RW DataWidth:0x1 // When 0 - SEMI core A is selected for all trigger/filter related act…
37873 …word address 6 and 7 are allocated for lock bits and to program these bits lock command must be us…
37876 …K signal; [6]: debug_mode_set: This bit is set when ctrl_wr_cmd is issued; [7]: mst_fsm_error: An …
37878 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37888 … 0x02021cUL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
37908 … 0x020238UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
37909 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37911 … 0x02023cUL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3)…
37957 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
37960 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
37965 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37966 … 0x020264UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
37967 … 0x020268UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
37968 … 0x020268UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
37970 … 0x02026cUL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-2 000000…
37973 … 0x020270UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-3 000000…
37976 … 0x020274UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-4 000000…
37979 … 0x020278UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-5 000000…
37986 … 0x020284UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
37988 … 0x020288UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3)…
37991 … 0x02028cUL //Access:R DataWidth:0x4 // Delay for each channel 2-5 is completed.
38003 …-enter frequency acquisition state, without resetting the initial frequency (starts from current f…
38006 …-enter frequency acquisition state, without resetting the initial frequency (starts from current f…
38012 …rite 4 For 3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 F…
38019 … 0x0202b4UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
38024 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38026 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
38030 … 0x0202c8UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38032 … 0x0202ccUL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38033 … 0x0202d0UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
38035 … 0x0202d4UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3)…
38036 …-enter frequency acquisition state, without resetting the initial frequency (starts from current f…
38038 …-enter frequency acquisition state, without resetting the initial frequency (starts from current f…
38044 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38045 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38046 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38047 …rite 4 For 3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 F…
38048 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38049 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38050 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38052 …2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is clea…
38053 …2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is clea…
38054 …2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is clea…
38073 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38088 … 0x020304UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38089 … 0x0204b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38090 … 0x0202a8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38091 … 0x020308UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38092 … 0x020308UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38093 … 0x0204b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38094 … 0x0202acUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38095 … 0x02030cUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38097 … 0x0204bcUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38098 … 0x0202b0UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38099 … 0x020310UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38100 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38101 … 0x0204c0UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38102 … 0x0202b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38103 … 0x020314UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38104 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38105 … 0x0204c4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38106 … 0x0202b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38107 … 0x020318UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38108 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38109 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38110 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38111 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38117 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38118 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38119 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38120 … 0x020324UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL …
38121 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38122 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38123 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38129 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38130 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38131 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38133 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38134 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38135 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38152 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN go…
38156 … (0x1<<7) // This bit generates an interrupt when PERST# …
38157 …PC_REG_INT_STS_0_PERST_DEASSERT_SHIFT 7
38174 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38186 …SERT (0x1<<7) // This bit masks, …
38187 …PC_REG_INT_MASK_0_PERST_DEASSERT_SHIFT 7
38212 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN go…
38216 … (0x1<<7) // This bit generates an interrupt when PERST# …
38217 …PC_REG_INT_STS_WR_0_PERST_DEASSERT_SHIFT 7
38234 … 0x020344UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38242 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN go…
38246 … (0x1<<7) // This bit generates an interrupt when PERST# …
38247 …PC_REG_INT_STS_CLR_0_PERST_DEASSERT_SHIFT 7
38264 … 0x020348UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38268 …-bit compliance enable pins on the ballout. These bits are used to override the pins if needed. 2'…
38273 …ss:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_contro…
38274 …ss:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_contro…
38275 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38276 …_bist_status 0 ccfc_ccam 1 ccfc_scam 2 igu 3 msem 4 prs_gft 5 prs_h 6 prs_l 7 psem 8 psem_vfc 9 qm…
38277 …_bist_status 0 ccfc_ccam 1 ccfc_scam 2 igu 3 msem 4 prs_gft 5 prs_h 6 prs_l 7 psem 8 psem_vfc 9 qm…
38278 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38279 …am bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist…
38280 …am bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist…
38281 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38282 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38283 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38285 …- bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - re…
38286 …- bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - re…
38288 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38289 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38290 … 0x020364UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL …
38291 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38292 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38294 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38295 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38297 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38298 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38300 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38301 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38303 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38304 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38306 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38307 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38309 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38310 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38312 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38313 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38315 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38316 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38318 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38319 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38321 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38322 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38324 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38325 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38327 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38328 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38329 … 0x020398UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38330 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38331 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38332 … 0x02039cUL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38362 … 0x0203c4UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38363 …ess:RW DataWidth:0x6 // Sets the CTL# (# in [0..5]) I/Os of the PADS in non - scan/mbist modes
38365 … 0x0203c8UL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38366 …cess:RW DataWidth:0x2 // Sets the SL# (# in [0..1]) I/Os of the PADS in non - scan/mbist modes
38368 … 0x0203ccUL //Access:R DataWidth:0x8 // PCIe lock signals. 0-unlocked; 1-locked. Global …
38372 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38373 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38414 …//Access:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the…
38422 …//Access:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the…
38424 …cal 0: Normal Operation Mode 1: Powerdown the RESCAL block Transition from 1->0 to start calibrati…
38429 …7] power-up time before starting calibration 2'b00: 32 refclk = 1.28us 2'b01: 128 refclk = 5.12us …
38435 … On-chip Sheet Resistance 0000 -24% ~ -21% 0001 -21% ~ -18% 0010 -18% ~ -15% 0011 -15% ~ -12% 0100…
38441 …hine status 0: POR 1: INIT 2: RESET 3: PWRDN 4: CALIB 5: PONVALID 6: RESULT 7: IDLE Global Registe…
38456 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38457 …2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is clea…
38458 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38464 … 0x0204e8UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38465 … 0x0204ecUL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38466 … 0x0204f0UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38467 … 0x0204f4UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38468 … 0x0204f8UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38469 … 0x0204fcUL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38470 … 0x020500UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38471 … 0x020504UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38499 …I_NIG_TX_EMPTY_EN (0x1<<7) // 0 : NIG Tx is em…
38500 …PMU_REG_LPI_MODE_ENTRY_EN_LPI_NIG_TX_EMPTY_EN_SHIFT 7
38563 …BFF_CAU_IDLE_EN (0x1<<7) // 0 : CAU IDLE is …
38564 …PMU_REG_OBFF_MODE_ENTRY_EN_OBFF_CAU_IDLE_EN_SHIFT 7
38618 …PGL_EMPTY_EN (0x1<<7) // 0 : PGL empty is…
38619 …PMU_REG_L1_MODE_ENTRY_EN_L1_PGL_EMPTY_EN_SHIFT 7
38650 …R_PGL_EMPTY_EN (0x1<<7) // 0 : PGL empty is…
38651 …PMU_REG_LTR_MODE_ENTRY_EN_LTR_PGL_EMPTY_EN_SHIFT 7
38684 …CLK_E1_EN (0x1<<7) // 0 : Shutdown STO…
38685 …PMU_REG_CLK_EN_CONFIG_STORM_CLK_E1_EN_SHIFT 7
38759 …TRY_EN_MCS_CAU_IDLE_EN (0x1<<7) // 0 : CAU IDLE is …
38760 …PMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_CAU_IDLE_EN_SHIFT 7
38813 …NTRY_EN_SCS_CAU_IDLE_EN (0x1<<7) // 0 : CAU IDLE is …
38814 …PMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_CAU_IDLE_EN_SHIFT 7
38867 …Y_EN_NCS_CAU_IDLE_EN (0x1<<7) // 0 : CAU IDLE is …
38868 …PMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_CAU_IDLE_EN_SHIFT 7
38921 …RY_EN_PCS_CAU_IDLE_EN (0x1<<7) // 0 : CAU IDLE is …
38922 …PMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_CAU_IDLE_EN_SHIFT 7
39016 …S_1_MSEM_SEM_IDLE_E0_ISIG_STATUS (0x1<<7) // Current status o…
39017 …PMU_REG_CPMU_INPUT_SIG_STATUS_1_MSEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT 7
39063 …S_2_PGLUE_PATH_IN_D3_E1_ISIG_STATUS (0x1<<7) // Current status o…
39064 …PMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PATH_IN_D3_E1_ISIG_STATUS_SHIFT 7
39116 …S_3_IGU_CPMU_EEE_PENDING_INTERRUPT_E1_ISIG_STATUS (0x1<<7) // Current status o…
39117 …PMU_REG_CPMU_INPUT_SIG_STATUS_3_IGU_CPMU_EEE_PENDING_INTERRUPT_E1_ISIG_STATUS_SHIFT 7
39153 …US_ERSTCLK_NW_CLK_SLOWDOWN_CMN_OSIG_STATUS (0x1<<7) // Current status o…
39154 …PMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_CMN_OSIG_STATUS_SHIFT 7
39263 … (0x1<<2) // 0 -> Send all broadcast packets to the appropriate networ…
39265 … (0x1<<3) // 0 -> Send all multicast packets to the appropriate networ…
39267 … (0x1<<4) // 0 -> only MAC address is used for comparison to detect Host2B…
39269 … (0x1<<5) // 0 -> Do not enable source MAC address learning for packets from…
39271 … (0x1<<6) // 0 -> Entries in SA Learning Cache are valid even after they…
39273 …EN (0x1<<7) // Setting this bit…
39274 …CSI_REG_CONFIG_FLOW_CONTROL_EN_SHIFT 7
39279 … (0x1<<10) // 0 -> Select NCSI RMII interface as the MII port …
39281 … (0x1<<11) // 0 -> Select NCSI RMII interface as the Management Po…
39283 … (0x1<<12) // 1 -> When BMB asserts any full condition, drop all the p…
39285 … (0x1<<13) // 1 -> When this bit is set, all pass through traffic will be directed to hos…
39370 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39372 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39374 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39376 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39378 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39380 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39382 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39384 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39422 … (0x3f<<1) // NCSI block has the capability to remove up-to six TAGs present i…
39424 …7) // This bits are used to configure how the inner vlan tag needs to be handled. Inner VLAN is al…
39425 …CSI_REG_TAG_RM_CONFIG_INNER_VLAN_RM_SHIFT 7
39426 …from the packet before sending it out to BMC. it is expected that once a non-zero value is set, al…
39438 …criptor for a BMC to Network packet if there is a VLAN header in the packet and VLAN ID is non-zero
39451 …to '1' causes the hardware arbitration scheme to begin. Any NCSI port can re-start the arbitration.
39455 …O_BYPASS (0x1<<7) // Setting this fie…
39456 …CSI_REG_SIDEBAND_ARB_ARB_AUTO_BYPASS_SHIFT 7
39457 … (0x1f<<8) // This field is a programmable inter-packet gap for when t…
39465 …mber of Ingress clock cycles that the arbitration master will wait before re-starting the arbitrat…
39484 …started. Setting a value of all 1s in this register will guarantee a store-and-forward operation. …
39509 …er. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 …
39510 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39511 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39512 …er. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 …
39513 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39514 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39515 …er. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 …
39516 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39517 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39519 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39522 … [2]: msdm. Bit [3]: psdm. Bit [4]: ysdm. Bit [5]: usdm Bit [6]: tsdm. Bit [7]: xsdm. Bit [8]: dbu…
39525 …-7 are applicable. The fields: Bit [0]: PF #0. Bit [1]: PF #1. Bit [2]: PF #2. Bit [3]:…
39527 …L = 1. Value of all 1s is applicable and represents VF not valid. BB: only bits 0-6 are applicable.
39528 …sked, access with the port is not written to the trace FIFO. BB: only bits 0-1 are applicable. The…
39530 …_OV. Over-ride to VN PROTECTION. Bit [5]: PDA_OV. Over-ride to PDA PROTECTION. Bit [6]: HV_OV. Ove…
39627 …_FWD_BB (0x1<<7) // Terminate/Forwar…
39628 …MAC_REG_COMMAND_CONFIG_PAUSE_FWD_BB_SHIFT 7
39639 …X are disabled. Config registers are not affected by sw reset. Write a 0 to de-assert the sw reset.
39667 …-of-band egress flow control is enabled. When this bit is set and input pin ext_tx_flow_control is…
39673 … 0x051014UL //Access:RW DataWidth:0x10 // Defines a 16-Bit maximum frame len…
39674 … 0x051018UL //Access:RW DataWidth:0x10 // 16-Bit value; sets; in i…
39708 …xcluding SFD to be programmable from min of 2 bytes to the max allowable of 7 bytes; with granular…
39709 …G between Back-to-Back packets. This is the IPG parameter used exclusively in Full-Duplex mode whe…
39710 …dth:0x10 // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
39720 …E_PREDICTION_MODE_BB (0x1<<7) // When set to 1; e…
39721 …MAC_REG_UMAC_EEE_CTRL_LP_IDLE_PREDICTION_MODE_BB_SHIFT 7
39722 …the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register…
39723 …the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register…
39727 …tate when it receives packet for transmission. The decrement unit is 1 micro-second. This register…
39728 …tate when it receives packet for transmission. The decrement unit is 1 micro-second. This register…
39737 … (0x7f<<16) // Non Back-to-Back Transmit IPG pa…
39739 … (0x7f<<24) // Non Back-to-Back Transmit IPG pa…
39788 …B; fixed. It should be noted; that as number of preamble bytes reduces from 7; the IPG also increa…
39790 …ss:RW DataWidth:0x20 // This register contains the bits [31:0] in the 48-bit MAC address. The…
39792 …L_BB (0x1<<0) // Read-only field assertion …
39794 …TY_BB (0x1<<1) // Read-only field assertion …
39798 …s:RW DataWidth:0x10 // This register contains the bits [47:32] in the 48-bit MAC address. The…
39815 …- skipped (unsupported) 1 - stackvlan (unsupported) 2 - carrerr (on by default) 3 - codeerr (on by…
39817 … 0x051338UL //Access:RW DataWidth:0x8 // probe address bit 7 - U/L bit 6 - GMII/XMGII CL…
39830 … (0x1<<0) // Enables the PPP-Tx functionality.
39832 … (0x1<<1) // Enables the PPP-Rx functionality.
39864 …_I_ECC_1_RF_INT_E5 (0x1<<7) // This bit masks, …
39865 …CP2_REG_PRTY_MASK_H_0_MEM004_I_ECC_1_RF_INT_E5_SHIFT 7
39900 …_I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, …
39901 …CP2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT 7
39934 …004_I_ECC_1_EN_E5 (0x1<<7) // Enable ECC for m…
39935 …CP2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_1_EN_E5_SHIFT 7
39968 …0_MEM004_I_ECC_1_PRTY_E5 (0x1<<7) // Set parity only …
39969 …CP2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_1_PRTY_E5_SHIFT 7
40002 …TED_0_MEM004_I_ECC_1_CORRECT_E5 (0x1<<7) // Record if a corr…
40003 …CP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_1_CORRECT_E5_SHIFT 7
40046 …_I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, …
40047 …PTE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT 7
40056 … DORQ FIFO. When the occupancy is more than that number, local edpm_en is de-asserted. It is than …
40067 …_I_MEM_PRTY_BB (0x1<<7) // This bit masks, …
40068 …CIE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_SHIFT 7
40083 …_I_MEM_PRTY_K2_E5 (0x1<<7) // This bit masks, …
40084 …CIE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_E5_SHIFT 7
40322 …ET_STATUS_1_TRAINING_RST_N_K2_E5 (0x1<<7) //
40323 …CIE_REG_RESET_STATUS_1_TRAINING_RST_N_K2_E5_SHIFT 7
40342 …MSG_UNLOCK_K2_E5 (0x1<<16) // One-cycle pulse that indi…
40344 …TURNOFF_K2_E5 (0x1<<17) // One-clock-cycle pulse that i…
40349 … to wake up the PMC state machine from a D1, D2 or D3 power state. Upon wake-up, the core sends a …
40415 … 0x054328UL //Access:R DataWidth:0x5 // pm_dev_num[4:0]- Device number
40416 … 0x05432cUL //Access:R DataWidth:0x8 // pm_bus_num[7:0]- Bus Number
40427 … 0x054358UL //Access:RW DataWidth:0x15 // Power Budget Table entry 7
40466 …ECT_K2_E5 (0x1<<7) // L1 Entry detecte…
40467 …CIE_REG_INT_STS_L1_ENTRY_DETECT_K2_E5_SHIFT 7
40472 … (0x1<<10) // Do not use -- keep mask bit set to…
40478 … (0x1<<13) // Non-Fatal Error Message s…
40484 … (0x1<<16) // Vendor-Defined Message recei…
40501 …TECT_K2_E5 (0x1<<7) // This bit masks, …
40502 …CIE_REG_INT_MASK_L1_ENTRY_DETECT_K2_E5_SHIFT 7
40536 …DETECT_K2_E5 (0x1<<7) // L1 Entry detecte…
40537 …CIE_REG_INT_STS_WR_L1_ENTRY_DETECT_K2_E5_SHIFT 7
40542 … (0x1<<10) // Do not use -- keep mask bit set to…
40548 …E5 (0x1<<13) // Non-Fatal Error Message s…
40554 … (0x1<<16) // Vendor-Defined Message recei…
40571 …_DETECT_K2_E5 (0x1<<7) // L1 Entry detecte…
40572 …CIE_REG_INT_STS_CLR_L1_ENTRY_DETECT_K2_E5_SHIFT 7
40577 … (0x1<<10) // Do not use -- keep mask bit set to…
40583 …_E5 (0x1<<13) // Non-Fatal Error Message s…
40589 … (0x1<<16) // Vendor-Defined Message recei…
40608 …_E5 (0x1<<0) // Power-on reset occurred.
40618 …_2_K2_E5 (0x1<<5) // Non-sticky register reset…
40622 …RST_2_K2_E5 (0x1<<7) // PIPE reset occur…
40623 …CIE_REG_RESET_STATUS_2_PIPE_RST_2_K2_E5_SHIFT 7
40640 …(0x1<<16) // Soft power-on reset occurred. NOTE: This bit is unreliable for indication of a soft p…
40650 …2_K2_E5 (0x1<<21) // Soft non-sticky register reset…
40678 …EM013_I_MEM_PRTY_K2_E5 (0x1<<7) // This bit masks, …
40679 …XPREQBUS_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_E5_SHIFT 7
40718 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
40719 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
40735 …IFO_OVFL_ERR (0x1<<7) // CFC load request…
40736 …ORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT 7
40737 … (0x1<<8) // CFC load request FIFO under-run
40741 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40760 …FIFO_OVFL_ERR (0x1<<7) // This bit masks, …
40761 …ORQ_REG_INT_MASK_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT 7
40785 …Q_FIFO_OVFL_ERR (0x1<<7) // CFC load request…
40786 …ORQ_REG_INT_STS_WR_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT 7
40787 …RR (0x1<<8) // CFC load request FIFO under-run
40791 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40810 …EQ_FIFO_OVFL_ERR (0x1<<7) // CFC load request…
40811 …ORQ_REG_INT_STS_CLR_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT 7
40812 …ERR (0x1<<8) // CFC load request FIFO under-run
40816 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40840 …_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
40841 …ORQ_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5_SHIFT 7
40871 …en multiplied by 16, is equal to the maximum ICID plus 1 of connection type 7. This is per PF conf…
40879 …en multiplied by 16, is equal to the maximum ICID plus 1 of connection type 7. This is per PF conf…
40880 …2 // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 me…
40881 …2 // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 me…
40904 … 0x1004a8UL //Access:RW DataWidth:0x2 // Target value used in DEMS mode for DEMS = 7.
40905 …UL //Access:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 7. Bit 2 of AggValSel …
40906 …4b0UL //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS = 7. Reset value = SET_A…
40907 … 0x1004f4UL //Access:RW DataWidth:0x2 // AGG command value in PWM non-DPM mode.
40910 …n 2 port mode it is equal to 0 for all PF-s. In 4 port mode, it is equal to 0 for even PF-s and to…
40915 …ccess:RW DataWidth:0x1 // Enable DPM doorbells for all this PF child VF-s. In case not set th…
40929 … 0x100810UL //Access:RW DataWidth:0x1 // If set then CCFC mini-cache is enabled.
40931 …and first DPM doorbell appears it is truncated to one entry and aborted; non-first doorbell is dro…
40932 … doorbell appears it is truncated to one entry and DpmAbort flag is set; non-first doorbell is sil…
40946 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40947 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40948 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40949 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40952 …L //Access:RW DataWidth:0x20 // Enable bit per each RoCE Opcode 5 LSB-s. N-th bit set means co…
40953 … // If 0 - the RoCE CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final …
40969 … 0x100918UL //Access:RW DataWidth:0x2 // TPH Hint value in case of non-inline L2 EDPM.
40970 … 0x10091cUL //Access:RW DataWidth:0x3 // ATC attribute value of non-inline L2 EDPM.
40972 … 0x100924UL //Access:RW DataWidth:0xe // Maximum non-inline L2 EDPM PktSiz…
40973 … 0x100928UL //Access:RW DataWidth:0x8 // The maximum number of WORD-s which the PBF may a…
40980 …DataWidth:0xb // Counter of DORQ FIFO entries used by corresponding PF or any of its child VF-s.
40982 … number of DORQ FIFO entries used by corresponding PF or any of its child VF-s. This is a per PF c…
40992 …de is active and all doorbells are dropped at the entrance to DORQ FIFO. De-asserted when auto_di…
40995 … 0x1009fcUL //Access:R DataWidth:0x20 // Accounts for any non-DPM doorbell or first…
41003 …0 // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_deta…
41004 …-armed by db_drop_details_rel. The following details of the transaction will be recorded: Doorbell…
41005 …7 // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_deta…
41007 …- Size of the data is not equal to 4 or to a multiple of 8 bytes; 1 - 2 LSB-s of the address are n…
41013 …- DPM doorbell and rewind configuration of DPM timer (dpm_timeout) is 0; 1 - PF DPM doorbell and i…
41015 …- DPM doorbell and rewind configuration of DPM timer (dpm_timeout) is 0; 1 - First DPM doorbell an…
41027 … be done at first cycle of first DPM doorbell by the size of DpmSize. No non-first DPM doorbells s…
41032 …ue of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Re…
41034 …-cache was used. 36 - CDU Validation Error; 35 - CFC Load Cancel; 34 - CFC Load Error; 33 - CFC LC…
41039 …Width:0x1 // comment="Selects IEDPM payload endianity. 0 - little endian (lsB first); 1 - big e…
41053 …- DPM FSM state [194:192] - DbAggValSel [191:190] - DbAggCmd [189:182] - DbAggFlgCmd [181] - IEDPM…
41087 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41088 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41089 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41090 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41091 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41092 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41093 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41094 … as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per c…
41095 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41096 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41097 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41098 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41099 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41100 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41101 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41102 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41110 …lect which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 7.
41133 …//Access:RW DataWidth:0x1 // QM Bypass mode is enabled for XCM messages for connection type 7.
41134 …th:0x1 // QM Bypass mode is enabled for XCM messages for connection type 7. Per connection type.
41157 …ccess:RW DataWidth:0x1 // Indicates whether DPI validation is supported for connection type 7.
41158 …0x1 // Indicates whether DPI validation is supported for connection type 7. Per connection type.
41181 …UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell for connection type 7.
41182 …UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell for connection type 7.
41205 …text to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 7.
41206 …text to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 7.
41229 … 0x100630UL //Access:RW DataWidth:0x8 // Enable for XCM counter flag command for connection 7.
41230 … 0x102a04UL //Access:RW DataWidth:0x8 // Enable for XCM counter flag command for connection 7.
41253 … 0x100650UL //Access:RW DataWidth:0x8 // Enable for TCM counter flag command for connection 7.
41254 … 0x102a44UL //Access:RW DataWidth:0x8 // Enable for TCM counter flag command for connection 7.
41277 … 0x100670UL //Access:RW DataWidth:0x8 // Enable for UCM counter flag command for connection 7.
41278 … 0x102a84UL //Access:RW DataWidth:0x8 // Enable for UCM counter flag command for connection 7.
41301 …0690UL //Access:RW DataWidth:0x8 // Enable for XCM aggregation value command for connection 7.
41302 …2ac4UL //Access:RW DataWidth:0x8 // Enable for XCM aggregation value command for connection 7.
41325 …06b0UL //Access:RW DataWidth:0x8 // Enable for TCM aggregation value command for connection 7.
41326 …2b04UL //Access:RW DataWidth:0x8 // Enable for TCM aggregation value command for connection 7.
41349 …06d0UL //Access:RW DataWidth:0x8 // Enable for UCM aggregation value command for connection 7.
41350 …2b44UL //Access:RW DataWidth:0x8 // Enable for UCM aggregation value command for connection 7.
41364 … // If 0 - the iWARP CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final…
41365 … //Access:RW DataWidth:0x20 // Enable bit per each iWARP Opcode 5 LSB-s. N-th bit set means co…
41380 …the transaction will be recorded: Doorbell DPM type. 0 - Legacy 1 - RDMA 2 - L2 Inline 3 - L2 Non-…
41385 …- First DPM doorbell does not match DPM global start conditions at CFC load response for Internal …
41387 …- First DPM doorbell does not match DPM global start conditions at CFC load response for Internal …
41388 …-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: IEDPM…
41389 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41390 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41391 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41392 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41394 …- First QWord (offset 0) arives on IEDPM buffer which is not free; 3 - Non-first QWord (offset oth…
41416 …ty type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 7.
41432 …ve flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 7.
41448 …ffinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 7.
41461 …- mapping memory; Bit 1 - SB memory (producer and consumer); Bit 2 - SB interrupt before mask and …
41463 …// If enabled the IGU forwards write/read requests to the TPH interface. 1 - enabled; 0 - disabled.
41465 …ed the IGU allows to VF to send cleanup commands on the int ack address. 1 - enabled; 0 - disabled.
41467 …the IGU allows bypass mode of the rate limiter when the system is empty. 1 - enabled; 0 - disabled.
41473 … 0x18006cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
41492 …D_WITH_SIMD_DIS (0x1<<7) // During interrupt…
41493 …GU_REG_INT_STS_DURIN_INT_READ_WITH_SIMD_DIS_SHIFT 7
41515 …AD_WITH_SIMD_DIS (0x1<<7) // This bit masks, …
41516 …GU_REG_INT_MASK_DURIN_INT_READ_WITH_SIMD_DIS_SHIFT 7
41538 …READ_WITH_SIMD_DIS (0x1<<7) // During interrupt…
41539 …GU_REG_INT_STS_WR_DURIN_INT_READ_WITH_SIMD_DIS_SHIFT 7
41561 …_READ_WITH_SIMD_DIS (0x1<<7) // During interrupt…
41562 …GU_REG_INT_STS_CLR_DURIN_INT_READ_WITH_SIMD_DIS_SHIFT 7
41579 …I_MEM_PRTY_0_K2 (0x1<<7) // This bit masks, …
41580 …GU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_K2_SHIFT 7
41599 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
41600 …GU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5_SHIFT 7
41689 …I_MEM_PRTY_0_BB (0x1<<7) // This bit masks, …
41690 …GU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_BB_SHIFT 7
41761 …r of MSI/MSIX/ATTN messages sent for the PF: address 0 - number of MSI/MSIX messages; address 1 - …
41771 …Debug: count the number of PXP requests sent on behalf of a specific MSI/MSI-X vector on the SB in…
41785 … 0x180600UL //Access:RW DataWidth:0x14 // IPS statistics - number of messages s…
41787 …- function enable; b1 - MSI/MSIX enable; b2 - INT enable; b3 - attention enable; b4 - single ISR m…
41788 …h:0x9 // d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enabl…
41816 …th:0x1 // PF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41818 …th:0x1 // VF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41829 …idth:0x20 // [15:0] - function number: opaque fid. [28:16] - PXP BAR address; [30:29] - Reserved…
41831 … DataWidth:0x20 // Address 0 - MSI address low (two Lsbit are zero). Address 1 - MSI address hig…
41834 …g is enabled, the match address of the hit response is used to perform a two-cycle …
41836 … read of the entire CAM will be started (or re-started). This will e…
41838 … 0x180864UL //Access:RW DataWidth:0x1 // Enable the RL statistic. 0 - disabled; 1 - enabled.
41868 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41869 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41870 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41871 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41872 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41873 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41874 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41875 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41876 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41877 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41878 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41879 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41880 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41881 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41882 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41883 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41884 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41885 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41886 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41887 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41888 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41889 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41890 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41891 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41892 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41893 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41894 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41895 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41896 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41897 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41899 …UL //Access:RW DataWidth:0x20 // SB interrupt before mask. 0 - prod equal cons. 1 - prod not e…
41901 …UL //Access:RW DataWidth:0x20 // SB interrupt before mask. 0 - prod equal cons. 1 - prod not e…
41902 …UL //Access:RW DataWidth:0x20 // SB interrupt before mask. 0 - prod equal cons. 1 - prod not e…
41903 … 0x180ce0UL //Access:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The b…
41905 … 0x180d00UL //Access:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The b…
41906 … 0x180d04UL //Access:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The b…
41907 … 0x180d20UL //Access:RW DataWidth:0x20 // PBA register. 0 - PBA clear, 1 - PBA set - the appr…
41909 … 0x180d40UL //Access:RW DataWidth:0x20 // PBA register. 0 - PBA clear, 1 - PBA set - the appr…
41910 … 0x180d44UL //Access:RW DataWidth:0x20 // PBA register. 0 - PBA clear, 1 - PBA set - the appr…
41911 …- sets the max value that the rate_counter can reach; [19:10] tick_interval - define the max inter…
41913 …- receives the tick_interval value when reaching zero; or when writing to the tick_interval. The t…
41923 …er - incremented by one when Tick_value reaches zero and decremented whenever a message from that …
41927 …Tph field for attention message. Bits 8:0 - steering tag; bits 12:9 - reserved; bits 14:13 - st hi…
41928 …miter group enable status bit for groups 0-31. For each bit: 0 - the rate limiter of the group is …
41929 …iter group enable status bit for groups 32-63. For each bit: 0 - the rate limiter of the group is …
41930 …/ Rate Limiter group credit status bit for groups 0-31. For each bit: 0 - the group has no credit.…
41931 … Rate Limiter group credit status bit for groups 32-63. For each bit: 0 - the group has no credit.…
41932 …imiter group pending status bit for groups 0-31. For each bit: 0 - there are no pending SB in that…
41933 …miter group pending status bit for groups 32-63. For each bit: 0 - there are no pending SB in that…
41934 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port0.
41935 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port1.
41936 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port2.
41937 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port3.
41939 …L //Access:R DataWidth:0x5 // Debug: [4] - attention write done message is pending (0-no pen…
41940 …518UL //Access:RW DataWidth:0x1 // Debug only: 0 - FIFO collects 64 first error messages; 1 -…
41942 …- fid ([8] - if set - PF; else VF, [7:0] - FID). [12:9] - source (values 0-7 according to PXP sour…
41966 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 0; [7:0] = VF number; if PF - [8] = 1;…
41973 … debug. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM) 8…
41978 …- MSIX read/write; Bit [1] - PBA read/write; Bit [2] - Producer update (or cleanup command through…
41993 … DataWidth:0x18 // Producers only. Address 0-511 match to the mapping memory. Address 512-227:…
41997 …W DataWidth:0x18 // Consumers only. Address 0-511 match to the mapping memory. Address 512-227…
42001 …- valid. [8:1] - vector number (0-128 for PF; 0-63 for VF). [17:9] - FID (if VF: [17] = 0; [16:9] …
42005 …x61 // [63:0] - MSIX message address (bit [1:0] are always zero); [95:64] - MSIX message data; […
42030 …BB_K2 (0x1<<7) // Write to full F…
42031 …AU_REG_INT_STS_CQE_FIFO_ERR_BB_K2_SHIFT 7
42053 …ERR_BB_K2 (0x1<<7) // Write to full F…
42054 …AU_REG_INT_STS_CLR_CQE_FIFO_ERR_BB_K2_SHIFT 7
42076 …RR_BB_K2 (0x1<<7) // Write to full F…
42077 …AU_REG_INT_STS_WR_CQE_FIFO_ERR_BB_K2_SHIFT 7
42099 …_BB_K2 (0x1<<7) // This bit masks, …
42100 …AU_REG_INT_MASK_CQE_FIFO_ERR_BB_K2_SHIFT 7
42132 …I_MEM_PRTY_K2_E5 (0x1<<7) // This bit masks, …
42133 …AU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_E5_SHIFT 7
42152 …I_MEM_PRTY_BB (0x1<<7) // This bit masks, …
42153 …AU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_SHIFT 7
42230 …P_REQ_NS (0x1<<7) // The value of the…
42231 …AU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_NS_SHIFT 7
42245 … number of outstanding write requests without receiving write done. Values 1-128. Zero is not a va…
42246 …appropriate bit will be clear. [0] - PI memory; [1] - SB var memory; [2]- SB address memory; [3] -…
42247 …p on the written SB number. [8:0] - SB absolute index; [9] - Cleanup set/clr (0-clr; 1 - set); [12…
42251 … 0x1c0600UL //Access:RW DataWidth:0x1 // Indicate the size of the CQE. 0 - 32B; 1 - 64B.
42252 …W DataWidth:0x2 // Indicate the size of the AGG unit. 0 - 64B; 1 - 128B; 2 - 256B; 3 - illega…
42253 … 0x1c0608UL //Access:RW DataWidth:0x1 // Flush all command - will flush all the C…
42260 … 0x1c0780UL //Access:R DataWidth:0x20 // Rx timers status. 0 - inactive 1 - active.
42262 … 0x1c0800UL //Access:R DataWidth:0x20 // Tx timers status. 0 - inactive 1 - active.
42266 … 0x1c0980UL //Access:R DataWidth:0x1 // Debug: IGU-CAU request interface…
42267 … 0x1c0984UL //Access:R DataWidth:0x1 // Debug: IGU-CAU command interface…
42279 …ics on. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM); …
42293 … timer command type. One bit for each timer command type: [0] - rewind; [1] - clear; [2] - rewind …
42311 …- FIFO empty; 1 - FIFO not empty. [0] - PXP command FIFO; [1] - reserved; [2] - timers expiration …
42312 …- error typ (1- read request; 2 - reserved; 3 - sb_index >= CAU_NUM_SB or SB index > CAU_NUM_PI/n…
42313 …- source (0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM)…
42314 …a // Debug; [9] if set data valid; [8] previous FSM_sel; [7:4] - previous state; [3:0] - previo…
42316 …h:0x19 // comment="Debug: [15:0] The PF that caused the error- one bit per PF; [24:16] - SB inde…
42318 …e was writing to agg_units_state_read_en register. (i =0-15). 0 - free; 1 - dirty; 2 - clean; 3 - …
42319 …was writing to agg_units_state_read_en register. (i = 16-31). 0 - free; 1 - dirty; 2 - clean; 3 - …
42320 …was writing to agg_units_state_read_en register. (i = 32-47). 0 - free; 1 - dirty; 2 - clean; 3 - …
42321 …was writing to agg_units_state_read_en register. (i = 48-63). 0 - free; 1 - dirty; 2 - clean; 3 - …
42334 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 1; [7:0] = VF number; if PF - [8] = 0;…
42341 … debug. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM); …
42346 … (0x7<<0) // Debug: command type for the debug. [0] - PI producer update; [1] - cleanup; [2] - …
42365 … 0x1c0f0cUL //Access:R DataWidth:0x5 // Debug: FSM state for debug.Idle state value are 0-2
42367 … 0x1c2000UL //Access:WB_R DataWidth:0x80 // Debug: Provides read-only access of the CQ…
42369 … 0x1c2200UL //Access:WB_R DataWidth:0x35 // Debug: Provides read-only access of the IG…
42371 … 0x1c2300UL //Access:WB_R DataWidth:0x62 // Debug: Provides read-only access of the PX…
42373 …2400UL //Access:WB_R DataWidth:0x84 // Debug: Provides read-only access of the PXP write-data FI…
42375 … and PI relative number of each aggregation unit. [0] - valid; [9:1] - absolute SB index; [14:10] …
42377 …7:4] of the address are the current_state and bits [3:0] are the event_id. The data is :[3:0] - ne…
42379 …-2 only); [49:48] TimerRes1 (This value will determine the TX FSM timer resolution in ticks. Valid…
42387 …ry.[15:0] - protocol producer; [22:16] - PiTimeSet (This value determines the TimeSet that the PI …
42394 …- address; [71:64] - valid slots; [84:72] - FID ([13:9] - PF number (in case of VF the parent PF);…
42396 …h:0x18 // The SB timers. For each SB there are two timers: [11:0] - RX timer; [23:12] - TX timer.
42400 … 0x1f0000UL //Access:RW DataWidth:0x1 // Soft reset - reset all FSM.
42401 …UL //Access:W DataWidth:0x1 // Any write to this register triggers MAC-VLAN Cache initializa…
42408 … (0x1<<1) // Load Request Mini-cache validation error
42418 … (0x1<<1) // Load Request Mini-cache validation error
42423 … (0x1<<1) // Load Request Mini-cache validation error
42432 …0168UL //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a PF packet, task-…
42433 …016cUL //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a VF packet, task-…
42434 …0170UL //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a PF packet, task-…
42435 …0174UL //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a VF packet, task-…
42442 … 0x1f0190UL //Access:RW DataWidth:0x1 // Per-PF: If set, override …
42443 … 0x1f0194UL //Access:RW DataWidth:0x20 // Per-opcode requester/resp…
42444 … 0x1f0198UL //Access:RW DataWidth:0x1 // Per-PF: If set, a load re…
42445 … 0x1f019cUL //Access:RW DataWidth:0x1 // If set, CFC load mini-cache is enabled.
42446 … 0x1f01a0UL //Access:RW DataWidth:0x1 // 0-search response initiator type,1-Excha…
42447 … 0x1f01a4UL //Access:RW DataWidth:0x1 // 0-Exchange Context field in the fcoe search req is z…
42474 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
42475 …RS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 7
42538 …I_ECC_RF_INT_K2 (0x1<<7) // This bit masks, …
42539 …RS_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT_K2_SHIFT 7
42610 …I_MEM_PRTY_BB (0x1<<7) // This bit masks, …
42611 …RS_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_SHIFT 7
42646 …27_I_ECC_EN_K2 (0x1<<7) // Enable ECC for m…
42647 …RS_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_EN_K2_SHIFT 7
42682 …_MEM027_I_ECC_PRTY_K2 (0x1<<7) // Set parity only …
42683 …RS_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_PRTY_K2_SHIFT 7
42707 …I_MEM_PRTY_K2 (0x1<<7) // This bit masks, …
42708 …RS_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2_SHIFT 7
42791 …ED_0_MEM027_I_ECC_CORRECT_K2 (0x1<<7) // Record if a corr…
42792 …RS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_CORRECT_K2_SHIFT 7
42803 … 0x1f0400UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42804 … 0x1f0404UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42805 … 0x1f0408UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42806 … 0x1f040cUL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42838 … 0x1f041cUL //Access:RW DataWidth:0x1 // Per-PF: If set, search re…
42839 … 0x1f0420UL //Access:RW DataWidth:0x1 // Per-PF: Enables VF_ID (if…
42840 … 0x1f0424UL //Access:RW DataWidth:0x1 // Per-PF: Enables load requ…
42842 … 0x1f042cUL //Access:RW DataWidth:0x11 // Per-PF: Max value for tem…
42843 … 0x1f0430UL //Access:RW DataWidth:0x11 // Per-PF: Max value for tem…
42844 … 0x1f0434UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow …
42845 … 0x1f0438UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow search for non-IP …
42846 … 0x1f043cUL //Access:RW DataWidth:0x1 // Per-PF: If this field is 1, Over-IPv4-prot…
42862 …ASK_ICMP_CODE (0x1<<7) // If this bit is 0…
42863 …RS_REG_OPENFLOW_SEARCH_KEY_MASK_ICMP_CODE_SHIFT 7
42888 … // Per-PF: Indicates whether to include the Inner VLAN in the search for each protocol. 0 - TC…
42889 … // Per-PF: Indicates whether to include the Outer TAG in the search for each protocol. 0 - TCP…
42890 …-PF: Indicates whether to include Tenant ID (if it exists) in the search for each encapsulation ty…
42891 …o be 0 if the ID matches the default value. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 …
42895 …nant ID used in the search request if Tenant ID exists in the encapsulated T-tag packet.. A zero i…
42899 …ccess:RW DataWidth:0x20 // If the Tenant ID exists in the encapsulated T-Tag packet and does n…
42900 …ataWidth:0x3 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. The T-tag bit of …
42905 …DataWidth:0x1 // MAC port arbitration guarantees fairness at byte-level (0) or packet-level (1).
42906 … DataWidth:0x1 // Main/LB arbitration guarantees fairness at byte-level (0) or packet-level (1).
42909 … 0x1f0510UL //Access:RW DataWidth:0x8 // Size of inter-packet gap and FCS us…
42910 …ority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 tr…
42911 …ority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 tr…
42912 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
42913 …bits are for priority 8 client. The clients are assigned the IDs corresponding to their TC # (0-8)
42914 …bits are for priority 8 client. The clients are assigned the IDs corresponding to their TC # (0-8)
42915 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
42916 … 0x1f052cUL //Access:RW DataWidth:0x1 // Enables pseudo-random round robin ar…
42919 …0x1f0538UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42922 …0x1f0544UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42925 …0x1f0550UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42928 …0x1f055cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42931 …0x1f0568UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42934 …0x1f0574UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42937 …0x1f0580UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42938 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 7 is allowed to reach.
42939 …idth:0x20 // Specify the weight (in bytes) to be added to credit register 7 when it is time to i…
42940 …R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter credit register 7.
42943 …0x1f0598UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42946 …0x1f05a4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42949 …0x1f05b0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42952 …0x1f05bcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42955 …0x1f05c8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42958 …0x1f05d4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42961 …0x1f05e0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42964 …0x1f05ecUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42967 …0x1f05f8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42970 …0x1f0604UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42973 …0x1f0610UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42976 …0x1f061cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42979 …0x1f0628UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42982 …0x1f0634UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42985 …0x1f0640UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42986 …r bound that the credit register is allowed to reach for main traffic on TC 7 during WFQ Main/Loop…
42987 …weight (in bytes) to be added to the credit register for main traffic on TC 7 when it is time to i…
42988 …Width:0x20 // Current upper 32 bits of the 33-bit value in the credit register for main traffic …
42989 …und that the credit register is allowed to reach for loopback traffic on TC 7 during WFQ Main/Loop…
42990 …ht (in bytes) to be added to the credit register for loopback traffic on TC 7 when it is time to i…
42991 …:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback tr…
42994 …0x1f0664UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42995 … 0x1f0700UL //Access:RW DataWidth:0x4 // Per-port: Size of the pro…
43007 …ataWidth:0x6 // Per-port: Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - V…
43010 … 0x1f073cUL //Access:RW DataWidth:0x10 // Per-PF: Base value used i…
43011 … 0x1f0740UL //Access:RW DataWidth:0x10 // Per-PF: Base value used i…
43026 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
43027 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
43028 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
43029 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
43030 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
43031 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
43032 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
43033 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
43034 … 0x1f079cUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43035 … 0x1f07a0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43036 … 0x1f07a4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43037 … 0x1f07a8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43038 … 0x1f07acUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43039 … 0x1f07b0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43040 … 0x1f07b4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43041 … 0x1f07b8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43046 … 0x1f07ccUL //Access:RW DataWidth:0x20 // Per-PF/Per-port: Destination …
43047 … 0x1f07d0UL //Access:RW DataWidth:0x10 // Per-PF/Per-port: Destination …
43048 … 0x1f07d4UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43049 … 0x1f07d8UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43050 … 0x1f07dcUL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43051 … 0x1f07e0UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43052 … 0x1f07e4UL //Access:RW DataWidth:0x2 // Per-PF: Destination IP address match value - …
43053 … 0x1f07e8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43054 … 0x1f07ecUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43055 … 0x1f07f0UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43056 … 0x1f07f4UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43057 … 0x1f07f8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43058 … 0x1f07fcUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43059 … 0x1f0800UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43060 … 0x1f0804UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43061 … 0x1f0808UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43062 … 0x1f080cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43063 … 0x1f0810UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43064 … 0x1f0814UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43065 … 0x1f0818UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43066 … 0x1f081cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43067 … 0x1f0820UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43068 … 0x1f0824UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43069 … 0x1f0828UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43070 … 0x1f082cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43071 … 0x1f0830UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43072 … 0x1f0834UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43073 … 0x1f0838UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43074 … 0x1f083cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43075 … 0x1f0840UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43076 … 0x1f0844UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43077 … 0x1f0848UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43078 … 0x1f084cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43079 … 0x1f0850UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43080 … 0x1f0854UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43081 … 0x1f0858UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43082 … 0x1f085cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43083 … 0x1f0860UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43084 … 0x1f0864UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43088 … 0x1f0874UL //Access:RW DataWidth:0x1 // Per-port: Flag enabling …
43089 … 0x1f0878UL //Access:RW DataWidth:0x1 // Per-port: Flag to compar…
43093 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43098 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43100 …ch in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg;…
43111 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43113 …ch in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg;…
43126 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43139 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43146 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43156 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43157 … 0x1f093cUL //Access:RW DataWidth:0x4 // Connection type for no-match packets.
43158 … 0x1f0940UL //Access:RW DataWidth:0x4 // Per-port: PFID for no-match packet…
43159 … 0x1f0944UL //Access:RW DataWidth:0x1 // Per-PF: If set, the PFID may be overridden for n…
43160 … 0x1f0948UL //Access:RW DataWidth:0x20 // Per-PF: CID for no-match packets.
43161 … 0x1f094cUL //Access:RW DataWidth:0x9 // Per-PF: LCID for no-match packets.
43169 … 0x1f096cUL //Access:RW DataWidth:0x1 // Per-PF: If set, and PF cl…
43170 …sulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN 2 - NGE
43171 …sulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN 2 - NGE
43172 …ulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN, 2 - NGE
43173 …-PF: Indicates whether to include Tenant ID (if it exists) in the MAC VLAN Cache entry for each en…
43174 …-VLAN Cache Flexible Field. If two blocks are used, this block is used for the upper bytes. 14:11…
43175 …the MAC-VLAN Cache Flexible Field. This block is only used if the number of bytes in mac_vlan_fle…
43178 … 0x1f09d0UL //Access:RW DataWidth:0x1 // Per-PF: If set, the SACK …
43179 …-FCoE packets. This allows Over-L2-Raw Part2 to be available on non-RoCE packets. The RoCE specifi…
43180 … 0x1f09d8UL //Access:RW DataWidth:0x20 // Per-PF: Mask used in RDMA…
43189 … 0x1f09fcUL //Access:RW DataWidth:0x1 // Per-PF: Enables SYN cooki…
43190 … 0x1f0a00UL //Access:RW DataWidth:0x1 // Per-PF: If set, enables i…
43191 …1 // Per-PF: If set, 4B for Ethernet CRC is included in Packet Length for Statistics field. For…
43192 …-PF: For each bit set, the length of the corresponding tag in the inner header will be subtracted …
43193 …-PF: For each bit set, the length of the corresponding tag in the first header will be subtracted …
43194 … 0x1f0a10UL //Access:RW DataWidth:0x1 // Per-Port: If set and clas…
43195 … 0x1f0a14UL //Access:RW DataWidth:0x8 // Per-Port: If classificati…
43196 … 0x1f0a18UL //Access:RW DataWidth:0x9 // Per-Port: If classificati…
43197 … 0x1f0a1cUL //Access:RW DataWidth:0x20 // Per-PF: This value is passed to the per-PF …
43198 … 0x1f0a20UL //Access:RW DataWidth:0x2 // Per-Port: This value goes…
43199 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 0. In …
43200 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 0. In 4…
43201 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 1. In …
43202 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 1. In 4…
43203 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 2. In …
43204 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 2. In 4…
43205 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 3. In …
43206 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 3. In 4…
43207 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 4. In …
43208 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 4. In 4…
43209 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 5. In …
43210 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 5. In 4…
43211 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 6. In …
43212 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 6. In 4…
43213 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 7. In …
43214 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 7. In 4…
43215 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 8. In 4…
43216 …0x1f0a68UL //Access:RW DataWidth:0x3 // bit 0 - ignore for VXLAN, bit 1 - ignore for NGE, bit…
43226 …UL //Access:RC DataWidth:0x18 // The number of processed packets for TC 7. Counts packets as …
43233 …-port): Packet available status of the main and loopback queues of each traffic class, before bein…
43234 …dth:0x18 // Debug only (per-port): STORM backpressure status (blocked priorities) Each set bit r…
43236 …ue of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Re…
43238 …f0b68UL //Access:R DataWidth:0xd // Debug only: In the case of a mini-cache LCID validation…
43266 …kts sent to TCM: Reserved - 127:66, Parsing and Error flags - 65:50, Start block - 49:37, Priority…
43303 … 0x1f0f8cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
43307 …-encasulated packet): 40.Source MAC 39.Destination MAC 38.VLAN (12b) ) � Tag 1 37.Provider VLAN (1…
43309 …-14 data 14-11 PF ID (3bit BB 4bit K2) 10-7 Tunnel type (4b) 0000-no tunnel 0001-vxlan 0010-GRE MA…
43324 …ld the priority field in the GFT used frame fields inner header 0- use CVLAN priority 1- use SVLAN…
43325 …d the priority field in the GFT used frame fields tunnel header 0- use CVLAN priority 1- use SVLAN…
43326 … 0x1f11bcUL //Access:RW DataWidth:0x1 // Per-PF: Enables gft searc…
43327 … 0x1f11c0UL //Access:RW DataWidth:0x1 // Per-PF: Enables gft search for non-IP pac…
43332 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43391 …// Context region for received Ethernet packet with a match and packet type 7. Used in CFC load re…
43392 …// Context region for received Ethernet packet with a match and packet type 7. Used in CFC load re…
43443 …:0x8 // Context region for pure acknowledge packets with connection type 7. Used in CFC load re…
43444 …:0x8 // Context region for pure acknowledge packets with connection type 7. Used in CFC load re…
43467 …Width:0x8 // The increment value to send in the CCFC load request message for connection type 7.
43468 …Width:0x8 // The increment value to send in the CCFC load request message for connection type 7.
43481 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43489 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43497 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43505 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43513 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43521 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43529 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43535 … (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 7
43537 …d connection type 7. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - …
43544 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43551 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43558 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43565 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43572 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43579 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43586 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43593 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43625 … // Ordered list of building blocks in TSTORM message for connection type 7. Unused blocks must …
43626 …20 // Ordered list of building blocks in PTLD message for connection type 7. Unused blocks must …
43627 … // Ordered list of building blocks in TSTORM message for connection type 7. Unused blocks must …
43628 …10 // Ordered list of building blocks in PTLD message for connection type 7. Unused blocks must …
43648 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43661 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43674 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43685 … 0x1f169cUL //Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on TCP 4 tuple. 0- p…
43686 … 0x1f16a0UL //Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on UDP 4 tuple. 0- p…
43706 …ataWidth:0x1 // Burst mode enabled. Set this bits to have the main round-robin arbiter stays o…
43713 …rom TX to RX. This loopback is on the line side after clock domain crossing - from the last TX pip…
43715 …om TX to RX. This loopback is on the core side before clock domain crossing - from the first TX pi…
43717 …om RX to TX. This loopback is on the line side before clock domain crossing - from the first RX pi…
43719 …rom RX to TX. This loopback is on the core side after clock domain crossing - from the last RX pip…
43723 …B_BB (0x1<<7) // Enables SOP; SOM…
43724 …MAC_REG_CTRL_XLGMII_ALIGN_ENB_BB_SHIFT 7
43729 … (0x1<<10) // Resets the RS layer functionality - fault handling.
43731 …ide the one column idle/sequence ordered set check before SOP in XGMII mode - effectively supporti…
43775 … (0x1<<1) // True to allow any non-Idle character to sta…
43779 …the MAC checks for IEEE Ethernet format premable - K.SOP + 5 '55' premable bytes + 'D5' SFD charac…
43783 …inimum receive packet size is reduced to 18 bytes from the default 33 bytes - Should be used in MA…
43805 …; the TX faults inputs are used to send out fault sequences - else receive faults are used -- used…
43815 …OW_CONTROL_TIMERS_ON_LINK_DOWN_BB (0x1<<7) // If set; the Rece…
43816 …MAC_REG_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_BB_SHIFT 7
43825 … (0x1<<0) // A rising edge on this register bit (0->1); clears the stick…
43827 … (0x1<<1) // A rising edge on this register bit (0->1); clears the stick…
43829 … (0x1<<2) // A rising edge on this register bit (0->1); clears the stick…
43832 …<<0) // This field is Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
43844 …use_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
43846 …use_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
43848 … (0xffff<<0) // Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
43850 …xffff<<16) // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
43853 … (0x1<<0) // Enable automatic re-send of PFC packet af…
43876 … (0x1<<3) // When set and llfc_in_ipg_only =0; GXPORT operates in cut-through mode.
43928 …TUS_BB (0x1<<7) // This bit indicat…
43929 …MAC_REG_FIFO_STATUS_LINK_STATUS_BB_SHIFT 7
43931 … (0x1<<0) // A rising edge on this register bit (0->1); clears the stick…
43933 … (0x1<<1) // A rising edge on this register bit (0->1); clears the stick…
43935 … (0x1<<2) // A rising edge on this register bit (0->1); clears the stick…
43937 … (0x1<<3) // A rising edge on this register bit (0->1); clears the stick…
43939 … (0x1<<4) // A rising edge on this register bit (0->1); clears the stick…
43941 … (0x1<<5) // A rising edge on this register bit (0->1); clears the stick…
43943 … (0x1<<6) // A rising edge on this register bit (0->1); clears the stick…
43985 … 0x210130UL //Access:RW DataWidth:0x10 // XMAC IP Version ID - corresponds to RTL/D…
44007 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44011 …PPEND_EN_0_K2_E5 (0x1<<7) // This bit control…
44012 …NIG_REG_NIG_PORT0_CONF_CRC_APPEND_EN_0_K2_E5_SHIFT 7
44019 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44021 …G with 4x10 SERDES) 5 : 4x20G (BB), NA (K2) 6 : 1x40G + 2x10G (BB), NA (K2) 7 : 1x40G + 2x20G (BB)…
44027 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44031 …PPEND_EN_1_K2_E5 (0x1<<7) // This bit control…
44032 …NIG_REG_NIG_PORT1_CONF_CRC_APPEND_EN_1_K2_E5_SHIFT 7
44039 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44047 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44051 …PPEND_EN_2_K2_E5 (0x1<<7) // This bit control…
44052 …NIG_REG_NIG_PORT2_CONF_CRC_APPEND_EN_2_K2_E5_SHIFT 7
44059 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44079 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44083 …PPEND_EN_3_K2_E5 (0x1<<7) // This bit control…
44084 …NIG_REG_NIG_PORT3_CONF_CRC_APPEND_EN_3_K2_E5_SHIFT 7
44091 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44101 …1<<0) // This regiseter enables loopback mode (used for debug) 0 - loopback inactive 1 - loopback …
44121 …RROR_VLAN_K2_E5 (0x1<<7) // Set to 1 for mas…
44122 …NIG_REG_NWM_ERROR_MASK_NWM_ERROR_VLAN_K2_E5_SHIFT 7
44262 … (0x1<<0) // If set overrides hardware control of the Traffic LED. The Traffic LED will then b…
44264 …_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LED_CONTROL_BLINK_TRAFFIC bit bit is also s…
44266 …th the LED_CONTROL_OVERRIDE_TRAFFIC bit and LED_CONTROL_TRAFFIC LED bit; the Traffic LED will blin…
44270 …eriod of each blink cycle (on + off) for Traffic LED in milliseconds. Must be a non-zero value. Th…
44274 …idth:0x4 // Led mode: 0 -> MAC; 1-3 -> PHY1; 4 -> MAC2; 5-7 -> PHY4; 8 -> MAC3;…
44275 …LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G […
44276 …LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G […
44277 …LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G […
44280 …LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G […
44283 … corresponding Physical function. 0 -> NW0 connects to PF0 1 -> NW0 connects to PF1 2 -> NW0 co…
44285 … corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connects to PF1 2 -> NW1 co…
44287 … corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1 2 -> NW2 co…
44289 … corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1 2 -> NW3 co…
44292 …0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6]…
44294 …0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6]…
44296 …0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6]…
44298 …0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6]…
44299 …0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6]…
44300 …0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6]…
44301 …0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6]…
44302 …0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6]…
44303 …h:0x1 // When set, PMIF block uses values in following registers to configure NIG - PM interface
44307 …G port is assigned to each PMEG Port. [1:0] -- PMEG Port 0 [3:2] -- PMEG Port 1 [5:4] -- PMEG Port…
44308 …G port is assigned to each PMFC Port. [1:0] -- PMFC Port 0 [3:2] -- PMFC Port 1 [5:4] -- PMFC Port…
44309 …e PMEG Port ID every cycle. Valid values are: 0 -- Only Port 0 is used 1 -- All Ports (0-3) are us…
44310 …e PMFC Port ID every cycle. Valid values are: 0 -- Only Port 0 is used 1 -- All Ports (0-3) are us…
44374 …ports 0,2 and should be used for 100G or 2x50G NW modes. Bit 0 - port0 CRC enable. Bit 1 - port2 C…
44375 …ports 0,2 and should be used for 100G or 2x50G NW modes. Bit 0 - port0 CRC enable. Bit 1 - port2 C…
44376 …pted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - por…
44377 …pted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - por…
44399 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44401 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44403 … (0x1<<7) // End of packet error on M-Storm …
44404 …RM_REG_INT_STS_MSTORM_EOP_ERR_BB_K2_SHIFT 7
44405 … (0x1<<8) // End of packet error on U-Storm command interfa…
44426 …RR_BB_K2 (0x1<<7) // This bit masks, …
44427 …RM_REG_INT_MASK_MSTORM_EOP_ERR_BB_K2_SHIFT 7
44445 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44447 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44449 … (0x1<<7) // End of packet error on M-Storm …
44450 …RM_REG_INT_STS_WR_MSTORM_EOP_ERR_BB_K2_SHIFT 7
44451 … (0x1<<8) // End of packet error on U-Storm command interfa…
44468 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44470 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44472 … (0x1<<7) // End of packet error on M-Storm …
44473 …RM_REG_INT_STS_CLR_MSTORM_EOP_ERR_BB_K2_SHIFT 7
44474 … (0x1<<8) // End of packet error on U-Storm command interfa…
44498 …I_MEM_PRTY_BB (0x1<<7) // This bit masks, …
44499 …RM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_SHIFT 7
44504 …I_MEM_PRTY_K2_E5 (0x1<<7) // This bit masks, …
44505 …RM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_E5_SHIFT 7
44669 …_REG_TAG_SZ_SIZE 7
44670 … 0x230420UL //Access:RW DataWidth:0x10 // Provides the value of the 16-bit pad that will be …
44673 … Initial credit to be used on the RDIF command interface for regular (non-pass-through) requests. …
44674 …on the RDIF command interface for pass-through requests. This value defines the maximum number of …
44678 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
44679 …th:0x9 // Defines the number of occupied entries required in the PXP read-response FIFO before …
44680 … DataWidth:0x20 // Statistics counter provides a count of the number of M-Storm comands that ha…
44681 … DataWidth:0x20 // Statistics counter provides a count of the number of U-Storm comands that ha…
44710 … 0x232000UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the M-Storm comma…
44712 … 0x232400UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the U-Storm comma…
44714 … 0x232800UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the BR…
44716 … 0x232c00UL //Access:R DataWidth:0x7 // Provides read-only access of the BR…
44718 … 0x233000UL //Access:WB_R DataWidth:0x2c // Provides read-only access of the ta…
44720 … 0x233400UL //Access:R DataWidth:0x11 // Provides read-only access of the pa…
44722 … 0x233600UL //Access:R DataWidth:0xb // Provides read-only access of the PB…
44724 … 0x233800UL //Access:WB_R DataWidth:0x100 // Provides read-only access of the PR…
44726 … 0x233c00UL //Access:R DataWidth:0x8 // Provides read-only access of the PXP write-done re…
44773 … 0x238480UL //Access:RW DataWidth:0x10 // Per-PF Bitmask for inclus…
44774 … 0x238484UL //Access:RW DataWidth:0x8 // Per-StringType Bitmask fo…
44794 …_T2 (0x1<<7) // Controls PXP Req…
44795 …RC_REG_PXP_CTRL_PXP_TPHVALID_T2_SHIFT 7
44830 …R (0x1<<7) // Input FIFO overf…
44831 …SS_REG_INT_STS_INP_FIFO_ERROR_SHIFT 7
44875 …OR (0x1<<7) // This bit masks, …
44876 …SS_REG_INT_MASK_INP_FIFO_ERROR_SHIFT 7
44920 …RROR (0x1<<7) // Input FIFO overf…
44921 …SS_REG_INT_STS_WR_INP_FIFO_ERROR_SHIFT 7
44965 …ERROR (0x1<<7) // Input FIFO overf…
44966 …SS_REG_INT_STS_CLR_INP_FIFO_ERROR_SHIFT 7
45074 …2 then bits 9:0 is addr to RSS KEY LSB table. If bits 12:10 are 3 then bits 7:0 is addr to RSS INF…
45076 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45077 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45078 …0x20 // Debug register. FIFO empty status: {b15:8 - inp_fifo_counter; b7:6- cmd_fifo_couter; b5:…
45079 …ster. State of each state machine {b15:12 - calc_cur_state; b11:8 - main_cur_state;b7:4 - msg_cur_…
45109 …_LOW_FIFO_FULL_E5 (0x1<<7) // The key_low fifo…
45110 …SS_REG_FIFO_FULL_STATUS1_KEY_LOW_FIFO_FULL_E5_SHIFT 7
45136 …Y_LOW_FIFO_EMPTY_E5 (0x1<<7) // The key_low fifo…
45137 …SS_REG_FIFO_EMPTY_STATUS1_KEY_LOW_FIFO_EMPTY_E5_SHIFT 7
45203 …H (0x1<<7) // TQ read underflo…
45204 …PB_REG_INT_STS_TQ_ERROR_RD_TH_SHIFT 7
45222 …TH (0x1<<7) // This bit masks, …
45223 …PB_REG_INT_MASK_TQ_ERROR_RD_TH_SHIFT 7
45241 …D_TH (0x1<<7) // TQ read underflo…
45242 …PB_REG_INT_STS_WR_TQ_ERROR_RD_TH_SHIFT 7
45260 …RD_TH (0x1<<7) // TQ read underflo…
45261 …PB_REG_INT_STS_CLR_TQ_ERROR_RD_TH_SHIFT 7
45282 …_SELECT (0xf<<7) // Obsolete.
45283 …PB_REG_CONTROL_DEBUG_SELECT_SHIFT 7
45324 … 0x23e000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
45331 …x4 // Page size in L2P table for CDU-Task module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-51…
45332 … // Page size in L2P table for CDU module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45333 …4 // Page size in L2P table for TM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45334 …4 // Page size in L2P table for QM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45335 … // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45336 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45337 … // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45338 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45339 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45346 … 0x240048UL //Access:RW DataWidth:0xe // First memory address base for cdu-connection in ILT.
45347 … 0x24004cUL //Access:RW DataWidth:0xe // Last memory address base for cdu-connection in ILT.
45348 … 0x240050UL //Access:RW DataWidth:0xe // First memory address base for cdu-task in ILT.
45349 … 0x240054UL //Access:RW DataWidth:0xe // Last memory address base for cdu-task in ILT.
45387 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45391 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45393 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45395 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45397 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45399 … (0x1<<7) // Indicates that o…
45400 …SWRQ2_REG_INT_STS_ELT_ADDR_SHIFT 7
45403 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45405 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45407 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45409 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45411 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45413 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45436 … (0x1<<7) // This bit masks, …
45437 …SWRQ2_REG_INT_MASK_ELT_ADDR_SHIFT 7
45461 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45465 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45467 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45469 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45471 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45473 …R (0x1<<7) // Indicates that o…
45474 …SWRQ2_REG_INT_STS_WR_ELT_ADDR_SHIFT 7
45477 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45479 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45481 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45483 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45485 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45487 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45498 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45502 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45504 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45506 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45508 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45510 …DR (0x1<<7) // Indicates that o…
45511 …SWRQ2_REG_INT_STS_CLR_ELT_ADDR_SHIFT 7
45514 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45516 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45518 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45520 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45522 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45524 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45559 …09_I_MEM_PRTY_BB (0x1<<7) // This bit masks, …
45560 …SWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_SHIFT 7
45569 …02_I_MEM_PRTY_K2 (0x1<<7) // This bit masks, …
45570 …SWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT 7
45577 …write to memory: pswrq.i_l2p_table.rf_ecc_error_connect Includes 2 words of 7 bits each. The msb o…
45578 …write to memory: pswrq.i_l2p_table.rf_ecc_error_connect Includes 2 words of 7 bits each. The msb o…
45596 … to memory: pswrq.i_l2p_table_high.rf_ecc_error_connect Includes 2 words of 7 bits each. The msb o…
45634 …W DataWidth:0x3 // Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010:…
45635 …RW DataWidth:0x3 // Max burst size filed for read requests port 0; 000 - 128B; 001:256B; 010:…
45638 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45639 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45653 …DataWidth:0x8 // Initial value of global counter; This value MUST be 256 - sum of all clients t…
45666 … 0x240470UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 7 in pswrq memory.
45698 … 0x2404f0UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 7.
46001 … 0x2406a0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ5 Read- currently not used.
46104 … (0xf<<0) // Indicates the number of credits for read sub-requests in th reques…
46106 … (0x1f<<4) // Indicates the number of credits for write sub-requests in th reques…
46111 … 0x240724UL //Access:RW DataWidth:0x5 // Sets which vq head pointer to see out of queues 0-31.
46112 … 0x240728UL //Access:RW DataWidth:0x5 // Sets which vq tail pointer to see out of queues 0-31.
46146 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46147 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46148 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46149 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46150 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46151 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46152 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46153 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46154 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46155 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46156 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46157 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46158 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46159 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46160 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46161 …- SR from the VQ can send ATC lookup request to the ATC (assuming all other conditions are met). W…
46162 …ss:RW DataWidth:0x2 // ATC enable values per PF as follows: b0 - PF enable; b1 - VF enable; P…
46163 …ues of rq_atc_internal_ats_enable as follows: b0 - PF0; b1 - VF0; b2 - PF1; b3 - VF1; b30 - PF15 ;…
46164 …lways sent to the GLUE with the at_valid=1 indication (see atc_code in PSWRQ-PGLUE interface for m…
46166 … 0x240800UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46167 … 0x240804UL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i…
46168 … 0x240808UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46169 … 0x24080cUL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i…
46170 … 0x240810UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46171 … // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ…
46175 …- assert ilt fail interrupt (rq_elt_addr) in case working in ilt mode and onchip translation fail …
46178 …FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 d…
46182 …0x20 // FOR DBG: bit 0 relaxed ordering; bit 1 no-snoop; bits 5:2 client id; bit 6 done type; bi…
46183 … 0x240844UL //Access:R DataWidth:0x20 // The total number of WR SR-s that were sent to t…
46184 … 0x240848UL //Access:R DataWidth:0x20 // The total number of RD SR-s that were sent to t…
46185 … 0x24084cUL //Access:R DataWidth:0x20 // The number of PBF RD SR-s that were sent to t…
46186 … 0x240850UL //Access:R DataWidth:0x20 // The number of USDM-DP WR SR-s that were sent …
46187 … 0x240854UL //Access:R DataWidth:0x20 // The number of TREQ SR-s that were sent to t…
46188 … 0x240858UL //Access:R DataWidth:0x20 // The number of ICPL SR-s that were sent to t…
46189 …20 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46190 …9 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46191 …20 // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46192 …c // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46193 …0x20 // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46194 …0xc // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46195 …:0x20 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46196 …:0x9 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46197 … // Counting window mode. 0 - manual window: counting is manually being initiated & stopped by t…
46200 …en working in manual window mode (i.e. Sr_cnt_window_mode = 0). 0 - stop counting. 1 - start count…
46202 …global window counter). 0 - start counting upon any first SR that is sent to the PGLUE. 1 - start …
46204 …l window counter (i.e. 0 is for 1 clk_pci cycle; 1 is for 2 clk_pci cycles; 7 is for 8 clk_pci cyc…
46205 …atus of the SR count mechanism: 0 - idle: ready to start new counting. 1 - ongoing: counting is cu…
46206 … 0x2408a0UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46207 … 0x2408a4UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46208 … 0x2408a8UL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46209 …dth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client …
46210 … 0x2408b0UL //Access:R DataWidth:0x9 // bit 8-0: srid.
46211 … 0x2408b4UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46212 … 0x2408b8UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46213 … 0x2408bcUL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46214 … DataWidth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15…
46215 … 0x2408c4UL //Access:R DataWidth:0xa // b1-0: atc code; b2: wdone type; b4-3: endianity; …
46243 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46244 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46245 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46246 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46247 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46258 …l2p_vf_err or rq_elt_addr interrupt. [12:0] - Length in bytes. [16:13] - PFID. [17] - VF_VALID. …
46259 …:16] client ID. [21] - Error type - 0 - rq_l2p_vf_err; 1 - rq_elt_addr. [22] - w_nr - 0 - read; 1 …
46261 …:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must be big…
46263 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46264 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46265 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46266 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46267 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46268 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46269 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46270 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46271 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46272 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46273 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46274 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46275 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46276 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46277 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46278 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46279 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46280 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46281 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46282 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46283 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46284 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46285 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46286 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46287 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46288 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46289 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46290 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46291 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46294 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46295 … 0x2409c4UL //Access:R DataWidth:0x9 // Debug only: The SR counter - number of unused sub…
46328 …0x240a48UL //Access:R DataWidth:0xa // Debug only: The blocks counter - number of unused blo…
46391 … 0x240b44UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46392 … 0x240b48UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46393 … 0x240b4cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46394 … 0x240b50UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46395 … 0x240b54UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46396 … 0x240b58UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46397 … 0x240b5cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46398 … 0x240b60UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46399 … 0x240b64UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46400 … 0x240b68UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46401 … 0x240b6cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46402 … 0x240b70UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46403 … 0x240b74UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46404 … 0x240b78UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46405 … 0x240b7cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46406 … 0x240b80UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46407 … 0x240b84UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46408 … 0x240b88UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46409 … 0x240b8cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46410 … 0x240b90UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46411 … 0x240b94UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46412 … 0x240b98UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46413 … 0x240b9cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46414 … 0x240ba0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46415 … 0x240ba4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46416 … 0x240ba8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46417 … 0x240bacUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46418 … 0x240bb0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46419 … 0x240bb4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46420 … 0x240bb8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46421 … 0x240bbcUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46422 … 0x240bc0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46430 … 0 - the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW count…
46431 …- the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters…
46432 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46433 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46434 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46435 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46436 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46437 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46438 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46439 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46440 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46441 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46442 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46443 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46444 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46445 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46446 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46447 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46448 …-PGLUE request interface write credit; 0 - no more credit for wr SR-s (i.e. write SR-s cannot be s…
46449 …-PGLUE request interface read credit; 0 - no more credit for rd SR-s (i.e. read SR-s cannot be sen…
46450 …can be a workaround for possible bugs in the byte counters. Id-s are based on wr client id-s (take…
46451 …-1] between qc_cmg_add_2_q (indication that new request is written into hoq0) and cmg_qc_del_head …
46452 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46453 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46454 … 0x240c40UL //Access:R DataWidth:0xe // For debug and Idle-check use. The value …
46456 …ite done for them from the PGLUE). Upon reaching the threshold no more wr SR-s will be sent by the…
46466 … 0x240c70UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 7
46491 …ID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is m…
46492 …ID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is m…
46493 …ID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is m…
46494 …ID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is m…
46495 …ID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is m…
46496 …ID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is m…
46497 …this VQ. Map M2P to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped to …
46513 … // Page size in L2P table for tgsrc module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
46514 … // Page size in L2P table for RGSRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
46552 …5 // Internal lookup table for logical to physical address translation. Re-instantiated in E4 du…
46581 …VERFLOW (0x1<<7) // Overflow in xsdm…
46582 …SWRQ_REG_INT_STS_XSDM_FIFO_OVERFLOW_SHIFT 7
46628 …OVERFLOW (0x1<<7) // This bit masks, …
46629 …SWRQ_REG_INT_MASK_XSDM_FIFO_OVERFLOW_SHIFT 7
46675 …O_OVERFLOW (0x1<<7) // Overflow in xsdm…
46676 …SWRQ_REG_INT_STS_WR_XSDM_FIFO_OVERFLOW_SHIFT 7
46722 …FO_OVERFLOW (0x1<<7) // Overflow in xsdm…
46723 …SWRQ_REG_INT_STS_CLR_XSDM_FIFO_OVERFLOW_SHIFT 7
46772 …- TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM; 5 - PSDM; 6 - QM; 7 - TM; 8 - SRC; 9 - DMAE; 10 - …
46773 …- TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM; 5 - PSDM; 6 - QM; 7 - TM; 8 - SRC; 9 - DMAE; 10 - …
46802 …VERFLOW (0x1<<7) // Overflow in tsdm…
46803 …SWWR_REG_INT_STS_TSDM_FIFO_OVERFLOW_SHIFT 7
46841 …OVERFLOW (0x1<<7) // This bit masks, …
46842 …SWWR_REG_INT_MASK_TSDM_FIFO_OVERFLOW_SHIFT 7
46880 …O_OVERFLOW (0x1<<7) // Overflow in tsdm…
46881 …SWWR_REG_INT_STS_WR_TSDM_FIFO_OVERFLOW_SHIFT 7
46919 …FO_OVERFLOW (0x1<<7) // Overflow in tsdm…
46920 …SWWR_REG_INT_STS_CLR_TSDM_FIFO_OVERFLOW_SHIFT 7
46948 …- client ID. [7:5] - (sum1[5:3] + 1) or (sum1[5:4] + 1) according to the definition in the spec. […
46956 …0x29b068UL //Access:RW DataWidth:0x7 // If Number of entries in the PRM-secondary internal fi…
46957 … 0x29b06cUL //Access:R DataWidth:0x7 // Current internal PRM-secondary fill level …
46958 … 0x29b070UL //Access:R DataWidth:0x7 // Maximum internal PRM-secondary fill level …
46974 …FLOW (0x1<<7) // Underflow in the…
46975 …SWWR2_REG_INT_STS_TSDM_UNDERFLOW_SHIFT 7
46996 … the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the…
47019 …RFLOW (0x1<<7) // This bit masks, …
47020 …SWWR2_REG_INT_MASK_TSDM_UNDERFLOW_SHIFT 7
47064 …DERFLOW (0x1<<7) // Underflow in the…
47065 …SWWR2_REG_INT_STS_WR_TSDM_UNDERFLOW_SHIFT 7
47086 … the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the…
47109 …NDERFLOW (0x1<<7) // Underflow in the…
47110 …SWWR2_REG_INT_STS_CLR_TSDM_UNDERFLOW_SHIFT 7
47131 … the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the…
47159 …18_I_MEM_PRTY_4_E5 (0x1<<7) // This bit masks, …
47160 …SWWR2_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_4_E5_SHIFT 7
47235 …14_I_MEM_PRTY_5_BB_K2 (0x1<<7) // This bit masks, …
47236 …SWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_5_BB_K2_SHIFT 7
47280 …21_I_MEM_PRTY_8_E5 (0x1<<7) // This bit masks, …
47281 …SWWR2_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_8_E5_SHIFT 7
47352 …09_I_MEM_PRTY_0_BB_K2 (0x1<<7) // This bit masks, …
47353 …SWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_0_BB_K2_SHIFT 7
47411 …12_I_MEM_PRTY_3_E5 (0x1<<7) // This bit masks, …
47412 …SWWR2_REG_PRTY_MASK_H_2_MEM012_I_MEM_PRTY_3_E5_SHIFT 7
47483 …10_I_MEM_PRTY_4_BB_K2 (0x1<<7) // This bit masks, …
47484 …SWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_4_BB_K2_SHIFT 7
47538 …05_I_MEM_PRTY_3_E5 (0x1<<7) // This bit masks, …
47539 …SWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_3_E5_SHIFT 7
47540 …05_I_MEM_PRTY_4_BB_K2 (0x1<<7) // This bit masks, …
47541 …SWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_4_BB_K2_SHIFT 7
47633 …15_I_MEM_PRTY_3_E5 (0x1<<7) // This bit masks, …
47634 …SWWR2_REG_PRTY_MASK_H_4_MEM015_I_MEM_PRTY_3_E5_SHIFT 7
47719 …ue is the one expected in idle check except for the Timers VQ (VQ3). This register is for VQs 0-23.
47725 …a. Arrowhead: The reset value of 1 should not be changed. It can cause Xs on the outputs - CQ79817.
47727 …-block until end of packet. Note that the override may start a few cycles before or after the last…
47729 …uest with error on receive side: [15:0] - Echo ID. [28:16] - sub-request length minus 1. [29] - fi…
47730 …ils of first request with error on receive side: [4:0] - VQ ID. [9:5] - client ID. [10] - valid - …
47737 …e is the one expected in idle check except for the Timers VQ (VQ3). This register is for VQs 24-31.
47764 …han this Number of entries are used in the clock synchronization FIFO; it de-asserts the 'almost f…
47766 …this Number of entries are used in the CDU clock synchronization FIFO; it de-asserts the 'almost f…
47768 …this Number of entries are used in the PBF clock synchronization FIFO; it de-asserts the 'almost f…
47770 …han this Number of entries are used in the clock synchronization FIFO; it de-asserts the 'almost f…
47771 …read clients: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 PBF (TDIF); 7 QM; 8 TM; 9 SRC; 10 …
47772 …d144UL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since reset in 16…
47773 …d148UL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since reset in 16…
47774 …d14cUL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since reset in 16…
47775 …d150UL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since reset in 16…
47779 …d160UL //Access:R DataWidth:0x8 // Per-client maximum sync FIFO fill level since reset in 16…
47844 …24_I_ECC_RF_INT_BB_K2 (0x1<<7) // This bit masks, …
47845 …SWRD2_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_BB_K2_SHIFT 7
47854 …27_I_ECC_RF_INT_E5 (0x1<<7) // This bit masks, …
47855 …SWRD2_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT_E5_SHIFT 7
47998 …EM024_I_ECC_EN_BB_K2 (0x1<<7) // Enable ECC for m…
47999 …SWRD2_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_EN_BB_K2_SHIFT 7
48008 …EM027_I_ECC_EN_E5 (0x1<<7) // Enable ECC for m…
48009 …SWRD2_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_EN_E5_SHIFT 7
48041 …Y_0_MEM024_I_ECC_PRTY_BB_K2 (0x1<<7) // Set parity only …
48042 …SWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_PRTY_BB_K2_SHIFT 7
48051 …Y_0_MEM027_I_ECC_PRTY_E5 (0x1<<7) // Set parity only …
48052 …SWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_PRTY_E5_SHIFT 7
48084 …ECTED_0_MEM024_I_ECC_CORRECT_BB_K2 (0x1<<7) // Record if a corr…
48085 …SWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_CORRECT_BB_K2_SHIFT 7
48094 …ECTED_0_MEM027_I_ECC_CORRECT_E5 (0x1<<7) // Record if a corr…
48095 …SWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_CORRECT_E5_SHIFT 7
48121 …:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must be big…
48124 … 0 - The delivery port continues delivering the next PBF request only if the second delivery port …
48212 …ter-engine indicating if the engine is idle. Idle means the engine is not sending request (and the…
48213 …- pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 P…
48214 … 0x2a0060UL //Access:R DataWidth:0x1 // 1 - An error request is …
48216 …- RSV [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM…
48217 …idth:0x7 // The data of the first incorrect access. the format is: [6:0] - length in DWs. The d…
48218 … 0x2a0070UL //Access:R DataWidth:0x1 // 1 - An incorrect access …
48220 … 0x2a0078UL //Access:R DataWidth:0x1 // 1- permission violation…
48221 …0x2a007cUL //Access:R DataWidth:0x11 // Log of the permission violation: {QID[8:0];VFID[7:0]}.
48225 …or source in internal write interface: [1:0] usdm; [3:2] xsdm; [5:4] msdm; [7:6] ysdm; [9:8] psdm;…
48226 … its allowed credits. the format is: [3:0] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSD…
48227 … 0x2a0094UL //Access:R DataWidth:0x1 // 1 - A source credit viol…
48231 …stination in internal write interface. [1:0] usdm; [3:2] xsdm; [5:4] msdm; [7:6] ysdm; [9:8] psdm;…
48233 … 0x2a00acUL //Access:R DataWidth:0x1 // 1 - PSWHST is in drain m…
48235 …- length in DWs; [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - cli…
48236 … 0x2a00b8UL //Access:R DataWidth:0x1 // 1 - An hst timeout data …
48238 …interface. PSWHST issues an attention if more credits are consumed. Added in BB-B0 due to pipeline.
48262 …M; 3 XSDM; 4 YSDM; 5 PSDM; 6 IGU; 7 CAU). Bit mask decoding: (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YS…
48279 …YNC_FIFO_ERR (0x1<<7) // An error in data…
48280 …SWHST_REG_INT_STS_HST_DATA_SYNC_FIFO_ERR_SHIFT 7
48291 … (0x1<<13) // An error in write source FIFO 7.
48316 …SYNC_FIFO_ERR (0x1<<7) // This bit masks, …
48317 …SWHST_REG_INT_MASK_HST_DATA_SYNC_FIFO_ERR_SHIFT 7
48353 …A_SYNC_FIFO_ERR (0x1<<7) // An error in data…
48354 …SWHST_REG_INT_STS_WR_HST_DATA_SYNC_FIFO_ERR_SHIFT 7
48365 … (0x1<<13) // An error in write source FIFO 7.
48390 …TA_SYNC_FIFO_ERR (0x1<<7) // An error in data…
48391 …SWHST_REG_INT_STS_CLR_HST_DATA_SYNC_FIFO_ERR_SHIFT 7
48402 … (0x1<<13) // An error in write source FIFO 7.
48430 …04_I_MEM_PRTY (0x1<<7) // This bit masks, …
48431 …SWHST_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT 7
48451 …und interrupts memory. E4 entry structure: [15:0] - CompParams. [23:16] - EventID. [24] - T. [28:2…
48453 … DataWidth:0x9 // Indirect access to the permission table. The fields are : {Valid; VFID[7:0]}.
48478 …IFO_OVERFLOW (0x1<<7) // Indicates an ove…
48479 …GLUE_B_REG_INT_STS_CSSNOOP_FIFO_OVERFLOW_SHIFT 7
48490 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48527 …FIFO_OVERFLOW (0x1<<7) // This bit masks, …
48528 …GLUE_B_REG_INT_MASK_CSSNOOP_FIFO_OVERFLOW_SHIFT 7
48576 …P_FIFO_OVERFLOW (0x1<<7) // Indicates an ove…
48577 …GLUE_B_REG_INT_STS_WR_CSSNOOP_FIFO_OVERFLOW_SHIFT 7
48588 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48625 …OP_FIFO_OVERFLOW (0x1<<7) // Indicates an ove…
48626 …GLUE_B_REG_INT_STS_CLR_CSSNOOP_FIFO_OVERFLOW_SHIFT 7
48637 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48681 …024_I_MEM_PRTY_K2_E5 (0x1<<7) // This bit masks, …
48682 …GLUE_B_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_E5_SHIFT 7
48701 …012_I_MEM_PRTY_BB (0x1<<7) // This bit masks, …
48702 …GLUE_B_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_SHIFT 7
48783 …- for Atomic Op / MRD handling of NPH credits. 0 - Can send both if there is one NPH credit and th…
48787 … (0x1<<0) // 0 - Debug bus is not output to RBCN_e0. 1 - …
48789 … (0x1<<1) // 0 - Debug bus is not output to RBCN_e1. 1 - …
48806 … (0x1<<9) // This bit give strict priority to read over write on the PGL read-write arbiter.
48809 …was blocked because of bus_master_en was deasserted. Bit 1: Added in BigBear-B0. Indicates that cu…
48810 …was blocked because of bus_master_en was deasserted. Bit 1: Added in BigBear-B0. Indicates that cu…
48820 …- Target memory read arrived with a correctable error. Bit 1 - Target memory read arrived with an …
48835 …UL //Access:RW DataWidth:0x1 // Debug only: 0 - PCIe checksum is generated towards PCIe core.…
48839 …:0x5 // Pseudo VF target mode configuration that controls the size of each pseudo-VF in the BAR.
48841 … to accesss DORQ via BAR0: 0-disable access; 1-enable access if BAR0 size is 128K; 2-enable acces…
48842 … 0x2a84ecUL //Access:RW DataWidth:0x9 // VSC fields: bit 0 - enable VSC; bits 1-8 - VSC reser…
48846 …DISABLE_INPUTS (0x1<<7) // Debug only: disa…
48847 …GLUE_B_REG_PGL_CONTROL0_PGL_DISABLE_INPUTS_SHIFT 7
48858 …-PF region. Addresses 0x0 - 0x5c: 12 per-PF PF windows. Each PF window contains two 32-bit values.…
48860 …region. 0x0 - 0x3c8 (0x200 - 0x5c8) - 243 global windows. Each entry is the 12-bit window offset.…
48862 …dress[12:7] in PCI configuration space of the first register on which config space A attention is …
48863 …_address generates an attention. If bit N is set - a CSSNOOP cycle with address {cfg_space_a_addre…
48864 …dress[12:7] in PCI configuration space of the first register on which config space B attention is …
48865 …_address generates an attention. If bit N is set - a CSSNOOP cycle with address {cfg_space_b_addre…
48867 …est register. Note: register contains bits from both paths. Note: Need to re-read the enabled regi…
48869 …est register. Note: register contains bits from both paths. Note: Need to re-read the enabled regi…
48891 …ABLED_REQUEST (0x1<<1) // Debug only: When 1 SR-IOV disbaled request …
48904 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48905 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48906 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48907 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48908 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48909 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48910 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48911 …PH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled event…
48912 …- Shadow bits clear for PFs 0 to 31. MCP writes 1 to a bit in this register in order to reset the…
48922 …th:0x10 // Shadow vf_enable register for all PFs. Each bit indicates if SR-IOV for the correspon…
48926 …- Reserved. Bit 1 - Reserved. Bit 2 - Reserved. Bit 3 - Reserved. Bit 4 - Completion with Configur…
48935 …ccess:R DataWidth:0x10 // Was_error indication dirty bits for PFs 0 to 7. Each bit indicates…
48944 …W DataWidth:0x10 // Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 to a …
48945 …- PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of …
48946 …- PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of …
48949 …ot submitted due to error. [4:0] VQID. [17:5] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. …
48950 …- Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indica…
48953 …QID. [5] TREQ. 1 - Indicates the request is a Translation Request. [18:6] - Length in bytes. [19] …
48954 …- Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indica…
48955 …- PFID. [11:4] - VFID. [12] - VF_VALID. [17:13] - ITAG Index. [21:18] - Error type - [18] - Indic…
48956 …68UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-VF for master and tar…
48957 …6cUL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for master transac…
48958 …70UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target write t…
48959 …74UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target read tr…
48968 …pfid_enable registers for target flow. Bits [15:0] - internal_pfid_enable_target_write; Bits [31:1…
48969 … global view of internal_pfid_enable registers for master flow. Bits [15:0] - internal_pfid_enable…
49000 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49001 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49002 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49003 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49004 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49005 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49006 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49007 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49008 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49009 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49010 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49011 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49012 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49013 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49014 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49015 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49016 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49017 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49018 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49019 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49020 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49021 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49022 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49023 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49024 … 0x2aa318UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49025 … 0x2aa31cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49026 … 0x2aa320UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49027 … 0x2aa324UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49028 … 0x2aa328UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49029 … 0x2aa32cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49030 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49031 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49032 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49033 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49034 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49035 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49036 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49037 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49038 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49039 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49040 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49041 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49042 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49043 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49044 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49045 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49046 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49047 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49048 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49049 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49050 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49051 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49052 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49053 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49054 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49055 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49056 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49057 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49058 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49059 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49060 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49061 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49062 …R0. [12:0] Address in DWs (bits [14:2] of byte address). [14:13] BAR. [22:15] VFID. [26:23] - PFID.
49063 …st with length violation (too many DWs) accessing BAR0. [5:0] - Length in DWs. [6] valid - indica…
49064 …ermission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. [23:16] VFID. [27:24] - PFID. [28…
49065 …- clears INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears TX_ERR_WR_ADD_31_0 T…
49067 … 0x2aa3c4UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates t…
49068 … 0x2aa3c8UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates t…
49069 … 0x2aa3ccUL //Access:RW DataWidth:0x1 // 1 - Do not discard IGU m…
49070 …- Accesses to the first 8KB of IGU in BAR0 (MSIX table and PBA) are not allowed. When this value i…
49071 …pletion is considered erroneous. [3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [17:13] - OTB EntryI…
49072 …- Unsupported Request or Completer Abort on User RX Interface. 1 - Reception of a poisoned TLP on …
49073 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49074 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49075 …- Enable the fix for CQ45220. If a Function receives a Translation Completion with a Translation S…
49076 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49077 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49094 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49096 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49098 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49100 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49102 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49104 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49106 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49108 … 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-s…
49110 …-only register reflects the value of the corresponding 'PF trusted' config bit on the external con…
49113 …. 1 - Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFI…
49114 …- PGLUE will submit the request with TPH info. PXP will take care of aligning it correctly when se…
49115 … address). [13:10] BE first. [17:14] BE last. [21:18] - PFID. [27:22] - Length in DWs. [28] valid …
49116 …- original PFID. [7:4] Pretend PFID. [15:8] Pretend VFID. [16] Pretend vf_valid. [20:17] Pretend r…
49118 …2aa560UL //Access:RW DataWidth:0x1 // 0 - Work with external BAR0 mechanism as defined in E4 …
49125 …57cUL //Access:RW DataWidth:0x1 // FID channel enable configuration per-VF. Controls Target …
49126 …led for that SDM. One bit per SDM. Bit 0 - TSDM. Bit 1 - MSDM. Bit 2 - USDM. Bit 3 - XSDM. Bit 4 -…
49127 …3 // Window size for VF to PF channel. 0 - NA; 1 - 8B; 2 - 16B; 3 - 32B; 4 - 64B; 5 - 128B; 6 -…
49130 … (0x1<<0) // Decision bit for PF master requests when BME is cleared: 0 - block; 1 - discard.
49132 …(0x1<<1) // Decision bit for PF master requests when fid_enable is cleared: 0 - block; 1 - discard.
49134 … (0x1<<2) // Decision bit for PF master requests when was_error is set: 0 - block; 1 - discard.
49136 … (0x1<<3) // Decision bit for VF master requests when BME is cleared: 0 - block; 1 - discard.
49138 …(0x1<<4) // Decision bit for VF master requests when fid_enable is cleared: 0 - block; 1 - discard.
49140 … (0x1<<5) // Decision bit for VF master requests when was_error is set: 0 - block; 1 - discard.
49143 … PF master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set att…
49145 …er requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set att…
49147 …F master requests when was_error is set: 0 - Always set (and log error details); 1 - never set att…
49149 … VF master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set att…
49151 …er requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set att…
49153 …F master requests when was_error is set: 0 - Always set (and log error details); 1 - never set att…
49162 … of '1' instructs PGLUE to use the client ID value in the 'tag' field of non-TPH master write pack…
49163 …RW DataWidth:0x1 // This field is an enable bit for 'detection of out-of-range requests' debu…
49165 … of ) the minimal legal address value. It is used in the 'detection of out-of-range requests' debu…
49167 … of ) the maximal legal address value. It is used in the 'detection of out-of-range requests' debu…
49171 …th illegal address. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49172 …- address was smaller than minimal_address_log; 1 - address was bigger than maximal_address_log. …
49175 …th TPH information. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49176 … [4:0] client ID. [6:5] PH. [14:7] Steering Tag. [15] - write_n_read: 0 - read; 1 - write. [16] -…
49177 …x1 // 0 - never pad write sub-requests with zeros. 1 - Pad write sub-requests with zeros and al…
49178 …/Access:RW DataWidth:0x3 // Cache line size for padding. 0 - 32B. 1 - 64B. 2 - 128B. 3 - 256B.
49179 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49180 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49181 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49182 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49183 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49184 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49185 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49186 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49196 …t error indication. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49197 …[15:0] Request ID. [20:16] client ID. [21] - write_n_read: 0 - read; 1 - write. [22] - last SR. […
49226 …x2aaef4UL //Access:R DataWidth:0xc // Error log for dllp abort bit8 to 11 pfid bit0 to 7 tag
49233 … 0x2aaf10UL //Access:R DataWidth:0x10 // pm_dstate 47-032
49235 … 0x2aaf60UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 31-0
49236 … 0x2aaf64UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 63 -32
49237 … 0x2aaf68UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 95 - 64
49238 … 0x2aaf6cUL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 127 - 96
49239 … 0x2aaf70UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 159-128
49243 … // Indicates there was an error in MCTP BIt 21-30 Message code Bit 7-22 Vender ID Bit 3-6 TAG…
49244 …dth:0x20 // Indicates there was an error in MCTP Bit 21-30 Length Bit 5-20 PCIE REQ ID Bit 0-4 …
49245 …x2aaf88UL //Access:R DataWidth:0xc // Error log for ecrc abort bit8 to 11 pfid bit0 to 7 tag
49246 …0x2aaf8cUL //Access:R DataWidth:0xc // Error log for tlp abort bit8 to 11 pfid bit0 to 7 tag
49247 … 0x2aaf90UL //Access:R DataWidth:0xc // Error log for poison bit8 to 11 pfid bit0 to 7 tag
49256 …0x2aafb4UL //Access:RW DataWidth:0x1 // 0 - Don't discard target request with unknown header …
49257 …cess:RW DataWidth:0x1 // 0 - Don't compare the function received in the completion to the ori…
49258 … 0x2aafbcUL //Access:RW DataWidth:0x1 // 0 - Enable b2b pop from sync fifos in pgl_pci_core_r…
49259 … 0x2aafc0UL //Access:RW DataWidth:0x1 // 0 - Don't discard master request during FLR 1 …
49260 … DataWidth:0x4 // 0 - TXCPL sync fifo push overflow 1 - TXR sync fifo push overflow 2 - TXW hea…
49261 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo pop underflow 1 - RX header syn…
49262 …x2aafccUL //Access:R DataWidth:0x12 // 8:0 - RX target read and config sync fifo pop status …
49263 … 0x2aafd0UL //Access:R DataWidth:0x1c // RX data sync fifo pop status (7 bit per each 128b in…
49273 …Width:0x1 // When set, the self init for the context memory is done. TBD - need to change to re…
49312 …O_FIFO_OV (0x1<<7) // CFC LOAD ECHO FI…
49313 …M_REG_INT_STS_0_CFC_LOAD_ECHO_FIFO_OV_SHIFT 7
49377 …HO_FIFO_OV (0x1<<7) // This bit masks, …
49378 …M_REG_INT_MASK_0_CFC_LOAD_ECHO_FIFO_OV_SHIFT 7
49442 …ECHO_FIFO_OV (0x1<<7) // CFC LOAD ECHO FI…
49443 …M_REG_INT_STS_WR_0_CFC_LOAD_ECHO_FIFO_OV_SHIFT 7
49507 …_ECHO_FIFO_OV (0x1<<7) // CFC LOAD ECHO FI…
49508 …M_REG_INT_STS_CLR_0_CFC_LOAD_ECHO_FIFO_OV_SHIFT 7
49562 … (0x1<<2) // Context Read with Last indication de-asserted.
49564 … (0x1<<3) // Context Write with Last indication de-asserted.
49572 …EOP_ERROR (0x1<<7) // PXP Read Data EO…
49573 …M_REG_INT_STS_1_PXP_RD_DATA_EOP_ERROR_SHIFT 7
49595 …_EOP_ERROR (0x1<<7) // This bit masks, …
49596 …M_REG_INT_MASK_1_PXP_RD_DATA_EOP_ERROR_SHIFT 7
49608 … (0x1<<2) // Context Read with Last indication de-asserted.
49610 … (0x1<<3) // Context Write with Last indication de-asserted.
49618 …TA_EOP_ERROR (0x1<<7) // PXP Read Data EO…
49619 …M_REG_INT_STS_WR_1_PXP_RD_DATA_EOP_ERROR_SHIFT 7
49631 … (0x1<<2) // Context Read with Last indication de-asserted.
49633 … (0x1<<3) // Context Write with Last indication de-asserted.
49641 …ATA_EOP_ERROR (0x1<<7) // PXP Read Data EO…
49642 …M_REG_INT_STS_CLR_1_PXP_RD_DATA_EOP_ERROR_SHIFT 7
49674 …_MEM_PRTY (0x1<<7) // This bit masks, …
49675 …M_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT 7
49770 …x2 // Number of timers per connection group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49771 …idth:0x2 // Number of timers per task group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49772 …- the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each gr…
49773 …- the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each gr…
49776 …lock in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49777 …lock in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49778 …ckss in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49779 …eld for writes; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49780 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49781 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49782 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49783 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49784 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49785 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49786 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49787 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49788 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49789 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49790 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49791 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49792 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49793 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49854 …o, Bit [6]: if = 1, the following error is enabled: RESERVED command, Bit [7]: if = 1, the follo…
49858 …the debug_0 registers. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved,…
49859 …tes that the debug_0 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49863 …- SET TIMER, 1 - CLEAR TIMER, 2 - STOP ALL TIMERS, 3 - INIT, 4 - FORCE CLEAR TIMER, 5 - reserved,…
49866 …s:R DataWidth:0x1 // The Leader Type field for the errored command: 0 - connection, 1 - task.
49867 …r the errored command. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved,…
49869 …ero, Bit [6]: if = 1, the following error happened: RESERVED command, Bit [7]: if = 1, the follo…
49870 …tes that the debug_1 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49872 …-0: LCID, Bit 9: scan type (0 - connection, 1 - task), Bits 12-10: type (3 LSbits), Bit 13: Load E…
49873 …tes that the debug_2 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49874 …last indication de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 10…
49875 …tes that the debug_3 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49876 …ion de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 11-10: Qward V…
49877 …-0: cmd_handler. Bit 3: reserved. Bits 7-4: writ…
49878 …tes that the debug_4 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49879 … Bits 8-0: function # (0-239 VFs, 240 and above PFs / segments) . Bit 9: type (0 - connecti…
49889 …- number of connections, the value should be multiplies of group_size_resolution_conn register (fo…
49893 …- number of tasks, the value should be multiplies of group_size_resolution_task register (for exam…
49897 …r connections, the last 512 rows contain the scan rate fields for tasks. TBD - describe the fields.
49908 … (0x1<<10) // When set link list ram will be initialized - all LCIDs will be lo…
49912 …TID Lock RAM to be initialized. This cannot be set during normal operation -- the block must be id…
49993 … it updates these fields. [31:28] -- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Request…
49994 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
49995 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
49996 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
50010 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50020 … (0xf<<10) // This register is not used in BB-B0. Reduced width to …
50048 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50049 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50050 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50078 …00UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a …
50079 …04UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a …
50080 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50081 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50086 … (0x1<<10) // This field is not used in BB-B0. When set, this co…
50112 …L //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if les…
50131 … //Access:RW DataWidth:0x9 // This is the LCID Threshold for LC CLient 7 (TSDM). When the num…
50167 …cast Bit[3] = RoCE Unicast Bit[4] = FCoE Bit[5] = OpenFlow Bit[6] = GFT Bit[7] = Reserved
50186 … 0x2d0a3cUL //Access:R DataWidth:0xa // {HIT;LCID}. HIT - if set then previous…
50187 …cess:RW DataWidth:0x1 // Added in E4B0. 0 - tid is not included in hash calculation (like in …
50188 …ess:RW DataWidth:0x1 // Added in E4B0. 0 - vlan is not included in hash calculation (like in …
50192 … 0x2d0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CI…
50196 … 0x2d0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the ST…
50207 … 0x2db000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
50224 … (0x1<<10) // When set link list ram will be initialized - all LCIDs will be lo…
50228 …TID Lock RAM to be initialized. This cannot be set during normal operation -- the block must be id…
50336 … it updates these fields. [31:28] -- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Request…
50337 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
50338 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
50339 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
50353 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50363 … (0xf<<10) // This register is not used in BB-B0. Reduced width to …
50391 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50392 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50393 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50421 …00UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a …
50422 …04UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a …
50423 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50424 …ar will cause a CFC execution error (weak_enable will override to force load-cancel) to a search o…
50429 … (0x1<<10) // This field is not used in BB-B0. When set, this co…
50455 …L //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if les…
50474 … //Access:RW DataWidth:0x9 // This is the LCID Threshold for LC CLient 7 (TSDM). When the num…
50510 …cast Bit[3] = RoCE Unicast Bit[4] = FCoE Bit[5] = OpenFlow Bit[6] = GFT Bit[7] = Reserved
50529 … 0x2e0a3cUL //Access:R DataWidth:0xa // {HIT;LCID}. HIT - if set then previous…
50530 …cess:RW DataWidth:0x1 // Added in E4B0. 0 - tid is not included in hash calculation (like in …
50531 …ess:RW DataWidth:0x1 // Added in E4B0. 0 - vlan is not included in hash calculation (like in …
50535 … 0x2e0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CI…
50539 … 0x2e0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the ST…
50550 … 0x2eb000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
50578 …RR (0x1<<7) // Increment overfl…
50579 …M_REG_INT_STS_BYTE_CRD_INC_ERR_SHIFT 7
50623 …ERR (0x1<<7) // This bit masks, …
50624 …M_REG_INT_MASK_BYTE_CRD_INC_ERR_SHIFT 7
50668 …C_ERR (0x1<<7) // Increment overfl…
50669 …M_REG_INT_STS_WR_BYTE_CRD_INC_ERR_SHIFT 7
50713 …NC_ERR (0x1<<7) // Increment overfl…
50714 …M_REG_INT_STS_CLR_BYTE_CRD_INC_ERR_SHIFT 7
50758 … (0x1<<7) // This bit masks, …
50759 …M_REG_PRTY_MASK_WRBUFF_SHIFT 7
50781 …_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
50782 …M_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5_SHIFT 7
50785 …_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, …
50786 …M_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_K2_SHIFT 7
50916 …_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
50917 …M_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_E5_SHIFT 7
50984 …_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, …
50985 …M_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_BB_K2_SHIFT 7
51031 …_MEM_PRTY_7_E5 (0x1<<7) // This bit masks, …
51032 …M_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_7_E5_SHIFT 7
51067 …_MEM_PRTY_10_K2 (0x1<<7) // This bit masks, …
51068 …M_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_10_K2_SHIFT 7
51087 …_MEM_PRTY_BB (0x1<<7) // This bit masks, …
51088 …M_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_BB_SHIFT 7
51180 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51181 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51182 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51183 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51184 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51185 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51186 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51187 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51188 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51189 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51190 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51191 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51192 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51193 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51194 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51195 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51196 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51197 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51198 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51199 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51200 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51201 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51202 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51203 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51204 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51205 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51206 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51207 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51208 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51209 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51210 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51211 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51212 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51213 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51214 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51215 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51216 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51217 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51218 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51219 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51220 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51221 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51222 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51223 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51224 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51225 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51226 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51227 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51228 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51229 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51230 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51231 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51232 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51233 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51234 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51235 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51236 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51237 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51238 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51239 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51240 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51241 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51242 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51243 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51244 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51245 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51246 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51254 …L //Access:WB DataWidth:0x36 // Pointer Table Memory for Other queues 63-0; The mapping is as …
51260 … 0x2f1010UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards…
51264 … 0x2f1030UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards…
51265 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51266 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51267 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51268 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51269 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51270 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51271 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51272 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51273 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51274 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51275 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51276 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51277 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51278 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51279 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51280 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51281 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51282 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51283 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51284 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51367 …-b0: rd first bank in page; b3: reserved (zero); b6-b4: wr first bank in page; b7: reserved (zero)…
51368 …al STU within the PXP (there is STU per PF). 0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
51369 …H field used in the PCI request. Per PF value. bits: 8-0 TPH Steering Tag Index; 12-9 reserved; 14…
51375 …- VOQs [0..31] VoqCrdLineFull_msb - VOQs [32..35] Some VOQs are "not used" depending on the…
51376 … to the matched Voq line credit (relevant only for VOQs that are being used - or in other words VO…
51377 …- VOQs [0..31]. VoqCrdByteFull_msb - VOQs [32..35]. Some VOQs are "not used" depending on t…
51378 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51379 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51380 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51381 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51382 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51383 …- VOQs [0..31]. AFullQmBypThrLineVoqMask_msb - VOQs [32..35]. Some VOQs are "not used" depe…
51388 …- resource is required to be more than the almost full threshold. 0 - resource value is do not car…
51391 …ost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_3
51392 …ost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_4
51395 …- resource is required to be more than the almost full threshold. 0 - resource value is do not car…
51398 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51399 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51400 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51401 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51402 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51403 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51404 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51405 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51406 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51407 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51408 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51409 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51410 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51411 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51412 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51413 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51414 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51415 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51416 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51417 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51418 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51419 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51420 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51421 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51422 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51423 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51424 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b01. NOTE: weight update is allowed only to queues w…
51425 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b11. NOTE: weight update is allowed only to queues w…
51436 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51437 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51438 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51439 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51440 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51441 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51442 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51443 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51444 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51445 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51446 …is masked. i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51447 …7-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM s…
51462 …0x2f2800UL //Access:R DataWidth:0x1 // The status of the Other PQ-s: bit0 - PQ paused. Shoul…
51466 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51467 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51468 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51469 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51470 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51471 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51472 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51473 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51474 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51475 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51476 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51477 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51478 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51479 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51480 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51481 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51482 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51483 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51484 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51485 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51486 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51487 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51488 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51489 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51490 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51491 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51492 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51493 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51494 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51495 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51496 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51497 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51498 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51499 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51500 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51501 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51502 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51503 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51504 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51505 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51506 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51507 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51508 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51509 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51510 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51511 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51512 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51513 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51514 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51515 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51516 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51517 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51518 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51519 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51520 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51521 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51522 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51523 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51524 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51525 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51526 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51527 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51528 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51529 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51530 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51531 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51532 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51533 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51534 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51535 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51536 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51537 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51538 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51539 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51540 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51541 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51542 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51543 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51544 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51545 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51550 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for selecting a line…
51551 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for enabling dwords …
51552 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for circular right s…
51553 … // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing valid.
51554 … // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing frame.
51555 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 lsb data that…
51556 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 msb data that…
51557 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 frame bits tha…
51558 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 valid bits tha…
51571 …ut period in 25Mhz clock cycles for the global. VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51572 …out period in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51573 … for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. Upon init should be set with value of …
51574 …od counter in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51575 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51576 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51577 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51578 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51579 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51580 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51581 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51582 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51585 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51587 …-init mode. In init mode should be written with the same value of RlGlblUpperBound. Sign: the msb …
51591 …x1 // when 1 - force cam search and update sts_rlglbl_pq_blocked vector even when the rlglblcrd…
51592 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51593 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51594 …o). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51595 …ector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlGlblCrd; b1 …
51596 …ataWidth:0x20 // The RL timeout period in 25Mhz clock cycles for the PF RL-s. NOTE: ck25 domain.…
51597 …:0x20 // The RL timeout period counter in 25Mhz clock cycles for the PF RL-s. Upon init should b…
51601 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51604 …-init mode. In init mode should be written with the same value of RlPfUpperBound. Sign: the msb is…
51608 …- VOQs [0..31]. RlPfVoqEnable_msb - VOQs [32..35]. Some VOQs are "not used" depending on th…
51609 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51610 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51611 …ero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51612 … vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlPfCrd; b1 …
51616 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51619 …- VOQ0..VOQ15. WfqPfCrd_msb - VOQ16..VOQ35. Should be read only access in non-init mode. In init m…
51624 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51625 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51626 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51627 …vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqPfCrd; b1 …
51629 …0x1 // when 1 - force cam search and update sts_wfqvp_pq_blocked vector even when the wfqvpcrd …
51630 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51631 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51632 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51633 …vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqVpCrd; b1 …
51634 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51635 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51636 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51637 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51638 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51639 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51640 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51641 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51642 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51643 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51644 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51645 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51646 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51647 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51648 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51649 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51650 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51651 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51652 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51653 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51654 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51655 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51656 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51657 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51659 …-idle state, trying to start new TX arbitration depends on the GO mode as follows: 0 - start new T…
51662 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51663 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51664 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51665 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51666 …when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqLineCrd; b1 - Err_…
51667 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51668 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51669 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51670 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51671 …when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqByteCrd; b1 - Err_…
51680 …mem in not initiazlied. There is mask bit per mem, the following are mems 31-0: b0: qm_mem_bigram_…
51681 …mem in not initiazlied. There is mask bit per mem, the following are mems 63-32: b32: qm_mem_cfc_l…
51682 …initialized with all zeroes. There is bit per mem, the following are mems 31-0: b0: qm_mem_bigram_…
51683 …initialized with all zeroes. There is bit per mem, the following are mems 63-32: b32: qm_mem_cfc_l…
51684 …ly being initialized. There is status bit per mem, the following are mems 31-0: b0: qm_mem_bigram_…
51685 …ly being initialized. There is status bit per mem, the following are mems 63-32: b32: qm_mem_cfc_l…
51689 … 0x2f5da8UL //Access:R DataWidth:0x16 // Provides read-only access to the BI…
51936 …th:0x4 // The status of the TX PQ-s: bit0 - PQ global VP/QCN RL block; bit1 - PQ active; bit2 -…
51939 …- PQ valid; bits 8:1 - RL id; bits 17:9 - VP id (value of all ones is reserved for pure-LB VOQ …
51945 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51948 …-init mode. In init mode should be written with the same value of WfqVpUpperBound. Sign: the msb i…
51951 …- Voq id; bit 9:6 - Pf id; Some VOQs are "not used" depending on the port_mode. Namely : port_m…
51954 …0UL //Access:WB DataWidth:0x36 // Pointer Table Memory for TX queues 447-0; The mapping is as …
51957 …-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb i…
51958 …-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb i…
51961 …7-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM s…
51962 …7-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM s…
51964 … // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mo…
51965 … // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mo…
51969 …it and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of …
51970 …it and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of …
51974 … // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mo…
51975 … // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mo…
51979 …0x18 // The init and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16.
51980 …it and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16. Some VOQs are …
51984 …- VOQs [0..31]. AFullQmBypThrLineVoqMask_msb (This one) - VOQs [32..35]. Some VOQs are "not used" …
51985 …F RL mechanism per VOQ. RlPfVoqEnable - VOQs [0..31]. RlPfVoqEnable_msb (This one) …
51986 …- VOQs [0..31]. VoqCrdLineFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51987 …- VOQs [0..31]. VoqCrdByteFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51989 …dth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
52004 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52005 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52007 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52008 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52010 … fwrd_guard ; [10] validate_ref ; [9] validate_app ; [8] validate_guard ; [7] reserved (formerly …
52013 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52014 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52016 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52017 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52019 … fwrd_guard ; [10] validate_ref ; [9] validate_app ; [8] validate_guard ; [7] reserved (formerly …
52021 … 0x3000ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52022 … 0x3000d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52023 …ork interface; [3] FWRD ref; [4] FWR app; [5] FWRD guard; [6] vlidate ref; [7] validate app; [8] v…
52042 …W_EOB (0x1<<7) // end of burst arr…
52043 …DIF_REG_INT_STS_PARTIAL_DIF_W_EOB_SHIFT 7
52061 …_W_EOB (0x1<<7) // This bit masks, …
52062 …DIF_REG_INT_MASK_PARTIAL_DIF_W_EOB_SHIFT 7
52080 …IF_W_EOB (0x1<<7) // end of burst arr…
52081 …DIF_REG_INT_STS_WR_PARTIAL_DIF_W_EOB_SHIFT 7
52099 …DIF_W_EOB (0x1<<7) // end of burst arr…
52100 …DIF_REG_INT_STS_CLR_PARTIAL_DIF_W_EOB_SHIFT 7
52106 …-7). Do not read from address[3:5]=i if debug_error_data_valid[i] isn't set. Bits [2:0] in the add…
52117 …-Initial reference tag Address offset-0 bits [31:0]; Field name-Application tag value Address offs…
52118 …- Has 8 QWORDs per task allocated (All are valid). In RDIF - Has 8 QWORDs per task allocated (QWOR…
52122 …dth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
52138 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52139 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52141 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52142 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52144 … fwrd_guard ; [10] validate_ref ; [9] validate_app ; [8] validate_guard ; [7] reserved (formerly …
52147 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52148 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52150 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52151 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52153 … fwrd_guard ; [10] validate_ref ; [9] validate_app ; [8] validate_guard ; [7] reserved (formerly …
52155 … 0x3100ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52156 … 0x3100d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52157 …ork interface; [3] FWRD ref; [4] FWR app; [5] FWRD guard; [6] vlidate ref; [7] validate app; [8] v…
52158 …- error type ([0] Write overflow. [1] Read overflow. [2] Read from DIX when DIX write pointer =< D…
52167 …Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol ID 7.
52192 …W_EOB (0x1<<7) // end of burst arr…
52193 …DIF_REG_INT_STS_PARTIAL_DIF_W_EOB_SHIFT 7
52211 …_W_EOB (0x1<<7) // This bit masks, …
52212 …DIF_REG_INT_MASK_PARTIAL_DIF_W_EOB_SHIFT 7
52230 …IF_W_EOB (0x1<<7) // end of burst arr…
52231 …DIF_REG_INT_STS_WR_PARTIAL_DIF_W_EOB_SHIFT 7
52249 …DIF_W_EOB (0x1<<7) // end of burst arr…
52250 …DIF_REG_INT_STS_CLR_PARTIAL_DIF_W_EOB_SHIFT 7
52271 …_I_MEM_PRTY (0x1<<7) // This bit masks, …
52272 …DIF_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT 7
52311 …-7). Do not read from address[3:5]=i if debug_error_data_valid[i] isn't set. Bits [2:0] in the add…
52322 …- Has 8 QWORDs per task allocated (All are valid). In RDIF - Has 8 QWORDs per task allocated (QWOR…
52373 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_…
52374 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_…
52389 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52447 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_…
52448 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_…
52463 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52473 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
52474 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
52491 …_ERROR (0x1<<7) // Read packet clie…
52492 …RB_REG_INT_STS_0_RC_PKT1_1ST_ERROR_SHIFT 7
52556 …T_ERROR (0x1<<7) // This bit masks, …
52557 …RB_REG_INT_MASK_0_RC_PKT1_1ST_ERROR_SHIFT 7
52621 …1ST_ERROR (0x1<<7) // Read packet clie…
52622 …RB_REG_INT_STS_WR_0_RC_PKT1_1ST_ERROR_SHIFT 7
52686 …_1ST_ERROR (0x1<<7) // Read packet clie…
52687 …RB_REG_INT_STS_CLR_0_RC_PKT1_1ST_ERROR_SHIFT 7
52747 …IFO_ERROR (0x1<<7) // Queue FIFO error…
52748 …RB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR_SHIFT 7
52808 …FIFO_ERROR (0x1<<7) // This bit masks, …
52809 …RB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR_SHIFT 7
52869 …E_FIFO_ERROR (0x1<<7) // Queue FIFO error…
52870 …RB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR_SHIFT 7
52930 …UE_FIFO_ERROR (0x1<<7) // Queue FIFO error…
52931 …RB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR_SHIFT 7
52995 …DSCR_FIFO_ERROR (0x1<<7) // Warning! Check t…
52996 …RB_REG_INT_STS_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT 7
53052 …_DSCR_FIFO_ERROR (0x1<<7) // This bit masks, …
53053 …RB_REG_INT_MASK_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT 7
53109 …ND_DSCR_FIFO_ERROR (0x1<<7) // Warning! Check t…
53110 …RB_REG_INT_STS_WR_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT 7
53166 …OND_DSCR_FIFO_ERROR (0x1<<7) // Warning! Check t…
53167 …RB_REG_INT_STS_CLR_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT 7
53221 …_FIFO_ERROR (0x1<<7) // Read packet clie…
53222 …RB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT 7
53284 …P_FIFO_ERROR (0x1<<7) // This bit masks, …
53285 …RB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT 7
53347 …RSP_FIFO_ERROR (0x1<<7) // Read packet clie…
53348 …RB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT 7
53410 …_RSP_FIFO_ERROR (0x1<<7) // Read packet clie…
53411 …RB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT 7
53475 …FIFO_ERROR (0x1<<7) // Link list arbite…
53476 …RB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR_SHIFT 7
53530 …_FIFO_ERROR (0x1<<7) // This bit masks, …
53531 …RB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR_SHIFT 7
53585 …LS_FIFO_ERROR (0x1<<7) // Link list arbite…
53586 …RB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT 7
53640 …RLS_FIFO_ERROR (0x1<<7) // Link list arbite…
53641 …RB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT 7
53701 …ction for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
53735 …ction for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
53752 …ction for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
53775 …FIFO_ERROR (0x1<<7) // Warning! Check t…
53776 …RB_REG_INT_STS_7_WC4_LL_REQ_FIFO_ERROR_SHIFT 7
53840 …_FIFO_ERROR (0x1<<7) // This bit masks, …
53841 …RB_REG_INT_MASK_7_WC4_LL_REQ_FIFO_ERROR_SHIFT 7
53905 …EQ_FIFO_ERROR (0x1<<7) // Warning! Check t…
53906 …RB_REG_INT_STS_WR_7_WC4_LL_REQ_FIFO_ERROR_SHIFT 7
53970 …REQ_FIFO_ERROR (0x1<<7) // Warning! Check t…
53971 …RB_REG_INT_STS_CLR_7_WC4_LL_REQ_FIFO_ERROR_SHIFT 7
54029 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
54031 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
54033 …(0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
54035 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer …
54036 …RB_REG_INT_STS_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT 7
54037 …) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
54039 …(0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
54041 …Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
54043 … Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
54045 …2) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
54047 …x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
54049 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
54051 … in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
54053 …available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
54070 …OINT_FIFO_ERROR (0x1<<7) // This bit masks, …
54071 …RB_REG_INT_MASK_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT 7
54099 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
54101 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
54103 …(0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
54105 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer …
54106 …RB_REG_INT_STS_WR_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT 7
54107 …) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
54109 …(0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
54111 …Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
54113 … Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
54115 …2) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
54117 …x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
54119 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
54121 … in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
54123 …available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
54134 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
54136 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
54138 …(0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
54140 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer …
54141 …RB_REG_INT_STS_CLR_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT 7
54142 …) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
54144 …(0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
54146 …Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
54148 … Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
54150 …2) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
54152 …x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
54154 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
54156 … in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
54158 …available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
54335 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 7
54369 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 7
54386 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 7
54414 …I_ECC_RF_INT (0x1<<7) // This bit masks, …
54415 …RB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_SHIFT 7
54539 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
54540 …RB_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_E5_SHIFT 7
54595 …I_MEM_PRTY_BB (0x1<<7) // This bit masks, …
54596 …RB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB_SHIFT 7
54639 …I_MEM_PRTY_K2 (0x1<<7) // This bit masks, …
54640 …RB_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_K2_SHIFT 7
54697 … (0x1<<7) // Enable ECC for memory ecc instance brb.BB_BANK_K…
54698 …RB_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_SHIFT 7
54749 … (0x1<<7) // Set parity only for memory ecc instance brb.BB_BANK…
54750 …RB_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_SHIFT 7
54801 … (0x1<<7) // Record if a correctable error occurred on memory ecc instance …
54802 …RB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_SHIFT 7
54839 …te up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[7].BB_BANK_BB_GEN_IF.i…
54848 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
54849 …04UL //Access:RW DataWidth:0xa // Number of valid bytes in header in 16-bytes resolution. Aft…
54857 …ngth error other way it will continue to work as usual.::s/STOP_LEN_ERR_RST/7/g in Reset Value::s/…
54858 … shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) R…
54920 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54921 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54922 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54923 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54924 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54925 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54926 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54927 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54928 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54929 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54930 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54931 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54932 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54933 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54934 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54935 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54936 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54937 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54938 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54939 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54940 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54941 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54942 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54943 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54944 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54945 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54946 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54947 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54948 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54949 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54950 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54951 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54952 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54953 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54954 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54955 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54956 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54957 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54958 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54959 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54960 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54961 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54962 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54963 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54964 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54965 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54966 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54967 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54968 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54969 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54970 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54971 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54972 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54973 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54974 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54975 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54976 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54977 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54978 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54979 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54980 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54981 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54982 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54983 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54984 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54985 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54986 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54987 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54988 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54989 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54990 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54991 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54992 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54993 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54994 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54995 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54996 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54997 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54998 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54999 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55000 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55001 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55002 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55003 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55004 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55005 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55006 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55007 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55008 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55009 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55010 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55011 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55012 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55013 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55014 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55015 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55016 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55017 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55018 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55019 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55020 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55021 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55022 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55023 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55024 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55025 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55026 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55027 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55033 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55034 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55035 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55036 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55037 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55038 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55039 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55040 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55041 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55042 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55043 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55044 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55045 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55046 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55047 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55048 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55049 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55050 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55051 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55052 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55053 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55054 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55055 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55056 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55057 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55058 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55059 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55060 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55061 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55062 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55063 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55065 …rted when number of allocated blocks in TC bigger lossless_threshold, if 0 - then full to that TC…
55070 …cycles.B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE_RST/1/g in Reset Value::s/NO_DEAD…
55072 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55074 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55076 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55078 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55080 …ty then selection between them is done with RR. Possible values are 1-3. Priority 7 is highest. ::…
55082 …n packet will be written without intra packet dead cycles .B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser…
55083 …riority mechanism is enabled for the corresponding client. B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser…
55084 …is is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
55085 …iority for EOP read client to BIG RAM arbiters. Possible values are 0-7. Priority 7 is highest::s/…
55086 …client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7…
55087 …h multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is high…
55116 …-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When…
55118 … (0xf<<10) // There is bit per each EOP read client interface: B0 - IF0, B1- IF1. When bit is…
55122 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
55125 …-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When…
55127 … (0xf<<10) // There is bit per each EOP read client interface: B0 - IF0, B1- IF1. When bit is…
55141 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55142 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55143 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55144 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55145 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55146 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55147 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55148 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55149 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55150 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55151 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55152 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55153 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55154 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55155 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55156 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55159 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55160 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55161 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55162 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55163 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55164 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55165 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55166 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55167 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55168 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55169 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55170 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55171 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55172 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55173 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55174 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55175 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55176 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
55182 … // Debug register. FIFO counters status of link list arbiter: {rls_fifo[7:4]; prefetch_fifo_1[…
55291 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
55294 …ister for each erad packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelli…
55296 …ister for each read packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelli…
55298 …-port per-TC counters. In BigBear, entries 0-7 are port 0 (main 0) TCs 0-7. Entries 8-16 are port …
55301 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55303 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55305 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55307 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55309 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55311 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55313 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55315 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55330 …Access:RW DataWidth:0xe // Link list dual port memory that contains per-block descriptor::s/B…
55331 …Access:RW DataWidth:0xf // Link list dual port memory that contains per-block descriptor::s/B…
55338 …16 slots of 256 bytes;5=16/32 slots of 128 bytes;6=32/64 slots of 64 bytes; 7=64/128 slots of 32 b…
55367 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
55368 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
55370 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55371 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55372 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55373 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55374 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55375 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55376 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55377 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55378 …0x4c00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55379 …0x4c00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55380 …0x4c00bcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55381 …0x4c00c0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55383 …:0x8 // Logging register for segment message error: bits 3:0 - header len; bits 7:4 - number of…
55384 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 31:0 of the seg…
55385 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 63:32 of the se…
55386 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 95:64 of the se…
55387 …4c00d8UL //Access:W DataWidth:0x1 // Writing to this register clears seg msg logging registe…
55392 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55393 …g register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current len…
55401 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55403 … (0x1<<3) // Mini cache error - meaning that A load …
55405 … (0x1<<4) // Mini cache error - meaning that A load …
55427 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55429 … (0x1<<3) // Mini cache error - meaning that A load …
55431 … (0x1<<4) // Mini cache error - meaning that A load …
55440 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55442 … (0x1<<3) // Mini cache error - meaning that A load …
55444 … (0x1<<4) // Mini cache error - meaning that A load …
55461 …_I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, …
55462 …YLD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT 7
55465 …_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
55466 …YLD_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5_SHIFT 7
55521 … 0x4c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55523 … 0x4c0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55530 … (0x1<<2) // defines that only back-to-back aggregation is …
55549 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
55551 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
55553 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
55555 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
55558 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
55560 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
55562 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
55564 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
55567 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
55569 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
55571 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
55573 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
55576 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
55578 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
55580 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
55582 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
55618 … 0x4c0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55619 … 0x4c0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55620 … 0x4c092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55621 … 0x4c0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55622 … 0x4c0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55623 … 0x4c0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55624 … 0x4c093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55625 … 0x4c0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55626 … 0x4c0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55627 … 0x4c0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55628 … 0x4c094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55629 … 0x4c0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55630 … 0x4c0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55631 … 0x4c0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55632 … 0x4c095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55633 … 0x4c0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55634 … 0x4c0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55635 … 0x4c0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55636 … 0x4c096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55637 … 0x4c0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55638 … 0x4c0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55639 … 0x4c0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55640 … 0x4c097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55641 … 0x4c0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55642 … 0x4c0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55643 … 0x4c0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55644 … 0x4c098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55645 … 0x4c0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55646 … 0x4c0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55647 … 0x4c0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55648 … 0x4c099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55649 … 0x4c09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55651 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
55653 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
55655 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
55657 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
55660 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
55662 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
55664 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
55666 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
55669 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
55671 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
55673 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
55675 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
55678 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
55680 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
55682 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
55684 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
55723 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
55725 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
55727 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
55729 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
55731 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
55733 … (0x1f<<9) // offset of the flow-ID, in 32b units, fro…
55735 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
55737 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
55758 … (0xff<<0) // The value by which to increment the event-ID in case of success…
55760 … (0xff<<8) // The value by which to increment the event-ID in case of success…
55762 … (0xff<<16) // The value by which to increment the event-ID in case of success…
55764 … (0xff<<24) // The value by which to increment the event-ID in case of success…
55813 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
55814 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
55816 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55817 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55818 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55819 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55820 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55821 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55822 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55823 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55824 …0x4c8098UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55825 …0x4c809cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55826 …0x4c80a0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55827 …0x4c80a4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55832 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55833 …g register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current len…
55841 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55843 … (0x1<<3) // Mini cache error - meaning that A load …
55845 … (0x1<<4) // Mini cache error - meaning that A load …
55867 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55869 … (0x1<<3) // Mini cache error - meaning that A load …
55871 … (0x1<<4) // Mini cache error - meaning that A load …
55880 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55882 … (0x1<<3) // Mini cache error - meaning that A load …
55884 … (0x1<<4) // Mini cache error - meaning that A load …
55902 … 0x4c8400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55904 … 0x4c8800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55925 …the BRB read response buffer. The slot size would be the BRB-response-buffer-size/number-of-slots.…
55928 …ata returning from the BRB is swapped. meaning that bytes 0-3 is swapped with bytes 4-7 in e…
55929 …30UL //Access:RW DataWidth:0x3 // Max credit number for the BRB request-resonse interface::/M…
55949 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
55950 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
55952 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55953 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55954 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55955 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55956 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55957 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55958 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55959 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55960 …0x4d00acUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55961 …0x4d00b0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55962 …0x4d00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55963 …0x4d00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55968 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55969 …g register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current len…
55977 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55979 … (0x1<<3) // Mini cache error - meaning that A load …
55981 … (0x1<<4) // Mini cache error - meaning that A load …
56003 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56005 … (0x1<<3) // Mini cache error - meaning that A load …
56007 … (0x1<<4) // Mini cache error - meaning that A load …
56016 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56018 … (0x1<<3) // Mini cache error - meaning that A load …
56020 … (0x1<<4) // Mini cache error - meaning that A load …
56041 …_I_MEM_PRTY (0x1<<7) // This bit masks, …
56042 …MLD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT 7
56083 … 0x4d0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56085 … 0x4d0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56092 … (0x1<<2) // defines that only back-to-back aggregation is …
56111 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
56113 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
56115 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
56117 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
56120 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
56122 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
56124 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
56126 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
56129 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
56131 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
56133 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
56135 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
56138 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
56140 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
56142 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
56144 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
56180 … 0x4d0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56181 … 0x4d0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56182 … 0x4d092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56183 … 0x4d0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56184 … 0x4d0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56185 … 0x4d0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56186 … 0x4d093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56187 … 0x4d0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56188 … 0x4d0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56189 … 0x4d0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56190 … 0x4d094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56191 … 0x4d0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56192 … 0x4d0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56193 … 0x4d0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56194 … 0x4d095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56195 … 0x4d0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56196 … 0x4d0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56197 … 0x4d0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56198 … 0x4d096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56199 … 0x4d0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56200 … 0x4d0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56201 … 0x4d0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56202 … 0x4d097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56203 … 0x4d0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56204 … 0x4d0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56205 … 0x4d0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56206 … 0x4d098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56207 … 0x4d0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56208 … 0x4d0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56209 … 0x4d0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56210 … 0x4d099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56211 … 0x4d09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56213 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
56215 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
56217 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
56219 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
56222 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
56224 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
56226 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
56228 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
56231 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
56233 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
56235 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
56237 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
56240 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
56242 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
56244 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
56246 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
56285 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
56287 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
56289 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
56291 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
56293 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
56295 … (0x1f<<9) // offset of the flow-ID, in 32b units, fro…
56297 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
56299 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
56320 … (0xff<<0) // The value by which to increment the event-ID in case of success…
56322 … (0xff<<8) // The value by which to increment the event-ID in case of success…
56324 … (0xff<<16) // The value by which to increment the event-ID in case of success…
56326 … (0xff<<24) // The value by which to increment the event-ID in case of success…
56353 … 0x4e0014UL //Access:RW DataWidth:0x4 // Log 2 of the BD size in bytes - 2:BD size is 4bytes;…
56355 …0x4e001cUL //Access:RW DataWidth:0x4 // Log 2 of the SGE size in bytes - 2:SGE size is 4bytes…
56359 …16 slots of 256 bytes;5=16/32 slots of 128 bytes;6=32/64 slots of 64 bytes; 7=64/128 slots of 32 b…
56389 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
56390 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
56392 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56393 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56394 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56395 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56396 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56397 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56398 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56399 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56400 …0x4e00d0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56401 …0x4e00d4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56402 …0x4e00d8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56403 …0x4e00dcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56408 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
56409 …g register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current len…
56417 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56419 … (0x1<<3) // Mini cache error - meaning that A load …
56421 … (0x1<<4) // Mini cache error - meaning that A load …
56443 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56445 … (0x1<<3) // Mini cache error - meaning that A load …
56447 … (0x1<<4) // Mini cache error - meaning that A load …
56456 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56458 … (0x1<<3) // Mini cache error - meaning that A load …
56460 … (0x1<<4) // Mini cache error - meaning that A load …
56479 …_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
56480 …ULD_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5_SHIFT 7
56493 …_I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, …
56494 …ULD_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT 7
56557 … 0x4e0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56559 … 0x4e0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56561 … 0x4e0c00UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue2 - Debug access::/TMLD_…
56563 … 0x4e1000UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue3 - Debug access::/TMLD_…
56570 … (0x1<<2) // defines that only back-to-back aggregation is …
56589 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
56591 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
56593 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
56595 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
56598 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
56600 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
56602 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
56604 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
56607 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
56609 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
56611 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
56613 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
56616 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
56618 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
56620 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
56622 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
56658 … 0x4e1424UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56659 … 0x4e1428UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56660 … 0x4e142cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56661 … 0x4e1430UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56662 … 0x4e1434UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56663 … 0x4e1438UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56664 … 0x4e143cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56665 … 0x4e1440UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56666 … 0x4e1444UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56667 … 0x4e1448UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56668 … 0x4e144cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56669 … 0x4e1450UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56670 … 0x4e1454UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56671 … 0x4e1458UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56672 … 0x4e145cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56673 … 0x4e1460UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56674 … 0x4e1464UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56675 … 0x4e1468UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56676 … 0x4e146cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56677 … 0x4e1470UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56678 … 0x4e1474UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56679 … 0x4e1478UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56680 … 0x4e147cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56681 … 0x4e1480UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56682 … 0x4e1484UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56683 … 0x4e1488UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56684 … 0x4e148cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56685 … 0x4e1490UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56686 … 0x4e1494UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56687 … 0x4e1498UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56688 … 0x4e149cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56689 … 0x4e14a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56691 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
56693 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
56695 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
56697 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
56700 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
56702 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
56704 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
56706 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
56709 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
56711 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
56713 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
56715 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
56718 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
56720 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
56722 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
56724 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
56763 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
56765 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
56767 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
56769 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
56771 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
56773 … (0x1f<<9) // offset of the flow-ID, in 32b units, fro…
56775 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
56777 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
56798 … (0xff<<0) // The value by which to increment the event-ID in case of success…
56800 … (0xff<<8) // The value by which to increment the event-ID in case of success…
56802 … (0xff<<16) // The value by which to increment the event-ID in case of success…
56804 … (0xff<<24) // The value by which to increment the event-ID in case of success…
56819 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
56823 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
56844 …FO_ERROR_WR (0x1<<7) // FIFO error in MS…
56845 …IG_REG_INT_STS_0_MSDM_SYNCFIFO_ERROR_WR_SHIFT 7
56873 …IFO_ERROR_WR (0x1<<7) // This bit masks, …
56874 …IG_REG_INT_MASK_0_MSDM_SYNCFIFO_ERROR_WR_SHIFT 7
56902 …CFIFO_ERROR_WR (0x1<<7) // FIFO error in MS…
56903 …IG_REG_INT_STS_WR_0_MSDM_SYNCFIFO_ERROR_WR_SHIFT 7
56931 …NCFIFO_ERROR_WR (0x1<<7) // FIFO error in MS…
56932 …IG_REG_INT_STS_CLR_0_MSDM_SYNCFIFO_ERROR_WR_SHIFT 7
56960 …ROR (0x1<<7) // Error in the TX …
56961 …IG_REG_INT_STS_1_TX_SOPQ7_ERROR_SHIFT 7
57025 …RROR (0x1<<7) // This bit masks, …
57026 …IG_REG_INT_MASK_1_TX_SOPQ7_ERROR_SHIFT 7
57090 …_ERROR (0x1<<7) // Error in the TX …
57091 …IG_REG_INT_STS_WR_1_TX_SOPQ7_ERROR_SHIFT 7
57155 …7_ERROR (0x1<<7) // Error in the TX …
57156 …IG_REG_INT_STS_CLR_1_TX_SOPQ7_ERROR_SHIFT 7
57206 … (0x1<<0) // Error in the pure-loopback SOPQ.
57220 …FIFO_ERROR (0x1<<7) // Error in LLH Dat…
57221 …IG_REG_INT_STS_2_P0_RX_LLH_DFIFO_ERROR_SHIFT 7
57265 …DFIFO_ERROR (0x1<<7) // This bit masks, …
57266 …IG_REG_INT_MASK_2_P0_RX_LLH_DFIFO_ERROR_SHIFT 7
57296 … (0x1<<0) // Error in the pure-loopback SOPQ.
57310 …H_DFIFO_ERROR (0x1<<7) // Error in LLH Dat…
57311 …IG_REG_INT_STS_WR_2_P0_RX_LLH_DFIFO_ERROR_SHIFT 7
57341 … (0x1<<0) // Error in the pure-loopback SOPQ.
57355 …LH_DFIFO_ERROR (0x1<<7) // Error in LLH Dat…
57356 …IG_REG_INT_STS_CLR_2_P0_RX_LLH_DFIFO_ERROR_SHIFT 7
57400 …E_TOO_LONG_INT (0x1<<7) // Triggered by TC …
57401 …IG_REG_INT_STS_3_P0_TC6_PAUSE_TOO_LONG_INT_SHIFT 7
57437 …SE_TOO_LONG_INT (0x1<<7) // This bit masks, …
57438 …IG_REG_INT_MASK_3_P0_TC6_PAUSE_TOO_LONG_INT_SHIFT 7
57474 …AUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC …
57475 …IG_REG_INT_STS_WR_3_P0_TC6_PAUSE_TOO_LONG_INT_SHIFT 7
57511 …PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC …
57512 …IG_REG_INT_STS_CLR_3_P0_TC6_PAUSE_TOO_LONG_INT_SHIFT 7
57534 … (0x1<<0) // Error in the pure-loopback SOPQ.
57548 …FIFO_ERROR (0x1<<7) // Error in LLH Dat…
57549 …IG_REG_INT_STS_4_P1_RX_LLH_DFIFO_ERROR_SHIFT 7
57593 …DFIFO_ERROR (0x1<<7) // This bit masks, …
57594 …IG_REG_INT_MASK_4_P1_RX_LLH_DFIFO_ERROR_SHIFT 7
57624 … (0x1<<0) // Error in the pure-loopback SOPQ.
57638 …H_DFIFO_ERROR (0x1<<7) // Error in LLH Dat…
57639 …IG_REG_INT_STS_WR_4_P1_RX_LLH_DFIFO_ERROR_SHIFT 7
57669 … (0x1<<0) // Error in the pure-loopback SOPQ.
57683 …LH_DFIFO_ERROR (0x1<<7) // Error in LLH Dat…
57684 …IG_REG_INT_STS_CLR_4_P1_RX_LLH_DFIFO_ERROR_SHIFT 7
57728 …E_TOO_LONG_INT (0x1<<7) // Triggered by TC …
57729 …IG_REG_INT_STS_5_P1_TC6_PAUSE_TOO_LONG_INT_SHIFT 7
57765 …SE_TOO_LONG_INT (0x1<<7) // This bit masks, …
57766 …IG_REG_INT_MASK_5_P1_TC6_PAUSE_TOO_LONG_INT_SHIFT 7
57802 …AUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC …
57803 …IG_REG_INT_STS_WR_5_P1_TC6_PAUSE_TOO_LONG_INT_SHIFT 7
57839 …PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC …
57840 …IG_REG_INT_STS_CLR_5_P1_TC6_PAUSE_TOO_LONG_INT_SHIFT 7
57862 … (0x1<<0) // Error in the pure-loopback SOPQ.
57876 …FIFO_ERROR_K2_E5 (0x1<<7) // Error in LLH Dat…
57877 …IG_REG_INT_STS_6_P2_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT 7
57921 …DFIFO_ERROR_K2_E5 (0x1<<7) // This bit masks, …
57922 …IG_REG_INT_MASK_6_P2_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT 7
57952 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
57966 …H_DFIFO_ERROR_K2_E5 (0x1<<7) // Error in LLH Dat…
57967 …IG_REG_INT_STS_WR_6_P2_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT 7
57997 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58011 …LH_DFIFO_ERROR_K2_E5 (0x1<<7) // Error in LLH Dat…
58012 …IG_REG_INT_STS_CLR_6_P2_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT 7
58056 …E_TOO_LONG_INT_K2_E5 (0x1<<7) // Triggered by TC …
58057 …IG_REG_INT_STS_7_P2_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 7
58093 …SE_TOO_LONG_INT_K2_E5 (0x1<<7) // This bit masks, …
58094 …IG_REG_INT_MASK_7_P2_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 7
58130 …AUSE_TOO_LONG_INT_K2_E5 (0x1<<7) // Triggered by TC …
58131 …IG_REG_INT_STS_WR_7_P2_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 7
58167 …PAUSE_TOO_LONG_INT_K2_E5 (0x1<<7) // Triggered by TC …
58168 …IG_REG_INT_STS_CLR_7_P2_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 7
58190 … (0x1<<0) // Error in the pure-loopback SOPQ.
58204 …FIFO_ERROR_K2_E5 (0x1<<7) // Error in LLH Dat…
58205 …IG_REG_INT_STS_8_P3_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT 7
58249 …DFIFO_ERROR_K2_E5 (0x1<<7) // This bit masks, …
58250 …IG_REG_INT_MASK_8_P3_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT 7
58280 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58294 …H_DFIFO_ERROR_K2_E5 (0x1<<7) // Error in LLH Dat…
58295 …IG_REG_INT_STS_WR_8_P3_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT 7
58325 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58339 …LH_DFIFO_ERROR_K2_E5 (0x1<<7) // Error in LLH Dat…
58340 …IG_REG_INT_STS_CLR_8_P3_RX_LLH_DFIFO_ERROR_K2_E5_SHIFT 7
58384 …E_TOO_LONG_INT_K2_E5 (0x1<<7) // Triggered by TC …
58385 …IG_REG_INT_STS_9_P3_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 7
58421 …SE_TOO_LONG_INT_K2_E5 (0x1<<7) // This bit masks, …
58422 …IG_REG_INT_MASK_9_P3_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 7
58458 …AUSE_TOO_LONG_INT_K2_E5 (0x1<<7) // Triggered by TC …
58459 …IG_REG_INT_STS_WR_9_P3_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 7
58495 …PAUSE_TOO_LONG_INT_K2_E5 (0x1<<7) // Triggered by TC …
58496 …IG_REG_INT_STS_CLR_9_P3_TC6_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 7
58536 …ERROR_E5 (0x1<<7) // Error in the TX …
58537 …IG_REG_INT_STS_10_TX_SOPQ23_ERROR_E5_SHIFT 7
58569 …_ERROR_E5 (0x1<<7) // This bit masks, …
58570 …IG_REG_INT_MASK_10_TX_SOPQ23_ERROR_E5_SHIFT 7
58602 …23_ERROR_E5 (0x1<<7) // Error in the TX …
58603 …IG_REG_INT_STS_WR_10_TX_SOPQ23_ERROR_E5_SHIFT 7
58635 …Q23_ERROR_E5 (0x1<<7) // Error in the TX …
58636 …IG_REG_INT_STS_CLR_10_TX_SOPQ23_ERROR_E5_SHIFT 7
58670 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
58671 …IG_REG_PRTY_MASK_H_0_MEM087_I_MEM_PRTY_E5_SHIFT 7
58778 …I_MEM_PRTY_K2 (0x1<<7) // This bit masks, …
58779 …IG_REG_PRTY_MASK_H_0_MEM074_I_MEM_PRTY_K2_SHIFT 7
58802 …I_MEM_PRTY_BB (0x1<<7) // This bit masks, …
58803 …IG_REG_PRTY_MASK_H_0_MEM091_I_MEM_PRTY_BB_SHIFT 7
58867 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
58868 …IG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_E5_SHIFT 7
58869 …I_MEM_PRTY_K2 (0x1<<7) // This bit masks, …
58870 …IG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_K2_SHIFT 7
58989 …I_MEM_PRTY_BB (0x1<<7) // This bit masks, …
58990 …IG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_BB_SHIFT 7
59058 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
59059 …IG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_E5_SHIFT 7
59112 …I_MEM_PRTY_K2 (0x1<<7) // This bit masks, …
59113 …IG_REG_PRTY_MASK_H_2_MEM019_I_MEM_PRTY_K2_SHIFT 7
59196 …I_MEM_PRTY_BB (0x1<<7) // This bit masks, …
59197 …IG_REG_PRTY_MASK_H_2_MEM047_I_MEM_PRTY_BB_SHIFT 7
59235 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
59236 …IG_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_E5_SHIFT 7
59287 …I_MEM_PRTY_K2 (0x1<<7) // This bit masks, …
59288 …IG_REG_PRTY_MASK_H_3_MEM080_I_MEM_PRTY_K2_SHIFT 7
59303 …I_MEM_PRTY_BB (0x1<<7) // This bit masks, …
59304 …IG_REG_PRTY_MASK_H_3_MEM020_I_MEM_PRTY_BB_SHIFT 7
59324 …0x1 // Close-gate function disable bit: 0 - egress drain mode is enabled when close-gate input…
59331 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid …
59332 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid …
59333 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid …
59334 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid …
59335 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid …
59336 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid …
59338 …RX packets. 0 is for XSTORM; 1 is for YSTORM. This configuration should be static during run-time.
59339 …get the current credit count on the interface. This configuration should be static during run-time.
59343 … (0x1<<8) // T-bit to be used in CM …
59349 …0x1 // Global configuration for selecting whether to drop the per-PF drop and per-VPORT drop pa…
59350 … 0x500848UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59351 … 0x50084cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59352 … 0x500850UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59353 … 0x500854UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59354 … 0x500858UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59355 … 0x50085cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59356 … 0x500860UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59357 … 0x500864UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59358 … 0x500868UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59359 … 0x50086cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59360 … 0x500870UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59361 … 0x500874UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59362 … 0x500878UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59363 … 0x50087cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59364 … 0x500880UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59365 … 0x500884UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59366 … 0x500888UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59367 … 0x50088cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59368 … 0x500890UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59369 … 0x500894UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59370 … 0x500898UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59371 … 0x50089cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59372 … 0x5008a0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59373 … 0x5008a4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59374 … 0x5008a8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59375 … 0x5008acUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59376 … 0x5008b0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59377 … 0x5008b4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59378 … 0x5008b8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59379 … 0x5008bcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59380 … 0x5008c0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59381 … 0x5008c4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59382 … 0x5008c8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59383 … 0x5008ccUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59384 … 0x5008d0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59385 … 0x5008d4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59386 … 0x5008d8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59387 … 0x5008dcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59388 … 0x5008e0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59389 … 0x5008e4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59390 … 0x5008e8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59391 … 0x5008ecUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59392 … 0x5008f0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59393 … 0x5008f4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59394 … 0x5008f8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59395 … 0x5008fcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59396 … 0x500900UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59397 … 0x500904UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59398 … 0x500908UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59399 … 0x50090cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59400 … 0x500910UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59401 … 0x500914UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59402 … 0x500918UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59403 … 0x50091cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59404 … 0x500920UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59405 … 0x500924UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59406 … 0x500928UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59407 … 0x50092cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59408 … 0x500930UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59409 … 0x500934UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59410 … 0x500938UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59411 … 0x50093cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59412 … 0x500940UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59413 … 0x500944UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59414 … 0x500948UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59415 … 0x50094cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59416 … 0x500950UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59417 … 0x500954UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59418 … 0x500958UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59419 … 0x50095cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59420 … 0x500960UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59421 … 0x500964UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59422 … 0x500968UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59423 … 0x50096cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59424 … 0x500970UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59425 … 0x500974UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59426 … 0x500978UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59427 … 0x50097cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59428 … 0x500980UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59429 … 0x500984UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59430 … 0x500988UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59431 … 0x50098cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59432 … 0x500990UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59433 … 0x500994UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59434 … 0x500998UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59435 … 0x50099cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59436 … 0x5009a0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59437 … 0x5009a4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59438 … 0x5009a8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59439 … 0x5009acUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59440 … 0x5009b0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59441 … 0x5009b4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59442 … 0x5009b8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59443 … 0x5009bcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59444 … 0x5009c0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59445 … 0x5009c4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59446 … 0x5009c8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59447 … 0x5009ccUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59448 … 0x5009d0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59449 … 0x5009d4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59450 … 0x5009d8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59451 … 0x5009dcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59452 … 0x5009e0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59453 … 0x5009e4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59454 … 0x5009e8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59455 … 0x5009ecUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59456 … 0x5009f0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59457 … 0x5009f4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59458 … 0x5009f8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59459 … 0x5009fcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59460 … 0x500a00UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59461 … 0x500a04UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59462 … 0x500a08UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59463 … 0x500a0cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59464 … 0x500a10UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59465 … 0x500a14UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59466 … 0x500a18UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59467 … 0x500a1cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59468 … 0x500a20UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59469 … 0x500a24UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59470 … 0x500a28UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59471 … 0x500a2cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59472 … 0x500a30UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59473 … 0x500a34UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59474 … 0x500a38UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59475 … 0x500a3cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59476 … 0x500a40UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59477 … 0x500a44UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59478 … 0x500a48UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59479 … 0x500a4cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59480 … 0x500a50UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59481 … 0x500a54UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59482 … 0x500a58UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59483 … 0x500a5cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59484 … 0x500a60UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59485 … 0x500a64UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59486 … 0x500a68UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59487 … 0x500a6cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59488 … 0x500a70UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59489 … 0x500a74UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59490 … 0x500a78UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59491 … 0x500a7cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59492 … 0x500a80UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59493 … 0x500a84UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59494 … 0x500a88UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59495 … 0x500a8cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59496 … 0x500a90UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59497 … 0x500a94UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59498 … 0x500a98UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59499 … 0x500a9cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59500 … 0x500aa0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59501 … 0x500aa4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59502 … 0x500aa8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59503 … 0x500aacUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59504 … 0x500ab0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59505 … 0x500ab4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59506 … 0x500ab8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59507 … 0x500abcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59508 … 0x500ac0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59509 … 0x500ac4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59510 … 0x500ac8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59511 … 0x500accUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59512 … 0x500ad0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59513 … 0x500ad4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59514 … 0x500ad8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59515 … 0x500adcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59516 … 0x500ae0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59517 … 0x500ae4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59518 … 0x500ae8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59519 … 0x500aecUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59520 … 0x500af0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59521 … 0x500af4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59522 … 0x500af8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59523 … 0x500afcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59524 … 0x500b00UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59525 … 0x500b04UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59526 … 0x500b08UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59527 … 0x500b0cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59528 … 0x500b10UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59529 … 0x500b14UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59530 … 0x500b18UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59531 … 0x500b1cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59532 … 0x500b20UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59533 … 0x500b24UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59534 … 0x500b28UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59535 … 0x500b2cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59536 … 0x500b30UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59537 … 0x500b34UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59538 … 0x500b38UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59539 … 0x500b3cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59540 … 0x500b40UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59541 … 0x500b44UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59542 … 0x500b48UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59543 … 0x500b4cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59544 … 0x500b50UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59545 … 0x500b54UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59546 … 0x500b58UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59547 … 0x500b5cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59548 … 0x500b60UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59549 … 0x500b64UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59550 … 0x500b68UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59551 … 0x500b6cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59552 … 0x500b70UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59553 … 0x500b74UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59554 … 0x500b78UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59555 … 0x500b7cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59556 … 0x500b80UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59557 … 0x500b84UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
59558 … 0x500c00UL //Access:RW DataWidth:0x1 // Per-PF drop configuration…
59561 …0cUL //Access:R DataWidth:0x18 // TX SOP descriptor queue empty status - for main traffic que…
59562 …c10UL //Access:R DataWidth:0x18 // TX SOP descriptor queue full status - for main traffic que…
59563 … DataWidth:0x40 // Addresses for TimeSync related registers in the timesync generator sub-module.
59567 …1 // Output enable for the STORM interface. This configuration should be static during run-time.
59580 …00UL //Access:RW DataWidth:0x4 // Size of the proprietary header, in 32-bit words, that is pr…
59586 …-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer tag);…
59587 … 0x50101cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59588 … 0x501020UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59589 … 0x501024UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59590 … 0x501028UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59591 … 0x50102cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59592 … 0x501030UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59593 … 0x501034UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59594 …-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer tag);…
59595 … 0x50103cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59596 … 0x501040UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59597 … 0x501044UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59598 … 0x501048UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59599 … 0x50104cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59600 … 0x501050UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59601 … 0x501054UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59603 … (0x1<<0) // Enable bit for Ethernet-over-GRE (L2 GRE) encaps…
59605 … (0x1<<1) // Enable bit for IP-over-GRE (IP GRE) encaps…
59612 … 0x501068UL //Access:RW DataWidth:0x10 // FCOE Ethertype - default is 0x8906.
59617 … 0x50107cUL //Access:RW DataWidth:0x8 // IPv4 protocol field for ICMPv4 - defaults to 0x01.
59618 … 0x501080UL //Access:RW DataWidth:0x8 // IPv6 next header field for ICMPv6 - defaults to 0x3A.
59651 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_0: 0 - IPv6; 1-IPv4.
59652 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_1: 0 - IPv6; 1-IPv4.
59653 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_2: 0 - IPv6; 1-IPv4.
59675 …MAC2 (0x1<<7) // Mask bit for for…
59676 …IG_REG_RX_LLH_NCSI_MCP_MASK_MAC2_SHIFT 7
59761 … for forwarding packets for each PF to MCP in multifunction mode. This is a per-PF split register.
59777 …D_MASK_MAC2 (0x1<<7) // Mask bit for not…
59778 …IG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC2_SHIFT 7
59863 … forwarding packets for the PF to the host in multifunction mode. This is a per-PF split register.
59889 …ss of all 1's for comparison. A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-…
60009 …ess of all 1's for comparison. A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-…
60127 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60147 …- message FIFO empty. Bit 1 - descriptor FIFO empty. Bit 2 - message FIFO has more than 32 entries…
60148 …-to-send data remaining below which ETS arbiter for the LB path should start selecting the next pa…
60150 … 0x501508UL //Access:RW DataWidth:0x1 // Zero-padding enable for LB…
60156 … DataWidth:0x20 // Increment PERIOD for the BRB interface rate limiter - in term of 25MHz clo…
60157 …W DataWidth:0x20 // Increment VALUE for the BRB interface rate limiter - in term of bytes, cy…
60158 … DataWidth:0x20 // Upper bound VALUE for the BRB interface rate limiter - in term of bytes, cy…
60161 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60163 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60166 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60168 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60171 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60173 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60176 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60178 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60181 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60183 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60186 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60188 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60191 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60193 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60196 … (0x1<<0) // Enable bit for the per-TC rate limiter to be…
60198 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60200 …40UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60201 …44UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60202 …48UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60203 …4cUL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60204 …50UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60205 …54UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60206 …58UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60207 …5cUL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60208 …560UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60209 …564UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60210 …568UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60211 …56cUL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60212 …570UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60213 …574UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60214 …578UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60215 …57cUL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60216 …0UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60217 …4UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60218 …8UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60219 …cUL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60220 …0UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60221 …4UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60222 …8UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60223 …cUL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60232 …lient): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6…
60233 …lient): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6…
60234 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60235 …g IDs: 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6…
60237 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
60239 … 0x5015e0UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbitration mo…
60247 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 7 is allowed to reach.
60257 …idth:0x20 // Specify the weight (in bytes) to be added to credit register 7 when it is time to i…
60260 …0x501634UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60261 …0x501638UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60262 …0x50163cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60263 …0x501640UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60264 …0x501644UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60265 …0x501648UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60266 …0x50164cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60267 …R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter credit register 7.
60268 …0x501654UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60269 …0x501658UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60272 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60293 … 0x501910UL //Access:RW DataWidth:0x1 // Enable for SW-specified packet time…
60297 …-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 0xFF0*:0:0:0:0:0:0:181. …
60298 …-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP …
60299 …-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 0xFF0*:0:0:0:0:0:0:181. …
60300 …-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP …
60301 …s:RW DataWidth:0x11 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60302 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60303 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60304 …s:RW DataWidth:0x11 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60305 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60306 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60307 …s:RW DataWidth:0x13 // Packet TimeSync information that is buffered in 1-deep FIFOs for TX sid…
60308 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
60309 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
60310 …-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp val…
60311 …-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp val…
60313 …ased on tag/VLAN/MAC matching. 2: classification based on protocol. 3: dual-stage classification.…
60314 …-stage classification mode; value of 0: AND the hit vectors; value of 1: OR the hit vectors; value…
60315 …Default per-port value to be used when protocol-based classification fails. This is the per-port …
60316 …lt per-port value to be used when outer-tag/inner VLAN/MAC classification fails. This is the per…
60317 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60318 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60319 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60320 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60321 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60322 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60323 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60324 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60325 …-bit field immediately following the Ethertype to be used for each of the outer tag value bit. The…
60326 … specify the indexes for bits 7:4 of the outer tag value[15:0]. Bits [23:18] of this register spe…
60330 …-port per-PF register. This register selects the classification type for the tag/VLAN/MAC mode. …
60331 … 0x5019b0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60333 … 0x5019c0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60335 … 0x5019d0UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. Per-function…
60337 … 0x5019e0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60338 …er-port per-PF register. Per-function MAC addresses to be matched with for MAC-address-based clas…
60340 … 0x501a80UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60342 …-port per-PF register. Per-function mode select bit to indicate whether the filter is to be used …
60344 …7 // This is a per-port per-PF register. Per-function select bits for the different protocol t…
60346 … 0x501b40UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60348 …e. 0 selects connection-based classification. 1 selects the PF-based classification. This regist…
60349 …-tuple search for TCP packets. Set this bit to use the TCP 4-tuple (TCP source and destination po…
60350 …-tuple search for UDP packets. Set this bit to use the UDP 4-tuple (UDP source and destination po…
60351 …ed to hash the data string in connection-based engine classification. This register is used only …
60352 …-entry Engine ID lookup table, with 1 bit per entry. Set the bit to 1 to have packets associated …
60354 …ts one of the 24-bit destination QP bits to be used as the engine ID. Valid values are 0-23. Thi…
60355 …-global-PF engine ID to be used in PF-based engine classification. Set the bit to 1 to have packe…
60356 …ss:RW DataWidth:0x3 // Flow control mode. 0 - disable; 1 - PFC; 2 - LLFC; 3 - PPP; 4 - PAUSE…
60357 …-bit configurations for specifying which TC (0-15 for future expansion) each priorty is to be mapp…
60359 …ting the packet priority information. Valid values are 2-5 for selecting one of the L2 tags 2-5. …
60361 …(0xf<<3) // Bit offset in the outer tag starting from which to extract the 3-bit packet priority i…
60363 … (0xf<<7) // Bit offset in the selected tag starting from which to…
60364 …IG_REG_PKT_PRIORITY_TAG_N_BITOFFSET_SHIFT 7
60365 …-TC full signals. This register may change during run time. Packet truncation/discarding affects…
60367 … 0x501bb4UL //Access:RW DataWidth:0x8 // Per-TC flow control enabl…
60368 … 0x501bb8UL //Access:RW DataWidth:0x8 // Per-TC flow control enabl…
60369 … 0x501bbcUL //Access:RW DataWidth:0x9 // Per-TC flow control enabl…
60370 …DataWidth:0x1 // Enable bit for the no-drop-hdr-ind field of the LB-only-header. When set, the…
60371 …-drop of LB packets with the no-drop-hdr-ind bit set due to per-TC full backpressure from the BRB.…
60372 …cifies the number of 256-bit cycles, starting from the SOP cycle, of the packet not to be dropped …
60373 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60374 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60375 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60376 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60377 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60378 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60379 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60380 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60381 … 0x501becUL //Access:RW DataWidth:0x10 // Bit-map indicating which …
60382 … 0x501bf0UL //Access:RW DataWidth:0x10 // Bit-map indicating which …
60383 … 0x501bf4UL //Access:RW DataWidth:0x10 // Bit-map indicating which …
60384 … 0x501bf8UL //Access:RW DataWidth:0x10 // Bit-map indicating which …
60385 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60386 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60387 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60388 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60393 …ain mode starts immediately upon assertion and stops at the next packet boundary upon de-assertion.
60394 …rts immediately upon assertion and stops at the next packet boundary upon de-assertion. Note that…
60395 …7 is for TC7 flow. When enabled -- draining of the corrresponding TC starts immediately - packet…
60396 …hen enabled -- draining of the corrresponding TC starts immediately - packet data are dropped and…
60436 … // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statist…
60454 …dropped due to buffer full. This is an RF generated RC statistics register - reading this registe…
60455 …uncated due to buffer full. This is an RF generated RC statistics register - reading this registe…
60497 … // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statist…
60498 …the TX packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the MCP/per…
60499 …// Statistic register for the number of TX packets that have the per-PF drop or per-VPORT drop con…
60500 …f the LB packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the per-T…
60501 …-PF drop or per-VPORT drop configuration set while the no-drop-hdr-ind in the packet is cleared. T…
60568 …ets from BMB to be forwarded to the host that got truncated due to BRB LB per-TC full backpressure.
60569 …ckets from BMB to be forwarded to the host that got dropped due to BRB LB per-TC full backpressure.
60570 … 0x501f08UL //Access:RW DataWidth:0x1 // Zero-padding enable for TX…
60576 …-to-transmit data remaining below which ETS arbiter for the transmit path should start selecting …
60584 …ccess:RW DataWidth:0x20 // Increment PERIOD for the global rate limiter - in term of 25MHz clo…
60585 …Access:RW DataWidth:0x20 // Increment VALUE for the global rate limiter - in term of bytes, cy…
60586 …cess:RW DataWidth:0x20 // Upper bound VALUE for the global rate limiter - in term of bytes, cy…
60589 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60590 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60591 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60592 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60594 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
60596 … 0x501f50UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbitration mo…
60605 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 7 is allowed to reach.
60617 …idth:0x20 // Specify the weight (in bytes) to be added to credit register 7 when it is time to i…
60622 …0x501fb8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60623 …0x501fbcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60624 …0x501fc0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60625 …0x501fc4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60626 …0x501fc8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60627 …0x501fccUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60628 …0x501fd0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60629 …R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter credit register 7.
60630 …0x501fd8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60631 …0x501fdcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60632 …0x501fe0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60633 …0x501fe4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60649 …MAC2 (0x1<<7) // Mask bit for for…
60650 …IG_REG_TX_LLH_NCSI_MCP_MASK_MAC2_SHIFT 7
60725 …WD_MASK_MAC2 (0x1<<7) // Mask bit for not…
60726 …IG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC2_SHIFT 7
60790 …_MAC2 (0x1<<7) // Mask bit for for…
60791 …IG_REG_TX_LLH_NCSI_NTWK_MASK_MAC2_SHIFT 7
60871 …erride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bi…
60872 …erride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bi…
60889 …n the BMC-to-host path to BRB. This is also used in the TX management path (when enabled by *tx_m…
60891 … 0x50209cUL //Access:RW DataWidth:0x1 // Host-to-MCP path enable. Se…
60895 … 0x5020acUL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
60900 … 0x5020c0UL //Access:RW DataWidth:0x7 // Almost-full threshold for DO…
60904 …. 0 - send debug traffic through port 0. 1 - send debug traffic through port 1. 2 - send debug tr…
60907 … 0x5020dcUL //Access:RW DataWidth:0x8 // Almost-full threshold for de…
60910 …- the number of valid bytes in the last cycle (0=all bytes are valid); [261]eop - active on the la…
60953 …-port per-PF register. L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L…
60954 … 0x508004UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Pro…
60955 …o enable ACPI pattern matching and TCP SYN matching in multi-function mode even when the per-funct…
60957 … 0x508080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
60959 … 0x508100UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Whe…
60960 … 0x508104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60961 … 0x508108UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60962 … 0x50810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60963 … 0x508110UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60964 … 0x508114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60965 … 0x508118UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60966 … 0x50811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60967 … 0x508120UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60968 … 0x508124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60969 … 0x508128UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60970 … 0x50812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60971 … 0x508130UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60972 … 0x508134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60973 … 0x508138UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60974 …813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC32C for pattern 7.
60975 … 0x508140UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60976 … 0x508144UL //Access:RW DataWidth:0x2 // This is a per-port per-PF register. Set…
60977 …-port per-PF register. Enable bits for fields to be compared if IPv6 is present in the packet. B…
60978 …-port per-PF register. Enable bits for fields to be compared if IPv4 is present in the packet. B…
60979 … 0x508150UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60980 … 0x508154UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60981 … 0x508158UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60982 … 0x50815cUL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60983 … 0x508160UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60985 … 0x508170UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60987 … 0x508180UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60988 … 0x508184UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60989 … 0x508188UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Whe…
60990 … 0x508190UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
60992 … 0x508198UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high …
60993 … 0x5081a0UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wa…
60995 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
60996 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
60997 … 0x5081c8UL //Access:R DataWidth:0xe // Wake packet length - the actual length of…
60998 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
60999 …s:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
61001 …s:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
61007 …est UDP port[15:0], source/dest IPV4 address[31:0]} or ethernet type[15:0] or IPV4OptionNumber[7:0]
61008 …est UDP port[15:0], source/dest IPV4 address[31:0]} or ethernet type[15:0] or IPV4OptionNumber[7:0]
61009 …est UDP port[15:0], source/dest IPV4 address[31:0]} or ethernet type[15:0] or IPV4OptionNumber[7:0]
61010 …est UDP port[15:0], source/dest IPV4 address[31:0]} or ethernet type[15:0] or IPV4OptionNumber[7:0]
61019 …ARD � insert timestamp using standard IPv4 Timestamp option. In this mode 32-bit timestamp with se…
61022 …RW DataWidth:0x5 // Global timestamp shift for the free running counter. Legal values are 0-16
61026 …ataWidth:0x15 // RX User protocol Packet information that is buffered in 1-deep FIFOs. Bits [15…
61027 …ataWidth:0x40 // RX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp …
61029 …ataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Source add…
61031 …ataWidth:0x15 // TX User protocol Packet information that is buffered in 1-deep FIFOs. Bits [15…
61032 …ataWidth:0x40 // TX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp …
61034 …ataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Destinatio…
61050 … 0x5088e0UL //Access:RW DataWidth:0x4 // Bits 3:0 are the active-low output enables fo…
61052 …FO data bytes occupancy is higher than this threshold nig_dorq_edpm_en is de-asserted. The value i…
61059 … // This field maps (ipv4_tos >> 2) 6 bits to 6 bits: bits 5:3 - priority bits 2:0 - TC This co…
61065 …-port register L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L2 tags 0…
61066 … 0x508b14UL //Access:RW DataWidth:0x1 // This is a per-port register. Propr…
61067 … 0x508b18UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61068 … 0x508b1cUL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61069 … 0x508b20UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61070 … 0x508b24UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61071 … 0x508b28UL //Access:RW DataWidth:0x1 // This is a per-port register. Enabl…
61072 … 0x508b2cUL //Access:RW DataWidth:0x1 // This is a per-port register. Enable…
61073 … 0x508b30UL //Access:RW DataWidth:0x1 // This is a per-port register. Perfo…
61074 … 0x508b34UL //Access:RW DataWidth:0x10 // This is a per-port register. Next …
61075 … 0x508b38UL //Access:RW DataWidth:0x10 // This is a per-port register. Destin…
61076 … a per-port register which defines mapping of TC from the received TC to the TC sent to the BRB. b…
61094 …2_RX_LLH_NCSI_MCP_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for for…
61095 …IG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V6_CLI_E5_SHIFT 7
61107 …2_TX_LLH_NCSI_MCP_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for for…
61108 …IG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V6_CLI_E5_SHIFT 7
61124 …D_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for not…
61125 …IG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V6_CLI_E5_SHIFT 7
61137 …WD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for not…
61138 …IG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V6_CLI_E5_SHIFT 7
61150 …_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for for…
61151 …IG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V6_CLI_E5_SHIFT 7
61161 …nables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.
61162 …nables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.
61163 …t reisters. This enables credit sharing with one of the BTB TCs. 0: MNG. 1-8: BTB per TC. 9: B…
61190 … 0x509060UL //Access:RW DataWidth:0x20 // Destination MAC address 7. LLH will look for …
61191 … 0x509064UL //Access:RW DataWidth:0x10 // Destination MAC address 7. LLH will look for …
61192 …ther to use the MPA CRC calculation on one fully contained PDU (legacy mode - 0) or on multiple PD…
61193 …MAC addresses to be matched with for MAC-address-based classification. This register is also used…
61197 …ter is to be used for MAC-addresss based classification or protocol-based classification. Set thi…
61199 …512 select bits for the different protocol types to be evaluated in protocol-based classification …
61207 … 0x50d400UL //Access:RW DataWidth:0x1 // Per-VPORT drop configurat…
61209 … 0x50d800UL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
61253 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
61254 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
61397 …IFO_ERROR (0x1<<7) // Queue FIFO error…
61398 …MB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR_SHIFT 7
61454 …FIFO_ERROR (0x1<<7) // This bit masks, …
61455 …MB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR_SHIFT 7
61511 …E_FIFO_ERROR (0x1<<7) // Queue FIFO error…
61512 …MB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR_SHIFT 7
61568 …UE_FIFO_ERROR (0x1<<7) // Queue FIFO error…
61569 …MB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR_SHIFT 7
61629 …DSCR_FIFO_ERROR (0x1<<7) // Warning! Check t…
61630 …MB_REG_INT_STS_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT 7
61682 …_DSCR_FIFO_ERROR (0x1<<7) // This bit masks, …
61683 …MB_REG_INT_MASK_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT 7
61735 …ND_DSCR_FIFO_ERROR (0x1<<7) // Warning! Check t…
61736 …MB_REG_INT_STS_WR_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT 7
61788 …OND_DSCR_FIFO_ERROR (0x1<<7) // Warning! Check t…
61789 …MB_REG_INT_STS_CLR_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT 7
61841 …_FIFO_ERROR (0x1<<7) // Read packet clie…
61842 …MB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT 7
61904 …P_FIFO_ERROR (0x1<<7) // This bit masks, …
61905 …MB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT 7
61967 …RSP_FIFO_ERROR (0x1<<7) // Read packet clie…
61968 …MB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT 7
62030 …_RSP_FIFO_ERROR (0x1<<7) // Read packet clie…
62031 …MB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT 7
62091 …FIFO_ERROR (0x1<<7) // Link list arbite…
62092 …MB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR_SHIFT 7
62146 …_FIFO_ERROR (0x1<<7) // This bit masks, …
62147 …MB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR_SHIFT 7
62201 …LS_FIFO_ERROR (0x1<<7) // Link list arbite…
62202 …MB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT 7
62256 …RLS_FIFO_ERROR (0x1<<7) // Link list arbite…
62257 …MB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT 7
62313 …T_PTR_FIFO_ERROR (0x1<<7) // Read packet clie…
62314 …MB_REG_INT_STS_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT 7
62372 …RT_PTR_FIFO_ERROR (0x1<<7) // This bit masks, …
62373 …MB_REG_INT_MASK_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT 7
62431 …STRT_PTR_FIFO_ERROR (0x1<<7) // Read packet clie…
62432 …MB_REG_INT_STS_WR_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT 7
62490 …_STRT_PTR_FIFO_ERROR (0x1<<7) // Read packet clie…
62491 …MB_REG_INT_STS_CLR_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT 7
62549 …_LEFT_FIFO_ERROR (0x1<<7) // Read packet clie…
62550 …MB_REG_INT_STS_6_RC_PKT8_RLS_LEFT_FIFO_ERROR_SHIFT 7
62585 …ction for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
62610 …S_LEFT_FIFO_ERROR (0x1<<7) // This bit masks, …
62611 …MB_REG_INT_MASK_6_RC_PKT8_RLS_LEFT_FIFO_ERROR_SHIFT 7
62671 …RLS_LEFT_FIFO_ERROR (0x1<<7) // Read packet clie…
62672 …MB_REG_INT_STS_WR_6_RC_PKT8_RLS_LEFT_FIFO_ERROR_SHIFT 7
62707 …ction for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
62732 …_RLS_LEFT_FIFO_ERROR (0x1<<7) // Read packet clie…
62733 …MB_REG_INT_STS_CLR_6_RC_PKT8_RLS_LEFT_FIFO_ERROR_SHIFT 7
62768 …ction for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
62795 …FIFO_ERROR (0x1<<7) // Warning! Check t…
62796 …MB_REG_INT_STS_7_WC4_LL_REQ_FIFO_ERROR_SHIFT 7
62860 …_FIFO_ERROR (0x1<<7) // This bit masks, …
62861 …MB_REG_INT_MASK_7_WC4_LL_REQ_FIFO_ERROR_SHIFT 7
62925 …EQ_FIFO_ERROR (0x1<<7) // Warning! Check t…
62926 …MB_REG_INT_STS_WR_7_WC4_LL_REQ_FIFO_ERROR_SHIFT 7
62990 …REQ_FIFO_ERROR (0x1<<7) // Warning! Check t…
62991 …MB_REG_INT_STS_CLR_7_WC4_LL_REQ_FIFO_ERROR_SHIFT 7
63049 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
63051 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
63053 …(0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
63055 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer …
63056 …MB_REG_INT_STS_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT 7
63057 …) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
63059 …(0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
63061 …Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
63063 … Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
63065 …2) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
63067 …x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
63069 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
63071 … in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
63073 …available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
63120 …OINT_FIFO_ERROR (0x1<<7) // This bit masks, …
63121 …MB_REG_INT_MASK_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT 7
63179 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
63181 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
63183 …(0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
63185 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer …
63186 …MB_REG_INT_STS_WR_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT 7
63187 …) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
63189 …(0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
63191 …Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
63193 … Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
63195 …2) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
63197 …x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
63199 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
63201 … in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
63203 …available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
63244 …(0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
63246 … (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
63248 …(0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
63250 … (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer …
63251 …MB_REG_INT_STS_CLR_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT 7
63252 …) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
63254 …(0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
63256 …Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
63258 … Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
63260 …2) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
63262 …x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
63264 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
63266 … in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
63268 …available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
63315 …FIFO_ERROR (0x1<<7) // Warning! Check t…
63316 …MB_REG_INT_STS_9_WC9_NOTIFY_FIFO_ERROR_SHIFT 7
63390 …_FIFO_ERROR (0x1<<7) // This bit masks, …
63391 …MB_REG_INT_MASK_9_WC9_NOTIFY_FIFO_ERROR_SHIFT 7
63465 …FY_FIFO_ERROR (0x1<<7) // Warning! Check t…
63466 …MB_REG_INT_STS_WR_9_WC9_NOTIFY_FIFO_ERROR_SHIFT 7
63540 …IFY_FIFO_ERROR (0x1<<7) // Warning! Check t…
63541 …MB_REG_INT_STS_CLR_9_WC9_NOTIFY_FIFO_ERROR_SHIFT 7
63647 …IFO_PUSH_ERROR (0x1<<7) // Warning! Check t…
63648 …MB_REG_INT_STS_11_WC9_SYNC_FIFO_PUSH_ERROR_SHIFT 7
63658 …FIFO_PUSH_ERROR (0x1<<7) // This bit masks, …
63659 …MB_REG_INT_MASK_11_WC9_SYNC_FIFO_PUSH_ERROR_SHIFT 7
63669 …C_FIFO_PUSH_ERROR (0x1<<7) // Warning! Check t…
63670 …MB_REG_INT_STS_WR_11_WC9_SYNC_FIFO_PUSH_ERROR_SHIFT 7
63680 …NC_FIFO_PUSH_ERROR (0x1<<7) // Warning! Check t…
63681 …MB_REG_INT_STS_CLR_11_WC9_SYNC_FIFO_PUSH_ERROR_SHIFT 7
63714 …I_ECC_RF_INT (0x1<<7) // This bit masks, …
63715 …MB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_SHIFT 7
63811 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
63812 …MB_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_E5_SHIFT 7
63861 …I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, …
63862 …MB_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB_K2_SHIFT 7
63876 …erate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[7].i_bb_bank.rf_ecc_er…
63900 … (0x1<<7) // Enable ECC for memory ecc instance bmb.BB_BANK_…
63901 …MB_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_SHIFT 7
63933 … (0x1<<7) // Set parity only for memory ecc instance bmb.BB_BA…
63934 …MB_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_SHIFT 7
63966 … (0x1<<7) // Record if a correctable error occurred on memory ecc instanc…
63967 …MB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_SHIFT 7
63985 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
63986 …04UL //Access:RW DataWidth:0xa // Number of valid bytes in header in 16-bytes resolution. Aft…
63994 …ngth error other way it will continue to work as usual.::s/STOP_LEN_ERR_RST/7/g in Reset Value::s/…
63995 … shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) R…
64009 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64010 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64011 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64012 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64013 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64014 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64015 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64016 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64017 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64018 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64019 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64020 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64021 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64022 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64023 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64024 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64025 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64026 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64027 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64033 …NO_DEAD_CYCLE_RST/1/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser…
64035 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64037 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64039 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64041 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64043 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64045 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64047 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64049 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64051 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64053 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64057 …is is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
64058 …client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7…
64059 …h multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is high…
64089 …C_PKT_INP_IF_RST/15/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser…
64093 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
64096 …C_PKT_OUT_IF_RST/31/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser…
64106 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64107 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64108 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64109 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64110 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64111 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64112 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64113 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64114 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64115 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64128 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64129 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64130 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64131 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64132 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64133 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64134 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64135 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64136 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64137 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64138 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64139 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64140 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64141 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64142 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64143 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64144 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64145 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64146 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64147 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64148 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64149 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64150 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64151 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64152 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64153 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64154 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64155 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64156 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64157 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64158 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64159 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64160 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
64163 … // Debug register. FIFO counters status of link list arbiter: {rls_fifo[7:4]; prefetch_fifo_1[…
64252 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
64254 …s register for each erad packet client interface: TBD. Message spelling (MSB->LSB): rest_size_erro…
64257 …s register for each read packet client interface: TBD. Message spelling (MSB->LSB): opaque[1:0]; r…
64260 …32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[…
64262 …32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[…
64264 …32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[…
64266 …32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[…
64268 …32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[…
64270 …32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[…
64272 …32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[…
64274 …32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[…
64276 …32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[…
64278 …32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[…
64280 …Access:RW DataWidth:0xc // Link list dual port memory that contains per-block descriptor::s/B…
64285 … 0x560000UL //Access:RW DataWidth:0x1 // Initiate the ATC array - reset all the valid …
64287 …taWidth:0x20 // Logging register for reuse miss on transpend entry [31:0] - TID of the problemat…
64288 …taWidth:0x1c // Logging register for reuse miss on transpend entry [27:0] - ATC page index of th…
64289 …gister for reuse miss on transpend entry [11:0] - Reuse count of the problematic lookuprequest [23…
64290 …ster for the case of invalidation halt (lkpres of invalidated range) [31:0] - TID of the problemat…
64291 …ster for the case of invalidation halt (lkpres of invalidated range) [27:0] - ATC page index of th…
64292 …ster for the case of invalidation halt (lkpres of invalidated range) [11:0] - Reuse count of the p…
64294 …s of the PXP read requests issued by the PTU logic. [0:8] - ST index; [10:9] - ST hint; [11] - ST …
64301 … 0x560078UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per PF.
64304 …aWidth:0x1 // Bit per PF. Indicates that the marked invalidation is done - when read it is also…
64306 … 0x56008cUL //Access:RW DataWidth:0x1 // When set - the block will halt …
64307 … 0x560090UL //Access:RW DataWidth:0x3 // Max credits of the PBF->PXP interface.
64308 … 0x560094UL //Access:RW DataWidth:0x3 // Max credits of the PRM->PXP interface.
64309 … 0x560098UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64310 … 0x56009cUL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64311 … 0x5600a0UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64320 …00c4UL //Access:RW DataWidth:0x1 // Replacement mode for the ATC. If de-asserted then low pri…
64339 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64351 …_THAN_STU (0x1<<7) // Indicates Ireq w…
64352 …TU_REG_INT_STS_ATC_IREQ_LESS_THAN_STU_SHIFT 7
64368 …S_THAN_STU (0x1<<7) // This bit masks, …
64369 …TU_REG_INT_MASK_ATC_IREQ_LESS_THAN_STU_SHIFT 7
64373 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64385 …ESS_THAN_STU (0x1<<7) // Indicates Ireq w…
64386 …TU_REG_INT_STS_WR_ATC_IREQ_LESS_THAN_STU_SHIFT 7
64390 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64402 …LESS_THAN_STU (0x1<<7) // Indicates Ireq w…
64403 …TU_REG_INT_STS_CLR_ATC_IREQ_LESS_THAN_STU_SHIFT 7
64425 …I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, …
64426 …TU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT 7
64431 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
64432 …TU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_E5_SHIFT 7
64477 …00UL //Access:RW DataWidth:0x2 // Defines the number of sets - 3 - 512 ;2- 256; 1- 128; 0- 64.
64483 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64484 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64485 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64486 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64487 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64488 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64489 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64490 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64491 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64492 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64493 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64494 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64509 … 0x560480UL //Access:RW DataWidth:0x1 // CheckTags configuration bit - when set the availab…
64510 … 0x560484UL //Access:RW DataWidth:0x8 // TAG threshold - for the checkTags fe…
64523 … 0x5604b8UL //Access:RC DataWidth:0x20 // Number of hits for Main-lookups in the ATC.
64525 … 0x5604c0UL //Access:RC DataWidth:0x20 // Number of treqs issued due to pre-lookup.
64572 … //Access:R DataWidth:0x20 // Data belongs to an erroneous TCPL: [31:0]-bits [31:0] of the ad…
64573 … //Access:R DataWidth:0x14 // Data belongs to an erroneous TCPL: [19:0]-bits [51:32] of the a…
64578 … 0x560594UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 31-0.
64579 … 0x560598UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 63-32.
64580 … 0x56059cUL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 95-64.
64581 … 0x5605a0UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 127-96.
64582 … 0x5605a4UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 159-128.
64583 … 0x5605a8UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 191-160.
64584 … 0x5605acUL //Access:R DataWidth:0x10 // Indicates the end of FLI flow for PF 15-0.
64585 …b0UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 31-0 accordingly.
64586 …b4UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 63-32 accordingly.
64587 …8UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 95-64 accordingly.
64588 …cUL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 127-96 accordingly.
64589 …L //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 159-128 accordingly.
64590 …UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 191-160 accordingly.
64591 …c8UL //Access:RW DataWidth:0x10 // Clears the FLI done indication for PF bits 15-0 accordingly.
64610 …605e4UL //Access:RW DataWidth:0x8 // Resource Type of the invalidated range - register per PF.
64612 …ster for the case of invalidation halt (lkpres of invalidated range) [7:0] - Resource type of t…
64614 …x8 // Logging register for reuse miss on transpend entry bits [35:28] - of the problematic r…
64615 …taWidth:0x8 // Logging register for reuse miss on transpend entry [7:0] - Resource type of t…
64617 … 0x560600UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per Strom.
64621 … 0x560640UL //Access:RW DataWidth:0x8 // TID of the invalidated range - register per Storm.
64627 …dth:0x1 // Bit per Storm. Indicates that the marked invalidation is done - when read it is also…
64631 …x40 // Access the GPA table way 0; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64633 …x40 // Access the GPA table way 1; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64635 …x40 // Access the GPA table way 2; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64639 …h:0x40 // Access the GPA table way3; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID-…
64641 …- {par - [51]; NS bit - [50]; W bit - [49]; R bit - [48]; U bit - [47]; Priority bit - [46]; PLRU …
64643 … // Access the GPA table way 0; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64645 … // Access the GPA table way 1; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64647 … // Access the GPA table way 2; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64649 … // Access the GPA table way3; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64651 …- { Priority bit - [23]; PLRU - [22]; Err bit - [21]; invpend bit [20]; transpend bit - [19]; vali…
64658 … (0x1<<1) // Enables CDU Inputs -- Must be set for norm…
64660 … (0x1<<2) // Enables CDU Outputs -- Must be set for nor…
64668 … (0x1<<6) // Masks all PCIE Errors for Load transactions. NOTE -- This is not connecte…
64685 … (0x1<<7) // Byte valid Error…
64686 …DU_REG_INT_STS_BVALID_ERROR_SHIFT 7
64702 …ROR (0x1<<7) // Byte valid Error…
64703 …DU_REG_INT_STS_CLR_BVALID_ERROR_SHIFT 7
64719 …OR (0x1<<7) // Byte valid Error…
64720 …DU_REG_INT_STS_WR_BVALID_ERROR_SHIFT 7
64736 … (0x1<<7) // This bit masks, …
64737 …DU_REG_INT_MASK_BVALID_ERROR_SHIFT 7
64755 …tion for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64757 …tion for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64759 …tion for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64761 …tion for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64764 …tion for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64766 …tion for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64768 …tion for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64770 …tion for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64773 …tion for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64775 …tion for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64777 …tion for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64779 …tion for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64782 …tion for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64784 …tion for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64786 …tion for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64788 …tion for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] -…
64790 …rols the Full signal to PXP. This register must never be set higher than 8 -- doing so will result…
64791 …ories when past this limit. This register must never be set higher than 13 -- doing so will result…
64865 …// Logging of error data in case of a CCFC Load error. [24:16] LCID [11:8] Type [7:0] Regions
64866 …// Logging of error data in case of a TCFC Load error. [24:16] LCID [11:8] Type [7:0] Regions
64867 …gging of error data in case of a CCFC Writeback Error. [24:16] LCID [11:8] Type [7:0] Regions
64868 …gging of error data in case of a TCFC Writeback Error. [24:16] LCID [11:8] Type [7:0] Regions
64872 … (0xfff<<12) // Block waste within a page. this number equals to PageSize-NCIB*ContextSize.
64904 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64910 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64911 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64922 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64923 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64924 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64925 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64926 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64927 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64928 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64929 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64930 …0x5a0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64931 …0x5a0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64932 …0x5a0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64933 …0x5a003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64936 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
64937 …g register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current len…
64945 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64947 … (0x1<<3) // Mini cache error - meaning that A load …
64949 … (0x1<<4) // Mini cache error - meaning that A load …
64971 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64973 … (0x1<<3) // Mini cache error - meaning that A load …
64975 … (0x1<<4) // Mini cache error - meaning that A load …
64984 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64986 … (0x1<<3) // Mini cache error - meaning that A load …
64988 … (0x1<<4) // Mini cache error - meaning that A load …
65007 …_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
65008 …TLD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5_SHIFT 7
65013 … 0x5a0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65020 … (0x1<<2) // defines that only back-to-back aggregation is …
65039 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
65041 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
65043 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
65045 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
65048 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
65050 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
65052 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
65054 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
65057 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
65059 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
65061 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
65063 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
65066 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
65068 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
65070 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
65072 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
65108 … 0x5a0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65109 … 0x5a0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65110 … 0x5a082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65111 … 0x5a0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65112 … 0x5a0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65113 … 0x5a0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65114 … 0x5a083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65115 … 0x5a0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65116 … 0x5a0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65117 … 0x5a0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65118 … 0x5a084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65119 … 0x5a0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65120 … 0x5a0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65121 … 0x5a0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65122 … 0x5a085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65123 … 0x5a0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65124 … 0x5a0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65125 … 0x5a0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65126 … 0x5a086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65127 … 0x5a0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65128 … 0x5a0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65129 … 0x5a0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65130 … 0x5a087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65131 … 0x5a0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65132 … 0x5a0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65133 … 0x5a0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65134 … 0x5a088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65135 … 0x5a0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65136 … 0x5a0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65137 … 0x5a0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65138 … 0x5a089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65139 … 0x5a08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65141 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
65143 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
65145 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
65147 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
65150 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
65152 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
65154 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
65156 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
65159 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
65161 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
65163 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
65165 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
65168 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
65170 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
65172 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
65174 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
65213 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
65215 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
65217 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
65219 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
65221 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
65223 … (0x1f<<9) // offset of the flow-ID, in 32b units, fro…
65225 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
65227 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
65248 … (0xff<<0) // The value by which to increment the event-ID in case of success…
65250 … (0xff<<8) // The value by which to increment the event-ID in case of success…
65252 … (0xff<<16) // The value by which to increment the event-ID in case of success…
65254 … (0xff<<24) // The value by which to increment the event-ID in case of success…
65274 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65275 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65276 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65277 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65278 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65279 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65280 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65281 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65282 …0x5c0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65283 …0x5c0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65284 …0x5c0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65285 …0x5c003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65288 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
65289 …g register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current len…
65297 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65299 … (0x1<<3) // Mini cache error - meaning that A load …
65301 … (0x1<<4) // Mini cache error - meaning that A load …
65323 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65325 … (0x1<<3) // Mini cache error - meaning that A load …
65327 … (0x1<<4) // Mini cache error - meaning that A load …
65336 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65338 … (0x1<<3) // Mini cache error - meaning that A load …
65340 … (0x1<<4) // Mini cache error - meaning that A load …
65359 …_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
65360 …PLD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5_SHIFT 7
65365 … 0x5c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65372 … (0x1<<2) // defines that only back-to-back aggregation is …
65391 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
65393 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
65395 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
65397 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
65400 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
65402 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
65404 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
65406 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
65409 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
65411 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
65413 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
65415 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
65418 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
65420 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
65422 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
65424 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
65460 … 0x5c0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65461 … 0x5c0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65462 … 0x5c082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65463 … 0x5c0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65464 … 0x5c0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65465 … 0x5c0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65466 … 0x5c083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65467 … 0x5c0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65468 … 0x5c0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65469 … 0x5c0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65470 … 0x5c084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65471 … 0x5c0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65472 … 0x5c0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65473 … 0x5c0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65474 … 0x5c085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65475 … 0x5c0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65476 … 0x5c0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65477 … 0x5c0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65478 … 0x5c086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65479 … 0x5c0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65480 … 0x5c0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65481 … 0x5c0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65482 … 0x5c087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65483 … 0x5c0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65484 … 0x5c0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65485 … 0x5c0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65486 … 0x5c088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65487 … 0x5c0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65488 … 0x5c0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65489 … 0x5c0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65490 … 0x5c089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65491 … 0x5c08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65493 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
65495 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
65497 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
65499 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
65502 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
65504 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
65506 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
65508 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
65511 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
65513 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
65515 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
65517 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
65520 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
65522 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
65524 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
65526 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
65565 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
65567 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
65569 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
65571 … (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
65573 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
65575 … (0x1f<<9) // offset of the flow-ID, in 32b units, fro…
65577 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
65579 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
65600 … (0xff<<0) // The value by which to increment the event-ID in case of success…
65602 … (0xff<<8) // The value by which to increment the event-ID in case of success…
65604 … (0xff<<16) // The value by which to increment the event-ID in case of success…
65606 … (0xff<<24) // The value by which to increment the event-ID in case of success…
65658 …I_MEM_PRTY_K2_E5 (0x1<<7) // This bit masks, …
65659 …OL_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_E5_SHIFT 7
65693 …-port per-PF register. L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L…
65695 … 0x608080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
65697 … 0x608100UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
65698 … 0x608104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65699 … 0x608108UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65700 … 0x60810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65701 … 0x608110UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65702 … 0x608114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65703 … 0x608118UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65704 … 0x60811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65705 … 0x608120UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65706 … 0x608124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65707 … 0x608128UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65708 … 0x60812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65709 … 0x608130UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65710 … 0x608134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65711 … 0x608138UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65712 …813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC32C for pattern 7.
65713 … 0x608140UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65714 … 0x608144UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Whe…
65715 … 0x608148UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
65717 … 0x608150UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high …
65718 … 0x608160UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wa…
65720 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
65721 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
65722 … 0x608188UL //Access:R DataWidth:0xe // Wake packet length - the actual length of…
65723 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
65725 …election - acpi_default_pf_sel. 2: Select the first of each: 2 ports (quad_port_mode is 0) - use o…
65726 … 0x608198UL //Access:RW DataWidth:0x2 // This is a per-PF register. Set bit…
65727 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid …
65728 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid …
65729 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid …
65730 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid …
65731 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid …
65732 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid …
65764 …erride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bi…
65765 …erride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bi…
65766 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid …
65788 …_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_INPUT_SEL_I_K2_E5 (0x3<<7) //
65789 …HY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_INPUT_SEL_I_K2_E5_SHIFT 7
65813 …_PHY_REFCLK_CONTROL_PHY1_REFCLK_GATE_I_K2_E5 (0x1<<7) //
65814 …HY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_REFCLK_GATE_I_K2_E5_SHIFT 7
65886 …d on CMU0 in multiple CMU PHYs if there are any active lanes. Signal is over-riden by por_n_i so h…
65894 …_I_K2_E5 (0x1<<7) // Powerdown contro…
65895 …S_REG_COMMON_CONTROL_CMU1_PD_I_K2_E5_SHIFT 7
65911 …- rxsig_det_mask_i 16 - rxeii_exit_type_i 15 - rxei_infer_i 14 - bslip_req_i 13 - data_width_i - 0…
65915 …pcs_sdet 0 - ln1_stat_o[2] (RX Locked indicator) 1 - ln1_astat_o[5] (Raw signal detext indicator)…
65923 …- not used 12 - ln1_ok_o 11 - ln1_runlen_err_o 10:4 - not used 3:2 - ln1_rx_locked_o - bit 3 =rxda…
65925 …(0x3f<<14) // 19 - Raw signal detect - Bit Slip Ack 18 - ln1_bitslip_ack_o - Bit Slip Ack 17 - not…
65936 …LK_OE_L_I_K2_E5 (0x1<<7) // Output enables f…
65937 …S_REG_CLOCK_SELECT_CMU1_REFCLK_OE_L_I_K2_E5_SHIFT 7
65968 …-0x1ff. Reserved = 0x200-0x3ff. LANE1 registers = 0x400-0x5ff. Reserved = 0x600-0x7f…
65977 …to set0 1: Using registers belonging to set1 SETS_W-1: Using set of registers belonging to set SET…
65979 …corresponds to FLOW 1 Bit [1] : corresponds to FLOW 2 Any toggle from zero-to-one will generate an…
65984 … (0x3<<1) // It replicates the mode-sel value when voltag…
65986 … (0x7<<3) // It replicates the set-sel value when voltag…
66027 … (0x1<<0) // If set overrides hardware control of the Traffic LED. The Traffic LED will then b…
66029 …_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LED_CONTROL_BLINK_TRAFFIC bit bit is also s…
66031 …th the LED_CONTROL_OVERRIDE_TRAFFIC bit and LED_CONTROL_TRAFFIC LED bit; the Traffic LED will blin…
66033 …it is cleared: Number of main clock cycles the led is ON will be 2^32. Number of main clock cycles…
66037 …n + off) for Traffic LED. number of main clock cycles the led is ON = (contorl_blink_rate*2^15) n…
66039 …Led mode: 0 -> MAC; 1-2 -> PHY1; 3 -> PHY3; 4 -> MAC2; 5-6 -> PHY4; 7 -> PHY6;…
66040 …// LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1' to each bit location wil…
66041 …// LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1' to each bit location wil…
66042 …// LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1' to each bit location wil…
66043 …LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G This register allows the MAC (Dri…
66045 … corresponding Physical function. 0 -> NW0 connects to PF0 1 -> NW0 connects to PF1 2 -> NW0 co…
66047 … corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connects to PF1 2 -> NW1 co…
66049 … corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1 2 -> NW2 co…
66051 … corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1 2 -> NW3 co…
66053 …/Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G …
66054 …/Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G …
66055 …/Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G …
66056 …/Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G …
66057 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
66073 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66075 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66081 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66084 …<0) // 0x0 - Select reference clock from Bump 0x1 - Select inter-macro refrence clock from the lef…
66086 … (0x3<<2) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro ref…
66088 … (0x3<<4) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro re…
66090 …l is used for nws_nwm_sd_energy_detect. 0 - use ~lnX_stat_los_o 1 - use ~lnX_stat_los_deglitch_o (…
66108 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66110 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66112 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66114 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66116 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66118 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66121 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66128 … (0x1f<<0) // Sets phy_ctrl_refclk_i used for CMU0 0x09 - refclk is 257.8125Mhz
66130 … Sets phy_ctrl_rate1_i used for CMU0 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66132 … Sets phy_ctrl_rate1_i used for CMU1 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66148 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66150 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66152 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66154 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66157 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66164 … (0x1<<0) // 0x0 - No error 0x1 - Phy has inter…
66166 … (0x1<<1) // 0x1 - Indicates CMU0 PLL h…
66168 … (0x1<<2) // 0x1 - Indicates CMU1 PLL h…
66170 … (0x1<<3) // 0x0 - PHY is not ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. The signal…
66172 … (0x1<<4) // 0x0 - PHY is not ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. The signal…
66174 … (0x1<<5) // 0x0 - PHY is not ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. The signal…
66176 … (0x1<<6) // 0x0 - PHY is not ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. The signal…
66178 … (0x1<<7) // 0x0 - PHY is not ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. The s…
66179 …WS_REG_COMMON_STATUS_LN2_RST_PD_READY_O_K2_SHIFT 7
66180 … (0x1<<8) // 0x0 - PHY is not ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. The signal…
66196 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66198 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66200 … LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instea…
66204 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66207 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66209 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66211 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66213 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66215 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66218 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66220 … (0x1<<1) // 0x0 - data on ln0_rxdata_o is invalid. 0x1 - d…
66222 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66224 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. …
66226 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. …
66231 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66233 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66239 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66256 …0_LINK_STATUS_10G_KR_I_K2 (0x1<<7) // Set to 1 if the …
66257 …WS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_10G_KR_I_K2_SHIFT 7
66261 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66268 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66270 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66272 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66274 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66276 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66278 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66280 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66282 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66284 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66288 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66294 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66296 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66314 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66316 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66318 … LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instea…
66322 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66325 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66332 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66334 … (0x1<<1) // 0x0 - data on ln1_rxdata_o is invalid. 0x1 - d…
66336 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66338 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. …
66340 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. …
66370 …1_LINK_STATUS_10G_KR_I_K2 (0x1<<7) // Set to 1 if the …
66371 …WS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_10G_KR_I_K2_SHIFT 7
66375 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66377 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66379 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66381 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66383 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66386 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66388 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66390 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66392 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66394 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66396 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66398 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66400 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66402 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66406 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66412 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66414 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66421 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66423 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66429 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66432 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66434 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66436 … LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instea…
66440 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66443 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66450 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66452 … (0x1<<1) // 0x0 - data on ln2_rxdata_o is invalid. 0x1 - d…
66454 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66456 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. …
66458 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. …
66488 …2_LINK_STATUS_10G_KR_I_K2 (0x1<<7) // Set to 1 if the …
66489 …WS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_10G_KR_I_K2_SHIFT 7
66493 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66500 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66502 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66504 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66506 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66508 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66510 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66512 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66514 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66516 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66520 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66526 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66528 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66546 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66548 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66550 … LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instea…
66554 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66557 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66559 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66561 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66563 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66565 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66568 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66570 … (0x1<<1) // 0x0 - data on ln3_rxdata_o is invalid. 0x1 - d…
66572 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66574 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. …
66576 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. …
66581 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66583 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66589 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66606 …3_LINK_STATUS_10G_KR_I_K2 (0x1<<7) // Set to 1 if the …
66607 …WS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_10G_KR_I_K2_SHIFT 7
66611 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66618 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66620 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66622 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66624 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66626 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66628 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66630 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66632 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66634 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66638 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66644 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66646 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66664 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66684 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66686 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66688 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66690 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66692 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66697 …one bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustm…
66707 …K_E5 (0x1<<7) // Phase Lock. Enab…
66708 …WS_REG_RX0_CONTROL_RX0PHSLOCK_E5_SHIFT 7
66712 …one bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustm…
66722 …K_E5 (0x1<<7) // Phase Lock. Enab…
66723 …WS_REG_RX1_CONTROL_RX1PHSLOCK_E5_SHIFT 7
66727 …one bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustm…
66737 …K_E5 (0x1<<7) // Phase Lock. Enab…
66738 …WS_REG_RX2_CONTROL_RX2PHSLOCK_E5_SHIFT 7
66742 …one bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustm…
66752 …K_E5 (0x1<<7) // Phase Lock. Enab…
66753 …WS_REG_RX3_CONTROL_RX3PHSLOCK_E5_SHIFT 7
66757 …t preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coeffi…
66771 …the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 N…
66777 …fined as follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decreme…
66781 …t preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coeffi…
66795 …the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 N…
66801 …fined as follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decreme…
66805 …t preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coeffi…
66819 …the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 N…
66825 …fined as follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decreme…
66829 …t preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coeffi…
66843 …the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 N…
66849 …fined as follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decreme…
66902 …LVE_25G_KR_K2 (0x1<<7) // Autonegotiation …
66903 …WS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_KR_K2_SHIFT 7
66923 …OLVE_25G_KR_K2 (0x1<<7) // This bit masks, …
66924 …WS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_KR_K2_SHIFT 7
66944 …ESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation …
66945 …WS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_KR_K2_SHIFT 7
66965 …RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation …
66966 …WS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_KR_K2_SHIFT 7
66984 …LVE_25G_KR_K2 (0x1<<7) // Autonegotiation …
66985 …WS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_KR_K2_SHIFT 7
67003 …OLVE_25G_KR_K2 (0x1<<7) // This bit masks, …
67004 …WS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_KR_K2_SHIFT 7
67022 …ESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation …
67023 …WS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_KR_K2_SHIFT 7
67041 …RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation …
67042 …WS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_KR_K2_SHIFT 7
67060 …LVE_25G_KR_K2 (0x1<<7) // Autonegotiation …
67061 …WS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_KR_K2_SHIFT 7
67079 …OLVE_25G_KR_K2 (0x1<<7) // This bit masks, …
67080 …WS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_KR_K2_SHIFT 7
67098 …ESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation …
67099 …WS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_KR_K2_SHIFT 7
67117 …RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation …
67118 …WS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_KR_K2_SHIFT 7
67136 …LVE_25G_KR_K2 (0x1<<7) // Autonegotiation …
67137 …WS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_KR_K2_SHIFT 7
67155 …OLVE_25G_KR_K2 (0x1<<7) // This bit masks, …
67156 …WS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_KR_K2_SHIFT 7
67174 …ESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation …
67175 …WS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_KR_K2_SHIFT 7
67193 …RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation …
67194 …WS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_KR_K2_SHIFT 7
67211 …10 // PHY instance0 = 0x000-0x1fff. PHY instance1 = 0x2000-0x3fff. PHY instance2 = 0x4000-0x5fff…
67213 …-0x7ff. CMU0 registers = 0x0800-0x0bff. CMU1 registers = 0x0c00-0x0fff. Reserved = …
67215 …its[15:8] = ram address [2] bits[7:0] = ram address [3] register 0 = ram location [3:0] registe…
67217 …its[15:8] = ram address [2] bits[7:0] = ram address [3] register 0 = ram location [3:0] registe…
67234 …3_K2_E5 (0x1<<7) // TX fifo overflow
67235 …WM_REG_INT_STS_TX_OVERFLOW_3_K2_E5_SHIFT 7
67269 …3_K2_E5 (0x1<<7) // This bit masks, …
67270 …WM_REG_INT_MASK_TX_OVERFLOW_3_K2_E5_SHIFT 7
67304 …OW_3_K2_E5 (0x1<<7) // TX fifo overflow
67305 …WM_REG_INT_STS_WR_TX_OVERFLOW_3_K2_E5_SHIFT 7
67339 …LOW_3_K2_E5 (0x1<<7) // TX fifo overflow
67340 …WM_REG_INT_STS_CLR_TX_OVERFLOW_3_K2_E5_SHIFT 7
67359 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67360 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67361 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67362 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67364 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67368 …_REMOTE_FAULT_K2_E5 (0x1<<7) // Live Remote Faul…
67369 …WM_REG_LN0_LIVE_STS_LN0_LIVE_REMOTE_FAULT_K2_E5_SHIFT 7
67380 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67384 …_REMOTE_FAULT_K2_E5 (0x1<<7) // Live Remote Faul…
67385 …WM_REG_LN1_LIVE_STS_LN1_LIVE_REMOTE_FAULT_K2_E5_SHIFT 7
67396 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67400 …_REMOTE_FAULT_K2_E5 (0x1<<7) // Live Remote Faul…
67401 …WM_REG_LN2_LIVE_STS_LN2_LIVE_REMOTE_FAULT_K2_E5_SHIFT 7
67412 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67416 …_REMOTE_FAULT_K2_E5 (0x1<<7) // Live Remote Faul…
67417 …WM_REG_LN3_LIVE_STS_LN3_LIVE_REMOTE_FAULT_K2_E5_SHIFT 7
67440 … (0x1<<1) // Auto-Negotiation status. Set to '1' when the Auto…
67444 … (0x1<<3) // Auto-Negotiation status. Set to '1' when the Auto…
67448 … (0x1<<5) // Auto-Negotiation status. Set to '1' when the Auto…
67452 … (0x1<<7) // Auto-Negotiation status. Set to '1' when the…
67453 …WM_REG_SGMII_PCS_STATUS_SG3_AN_DONE_K2_E5_SHIFT 7
67470 … 0x800058UL //Access:RW DataWidth:0x1 // Controls the fast-wake mode for the LPI…
67522 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67531 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67540 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67549 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67554 …(1) the block synchronization state machines could successfully lock onto 66-bit block boundaries …
67558 …-lock or align-done status, depending on current mode, and a cleared hi-ber status. The signal sta…
67568 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67570 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67572 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67574 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67576 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67578 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67580 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67582 …7) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly …
67583 …WM_REG_TX_FAULT_MAC2_TX_REM_FAULT_K2_E5_SHIFT 7
67584 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67586 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67588 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67590 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67592 …is defined as "REGISTER VAL"x100nsec. The reset value for this counter is 70 which represent 7usec.
67593 …is defined as "REGISTER VAL"x100nsec. The reset value for this counter is 70 which represent 7usec.
67594 …is defined as "REGISTER VAL"x100nsec. The reset value for this counter is 70 which represent 7usec.
67595 …is defined as "REGISTER VAL"x100nsec. The reset value for this counter is 70 which represent 7usec.
67607 …rrors in a block. count of the number of times fec_cerr asserted for virtual lane 7. Clear on Read.
67615 …rors in a block. count of the number of times fec_ncerr asserted for virtual lane 7. Clear on Read.
67641 …I_MEM_PRTY_K2_E5 (0x1<<7) // This bit masks, …
67642 …WM_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY_K2_E5_SHIFT 7
67704 …I_MEM_PRTY_K2_E5 (0x1<<7) // This bit masks, …
67705 …WM_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_K2_E5_SHIFT 7
67767 …I_MEM_PRTY_K2_E5 (0x1<<7) // This bit masks, …
67768 …WM_REG_PRTY_MASK_H_2_MEM067_I_MEM_PRTY_K2_E5_SHIFT 7
67824 …_CREDIT_IF_ENABLE (0x1<<7) // Enables the qm_l…
67825 …BF_REG_IF_ENABLE_REG_QM_LINE_CREDIT_IF_ENABLE_SHIFT 7
67919 …I_ECC_1_RF_INT_E5 (0x1<<7) // This bit masks, …
67920 …BF_REG_PRTY_MASK_H_0_MEM011_I_ECC_1_RF_INT_E5_SHIFT 7
67983 …I_ECC_0_RF_INT_BB_K2 (0x1<<7) // This bit masks, …
67984 …BF_REG_PRTY_MASK_H_0_MEM012_I_ECC_0_RF_INT_BB_K2_SHIFT 7
68056 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
68057 …BF_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_E5_SHIFT 7
68084 …I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, …
68085 …BF_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB_K2_SHIFT 7
68157 …mory: pbf.i_pbf_ycmd_qs.i_ycmd_hdr.rf_ecc_error_connect Includes 2 words of 7 bits each. The msb o…
68176 …11_I_ECC_1_EN_E5 (0x1<<7) // Enable ECC for m…
68177 …BF_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_1_EN_E5_SHIFT 7
68222 …12_I_ECC_0_EN_BB_K2 (0x1<<7) // Enable ECC for m…
68223 …BF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_0_EN_BB_K2_SHIFT 7
68272 …_MEM011_I_ECC_1_PRTY_E5 (0x1<<7) // Set parity only …
68273 …BF_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_1_PRTY_E5_SHIFT 7
68318 …_MEM012_I_ECC_0_PRTY_BB_K2 (0x1<<7) // Set parity only …
68319 …BF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_0_PRTY_BB_K2_SHIFT 7
68368 …ED_0_MEM011_I_ECC_1_CORRECT_E5 (0x1<<7) // Record if a corr…
68369 …BF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_1_CORRECT_E5_SHIFT 7
68414 …ED_0_MEM012_I_ECC_0_CORRECT_BB_K2 (0x1<<7) // Record if a corr…
68415 …BF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_0_CORRECT_BB_K2_SHIFT 7
68448 …0400UL //Access:RW DataWidth:0x3 // PXP read request interface initial credit - transoriented.
68449 … 0xd80404UL //Access:RW DataWidth:0x6 // TDIF pass-through command inter…
68450 … 0xd80408UL //Access:RW DataWidth:0x6 // TDIF non_pass-through command inter…
68452 …10UL //Access:RW DataWidth:0x2 // PXP internal write interface initial credit - transoriented.
68453 … 0xd80414UL //Access:RW DataWidth:0x3 // TM interface initial credit - transoriented.
68482 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
68483 …-port: Bit-map indicating which L2 hdrs may appear after the LLC header on this port. This applie…
68484 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
68485 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
68486 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
68487 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
68488 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
68489 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
68490 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
68491 … 0xd804d4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68492 … 0xd804d8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68493 … 0xd804dcUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68494 … 0xd804e0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68495 … 0xd804e4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68496 … 0xd804e8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68497 … 0xd804ecUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68498 … 0xd804f0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68499 … 0xd804f4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68511 … 0xd80524UL //Access:RW DataWidth:0x1 // Per-port: Flag to compar…
68525 …AL_TUNNEL_EXT_TYPE_EN_E5 (0x1<<7) // Enables inclusio…
68526 …BF_REG_SAME_AS_LAST_CONFIG_SAL_TUNNEL_EXT_TYPE_EN_E5_SHIFT 7
68540 …D_CONFIG_SAL_FLEX_UPPER_REGQ_OFFSET_E5 (0x1f<<7) // RegQ offset (wit…
68541 …BF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_SAL_FLEX_UPPER_REGQ_OFFSET_E5_SHIFT 7
68544 …used only if sal_flex_upper_bytes is not 0, and number of bytes selected = 8 - sal_flex_upper_bytes
68550 …/Access:RW DataWidth:0x20 // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in …
68551 …/Access:RW DataWidth:0x20 // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in …
68580 …R_TYPE_7_E5 (0xff<<24) // ipv6 extension uniform header type 7
68622 …IDS_IPV6_EXT_UNIFORM_HDR_TYPE_7_VALID_E5 (0x1<<7) // If set, validate…
68623 …BF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_7_VALID_E5_SHIFT 7
68641 …rder. Reset value is in the order from left to right: tag0; tag1; tag2; tag3; tag4; tag5; llc-snap.
68642 …//Access:RW DataWidth:0x4 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. T…
68663 …DataWidth:0xb // Number of shared BTB 256 byte blocks which can be used by all TC-s in the port.
68666 …y. bits 3:0 hold the TC number from 0 to 7 of the highest priority TC. bits 31:28 hold the TC numb…
68667 …-priority w/ anti-starvation arbiter is a RR arbiter. A value of all ones means no RR slots; i.e. …
68668 …W DataWidth:0x8 // L2 EDPM threshold in 256 byte blocks. Only if all TC-s have allocated bloc…
68669 …s:RW DataWidth:0xb // CPMU threshold in 256 byte blocks. Only if all TC-s in port N have allo…
68670 … DataWidth:0xb // RDMA EDPM threshold in 256 byte blocks. Only if all TC-s have allocated bloc…
68831 …Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 7.
68832 … 0xd80864UL //Access:RW DataWidth:0x5 // Almost full threshold for VOQ 7 in the YSTORM comman…
68833 …ess:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 7 (after ending the c…
68834 … 0xd8086cUL //Access:RC DataWidth:0x20 // Number of commands received on VOQ 7 from YSTORM.
68835 … 0xd80870UL //Access:R DataWidth:0xa // Number of commands in the Y command queue of VOQ 7.
68836 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 7. Reset upon init.
68837 …/Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue of VOQ 7.
68838 …0xd8087cUL //Access:RW DataWidth:0xb // The number of BTB 256 byte blocks guaranteed for VOQ 7
68840 …0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 7
68846 …cess:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 7 in both guaranteed a…
68847 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 7. Reset upon init.
68848 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 7. Reset upon init.
69370 …RD_TH (0x1<<7) // TQ read underflo…
69371 …BF_PB1_REG_INT_STS_TQ_ERROR_RD_TH_SHIFT 7
69389 …_RD_TH (0x1<<7) // This bit masks, …
69390 …BF_PB1_REG_INT_MASK_TQ_ERROR_RD_TH_SHIFT 7
69408 …OR_RD_TH (0x1<<7) // TQ read underflo…
69409 …BF_PB1_REG_INT_STS_WR_TQ_ERROR_RD_TH_SHIFT 7
69427 …ROR_RD_TH (0x1<<7) // TQ read underflo…
69428 …BF_PB1_REG_INT_STS_CLR_TQ_ERROR_RD_TH_SHIFT 7
69449 …EBUG_SELECT (0xf<<7) // Obsolete.
69450 …BF_PB1_REG_CONTROL_DEBUG_SELECT_SHIFT 7
69491 … 0xda2000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
69510 …RD_TH (0x1<<7) // TQ read underflo…
69511 …BF_PB2_REG_INT_STS_TQ_ERROR_RD_TH_SHIFT 7
69529 …_RD_TH (0x1<<7) // This bit masks, …
69530 …BF_PB2_REG_INT_MASK_TQ_ERROR_RD_TH_SHIFT 7
69548 …OR_RD_TH (0x1<<7) // TQ read underflo…
69549 …BF_PB2_REG_INT_STS_WR_TQ_ERROR_RD_TH_SHIFT 7
69567 …ROR_RD_TH (0x1<<7) // TQ read underflo…
69568 …BF_PB2_REG_INT_STS_CLR_TQ_ERROR_RD_TH_SHIFT 7
69589 …EBUG_SELECT (0xf<<7) // Obsolete.
69590 …BF_PB2_REG_CONTROL_DEBUG_SELECT_SHIFT 7
69631 … 0xda6000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
69635 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
69636 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
69783 …IFO_ERROR (0x1<<7) // Queue FIFO error…
69784 …TB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR_SHIFT 7
69816 …FIFO_ERROR (0x1<<7) // This bit masks, …
69817 …TB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR_SHIFT 7
69849 …E_FIFO_ERROR (0x1<<7) // Queue FIFO error…
69850 …TB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR_SHIFT 7
69882 …UE_FIFO_ERROR (0x1<<7) // Queue FIFO error…
69883 …TB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR_SHIFT 7
69953 …_FIFO_ERROR (0x1<<7) // Read packet clie…
69954 …TB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT 7
70018 …P_FIFO_ERROR (0x1<<7) // This bit masks, …
70019 …TB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT 7
70083 …RSP_FIFO_ERROR (0x1<<7) // Read packet clie…
70084 …TB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT 7
70148 …_RSP_FIFO_ERROR (0x1<<7) // Read packet clie…
70149 …TB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT 7
70203 …FIFO_ERROR (0x1<<7) // Link list arbite…
70204 …TB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR_SHIFT 7
70250 …_FIFO_ERROR (0x1<<7) // This bit masks, …
70251 …TB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR_SHIFT 7
70297 …LS_FIFO_ERROR (0x1<<7) // Link list arbite…
70298 …TB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT 7
70344 …RLS_FIFO_ERROR (0x1<<7) // Link list arbite…
70345 …TB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT 7
70401 …T_PTR_FIFO_ERROR (0x1<<7) // Read packet clie…
70402 …TB_REG_INT_STS_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT 7
70466 …RT_PTR_FIFO_ERROR (0x1<<7) // This bit masks, …
70467 …TB_REG_INT_MASK_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT 7
70531 …STRT_PTR_FIFO_ERROR (0x1<<7) // Read packet clie…
70532 …TB_REG_INT_STS_WR_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT 7
70596 …_STRT_PTR_FIFO_ERROR (0x1<<7) // Read packet clie…
70597 …TB_REG_INT_STS_CLR_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT 7
70740 …I_ECC_RF_INT (0x1<<7) // This bit masks, …
70741 …TB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_SHIFT 7
70848 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
70849 …TB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_E5_SHIFT 7
70870 … (0x1<<7) // Enable ECC for memory ecc instance btb.BB_BANK_K…
70871 …TB_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_SHIFT 7
70922 … (0x1<<7) // Set parity only for memory ecc instance btb.BB_BANK…
70923 …TB_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_SHIFT 7
70974 … (0x1<<7) // Record if a correctable error occurred on memory ecc instance …
70975 …TB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_SHIFT 7
71012 …te up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[7].BB_BANK_BB_GEN_IF.i…
71021 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
71022 …04UL //Access:RW DataWidth:0xa // Number of valid bytes in header in 16-bytes resolution. Aft…
71030 …ngth error other way it will continue to work as usual.::s/STOP_LEN_ERR_RST/7/g in Reset Value::s/…
71031 …L_EN/d in Existance. Value for 40G mode (reset value, both BB and K2): 2880 - (34 + 2 + (9600+32)/…
71032 …-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 ::s/NO_DEAD_CYCLE_RST/1/g in …
71034 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71036 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71038 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71040 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71042 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71044 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71046 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71048 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71050 … be written without intra packet dead cycles .B0-NIG main port0; B1-NIG LB port0; B2-NIG main port…
71051 …nism is enabled for the corresponding client. B0-NIG main port0; B1-NIG LB port0; B2-NIG main port…
71052 …is is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is high…
71053 …client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7…
71054 …h multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is high…
71077 …-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropr…
71081 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
71084 …-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropr…
71097 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
71101 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71102 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71103 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71104 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71105 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71106 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71107 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71108 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71109 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71110 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71111 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71112 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71113 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71114 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71115 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71116 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71117 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71118 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71119 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71120 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71121 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71122 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71123 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71124 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71125 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71126 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71127 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
71130 … // Debug register. FIFO counters status of link list arbiter: {rls_fifo[7:4]; prefetch_fifo_1[…
71136 …f the packet arrived it can be sent to the read client. This is because (375-425)/425 is less then…
71141 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
71144 … erad packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1.…
71148 … read packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1.…
71151 …32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[…
71155 …Access:RW DataWidth:0xc // Link list dual port memory that contains per-block descriptor::s/B…
71156 …Access:RW DataWidth:0xd // Link list dual port memory that contains per-block descriptor::s/B…
71190 … (0x1<<31) // When set this bit validates bits 10-0 of this register.
71232 … (0x3fff<<0) // Offset (in 32-bit words) of the mai…
71236 … (0xfff<<20) // Mailbox size in 32-bit words. Default ma…
71239 … (0x3fff<<0) // Offset (in 32-bit words) of the mai…
71243 … (0xfff<<20) // Mailbox size in 32-bit words. Default ma…
71248 …river to alert the MCP. Changing this register updates the corresponding per-PF bit in the MCP Doo…
71266 …taWidth:0x20 // Port mode for GRC Master transactions 0: 1-port mode, 1: 2-port mode, 2: 4-port …
71268 …W DataWidth:0x20 // EPIO mask for signal transitioning from high to low. 1 -> MASK the event
71269 …W DataWidth:0x20 // EPIO mask for signal transitioning from low to high. 1 -> MASK the event
71274 …/ When this bit is written to a 1, the processor will reset as if from power-up state. All "Reset"…
71286 …A (0x1<<7) // When this bit is…
71287 …CP_REG_CPU_MODE_INTERRUPT_ENA_SHIFT 7
71317 …D (0x1<<7) // This bit is set …
71318 …CP_REG_CPU_STATE_ALIGN_HALTED_SHIFT 7
71327 … is each time an interrupt input is asserted, regardless of the interrupt enable bit (bit 7, mode).
71354 …HALTED_MASK (0x1<<7) // This bit enables…
71355 …CP_REG_CPU_EVENT_MASK_ALIGN_HALTED_MASK_SHIFT 7
71366 …nstruction in the decode stage of the pipeline. Bits 31-2 are implemented. '1's written to bits 1-…
71369 …7 in mode register). This register is intended to allow a way to return from an interrupt service …
71377 … (0x3fffffff<<2) // This field sets the 32-bit word on which the…
71380 … (0x7ff<<0) // 11 bit set-1 debug visibility ve…
71384 … (0xf<<12) // 4 bit select for the peek value of the set-1 debug visibility ve…
71386 … (0x7ff<<16) // 11 bit set-2 debug visibility ve…
71390 … (0xf<<28) // 4 bit select for the peek value of the set-2 debug visibility ve…
71399 …/ While the processor is halted, the general purpose processor registers (r0-r31) can be read and …
71402 … (0xffff<<0) // This value is used to specify the bit at the auto-polled address that i…
71404 …xffff<<16) // This value is used to define the register address in MDIO auto-poll transactions. Fo…
71407 …-B0, on the first read of this register when the START_BUSY bit returns to '0', this value, in the…
71417 …ust be read as a '0' before setting to prevent un-predictable results. On chip versions before Tet…
71420 …by the MDIO interface if auto-polling is enabled. The value of this bit is reflected by in the mai…
71427 … (0x1<<1) // If this bit is set, the 32-bit pre-amble will not be generated during au…
71431 … (0x1<<4) // This bit enables auto-polling. When auto-polling is o…
71453 … COMMAND register. This bit must be set to proper value before the link auto-polling function is e…
71476 …arpCore SERDES microcontroller program memory interfaces. This register auto-increments after each…
71521 … 2 PCIE SERDES microcontroller program memory interfaces. This register auto-increments after each…
71542 …address offset for the AVS RBUS program memory interface. This register auto-increments after each…
71547 … (0x1f<<0) // Number of bytes to be transfered in Read or Write operation. Valid lengths are 0-16.
71551 …count>1, additional bytes will be accessed. Address 0 is DataReg0[7:0], Address 7 is DataReg3[3…
71570 …ice ID of the Slave Device. This is a 7-bit field as defined by the I2C spec, but can be written h…
71600 … (0x1<<1) // This bit indicates that in In-Use Error has occured…
71620 … (0x7f<<0) // This is the length of the VDM packet, in 32-bit DWords. 0x0 is an…
71648 …1 (0x1ff<<7) // Reserved for fut…
71649 …CP_REG_P2M_P2M_STATUS_RESERVED1_SHIFT 7
71689 …P2M_LENGTH_FILT_CONFIG_UNUSED0 (0x1<<7) //
71690 …CP_REG_P2M_P2M_LENGTH_FILT_CONFIG_UNUSED0_SHIFT 7
71698 …/Access:R DataWidth:0x20 // Reading this register will give the next 32-bits of the current H…
71707 … 0xe06240UL //Access:R DataWidth:0x20 // 32-bit Packet Data.
71709 … (0x7f<<0) // 7-bit Length from VDM H…
71712 … (0xffff<<0) // 16-bit PCI Requester ID …
71715 … (0xffff<<0) // 16-bit Vendor ID from VD…
71718 … (0xffff<<0) // 16-bit FID from VDM Head…
71720 … 0xe06254UL //Access:R DataWidth:0x20 // 32-bit Vendor Defined DW…
71728 …M_OTHER_HDR_FIELDS_UNUSED1 (0x1ff<<7) //
71729 …CP_REG_P2M_P2M_OTHER_HDR_FIELDS_UNUSED1_SHIFT 7
71730 … (0xff<<16) // This is the 8-bit Tag from VDM Head…
71734 … (0x1<<0) // If this bit is cleared then the look-up is bypassed and th…
71800 … 0xe06328UL //Access:RW DataWidth:0x20 // Reflects the status of page 7.
71906 …//Access:RW DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction hi…
71907 …//Access:RW DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction mi…
71945 … (0x1<<7) // This bit is pass…
71946 …CP_REG_NVM_COMMAND_FIRST_SHIFT 7
71953 …en_cmd to flash device through SPI interface to set Flash device to be write-enabled. Used for the…
71955 …di_cmd to flash device through SPI interface to set Flash device to be write-disabled. Used for th…
71965 …it is set, the 256B page mode is disabled for the next operation. It is self-clearing when both th…
71972 …/ 24 bit address value used in read, write and erase operations. When in bit-bang mode, the bottom…
71980 … (0x1<<2) // Enable pass-thru mode to the byte…
71982 … (0x1<<3) // Enable bit-bang mode to control …
71984 …s "ready". This is automatically interpreted by hardware. This value is self-configured on reset b…
71986 … (0xf<<7) // Divisor used to …
71987 …CP_REG_NVM_CFG1_SPI_CLK_DIV_SHIFT 7
72043 …R3 (0x1<<7) // Write this bit a…
72044 …CP_REG_NVM_SW_ARB_ARB_REQ_CLR3_SHIFT 7
72045 …at point, the next Arb bit will read as 1. At any time, only one of the ARB[7:0] bits will be read…
72064 … (0xffff<<8) // Device ID: Memory type = device_id[15:8] Size = device_id[7:0]
72069 …rface state machine through SPI interface To flash device, and make the flash device write-enabled.
72071 …face state machine through SPI interface To flash device, and make the flash device write-disabled.
72082 …s not used by FLSH hardware. It is only used by software. This value is self-configured on reset b…
72084 … (0x1<<3) // This bit is self-configured on reset b…
72086 … address bit when MODE_256 is not set with Atmel devices. This value is self-configured on reset b…
72088 …or Atmel, this defaults to 1. For ST, this defaults to 0. This value is self-configured on reset b…
72090 …7) // Fast Mode. When this bit is set in ST mode, fast read command is used. In Atmel mode, this b…
72091 …CP_REG_NVM_CFG4_FAST_SHIFT 7
72102 …ng f(SCLK) = f(core_clk)/(2*(SPI_SLOW_CLK_DIV +1)). [Ex: SPI_SLOW_CLK_DIV=0 -> f(SCLK) = f(core…
72104 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72106 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72108 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72110 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72112 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72114 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72116 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72118 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72120 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72122 … 0xe06430UL //Access:RW DataWidth:0x20 // NVM re-configuration registe…
72167 …AR area, it will place the offset from the BAR value in this register and re-try the PCI bus to ma…
72292 …SSIGN_ADDR (0x1<<7) // When this bit is…
72293 …CP_REG_SMBUS_CONFIG_HW_ARP_ASSIGN_ADDR_SHIFT 7
72294 …SMBUS block will respond to ARP that is it to SMBUS Device Default Address (7'b1100001) and reslov…
72296 …SMBUS block will respond to ARP that is it to SMBUS Device Default Address (7'b1100001) and reslov…
72308 … (0x1<<28) // When this bit is '1' the SMBUS block responds to slave address 7'b0000000.
72310 … bit is '1', the SMBUS block is placed into bit-bang mode. SMBUS interface pins are controlled usi…
72330 …SMB_ADDR0 (0x1<<7) // When this bit is…
72331 …CP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR0_SHIFT 7
72377 … (0x1<<28) // When the SMBUS interface is configured for bit-bang mode, this bit c…
72381 … (0x1<<30) // When the SM Bus interface is configured for bit-bang mode, this bit c…
72402 … number of bytes that SMBUS block should read from the slave in Block Write - Block Read Process C…
72416 … has no effect. This bit must be read as a '0' before setting it to prevent un-predictable results.
72431 …as no effect. This bit must be read as a '0' before setting it to prevent un-predictable results. …
72512 … (0x1<<31) // 0 - Byte other then last in an WMBUS transaction …
72575 … (0xff<<24) // UDID_0 byte 7.
72611 … (0xff<<24) // UDID_1 byte 7.
72666 …RR (0x1<<7) // This bit indicat…
72667 …CP_REG_FRM_BMB_FIFO_STATUS_ERR_SHIFT 7
72684 … processor. This can be modified at any time and may be used for processor-to-processor communicat…
72700 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
72702 … (0x1<<7) // Enable for input full from pxp-HW …
72703 …SDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT 7
72704 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
72706 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
72750 … (0x1<<7) // Enable for output data to pxp-HW i…
72751 …SDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT 7
72800 … (0x1<<7) // This bit should be set to disable the PXP-Async interface …
72801 …SDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT 7
72815 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
72821 …WAIT_ERROR (0x1<<7) // INT_ram wait fif…
72822 …SDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT 7
72865 … (0x1<<29) // Last-cycle indication not …
72884 …_WAIT_ERROR (0x1<<7) // This bit masks, …
72885 …SDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT 7
72941 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
72947 …AM_WAIT_ERROR (0x1<<7) // INT_ram wait fif…
72948 …SDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT 7
72991 …E5 (0x1<<29) // Last-cycle indication not …
73004 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73010 …RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fif…
73011 …SDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT 7
73054 …_E5 (0x1<<29) // Last-cycle indication not …
73081 …_I_MEM_PRTY (0x1<<7) // This bit masks, …
73082 …SDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT 7
73100 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
73101 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
73102 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
73104 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
73107 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
73127 …re-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode bit where 0=nor…
73204 … 0xf82000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73206 … 0xf82400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
73208 … 0xf82800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
73210 … 0xf82c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
73212 … 0xf83000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
73214 … 0xf83400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
73216 … 0xf83800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
73218 … 0xf83c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
73220 … 0xf84000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
73241 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
73243 … (0x1<<7) // Enable for input full from pxp-HW …
73244 …SDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT 7
73245 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
73247 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73291 … (0x1<<7) // Enable for output data to pxp-HW i…
73292 …SDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT 7
73341 … (0x1<<7) // This bit should be set to disable the PXP-Async interface …
73342 …SDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT 7
73356 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73362 …WAIT_ERROR (0x1<<7) // INT_ram wait fif…
73363 …SDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT 7
73406 … (0x1<<29) // Last-cycle indication not …
73425 …_WAIT_ERROR (0x1<<7) // This bit masks, …
73426 …SDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT 7
73482 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73488 …AM_WAIT_ERROR (0x1<<7) // INT_ram wait fif…
73489 …SDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT 7
73532 …E5 (0x1<<29) // Last-cycle indication not …
73545 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73551 …RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fif…
73552 …SDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT 7
73595 …_E5 (0x1<<29) // Last-cycle indication not …
73622 …_I_MEM_PRTY (0x1<<7) // This bit masks, …
73623 …SDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT 7
73637 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
73638 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
73639 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
73641 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
73644 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
73665 …re-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode bit where 0=nor…
73742 … 0xf92000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73744 … 0xf92400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
73746 … 0xf92800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
73748 … 0xf92c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
73750 … 0xf93000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
73752 … 0xf93400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
73754 … 0xf93800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
73756 … 0xf93c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
73758 … 0xf94000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
73779 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
73781 … (0x1<<7) // Enable for input full from pxp-HW …
73782 …SDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT 7
73783 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
73785 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73829 … (0x1<<7) // Enable for output data to pxp-HW i…
73830 …SDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT 7
73879 … (0x1<<7) // This bit should be set to disable the PXP-Async interface …
73880 …SDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT 7
73894 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73900 …WAIT_ERROR (0x1<<7) // INT_ram wait fif…
73901 …SDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT 7
73944 … (0x1<<29) // Last-cycle indication not …
73963 …_WAIT_ERROR (0x1<<7) // This bit masks, …
73964 …SDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT 7
74020 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74026 …AM_WAIT_ERROR (0x1<<7) // INT_ram wait fif…
74027 …SDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT 7
74070 …E5 (0x1<<29) // Last-cycle indication not …
74083 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74089 …RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fif…
74090 …SDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT 7
74133 …_E5 (0x1<<29) // Last-cycle indication not …
74162 …_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
74163 …SDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5_SHIFT 7
74172 …_I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, …
74173 …SDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT 7
74199 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
74200 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
74201 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
74203 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
74206 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
74227 …re-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode bit where 0=nor…
74304 … 0xfa2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74306 … 0xfa2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
74308 … 0xfa2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
74310 … 0xfa2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
74312 … 0xfa3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
74314 … 0xfa3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
74316 … 0xfa3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
74318 … 0xfa3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
74320 … 0xfa4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
74341 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
74343 … (0x1<<7) // Enable for input full from pxp-HW …
74344 …SDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT 7
74345 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
74347 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74391 … (0x1<<7) // Enable for output data to pxp-HW i…
74392 …SDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT 7
74441 … (0x1<<7) // This bit should be set to disable the PXP-Async interface …
74442 …SDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT 7
74456 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74462 …WAIT_ERROR (0x1<<7) // INT_ram wait fif…
74463 …SDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT 7
74506 … (0x1<<29) // Last-cycle indication not …
74525 …_WAIT_ERROR (0x1<<7) // This bit masks, …
74526 …SDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT 7
74582 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74588 …AM_WAIT_ERROR (0x1<<7) // INT_ram wait fif…
74589 …SDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT 7
74632 …E5 (0x1<<29) // Last-cycle indication not …
74645 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74651 …RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fif…
74652 …SDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT 7
74695 …_E5 (0x1<<29) // Last-cycle indication not …
74724 …_I_MEM_PRTY (0x1<<7) // This bit masks, …
74725 …SDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT 7
74741 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
74742 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
74743 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
74745 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
74748 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
74768 …re-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode bit where 0=nor…
74845 … 0xfb2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74847 … 0xfb2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
74849 … 0xfb2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
74851 … 0xfb2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
74853 … 0xfb3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
74855 … 0xfb3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
74857 … 0xfb3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
74859 … 0xfb3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
74861 … 0xfb4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
74882 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
74884 … (0x1<<7) // Enable for input full from pxp-HW …
74885 …SDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT 7
74886 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
74888 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74932 … (0x1<<7) // Enable for output data to pxp-HW i…
74933 …SDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT 7
74982 … (0x1<<7) // This bit should be set to disable the PXP-Async interface …
74983 …SDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT 7
74997 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75003 …WAIT_ERROR (0x1<<7) // INT_ram wait fif…
75004 …SDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT 7
75047 … (0x1<<29) // Last-cycle indication not …
75066 …_WAIT_ERROR (0x1<<7) // This bit masks, …
75067 …SDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT 7
75123 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75129 …AM_WAIT_ERROR (0x1<<7) // INT_ram wait fif…
75130 …SDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT 7
75173 …E5 (0x1<<29) // Last-cycle indication not …
75186 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75192 …RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fif…
75193 …SDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT 7
75236 …_E5 (0x1<<29) // Last-cycle indication not …
75267 …_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
75268 …SDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5_SHIFT 7
75271 …_I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, …
75272 …SDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT 7
75310 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
75311 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
75312 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
75314 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
75317 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
75339 …re-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode bit where 0=nor…
75416 … 0xfc2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75418 … 0xfc2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
75420 … 0xfc2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
75422 … 0xfc2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
75424 … 0xfc3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
75426 … 0xfc3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
75428 … 0xfc3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
75430 … 0xfc3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
75432 … 0xfc4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
75453 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
75455 … (0x1<<7) // Enable for input full from pxp-HW …
75456 …SDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT 7
75457 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
75459 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
75503 … (0x1<<7) // Enable for output data to pxp-HW i…
75504 …SDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT 7
75553 … (0x1<<7) // This bit should be set to disable the PXP-Async interface …
75554 …SDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT 7
75568 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75574 …WAIT_ERROR (0x1<<7) // INT_ram wait fif…
75575 …SDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT 7
75618 … (0x1<<29) // Last-cycle indication not …
75637 …_WAIT_ERROR (0x1<<7) // This bit masks, …
75638 …SDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT 7
75694 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75700 …AM_WAIT_ERROR (0x1<<7) // INT_ram wait fif…
75701 …SDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT 7
75744 …E5 (0x1<<29) // Last-cycle indication not …
75757 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75763 …RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fif…
75764 …SDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT 7
75807 …_E5 (0x1<<29) // Last-cycle indication not …
75834 …_I_MEM_PRTY (0x1<<7) // This bit masks, …
75835 …SDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT 7
75853 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
75854 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
75855 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
75857 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
75860 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
75881 …re-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode bit where 0=nor…
75958 … 0xfd2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75960 … 0xfd2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
75962 … 0xfd2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
75964 … 0xfd2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
75966 … 0xfd3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
75968 … 0xfd3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
75970 … 0xfd3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
75972 … 0xfd3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
75974 … 0xfd4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
75982 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
76026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76027 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76029 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76031 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76033 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76035 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76037 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76039 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76041 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76042 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76043 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76044 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76045 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76046 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76047 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76048 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76049 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76050 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76051 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76052 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76053 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76054 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76055 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76056 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76057 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76058 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76059 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76060 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76061 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76062 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76063 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76064 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76065 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76066 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76067 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76068 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76069 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76070 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76071 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76073 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76074 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76090 …L_ERR (0x1<<7) // Write to full YS…
76091 …CM_REG_INT_STS_0_IS_YSDM_OVFL_ERR_SHIFT 7
76127 …FL_ERR (0x1<<7) // This bit masks, …
76128 …CM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR_SHIFT 7
76164 …OVFL_ERR (0x1<<7) // Write to full YS…
76165 …CM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR_SHIFT 7
76201 …_OVFL_ERR (0x1<<7) // Write to full YS…
76202 …CM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR_SHIFT 7
76238 …L_ERR (0x1<<7) // Write to full QM…
76239 …CM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_SHIFT 7
76262 … (0x1<<19) // In-process Table overflo…
76289 …FL_ERR (0x1<<7) // This bit masks, …
76290 …CM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_SHIFT 7
76340 …OVFL_ERR (0x1<<7) // Write to full QM…
76341 …CM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_SHIFT 7
76364 … (0x1<<19) // In-process Table overflo…
76391 …_OVFL_ERR (0x1<<7) // Write to full QM…
76392 …CM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_SHIFT 7
76415 … (0x1<<19) // In-process Table overflo…
76442 …NT_ILLEG_PQNUM (0x1<<7) // Access to illega…
76443 …CM_REG_INT_STS_2_QM_ACT_ST_CNT_ILLEG_PQNUM_SHIFT 7
76459 …CNT_ILLEG_PQNUM (0x1<<7) // This bit masks, …
76460 …CM_REG_INT_MASK_2_QM_ACT_ST_CNT_ILLEG_PQNUM_SHIFT 7
76476 …T_CNT_ILLEG_PQNUM (0x1<<7) // Access to illega…
76477 …CM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_ILLEG_PQNUM_SHIFT 7
76493 …ST_CNT_ILLEG_PQNUM (0x1<<7) // Access to illega…
76494 …CM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_ILLEG_PQNUM_SHIFT 7
76514 …I_ECC_0_RF_INT_E5 (0x1<<7) // This bit masks, …
76515 …CM_REG_PRTY_MASK_H_0_MEM033_I_ECC_0_RF_INT_E5_SHIFT 7
76516 …I_ECC_1_RF_INT_K2 (0x1<<7) // This bit masks, …
76517 …CM_REG_PRTY_MASK_H_0_MEM033_I_ECC_1_RF_INT_K2_SHIFT 7
76616 …I_ECC_1_RF_INT_BB (0x1<<7) // This bit masks, …
76617 …CM_REG_PRTY_MASK_H_0_MEM032_I_ECC_1_RF_INT_BB_SHIFT 7
76649 …I_MEM_PRTY_K2_E5 (0x1<<7) // This bit masks, …
76650 …CM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_K2_E5_SHIFT 7
76651 …I_MEM_PRTY_BB (0x1<<7) // This bit masks, …
76652 …CM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_SHIFT 7
76688 …33_I_ECC_0_EN_E5 (0x1<<7) // Enable ECC for m…
76689 …CM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_0_EN_E5_SHIFT 7
76690 …33_I_ECC_1_EN_K2 (0x1<<7) // Enable ECC for m…
76691 …CM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_1_EN_K2_SHIFT 7
76702 …32_I_ECC_1_EN_BB (0x1<<7) // Enable ECC for m…
76703 …CM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_1_EN_BB_SHIFT 7
76725 …_MEM033_I_ECC_0_PRTY_E5 (0x1<<7) // Set parity only …
76726 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_0_PRTY_E5_SHIFT 7
76727 …_MEM033_I_ECC_1_PRTY_K2 (0x1<<7) // Set parity only …
76728 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_1_PRTY_K2_SHIFT 7
76739 …_MEM032_I_ECC_1_PRTY_BB (0x1<<7) // Set parity only …
76740 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_1_PRTY_BB_SHIFT 7
76762 …ED_0_MEM033_I_ECC_0_CORRECT_E5 (0x1<<7) // Record if a corr…
76763 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_0_CORRECT_E5_SHIFT 7
76764 …ED_0_MEM033_I_ECC_1_CORRECT_K2 (0x1<<7) // Record if a corr…
76765 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_1_CORRECT_K2_SHIFT 7
76776 …ED_0_MEM032_I_ECC_1_CORRECT_BB (0x1<<7) // Record if a corr…
76777 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_1_CORRECT_BB_SHIFT 7
76781 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
76783 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76784 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76785 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76786 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76787 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76788 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76789 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76790 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76791 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76792 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76793 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76794 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76795 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76796 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76797 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76798 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76799 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76800 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76801 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76802 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76803 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76804 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76805 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76806 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76807 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76808 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76810 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76812 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76814 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76816 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76817 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76818 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76819 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76820 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76821 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76822 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76823 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76824 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76825 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76826 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76827 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76828 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76829 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76830 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76831 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76832 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76833 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76834 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76835 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76836 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76849 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76850 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76851 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76852 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76853 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76854 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76855 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
76856 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76857 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76858 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76859 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76860 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76861 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76862 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76863 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76864 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76865 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76866 … 0x1000680UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
76868 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
76879 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
76880 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
76881 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
76883 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
76888 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76889 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76890 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76891 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
76905 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76906 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76907 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76908 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76909 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76910 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76911 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76912 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76913 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76914 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76915 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76916 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76917 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76918 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76919 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76920 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76921 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76922 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76923 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76924 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76925 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76926 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76927 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76928 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76942 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
76943 … 0x1000904UL //Access:RW DataWidth:0xa // [9]: PQ Type (0-Other PQ; 1-TX PQ); if bit[…
76944 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
76945 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
76946 … 0x1000a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
76947 … 0x1000a10UL //Access:R DataWidth:0x1 // In-process Table almost …
76969 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
76970 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
76971 …th:0x5 // QM output initial credit (XCM TX queues). Max credit available - 16.Write writes the …
76972 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
77008 …tive counter overflow/uder-run. Is reset on read. [0] - If set, there was under-run; [1] - If set,…
77025 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
77028 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
77030 …ess:R DataWidth:0x20 // Debug read from XSEM Input stage buffer with 32-bits granularity. Rea…
77032 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
77034 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
77036 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
77038 …ess:R DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Rea…
77040 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
77042 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
77043 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
77044 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
77050 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
77053 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
77247 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77248 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77249 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77250 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77251 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77252 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77253 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77254 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77255 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77256 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77257 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77258 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77259 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77260 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77261 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77262 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77273 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
77283 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
77284 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
77286 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
77288 …alue. [28:20] PQ number. [29:29] Reserved. [31:30] Command type: 0 - SET; 1 - DEC; 2 - INC; The ad…
77291 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
77333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77334 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77336 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77338 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77354 …L_ERR (0x1<<7) // Write to full XY…
77355 …CM_REG_INT_STS_0_IS_XYLD_OVFL_ERR_SHIFT 7
77385 …FL_ERR (0x1<<7) // This bit masks, …
77386 …CM_REG_INT_MASK_0_IS_XYLD_OVFL_ERR_SHIFT 7
77416 …OVFL_ERR (0x1<<7) // Write to full XY…
77417 …CM_REG_INT_STS_WR_0_IS_XYLD_OVFL_ERR_SHIFT 7
77447 …_OVFL_ERR (0x1<<7) // Write to full XY…
77448 …CM_REG_INT_STS_CLR_0_IS_XYLD_OVFL_ERR_SHIFT 7
77478 …R_ERR0 (0x1<<7) // Read from empty …
77479 …CM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_SHIFT 7
77492 … (0x1<<14) // In-process Table overflo…
77525 …ER_ERR0 (0x1<<7) // This bit masks, …
77526 …CM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_SHIFT 7
77572 …NDER_ERR0 (0x1<<7) // Read from empty …
77573 …CM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_SHIFT 7
77586 … (0x1<<14) // In-process Table overflo…
77619 …UNDER_ERR0 (0x1<<7) // Read from empty …
77620 …CM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_SHIFT 7
77633 … (0x1<<14) // In-process Table overflo…
77678 …I_ECC_1_RF_INT_BB_K2 (0x1<<7) // This bit masks, …
77679 …CM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT 7
77682 …I_ECC_RF_INT_E5 (0x1<<7) // This bit masks, …
77683 …CM_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_E5_SHIFT 7
77865 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
77866 …CM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 7
77886 …05_I_ECC_1_EN_BB_K2 (0x1<<7) // Enable ECC for m…
77887 …CM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT 7
77890 …06_I_ECC_EN_E5 (0x1<<7) // Enable ECC for m…
77891 …CM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_E5_SHIFT 7
77936 …_MEM005_I_ECC_1_PRTY_BB_K2 (0x1<<7) // Set parity only …
77937 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT 7
77940 …_MEM006_I_ECC_PRTY_E5 (0x1<<7) // Set parity only …
77941 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_E5_SHIFT 7
77986 …ED_0_MEM005_I_ECC_1_CORRECT_BB_K2 (0x1<<7) // Record if a corr…
77987 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT 7
77990 …ED_0_MEM006_I_ECC_CORRECT_E5 (0x1<<7) // Record if a corr…
77991 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_E5_SHIFT 7
78022 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
78072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78073 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78074 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78075 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78076 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78077 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78078 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78079 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78080 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78081 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78091 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78092 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78093 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78094 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78095 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78096 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78097 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
78098 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78099 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78100 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78101 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78102 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78103 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78104 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78105 … 0x1080664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
78107 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78108 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78121 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
78122 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
78123 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
78125 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
78130 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78131 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78132 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78133 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
78150 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78151 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78152 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78153 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78154 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78155 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78156 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78157 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78158 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78159 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78160 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78161 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78162 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78163 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78164 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78165 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78166 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78167 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78168 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78169 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78170 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78171 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78172 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78173 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78213 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
78214 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
78219 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78220 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78221 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78222 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78223 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78224 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78225 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78226 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78227 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78228 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78229 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78230 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78231 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78232 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78233 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78242 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
78243 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
78244 … 0x1080a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
78245 … 0x1080a10UL //Access:R DataWidth:0x1 // In-process Table almost …
78269 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
78270 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
78271 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
78272 …1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the i…
78273 …h:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the in…
78312 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
78314 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
78316 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
78318 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
78320 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
78321 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
78322 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
78323 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
78324 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
78333 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
78336 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
78516 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
78517 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
78519 …ess:R DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Rea…
78520 …ess:R DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Rea…
78525 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
78526 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
78529 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78535 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
78536 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
78539 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
78564 …L_ERR_E5 (0x1<<7) // Write to full YP…
78565 …CM_REG_INT_STS_0_IS_YPLD_OVFL_ERR_E5_SHIFT 7
78583 …FL_ERR_E5 (0x1<<7) // This bit masks, …
78584 …CM_REG_INT_MASK_0_IS_YPLD_OVFL_ERR_E5_SHIFT 7
78602 …OVFL_ERR_E5 (0x1<<7) // Write to full YP…
78603 …CM_REG_INT_STS_WR_0_IS_YPLD_OVFL_ERR_E5_SHIFT 7
78621 …_OVFL_ERR_E5 (0x1<<7) // Write to full YP…
78622 …CM_REG_INT_STS_CLR_0_IS_YPLD_OVFL_ERR_E5_SHIFT 7
78646 …R_ERR2_BB_K2 (0x1<<7) // Read from empty …
78647 …CM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_BB_K2_SHIFT 7
78656 …R_ERR3_E5 (0x1<<7) // Read from empty …
78657 …CM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_E5_SHIFT 7
78658 …K2 (0x1<<10) // In-process Table overflo…
78660 … (0x1<<8) // In-process Table overflo…
78699 …ER_ERR2_BB_K2 (0x1<<7) // This bit masks, …
78700 …CM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_BB_K2_SHIFT 7
78709 …ER_ERR3_E5 (0x1<<7) // This bit masks, …
78710 …CM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_E5_SHIFT 7
78752 …NDER_ERR2_BB_K2 (0x1<<7) // Read from empty …
78753 …CM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_BB_K2_SHIFT 7
78762 …NDER_ERR3_E5 (0x1<<7) // Read from empty …
78763 …CM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_E5_SHIFT 7
78764 …BB_K2 (0x1<<10) // In-process Table overflo…
78766 …_E5 (0x1<<8) // In-process Table overflo…
78805 …UNDER_ERR2_BB_K2 (0x1<<7) // Read from empty …
78806 …CM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_BB_K2_SHIFT 7
78815 …UNDER_ERR3_E5 (0x1<<7) // Read from empty …
78816 …CM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_E5_SHIFT 7
78817 …_BB_K2 (0x1<<10) // In-process Table overflo…
78819 …L_E5 (0x1<<8) // In-process Table overflo…
78880 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
78881 …CM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5_SHIFT 7
78884 …I_MEM_PRTY_K2 (0x1<<7) // This bit masks, …
78885 …CM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT 7
78888 …I_MEM_PRTY_BB (0x1<<7) // This bit masks, …
78889 …CM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_SHIFT 7
78998 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
79003 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79004 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79005 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79006 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79007 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79008 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79009 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
79010 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79011 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79012 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79013 … 0x110063cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
79015 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
79025 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
79026 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
79027 … DataWidth:0x2 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
79029 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
79034 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79035 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79036 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79037 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
79052 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
79053 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
79054 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
79055 … 0x1100a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
79056 … 0x1100a10UL //Access:R DataWidth:0x1 // In-process Table almost …
79060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
79076 …ess:R DataWidth:0x20 // Debug read from PSEM Input stage buffer with 32-bits granularity. Rea…
79079 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
79081 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
79082 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
79085 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
79087 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
79123 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
79124 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
79131 …ess:R DataWidth:0x20 // Debug read from YPLD Input stage buffer with 32-bits granularity. Rea…
79133 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
79135 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
79177 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79178 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79179 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79180 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79182 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79184 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79186 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79187 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79188 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79189 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79190 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79191 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79192 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79193 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79194 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79195 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79196 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79197 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79198 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79199 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79219 …L_ERR_E5 (0x1<<7) // Write to full PS…
79220 …CM_REG_INT_STS_0_IS_PSDM_OVFL_ERR_E5_SHIFT 7
79231 …L_ERR_BB_K2 (0x1<<7) // Write to full Ys…
79232 …CM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_BB_K2_SHIFT 7
79258 …FL_ERR_E5 (0x1<<7) // This bit masks, …
79259 …CM_REG_INT_MASK_0_IS_PSDM_OVFL_ERR_E5_SHIFT 7
79270 …FL_ERR_BB_K2 (0x1<<7) // This bit masks, …
79271 …CM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_BB_K2_SHIFT 7
79297 …OVFL_ERR_E5 (0x1<<7) // Write to full PS…
79298 …CM_REG_INT_STS_WR_0_IS_PSDM_OVFL_ERR_E5_SHIFT 7
79309 …OVFL_ERR_BB_K2 (0x1<<7) // Write to full Ys…
79310 …CM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_BB_K2_SHIFT 7
79336 …_OVFL_ERR_E5 (0x1<<7) // Write to full PS…
79337 …CM_REG_INT_STS_CLR_0_IS_PSDM_OVFL_ERR_E5_SHIFT 7
79348 …_OVFL_ERR_BB_K2 (0x1<<7) // Write to full Ys…
79349 …CM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_BB_K2_SHIFT 7
79371 …ERR (0x1<<7) // Write to full TM…
79372 …CM_REG_INT_STS_1_IS_TM_OVFL_ERR_SHIFT 7
79399 … (0x1<<21) // In-process Table overflo…
79440 …_ERR (0x1<<7) // This bit masks, …
79441 …CM_REG_INT_MASK_1_IS_TM_OVFL_ERR_SHIFT 7
79509 …FL_ERR (0x1<<7) // Write to full TM…
79510 …CM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR_SHIFT 7
79537 … (0x1<<21) // In-process Table overflo…
79578 …VFL_ERR (0x1<<7) // Write to full TM…
79579 …CM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR_SHIFT 7
79606 … (0x1<<21) // In-process Table overflo…
79659 …I_ECC_1_RF_INT_E5 (0x1<<7) // This bit masks, …
79660 …CM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_E5_SHIFT 7
79769 …I_ECC_0_RF_INT_K2 (0x1<<7) // This bit masks, …
79770 …CM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_K2_SHIFT 7
79811 …I_ECC_0_RF_INT_BB (0x1<<7) // This bit masks, …
79812 …CM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT_BB_SHIFT 7
79838 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
79839 …CM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5_SHIFT 7
79861 …06_I_ECC_1_EN_E5 (0x1<<7) // Enable ECC for m…
79862 …CM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_E5_SHIFT 7
79877 …24_I_ECC_0_EN_K2 (0x1<<7) // Enable ECC for m…
79878 …CM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN_K2_SHIFT 7
79887 …23_I_ECC_0_EN_BB (0x1<<7) // Enable ECC for m…
79888 …CM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_0_EN_BB_SHIFT 7
79906 …_MEM006_I_ECC_1_PRTY_E5 (0x1<<7) // Set parity only …
79907 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_E5_SHIFT 7
79922 …_MEM024_I_ECC_0_PRTY_K2 (0x1<<7) // Set parity only …
79923 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY_K2_SHIFT 7
79932 …_MEM023_I_ECC_0_PRTY_BB (0x1<<7) // Set parity only …
79933 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_0_PRTY_BB_SHIFT 7
79951 …ED_0_MEM006_I_ECC_1_CORRECT_E5 (0x1<<7) // Record if a corr…
79952 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_E5_SHIFT 7
79967 …ED_0_MEM024_I_ECC_0_CORRECT_K2 (0x1<<7) // Record if a corr…
79968 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT_K2_SHIFT 7
79977 …ED_0_MEM023_I_ECC_0_CORRECT_BB (0x1<<7) // Record if a corr…
79978 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_0_CORRECT_BB_SHIFT 7
79982 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
80024 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80025 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80027 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80029 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80031 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80033 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80035 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80037 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80039 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80041 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80042 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80043 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80053 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80054 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80055 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80056 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80057 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80058 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80059 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
80060 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80061 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80062 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80063 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80064 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80065 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80066 … 0x1180664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
80068 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80069 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80082 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
80083 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
80084 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
80086 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
80091 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80092 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80093 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80094 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
80111 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80112 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80113 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80114 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80115 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80116 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80117 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80118 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80119 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80120 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80121 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80122 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80123 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80124 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80125 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80126 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80127 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80128 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80129 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80130 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80131 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80132 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80133 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80134 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80174 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
80175 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
80180 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80182 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80184 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80194 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
80195 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
80196 … 0x1180a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
80197 … 0x1180a10UL //Access:R DataWidth:0x1 // In-process Table almost …
80223 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
80224 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
80225 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
80226 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
80264 …ess:R DataWidth:0x20 // Debug read from TSEM Input stage buffer with 32-bits granularity. Rea…
80267 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
80269 …cess:R DataWidth:0x20 // Debug read from PRS Input stage buffer with 32-bits granularity. Rea…
80271 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
80273 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
80275 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
80276 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
80277 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
80278 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
80279 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
80288 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
80291 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
80495 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
80496 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
80503 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
80510 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
80520 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
80521 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
80528 …ess:R DataWidth:0x20 // Debug read from PTLD Input stage buffer with 32-bits granularity. Rea…
80530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80535 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80536 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80537 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80538 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80539 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80540 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80541 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80542 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80543 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80544 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80545 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80546 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
80549 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
80591 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80592 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80593 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80594 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80595 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80596 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80612 …L_ERR_E5 (0x1<<7) // Write to full TS…
80613 …CM_REG_INT_STS_0_IS_TSDM_OVFL_ERR_E5_SHIFT 7
80620 …L_ERR_BB_K2 (0x1<<7) // Write to full US…
80621 …CM_REG_INT_STS_0_IS_USDM_OVFL_ERR_BB_K2_SHIFT 7
80667 …FL_ERR_E5 (0x1<<7) // This bit masks, …
80668 …CM_REG_INT_MASK_0_IS_TSDM_OVFL_ERR_E5_SHIFT 7
80675 …FL_ERR_BB_K2 (0x1<<7) // This bit masks, …
80676 …CM_REG_INT_MASK_0_IS_USDM_OVFL_ERR_BB_K2_SHIFT 7
80722 …OVFL_ERR_E5 (0x1<<7) // Write to full TS…
80723 …CM_REG_INT_STS_WR_0_IS_TSDM_OVFL_ERR_E5_SHIFT 7
80730 …OVFL_ERR_BB_K2 (0x1<<7) // Write to full US…
80731 …CM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR_BB_K2_SHIFT 7
80777 …_OVFL_ERR_E5 (0x1<<7) // Write to full TS…
80778 …CM_REG_INT_STS_CLR_0_IS_TSDM_OVFL_ERR_E5_SHIFT 7
80785 …_OVFL_ERR_BB_K2 (0x1<<7) // Write to full US…
80786 …CM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR_BB_K2_SHIFT 7
80832 …_ERR0 (0x1<<7) // Write to full GR…
80833 …CM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_SHIFT 7
80848 … (0x1<<15) // In-process Table overflo…
80885 …L_ERR0 (0x1<<7) // This bit masks, …
80886 …CM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_SHIFT 7
80938 …VFL_ERR0 (0x1<<7) // Write to full GR…
80939 …CM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_SHIFT 7
80954 … (0x1<<15) // In-process Table overflo…
80991 …OVFL_ERR0 (0x1<<7) // Write to full GR…
80992 …CM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_SHIFT 7
81007 … (0x1<<15) // In-process Table overflo…
81056 …I_ECC_0_RF_INT_E5 (0x1<<7) // This bit masks, …
81057 …CM_REG_PRTY_MASK_H_0_MEM031_I_ECC_0_RF_INT_E5_SHIFT 7
81140 …I_ECC_1_RF_INT_BB_K2 (0x1<<7) // This bit masks, …
81141 …CM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT_BB_K2_SHIFT 7
81179 …I_MEM_PRTY_E5 (0x1<<7) // This bit masks, …
81180 …CM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5_SHIFT 7
81204 …31_I_ECC_0_EN_E5 (0x1<<7) // Enable ECC for m…
81205 …CM_REG_MEM_ECC_ENABLE_0_MEM031_I_ECC_0_EN_E5_SHIFT 7
81216 …25_I_ECC_1_EN_BB_K2 (0x1<<7) // Enable ECC for m…
81217 …CM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_1_EN_BB_K2_SHIFT 7
81235 …_MEM031_I_ECC_0_PRTY_E5 (0x1<<7) // Set parity only …
81236 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM031_I_ECC_0_PRTY_E5_SHIFT 7
81247 …_MEM025_I_ECC_1_PRTY_BB_K2 (0x1<<7) // Set parity only …
81248 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_1_PRTY_BB_K2_SHIFT 7
81266 …ED_0_MEM031_I_ECC_0_CORRECT_E5 (0x1<<7) // Record if a corr…
81267 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM031_I_ECC_0_CORRECT_E5_SHIFT 7
81278 …ED_0_MEM025_I_ECC_1_CORRECT_BB_K2 (0x1<<7) // Record if a corr…
81279 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_1_CORRECT_BB_K2_SHIFT 7
81283 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
81333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81334 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81336 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81338 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81339 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81340 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81341 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81342 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81352 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81353 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81354 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81355 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81356 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81357 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81358 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
81359 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81360 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81361 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81362 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81363 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81364 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81365 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81366 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81367 … 0x120066cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
81369 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81370 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81383 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
81384 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
81385 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
81387 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
81392 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81393 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81394 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81395 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
81412 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81413 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81414 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81415 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81416 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81417 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81418 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81419 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81420 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81421 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81422 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81423 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81424 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81425 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81426 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81427 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81428 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81429 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81430 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81431 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81432 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81433 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81434 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81435 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81475 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
81476 …7 (REGQ) complies to 320 LTIDs. Maximum context size per LTID is 20. Maximum number of LTIDs allow…
81481 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81482 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81483 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81484 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81485 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81486 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81487 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81488 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81497 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
81498 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
81499 … 0x1200a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
81500 … 0x1200a10UL //Access:R DataWidth:0x1 // In-process Table almost …
81524 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
81525 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
81526 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
81527 …1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the i…
81528 …h:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the in…
81568 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
81571 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
81573 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
81575 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
81577 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
81579 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
81580 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
81581 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
81582 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
81583 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
81592 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
81595 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
81765 …ess:R DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Rea…
81766 …ess:R DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Rea…
81774 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
81781 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
81793 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
81794 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
81804 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
81805 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
81808 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81810 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81812 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81814 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81816 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
81817 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
81820 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
81866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81867 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81868 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81869 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81870 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81871 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81872 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81873 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81874 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81875 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81876 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81877 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81878 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81879 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81880 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81881 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81897 …L_ERR (0x1<<7) // Write to full US…
81898 …CM_REG_INT_STS_0_IS_USDM_OVFL_ERR_SHIFT 7
81938 …FL_ERR (0x1<<7) // This bit masks, …
81939 …CM_REG_INT_MASK_0_IS_USDM_OVFL_ERR_SHIFT 7
81979 …OVFL_ERR (0x1<<7) // Write to full US…
81980 …CM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR_SHIFT 7
82020 …_OVFL_ERR (0x1<<7) // Write to full US…
82021 …CM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR_SHIFT 7
82075 …L_ERR_E5 (0x1<<7) // Write to full QM…
82076 …CM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_E5_SHIFT 7
82077 …ER_ERR_BB_K2 (0x1<<7) // Read from empty …
82078 …CM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_BB_K2_SHIFT 7
82121 …K2 (0x1<<18) // In-process Table overflo…
82123 … (0x1<<19) // In-process Table overflo…
82194 …FL_ERR_E5 (0x1<<7) // This bit masks, …
82195 …CM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_E5_SHIFT 7
82196 …DER_ERR_BB_K2 (0x1<<7) // This bit masks, …
82197 …CM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_BB_K2_SHIFT 7
82313 …OVFL_ERR_E5 (0x1<<7) // Write to full QM…
82314 …CM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_E5_SHIFT 7
82315 …UNDER_ERR_BB_K2 (0x1<<7) // Read from empty …
82316 …CM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_BB_K2_SHIFT 7
82359 …BB_K2 (0x1<<18) // In-process Table overflo…
82361 …E5 (0x1<<19) // In-process Table overflo…
82432 …_OVFL_ERR_E5 (0x1<<7) // Write to full QM…
82433 …CM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_E5_SHIFT 7
82434 …_UNDER_ERR_BB_K2 (0x1<<7) // Read from empty …
82435 …CM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_BB_K2_SHIFT 7
82478 …_BB_K2 (0x1<<18) // In-process Table overflo…
82480 …_E5 (0x1<<19) // In-process Table overflo…
82549 …I_ECC_1_RF_INT_E5 (0x1<<7) // This bit masks, …
82550 …CM_REG_PRTY_MASK_H_0_MEM008_I_ECC_1_RF_INT_E5_SHIFT 7
82641 …I_ECC_1_RF_INT_BB_K2 (0x1<<7) // This bit masks, …
82642 …CM_REG_PRTY_MASK_H_0_MEM007_I_ECC_1_RF_INT_BB_K2_SHIFT 7
82699 …08_I_ECC_1_EN_E5 (0x1<<7) // Enable ECC for m…
82700 …CM_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_1_EN_E5_SHIFT 7
82719 …07_I_ECC_1_EN_BB_K2 (0x1<<7) // Enable ECC for m…
82720 …CM_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_1_EN_BB_K2_SHIFT 7
82740 …_MEM008_I_ECC_1_PRTY_E5 (0x1<<7) // Set parity only …
82741 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_1_PRTY_E5_SHIFT 7
82760 …_MEM007_I_ECC_1_PRTY_BB_K2 (0x1<<7) // Set parity only …
82761 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_1_PRTY_BB_K2_SHIFT 7
82781 …ED_0_MEM008_I_ECC_1_CORRECT_E5 (0x1<<7) // Record if a corr…
82782 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_1_CORRECT_E5_SHIFT 7
82801 …ED_0_MEM007_I_ECC_1_CORRECT_BB_K2 (0x1<<7) // Record if a corr…
82802 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_1_CORRECT_BB_K2_SHIFT 7
82808 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
82850 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82851 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82852 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82853 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82854 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82855 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82856 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82857 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82858 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82859 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82860 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82861 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82862 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82863 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82864 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82865 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82867 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82882 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82883 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82884 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82885 …onding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82886 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82887 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82888 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
82889 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82890 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82891 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82892 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82893 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82894 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82895 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82896 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82897 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82898 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82899 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82900 … 0x1280684UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
82902 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82903 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82916 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
82917 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
82918 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
82920 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
82925 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82926 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82927 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82928 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
82945 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82946 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82947 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82948 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82949 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82950 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82951 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82952 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82953 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82954 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82955 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82956 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82957 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82958 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82959 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82960 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82961 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82962 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82963 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82964 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82965 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82966 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82967 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82968 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
83008 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
83009 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
83014 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83015 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83016 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83017 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83018 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83019 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83020 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83021 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83022 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83031 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
83032 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
83033 … 0x1280a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
83034 … 0x1280a10UL //Access:R DataWidth:0x1 // In-process Table almost …
83060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
83061 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
83062 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
83063 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
83124 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
83127 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
83129 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
83131 …ess:R DataWidth:0x20 // Debug read from RDIF Input stage buffer with 32-bits granularity. Rea…
83133 …ess:R DataWidth:0x20 // Debug read from TDIF Input stage buffer with 32-bits granularity. Rea…
83135 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
83137 …ess:R DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Rea…
83139 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
83141 …ess:R DataWidth:0x20 // Debug read from YULD Input stage buffer with 32-bits granularity. Rea…
83143 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
83144 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
83145 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
83146 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
83147 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
83156 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
83159 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
83353 …ess:R DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Rea…
83354 …ess:R DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Rea…
83363 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
83365 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83366 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83367 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83368 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83369 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83370 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83371 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83372 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83373 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83374 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83375 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83376 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
83394 …LE_IN_BB_K2 (0x1<<7) // Enable for stall…
83395 …SEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2_SHIFT 7
83424 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
83435 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
83438 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
83440 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
83442 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
83444 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
83446 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
83449 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
83451 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
83453 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
83455 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83458 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
83460 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
83462 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
83464 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83494 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83504 …TORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
83505 …SEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
83522 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83562 …R_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
83563 …SEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
83570 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83623 …STORE_POP_ERROR_B_E5 (0x1<<7) // This bit masks, …
83624 …SEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
83681 …WR_POP_ERROR_BB_K2 (0x1<<7) // This bit masks, …
83682 …SEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
83732 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83742 …T_STORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
83743 …SEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
83760 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83800 …A_WR_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
83801 …SEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
83808 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83851 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83861 …XT_STORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
83862 …SEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
83879 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83919 …RA_WR_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
83920 …SEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
83927 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83980 …D_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
83981 …SEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
84038 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84040 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84044 … (0x1<<7) // Indicates that a DMA request cycle was received which…
84045 …SEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
84054 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84071 …RD_PUSH_ERROR_A_E5 (0x1<<7) // This bit masks, …
84072 …SEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
84135 …D_OOR_ERROR_BB_K2 (0x1<<7) // This bit masks, …
84136 …SEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
84162 …A_RD_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
84163 …SEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
84220 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84222 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84226 … (0x1<<7) // Indicates that a DMA request cycle was received which…
84227 …SEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
84236 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84253 …RA_RD_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
84254 …SEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
84311 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84313 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84317 … (0x1<<7) // Indicates that a DMA request cycle was received which…
84318 …SEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
84327 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84344 …_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
84345 …SEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
84356 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84358 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84407 …FC_FIFO_ERROR_E5 (0x1<<7) // This bit masks, …
84408 …SEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
84470 …RBC_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
84471 …SEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
84482 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84484 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84533 …_RBC_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
84534 …SEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
84545 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84547 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84628 … 0x1400408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
84629 … 0x140040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
84630 … 0x1400420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
84633 … 0x1400440UL //Access:R DataWidth:0x10 // This read-only register provide…
84640 …UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be acti…
84641 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
84642 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
84643 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
84647 … 0x1400600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
84649 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
84650 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
84656 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
84659 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84660 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84662 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
84664 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
84667 …0x1400b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
84674 …1400b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
84675 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
84677 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
84681 … 0x1400d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
84683 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
84685 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
84686 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
84696 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
84701 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
84714 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
84717 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
84720 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
84721 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
84733 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
84738 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
84749 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
84751 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
84756 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
84772 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
84782 … 0x1408000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
84788 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
84793 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84794 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84817 …LE_IN_BB_K2 (0x1<<7) // Enable for stall…
84818 …SEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2_SHIFT 7
84847 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
84858 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
84861 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
84863 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
84865 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
84867 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
84869 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
84872 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
84874 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
84876 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
84878 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84881 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
84883 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
84885 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
84887 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84917 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
84927 …TORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
84928 …SEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
84945 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84985 …R_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
84986 …SEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
84993 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85046 …STORE_POP_ERROR_B_E5 (0x1<<7) // This bit masks, …
85047 …SEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
85104 …WR_POP_ERROR_BB_K2 (0x1<<7) // This bit masks, …
85105 …SEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
85155 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85165 …T_STORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
85166 …SEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
85183 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85223 …A_WR_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
85224 …SEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
85231 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85274 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85284 …XT_STORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
85285 …SEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
85302 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85342 …RA_WR_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
85343 …SEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
85350 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85403 …D_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
85404 …SEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
85461 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85463 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85467 … (0x1<<7) // Indicates that a DMA request cycle was received which…
85468 …SEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
85477 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85494 …RD_PUSH_ERROR_A_E5 (0x1<<7) // This bit masks, …
85495 …SEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
85558 …D_OOR_ERROR_BB_K2 (0x1<<7) // This bit masks, …
85559 …SEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
85585 …A_RD_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
85586 …SEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
85643 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85645 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85649 … (0x1<<7) // Indicates that a DMA request cycle was received which…
85650 …SEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
85659 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85676 …RA_RD_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
85677 …SEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
85734 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85736 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85740 … (0x1<<7) // Indicates that a DMA request cycle was received which…
85741 …SEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
85750 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85767 …_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
85768 …SEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
85779 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85781 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85830 …FC_FIFO_ERROR_E5 (0x1<<7) // This bit masks, …
85831 …SEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
85893 …RBC_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
85894 …SEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
85905 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85907 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85956 …_RBC_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
85957 …SEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
85968 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85970 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
86051 … 0x1500408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
86052 … 0x150040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
86053 … 0x1500420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
86056 … 0x1500440UL //Access:R DataWidth:0x10 // This read-only register provide…
86063 …UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be acti…
86064 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
86065 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
86066 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
86070 … 0x1500600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
86072 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
86073 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
86079 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
86082 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86083 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86085 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
86087 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
86090 …0x1500b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
86097 …1500b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
86098 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
86100 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
86104 … 0x1500d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
86106 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
86108 …L //Access:RW DataWidth:0xe // Provides access to the thread ordering queue pop-enable vector.
86109 … //Access:RW DataWidth:0xe // Provides access to the thread ordering queue wake-enable vector.
86119 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
86124 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
86137 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
86140 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
86143 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
86144 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
86156 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
86161 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
86172 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
86174 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
86179 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
86195 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
86205 … 0x1508000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the ex…
86211 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
86216 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86217 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86241 …LE_IN_BB_K2 (0x1<<7) // Enable for stall…
86242 …SEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2_SHIFT 7
86271 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
86282 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
86285 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
86287 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
86289 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
86291 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
86293 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
86296 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
86298 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
86300 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
86302 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86305 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
86307 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
86309 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
86311 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86341 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86351 …TORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
86352 …SEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
86369 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86409 …R_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
86410 …SEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
86417 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86470 …STORE_POP_ERROR_B_E5 (0x1<<7) // This bit masks, …
86471 …SEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
86528 …WR_POP_ERROR_BB_K2 (0x1<<7) // This bit masks, …
86529 …SEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
86579 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86589 …T_STORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
86590 …SEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
86607 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86647 …A_WR_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
86648 …SEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
86655 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86698 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86708 …XT_STORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
86709 …SEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
86726 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86766 …RA_WR_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
86767 …SEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
86774 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86827 …D_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
86828 …SEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
86885 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
86887 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
86891 … (0x1<<7) // Indicates that a DMA request cycle was received which…
86892 …SEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
86901 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
86918 …RD_PUSH_ERROR_A_E5 (0x1<<7) // This bit masks, …
86919 …SEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
86982 …D_OOR_ERROR_BB_K2 (0x1<<7) // This bit masks, …
86983 …SEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
87009 …A_RD_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
87010 …SEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
87067 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
87069 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
87073 … (0x1<<7) // Indicates that a DMA request cycle was received which…
87074 …SEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
87083 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87100 …RA_RD_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
87101 …SEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
87158 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
87160 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
87164 … (0x1<<7) // Indicates that a DMA request cycle was received which…
87165 …SEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
87174 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87191 …_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
87192 …SEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
87203 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87205 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87254 …FC_FIFO_ERROR_E5 (0x1<<7) // This bit masks, …
87255 …SEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
87317 …RBC_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
87318 …SEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
87329 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87331 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87380 …_RBC_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
87381 …SEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
87392 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87394 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87473 … 0x1600408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
87474 … 0x160040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
87475 … 0x1600420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
87478 … 0x1600440UL //Access:R DataWidth:0x10 // This read-only register provide…
87485 …UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be acti…
87486 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
87487 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
87488 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
87492 … 0x1600600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
87493 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
87494 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
87500 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
87503 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87504 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87506 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
87508 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
87511 …0x1600b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
87518 …1600b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
87519 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
87521 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
87525 … 0x1600d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
87527 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
87529 …L //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue pop-enable vector.
87530 … //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue wake-enable vector.
87540 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
87545 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
87557 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
87560 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
87563 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
87564 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
87575 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
87580 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
87591 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
87593 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
87598 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
87614 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
87624 … 0x1608000UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the ex…
87630 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
87635 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87636 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87660 …LE_IN_BB_K2 (0x1<<7) // Enable for stall…
87661 …SEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2_SHIFT 7
87690 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
87701 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
87704 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
87706 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
87708 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
87710 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
87712 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
87715 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
87717 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
87719 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
87721 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87724 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
87726 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
87728 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
87730 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87760 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
87770 …TORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
87771 …SEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
87788 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87828 …R_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
87829 …SEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
87836 … (0x1<<11) // Signals an unknown address in the fast-memory window.
87889 …STORE_POP_ERROR_B_E5 (0x1<<7) // This bit masks, …
87890 …SEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
87947 …WR_POP_ERROR_BB_K2 (0x1<<7) // This bit masks, …
87948 …SEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
87998 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88008 …T_STORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
88009 …SEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
88026 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88066 …A_WR_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
88067 …SEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
88074 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88117 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88127 …XT_STORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
88128 …SEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
88145 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88185 …RA_WR_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
88186 …SEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
88193 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88246 …D_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
88247 …SEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
88304 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88306 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88310 … (0x1<<7) // Indicates that a DMA request cycle was received which…
88311 …SEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
88320 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88337 …RD_PUSH_ERROR_A_E5 (0x1<<7) // This bit masks, …
88338 …SEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
88401 …D_OOR_ERROR_BB_K2 (0x1<<7) // This bit masks, …
88402 …SEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
88428 …A_RD_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
88429 …SEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
88486 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88488 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88492 … (0x1<<7) // Indicates that a DMA request cycle was received which…
88493 …SEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
88502 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88519 …RA_RD_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
88520 …SEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
88577 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88579 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88583 … (0x1<<7) // Indicates that a DMA request cycle was received which…
88584 …SEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
88593 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88610 …_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
88611 …SEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
88622 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88624 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88673 …FC_FIFO_ERROR_E5 (0x1<<7) // This bit masks, …
88674 …SEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
88736 …RBC_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
88737 …SEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
88748 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88750 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88799 …_RBC_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
88800 …SEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
88811 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88813 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88892 … 0x1700408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
88893 … 0x170040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
88894 … 0x1700420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
88897 … 0x1700440UL //Access:R DataWidth:0x10 // This read-only register provide…
88904 …UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be acti…
88905 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
88906 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
88907 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
88911 … 0x1700600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
88912 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
88913 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
88919 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
88922 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88923 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88925 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
88927 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
88930 …0x1700b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
88937 …1700b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
88938 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
88940 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
88944 … 0x1700d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
88946 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
88948 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
88949 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
88959 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
88964 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
88976 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
88979 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
88982 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
88983 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
88994 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
88999 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
89010 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
89012 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
89017 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
89033 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
89043 … 0x1708000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
89049 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
89054 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89055 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89078 …LE_IN_BB_K2 (0x1<<7) // Enable for stall…
89079 …SEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2_SHIFT 7
89108 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
89119 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
89122 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
89124 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
89126 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
89128 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
89130 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
89133 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
89135 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
89137 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
89139 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89142 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
89144 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
89146 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
89148 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89178 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89188 …TORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
89189 …SEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
89206 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89246 …R_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
89247 …SEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
89254 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89307 …STORE_POP_ERROR_B_E5 (0x1<<7) // This bit masks, …
89308 …SEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
89365 …WR_POP_ERROR_BB_K2 (0x1<<7) // This bit masks, …
89366 …SEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
89416 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89426 …T_STORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
89427 …SEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
89444 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89484 …A_WR_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
89485 …SEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
89492 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89535 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89545 …XT_STORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
89546 …SEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
89563 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89603 …RA_WR_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
89604 …SEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
89611 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89664 …D_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
89665 …SEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
89722 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89724 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89728 … (0x1<<7) // Indicates that a DMA request cycle was received which…
89729 …SEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
89738 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
89755 …RD_PUSH_ERROR_A_E5 (0x1<<7) // This bit masks, …
89756 …SEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
89819 …D_OOR_ERROR_BB_K2 (0x1<<7) // This bit masks, …
89820 …SEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
89846 …A_RD_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
89847 …SEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
89904 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89906 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89910 … (0x1<<7) // Indicates that a DMA request cycle was received which…
89911 …SEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
89920 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
89937 …RA_RD_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
89938 …SEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
89995 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89997 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
90001 … (0x1<<7) // Indicates that a DMA request cycle was received which…
90002 …SEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
90011 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
90028 …_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
90029 …SEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
90040 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90042 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90091 …FC_FIFO_ERROR_E5 (0x1<<7) // This bit masks, …
90092 …SEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
90154 …RBC_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
90155 …SEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
90166 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90168 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90217 …_RBC_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
90218 …SEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
90229 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90231 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90295 …_I_ECC_7_RF_INT_E5 (0x1<<7) // This bit masks, …
90296 …SEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_7_RF_INT_E5_SHIFT 7
90336 …005_I_ECC_7_EN_E5 (0x1<<7) // Enable ECC for m…
90337 …SEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_7_EN_E5_SHIFT 7
90353 …0_MEM005_I_ECC_7_PRTY_E5 (0x1<<7) // Set parity only …
90354 …SEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_7_PRTY_E5_SHIFT 7
90370 …TED_0_MEM005_I_ECC_7_CORRECT_E5 (0x1<<7) // Record if a corr…
90371 …SEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_7_CORRECT_E5_SHIFT 7
90374 … 0x1800408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
90375 … 0x180040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
90376 … 0x1800420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
90379 … 0x1800440UL //Access:R DataWidth:0x10 // This read-only register provide…
90386 …UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be acti…
90387 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
90388 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
90389 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
90393 … 0x1800600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
90394 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
90395 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
90401 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
90404 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90405 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90407 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
90409 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
90412 …0x1800b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
90419 …1800b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
90420 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
90422 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
90426 … 0x1800d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
90428 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
90430 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
90431 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
90441 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
90446 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
90458 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
90461 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
90464 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
90465 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
90476 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
90481 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
90492 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
90494 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
90499 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
90515 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
90525 … 0x1808000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
90531 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
90536 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90537 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90561 …LE_IN_BB_K2 (0x1<<7) // Enable for stall…
90562 …SEM_REG_ENABLE_IN_STALL_ENABLE_IN_BB_K2_SHIFT 7
90591 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
90602 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
90605 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
90607 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
90609 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
90611 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
90613 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
90616 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
90618 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
90620 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
90622 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90625 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
90627 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
90629 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
90631 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90661 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90671 …TORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
90672 …SEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
90689 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90729 …R_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
90730 …SEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
90737 … (0x1<<11) // Signals an unknown address in the fast-memory window.
90790 …STORE_POP_ERROR_B_E5 (0x1<<7) // This bit masks, …
90791 …SEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
90848 …WR_POP_ERROR_BB_K2 (0x1<<7) // This bit masks, …
90849 …SEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
90899 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90909 …T_STORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
90910 …SEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
90927 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90967 …A_WR_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
90968 …SEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
90975 … (0x1<<11) // Signals an unknown address in the fast-memory window.
91018 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
91028 …XT_STORE_POP_ERROR_B_E5 (0x1<<7) // Error in externa…
91029 …SEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_B_E5_SHIFT 7
91046 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91086 …RA_WR_POP_ERROR_BB_K2 (0x1<<7) // Error in DRA_WR_…
91087 …SEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_BB_K2_SHIFT 7
91094 … (0x1<<11) // Signals an unknown address in the fast-memory window.
91147 …D_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
91148 …SEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
91205 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91207 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91211 … (0x1<<7) // Indicates that a DMA request cycle was received which…
91212 …SEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
91221 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91238 …RD_PUSH_ERROR_A_E5 (0x1<<7) // This bit masks, …
91239 …SEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
91302 …D_OOR_ERROR_BB_K2 (0x1<<7) // This bit masks, …
91303 …SEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
91329 …A_RD_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
91330 …SEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
91387 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91389 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91393 … (0x1<<7) // Indicates that a DMA request cycle was received which…
91394 …SEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
91403 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91420 …RA_RD_PUSH_ERROR_A_E5 (0x1<<7) // DRA RD FIFO erro…
91421 …SEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_A_E5_SHIFT 7
91478 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91480 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91484 … (0x1<<7) // Indicates that a DMA request cycle was received which…
91485 …SEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_BB_K2_SHIFT 7
91494 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91511 …_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
91512 …SEM_REG_INT_STS_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
91523 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91525 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91574 …FC_FIFO_ERROR_E5 (0x1<<7) // This bit masks, …
91575 …SEM_REG_INT_MASK_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
91637 …RBC_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
91638 …SEM_REG_INT_STS_WR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
91649 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91651 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91700 …_RBC_VFC_FIFO_ERROR_E5 (0x1<<7) // VFC FIFO error
91701 …SEM_REG_INT_STS_CLR_2_MUX_RBC_VFC_FIFO_ERROR_E5_SHIFT 7
91712 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91714 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91793 … 0x1900408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
91794 … 0x190040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
91795 … 0x1900420UL //Access:WB_R DataWidth:0xf0 // This read-only register provide…
91798 … 0x1900440UL //Access:R DataWidth:0x10 // This read-only register provide…
91805 …UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be acti…
91806 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
91807 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
91808 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
91812 … 0x1900600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
91813 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
91814 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
91820 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
91823 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91824 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91826 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
91828 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
91831 …0x1900b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
91838 …1900b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
91839 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
91841 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
91845 … 0x1900d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the em…
91847 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
91849 …L //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue pop-enable vector.
91850 … //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue wake-enable vector.
91860 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
91865 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
91877 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
91880 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
91883 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
91884 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
91895 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
91900 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
91911 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
91913 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
91918 …he corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1…
91934 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
91944 … 0x1908000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the ex…
91950 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
91955 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
91956 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…