Lines Matching full:pxp
36420 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36426 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36429 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36435 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36438 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36444 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36447 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36453 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36456 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36462 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36465 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36471 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36474 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36480 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36483 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36489 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36492 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36498 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36500 … DataWidth:0x20 // First 32b for enabling the output for close the gate pxp. Mapped as follows:…
36501 …pxp. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[…
36502 … DataWidth:0x20 // Third 32b for enabling the output for close the gate pxp. Mapped as follows:…
36503 … DataWidth:0x20 // Fourth 32b for enabling the output for close the gate pxp. Mapped as follows:…
36504 … DataWidth:0x20 // Fifth 32b for enabling the output for close the gate pxp. Mapped as follows:…
36505 … DataWidth:0x20 // Sixth 32b for enabling the output for close the gate pxp. Mapped as follows:…
36506 …DataWidth:0x20 // Seventh 32b for enabling the output for close the gate pxp. Mapped as follows:…
36507 …pxp. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PS…
36508 … DataWidth:0x20 // Nineth 32b for enabling the output for close the gate pxp. Mapped as follows:…
36510 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36516 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36519 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36525 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36528 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36534 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36537 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36543 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36546 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36552 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36555 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36561 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36564 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36570 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36573 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36579 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36582 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36588 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36591 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36597 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36600 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36606 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36609 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36615 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36618 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36624 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36627 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36633 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36638 …PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue…
36644 …error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event…
36647 …OSE_MASK (0x1<<0) // Pxp close the gate mask…
37124 …n engine for PXP messages. Set bit 0 to send PXP messages to engine 0. Set bit 1 to send PXP messa…
37301 … send; 0 - One Shot; c) When DBG_REGISTERS_DEBUG_TARGET =2 (PXP): 1 - wrap host memory in PXP; 0 -…
37836 … 0x010b3cUL //Access:RW DataWidth:0x6 // The packet size to NIG or PXP target is in granul…
38561 … (0x1<<6) // 0 : PXP empty is not part of OBFF logic. 1 : PXP…
38616 … (0x1<<6) // 0 : PXP empty is not part of L1 request generation logic…
38648 … (0x1<<6) // 0 : PXP empty is not part of LTR request generation logic…
38757 … (0x1<<6) // 0 : PXP empty is not part of Main Clock slowdown logic.…
38811 … (0x1<<6) // 0 : PXP empty is not part of Storm Clock slowdown logic.…
38865 … (0x1<<6) // 0 : PXP empty is not part of Nw Clock slowdown logic. …
38919 … (0x1<<6) // 0 : PXP empty is not part of PCI Clock slowdown logic. …
39509 … 1 it is write, If = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm.…
39512 … 1 it is write, if = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm.…
39515 … 1 it is write, if = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm.…
39519 …ddress attribute to UA PROTECTION. Bits [46:43]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm.…
39522 …, and its accesses are not written to the trace FIFO. The fields: Bit [0]: pxp. Bit [1]: mcp. Bit …
40939 …3cUL //Access:RW DataWidth:0x1 // If 1, then full is asserted towards PXP when DORQ FIFO fill…
40940 …asserted towards PXP. If DORQ FIFO fill level is equal or greater than it and dq_pxp_full_en is 0,…
40941 …L //Access:RW DataWidth:0xe // Number of cycles in which full towards PXP is asserted if DORQ…
40994 … 0x1009f8UL //Access:RW DataWidth:0x8 // Size in bytes of the PXP transactions to be …
41029 … 0x100a84UL //Access:RC DataWidth:0x20 // Number of PXP transaction of a se…
41469 …x180050UL //Access:RW DataWidth:0x2 // PXP req credit. The max number of outstanding messages…
41482 …IG (0x1<<2) // PXP write message lengt…
41528 …O_BIG (0x1<<2) // PXP write message lengt…
41551 …OO_BIG (0x1<<2) // PXP write message lengt…
41764 … 0x18040cUL //Access:R DataWidth:0x20 // Debug: number of PXP messeges sent (atte…
41765 … 0x180410UL //Access:R DataWidth:0x20 // Debug: number of PXP write done received…
41771 … 0x180418UL //Access:RC DataWidth:0x20 // Debug: count the number of PXP requests sent on be…
41829 …PXP BAR address; [30:29] - Reserved; [31] command type - 0-read; 1-wr. When writing to this regist…
41942 …PXP sources, 8 - CAU, 9 - ATTN, 10 - GRC command register). [16:13] - error type (value: 0 - no er…
42012 …CMD (0x1<<1) // PXP read request arrive…
42014 …GTH_CMD (0x1<<2) // PXP write request witho…
42035 …_RD_CMD (0x1<<1) // PXP read request arrive…
42037 …_LENGTH_CMD (0x1<<2) // PXP write request witho…
42058 …RD_CMD (0x1<<1) // PXP read request arrive…
42060 …LENGTH_CMD (0x1<<2) // PXP write request witho…
42224 … (0x3<<0) // The value of the TPH Hint field in the PXP request for SB DMA.
42226 … (0x3<<4) // The endianity mode in the PXP request.
42228 … (0x1<<6) // The value of the Relax Ordering field in the PXP request.
42230 … (0x1<<7) // The value of the No Snoop field in the PXP request.
42232 … (0x1f<<8) // The value of the VQID field in the PXP request.
42234 … (0x1<<13) // The value of the Pad to Cache Line field in the SB DMA PXP request.
42236 … (0x7<<15) // The value of the ATC flags in the PXP request.
42238 … (0x1<<18) // The value of the done type in the PXP request.
42240 … (0x3<<2) // The value of the TPH Hint field in the PXP request for CQE mes…
42242 … (0x1<<14) // The value of the Pad to Cache Line field in the CQE PXP request.
42249 …arbiter (sp with anti starvation) priority for the input clients: bits 1:0 PXP input commands. bit…
42304 …0x1c0ba8UL //Access:RW DataWidth:0x20 // The number of CQE messages that where sent to the PXP.
42311 … // Debug: all the FIFO status. 0 - FIFO empty; 1 - FIFO not empty. [0] - PXP command FIFO; [1] -…
42312 …/ Debug; debug information if an error command arrived to the CAU from the PXP: [20:18] - error ty…
42371 … //Access:WB_R DataWidth:0x62 // Debug: Provides read-only access of the PXP reques FIFO. Intend…
42373 … //Access:WB_R DataWidth:0x84 // Debug: Provides read-only access of the PXP write-data FIFO. In…
42377 …y 1); [7] - SB write cmd (If set the entire SB segment is written over the PXP to host memory); [8…
44381 … 0x23000cUL //Access:RW DataWidth:0x1 // Enables the PXP request acknowledge…
44670 …0 // Provides the value of the 16-bit pad that will be inserted into the PXP data stream when pa…
44672 …30428UL //Access:RW DataWidth:0x3 // Initial credit to be used on the PXP request interface. …
44679 …DataWidth:0x9 // Defines the number of occupied entries required in the PXP read-response FIFO …
44726 …33c00UL //Access:R DataWidth:0x8 // Provides read-only access of the PXP write-done response…
44788 … (0x7<<0) // Controls PXP Request ATC Field f…
44790 … (0x1<<3) // Controls PXP Request TPH Valid f…
44792 … (0x7<<4) // Controls PXP Request ATC Field f…
44794 … (0x1<<7) // Controls PXP Request TPH Valid f…
44796 … (0x1<<8) // Controls PXP Request DonType Fie…
45740 … (0x1<<0) // Relaxed oredering attribute for cdu. Removed in E4B0, PXP request flag is use…
45742 … (0x1<<1) // Nosnoop attribute for cdu. Removed in E4B0, PXP request flag is use…
48866 …cates that the corresponding PF generates config space A attention. Set by PXP. Reset by MCP writi…
48868 …cates that the corresponding PF generates config space B attention. Set by PXP. Reset by MCP writi…
48870 …it indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writi…
48871 …it indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writi…
48872 …it indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writi…
48873 …it indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writi…
48874 …it indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writi…
48875 …it indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writi…
48876 …it indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writi…
48877 …it indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writi…
48878 …it indicates that the FLR register of the corresponding PF was set. Set by PXP. Reset by MCP writi…
48893 …ister of the corresponding PF is written to 0 and was previously 1. Set by PXP. Reset by MCP writi…
48927 …was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writi…
48928 …was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writi…
48929 …was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writi…
48930 …was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writi…
48931 …was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writi…
48932 …was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writi…
48933 …was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writi…
48934 …was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writi…
48935 …was a completion with uncorrectable error for the corresponding PF. Set by PXP. Reset by MCP writi…
49114 …th not a multiple of DWs. 0 - PGLUE will submit the request with TPH info. PXP will take care of a…
49199 …attention dirty bits. Bit 0 is for engine 0 and bit 1 for engine 1. Set by PXP. Reset by MCP writi…
49201 …2aae90UL //Access:R DataWidth:0x10 // MPS attention dirty bit. Set by PXP. Reset by MCP writi…
49203 …it indicates that the VPD register of the corresponding PF was set. Set by PXP. Reset by MCP accor…
49277 … 0x2c0014UL //Access:RW DataWidth:0x1 // When set init the PXP READ DATA FIFO.
49278 … 0x2c0018UL //Access:RW DataWidth:0x1 // When set init the PXP READ CTRL FIFO.
49288 … 0x2c0060UL //Access:RW DataWidth:0x1 // Enable pxp request, wr and rd …
49292 … 0x2c0078UL //Access:RW DataWidth:0x2 // Credit for the PXP request interface.
49300 …OV (0x1<<1) // PXP READ DATA FIFO Over…
49302 …UN (0x1<<2) // PXP READ DATA FIFO Unde…
49304 …OV (0x1<<3) // PXP READ CTRL FIFO Over…
49306 …UN (0x1<<4) // PXP READ CTRL FIFO Unde…
49430 …FO_OV (0x1<<1) // PXP READ DATA FIFO Over…
49432 …FO_UN (0x1<<2) // PXP READ DATA FIFO Unde…
49434 …FO_OV (0x1<<3) // PXP READ CTRL FIFO Over…
49436 …FO_UN (0x1<<4) // PXP READ CTRL FIFO Unde…
49495 …IFO_OV (0x1<<1) // PXP READ DATA FIFO Over…
49497 …IFO_UN (0x1<<2) // PXP READ DATA FIFO Unde…
49499 …IFO_OV (0x1<<3) // PXP READ CTRL FIFO Over…
49501 …IFO_UN (0x1<<4) // PXP READ CTRL FIFO Unde…
49566 …LID (0x1<<4) // PXP Read Data EOP with …
49572 …OR (0x1<<7) // PXP Read Data EOP with …
49612 …BVALID (0x1<<4) // PXP Read Data EOP with …
49618 …ERROR (0x1<<7) // PXP Read Data EOP with …
49635 …_BVALID (0x1<<4) // PXP Read Data EOP with …
49641 …_ERROR (0x1<<7) // PXP Read Data EOP with …
49740 …0x2c0400UL //Access:RW DataWidth:0x6 // Almost full threshold for the PXP READ DATA FIFO, whi…
49741 …0x2c0404UL //Access:RW DataWidth:0x4 // Almost full threshold for the PXP READ CTRL FIFO, whi…
49837 … 0x2c0678UL //Access:RC DataWidth:0x8 // Number of PXP read data packets r…
49841 … 0x2c070cUL //Access:R DataWidth:0x1 // When set indicates that the PXP READ DATA FIFO is f…
49842 … 0x2c0710UL //Access:R DataWidth:0x6 // Indicates the status of the PXP READ DATA FIFO, num…
49843 … 0x2c0714UL //Access:R DataWidth:0x1 // When set indicates that the PXP READ CTRL FIFO is f…
49844 … 0x2c0718UL //Access:R DataWidth:0x4 // Indicates the status of the PXP READ CTRL FIFO, num…
49879 … 0x2c07a4UL //Access:R DataWidth:0x17 // The PXP read data is receiv…
51368 …TU size; this should be configured according to the minimal STU within the PXP (there is STU per P…
51370 … 0x2f1534UL //Access:RW DataWidth:0x1 // pad to cache line field as part of PXP write request
51548 … 0x2f2e6cUL //Access:RW DataWidth:0x2 // Init credit for the pxp request interface.
51549 … 0x2f2e70UL //Access:R DataWidth:0x2 // Actual credit for the pxp request interface.
51561 …W DataWidth:0x1 // PCI rd error indication. The QM sets this reg upon PXP rdata with error. T…
52376 … (0x1f<<0) // Controls PXP Request VQID Field
52378 … (0x1<<5) // Controls PXP Request TPH valid F…
52380 … (0x3<<6) // Controls PXP Request TPH hint Fi…
52382 … (0x1ff<<8) // Controls PXP Request TPH index F…
52384 … (0x1<<17) // Controls PXP Request done type F…
52386 … 0x320450UL //Access:RW DataWidth:0x2 // PXP request intial cred…
52392 … 0x320468UL //Access:RC DataWidth:0x20 // Number of PXP read requests which…
52393 … 0x32046cUL //Access:RC DataWidth:0x20 // Number of PXP read done which wer…
52394 … 0x320470UL //Access:RC DataWidth:0x20 // Number of PXP write requests whic…
52395 … 0x320474UL //Access:RC DataWidth:0x20 // Number of PXP write done which we…
52450 … (0x1f<<0) // Controls PXP Request VQID Field
52452 … (0x1<<5) // Controls PXP Request TPH valid F…
52454 … (0x3<<6) // Controls PXP Request TPH hint Fi…
52456 … (0x1ff<<8) // Controls PXP Request TPH index F…
52458 … (0x1<<17) // Controls PXP Request done type F…
52460 … 0x322450UL //Access:RW DataWidth:0x2 // PXP request intial cred…
52466 … 0x322468UL //Access:RC DataWidth:0x20 // Number of PXP read requests which…
52467 … 0x32246cUL //Access:RC DataWidth:0x20 // Number of PXP read done which wer…
52468 … 0x322470UL //Access:RC DataWidth:0x20 // Number of PXP write requests whic…
52469 … 0x322474UL //Access:RC DataWidth:0x20 // Number of PXP write done which we…
55343 … 0x4c0028UL //Access:RW DataWidth:0x5 // VQID value for PXP read requests issue…
55362 … 0x4c0074UL //Access:RC DataWidth:0x20 // Statistics counter of PXP requests sent
56364 … 0x4e0040UL //Access:RW DataWidth:0x5 // VQID value for PXP read requests issue…
56384 … 0x4e0090UL //Access:RC DataWidth:0x20 // Statistics counter of PXP requests sent
59568 … 0x500e0cUL //Access:RW DataWidth:0x1 // Output enable of message to PXP IF.
60404 …h:0x10 // Current value of PFC/LLFC priority or PAUSE signal sent to MAC/PXP, depending on the f…
60407 … // Address to be used in the header of the flow control message sent to PXP internal write inte…
60408 …ination Client ID field for the header of the flow control message sent to PXP internal write inte…
60409 …0 // CompParams value for the header of the flow control message sent to PXP internal write inte…
60410 …Trigger value to be used in the header of the flow control message sent to PXP internal write inte…
61185 …4cUL //Access:RW DataWidth:0x3 // Selects which timer will be sent to PXP 0: free running cou…
64293 … 0x560058UL //Access:RW DataWidth:0x5 // VQID of the PXP read requests issue…
64294 … 0x56005cUL //Access:RW DataWidth:0xc // TPH fileds of the PXP read requests issue…
64295 …0x560060UL //Access:RW DataWidth:0x1 // Releaxed Ordering flag of the PXP read requests issue…
64296 … 0x560064UL //Access:RW DataWidth:0x1 // No Snoop flag of the PXP read requests issue…
64297 … 0x560068UL //Access:RW DataWidth:0x3 // ATC flags of the PXP read requests issue…
64305 … is currently invalidated; if reset such requests will be sent towards the PXP with the PBLBase an…
64307 … 0x560090UL //Access:RW DataWidth:0x3 // Max credits of the PBF->PXP interface.
64308 … 0x560094UL //Access:RW DataWidth:0x3 // Max credits of the PRM->PXP interface.
64309 … 0x560098UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64310 … 0x56009cUL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64311 … 0x5600a0UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64629 … is currently invalidated; if reset such requests will be sent towards the PXP with the PBLBase an…
64656 … (0x1<<0) // Enables PXP Accesses.
64666 … (0x1<<5) // Sets the PXP Arbiter to Strict P…
64685 … (0x1<<7) // Byte valid Error on PXP Interface. All tra…
64702 … (0x1<<7) // Byte valid Error on PXP Interface. All tra…
64719 … (0x1<<7) // Byte valid Error on PXP Interface. All tra…
64790 …l signal to PXP. This register must never be set higher than 8 -- doing so will result in FIFO ove…
64791 …er be set higher than 13 -- doing so will result in data corruption to the PXP due to FIFO overflo…
64793 … (0x7<<0) // ATC Flags Field for CCFC PXP Writes.
64795 … (0x7<<3) // ATC Flags Field for CCFC PXP Reads.
64799 … (0x1<<16) // TPH Valid bit for CCFC PXP Requests.
64801 … (0x1<<17) // Relaxed ordering bit for CCFC PXP rd_req.
64803 … (0x1<<18) // Relaxed ordering bit for CCFC PXP wr_req.
64805 … (0x1<<19) // No snoop bit for CCFC PXP rd_req.
64807 … (0x1<<20) // No snoop bit for CCFC PXP wr_req.
64810 … (0x7<<0) // ATC Flags Field for TCFC PXP Writes.
64812 … (0x7<<3) // ATC Flags Field for TCFC PXP Reads.
64816 … (0x1<<16) // TPH Valid bit for TCFC PXP Requests.
64818 … (0x1<<17) // Relaxed ordering bit for TCFC working memory PXP rd_req.
64820 … (0x1<<18) // Relaxed ordering bit for TCFC init memory PXP rd_req.
64822 … (0x1<<19) // Relaxed ordering bit for TCFC working memory PXP wr_req.
64824 … (0x1<<20) // No snoop bit for TCFC working memory PXP rd_req.
64826 … (0x1<<21) // No snoop bit for TCFC init memory PXP rd_req.
64828 … (0x1<<22) // No snoop bit for TCFC working memory PXP wr_req.
64830 … 0x580608UL //Access:RW DataWidth:0x5 // VQID used for PXP Read (Load) transac…
64831 … 0x58060cUL //Access:RW DataWidth:0x5 // VQID used for PXP Write (WriteBack) t…
64837 … (0x3<<16) // PXP Read Request Credit…
64841 … (0x1<<23) // Uses pxp_init_ldcredit to update PXP Read Credits.
64843 … (0x3<<24) // PXP Write Request Credi…
64847 … (0x1<<31) // Uses pxp_init_wbcredit to update PXP Write Credits.
68448 … 0xd80400UL //Access:RW DataWidth:0x3 // PXP read request interf…
68452 … 0xd80410UL //Access:RW DataWidth:0x2 // PXP internal write inte…
68691 …UL //Access:RC DataWidth:0x8 // Number of packets received with error indication from PXP/TDIF
71657 …// Setting this bit will cause the P2M block to assert backpressure to the PXP when the packet FIF…
72700 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA…
72702 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA…
72704 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA…
72706 … (0x1<<9) // Enable for input ack from pxp-internal write for …
72712 … (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
72736 … (0x1<<0) // Enable for output request to pxp internal write for …
72750 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA…
72758 … (0x1<<11) // Enable for output write to pxp async in DMA_DST bl…
72760 … (0x1<<12) // Enable for output write to pxp in DMA_DST block.
72764 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
72768 … (0x1<<16) // Enable for output done to async PXP host IF.
72800 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-A…
72825 … (0x1<<9) // PXP immediate data fifo…
72827 …OR (0x1<<10) // PXP dst pending fifo er…
72841 …R (0x1<<17) // PXP read data fifo erro…
72857 … (0x1<<25) // PXP done fifo error in …
72951 …ROR (0x1<<9) // PXP immediate data fifo…
72953 …ERROR (0x1<<10) // PXP dst pending fifo er…
72967 …RROR (0x1<<17) // PXP read data fifo erro…
72983 …R (0x1<<25) // PXP done fifo error in …
73014 …RROR (0x1<<9) // PXP immediate data fifo…
73016 …_ERROR (0x1<<10) // PXP dst pending fifo er…
73030 …ERROR (0x1<<17) // PXP read data fifo erro…
73046 …OR (0x1<<25) // PXP done fifo error in …
73100 …iter used for all completion write requests in the completion manager: b0-PXP async b1-NOP;b2-int…
73102 …bin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;…
73104 …r of completion messages that can be allocated to PXP-Async transactions at any given time. If the…
73106 …DataWidth:0x3 // The initial number of messages that can be sent to the pxp interface without r…
73122 …0xf80628UL //Access:RC DataWidth:0x20 // The number of requests received from the pxp async if.
73125 …704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block.
73140 … 0xf80c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full …
73146 … 0xf80c34UL //Access:R DataWidth:0x1 // PXP interface is full …
73147 … 0xf80c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full…
73148 … 0xf80c3cUL //Access:R DataWidth:0x1 // PXP destination pending…
73149 … 0xf80c40UL //Access:R DataWidth:0x1 // PXP source pending fifo…
73152 … 0xf80c4cUL //Access:R DataWidth:0x1 // PXP link list full in s…
73155 … 0xf80c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_…
73173 … 0xf80d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty…
73178 … 0xf80d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empt…
73179 … 0xf80d30UL //Access:R DataWidth:0x1 // PXP destination pending…
73180 … 0xf80d34UL //Access:R DataWidth:0x1 // PXP source pending fifo…
73183 … 0xf80d40UL //Access:R DataWidth:0x1 // PXP link list empty in …
73204 …82000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async input FIFO. I…
73210 …82c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PXP response FIFO. Inte…
73241 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA…
73243 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA…
73245 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA…
73247 … (0x1<<9) // Enable for input ack from pxp-internal write for …
73253 … (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
73277 … (0x1<<0) // Enable for output request to pxp internal write for …
73291 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA…
73299 … (0x1<<11) // Enable for output write to pxp async in DMA_DST bl…
73301 … (0x1<<12) // Enable for output write to pxp in DMA_DST block.
73305 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
73309 … (0x1<<16) // Enable for output done to async PXP host IF.
73341 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-A…
73366 … (0x1<<9) // PXP immediate data fifo…
73368 …OR (0x1<<10) // PXP dst pending fifo er…
73382 …R (0x1<<17) // PXP read data fifo erro…
73398 … (0x1<<25) // PXP done fifo error in …
73492 …ROR (0x1<<9) // PXP immediate data fifo…
73494 …ERROR (0x1<<10) // PXP dst pending fifo er…
73508 …RROR (0x1<<17) // PXP read data fifo erro…
73524 …R (0x1<<25) // PXP done fifo error in …
73555 …RROR (0x1<<9) // PXP immediate data fifo…
73557 …_ERROR (0x1<<10) // PXP dst pending fifo er…
73571 …ERROR (0x1<<17) // PXP read data fifo erro…
73587 …OR (0x1<<25) // PXP done fifo error in …
73637 …iter used for all completion write requests in the completion manager: b0-PXP async b1-NOP;b2-int…
73639 …bin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;…
73641 …r of completion messages that can be allocated to PXP-Async transactions at any given time. If the…
73643 …DataWidth:0x3 // The initial number of messages that can be sent to the pxp interface without r…
73660 …0xf90628UL //Access:RC DataWidth:0x20 // The number of requests received from the pxp async if.
73663 …704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block.
73678 … 0xf90c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full …
73684 … 0xf90c34UL //Access:R DataWidth:0x1 // PXP interface is full …
73685 … 0xf90c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full…
73686 … 0xf90c3cUL //Access:R DataWidth:0x1 // PXP destination pending…
73687 … 0xf90c40UL //Access:R DataWidth:0x1 // PXP source pending fifo…
73690 … 0xf90c4cUL //Access:R DataWidth:0x1 // PXP link list full in s…
73693 … 0xf90c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_…
73711 … 0xf90d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty…
73716 … 0xf90d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empt…
73717 … 0xf90d30UL //Access:R DataWidth:0x1 // PXP destination pending…
73718 … 0xf90d34UL //Access:R DataWidth:0x1 // PXP source pending fifo…
73721 … 0xf90d40UL //Access:R DataWidth:0x1 // PXP link list empty in …
73742 …92000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async input FIFO. I…
73748 …92c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PXP response FIFO. Inte…
73779 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA…
73781 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA…
73783 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA…
73785 … (0x1<<9) // Enable for input ack from pxp-internal write for …
73791 … (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
73815 … (0x1<<0) // Enable for output request to pxp internal write for …
73829 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA…
73837 … (0x1<<11) // Enable for output write to pxp async in DMA_DST bl…
73839 … (0x1<<12) // Enable for output write to pxp in DMA_DST block.
73843 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
73847 … (0x1<<16) // Enable for output done to async PXP host IF.
73879 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-A…
73904 … (0x1<<9) // PXP immediate data fifo…
73906 …OR (0x1<<10) // PXP dst pending fifo er…
73920 …R (0x1<<17) // PXP read data fifo erro…
73936 … (0x1<<25) // PXP done fifo error in …
74030 …ROR (0x1<<9) // PXP immediate data fifo…
74032 …ERROR (0x1<<10) // PXP dst pending fifo er…
74046 …RROR (0x1<<17) // PXP read data fifo erro…
74062 …R (0x1<<25) // PXP done fifo error in …
74093 …RROR (0x1<<9) // PXP immediate data fifo…
74095 …_ERROR (0x1<<10) // PXP dst pending fifo er…
74109 …ERROR (0x1<<17) // PXP read data fifo erro…
74125 …OR (0x1<<25) // PXP done fifo error in …
74199 …iter used for all completion write requests in the completion manager: b0-PXP async b1-NOP;b2-int…
74201 …bin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;…
74203 …r of completion messages that can be allocated to PXP-Async transactions at any given time. If the…
74205 …DataWidth:0x3 // The initial number of messages that can be sent to the pxp interface without r…
74222 …0xfa0628UL //Access:RC DataWidth:0x20 // The number of requests received from the pxp async if.
74225 …704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block.
74240 … 0xfa0c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full …
74246 … 0xfa0c34UL //Access:R DataWidth:0x1 // PXP interface is full …
74247 … 0xfa0c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full…
74248 … 0xfa0c3cUL //Access:R DataWidth:0x1 // PXP destination pending…
74249 … 0xfa0c40UL //Access:R DataWidth:0x1 // PXP source pending fifo…
74252 … 0xfa0c4cUL //Access:R DataWidth:0x1 // PXP link list full in s…
74255 … 0xfa0c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_…
74273 … 0xfa0d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty…
74278 … 0xfa0d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empt…
74279 … 0xfa0d30UL //Access:R DataWidth:0x1 // PXP destination pending…
74280 … 0xfa0d34UL //Access:R DataWidth:0x1 // PXP source pending fifo…
74283 … 0xfa0d40UL //Access:R DataWidth:0x1 // PXP link list empty in …
74304 …a2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async input FIFO. I…
74310 …a2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PXP response FIFO. Inte…
74341 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA…
74343 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA…
74345 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA…
74347 … (0x1<<9) // Enable for input ack from pxp-internal write for …
74353 … (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
74377 … (0x1<<0) // Enable for output request to pxp internal write for …
74391 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA…
74399 … (0x1<<11) // Enable for output write to pxp async in DMA_DST bl…
74401 … (0x1<<12) // Enable for output write to pxp in DMA_DST block.
74405 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
74409 … (0x1<<16) // Enable for output done to async PXP host IF.
74441 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-A…
74466 … (0x1<<9) // PXP immediate data fifo…
74468 …OR (0x1<<10) // PXP dst pending fifo er…
74482 …R (0x1<<17) // PXP read data fifo erro…
74498 … (0x1<<25) // PXP done fifo error in …
74592 …ROR (0x1<<9) // PXP immediate data fifo…
74594 …ERROR (0x1<<10) // PXP dst pending fifo er…
74608 …RROR (0x1<<17) // PXP read data fifo erro…
74624 …R (0x1<<25) // PXP done fifo error in …
74655 …RROR (0x1<<9) // PXP immediate data fifo…
74657 …_ERROR (0x1<<10) // PXP dst pending fifo er…
74671 …ERROR (0x1<<17) // PXP read data fifo erro…
74687 …OR (0x1<<25) // PXP done fifo error in …
74741 …iter used for all completion write requests in the completion manager: b0-PXP async b1-NOP;b2-int…
74743 …bin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;…
74745 …r of completion messages that can be allocated to PXP-Async transactions at any given time. If the…
74747 …DataWidth:0x3 // The initial number of messages that can be sent to the pxp interface without r…
74763 …0xfb0628UL //Access:RC DataWidth:0x20 // The number of requests received from the pxp async if.
74766 …704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block.
74781 … 0xfb0c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full …
74787 … 0xfb0c34UL //Access:R DataWidth:0x1 // PXP interface is full …
74788 … 0xfb0c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full…
74789 … 0xfb0c3cUL //Access:R DataWidth:0x1 // PXP destination pending…
74790 … 0xfb0c40UL //Access:R DataWidth:0x1 // PXP source pending fifo…
74793 … 0xfb0c4cUL //Access:R DataWidth:0x1 // PXP link list full in s…
74796 … 0xfb0c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_…
74814 … 0xfb0d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty…
74819 … 0xfb0d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empt…
74820 … 0xfb0d30UL //Access:R DataWidth:0x1 // PXP destination pending…
74821 … 0xfb0d34UL //Access:R DataWidth:0x1 // PXP source pending fifo…
74824 … 0xfb0d40UL //Access:R DataWidth:0x1 // PXP link list empty in …
74845 …b2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async input FIFO. I…
74851 …b2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PXP response FIFO. Inte…
74882 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA…
74884 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA…
74886 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA…
74888 … (0x1<<9) // Enable for input ack from pxp-internal write for …
74894 … (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
74918 … (0x1<<0) // Enable for output request to pxp internal write for …
74932 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA…
74940 … (0x1<<11) // Enable for output write to pxp async in DMA_DST bl…
74942 … (0x1<<12) // Enable for output write to pxp in DMA_DST block.
74946 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
74950 … (0x1<<16) // Enable for output done to async PXP host IF.
74982 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-A…
75007 … (0x1<<9) // PXP immediate data fifo…
75009 …OR (0x1<<10) // PXP dst pending fifo er…
75023 …R (0x1<<17) // PXP read data fifo erro…
75039 … (0x1<<25) // PXP done fifo error in …
75133 …ROR (0x1<<9) // PXP immediate data fifo…
75135 …ERROR (0x1<<10) // PXP dst pending fifo er…
75149 …RROR (0x1<<17) // PXP read data fifo erro…
75165 …R (0x1<<25) // PXP done fifo error in …
75196 …RROR (0x1<<9) // PXP immediate data fifo…
75198 …_ERROR (0x1<<10) // PXP dst pending fifo er…
75212 …ERROR (0x1<<17) // PXP read data fifo erro…
75228 …OR (0x1<<25) // PXP done fifo error in …
75310 …iter used for all completion write requests in the completion manager: b0-PXP async b1-NOP;b2-int…
75312 …bin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;…
75314 …r of completion messages that can be allocated to PXP-Async transactions at any given time. If the…
75316 …DataWidth:0x3 // The initial number of messages that can be sent to the pxp interface without r…
75334 …0xfc0628UL //Access:RC DataWidth:0x20 // The number of requests received from the pxp async if.
75337 …704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block.
75352 … 0xfc0c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full …
75358 … 0xfc0c34UL //Access:R DataWidth:0x1 // PXP interface is full …
75359 … 0xfc0c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full…
75360 … 0xfc0c3cUL //Access:R DataWidth:0x1 // PXP destination pending…
75361 … 0xfc0c40UL //Access:R DataWidth:0x1 // PXP source pending fifo…
75364 … 0xfc0c4cUL //Access:R DataWidth:0x1 // PXP link list full in s…
75367 … 0xfc0c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_…
75385 … 0xfc0d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty…
75390 … 0xfc0d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empt…
75391 … 0xfc0d30UL //Access:R DataWidth:0x1 // PXP destination pending…
75392 … 0xfc0d34UL //Access:R DataWidth:0x1 // PXP source pending fifo…
75395 … 0xfc0d40UL //Access:R DataWidth:0x1 // PXP link list empty in …
75416 …c2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async input FIFO. I…
75422 …c2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PXP response FIFO. Inte…
75453 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA…
75455 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA…
75457 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA…
75459 … (0x1<<9) // Enable for input ack from pxp-internal write for …
75465 … (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
75489 … (0x1<<0) // Enable for output request to pxp internal write for …
75503 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA…
75511 … (0x1<<11) // Enable for output write to pxp async in DMA_DST bl…
75513 … (0x1<<12) // Enable for output write to pxp in DMA_DST block.
75517 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
75521 … (0x1<<16) // Enable for output done to async PXP host IF.
75553 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-A…
75578 … (0x1<<9) // PXP immediate data fifo…
75580 …OR (0x1<<10) // PXP dst pending fifo er…
75594 …R (0x1<<17) // PXP read data fifo erro…
75610 … (0x1<<25) // PXP done fifo error in …
75704 …ROR (0x1<<9) // PXP immediate data fifo…
75706 …ERROR (0x1<<10) // PXP dst pending fifo er…
75720 …RROR (0x1<<17) // PXP read data fifo erro…
75736 …R (0x1<<25) // PXP done fifo error in …
75767 …RROR (0x1<<9) // PXP immediate data fifo…
75769 …_ERROR (0x1<<10) // PXP dst pending fifo er…
75783 …ERROR (0x1<<17) // PXP read data fifo erro…
75799 …OR (0x1<<25) // PXP done fifo error in …
75853 …iter used for all completion write requests in the completion manager: b0-PXP async b1-NOP;b2-int…
75855 …bin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;…
75857 …r of completion messages that can be allocated to PXP-Async transactions at any given time. If the…
75859 …DataWidth:0x3 // The initial number of messages that can be sent to the pxp interface without r…
75876 …0xfd0628UL //Access:RC DataWidth:0x20 // The number of requests received from the pxp async if.
75879 …704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block.
75894 … 0xfd0c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full …
75900 … 0xfd0c34UL //Access:R DataWidth:0x1 // PXP interface is full …
75901 … 0xfd0c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full…
75902 … 0xfd0c3cUL //Access:R DataWidth:0x1 // PXP destination pending…
75903 … 0xfd0c40UL //Access:R DataWidth:0x1 // PXP source pending fifo…
75906 … 0xfd0c4cUL //Access:R DataWidth:0x1 // PXP link list full in s…
75909 … 0xfd0c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_…
75927 … 0xfd0d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty…
75932 … 0xfd0d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empt…
75933 … 0xfd0d30UL //Access:R DataWidth:0x1 // PXP destination pending…
75934 … 0xfd0d34UL //Access:R DataWidth:0x1 // PXP source pending fifo…
75937 … 0xfd0d40UL //Access:R DataWidth:0x1 // PXP link list empty in …
75958 …d2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async input FIFO. I…
75964 …d2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PXP response FIFO. Inte…