Lines Matching full:lane2
3405 … the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane…
3629 … (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane2
3631 … (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane2
3801 …M Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane1…
3825 …ug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane…
3935 …_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane…
4142 … detect state and uses this value instead. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. 0x7 = Lane7.
4186 …bug status register of Layer1-PerLane. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. 0x7 = Lane7. 0…
4298 …D_EQ_STATUS[1/2/3] viewport registers. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. _ ... 0x7 = Lan…
28626 …SR_5_X401_L2_MASTER_CDN_O_K2_E5 (0x1<<2) // Lane2 master reset
35958 …R_5_X401_L2_MASTER_CDN_O_K2_E5 (0x1<<2) // Lane2 master reset
40389 … 0x0542c0UL //Access:R DataWidth:0x20 // Lane2 debug signal bus t…
40390 … 0x0542c4UL //Access:R DataWidth:0x20 // Lane2 debug signal bus t…
40391 … 0x0542c8UL //Access:R DataWidth:0xe // Lane2 debug signal bus t…
67213 …ff. LANE0 registers = 0x1800-0x1fff. LANE1 registers = 0x2000-0x27ff. LANE2 registers = 0x28…