Lines Matching full:lane1
3405 …ta returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .…
3612 … (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane1
3614 … (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane1
3801 … during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. …
3825 …or Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .…
3935 …OL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .…
4142 …ring LTSSM detect state and uses this value instead. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. 0…
4186 …for silicon debug status register of Layer1-PerLane. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. 0…
4298 …ROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. _ …
28624 …SR_5_X401_L1_MASTER_CDN_O_K2_E5 (0x1<<1) // Lane1 master reset
35956 …R_5_X401_L1_MASTER_CDN_O_K2_E5 (0x1<<1) // Lane1 master reset
40386 … 0x0542b4UL //Access:R DataWidth:0x20 // Lane1 debug signal bus t…
40387 … 0x0542b8UL //Access:R DataWidth:0x20 // Lane1 debug signal bus t…
40388 … 0x0542bcUL //Access:R DataWidth:0xe // Lane1 debug signal bus t…
44142 …1<<6) // This interrupt is asserted when a violation of the allocated TDM lane1 bandwith is detect…
44208 …1<<6) // This interrupt is asserted when a violation of the allocated TDM lane1 bandwith is detect…
44241 …1<<6) // This interrupt is asserted when a violation of the allocated TDM lane1 bandwith is detect…
65968 …Width:0x8 // CMU registers = 0-0x1ff. Reserved = 0x200-0x3ff. LANE1 registers = 0x400-…
67213 …ff. Reserved = 0x1000-0x17ff. LANE0 registers = 0x1800-0x1fff. LANE1 registers = 0x20…