Lines Matching +full:8 +full:b10b
85 …R. Firmware must configure this field prior to starting the link. _ <15:8> is typically set to…
114 …_E5 (0x1<<8) // SERR# enable.
115 …CIEIP_REG_PCIEEP_CMD_SEE_E5_SHIFT 8
161 …_PCI_TYPE0_SERREN_K2 (0x1<<8) // Enables Error Re…
162 …CIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2_SHIFT 8
206 …R_ENA_BB (0x1<<8) // When set, this b…
207 …CIEIP_REG_STATUS_COMMAND_SERR_ENA_BB_SHIFT 8
243 … (0xff<<8) // Programming inte…
244 …CIEIP_REG_PCIEEP_REV_PI_E5_SHIFT 8
252 …_ID_PROGRAM_INTERFACE_K2 (0xff<<8) // Class Code Progr…
253 …CIEIP_REG_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2_SHIFT 8
261 …_CODE_BB (0xffffff<<8) // The 24-bit Class…
262 …CIEIP_REG_REV_ID_CLASS_CODE_CLASS_CODE_BB_SHIFT 8
266 … (0xff<<8) // Master latency t…
267 …CIEIP_REG_PCIEEP_CLSIZE_LT_E5_SHIFT 8
272 … (0xff<<24) // The BIST register functions are not supported. All 8 bits of the BIST reg…
277 …TENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2 (0xff<<8) // Does not apply t…
278 …CIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2_SHIFT 8
288 …ELINESIZE_LATENCY_TIMER_BB (0xff<<8) // This register do…
289 …CIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_BB_SHIFT 8
290 …EADER_TYPE_BB (0xff<<16) // The 8-bit Header Type regi…
292 …IST_BB (0xff<<24) // The 8-bit BIST register is…
452 … (0xff<<0) // The 8-bit Capabilities Poi…
457 … (0xff<<8) // Interrupt pin. I…
458 …CIEIP_REG_PCIEEP_INT_INTA_E5_SHIFT 8
466 …NT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2 (0xff<<8) // PCI Compatible I…
467 …CIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2_SHIFT 8
469 …E_INT_LINE_BB (0xff<<0) // The 8-bit Interrupt Line r…
471 …T_LINE_INT_PIN_BB (0xff<<8) // The 8-bit Interrupt P…
472 …CIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_INT_PIN_BB_SHIFT 8
480 …P_E5 (0xff<<8) // Next capability …
481 …CIEIP_REG_PCIEEP_PM_CAP_ID_NCP_E5_SHIFT 8
499 …PM_NEXT_POINTER_K2 (0xff<<8) // Next Capability …
500 …CIEIP_REG_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_K2_SHIFT 8
522 …NS_E5 (0x1<<8) // PME enable. A va…
523 …CIEIP_REG_PCIEEP_PM_CTL_PMEENS_E5_SHIFT 8
541 …_ENABLE_K2 (0x1<<8) // PME Enable. Th…
542 …CIEIP_REG_CON_STATUS_REG_PME_ENABLE_K2_SHIFT 8
556 … (0xff<<0) // The 8-bit Power Management Capability ID is set to 1 to indicate…
558 …PTR_BB (0xff<<8) // This value conti…
559 …CIEIP_REG_PM_CAP_PM_NEXT_CAP_PTR_BB_SHIFT 8
595 …BB (0x1<<8) // This bit enables…
596 …CIEIP_REG_PM_CSR_PME_ENABLE_BB_SHIFT 8
610 …_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_K2 (0xff<<8) // MSI Capability N…
611 …CIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_K2_SHIFT 8
623 … (0xff<<0) // The 8-bit VPD Capability ID is set to 3 to indicate that …
625 …P_PTR_BB (0xff<<8) // This value conti…
626 …CIEIP_REG_VPD_CAP_VPD_NEXT_CAP_PTR_BB_SHIFT 8
643 … (0xff<<0) // The 8-bit MSI Capability ID is set to 5 to indicate that …
645 …P_PTR_BB (0xff<<8) // This value conti…
646 …CIEIP_REG_MSI_CAP_MSI_NEXT_CAP_PTR_BB_SHIFT 8
676 …CP_E5 (0xff<<8) // Next capability …
677 …CIEIP_REG_PCIEEP_E_CAP_LIST_NCP_E5_SHIFT 8
689 …XT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2 (0xff<<8) // PCIE Next Capabi…
690 …CIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2_SHIFT 8
752 …_EN_E5 (0x1<<8) // Extended tag fie…
753 …CIEIP_REG_PCIEEP_DEV_CTL_ETF_EN_E5_SHIFT 8
789 …ICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2 (0x1<<8) // Extended Tag Fie…
790 …CIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2_SHIFT 8
872 …PM_E5 (0x1<<8) // Enable clock pow…
873 …CIEIP_REG_PCIEEP_LINK_CTL_ECPM_E5_SHIFT 8
909 …STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2 (0x1<<8) // Enable Clock Pow…
910 …CIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2_SHIFT 8
944 …OM64S_E5 (0x1<<8) // 64-bit AtomicOp …
945 …CIEIP_REG_PCIEEP_DEV_CAP2_ATOM64S_E5_SHIFT 8
979 …S2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2 (0x1<<8) // 64 Bit AtomicOp …
980 …CIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2_SHIFT 8
1004 …0_RQ_E5 (0x1<<8) // ID based orderin…
1005 …CIEIP_REG_PCIEEP_DEV_CTL2_ID0_RQ_E5_SHIFT 8
1027 …VICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2 (0x1<<8) // IDO Request Enab…
1028 …CIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2_SHIFT 8
1038 …LS_E5 (0x1<<8) // Crosslink suppor…
1039 …CIEIP_REG_PCIEEP_LINK_CAP2_CLS_E5_SHIFT 8
1047 …_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2 (0x1<<8) // Cross Link Suppo…
1048 …CIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2_SHIFT 8
1052 … 0x1 = 2.5 Gb/s target link speed. 0x2 = 5 Gb/s target link speed. 0x3 = 8 Gb/s target link spe…
1105 … (0xf<<12) // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The ac…
1126 …CAP_PTR_BB (0xff<<8) // This value conti…
1127 …CIEIP_REG_MSIX_CAP_MSIX_NEXT_CAP_PTR_BB_SHIFT 8
1149 …E_NEXT_CAP_PTR_BB (0xff<<8) // This registers c…
1150 …CIEIP_REG_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_BB_SHIFT 8
1162 …RL_NCP_E5 (0xff<<8) // Next capability …
1163 …CIEIP_REG_PCIEEP_MSIX_CAP_CNTRL_NCP_E5_SHIFT 8
1173 …T_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2 (0xff<<8) // MSI-X Next Capab…
1174 …CIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2_SHIFT 8
1227 …ROL_EXTENDED_TAG_EN_BB (0x1<<8) // Extended Tag Fie…
1228 …CIEIP_REG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_BB_SHIFT 8
1299 …L_EN_CLK_PW_MGMT_BB (0x1<<8) // Enable Clock Pow…
1300 …CIEIP_REG_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_BB_SHIFT 8
1346 …_E5 (0xff<<8) // Next capability …
1347 …CIEIP_REG_PCIEEP_VPD_BASE_NCO_E5_SHIFT 8
1355 …FFSET_K2 (0xff<<8) // VPD Pointer to N…
1356 …CIEIP_REG_VPD_BASE_VPD_NEXT_OFFSET_K2_SHIFT 8
1389 …ROL_2_IDO_REQ_ENABLE_BB (0x1<<8) // IDO Request Enab…
1390 …CIEIP_REG_DEVICE_STATUS_CONTROL_2_IDO_REQ_ENABLE_BB_SHIFT 8
1730 …T_RNRS_E5 (0x1<<8) // REPLAY_NUM rollo…
1731 …CIEIP_REG_PCIEEP_COR_ERR_STAT_RNRS_E5_SHIFT 8
1747 …F_REPLAY_NO_ROLEOVER_STATUS_K2 (0x1<<8) // REPLAY_NUM Rollo…
1748 …CIEIP_REG_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_K2_SHIFT 8
1766 …LAY_NUM_RO_STATUS_BB (0x1<<8) // REPLAY_NUM Rollo…
1767 …CIEIP_REG_CORR_ERR_STATUS_RPLAY_NUM_RO_STATUS_BB_SHIFT 8
1781 …_RNRM_E5 (0x1<<8) // REPLAY_NUM rollo…
1782 …CIEIP_REG_PCIEEP_COR_ERR_MSK_RNRM_E5_SHIFT 8
1798 …REPLAY_NO_ROLEOVER_MASK_K2 (0x1<<8) // REPLAY_NUM Rollo…
1799 …CIEIP_REG_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_K2_SHIFT 8
1817 …_BB (0x1<<8) // REPLAY_NUM Rollo…
1818 …CIEIP_REG_CORR_ERR_MASK_RNRS_BB_SHIFT 8
1834 …_CNTRL_CE_E5 (0x1<<8) // ECRC check enabl…
1835 …CIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_CE_E5_SHIFT 8
1851 …FF_ECRC_CHECK_EN_K2 (0x1<<8) // ECRC Check Enabl…
1852 …CIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_K2_SHIFT 8
1866 …L_ECRCEN_BB (0x1<<8) // ECRC Check Enable
1867 …CIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCEN_BB_SHIFT 8
1872 …_DWORD_SECOND_BYTE_K2 (0xff<<8) // Byte 1 of Header…
1873 …CIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_K2_SHIFT 8
1883 …D_DWORD_SECOND_BYTE_K2 (0xff<<8) // Byte 1 of Header…
1884 …CIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_K2_SHIFT 8
1894 …_DWORD_SECOND_BYTE_K2 (0xff<<8) // Byte 1 of Header…
1895 …CIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_K2_SHIFT 8
1905 …H_DWORD_SECOND_BYTE_K2 (0xff<<8) // Byte 1 of Header…
1906 …CIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_K2_SHIFT 8
1919 …F_CFG_TLP_PFX_LOG_1_SECOND_BYTE_K2 (0xff<<8) // Byte 1 of Error …
1920 …CIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_K2_SHIFT 8
1929 …F_CFG_TLP_PFX_LOG_2_SECOND_BYTE_K2 (0xff<<8) // Byte 1 Error TLP…
1930 …CIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_K2_SHIFT 8
1946 …F_CFG_TLP_PFX_LOG_3_SECOND_BYTE_K2 (0xff<<8) // Byte 1 Error TLP…
1947 …CIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_K2_SHIFT 8
1957 …F_CFG_TLP_PFX_LOG_4_SECOND_BYTE_K2 (0xff<<8) // Byte 1 Error TLP…
1958 …CIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_K2_SHIFT 8
1984 …EG_1_VC_REFERENCE_CLOCK_K2 (0x3<<8) // Reference Clock.
1985 …CIEIP_REG_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_K2_SHIFT 8
2030 …TA_DSCALE_BB (0x3<<8) // Data Scale
2031 …CIEIP_REG_PWR_BDGT_DATA_DSCALE_BB_SHIFT 8
2062 …TA_DS_E5 (0x3<<8) // Data scale.
2063 …CIEIP_REG_PCIEEP_PB_DATA_DS_E5_SHIFT 8
2108 …NFN_E5 (0xff<<8) // Next function nu…
2109 …CIEIP_REG_PCIEEP_ARI_CAP_CTL_NFN_E5_SHIFT 8
2129 …C_CONTROL_UNUSED0_BB (0x7fffff<<8) //
2130 …CIEIP_REG_VC_RSRC_CONTROL_UNUSED0_BB_SHIFT 8
2166 …PB_DATA_SCALE_K2 (0x3<<8) // Data Scale.
2167 …CIEIP_REG_DATA_REG_PB_PB_DATA_SCALE_K2_SHIFT 8
2188 …UTP_E5 (0xf<<8) // Lane 0 upstream …
2189 …CIEIP_REG_PCIEEP_EQ_CTL01_L0UTP_E5_SHIFT 8
2215 …UTP_E5 (0xf<<8) // Lane 2 upstream …
2216 …CIEIP_REG_PCIEEP_EQ_CTL23_L2UTP_E5_SHIFT 8
2244 …UTP_E5 (0xf<<8) // Lane 4 upstream …
2245 …CIEIP_REG_PCIEEP_EQ_CTL45_L4UTP_E5_SHIFT 8
2261 …N_NUM_K2 (0xff<<8) // Next Function Nu…
2262 …CIEIP_REG_CAP_REG_ARI_NEXT_FUN_NUM_K2_SHIFT 8
2275 …UTP_E5 (0xf<<8) // Lane 6 upstream …
2276 …CIEIP_REG_PCIEEP_EQ_CTL67_L6UTP_E5_SHIFT 8
2293 … (0xf<<0) // Lane 8 downstream port tran…
2295 … (0x7<<4) // Lane 8 downstream port rece…
2297 … (0xf<<8) // Lane 8 upstream port t…
2298 …CIEIP_REG_PCIEEP_EQ_CTL89_L8UTP_E5_SHIFT 8
2299 … (0x7<<12) // Lane 8 upstream port receiv…
2315 …L10UTP_E5 (0xf<<8) // Lane 10 upstream…
2316 …CIEIP_REG_PCIEEP_EQ_CTL1011_L10UTP_E5_SHIFT 8
2344 …L12UTP_E5 (0xf<<8) // Lane 12 upstream…
2345 …CIEIP_REG_PCIEEP_EQ_CTL1213_L12UTP_E5_SHIFT 8
2366 …L14UTP_E5 (0xf<<8) // Lane 14 upstream…
2367 …CIEIP_REG_PCIEEP_EQ_CTL1415_L14UTP_E5_SHIFT 8
2386 …REG_USP_TX_PRESET0_K2 (0xf<<8) // Upstream Port 8.…
2387 …CIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_K2_SHIFT 8
2410 …REG_USP_TX_PRESET2_K2 (0xf<<8) // Upstream Port 8.…
2411 …CIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_K2_SHIFT 8
2428 …REG_USP_TX_PRESET4_K2 (0xf<<8) // Upstream Port 8.…
2429 …CIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_K2_SHIFT 8
2446 …REG_USP_TX_PRESET6_K2 (0xf<<8) // Upstream Port 8.…
2447 …CIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_K2_SHIFT 8
2521 …R_NEXT_FUNCTION_NUMBER_BB (0xff<<8) // Next Function Nu…
2522 …CIEIP_REG_ARI_CONTROL_REGISTER_NEXT_FUNCTION_NUMBER_BB_SHIFT 8
2563 …L0123_L1DTP_E5 (0xf<<8) // Downstream port …
2564 …CIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L1DTP_E5_SHIFT 8
2589 … (0x1<<4) // When set, the device is permitted to locate VF in Func Number 8 to 255. This field i…
2600 …L4567_L5DTP_E5 (0xf<<8) // Downstream port …
2601 …CIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L5DTP_E5_SHIFT 8
2623 … (0xf<<0) // Downstream port 16.0 GT/s transmitter preset 8.
2625 … (0xf<<4) // Upstream port 16.0 GT/s transmitter preset 8.
2627 …L891011_L9DTP_E5 (0xf<<8) // Downstream port …
2628 …CIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L9DTP_E5_SHIFT 8
2654 …L12131415_L13DTP_E5 (0xf<<8) // Downstream port …
2655 …CIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L13DTP_E5_SHIFT 8
2707 …_STAT0_MPL_E5 (0xff<<8) // Margin payload f…
2708 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_MPL_E5_SHIFT 8
2732 …_STAT1_MPL_E5 (0xff<<8) // Margin payload f…
2733 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_MPL_E5_SHIFT 8
2767 …_STAT2_MPL_E5 (0xff<<8) // Margin payload f…
2768 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_MPL_E5_SHIFT 8
2792 …_STAT3_MPL_E5 (0xff<<8) // Margin payload f…
2793 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_MPL_E5_SHIFT 8
2827 …_STAT4_MPL_E5 (0xff<<8) // Margin payload f…
2828 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_MPL_E5_SHIFT 8
2852 …_STAT5_MPL_E5 (0xff<<8) // Margin payload f…
2853 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_MPL_E5_SHIFT 8
2885 …_STAT6_MPL_E5 (0xff<<8) // Margin payload f…
2886 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_MPL_E5_SHIFT 8
2910 …_STAT7_MPL_E5 (0xff<<8) // Margin payload f…
2911 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_MPL_E5_SHIFT 8
2927 …G_TPH_REQ_EXTENDED_TPH_K2 (0x1<<8) // Extended TPH Req…
2928 …CIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2_SHIFT 8
2942 …_STAT8_MPL_E5 (0xff<<8) // Margin payload f…
2943 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_MPL_E5_SHIFT 8
2955 …G_REG_TPH_REQ_CTRL_REQ_EN_K2 (0x3<<8) // TPH Requester En…
2956 …CIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2_SHIFT 8
2971 …_STAT9_MPL_E5 (0xff<<8) // Margin payload f…
2972 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_MPL_E5_SHIFT 8
2984 …TPH_REQ_ST_TABLE_HIGHER_0_K2 (0xff<<8) // ST Table 0 Upper…
2985 …CIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2_SHIFT 8
2996 …_STAT10_MPL_E5 (0xff<<8) // Margin payload f…
2997 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_MPL_E5_SHIFT 8
3013 …FECTIVE_GRANULARITY_BB (0xff<<8) // Field provides i…
3014 …CIEIP_REG_PTM_CTRL_REG_PTM_EFFECTIVE_GRANULARITY_BB_SHIFT 8
3022 …_STAT11_MPL_E5 (0xff<<8) // Margin payload f…
3023 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_MPL_E5_SHIFT 8
3039 …_STAT12_MPL_E5 (0xff<<8) // Margin payload f…
3040 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_MPL_E5_SHIFT 8
3063 …_STAT13_MPL_E5 (0xff<<8) // Margin payload f…
3064 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_MPL_E5_SHIFT 8
3093 …_STAT14_MPL_E5 (0xff<<8) // Margin payload f…
3094 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_MPL_E5_SHIFT 8
3110 …_STAT15_MPL_E5 (0xff<<8) // Margin payload f…
3111 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_MPL_E5_SHIFT 8
3127 …0x20 // The read-only value of this register is controlled by setting bit 8 of the EXT_CAP_ENA f…
3152 … (0x1<<7) // when Set, it indicates function will operate with Bar sized to 8M. Value reflected he…
3154 …CAPABILITY_BB (0x1<<8) // when Set, it ind…
3155 …CIEIP_REG_RBAR_CAP_SIZE_16M_CAPABILITY_BB_SHIFT 8
3192 …BB (0x1f<<8) // When this reg is…
3193 …CIEIP_REG_RBAR_CTRL_BAR_SIZE_BB_SHIFT 8
3225 …_EXTENDED_TPH_REQ_SUPP_BB (0x1<<8) // If Set function …
3226 …CIEIP_REG_TPH_REQ_CAPABILITY_EXTENDED_TPH_REQ_SUPP_BB_SHIFT 8
3241 …H_REQUESTER_ENABLE_BB (0x3<<8) // Value indicates …
3242 …CIEIP_REG_TPH_REQ_CONTROL_TPH_REQUESTER_ENABLE_BB_SHIFT 8
3274 …SUB_CMN_MODE_UP_TIME_BB (0xff<<8) // Time in us that …
3275 …CIEIP_REG_PML1_SUB_CAP_REG_L1SUB_CMN_MODE_UP_TIME_BB_SHIFT 8
3298 …OMMON_MODE_RESTORE_TIME_BB (0xff<<8) // For downstream p…
3299 …CIEIP_REG_PML1_SUB_CONTROL1_COMMON_MODE_RESTORE_TIME_BB_SHIFT 8
3320 …UB_CONTROL2_RSVD_BB (0xffffff<<8) //
3321 …CIEIP_REG_PML1_SUB_CONTROL2_RSVD_BB_SHIFT 8
3350 …_EXT_E5 (0x1<<8) // Extended TPH req…
3351 …CIEIP_REG_PCIEEP_TPH_REQ_CAP_EXT_E5_SHIFT 8
3361 …_CREN_E5 (0x3<<8) // TPH requestor en…
3362 …CIEIP_REG_PCIEEP_TPH_REQ_CTL_CREN_E5_SHIFT 8
3366 …_STH_E5 (0xff<<8) // ST table 0 upper…
3367 …CIEIP_REG_PCIEEP_TPH_ST_TABLE_STH_E5_SHIFT 8
3405 …ROL_REG_EVENT_COUNTER_LANE_SELECT_K2 (0xf<<8) // Event Counter La…
3406 …CIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_K2_SHIFT 8
3407 …_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within…
3413 …_CONTROL_REG_TIME_BASED_DURATION_SELECT_K2 (0xff<<8) // Time-based Durat…
3414 …CIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_K2_SHIFT 8
3436 …0_CRC_TYPE_K2 (0xf<<8) // Error injection …
3437 …CIEIP_REG_EINJ0_CRC_REG_EINJ0_CRC_TYPE_K2_SHIFT 8
3441 …INJ1_SEQNUM_TYPE_K2 (0x1<<8) // Sequence number …
3442 …CIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_K2_SHIFT 8
3448 …J2_DLLP_TYPE_K2 (0x3<<8) // DLLP Type. Selec…
3449 …CIEIP_REG_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_K2_SHIFT 8
3450 …ess:RW DataWidth:0x20 // Error Injection Control 3 (Symbol Error). When 8b/10b encoding is use…
3453 …OL_TYPE_K2 (0x7<<8) // Error Type. 8b/10b encodi…
3454 …CIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_K2_SHIFT 8
3458 …_UPDFC_TYPE_K2 (0x7<<8) // Update-FC type. …
3459 …CIEIP_REG_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_K2_SHIFT 8
3467 …INJ5_SPECIFIED_TLP_K2 (0x1<<8) // Specified TLP. S…
3468 …CIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_K2_SHIFT 8
3469 …ess when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TL…
3470 …ess when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TL…
3471 …ess when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TL…
3472 …ess when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TL…
3473 …ess when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TL…
3481 …ess when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TL…
3497 …ECVS_E5 (0xff<<8) // Egress control v…
3498 …CIEIP_REG_PCIEEP_ACS_CAP_CTL_ECVS_E5_SHIFT 8
3513 …ess when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TL…
3519 …ess when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TL…
3527 …ess when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TL…
3537 …ess when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TL…
3545 …ess when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TL…
3564 …M_MD_SUPP_E5 (0xff<<8) // Port common mode…
3565 …CIEIP_REG_PCIEEP_L1SUB_CAP_COM_MD_SUPP_E5_SHIFT 8
3570 …ess when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TL…
3585 …_COM_MODE_E5 (0xff<<8) // Common mode rest…
3586 …CIEIP_REG_PCIEEP_L1SUB_CTL1_T_COM_MODE_E5_SHIFT 8
3591 …ess when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TL…
3600 …ess when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TL…
3604 …ON_CTRL_DNSTREAM_COMP_TX_PRESETS0_BB (0xf<<8) // Latest Transmitt…
3605 …CIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS0_BB_SHIFT 8
3625 …ess when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TL…
3629 …ON_CTRL_DNSTREAM_COMP_TX_PRESETS2_BB (0xf<<8) // Latest Transmitt…
3630 …CIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS2_BB_SHIFT 8
3648 …G_MPIDW_E5 (0x1f<<8) // Default value fo…
3649 …CIEIP_REG_PCIEEP_PASID_CTL_REG_MPIDW_E5_SHIFT 8
3656 …ess when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TL…
3660 …ON_CTRL_DNSTREAM_COMP_TX_PRESETS4_BB (0xf<<8) // Latest Transmitt…
3661 …CIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS4_BB_SHIFT 8
3684 …6_INVERTED_CONTROL_K2 (0x1<<8) // Inverted Error I…
3685 …CIEIP_REG_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_K2_SHIFT 8
3691 …ON_CTRL_DNSTREAM_COMP_TX_PRESETS6_BB (0xf<<8) // Latest Transmitt…
3692 …CIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS6_BB_SHIFT 8
3715 …ON_CTRL_DNSTREAM_COMP_TX_PRESETS8_BB (0xf<<8) // Latest Transmitt…
3716 …CIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS8_BB_SHIFT 8
3736 …EV_CNTR_LANE_SEL_E5 (0xf<<8) // Event counter la…
3737 …CIEIP_REG_PCIEEP_RAS_EC_CTL_EV_CNTR_LANE_SEL_E5_SHIFT 8
3743 …TION_CTRL_DNSTREAM_COMP_TX_PRESETS10_BB (0xf<<8) // Latest Transmitt…
3744 …CIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS10_BB_SHIFT 8
3761 …TION_CTRL_DNSTREAM_COMP_TX_PRESETS12_BB (0xf<<8) // Latest Transmitt…
3762 …CIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS12_BB_SHIFT 8
3778 …TBASE_DUR_SEL_E5 (0xff<<8) // Time-based durat…
3779 …CIEIP_REG_PCIEEP_RAS_TBA_CTL_TBASE_DUR_SEL_E5_SHIFT 8
3785 …TION_CTRL_DNSTREAM_COMP_TX_PRESETS14_BB (0xf<<8) // Latest Transmitt…
3786 …CIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS14_BB_SHIFT 8
3805 …2.5GT/s, 8.0GT/s or higher: - 0x0: 1 - 0x1: 4 - 0x2: 8 - 0x3: 16 5.0GT/s: - 0x0: 2 - 0x1: 8 …
3816 …RECT_RECIDLE_TO_CONFIG_K2 (0x1<<8) // Direct Recovery.…
3817 …CIEIP_REG_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_K2_SHIFT 8
3844 …REG_PIPE_POWER_DOWN_K2 (0x7<<8) // PIPE:PowerDown. …
3845 …CIEIP_REG_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_K2_SHIFT 8
3848 …qualization_done_8GT_data_rate - 7: equalization_done_16GT_data_rate - 15:8: idle_to_rlock_trans…
3851 …K - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h: S_L1_EXIT - 8h: S_L23RDY - 9h: S_…
3853 …NTERNAL_PM_SSTATE_K2 (0xf<<8) // Internal PM Stat…
3854 …CIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_K2_SHIFT 8
3888 …L0_EINJ0_CRC_TYPE_E5 (0xf<<8) // Error injection …
3889 …CIEIP_REG_PCIEEP_RAS_EINJ_CTL0_EINJ0_CRC_TYPE_E5_SHIFT 8
3899 …REDIT_DATA0_K2 (0xfff<<8) // Credit Data0. C…
3900 …CIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA0_K2_SHIFT 8
3906 …L1_EINJ1_SEQNUM_TYPE_E5 (0x1<<8) // Sequence number …
3907 …CIEIP_REG_PCIEEP_RAS_EINJ_CTL1_EINJ1_SEQNUM_TYPE_E5_SHIFT 8
3918 …L2_EINJ2_DLLP_TYPE_E5 (0x3<<8) // DLLP type. Sele…
3919 …CIEIP_REG_PCIEEP_RAS_EINJ_CTL2_EINJ2_DLLP_TYPE_E5_SHIFT 8
3923 …SYMBOL_TYPE_E5 (0x7<<8) // Error type, 8 b/10 b enco…
3924 …CIEIP_REG_PCIEEP_RAS_EINJ_CTL3_EINJ3_SYMBOL_TYPE_E5_SHIFT 8
3928 …L4_EINJ4_VC_TYPE_E5 (0x7<<8) // Update-FC type. …
3929 …CIEIP_REG_PCIEEP_RAS_EINJ_CTL4_EINJ4_VC_TYPE_E5_SHIFT 8
3948 …L5_EINJ5_SP_TLP_E5 (0x1<<8) // Specified TLP. …
3949 …CIEIP_REG_PCIEEP_RAS_EINJ_CTL5_EINJ5_SP_TLP_E5_SHIFT 8
4098 …L6PE_EINJ6_INV_CNTRL_E5 (0x1<<8) // Inverted error i…
4099 …CIEIP_REG_PCIEEP_RAS_EINJ_CTL6PE_EINJ6_INV_CNTRL_E5_SHIFT 8
4114 …L_OFF_ERROR_INJ_COUNT_K2 (0xff<<8) // Error injection …
4115 …CIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_K2_SHIFT 8
4121 …CATION_OFF_LOC_FIRST_CORR_ERROR_K2 (0xff<<8) // Location/ID of t…
4122 …CIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_K2_SHIFT 8
4130 …LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_K2 (0xff<<8) // Location/ID of t…
4131 …CIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_K2_SHIFT 8
4146 … specification. Gen1 or Gen3 0x0 = 1. 0x1 = 4. 0x2 = 8. 0x3 - 16. Gen2 0x0 = 2. 0x1 = 8. …
4160 …_DIR_RECIDLE_CONFIG_E5 (0x1<<8) // Direct Recovery.…
4161 …CIEIP_REG_PCIEEP_RAS_SD_CTL2_DIR_RECIDLE_CONFIG_E5_SHIFT 8
4207 …_GRAN_K2 (0xff<<8) // PTM Local Clock …
4208 …CIEIP_REG_PTM_CAP_OFF_PTM_CLK_GRAN_K2_SHIFT 8
4214 …SSM_PIPE_PWR_DWN_E5 (0x7<<8) // PIPE:PowerDown. …
4215 …CIEIP_REG_PCIEEP_RAS_SD_L1LTSSM_PIPE_PWR_DWN_E5_SHIFT 8
4225 …_GRAN_K2 (0xff<<8) // PTM Effective Gr…
4226 …CIEIP_REG_PTM_CONTROL_OFF_EFF_GRAN_K2_SHIFT 8
4230 …USPM_INT_PM_SSTATE_E5 (0xf<<8) // Internal PM stat…
4231 …CIEIP_REG_PCIEEP_RAS_SD_STATUSPM_INT_PM_SSTATE_E5_SHIFT 8
4272 …L3FC_CREDIT_DATA0_E5 (0xfff<<8) // Credit data 0. …
4273 …CIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_DATA0_E5_SHIFT 8
4283 …_PTM_REQ_LONG_TIMER_K2 (0xff<<8) // PTM Requester Lo…
4284 …CIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_LONG_TIMER_K2_SHIFT 8
4302 …TL1_EXT_EQ_TIMEOUT_E5 (0x3<<8) // Extends EQ Phase…
4303 …CIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_EXT_EQ_TIMEOUT_E5_SHIFT 8
4391 …ZE_BB (0xff<<8) // These bits contr…
4392 …CIEIP_REG_CONFIG_2_ROM_BAR_SIZE_BB_SHIFT 8
4401 …_BYTE_BB (0xff<<8) // This value is re…
4402 …CIEIP_REG_CONFIG_3_REG_STICKY_BYTE_BB_SHIFT 8
4425 …_PRG_BB (0xff<<8) // This is the valu…
4426 …CIEIP_REG_PM_DATA_A_PM_DATA_1_PRG_BB_SHIFT 8
4435 …_PRG_BB (0xff<<8) // This is the valu…
4436 …CIEIP_REG_PM_DATA_B_PM_DATA_5_PRG_BB_SHIFT 8
4454 …IZ_BAR3_SIZE_HIEXT_BB (0xf<<8) // These bits contr…
4455 …CIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR3_SIZE_HIEXT_BB_SHIFT 8
4536 …P_REG_0_8MB_K2 (0x1<<7) // Up to 8MB BAR Supported. N…
4538 …EG_RESBAR_CAP_REG_0_16MB_K2 (0x1<<8) // Up to 16MB BAR S…
4539 …CIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_K2_SHIFT 8
4556 …_REG_0_8GB_K2 (0x1<<17) // Up to 8GB BAR Supported. N…
4587 …EG_RESBAR_CTRL_REG_BAR_SIZE_K2 (0x1f<<8) // BAR Size. Note…
4588 …CIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_K2_SHIFT 8
4609 …L_ERR_INJ_CNT_E5 (0xff<<8) // Error injection …
4610 …CIEIP_REG_PCIEEP_RASDP_CE_ICTL_ERR_INJ_CNT_E5_SHIFT 8
4621 …_LOC_FIRST_CORR_ERR_E5 (0xff<<8) // Location/ID of t…
4622 …CIEIP_REG_PCIEEP_RASDP_CE_LOC_LOC_FIRST_CORR_ERR_E5_SHIFT 8
4635 …C_LOC_FIRST_UCORR_ERR_E5 (0xff<<8) // Location/ID of t…
4636 …CIEIP_REG_PCIEEP_RASDP_UCE_LOC_LOC_FIRST_UCORR_ERR_E5_SHIFT 8
4658 …_MASK_CAPABLE_BB (0x1<<8) // This value contr…
4659 …CIEIP_REG_REG_ID_VAL4_MSI_PV_MASK_CAPABLE_BB_SHIFT 8
4745 …_E5 (0xff<<8) // PTM local clock …
4746 …CIEIP_REG_PCIEEP_PTM_CAP_CLKG_E5_SHIFT 8
4752 …GRAN_E5 (0xff<<8) // PTM effective gr…
4753 …CIEIP_REG_PCIEEP_PTM_CTL_EFF_GRAN_E5_SHIFT 8
4771 …from the pm_data register when the DATA_SEL value in the PM_CSR register is 8. This is the power d…
4773 …_DATA_C_RESERVED0_BB (0xffffff<<8) //
4774 …CIEIP_REG_REG_PM_DATA_C_RESERVED0_BB_SHIFT 8
4782 …RLT_E5 (0xff<<8) // PTM requester lo…
4783 …CIEIP_REG_PCIEEP_PTM_REQ_CTL_RLT_E5_SHIFT 8
4830 … (0x3f<<8) // BAR Size. PEM advertises the minimum allowable BAR size of 0x0 (1MB) but w…
4831 …CIEIP_REG_PCIEEP_RBAR_CTL_RBARS_E5_SHIFT 8
5032 …T2_CAP_ADDR_RW_BB (0xffffff<<8) //
5033 …CIEIP_REG_REG_EXT2_CAP_ADDR_RW_BB_SHIFT 8
5052 …_CMN_MODE_UP_TIME_BB (0xff<<8) // Time in us that …
5053 …CIEIP_REG_REG_L1SUB_CAP_L1SUB_CMN_MODE_UP_TIME_BB_SHIFT 8
5086 …G_RC_USER_MEM_LO1_UNUSED_1_BB (0xff<<8) //
5087 …CIEIP_REG_REG_RC_USER_MEM_LO1_UNUSED_1_BB_SHIFT 8
5098 …G_RC_USER_MEM_LO2_UNUSED_1_BB (0xff<<8) //
5099 …CIEIP_REG_REG_RC_USER_MEM_LO2_UNUSED_1_BB_SHIFT 8
5129 … (0x1<<7) // when Set, it indicates function will operate with Bar sized to 8M. Value programmed h…
5131 …SIZE_16M_CAPABILITY_BB (0x1<<8) // when Set, it ind…
5132 …CIEIP_REG_REG_RESIZEBAR_CAP_SIZE_16M_CAPABILITY_BB_SHIFT 8
5156 …he tl_reg private register space. Each PF is expected to have a multiple of 8 VFs and so this fiel…
5169 …2_SIZE_OF_VF_BB (0xf<<8) // This field influ…
5170 …CIEIP_REG_REG_VF_BAR_REG_BAR2_SIZE_OF_VF_BB_SHIFT 8
5183 …d indicates page sizes supported by the PF. PFs are required to support 4k, 8K, 64K, 256K, 1MB and…
5189 …T_CAP_EN_BB (0x3f<<8) // Enable for the V…
5190 …CIEIP_REG_REG_VF_CAP_EN_VF_EXT_CAP_EN_BB_SHIFT 8
5214 …register. The number of VFs assigned to a PF is assumed to be a multiple of 8. Software should pro…
5221 …R4_NSP_BB (0xf<<8) // This field descr…
5222 …CIEIP_REG_REG_VF_NSP_PF_VFBAR4_NSP_BB_SHIFT 8
5249 …th, Max_Payload_Size, and speed. The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe…
5258 …FORCED_LTSSM_E5 (0xf<<8) // Forced link comm…
5259 …CIEIP_REG_PCIEEP_PORT_FLINK_FORCED_LTSSM_E5_SHIFT 8
5269 …CED_LTSSM_K2 (0xf<<8) // Forced Link Comm…
5270 …CIEIP_REG_PORT_FORCE_OFF_FORCED_LTSSM_K2_SHIFT 8
5280 …TS_E5 (0xff<<8) // The number of fa…
5281 …CIEIP_REG_PCIEEP_ACK_FREQ_N_FTS_E5_SHIFT 8
5286 …latency. Values correspond to: 0x0 = 1 ms. 0x1 = 2 ms. 0x2 = 4 ms. 0x3 = 8 ms. 0x4 = 16 ms. 0…
5293 …_ACK_N_FTS_K2 (0xff<<8) // N_FTS. The numbe…
5294 …CIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_K2_SHIFT 8
5299 …nce Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - …
5320 …T_CTL_LINK_RATE_E5 (0xf<<8) // Reserved.
5321 …CIEIP_REG_PCIEEP_PORT_CTL_LINK_RATE_E5_SHIFT 8
5349 …_LINK_RATE_K2 (0xf<<8) // LINK_RATE is an …
5350 …CIEIP_REG_PORT_LINK_CTRL_OFF_LINK_RATE_K2_SHIFT 8
5370 …ed values are: 0x0 = 1 lane. 0x1 = 2 lanes. 0x3 = 4 lanes. 0x7 = 8 lanes. 0xF = 16 l…
5470 …2_RESERVED31_8_E5 (0xffffff<<8) // Reserved.
5471 …CIEIP_REG_PCIEEP_FILT_MSK2_RESERVED31_8_E5_SHIFT 8
5483 …ion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
5485 …ion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
5493 …ion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
5495 …ion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
5503 …ion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
5505 …ion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
5540 …R_VC1_E5 (0xff<<8) // WRR weight for V…
5541 …CIEIP_REG_PCIEEP_XMIT_ARB1_WRR_VC1_E5_SHIFT 8
5549 …R_WEIGHT_VC_1_K2 (0xff<<8) // WRR Weight for V…
5550 …CIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_K2_SHIFT 8
5558 …R_VC5_E5 (0xff<<8) // WRR weight for V…
5559 …CIEIP_REG_PCIEEP_XMIT_ARB2_WRR_VC5_E5_SHIFT 8
5567 …R_WEIGHT_VC_5_K2 (0xff<<8) // WRR Weight for V…
5568 …CIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_K2_SHIFT 8
5676 …_32DW_CHK_BB (0x1<<8) // Target mem Wr sh…
5677 …CIEIP_REG_TL_CONTROL_0_MEMWR_32DW_CHK_BB_SHIFT 8
5737 …C_CHK_BB (0x1<<8) // Enable Configura…
5738 …CIEIP_REG_TL_CONTROL_1_EN_TAC_CHK_BB_SHIFT 8
5796 …_MASK_BB (0x1<<8) // Unsupported Requ…
5797 …CIEIP_REG_TL_CONTROL_2_URES0_MASK_BB_SHIFT 8
5845 …ANES_E5 (0x1f<<8) // Predetermined nu…
5846 …CIEIP_REG_PCIEEP_GEN2_PORT_NLANES_E5_SHIFT 8
5864 …F_LANES_K2 (0x1f<<8) // Predetermined Nu…
5865 …CIEIP_REG_GEN2_CTRL_OFF_NUM_OF_LANES_K2_SHIFT 8
5866 …ical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1, depending on whic…
5895 …_CONTROL_3_TL_REG_TXCTRL_BB (0xff<<8) //
5896 …CIEIP_REG_TL_CONTROL_3_TL_REG_TXCTRL_BB_SHIFT 8
5899 …ink comes out of L1 into L0 due to PM_PME. The default value corresponds to 8 us and uses pulse_1u…
5927 …UNSPPORT_BB (0x1<<8) // This bit is set …
5928 …CIEIP_REG_TL_CTRLSTAT_5_ERR_UNSPPORT_BB_SHIFT 8
5982 … (0x1<<0) // This bit is used to disable function 8.
5998 …TROL_6_UNUSED_BB (0xffffff<<8) //
5999 …CIEIP_REG_TL_CONTROL_6_UNUSED_BB_SHIFT 8
6085 …ES2_MASK_BB (0x1<<8) // Unsupported Requ…
6086 …CIEIP_REG_TL_FUNC345_MASK_URES2_MASK_BB_SHIFT 8
6148 …R_UNSPPORT2_BB (0x1<<8) // This bit is set …
6149 …CIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT2_BB_SHIFT 8
6211 …ES5_MASK_BB (0x1<<8) // Unsupported Requ…
6212 …CIEIP_REG_TL_FUNC678_MASK_URES5_MASK_BB_SHIFT 8
6274 …R_UNSPPORT5_BB (0x1<<8) // Unsupported Requ…
6275 …CIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT5_BB_SHIFT 8
6340 … (0x7<<0) // Route the interrupt pin for Function 0 8o any of INTA to INTD…
6373 …_ALT_MSG_ERROR_BB (0x1<<8) // Based on 3.0 err…
6374 …CIEIP_REG_TL_RST_CTRL_ENABLE_ALT_MSG_ERROR_BB_SHIFT 8
6382 …FF_PULSE_BB (0x7f<<8) // Max number of PM…
6383 …CIEIP_REG_TL_OBFF_CTRL_MAX_OBFF_PULSE_BB_SHIFT 8
6405 …FUNC_9_HIDDEN_BB (0x1<<8) // Set if func9 is …
6406 …CIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_9_HIDDEN_BB_SHIFT 8
6451 …x20 // This register masks specific errors from setting pcie_err_attn for functions 8, 9, and 10.
6468 …URES8_MASK_BB (0x1<<8) // Unsupported Requ…
6469 …CIEIP_REG_TL_FUNC8TO10_MASK_URES8_MASK_BB_SHIFT 8
6514 … // This register stores the status of errors to generate pcie_err_attn for functions 8, 9, and 10.
6515 … (0x1<<0) // Poisoned Error Status detected for Function 8. If set, hw generate…
6517 … (0x1<<1) // Flow Control Protocol Error Status detected for Function 8, if set, generate pc…
6519 … (0x1<<2) // Completer Timeout Status detected for Function 8. If set, hw generate…
6521 … (0x1<<3) // Receive UR Status detectedfor Function 8. If set, generate pc…
6523 … (0x1<<4) // Unexpected Completion Status detected for Function 8, if set, generate pc…
6525 … (0x1<<5) // Receiver Overflow Status detected for Function 8. If set, hw generate…
6527 … (0x1<<6) // Malformed TLP Status detected for Function 8. If set, hw generate…
6529 … (0x1<<7) // ECRC Error TLP Status detected for Function 8. If set, hw generate…
6531 … (0x1<<8) // Unsupported Request Error Status detected for F…
6532 …CIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT8_BB_SHIFT 8
6594 …_URES11_MASK_BB (0x1<<8) // Unsupported Requ…
6595 …CIEIP_REG_TL_FUNC11TO13_MASK_URES11_MASK_BB_SHIFT 8
6660 …_ERR_UNSPPORT11_BB (0x1<<8) // Unsupported Requ…
6661 …CIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT11_BB_SHIFT 8
6709 …L_DSG3_E5 (0x1<<8) // Disable scramble…
6710 …CIEIP_REG_PCIEEP_PHY_GEN3_CTL_DSG3_E5_SHIFT 8
6729 …8GT/s EQ TS2 disable. The base spec defines that USP can optionally send 8GT EQ TS2 and it means U…
6736 …/s when operating at 8 GT/s or higher. - 1: The receiver does not comply with the ZRX-DC paramete…
6738 …ISABLE_SCRAMBLER_GEN_3_K2 (0x1<<8) // Disable Scramble…
6739 …CIEIP_REG_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_K2_SHIFT 8
6775 …_URES14_MASK_BB (0x1<<8) // Unsupported Requ…
6776 …CIEIP_REG_TL_FUNC14TO15_MASK_URES14_MASK_BB_SHIFT 8
6818 …_ERR_UNSPPORT14_BB (0x1<<8) // Unsupported Requ…
6819 …CIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNSPPORT14_BB_SHIFT 8
6853 …E_PF4_E5 (0x3<<8) // PF4 hide control…
6854 …CIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF4_E5_SHIFT 8
6886 …4_HIDE_CONTROL_K2 (0x3<<8) // Operates in the …
6887 …CIEIP_REG_PF_HIDE_CONTROL_PF4_HIDE_CONTROL_K2_SHIFT 8
6919 …8) // Preset request vector. Requesting of presets during the initial part of the EQ master phase.…
6920 …CIEIP_REG_PCIEEP_GEN3_EQ_CTL_PRV_E5_SHIFT 8
6934 …8) // Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase.…
6935 …CIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_K2_SHIFT 8
6963 …L_CPL_PASS_P_E5 (0xff<<8) // Completion passi…
6964 …CIEIP_REG_PCIEEP_ORD_RULE_CTRL_CPL_PASS_P_E5_SHIFT 8
6968 …_CPL_PASS_P_K2 (0xff<<8) // Completion Passi…
6969 …CIEIP_REG_ORDER_RULE_CTRL_OFF_CPL_PASS_P_K2_SHIFT 8
7019 …TL_L1SUB_EXIT_MODE_E5 (0x1<<8) // L1 exit control …
7020 …CIEIP_REG_PCIEEP_PHY_INTOP_CTL_L1SUB_EXIT_MODE_E5_SHIFT 8
7092 …IL_BB (0xff<<8) // Posted Header Cr…
7093 …CIEIP_REG_TL_HDR_FC_ST_PH_AVAIL_BB_SHIFT 8
7105 … (0xf<<28) // Non-Posted Data credits available: bit[11:8].
7110 …CC_BB (0xff<<8) // Posted Header Cr…
7111 …CIEIP_REG_TL_HDR_FCCON_ST_PH_CC_BB_SHIFT 8
7123 … (0xf<<28) // Non-Posted Data credits consumed: bit[11:8].
7130 …RDT_CNTR_BB (0x7f<<8) // Available Posted…
7131 …CIEIP_REG_TL_TGT_CRDT_ST_PD_CRDT_CNTR_BB_SHIFT 8
7139 …D_ALLOC_BB (0xff<<8) // Non-Posted data …
7140 …CIEIP_REG_TL_CRDT_ALLOC_ST_NPD_ALLOC_BB_SHIFT 8
7150 …CURR_STATE_BB (0x3<<8) // CPL_CURR_STATE R…
7151 …CIEIP_REG_TL_SMLOGIC_ST_CPL_CURR_STATE_BB_SHIFT 8
7248 …G_TTX_TLP_STAT_LEN_BB (0xffffff<<8) // TLP Statistics L…
7249 …CIEIP_REG_PCIER_TL_STAT_TX_CTL_REG_TTX_TLP_STAT_LEN_BB_SHIFT 8
7253 …8) // This register contains Enable bit and the TLP type that hardware can detect. Bit[15] is enab…
7254 …CIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_1_BB_SHIFT 8
7264 … (0x7f<<8) // This register contains the mask bits for reg_ttx_det_tlp…
7265 …CIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_1_BB_SHIFT 8
7281 …G_TRX_TLP_STAT_LEN_BB (0xffffff<<8) // TLP Statistics L…
7282 …CIEIP_REG_PCIER_TL_STAT_RX_CTL_REG_TRX_TLP_STAT_LEN_BB_SHIFT 8
7286 …8) // This register contains Enable bit and the TLP type that hardware can detect. Bit[15] is enab…
7287 …CIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_1_BB_SHIFT 8
7297 … (0x7f<<8) // This register contains the mask bits for reg_trx_det_tlp…
7298 …CIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_1_BB_SHIFT 8
7351 …RGINING_1_MTO_E5 (0x3f<<8) // Max timing offse…
7352 …CIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_1_MTO_E5_SHIFT 8
7360 …RGINING_2_SRT_E5 (0x3f<<8) // Sample rate timi…
7361 …CIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_SRT_E5_SHIFT 8
7391 …STAT_FIFO_RD_CTRL_CSRD_USER_B_BB (0x1<<8) // When cleared, in…
7392 …CIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_FIFO_RD_CTRL_CSRD_USER_B_BB_SHIFT 8
7424 …8 bits among the 256 32 bit signals Register 50 :: IND_PCIE_DBG_TRIG1_0TO1_MASK - mask bits [319:0…
7432 …_CTL_ATTNSM_BB (0x3<<8) // Debug fifo attn …
7433 …CIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_ATTNSM_BB_SHIFT 8
7484 …T_FIFO_RDAUTOINC_BB (0x1<<8) // When set and in …
7485 …CIEIP_REG_PCIER_TLDA0_CTLSTAT_FIFO_RDAUTOINC_BB_SHIFT 8
7511 …LSTAT_IND_WADDR_AUTOINC_BB (0x1<<8) // When set, the in…
7512 …CIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_WADDR_AUTOINC_BB_SHIFT 8
7523 …TLDA_TRIG0_1TO0_MASK1 -- Trigger 0 falling edge mask bits [63:32] Register 8 :: IND_TLDA_TRIG0_1T…
7534 …T_FIFO_RDAUTOINC_BB (0x1<<8) // When set and in …
7535 …CIEIP_REG_PCIER_TLDA1_CTLSTAT_FIFO_RDAUTOINC_BB_SHIFT 8
7561 …LSTAT_IND_WADDR_AUTOINC_BB (0x1<<8) // When set, the in…
7562 …CIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_WADDR_AUTOINC_BB_SHIFT 8
7573 …TLDA_TRIG0_1TO0_MASK1 -- Trigger 0 falling edge mask bits [63:32] Register 8 :: IND_TLDA_TRIG0_1T…
7623 …OL_1_UNUSED_3_BB (0x1<<8) // Reserved
7624 …CIEIP_REG_PDL_CONTROL_1_UNUSED_3_BB_SHIFT 8
7658 …1L2_WAIT_FOR_IDLE_BB (0xf<<8) // PHY: RxL0s, L1, …
7659 …CIEIP_REG_PDL_CONTROL_2_L0SL1L2_WAIT_FOR_IDLE_BB_SHIFT 8
7671 …ONTROL_3_MAX_TX_FTS_LIMIT_LONG_BB (0xff<<8) // PHY
7672 …CIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_LONG_BB_SHIFT 8
7687 …STREAM_PORT_BB (0x1<<8) // This bit is set …
7688 …CIEIP_REG_PDL_CONTROL_5_DOWNSTREAM_PORT_BB_SHIFT 8
7698 …DV_NFTS_DIFFCLK_GEN3_BB (0xff<<8) // Gen3 N_FTS value…
7699 …CIEIP_REG_PDL_CONTROL_6_REG_ADV_NFTS_DIFFCLK_GEN3_BB_SHIFT 8
7724 …CS_RXENABLE_BB (0x1<<8) // Enable checksum …
7725 …CIEIP_REG_PDL_CONTROL_10_DL_CS_RXENABLE_BB_SHIFT 8
7756 … (0x1fff<<0) // This maps 8k of addresses that c…
7758 … (0x1fff<<13) // This maps 8k of addresses that c…
7785 …ORRECT_BB (0x1<<8) // RX: Indicate DLP…
7786 …CIEIP_REG_DLATTN_VEC_DLP_INCORRECT_BB_SHIFT 8
7850 …_THRS_RESERVED_BB (0xffffff<<8) //
7851 …CIEIP_REG_DL_T2D_THRS_RESERVED_BB_SHIFT 8
7888 …LLIFY_BB (0x1<<8) // ATE TLP Nullify.…
7889 …CIEIP_REG_ATE_TLP_CFG_ATE_NULLIFY_BB_SHIFT 8
7979 …RXERR_IS_FRAMERR_BB (0x1<<8) // Consider DLLP an…
7980 …CIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_FRAMERR_BB_SHIFT 8
8137 …ALLOW_REMOTE_SPD_CHG_BB (0x1<<8) // Allow link partn…
8138 …CIEIP_REG_REG_PHY_CTL_4_REG_ALLOW_REMOTE_SPD_CHG_BB_SHIFT 8
8155 … (0x1f<<19) // Mask for indicating lanes to upconfigure (1, 2, 4, 8, or 16)
8183 …MCR_SERDES_RESET_MAX_BB (0x3f<<8) // Number of clocks…
8184 …CIEIP_REG_REG_PHY_CTL_6_REG_PMCR_SERDES_RESET_MAX_BB_SHIFT 8
8200 …eriods (~16ns) b001 : prescale = 2**3 of clock periods b010 : prescale = 2**8 of clock periods b01…
8221 … (0x1<<2) // If set, an 8b10b decode error occur…
8233 …NUSED_1_BB (0xf<<8) // Reserved - only …
8234 …CIEIP_REG_PHY_ERR_ATTN_VEC_UNUSED_1_BB_SHIFT 8
8254 …UNUSED_1_BB (0xf<<8) // Reserved - only …
8255 …CIEIP_REG_PHY_ERR_ATTN_MASK_UNUSED_1_BB_SHIFT 8
8269 …GEN3_FIXED_DATA_WIDTH_BB (0x1<<8) // *** Do not modif…
8270 …CIEIP_REG_REG_PHY_CTL_8_REG_GEN3_FIXED_DATA_WIDTH_BB_SHIFT 8
8295 … (0x1<<25) // Enable 4 ms inferred electrical idle in Recovery.RcvrCfg at 8 GT/s
8400 …_GEN3_ENA_DCBAL_SOS_BB (0x1<<8) // Enable SOS data …
8401 …CIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_DCBAL_SOS_BB_SHIFT 8
8451 …_SEDCFG_SEL_BB (0xf<<8) // SED fill/write s…
8452 …CIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_SEL_BB_SHIFT 8
8497 …_GEN3_EN_EXTEND_EQ1_TO_BB (0x1<<8) // [SEMI_FUNCTIONAL…
8498 …CIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ1_TO_BB_SHIFT 8
8585 …GEN3_EQ_LF_VAL_BB (0x3f<<8) // Registered progr…
8586 …CIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_LF_VAL_BB_SHIFT 8
8649 …_LPBK_MASTER_PATTERN_BB (0x1f<<8) // Loopback Master …
8650 …CIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_PATTERN_BB_SHIFT 8
8668 …E_SETTING_LPBK_MASTER_TS1_PRECURSOR_BB (0x3f<<8) // Loopback Master …
8669 …CIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_PRECURSOR_BB_SHIFT 8
8692 …TSSM_SUBST_BB (0x1ff<<8) // Software LTSSM S…
8693 …CIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_SUBST_BB_SHIFT 8
8707 …ATIS_LEN_BB (0xffffff<<8) // PCIE Statistic L…
8708 …CIEIP_REG_PCIE_STATIS_CTL_PCIE_STATIS_LEN_BB_SHIFT 8
8711 … (0xff<<0) // PCIE TX TLP Statistic High 8 bits. This is the nu…
8715 … (0xff<<0) // PCIE TX DLLP Statistic High 8 bits. This is the nu…
8719 … (0xff<<0) // PCIE TX Ordered Set Statistic High 8 bits. This is the nu…
8723 … (0xff<<0) // PCIE RX TLP Statistic High 8 bits. This is the nu…
8727 … (0xff<<0) // PCIE RX DLLP Statistic High 8 bits. This is the nu…
8731 … (0xff<<0) // PCIE RX Ordered Set Statistic High 8 bits. This is the nu…
8756 …LOCK_TIME_BB (0xff<<8) // Symbol Lock Time…
8757 …CIEIP_REG_LTSSM_STATIS_2_SYM_LOCK_TIME_BB_SHIFT 8
8775 …_1512_MCP_ERRS_13_BB (0x7f<<8) // For lane 13 in a…
8776 …CIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_13_BB_SHIFT 8
8788 …_BB (0x7f<<0) // For lane 8: The number of decod…
8790 …8_BB (0x1<<7) // For lane 8: Set by the link par…
8792 …_118_MCP_ERRS_9_BB (0x7f<<8) // For lane 9 in a …
8793 …CIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_9_BB_SHIFT 8
8809 …_74_MCP_ERRS_5_BB (0x7f<<8) // For lane 5 in a …
8810 …CIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_5_BB_SHIFT 8
8826 …_30_MCP_ERRS_1_BB (0x7f<<8) // For lane 1 in a …
8827 …CIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_1_BB_SHIFT 8
8843 …ORS_1512_TX_MCP_ERRS_13_BB (0x7f<<8) // For lane 13 in a…
8844 …CIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_13_BB_SHIFT 8
8856 …ERRS_8_BB (0x7f<<0) // For lane 8: The number of decod…
8858 …_LOCK_8_BB (0x1<<7) // For lane 8: Set by the local re…
8860 …ORS_118_TX_MCP_ERRS_9_BB (0x7f<<8) // For lane 9 in a …
8861 …CIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_9_BB_SHIFT 8
8877 …ORS_74_TX_MCP_ERRS_5_BB (0x7f<<8) // For lane 5 in a …
8878 …CIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_5_BB_SHIFT 8
8894 …ORS_30_TX_MCP_ERRS_1_BB (0x7f<<8) // For lane 1 in a …
8895 …CIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_1_BB_SHIFT 8
8909 …NUSED_1_BB (0xffffff<<8) // Reserved
8910 …CIEIP_REG_RX_FTS_LIMIT_UNUSED_1_BB_SHIFT 8
8914 …_BB (0xff<<8) // Count of recogni…
8915 …CIEIP_REG_FTS_HIST_FTS_HIST_1_BB_SHIFT 8
8921 … (0xff<<0) // Gen2 Debug History 8 transitions ago (see…
8923 …EBUG_9_BB (0xff<<8) // Gen2 Debug Histo…
8924 …CIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_9_BB_SHIFT 8
8932 …EBUG_5_BB (0xff<<8) // Gen2 Debug Histo…
8933 …CIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_5_BB_SHIFT 8
8941 …EBUG_1_BB (0xff<<8) // Gen2 Debug Histo…
8942 …CIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_1_BB_SHIFT 8
8950 …OV_HIST_5_BB (0xff<<8) // Recovery History…
8951 …CIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_5_BB_SHIFT 8
8959 …OV_HIST_1_BB (0xff<<8) // Recovery History…
8960 …CIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_1_BB_SHIFT 8
8968 …SSM_HIST_13_BB (0xff<<8) // LTSSM state 13 t…
8969 …CIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_13_BB_SHIFT 8
8975 … (0xff<<0) // LTSSM state 8 transitions in the p…
8977 …SSM_HIST_9_BB (0xff<<8) // LTSSM state 9 tr…
8978 …CIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_9_BB_SHIFT 8
8986 …SSM_HIST_5_BB (0xff<<8) // LTSSM state 5 tr…
8987 …CIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_5_BB_SHIFT 8
8995 …SSM_HIST_1_BB (0xff<<8) // LTSSM state last…
8996 …CIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_1_BB_SHIFT 8
9001 …ss:R DataWidth:0x20 // Duplicate of ltssm histogram entries 11, 10, 9, and 8 for compatibility
9040 …_SET_GEN3_ERR_ORDEREDSET_NO_EDS_BB (0x1<<8) // An ordered set o…
9041 …CIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ORDEREDSET_NO_EDS_BB_SHIFT 8
9154 …30_SED_EXT_CFG_1_BB (0xff<<8) // SED Extended Con…
9155 …CIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_1_BB_SHIFT 8
9163 …74_SED_EXT_CFG_5_BB (0xff<<8) // SED Extended Con…
9164 …CIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_5_BB_SHIFT 8
9184 …LKREQ_HIST_5_BB (0xf<<8) // The state of the…
9185 …CIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_5_BB_SHIFT 8
9201 …LKREQ_HIST_13_BB (0xf<<8) // The state of the…
9202 …CIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_13_BB_SHIFT 8
9211 … (0xf<<28) // The state of the clock PM state machine and perstb 8 transitions in the p…
9218 …LKREQ_HIST_21_BB (0xf<<8) // The state of the…
9219 …CIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_21_BB_SHIFT 8
9235 …LKREQ_HIST_29_BB (0xf<<8) // The state of the…
9236 …CIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_29_BB_SHIFT 8
9279 …F_CMD_SEE_E5 (0x1<<8) // VF RsvdP.
9280 …CIEIP_VF_REG_PCIEEPVF_CMD_SEE_E5_SHIFT 8
9328 …ND_REG_PCI_TYPE0_SERREN_K2 (0x1<<8) // Enables Error Re…
9329 …CIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2_SHIFT 8
9359 …E5 (0xff<<8) // Read-only copy o…
9360 …CIEIP_VF_REG_PCIEEPVF_REV_PI_E5_SHIFT 8
9368 …VISION_ID_PROGRAM_INTERFACE_K2 (0xff<<8) // Class Code Progr…
9369 …CIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2_SHIFT 8
9377 …LT_E5 (0xff<<8) // Master latency t…
9378 …CIEIP_VF_REG_PCIEEPVF_CLSIZE_LT_E5_SHIFT 8
9383 … (0xff<<24) // The BIST register functions are not supported. All 8 bits of the BIST reg…
9388 …YPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2 (0xff<<8) // Does not apply t…
9389 …CIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2_SHIFT 8
9482 …A_E5 (0xff<<8) // VF's read-only z…
9483 …CIEIP_VF_REG_PCIEEPVF_INT_INTA_E5_SHIFT 8
9491 …IN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2 (0xff<<8) // PCI Compatible I…
9492 …CIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2_SHIFT 8
9496 …IST_NCP_E5 (0xff<<8) // Next capability …
9497 …CIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_NCP_E5_SHIFT 8
9509 …CIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2 (0xff<<8) // PCIE Next Capabi…
9510 …CIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2_SHIFT 8
9572 …F_DEV_CTL_ETF_EN_E5 (0x1<<8) // VF RsvdP.
9573 …CIEIP_VF_REG_PCIEEPVF_DEV_CTL_ETF_EN_E5_SHIFT 8
9609 …OL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2 (0x1<<8) // Extended Tag Fie…
9610 …CIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2_SHIFT 8
9692 …F_LINK_CTL_ECPM_E5 (0x1<<8) // VF RsvdP.
9693 …CIEIP_VF_REG_PCIEEPVF_LINK_CTL_ECPM_E5_SHIFT 8
9729 …_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2 (0x1<<8) // Enable Clock Pow…
9730 …CIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2_SHIFT 8
9764 …P2_ATOM64S_E5 (0x1<<8) // 64-bit AtomicOp …
9765 …CIEIP_VF_REG_PCIEEPVF_DEV_CAP2_ATOM64S_E5_SHIFT 8
9799 …ILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2 (0x1<<8) // 64 Bit AtomicOp …
9800 …CIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2_SHIFT 8
9822 …F_DEV_CTL2_ID0_RQ_E5 (0x1<<8) // VF RsvdP.
9823 …CIEIP_VF_REG_PCIEEPVF_DEV_CTL2_ID0_RQ_E5_SHIFT 8
9845 …OL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2 (0x1<<8) // IDO Request Enab…
9846 …CIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2_SHIFT 8
9856 …AP2_CLS_E5 (0x1<<8) // Crosslink suppor…
9857 …CIEIP_VF_REG_PCIEEPVF_LINK_CAP2_CLS_E5_SHIFT 8
9865 …ITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2 (0x1<<8) // Cross Link Suppo…
9866 …CIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2_SHIFT 8
9923 … (0xf<<12) // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The ac…
9944 …P_CNTRL_NCP_E5 (0xff<<8) // Next capability …
9945 …CIEIP_VF_REG_PCIEEPVF_MSIX_CAP_CNTRL_NCP_E5_SHIFT 8
9955 …ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2 (0xff<<8) // MSI-X Next Capab…
9956 …CIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2_SHIFT 8
10002 …_CTL_NFN_E5 (0xff<<8) // Next Function Nu…
10003 …CIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_NFN_E5_SHIFT 8
10015 …EXT_FUN_NUM_K2 (0xff<<8) // Next Function Nu…
10016 …CIEIP_VF_REG_VF_CAP_REG_ARI_NEXT_FUN_NUM_K2_SHIFT 8
10044 …Q_CAP_EXT_E5 (0x1<<8) // Exgtended TPH Re…
10045 …CIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_EXT_E5_SHIFT 8
10059 …REG_REG_TPH_REQ_EXTENDED_TPH_K2 (0x1<<8) // Extended TPH Req…
10060 …CIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2_SHIFT 8
10070 …Q_CTL_CREN_E5 (0x3<<8) // TPH Requestor En…
10071 …CIEIP_VF_REG_PCIEEPVF_TPH_REQ_CTL_CREN_E5_SHIFT 8
10075 …ROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2 (0x3<<8) // TPH Requester En…
10076 …CIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2_SHIFT 8
10080 …TABLE_STH_E5 (0xff<<8) // ST Table 0 Upper…
10081 …CIEIP_VF_REG_PCIEEPVF_TPH_ST_TABLE_STH_E5_SHIFT 8
10085 …REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2 (0xff<<8) // ST Table 0 Upper…
10086 …CIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2_SHIFT 8
10109 …_CTL_ECVS_E5 (0xff<<8) // Egress control v…
10110 …CIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_ECVS_E5_SHIFT 8
10293 …ux_bkpt_stall, 10 - misc_local_mux_int_stall, 9 - misc_local_mux_ext_stall, 8 - misc_local_mux_sel…
10308 …et to 0x1 and port_id_ofset is set to 0x8, then the port ID is assigned from bits [9:8] of the CID.
10310 …bus spelling for debug: 0:2 - DRA WR STM Core_A, 3:5 - DRA WR STM Core_B, 6:8 - DRA RD STM Core_A,…
10348 … search request issued. The data returned is defined as follows: cam_search[8] = match, cam_rd_dat…
10382 …ABLE_REC_FILTER_EVENT_ID_RANGE_EN (0x1<<8) // Used to enable f…
10383 …EM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EVENT_ID_RANGE_EN_SHIFT 8
10388 … 0x000774UL //Access:RW DataWidth:0x8 // This 8-bit vector is used to enable the various 8…
10471 …TE_INTERRUPT (0x1<<8) // This is error in…
10472 …FC_REG_INTERRUPT_IND_RBC_WRITE_INTERRUPT_SHIFT 8
10501 …_FULL (0x1<<8) // Full indication …
10502 …FC_REG_INDICATIONS1_INP_FIFO_FULL_SHIFT 8
10522 …CNT (0x1f<<8) // Number of entrie…
10523 …FC_REG_INDICATIONS2_LEN_FIFO_CNT_SHIFT 8
10567 … (0xff<<8) // Number of transa…
10568 …FC_REG_DEBUG_DATA_RBC_CNT_SHIFT 8
10676 … (0x1<<8) // TQ read underflo…
10677 …B_REG_INT_STS_TQ_ERROR_RD_IH_SHIFT 8
10695 …H (0x1<<8) // This bit masks, …
10696 …B_REG_INT_MASK_TQ_ERROR_RD_IH_SHIFT 8
10714 …_IH (0x1<<8) // TQ read underflo…
10715 …B_REG_INT_STS_WR_TQ_ERROR_RD_IH_SHIFT 8
10733 …D_IH (0x1<<8) // TQ read underflo…
10734 …B_REG_INT_STS_CLR_TQ_ERROR_RD_IH_SHIFT 8
10787 …REG_DBG_OUT_DATA_SIZE 8
10800 …2_E5 (0xff<<0) // 8-bit value from packa…
10802 …_K2_E5 (0xff<<8) // 8-bit value from pa…
10803 …TH_MAC_REG_REVISION_CORE_VERSION_K2_E5_SHIFT 8
10824 …USE_IGNORE_K2_E5 (0x1<<8) // Ignore received …
10825 …TH_MAC_REG_COMMAND_CONFIG_PAUSE_IGNORE_K2_E5_SHIFT 8
10874 … (0xffff<<0) // Last 2 bytes: 5th is 7:0, 6th is 15:8
10901 …2cUL //Access:RW DataWidth:0x20 // reserved; register is writeable bits 8,4:0 but have no effe…
10904 …ABLE_MULTICAST_FRAME_K2_E5 (0x1<<8) // enables (1) or d…
10905 …TH_MAC_REG_HASHTABLE_LOAD_ENABLE_MULTICAST_FRAME_K2_E5_SHIFT 8
10951 …_K2_E5 (0x1<<8) // TX MAC datapath …
10952 …TH_MAC_REG_STATUS_TX_IS_IDLE_K2_E5_SHIFT 8
10954 … (0x7f<<0) // Number of octets in steps of 4 (XGMII) or 8 (XLGMII). Minimum 8. Value 12 …
11008 …atus bit for software to read the current received pause status. One bit for each of the 8 classes.
11123 … 0x000380UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11125 … 0x000388UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11127 … 0x000390UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11129 … 0x000398UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11131 … 0x0003a0UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11133 … 0x0003a8UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11135 … 0x0003b0UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11137 … 0x0003b8UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11139 … 0x0003c0UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11141 … 0x0003c8UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11143 … 0x0003d0UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11145 … 0x0003d8UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11147 … 0x0003e0UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11149 … 0x0003e8UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11151 … 0x0003f0UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11153 … 0x0003f8UL //Access:R DataWidth:0x20 // Set of 8 objects recording th…
11167 … (0xf<<8) // RS-FEC receive lane locked and aligned; One bit pe…
11168 …TH_RSFEC_REG_RS_FEC_STATUS_AMPS_LOCK_K2_E5_SHIFT 8
11234 …NFO1_RX_DP_OVERFLOW_K2_E5 (0x1<<8) // RX datapath 4x66…
11235 …TH_RSFEC_REG_RS_FEC_VENDOR_INFO1_RX_DP_OVERFLOW_K2_E5_SHIFT 8
11248 …0210UL //Access:RW DataWidth:0x20 // Bits 7:0; Must be written with the 8-bit value of 0x57 to…
11249 … (0xff<<0) // Bits 7:0; Must be written with 8-bit value 0x57 to en…
11265 …K2_E5 (0x1<<8) // Indicate full-du…
11266 …TH_PCS1G_REG_CONTROL_DUPLEX_K2_E5_SHIFT 8
11305 …_K2_E5 (0x1<<8) // Pause Support 2;…
11306 …TH_PCS1G_REG_DEV_ABILITY_PS2_K2_E5_SHIFT 8
11326 …_PS2_K2_E5 (0x1<<8) // Pause Support 2;…
11327 …TH_PCS1G_REG_PARTNER_ABILITY_PS2_K2_E5_SHIFT 8
11397 … (0xffff<<0) // RX 10B/8B code errors; May no…
11419 …LPI_ACTIVE_K2_E5 (0x1<<8) // 1: receive is cu…
11420 …TH_PCS10_50G_REG_STATUS1_RX_LPI_ACTIVE_K2_E5_SHIFT 8
11497 …PABILITY_EEE_40GBASE_RAWAKE_K2_E5 (0x1<<8) // When 1, EEE fast…
11498 …TH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE_K2_E5_SHIFT 8
11514 …2_BER_COUNTER_K2_E5 (0x3f<<8) // BER counter; Non…
11515 …TH_PCS10_50G_REG_BASER_STATUS2_BER_COUNTER_K2_E5_SHIFT 8
11561 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11562 …ED_BLOCKS_COUNTER_K2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks coun…
11629 …UI_CONFIG_TX_MAP_LANE1_K2_E5 (0xf<<8) // Set VL (0..3) to…
11630 …TH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_TX_MAP_LANE1_K2_E5_SHIFT 8
11636 …_M1_K2_E5 (0xff<<8) // Lane 0 Marker pa…
11637 …TH_PCS10_50G_REG_VENDOR_VL0_0_M1_K2_E5_SHIFT 8
11644 …_M1_K2_E5 (0xff<<8) // Lane 1 Marker pa…
11645 …TH_PCS10_50G_REG_VENDOR_VL1_0_M1_K2_E5_SHIFT 8
11652 …_M1_K2_E5 (0xff<<8) // Lane 2 Marker pa…
11653 …TH_PCS10_50G_REG_VENDOR_VL2_0_M1_K2_E5_SHIFT 8
11660 …_M1_K2_E5 (0xff<<8) // Lane 3 Marker pa…
11661 …TH_PCS10_50G_REG_VENDOR_VL3_0_M1_K2_E5_SHIFT 8
11670 …MODE_ST_ENA_CLAUSE49_K2_E5 (0x1<<8) // Current status o…
11671 …TH_PCS10_50G_REG_VENDOR_PCS_MODE_ST_ENA_CLAUSE49_K2_E5_SHIFT 8
11694 …LPI_ACTIVE_K2_E5 (0x1<<8) // 1: receive is cu…
11695 …TH_PCS10_25G_REG_STATUS1_RX_LPI_ACTIVE_K2_E5_SHIFT 8
11772 …PABILITY_EEE_40GBASE_RAWAKE_K2_E5 (0x1<<8) // When 1, EEE fast…
11773 …TH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE_K2_E5_SHIFT 8
11789 …2_BER_COUNTER_K2_E5 (0x3f<<8) // BER counter; Non…
11790 …TH_PCS10_25G_REG_BASER_STATUS2_BER_COUNTER_K2_E5_SHIFT 8
11836 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11837 …ED_BLOCKS_COUNTER_K2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks coun…
11880 …_M1_K2_E5 (0xff<<8) // Lane 0 Marker pa…
11881 …TH_PCS10_25G_REG_VENDOR_VL0_0_M1_K2_E5_SHIFT 8
11888 …_M1_K2_E5 (0xff<<8) // Lane 1 Marker pa…
11889 …TH_PCS10_25G_REG_VENDOR_VL1_0_M1_K2_E5_SHIFT 8
11896 …_M1_K2_E5 (0xff<<8) // Lane 2 Marker pa…
11897 …TH_PCS10_25G_REG_VENDOR_VL2_0_M1_K2_E5_SHIFT 8
11904 …_M1_K2_E5 (0xff<<8) // Lane 3 Marker pa…
11905 …TH_PCS10_25G_REG_VENDOR_VL3_0_M1_K2_E5_SHIFT 8
11914 …MODE_ST_ENA_CLAUSE49_K2_E5 (0x1<<8) // Current status o…
11915 …TH_PCS10_25G_REG_VENDOR_PCS_MODE_ST_ENA_CLAUSE49_K2_E5_SHIFT 8
12364 … 0x000604UL //Access:RW DataWidth:0x8 // lower 8-bits of 16-bit PHY e…
12365 … 0x000608UL //Access:RW DataWidth:0x8 // higher 8-bits of 16-bit PHY e…
12377 … 0x000624UL //Access:R DataWidth:0x8 // Errored register transfer address low 8 bits
12383 … 0x000680UL //Access:RW DataWidth:0x8 // lower 8-bits of the 16-bit d…
12384 … 0x000684UL //Access:RW DataWidth:0x8 // higher 8-bits of the 16-bit d…
12390 … (0xf<<0) // Digital test bus tbus output bits [11:8]
12424 … 0x00086cUL //Access:RW DataWidth:0x8 // Response auxiliary data or argument 8
14477 … 0x002200UL //Access:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU e…
14478 … 0x002204UL //Access:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU e…
14914 … 0x003200UL //Access:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU e…
14915 … 0x003204UL //Access:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU e…
15418 … 0x006140UL //Access:RW DataWidth:0x8 // lower 8-bits of 16-bit lane …
15419 … 0x006144UL //Access:RW DataWidth:0x8 // higher 8-bits of 16-bit lane …
15697 … 0x006654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 15-8
17799 … x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + …
17841 … x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + …
18100 … 0x008140UL //Access:RW DataWidth:0x8 // lower 8-bits of 16-bit lane …
18101 … 0x008144UL //Access:RW DataWidth:0x8 // higher 8-bits of 16-bit lane …
18379 … 0x008654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 15-8
20481 … x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + …
20523 … x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + …
20782 … 0x00a140UL //Access:RW DataWidth:0x8 // lower 8-bits of 16-bit lane …
20783 … 0x00a144UL //Access:RW DataWidth:0x8 // higher 8-bits of 16-bit lane …
21061 … 0x00a654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 15-8
23163 … x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + …
23205 … x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + …
23464 … 0x00c140UL //Access:RW DataWidth:0x8 // lower 8-bits of 16-bit lane …
23465 … 0x00c144UL //Access:RW DataWidth:0x8 // higher 8-bits of 16-bit lane …
23743 … 0x00c654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 15-8
25845 … x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + …
25887 … x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6 + x^8 + x^11 4 � CL93 1 + …
25946 …The only access to this divider. Not an override 4�d0: No division 4�d1: /2 4�d2: /4 4�d3: /8:
25972 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
26259 … 0: PMA operates in 10b/20b mode Enables %5 circuit 1: PMA operates in 8b/16b mode Enables …
26269 …1_8_K2_E5 (0xf<<0) // Snapshot of digital test bus data [11:8]
26273 …BUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
26567 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Genera…
26575 …<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist gener…
26607 …idth:0x8 // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit…
26609 … (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit…
26619 …mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assume…
26632 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
26675 …UL //Access:RW DataWidth:0x8 // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
26677 … (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
26830 …-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction of…
26893 … 0x0011f0UL //Access:RW DataWidth:0x8 // Bits 12:8: txdrv_c1_in[4:0] Bi…
27046 … 2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode. …
27048 … 2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
27214 … overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
27216 … overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
27359 … select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
27411 … (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word…
27413 …05_ENC_EN_O_K2_E5 (0x1<<6) // 8b/10b encoder enable.
27415 …05_DEC_EN_O_K2_E5 (0x1<<7) // 8b/10b decoder enable.
27554 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
28162 …TT_8_K2_E5 (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 cm1 [8]
28168 …TT_8_K2_E5 (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 c1 [8]
28910 …The only access to this divider. Not an override 4�d0: No division 4�d1: /2 4�d2: /4 4�d3: /8:
28936 … 0x00302cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
29223 … 0: PMA operates in 10b/20b mode Enables %5 circuit 1: PMA operates in 8b/16b mode Enables …
29233 …11_8_K2_E5 (0xf<<0) // Snapshot of digital test bus data [11:8]
29237 …TBUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29501 …The only access to this divider. Not an override 4�d0: No division 4�d1: /2 4�d2: /4 4�d3: /8:
29527 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
29798 … 0: PMA operates in 10b/20b mode Enables %5 circuit 1: PMA operates in 8b/16b mode Enables …
29808 …_8_K2_E5 (0xf<<0) // Snapshot of digital test bus data [11:8]
29812 …US_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29820 …is divider. Not an override 4�d0: No division 4�d1: /2 4�d2: /4 4�d3: /8 Used only in PCIe3 1…
29823 … 0: PMA operates in 10b/20b mode Enables %5 circuit 1: PMA operates in 8b/16b mode Enables …
30277 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Genera…
30285 …<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist gener…
30317 …idth:0x8 // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit…
30319 … (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit…
30329 …mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assume…
30342 … 0x000884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
30385 …UL //Access:RW DataWidth:0x8 // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
30387 … (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
30538 …-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction of…
30645 … 0x0009f0UL //Access:RW DataWidth:0x8 // Bits 12:8: txdrv_c1_in[4:0] Bi…
30800 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
30804 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
30832 … 2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode. …
30834 … 2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
30994 … overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
30996 … overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
31139 … select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
31191 … (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word…
31193 …5_ENC_EN_O_K2_E5 (0x1<<6) // 8b/10b encoder enable.
31195 …5_DEC_EN_O_K2_E5 (0x1<<7) // 8b/10b decoder enable.
31357 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Genera…
31365 …<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist gener…
31397 …idth:0x8 // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit…
31399 … (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit…
31409 …mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assume…
31422 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
31465 …UL //Access:RW DataWidth:0x8 // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
31467 … (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
31618 …-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction of…
31725 … 0x0011f0UL //Access:RW DataWidth:0x8 // Bits 12:8: txdrv_c1_in[4:0] Bi…
31880 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
31884 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
31912 … 2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode. …
31914 … 2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
32074 … overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
32076 … overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
32219 … select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
32271 … (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word…
32273 …5_ENC_EN_O_K2_E5 (0x1<<6) // 8b/10b encoder enable.
32275 …5_DEC_EN_O_K2_E5 (0x1<<7) // 8b/10b decoder enable.
32437 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Genera…
32445 …<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist gener…
32477 …idth:0x8 // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit…
32479 … (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit…
32489 …mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assume…
32502 … 0x001884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
32545 …UL //Access:RW DataWidth:0x8 // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
32547 … (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
32698 …-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction of…
32805 … 0x0019f0UL //Access:RW DataWidth:0x8 // Bits 12:8: txdrv_c1_in[4:0] Bi…
32960 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
32964 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
32992 … 2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode. …
32994 … 2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
33154 … overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
33156 … overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
33299 … select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
33351 … (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word…
33353 …5_ENC_EN_O_K2_E5 (0x1<<6) // 8b/10b encoder enable.
33355 …5_DEC_EN_O_K2_E5 (0x1<<7) // 8b/10b decoder enable.
33517 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Genera…
33525 …<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist gener…
33557 …idth:0x8 // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit…
33559 … (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit…
33569 …mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assume…
33582 … 0x002084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
33625 …UL //Access:RW DataWidth:0x8 // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
33627 … (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
33778 …-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction of…
33885 … 0x0021f0UL //Access:RW DataWidth:0x8 // Bits 12:8: txdrv_c1_in[4:0] Bi…
34040 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
34044 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
34072 … 2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode. …
34074 … 2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
34234 … overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
34236 … overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
34379 … select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
34431 … (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word…
34433 …5_ENC_EN_O_K2_E5 (0x1<<6) // 8b/10b encoder enable.
34435 …5_DEC_EN_O_K2_E5 (0x1<<7) // 8b/10b decoder enable.
34604 …24_EBUF_SYMB0_O_9_8_K2_E5 (0x3<<0) // Elastic buffer s0 [9:8]
34608 …26_EBUF_SYMB1_O_9_8_K2_E5 (0x3<<0) // Elastic buffer s1 [9:8]
34621 … 0x002880UL //Access:RW DataWidth:0x8 // SKP symbol for PCIe Gen3 SKP OS ---8'hAA
34633 … (0x3<<0) // 10-bit align symbol for ebuf during PIPE loopback [9:8]
34637 … (0x3<<0) // 10-bit align symbol for ebuf during PIPE loopback [9:8]
34703 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
35444 …T_8_K2_E5 (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 cm1 [8]
35450 …T_8_K2_E5 (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 c1 [8]
36360 …t_src; [3] rst_tsdm; [4] rst_tsem; [5] rst_tcm; [6] rst_rbcr;[7] rst_usdm; [8]rst_ucm; [9] rst_use…
36362 …t_rbcs; [3] rst_mcm; [4] rst_pcm; [5] rst_ycm; [6] rst_msdm; [7] rst_psdm; [8] rst_ysdm; [9] rst_…
36364 … [1] rst_rbch; [2] rst_nig_hard; [3] rst_dbg; [6:4] reserved; [7] rst_wol; [8] rst_wol_hard; [9] r…
36388 … 0x008420UL //Access:RW DataWidth:0x1 // Set/clr general attention 8; this will set/clr b…
36417 … 0x008494UL //Access:RW DataWidth:0x8 // [7:0] = mask 8 attention output sig…
36418 … 0x008498UL //Access:RW DataWidth:0x8 // Masks 8 attention output sig…
36419 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36420 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36421 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36422 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36423 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36424 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36425 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36426 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36427 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36428 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36429 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36430 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36431 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36432 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36433 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36434 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36435 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36436 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36437 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36438 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36439 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36440 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36441 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36442 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36443 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36444 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36445 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36446 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36447 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36448 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36449 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36450 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36451 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36452 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36453 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36454 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36455 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36456 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36457 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36458 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36459 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36460 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36461 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36462 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36463 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36464 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36465 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36466 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36467 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36468 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36469 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36470 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36471 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36472 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36473 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36474 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36475 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36476 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36477 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36478 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36479 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36480 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36481 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36482 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36483 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36484 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36485 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36486 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36487 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36488 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36489 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36490 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36491 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36492 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36493 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36494 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36495 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36496 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36497 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36498 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36499 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36500 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36501 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36502 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36503 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36504 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36505 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36506 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36507 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36508 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36509 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36510 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36511 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36512 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36513 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36514 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36515 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36516 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36517 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36518 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36519 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36520 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36521 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36522 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36523 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36524 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36525 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36526 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36527 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36528 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36529 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36530 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36531 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36532 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36533 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36534 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36535 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36536 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36537 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36538 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36539 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36540 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36541 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36542 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36543 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36544 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36545 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36546 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36547 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36548 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36549 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36550 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36551 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36552 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36553 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36554 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36555 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36556 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36557 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36558 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36559 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36560 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36561 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36562 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36563 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36564 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36565 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36566 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36567 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36568 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36569 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36570 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36571 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36572 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36573 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36574 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36575 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36576 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36577 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36578 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36579 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36580 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36581 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36582 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36583 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36584 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36585 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36586 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36587 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36588 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36589 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36590 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36591 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36592 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36593 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36594 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36595 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36596 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36597 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36598 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36599 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36600 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36601 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36602 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36603 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36604 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36605 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36606 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36607 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36608 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36609 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36610 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36611 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36612 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36613 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36614 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36615 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36616 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36617 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36618 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36619 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36620 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36621 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36622 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36623 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36624 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36625 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36626 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36627 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36628 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36629 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36630 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36631 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36632 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36633 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36634 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36637 …1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; […
36638 …8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] S…
36639 …4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] …
36640 …y error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] …
36641 …; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; […
36642 … error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; …
36643 … error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; […
36644 …WR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Par…
36645 …Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; …
36655 … PERST_N assertion (goes 0); [7] one clears PERST_N de-assertion (goes 1). [8] one clears PCIe lin…
36663 …of each engine is used in this configuration, with support for 8 TCs, 1 pure-LB TC, and 8 global P…
36676 …8 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_8.SW_TIMER_RELOAD…
36684 … 0x008c60UL //Access:RW DataWidth:0x20 // Reload value for counter 8 if reload; the value…
36701 …unter for sw timers1-8. there are 8 addresses in this register. address 0 - timer 1; address 1 - t…
36702 …C_REG_SW_TIMER_VAL_SIZE 8
36703 …et_reg_hard_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [8] rst_mcp_n_hard_core…
36705 …mcp_n_reset_cmn_core; [5] rst_misc_core; [6] rst_dbue (UART); [7] rst_bmb; [8] rst_ipc; [9]rst_crb…
36707 …v; [3] rst_crbch; [4] rst_opte; [5] rst_ncsi; [6] rst_umac; [7] rst_mstat; [8] rst_cpmu; [9] rst_r…
36762 …[4] rst_nwm_mac3; [5] rst_nwm_gpcs0; [6] rst_nwm_gpcs1; [7] rst_nwm_gpcs2; [8] rst_nwm_gpcs3; [9] …
36814 …SOP_FIFO_ERR_ENG1_BB (0x1<<8) // BTB_SOP FIFO err…
36815 …ISCS_REG_INT_STS_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_BB_SHIFT 8
36837 …_SOP_FIFO_ERR_ENG1_BB (0x1<<8) // This bit masks, …
36838 …ISCS_REG_INT_MASK_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_BB_SHIFT 8
36860 …TB_SOP_FIFO_ERR_ENG1_BB (0x1<<8) // BTB_SOP FIFO err…
36861 …ISCS_REG_INT_STS_WR_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_BB_SHIFT 8
36883 …BTB_SOP_FIFO_ERR_ENG1_BB (0x1<<8) // BTB_SOP FIFO err…
36884 …ISCS_REG_INT_STS_CLR_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_BB_SHIFT 8
37061 …h:0x20 // Debug only: [31:11] - spare RW register reset by por reset; [10:8] : PCIe Device Type:…
37078 …ERS_MDIO_OVERRIDE.MDIO_OVERRIDE is set. [3:0] - ch0_rr; [7:4] - ch1_rr; [11:8] - ch2_rr; [15:12] -…
37115 … 0x0097bcUL //Access:RW DataWidth:0x9 // [31:9] Reserved [8] OTP_AVS_SRAM_MO…
37116 … [14:12] OTP_VTRAP_TRIM_CODE: BG_adj [11:9] OTP_VTRAP_TRIM_CODE: MAX0_adj [8:6] OTP_VTRAP_TRIM_…
37117 … [14:12] OTP_VTRAP_TRIM_CODE: BG_adj [11:9] OTP_VTRAP_TRIM_CODE: MAX0_adj [8:6] OTP_VTRAP_TRIM_…
37121 …ket available status; [10] - STORM FIFO; [9] - BTB SOP FIFO for engine 0; [8] - BTB SOP FIFO for …
37122 …most full; [10] - STORM FIFO full; [9] - BTB SOP FIFO full for engine 0; [8] - BTB SOP FIFO ful…
37159 … (0xff<<8) // Set the Port for…
37160 …BU_REG_VFID_CFG_PORT_VALUE_SHIFT 8
37178 … 0x00c068UL //Access:RW DataWidth:0x1 // Command 8 go.
37267 …E_REG_DBG_OUT_DATA_SIZE 8
37272 …Bits 0- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - o…
37273 …Bits 0- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - o…
37290 …RW DataWidth:0x3 // Debug only: These bits are a client index for slot 8 in calendar as follo…
37299 …ORM (A and B) data + 6 different (in general case) HW blocks are logged 3 - 8 different (in genera…
37495 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37497 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37500 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37502 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37505 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37507 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37510 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37512 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37515 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37517 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37520 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37522 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37525 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37527 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37530 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37532 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37535 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37537 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37540 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37542 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37545 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37547 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37550 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37552 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37555 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37557 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37560 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37562 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37565 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37567 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37570 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37572 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37575 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37577 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37580 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37582 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37585 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37587 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37590 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37592 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37595 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37597 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37600 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37602 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37605 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37607 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37610 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37612 …values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37766 … (values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37768 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37771 … (values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37773 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37776 … (values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37778 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37781 … (values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37783 …(values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming da…
37825 …er when HW block is selected: [2:0] - bits[31:0]; [5:3] - bits[63:32]; [8:6] - bits[95:64]; …
37835 …th:0x4 // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -3…
37876 …. This bit is set to '0' in idle state, otherwise '1' in all other states; [8]: debug_mode: This b…
37888 … 0x02021cUL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf …
37894 …x020224UL //Access:RW DataWidth:0x1 // 0: divide core_pll clock by 2/4/8/16 according to post…
37908 … 0x020238UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): refer to postdi…
37967 … 0x020268UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf …
37971 …x020270UL //Access:RW DataWidth:0x1 // 0: divide core_pll clock by 2/4/8/16 according to post…
37986 … 0x020284UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): refer to postdi…
38003 …= 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for…
38006 …= 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for…
38012 …rite 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write 9 F…
38019 … 0x0202b4UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf …
38023 …x0202bcUL //Access:RW DataWidth:0x1 // 0: divide core_pll clock by 2/4/8/16 according to post…
38033 … 0x0202d0UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): refer to postdi…
38036 …= 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for…
38038 …= 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for…
38044 …set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this…
38045 …set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this…
38046 …set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this…
38047 …rite 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write 9 F…
38142 …S (0xf<<8) // Strap value on F…
38143 …PC_REG_HW_STRAPS_FLASH_STRAPS_SHIFT 8
38158 …_0_BB (0x1<<8) // This bit generat…
38159 …PC_REG_INT_STS_0_OTP_ECC_DED_0_BB_SHIFT 8
38188 …D_0_BB (0x1<<8) // This bit masks, …
38189 …PC_REG_INT_MASK_0_OTP_ECC_DED_0_BB_SHIFT 8
38218 …DED_0_BB (0x1<<8) // This bit generat…
38219 …PC_REG_INT_STS_WR_0_OTP_ECC_DED_0_BB_SHIFT 8
38248 …_DED_0_BB (0x1<<8) // This bit generat…
38249 …PC_REG_INT_STS_CLR_0_OTP_ECC_DED_0_BB_SHIFT 8
38276 …tatus 0 ccfc_ccam 1 ccfc_scam 2 igu 3 msem 4 prs_gft 5 prs_h 6 prs_l 7 psem 8 psem_vfc 9 qm 10 tcf…
38277 …tatus 0 ccfc_ccam 1 ccfc_scam 2 igu 3 msem 4 prs_gft 5 prs_h 6 prs_l 7 psem 8 psem_vfc 9 qm 10 tcf…
38404 …PLL_LOCK_BB (0x1<<8) // 1: PLL is locked…
38405 …PC_REG_SGMII_STATUS_SGMII_TXPLL_LOCK_BB_SHIFT 8
38429 …8 refclk 1'b1: 16 refclk [8:7] power-up time before starting calibration 2'b00: 32 refclk = 1.28us…
38458 …set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this…
38534 …FF_STALL_MEM_SET_VQ_EN (0x1<<8) // 0 : For the FSM …
38535 …PMU_REG_OBFF_MODE_CONTROL_OBFF_STALL_MEM_SET_VQ_EN_SHIFT 8
38565 …BFF_TM_SCAN_EN (0x1<<8) // 0 : Timer Scan s…
38566 …PMU_REG_OBFF_MODE_ENTRY_EN_OBFF_TM_SCAN_EN_SHIFT 8
38620 …CAU_IDLE_EN (0x1<<8) // 0 : CAU IDLE is …
38621 …PMU_REG_L1_MODE_ENTRY_EN_L1_CAU_IDLE_EN_SHIFT 8
38652 …R_CAU_IDLE_EN (0x1<<8) // 0 : CAU IDLE is …
38653 …PMU_REG_LTR_MODE_ENTRY_EN_LTR_CAU_IDLE_EN_SHIFT 8
38686 …_E0_EN (0x1<<8) // 0 : Shutdown Net…
38687 …PMU_REG_CLK_EN_CONFIG_NW_CLK_E0_EN_SHIFT 8
38761 …TRY_EN_MCS_TM_SCAN_EN (0x1<<8) // 0 : Timer Scan s…
38762 …PMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_TM_SCAN_EN_SHIFT 8
38815 …NTRY_EN_SCS_TM_SCAN_EN (0x1<<8) // 0 : Timer Scan s…
38816 …PMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_TM_SCAN_EN_SHIFT 8
38869 …Y_EN_NCS_TM_SCAN_EN (0x1<<8) // 0 : Timer Scan s…
38870 …PMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_TM_SCAN_EN_SHIFT 8
38923 …RY_EN_PCS_TM_SCAN_EN (0x1<<8) // 0 : Timer Scan s…
38924 …PMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_TM_SCAN_EN_SHIFT 8
39018 …S_1_MSEM_SEM_IDLE_E1_ISIG_STATUS (0x1<<8) // Current status o…
39019 …PMU_REG_CPMU_INPUT_SIG_STATUS_1_MSEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT 8
39065 …S_2_PGLUE_PGL_EMPTY_ISIG_STATUS (0x1<<8) // Current status o…
39066 …PMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PGL_EMPTY_ISIG_STATUS_SHIFT 8
39118 …S_3_NIG_TX_EMPTY_P2_E0_ISIG_STATUS_K2_E5 (0x1<<8) // Current status o…
39119 …PMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_TX_EMPTY_P2_E0_ISIG_STATUS_K2_E5_SHIFT 8
39155 …US_ERSTCLK_NW_CLK_SLOWDOWN_E0_OSIG_STATUS (0x1<<8) // Current status o…
39156 …PMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_E0_OSIG_STATUS_SHIFT 8
39275 … (0x1<<8) // Setting this bit…
39276 …CSI_REG_CONFIG_SW_PAUSE_SHIFT 8
39457 …N_IPG (0x1f<<8) // This field is a …
39458 …CSI_REG_SIDEBAND_ARB_ARB_TOKEN_IPG_SHIFT 8
39491 …I_REG_DBG_OUT_DATA_SIZE 8
39509 …coding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 …
39512 …coding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 …
39515 …coding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 …
39519 …8 = xsdm. 9 = dbu. 10 = dmae. Bits [51:47]: Error type. The decoding: 0 = no error (access to the …
39522 … [3]: psdm. Bit [4]: ysdm. Bit [5]: usdm Bit [6]: tsdm. Bit [7]: xsdm. Bit [8]: dbu. Bit [9]: dmae.
39525 … PF #4. Bit [5]: PF #5. Bit [6]: PF #6. Bit [7]: PF #7. Bit [8]: PF #8. Bit [9]: PF #9.…
39540 …_REG_DBG_OUT_DATA_SIZE 8
39629 …_IGNORE_BB (0x1<<8) // Ignore Pause Fra…
39630 …MAC_REG_COMMAND_CONFIG_PAUSE_IGNORE_BB_SHIFT 8
39651 … (0x1<<21) // If enabled; then CRS input to Unimac is ORed with tds[8] (tx data valid outp…
39732 …ID_MINOR_BB (0xff<<8) // Unimac version i…
39733 …MAC_REG_UMAC_REV_ID_REVISION_ID_MINOR_BB_SHIFT 8
39748 …C_REG_DBG_OUT_DATA_SIZE 8
39815 …4 - crcerr (on by default) 5 - lenerr 6 - oversize (on by default) 7 - rxok 8 - mcast 9 - bcast 10…
39866 …_I_ECC_2_RF_INT_E5 (0x1<<8) // This bit masks, …
39867 …CP2_REG_PRTY_MASK_H_0_MEM004_I_ECC_2_RF_INT_E5_SHIFT 8
39882 …_I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, …
39883 …CP2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT 8
39906 … data bit should have an error. Do not decode past the memory data width of 8. The two words must …
39907 … data bit should have an error. Do not decode past the memory data width of 8. The two words must …
39908 … data bit should have an error. Do not decode past the memory data width of 8. The two words must …
39909 … data bit should have an error. Do not decode past the memory data width of 8. The two words must …
39910 … data bit should have an error. Do not decode past the memory data width of 8. The two words must …
39911 … data bit should have an error. Do not decode past the memory data width of 8. The two words must …
39912 … data bit should have an error. Do not decode past the memory data width of 8. The two words must …
39913 … data bit should have an error. Do not decode past the memory data width of 8. The two words must …
39914 … data bit should have an error. Do not decode past the memory data width of 8. The two words must …
39915 … data bit should have an error. Do not decode past the memory data width of 8. The two words must …
39916 … data bit should have an error. Do not decode past the memory data width of 8. The two words must …
39917 … data bit should have an error. Do not decode past the memory data width of 8. The two words must …
39936 …004_I_ECC_2_EN_E5 (0x1<<8) // Enable ECC for m…
39937 …CP2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_2_EN_E5_SHIFT 8
39970 …0_MEM004_I_ECC_2_PRTY_E5 (0x1<<8) // Set parity only …
39971 …CP2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_2_PRTY_E5_SHIFT 8
40004 …TED_0_MEM004_I_ECC_2_CORRECT_E5 (0x1<<8) // Record if a corr…
40005 …CP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_2_CORRECT_E5_SHIFT 8
40026 …2_REG_DBG_OUT_DATA_SIZE 8
40048 …_I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, …
40049 …PTE_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT 8
40095 …_I_MEM_PRTY_0_BB (0x1<<8) // This bit masks, …
40096 …CIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_BB_SHIFT 8
40190 …_PLL_LOCK_BB (0x1<<8) // PLL Lock status …
40191 …CIE_REG_PCIE_STATUS_BITS_PHY_PLL_LOCK_BB_SHIFT 8
40331 …DM_Q_NOT_EMPTY_K2_E5 (0x1<<8) // Level indicating…
40332 …CIE_REG_LINK_DEBUG_STATUS_RADM_Q_NOT_EMPTY_K2_E5_SHIFT 8
40468 …CT_K2_E5 (0x1<<8) // L1 Exit detected.
40469 …CIE_REG_INT_STS_L1_EXIT_DETECT_K2_E5_SHIFT 8
40503 …ECT_K2_E5 (0x1<<8) // This bit masks, …
40504 …CIE_REG_INT_MASK_L1_EXIT_DETECT_K2_E5_SHIFT 8
40538 …ETECT_K2_E5 (0x1<<8) // L1 Exit detected.
40539 …CIE_REG_INT_STS_WR_L1_EXIT_DETECT_K2_E5_SHIFT 8
40573 …DETECT_K2_E5 (0x1<<8) // L1 Exit detected.
40574 …CIE_REG_INT_STS_CLR_L1_EXIT_DETECT_K2_E5_SHIFT 8
40599 …E_REG_DBG_OUT_DATA_SIZE 8
40624 …_2_K2_E5 (0x1<<8) // PERST occurred (…
40625 …CIE_REG_RESET_STATUS_2_PERST_2_K2_E5_SHIFT 8
40682 …EM017_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
40683 …XPREQBUS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 8
40684 …EM015_I_MEM_PRTY_K2 (0x1<<8) // This bit masks, …
40685 …XPREQBUS_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT 8
40737 …IFO_UNDER_ERR (0x1<<8) // CFC load request…
40738 …ORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT 8
40762 …FIFO_UNDER_ERR (0x1<<8) // This bit masks, …
40763 …ORQ_REG_INT_MASK_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT 8
40787 …Q_FIFO_UNDER_ERR (0x1<<8) // CFC load request…
40788 …ORQ_REG_INT_STS_WR_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT 8
40812 …EQ_FIFO_UNDER_ERR (0x1<<8) // CFC load request…
40813 …ORQ_REG_INT_STS_CLR_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT 8
40844 …_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
40845 …ORQ_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_E5_SHIFT 8
40880 …e. value of 0 means 1 DWord (4B) per connection, value of 1 means 2 DWords (8B) and so forth. This…
40881 …e. value of 0 means 1 DWord (4B) per connection, value of 1 means 2 DWords (8B) and so forth. This…
40882 …s the LOG2 of PWM page size in units of 4KB, i.e. 0 means 4KB page, 1 means 8KB pages and so forth…
40883 …s the LOG2 of PWM page size in units of 4KB, i.e. 0 means 4KB page, 1 means 8KB pages and so forth…
41004 …8 bytes; 1 - 2 LSB-s of the address are not zeroes (no DWORD alignment); 2 - The size of the data …
41007 …8 bytes; 1 - 2 LSB-s of the address are not zeroes (no DWORD alignment); 2 - The size of the data …
41013 …legal WqeSize/PktSize; 7 - First DPM doorbell and illegal RoCEFlags/SgeNum; 8 - First RoCE EDPM do…
41015 …legal WqeSize/PktSize; 7 - First DPM doorbell and illegal RoCEFlags/SgeNum; 8 - First RoCE EDPM do…
41050 …Q_REG_DBG_OUT_DATA_SIZE 8
41056 …uffer. 2) Initialization write access: write all the addresses modulo 8, i.e. 0, 8, .., 632. The a…
41058 …uffer. 2) Initialization write access: write all the addresses modulo 8, i.e. 0, 8, .., 312 to eli…
41095 …n XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. Per connection type 8.
41111 …lect which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 8.
41135 …th:0x1 // QM Bypass mode is enabled for XCM messages for connection type 8. Per connection type.
41159 …0x1 // Indicates whether DPI validation is supported for connection type 8. Per connection type.
41183 …UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell for connection type 8.
41207 …text to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 8.
41231 … 0x102a08UL //Access:RW DataWidth:0x8 // Enable for XCM counter flag command for connection 8.
41255 … 0x102a48UL //Access:RW DataWidth:0x8 // Enable for TCM counter flag command for connection 8.
41279 … 0x102a88UL //Access:RW DataWidth:0x8 // Enable for UCM counter flag command for connection 8.
41303 …2ac8UL //Access:RW DataWidth:0x8 // Enable for XCM aggregation value command for connection 8.
41327 …2b08UL //Access:RW DataWidth:0x8 // Enable for TCM aggregation value command for connection 8.
41351 …2b48UL //Access:RW DataWidth:0x8 // Enable for UCM aggregation value command for connection 8.
41417 …ty type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 8.
41433 …ve flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 8.
41449 …ffinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 8.
41494 …ATCH (0x1<<8) // Command FID not …
41495 …GU_REG_INT_STS_CMD_FID_NOT_MATCH_SHIFT 8
41517 …MATCH (0x1<<8) // This bit masks, …
41518 …GU_REG_INT_MASK_CMD_FID_NOT_MATCH_SHIFT 8
41540 …T_MATCH (0x1<<8) // Command FID not …
41541 …GU_REG_INT_STS_WR_CMD_FID_NOT_MATCH_SHIFT 8
41563 …OT_MATCH (0x1<<8) // Command FID not …
41564 …GU_REG_INT_STS_CLR_CMD_FID_NOT_MATCH_SHIFT 8
41583 …I_MEM_PRTY_1_K2 (0x1<<8) // This bit masks, …
41584 …GU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_K2_SHIFT 8
41603 …I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
41604 …GU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5_SHIFT 8
41693 …I_MEM_PRTY_1_BB (0x1<<8) // This bit masks, …
41694 …GU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_BB_SHIFT 8
41794 …IX_RO (0x1<<8) // RO for MSI and M…
41795 …GU_REG_MESSAGE_FIELDS_MSI_MSIX_RO_SHIFT 8
41868 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41869 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41870 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41871 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41872 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41873 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41874 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41875 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41876 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41877 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41878 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41879 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41880 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41881 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41882 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41883 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41884 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41885 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41886 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41887 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41888 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41889 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41890 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41891 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41892 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41893 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41894 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41895 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41896 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41897 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41911 …ceiving a timer mask command. 0 = 0; 1 = 1; 2 = 2; 3 = 4; 4 = 8; 5 = 16; 6 = 24; 7 = 32; 8 = 48; 9…
41927 …8UL //Access:RW DataWidth:0x10 // Tph field for attention message. Bits 8:0 - steering tag; bi…
41942 …oding is as follows: [8:0] - fid ([8] - if set - PF; else VF, [7:0] - FID). [12:9] - source (value…
41966 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 0; [7:0] = VF number; if PF - [8] =…
41973 …STORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM) 8 = CAU; 9 = internal …
41990 …_REG_DBG_OUT_DATA_SIZE 8
42001 …4000UL //Access:RW DataWidth:0x18 // Mapping CAM. Fields: [0] - valid. [8:1] - vector number (…
42024 …O_ERR (0x1<<8) // Write to full F…
42025 …AU_REG_INT_STS_IGU_WDATA_FIFO_ERR_SHIFT 8
42047 …_FIFO_ERR (0x1<<8) // Write to full F…
42048 …AU_REG_INT_STS_CLR_IGU_WDATA_FIFO_ERR_SHIFT 8
42070 …FIFO_ERR (0x1<<8) // Write to full F…
42071 …AU_REG_INT_STS_WR_IGU_WDATA_FIFO_ERR_SHIFT 8
42093 …FO_ERR (0x1<<8) // This bit masks, …
42094 …AU_REG_INT_MASK_IGU_WDATA_FIFO_ERR_SHIFT 8
42138 …I_MEM_PRTY_0_E5 (0x1<<8) // This bit masks, …
42139 …AU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_E5_SHIFT 8
42150 …I_MEM_PRTY_K2 (0x1<<8) // This bit masks, …
42151 …AU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_SHIFT 8
42156 …I_MEM_PRTY_BB (0x1<<8) // This bit masks, …
42157 …AU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_SHIFT 8
42232 …_REQ_VQID (0x1f<<8) // The value of the…
42233 …AU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_VQID_SHIFT 8
42247 … // Write to this register will perform cleanup on the written SB number. [8:0] - SB absolute ind…
42279 …TORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM); 8 = GRC cleanup; 9 = …
42286 …N (0x1<<8) // Statistic: enabl…
42287 …AU_REG_STAT_CTRL_FSM0_LINE_EN_SHIFT 8
42291 …N (0x1<<8) // Statistic: enabl…
42292 …AU_REG_STAT_CTRL_FSM1_LINE_EN_SHIFT 8
42313 …TORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM); 8=GRC cleanup; 9=timer…
42314 …0x1c0c8cUL //Access:R DataWidth:0xa // Debug; [9] if set data valid; [8] previous FSM_sel; […
42334 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 1; [7:0] = VF number; if PF - [8] =…
42341 …TORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM); 8 = GRC cleanup; 9 = …
42354 …_REG_DBG_OUT_DATA_SIZE 8
42377 …cmd (If set the entire SB segment is written over the PXP to host memory); [8] IGU cmd (If set the…
42379 … 0-2 only); [62:50] FID ([12:9] - PF number (in case of VF the parent PF); [8] - VF valid (1 - VF;…
42391 …_unit_size = 0), then N = 4 addresses If (cqe_agg_unit_size = 1), then N = 8 addresses If (cqe_a…
42394 …id slots; [84:72] - FID ([13:9] - PF number (in case of VF the parent PF); [8] - VF valid (1 - VF;…
42478 …I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
42479 …RS_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5_SHIFT 8
42540 …I_MEM_PRTY_K2 (0x1<<8) // This bit masks, …
42541 …RS_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_K2_SHIFT 8
42612 …I_MEM_PRTY_BB (0x1<<8) // This bit masks, …
42613 …RS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_SHIFT 8
42709 …I_MEM_PRTY_K2 (0x1<<8) // This bit masks, …
42710 …RS_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2_SHIFT 8
42864 …ASK_PRIORITY (0x1<<8) // If this bit is 0…
42865 …RS_REG_OPENFLOW_SEARCH_KEY_MASK_PRIORITY_SHIFT 8
42910 … 3-TC3 traffic; 4-TC4 traffic; 5-TC5 traffic; 6-TC6 traffic; 7-TC7 traffic; 8-TC8 traffic. Defaul…
42911 … 3-TC3 traffic; 4-TC4 traffic; 5-TC5 traffic; 6-TC6 traffic; 7-TC7 traffic; 8-TC8 traffic. Defaul…
42913 …0 client; upper bits are for priority 8 client. The clients are assigned the IDs corresponding to…
42914 …0 client; upper bits are for priority 8 client. The clients are assigned the IDs corresponding to…
42941 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 8 is allowed to reach.
42942 …idth:0x20 // Specify the weight (in bytes) to be added to credit register 8 when it is time to i…
42943 …R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter credit register 8.
42947 …for loopback traffic on TC 0 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42948 …when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42949 …for loopback traffic on TC 0 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42953 …for loopback traffic on TC 1 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42954 …when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42955 …for loopback traffic on TC 1 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42959 …for loopback traffic on TC 2 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42960 …when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42961 …for loopback traffic on TC 2 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42965 …for loopback traffic on TC 3 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42966 …when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42967 …for loopback traffic on TC 3 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42971 …for loopback traffic on TC 4 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42972 …when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42973 …for loopback traffic on TC 4 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42977 …for loopback traffic on TC 5 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42978 …when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42979 …for loopback traffic on TC 5 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42983 …for loopback traffic on TC 6 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42984 …when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42985 …for loopback traffic on TC 6 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42989 …for loopback traffic on TC 7 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42990 …when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42991 …for loopback traffic on TC 7 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not r…
42995 … is disabled this value should be 0. Legal values for this field are from 0 (disabled) to 8 (32B).
43093 … (0x3ff<<8) // The CM header for irregular or errored packets. Used in packet start me…
43094 …RS_REG_L2_IRREG_CASES_CM_HDR_SHIFT 8
43100 … (0x3ff<<8) // The CM header for tunneled packets with no match in the mac-vlan cache. Used in pac…
43101 …RS_REG_L2_TUNNELING_CM_HDR_SHIFT 8
43113 … (0x3ff<<8) // The CM header for tunneled packets with no match in the mac-vlan cache. Used in pac…
43114 …RS_REG_L2_TUNNELING_CACHED_MAC_VLAN_CM_HDR_SHIFT 8
43126 … (0x3ff<<8) // The CM header for packets that hit in the MAC/VLAN cache. Used in packet sta…
43127 …RS_REG_L2_CACHED_MAC_VLAN_CM_HDR_SHIFT 8
43139 … (0x3ff<<8) // The CM header for light L2. Used in packet start message to T…
43140 …RS_REG_LIGHT_L2_CM_HDR_SHIFT 8
43146 … (0x3ff<<8) // The CM header for regular packets. Used in packet start message …
43147 …RS_REG_L2_REGULAR_PKT_CM_HDR_SHIFT 8
43156 … for an FCoE packet. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - …
43174 …used, this block is used for the upper bytes. 14:11 - number of bytes, 0 to 8. 10:4 - byte offse…
43175 …ock is only used if the number of bytes in mac_vlan_flex_upper is less than 8. 10:4 - byte offset …
43200 …sages sent to TCM on the LB port for TC 0. In 4-port mode, only TCs 0-3 and 8 are valid. Counter l…
43202 …sages sent to TCM on the LB port for TC 1. In 4-port mode, only TCs 0-3 and 8 are valid. Counter l…
43204 …sages sent to TCM on the LB port for TC 2. In 4-port mode, only TCs 0-3 and 8 are valid. Counter l…
43206 …sages sent to TCM on the LB port for TC 3. In 4-port mode, only TCs 0-3 and 8 are valid. Counter l…
43208 …sages sent to TCM on the LB port for TC 4. In 4-port mode, only TCs 0-3 and 8 are valid. Counter l…
43210 …sages sent to TCM on the LB port for TC 5. In 4-port mode, only TCs 0-3 and 8 are valid. Counter l…
43212 …sages sent to TCM on the LB port for TC 6. In 4-port mode, only TCs 0-3 and 8 are valid. Counter l…
43214 …sages sent to TCM on the LB port for TC 7. In 4-port mode, only TCs 0-3 and 8 are valid. Counter l…
43215 …ort) Number of messages sent to TCM on the LB port for TC 8. In 4-port mode, only TCs 0-3 and 8 ar…
43227 …28UL //Access:RC DataWidth:0x18 // The number of process packets for TC 8. Counts packets as …
43233 …queues of each traffic class, before being back pressured by the STORMs. 16:8 - Loopback, 7:0 - ma…
43243 …_REG_DBG_OUT_DATA_SIZE 8
43255 …_REG_FC_DBG_OUT_DATA_A_SIZE 8
43257 …_REG_FC_DBG_OUT_DATA_SIZE 8
43272 …_REG_FC_DBG_OUT_DATA_B_SIZE 8
43307 …8.DSCP 7.Source port or ICMP type 6.Destination port or ICMP code 5.Ethertype 4.Ttl 3.TtlEqualOne …
43332 …ff<<8) // The CM header for Match Offload/ Match L2 filter packets and gft connection type . Used …
43333 …RS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8
43393 …// Context region for received Ethernet packet with a match and packet type 8. Used in CFC load re…
43445 …:0x8 // Context region for pure acknowledge packets with connection type 8. Used in CFC load re…
43469 …Width:0x8 // The increment value to send in the CCFC load request message for connection type 8.
43481 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 0. Used in…
43482 …RS_REG_CM_HDR_EVENT_ID_0_CM_HDR_SHIFT 8
43489 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 1. Used in…
43490 …RS_REG_CM_HDR_EVENT_ID_1_CM_HDR_SHIFT 8
43497 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 2. Used in…
43498 …RS_REG_CM_HDR_EVENT_ID_2_CM_HDR_SHIFT 8
43505 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 3. Used in…
43506 …RS_REG_CM_HDR_EVENT_ID_3_CM_HDR_SHIFT 8
43513 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 4. Used in…
43514 …RS_REG_CM_HDR_EVENT_ID_4_CM_HDR_SHIFT 8
43521 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 5. Used in…
43522 …RS_REG_CM_HDR_EVENT_ID_5_CM_HDR_SHIFT 8
43529 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 6. Used in…
43530 …RS_REG_CM_HDR_EVENT_ID_6_CM_HDR_SHIFT 8
43537 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 7. Used in…
43538 …RS_REG_CM_HDR_EVENT_ID_7_CM_HDR_SHIFT 8
43542 … (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 8
43544 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 8. Used in…
43545 …RS_REG_CM_HDR_EVENT_ID_8_CM_HDR_E5_SHIFT 8
43551 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 9. Used in…
43552 …RS_REG_CM_HDR_EVENT_ID_9_CM_HDR_E5_SHIFT 8
43558 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 10. Used i…
43559 …RS_REG_CM_HDR_EVENT_ID_10_CM_HDR_E5_SHIFT 8
43565 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 11. Used i…
43566 …RS_REG_CM_HDR_EVENT_ID_11_CM_HDR_E5_SHIFT 8
43572 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 12. Used i…
43573 …RS_REG_CM_HDR_EVENT_ID_12_CM_HDR_E5_SHIFT 8
43579 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 13. Used i…
43580 …RS_REG_CM_HDR_EVENT_ID_13_CM_HDR_E5_SHIFT 8
43586 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 14. Used i…
43587 …RS_REG_CM_HDR_EVENT_ID_14_CM_HDR_E5_SHIFT 8
43593 …3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 15. Used i…
43594 …RS_REG_CM_HDR_EVENT_ID_15_CM_HDR_E5_SHIFT 8
43629 …20 // Ordered list of building blocks in PTLD message for connection type 8. Unused blocks must …
43630 …10 // Ordered list of building blocks in PTLD message for connection type 8. Unused blocks must …
43648 … (0x3ff<<8) // The CM header. Used in packet start message to TCM. 9…
43649 …RS_REG_IPV6_EXT_CM_HDR_E5_SHIFT 8
43661 … (0x3ff<<8) // The CM header. Used in packet start message to TCM. 9…
43662 …RS_REG_AGG_TUNNEL_CM_HDR_E5_SHIFT 8
43674 … (0x3ff<<8) // The CM header. Used in packet start message to TCM. 9…
43675 …RS_REG_AGG_CM_HDR_E5_SHIFT 8
43723 … (0x1<<7) // Enables SOP; SOM & Sequence alignment to 8 byte boundaries; as …
43725 …_ENB_BB (0x1<<8) // If set; during e…
43726 …MAC_REG_CTRL_LOCAL_LPBK_LEAK_ENB_BB_SHIFT 8
43757 … (0x7f<<12) // Average interpacket gap. Must be >=8.
43761 … (0x7f<<25) // Lower 8 bits of throt_denom …
43764 … (0x1<<0) // Upper 8 bits of throt_denom …
43785 … SFD character and then processes the packet. If disabled; treats the first 8 bytes of packet as p…
43887 …X_LLFC_FC_OBJ_LOGICAL_BB (0xf<<8) // Value used for d…
43888 …MAC_REG_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_BB_SHIFT 8
43894 …X_LLFC_FC_OBJ_LOGICAL_BB (0xf<<8) // Value used to de…
43895 …MAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_BB_SHIFT 8
44013 …PPEND_CORRUPT_EN_0_K2_E5 (0x1<<8) // This bit control…
44014 …NIG_REG_NIG_PORT0_CONF_CRC_APPEND_CORRUPT_EN_0_K2_E5_SHIFT 8
44033 …PPEND_CORRUPT_EN_1_K2_E5 (0x1<<8) // This bit control…
44034 …NIG_REG_NIG_PORT1_CONF_CRC_APPEND_CORRUPT_EN_1_K2_E5_SHIFT 8
44053 …PPEND_CORRUPT_EN_2_K2_E5 (0x1<<8) // This bit control…
44054 …NIG_REG_NIG_PORT2_CONF_CRC_APPEND_CORRUPT_EN_2_K2_E5_SHIFT 8
44070 …YTE_COUNT_BB (0xff<<8) // Byte Count of th…
44071 …NIG_REG_PMFC_IF_CMD_PMFC_IF_BYTE_COUNT_BB_SHIFT 8
44085 …PPEND_CORRUPT_EN_3_K2_E5 (0x1<<8) // This bit control…
44086 …NIG_REG_NIG_PORT3_CONF_CRC_APPEND_CORRUPT_EN_3_K2_E5_SHIFT 8
44186 …YTE_COUNT_BB (0xff<<8) // Byte Count of th…
44187 …NIG_REG_PMEG_IF_CMD_PMEG_IF_BYTE_COUNT_BB_SHIFT 8
44266 …AFFIC_BB (0x1<<8) // Port0: If set al…
44267 …NIG_REG_LED_CONTROL_BLINK_TRAFFIC_BB_SHIFT 8
44272 …:RW DataWidth:0x8 // This register enable to read and write the cosmap 8 bit value for each N…
44274 … // Led mode: 0 -> MAC; 1-3 -> PHY1; 4 -> MAC2; 5-7 -> PHY4; 8 -> MAC3; 9 -…
44287 … (0x3<<8) // These bits makes…
44288 …NIG_REG_MAC_LED_SWAP_P2_BB_SHIFT 8
44306 …G_REG_DBG_OUT_DATA_SIZE 8
44352 …G_DBG_PMEG_RX_FAULT_PMEG_RX_REMOTE_FAULT_BB (0xf<<8) //
44353 …NIG_REG_CNIG_DBG_PMEG_RX_FAULT_PMEG_RX_REMOTE_FAULT_BB_SHIFT 8
44359 …G_DBG_PMFC_RX_FAULT_PMFC_RX_REMOTE_FAULT_BB (0xf<<8) //
44360 …NIG_REG_CNIG_DBG_PMFC_RX_FAULT_PMFC_RX_REMOTE_FAULT_BB_SHIFT 8
44405 …R_BB_K2 (0x1<<8) // End of packet er…
44406 …RM_REG_INT_STS_USTORM_EOP_ERR_BB_K2_SHIFT 8
44428 …RR_BB_K2 (0x1<<8) // This bit masks, …
44429 …RM_REG_INT_MASK_USTORM_EOP_ERR_BB_K2_SHIFT 8
44451 …_ERR_BB_K2 (0x1<<8) // End of packet er…
44452 …RM_REG_INT_STS_WR_USTORM_EOP_ERR_BB_K2_SHIFT 8
44474 …P_ERR_BB_K2 (0x1<<8) // End of packet er…
44475 …RM_REG_INT_STS_CLR_USTORM_EOP_ERR_BB_K2_SHIFT 8
44508 …I_MEM_PRTY_K2_E5 (0x1<<8) // This bit masks, …
44509 …RM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_E5_SHIFT 8
44510 …I_MEM_PRTY_BB (0x1<<8) // This bit masks, …
44511 …RM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_SHIFT 8
44604 …rm_dp.i_rdif.i_rdif_l1_sector0_mem.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
44605 …rm_dp.i_rdif.i_rdif_l1_sector0_mem.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
44606 …rm_dp.i_rdif.i_rdif_l1_sector1_mem.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
44607 …rm_dp.i_rdif.i_rdif_l1_sector1_mem.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
44608 …rm_dp.i_rdif.i_rdif_l1_sector2_mem.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
44609 …rm_dp.i_rdif.i_rdif_l1_sector2_mem.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
44702 …_REG_DBG_OUT_DATA_SIZE 8
44734 … (0xff<<8) // The maximum allo…
44735 …RC_REG_CTRL_MAXNUMHOPS_SHIFT 8
44796 … (0x1<<8) // Controls PXP Req…
44797 …RC_REG_PXP_CTRL_PXP_DONETYPE_SHIFT 8
44798 …ss:RW DataWidth:0x5 // The number of hash bits used for the search (h); Values can be 8 to 24.
44800 …_REG_EMPTY_PF_SIZE 8
44807 …_REG_DBG_OUT_DATA_SIZE 8
44832 …R (0x1<<8) // RSS command FIFO…
44833 …SS_REG_INT_STS_CMD_FIFO_ERROR_SHIFT 8
44877 …OR (0x1<<8) // This bit masks, …
44878 …SS_REG_INT_MASK_CMD_FIFO_ERROR_SHIFT 8
44922 …RROR (0x1<<8) // RSS command FIFO…
44923 …SS_REG_INT_STS_WR_CMD_FIFO_ERROR_SHIFT 8
44967 …ERROR (0x1<<8) // RSS command FIFO…
44968 …SS_REG_INT_STS_CLR_CMD_FIFO_ERROR_SHIFT 8
45078 …L //Access:R DataWidth:0x20 // Debug register. FIFO empty status: {b15:8 - inp_fifo_counter; …
45079 …/ Debug register. State of each state machine {b15:12 - calc_cur_state; b11:8 - main_cur_state;b7:…
45087 …_REG_DBG_OUT_DATA_SIZE 8
45111 …O_FIFO_FULL_E5 (0x1<<8) // The info fifo is…
45112 …SS_REG_FIFO_FULL_STATUS1_INFO_FIFO_FULL_E5_SHIFT 8
45138 …FO_FIFO_EMPTY_E5 (0x1<<8) // The info fifo is…
45139 …SS_REG_FIFO_EMPTY_STATUS1_INFO_FIFO_EMPTY_E5_SHIFT 8
45180 …STATE_E5 (0x3<<8) // calc_state delay…
45181 …SS_REG_STATE_MACHINES1_CALC_STATE_E5_SHIFT 8
45205 …H (0x1<<8) // TQ read underflo…
45206 …PB_REG_INT_STS_TQ_ERROR_RD_IH_SHIFT 8
45224 …IH (0x1<<8) // This bit masks, …
45225 …PB_REG_INT_MASK_TQ_ERROR_RD_IH_SHIFT 8
45243 …D_IH (0x1<<8) // TQ read underflo…
45244 …PB_REG_INT_STS_WR_TQ_ERROR_RD_IH_SHIFT 8
45262 …RD_IH (0x1<<8) // TQ read underflo…
45263 …PB_REG_INT_STS_CLR_TQ_ERROR_RD_IH_SHIFT 8
45316 …_REG_DBG_OUT_DATA_SIZE 8
45331 … // Page size in L2P table for CDU-Task module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8…
45332 …0x4 // Page size in L2P table for CDU module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8…
45333 …:0x4 // Page size in L2P table for TM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8…
45334 …:0x4 // Page size in L2P table for QM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8…
45335 …0x4 // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8…
45336 …0x4 // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8…
45337 …0x4 // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8…
45338 …0x4 // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8…
45339 …0x4 // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8…
45376 …RQ2_REG_DBG_OUT_DATA_SIZE 8
45401 … (0x1<<8) // E4: Indicates a …
45402 …SWRQ2_REG_INT_STS_L2P_VF_ERR_SHIFT 8
45438 …R (0x1<<8) // This bit masks, …
45439 …SWRQ2_REG_INT_MASK_L2P_VF_ERR_SHIFT 8
45475 …ERR (0x1<<8) // E4: Indicates a …
45476 …SWRQ2_REG_INT_STS_WR_L2P_VF_ERR_SHIFT 8
45512 …_ERR (0x1<<8) // E4: Indicates a …
45513 …SWRQ2_REG_INT_STS_CLR_L2P_VF_ERR_SHIFT 8
45553 …06_I_MEM_PRTY_BB (0x1<<8) // This bit masks, …
45554 …SWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT 8
45571 …10_I_MEM_PRTY_K2 (0x1<<8) // This bit masks, …
45572 …SWRQ2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_SHIFT 8
45638 …rmines alignment of write SRs when a request is split into several SRs. 0 - 8B aligned. 1 - 64B al…
45639 …ermines alignment of read SRs when a request is split into several SRs. 0 - 8B aligned. 1 - 64B al…
45667 … 0x240474UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 8 in pswrq memory.
45699 … 0x2404f4UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 8.
46182 …bit 1 no-snoop; bits 5:2 client id; bit 6 done type; bit 7 resevred; bit 10:8 pfid; bit 11 vf_vali…
46204 …ndow counter (i.e. 0 is for 1 clk_pci cycle; 1 is for 2 clk_pci cycles; 7 is for 8 clk_pci cycles).
46210 … 0x2408b0UL //Access:R DataWidth:0x9 // bit 8-0: srid.
46467 … 0x240c74UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 8
46491 …ID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is mapped to VQID 11. bit 6 is …
46492 …ID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is mapped to VQID 11. bit 6 is …
46493 …ID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is mapped to VQID 11. bit 6 is …
46494 …ID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is mapped to VQID 11. bit 6 is …
46495 …ID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is mapped to VQID 11. bit 6 is …
46496 …ID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is mapped to VQID 11. bit 6 is …
46497 …t 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to …
46513 …4 // Page size in L2P table for tgsrc module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8…
46514 …4 // Page size in L2P table for RGSRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8…
46557 …RQ_REG_DBG_OUT_DATA_SIZE 8
46583 …VERFLOW (0x1<<8) // Overflow in tsdm…
46584 …SWRQ_REG_INT_STS_TSDM_FIFO_OVERFLOW_SHIFT 8
46630 …OVERFLOW (0x1<<8) // This bit masks, …
46631 …SWRQ_REG_INT_MASK_TSDM_FIFO_OVERFLOW_SHIFT 8
46677 …O_OVERFLOW (0x1<<8) // Overflow in tsdm…
46678 …SWRQ_REG_INT_STS_WR_TSDM_FIFO_OVERFLOW_SHIFT 8
46724 …FO_OVERFLOW (0x1<<8) // Overflow in tsdm…
46725 …SWRQ_REG_INT_STS_CLR_TSDM_FIFO_OVERFLOW_SHIFT 8
46772 …0 - TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM; 5 - PSDM; 6 - QM; 7 - TM; 8 - SRC; 9 - DMAE; 10 …
46773 …0 - TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM; 5 - PSDM; 6 - QM; 7 - TM; 8 - SRC; 9 - DMAE; 10 …
46780 …WR_REG_DBG_OUT_DATA_SIZE 8
46804 …OVERFLOW (0x1<<8) // Overflow in cduw…
46805 …SWWR_REG_INT_STS_CDUWR_FIFO_OVERFLOW_SHIFT 8
46843 …_OVERFLOW (0x1<<8) // This bit masks, …
46844 …SWWR_REG_INT_MASK_CDUWR_FIFO_OVERFLOW_SHIFT 8
46882 …FO_OVERFLOW (0x1<<8) // Overflow in cduw…
46883 …SWWR_REG_INT_STS_WR_CDUWR_FIFO_OVERFLOW_SHIFT 8
46921 …IFO_OVERFLOW (0x1<<8) // Overflow in cduw…
46922 …SWWR_REG_INT_STS_CLR_CDUWR_FIFO_OVERFLOW_SHIFT 8
46948 …1[5:3] + 1) or (sum1[5:4] + 1) according to the definition in the spec. [10:8] - number_of_valid_6…
46976 …FLOW (0x1<<8) // Underflow in the…
46977 …SWWR2_REG_INT_STS_XSDM_UNDERFLOW_SHIFT 8
47021 …RFLOW (0x1<<8) // This bit masks, …
47022 …SWWR2_REG_INT_MASK_XSDM_UNDERFLOW_SHIFT 8
47066 …DERFLOW (0x1<<8) // Underflow in the…
47067 …SWWR2_REG_INT_STS_WR_XSDM_UNDERFLOW_SHIFT 8
47111 …NDERFLOW (0x1<<8) // Underflow in the…
47112 …SWWR2_REG_INT_STS_CLR_XSDM_UNDERFLOW_SHIFT 8
47161 …18_I_MEM_PRTY_5_E5 (0x1<<8) // This bit masks, …
47162 …SWWR2_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_5_E5_SHIFT 8
47237 …14_I_MEM_PRTY_6_BB_K2 (0x1<<8) // This bit masks, …
47238 …SWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_6_BB_K2_SHIFT 8
47282 …11_I_MEM_PRTY_0_E5 (0x1<<8) // This bit masks, …
47283 …SWWR2_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_0_E5_SHIFT 8
47354 …09_I_MEM_PRTY_1_BB_K2 (0x1<<8) // This bit masks, …
47355 …SWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_1_BB_K2_SHIFT 8
47413 …12_I_MEM_PRTY_4_E5 (0x1<<8) // This bit masks, …
47414 …SWWR2_REG_PRTY_MASK_H_2_MEM012_I_MEM_PRTY_4_E5_SHIFT 8
47485 …10_I_MEM_PRTY_5_BB_K2 (0x1<<8) // This bit masks, …
47486 …SWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_5_BB_K2_SHIFT 8
47542 …05_I_MEM_PRTY_4_E5 (0x1<<8) // This bit masks, …
47543 …SWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_4_E5_SHIFT 8
47544 …05_I_MEM_PRTY_5_BB_K2 (0x1<<8) // This bit masks, …
47545 …SWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_5_BB_K2_SHIFT 8
47635 …15_I_MEM_PRTY_4_E5 (0x1<<8) // This bit masks, …
47636 …SWWR2_REG_PRTY_MASK_H_4_MEM015_I_MEM_PRTY_4_E5_SHIFT 8
47680 …RD_REG_DBG_OUT_DATA_SIZE 8
47720 …RD2_REG_FIRST_SR_NODES_SIZE 8
47771 …lients: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 PBF (TDIF); 7 QM; 8 TM; 9 SRC; 10 CDURD;…
47772 …-client maximum sync FIFO fill level since reset in 16B lines. 7:0 TSDM; 15:8 MSDM; 23:16 USDM; 31…
47773 …-client maximum sync FIFO fill level since reset in 16B lines. 7:0 YSDM; 15:8 PSDM; 23:16 QM; 31:2…
47774 …r-client maximum sync FIFO fill level since reset in 16B lines. 7:0 SRC; 15:8 CDU; 23:16 DMAE; 31:…
47775 …-client maximum sync FIFO fill level since reset in 16B lines. 7:0 XYLD. 15:8 PTU. 23:16 TGSRC; 31…
47848 …25_I_ECC_RF_INT_BB_K2 (0x1<<8) // This bit masks, …
47849 …SWRD2_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_BB_K2_SHIFT 8
47856 …28_I_ECC_RF_INT_E5 (0x1<<8) // This bit masks, …
47857 …SWRD2_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_E5_SHIFT 8
47967 ….TETRIS_64_GEN_FOR[3].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
47968 ….TETRIS_64_GEN_FOR[0].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
47969 ….TETRIS_64_GEN_FOR[0].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
47970 ….TETRIS_64_GEN_FOR[4].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
47971 ….TETRIS_64_GEN_FOR[1].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
47972 ….TETRIS_64_GEN_FOR[1].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
47973 ….TETRIS_64_GEN_FOR[5].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
47974 ….TETRIS_64_GEN_FOR[2].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
47975 ….TETRIS_64_GEN_FOR[2].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
47976 ….TETRIS_64_GEN_FOR[6].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
47977 ….TETRIS_64_GEN_FOR[3].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
47978 ….TETRIS_64_GEN_FOR[4].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
47979 ….TETRIS_64_GEN_FOR[5].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
47980 ….TETRIS_64_GEN_FOR[6].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb o…
48002 …EM025_I_ECC_EN_BB_K2 (0x1<<8) // Enable ECC for m…
48003 …SWRD2_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN_BB_K2_SHIFT 8
48010 …EM028_I_ECC_EN_E5 (0x1<<8) // Enable ECC for m…
48011 …SWRD2_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_EN_E5_SHIFT 8
48045 …Y_0_MEM025_I_ECC_PRTY_BB_K2 (0x1<<8) // Set parity only …
48046 …SWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY_BB_K2_SHIFT 8
48053 …Y_0_MEM028_I_ECC_PRTY_E5 (0x1<<8) // Set parity only …
48054 …SWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_PRTY_E5_SHIFT 8
48088 …ECTED_0_MEM025_I_ECC_CORRECT_BB_K2 (0x1<<8) // Record if a corr…
48089 …SWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT_BB_K2_SHIFT 8
48096 …ECTED_0_MEM028_I_ECC_CORRECT_E5 (0x1<<8) // Record if a corr…
48097 …SWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_CORRECT_E5_SHIFT 8
48117 …RD2_REG_DBG_OUT_DATA_SIZE 8
48154 …HST2_REG_DBG_OUT_DATA_SIZE 8
48213 …4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERV…
48216 …4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERV…
48221 …0x2a007cUL //Access:R DataWidth:0x11 // Log of the permission violation: {QID[8:0];VFID[7:0]}.
48225 …nternal write interface: [1:0] usdm; [3:2] xsdm; [5:4] msdm; [7:6] ysdm; [9:8] psdm; [11:10] tsdm;…
48226 …the format is: [3:0] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 PBF; 7 QM; 8 NIG).
48231 …nternal write interface. [1:0] usdm; [3:2] xsdm; [5:4] msdm; [7:6] ysdm; [9:8] psdm; [11:10] tsdm;…
48235 …4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERV…
48259 …HST_REG_DBG_OUT_DATA_SIZE 8
48262 …ask decoding: (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 PBF; 7 QM; 8 NIG; 9 HOST WR; 10 H…
48263 …HST_REG_CLIENTS_WAITING_TO_SOURCE_ARB_SIZE 8
48281 …NC_FIFO_ERR (0x1<<8) // An error in comp…
48282 …SWHST_REG_INT_STS_HST_CPL_SYNC_FIFO_ERR_SHIFT 8
48293 … (0x1<<14) // An error in write source FIFO 8.
48318 …YNC_FIFO_ERR (0x1<<8) // This bit masks, …
48319 …SWHST_REG_INT_MASK_HST_CPL_SYNC_FIFO_ERR_SHIFT 8
48355 …_SYNC_FIFO_ERR (0x1<<8) // An error in comp…
48356 …SWHST_REG_INT_STS_WR_HST_CPL_SYNC_FIFO_ERR_SHIFT 8
48367 … (0x1<<14) // An error in write source FIFO 8.
48392 …L_SYNC_FIFO_ERR (0x1<<8) // An error in comp…
48393 …SWHST_REG_INT_STS_CLR_HST_CPL_SYNC_FIFO_ERR_SHIFT 8
48404 … (0x1<<14) // An error in write source FIFO 8.
48432 …09_I_MEM_PRTY (0x1<<8) // This bit masks, …
48433 …SWHST_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT 8
48480 …SLATION_SIZE_DIFFERENT (0x1<<8) // Indicates a func…
48481 …GLUE_B_REG_INT_STS_TCPL_TRANSLATION_SIZE_DIFFERENT_SHIFT 8
48529 …NSLATION_SIZE_DIFFERENT (0x1<<8) // This bit masks, …
48530 …GLUE_B_REG_INT_MASK_TCPL_TRANSLATION_SIZE_DIFFERENT_SHIFT 8
48578 …RANSLATION_SIZE_DIFFERENT (0x1<<8) // Indicates a func…
48579 …GLUE_B_REG_INT_STS_WR_TCPL_TRANSLATION_SIZE_DIFFERENT_SHIFT 8
48627 …TRANSLATION_SIZE_DIFFERENT (0x1<<8) // Indicates a func…
48628 …GLUE_B_REG_INT_STS_CLR_TCPL_TRANSLATION_SIZE_DIFFERENT_SHIFT 8
48683 …025_I_MEM_PRTY_K2_E5 (0x1<<8) // This bit masks, …
48684 …GLUE_B_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2_E5_SHIFT 8
48705 …013_I_MEM_PRTY_BB (0x1<<8) // This bit masks, …
48706 …GLUE_B_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_SHIFT 8
48780 …UE_B_REG_DBG_OUT_DATA_SIZE 8
48804 …L_PARITY_MODE (0x1<<8) // This bit forces …
48805 …GLUE_B_REG_PGL_CORE_DEBUG_PGL_PARITY_MODE_SHIFT 8
48840 …Width:0x5 // Pseudo VF target mode configuration that defines first VF divided by 8 for each PF.
48842 …UL //Access:RW DataWidth:0x9 // VSC fields: bit 0 - enable VSC; bits 1-8 - VSC reserved bits …
48848 …XW_CC_THRESH (0x1f<<8) // The fullness thr…
48849 …GLUE_B_REG_PGL_CONTROL0_PGL_TXW_CC_THRESH_SHIFT 8
49002 …upt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolutio…
49003 …upt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolutio…
49006 …upt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolutio…
49007 …upt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolutio…
49010 …upt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolutio…
49011 …upt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolutio…
49014 …upt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolutio…
49015 …upt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolutio…
49018 …upt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolutio…
49019 …upt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolutio…
49022 …upt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolutio…
49023 …upt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolutio…
49065 …CPL_IN_TWO_RCBS_DETAILS. Bit 7 - clears ADMIN_WINDOW_VIOLATION_DETAILS. Bit 8 - clears OUT_OF_RANG…
49070 …8KB of IGU in BAR0 (MSIX table and PBA) are not allowed. When this value is configured; BAR2 size …
49072 …equest on RX Lanes. 5 - ECRC error on RX Lanes. 6 - Reserved. 7 - Reserved. 8 - Illegal operation …
49092 …L_MAX_TAGS_DISABLE (0x1<<8) // This field disab…
49093 …GLUE_B_REG_PGL_TAGS_LIMIT_PGL_MAX_TAGS_DISABLE_SHIFT 8
49094 … 0x2aa440UL //Access:RW DataWidth:0x1a // 8 memories; each corre…
49096 … 0x2aa460UL //Access:RW DataWidth:0x1a // 8 memories; each corre…
49098 … 0x2aa480UL //Access:RW DataWidth:0x1a // 8 memories; each corre…
49100 … 0x2aa4a0UL //Access:RW DataWidth:0x1a // 8 memories; each corre…
49102 … 0x2aa4c0UL //Access:RW DataWidth:0x1a // 8 memories; each corre…
49104 … 0x2aa4e0UL //Access:RW DataWidth:0x1a // 8 memories; each corre…
49106 … 0x2aa500UL //Access:RW DataWidth:0x1a // 8 memories; each corre…
49108 … 0x2aa520UL //Access:RW DataWidth:0x1a // 8 memories; each corre…
49116 …ns an out of range function. [3:0] - original PFID. [7:4] Pretend PFID. [15:8] Pretend VFID. [16] …
49119 …4UL //Access:RW DataWidth:0x6 // Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.
49120 …8UL //Access:RW DataWidth:0x6 // Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.
49121 …cUL //Access:RW DataWidth:0x6 // Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.
49122 …0UL //Access:RW DataWidth:0x6 // Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.
49123 …4UL //Access:RW DataWidth:0x6 // Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.
49124 …8UL //Access:RW DataWidth:0x6 // Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.
49127 …cess:RW DataWidth:0x3 // Window size for VF to PF channel. 0 - NA; 1 - 8B; 2 - 16B; 3 - 32B; …
49128 …aWidth:0x6 // Defines the start offset of the VF to PF window within VF ZoneB in 8B granularity.
49151 …SETTING_ATTENTION_SETTING_VF_FID_ENABLE (0x3<<8) // Attention settin…
49152 …GLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_VF_FID_ENABLE_SHIFT 8
49190 …sing resizable BAR, the driver should read the value from BAR_SIZE (bits 12:8 in PCIE_REG_PCIER_RB…
49191 …e IP config space (bits 11:8 in PCIE_REG_PCIER_REG_VF_BAR_REG) and configure to this register. Dec…
49210 …PCIe IP config space (bits 11:8 in PCIE_REG_PCIER_REG_VF_BAR_REG) and configure to this register. …
49211 …PCIe IP config space (bits 11:8 in PCIE_REG_PCIER_REG_VF_BAR_REG) and configure to this register. …
49262 … 0x2aafccUL //Access:R DataWidth:0x12 // 8:0 - RX target read …
49314 …O_FIFO_UN (0x1<<8) // CFC LOAD ECHO FI…
49315 …M_REG_INT_STS_0_CFC_LOAD_ECHO_FIFO_UN_SHIFT 8
49379 …HO_FIFO_UN (0x1<<8) // This bit masks, …
49380 …M_REG_INT_MASK_0_CFC_LOAD_ECHO_FIFO_UN_SHIFT 8
49444 …ECHO_FIFO_UN (0x1<<8) // CFC LOAD ECHO FI…
49445 …M_REG_INT_STS_WR_0_CFC_LOAD_ECHO_FIFO_UN_SHIFT 8
49509 …_ECHO_FIFO_UN (0x1<<8) // CFC LOAD ECHO FI…
49510 …M_REG_INT_STS_CLR_0_CFC_LOAD_ECHO_FIFO_UN_SHIFT 8
49574 …ADERR_TASK (0x1<<8) // Tasks Load respo…
49575 …M_REG_INT_STS_1_CLOAD_RES_LOADERR_TASK_SHIFT 8
49597 …OADERR_TASK (0x1<<8) // This bit masks, …
49598 …M_REG_INT_MASK_1_CLOAD_RES_LOADERR_TASK_SHIFT 8
49620 …_LOADERR_TASK (0x1<<8) // Tasks Load respo…
49621 …M_REG_INT_STS_WR_1_CLOAD_RES_LOADERR_TASK_SHIFT 8
49643 …S_LOADERR_TASK (0x1<<8) // Tasks Load respo…
49644 …M_REG_INT_STS_CLR_1_CLOAD_RES_LOADERR_TASK_SHIFT 8
49678 …_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
49679 …M_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5_SHIFT 8
49684 …_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, …
49685 …M_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2_SHIFT 8
49741 …W DataWidth:0x4 // Almost full threshold for the PXP READ CTRL FIFO, which its size is 8 rows.
49748 …// Almost full threshold for the EXPIRATION COMMAND FIFO, which its size is 8 rows. For Debug only.
49772 …s. 11 - each group is selected to be scanned based on its nearest timer, every 1,8,64 scan pulses.
49773 …s. 11 - each group is selected to be scanned based on its nearest timer, every 1,8,64 scan pulses.
49780 …8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for ty…
49781 …8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for ty…
49782 …8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for ty…
49783 …8 types), configuration of the applicable client out interface that the expiration command is sent…
49784 …8 types), configuration of the applicable client out interface that the expiration command is sent…
49785 …8 types), configuration of the applicable client out interface that the expiration command is sent…
49786 …8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for ty…
49787 …8 types), configuration of the applicable client out interface that the stop all expiration comman…
49788 …8] - threshold selection for type 4, Bits [11:10] - threshold selection for type 5, Bits [13:12] -…
49789 …8] - threshold selection for type 4, Bits [11:10] - threshold selection for type 5, Bits [13:12] -…
49790 …8] - threshold selection for type 4, Bits [11:10] - threshold selection for type 5, Bits [13:12] -…
49791 …8 types), configuration of the threshold on the nearest expiration for sending write command to ho…
49792 …8 types), configuration of the threshold on the nearest expiration for sending write command to ho…
49793 …8 types), configuration of the threshold on the nearest expiration for sending write command to ho…
49872 …//Access:R DataWidth:0x17 // The load response with error fields: Bits 8-0: LCID, Bit 9: scan…
49874 …xb // The CDU context read with last indication de-asserted fields: Bits 8-0: LCID, Bit 9: Type…
49876 …d // The CDU context write with last indication de-asserted fields: Bits 8-0: LCID, Bit 9: Type…
49877 … Bits 7-4: write_timer. Bits 9-8: read_fifo. …
49879 …h bvalid != 0. The parameters for the errored data: Bits 8-0: function # (0-239…
49886 …REG_DBG_OUT_DATA_SIZE 8
49986 …C_REG_DBG_OUT_DATA_SIZE 8
50037 …OM_REQ (0x1<<8) // Debug only.
50038 …CFC_REG_DEBUG1_TYPE_FROM_REQ_SHIFT 8
50114 …C_REG_FLOAD_RGN_MSK_SIZE 8
50132 … //Access:RW DataWidth:0x9 // This is the LCID Threshold for LC CLient 8 (PSDM). When the num…
50210 …C_REG_STRING_CAM_SIZE 8
50329 …C_REG_DBG_OUT_DATA_SIZE 8
50380 …OM_REQ (0x1<<8) // Debug only.
50381 …CFC_REG_DEBUG1_TYPE_FROM_REQ_SHIFT 8
50457 …C_REG_FLOAD_RGN_MSK_SIZE 8
50475 … //Access:RW DataWidth:0x9 // This is the LCID Threshold for LC CLient 8 (PSDM). When the num…
50580 …RR (0x1<<8) // Decrement underf…
50581 …M_REG_INT_STS_BYTE_CRD_DEC_ERR_SHIFT 8
50625 …ERR (0x1<<8) // This bit masks, …
50626 …M_REG_INT_MASK_BYTE_CRD_DEC_ERR_SHIFT 8
50670 …C_ERR (0x1<<8) // Decrement underf…
50671 …M_REG_INT_STS_WR_BYTE_CRD_DEC_ERR_SHIFT 8
50715 …EC_ERR (0x1<<8) // Decrement underf…
50716 …M_REG_INT_STS_CLR_BYTE_CRD_DEC_ERR_SHIFT 8
50760 …XT_A (0x1<<8) // This bit masks, …
50761 …M_REG_PRTY_MASK_BIGRAMHIGH_EXT_A_SHIFT 8
50783 …_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
50784 …M_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 8
50789 …_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, …
50790 …M_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2_SHIFT 8
50920 …_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
50921 …M_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_E5_SHIFT 8
50986 …_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, …
50987 …M_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_BB_K2_SHIFT 8
51033 …_MEM_PRTY_8_E5 (0x1<<8) // This bit masks, …
51034 …M_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_8_E5_SHIFT 8
51069 …_MEM_PRTY_11_K2 (0x1<<8) // This bit masks, …
51070 …M_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_11_K2_SHIFT 8
51091 …_MEM_PRTY_BB (0x1<<8) // This bit masks, …
51092 …M_REG_PRTY_MASK_H_2_MEM002_I_MEM_PRTY_BB_SHIFT 8
51183 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51184 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51185 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51186 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51187 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51188 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51189 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51190 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51191 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51192 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51193 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51194 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51195 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51196 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51197 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51198 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51199 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51200 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51201 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51202 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51203 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51204 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51205 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51206 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51207 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51208 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51209 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51210 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51211 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51212 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51213 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51214 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51215 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51216 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51217 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51218 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51219 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51220 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51221 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51222 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51223 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51224 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51225 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51226 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51227 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51228 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51229 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51230 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51231 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51232 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51233 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51234 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51235 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51236 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51237 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51238 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51239 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51240 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51241 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51242 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51243 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51244 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51245 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51246 …onfiguration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 …
51368 …nimal STU within the PXP (there is STU per PF). 0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8…
51369 …th:0x10 // The PCI TPH field used in the PCI request. Per PF value. bits: 8-0 TPH Steering Tag I…
51375 …depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31] are "not used".…
51377 …depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31] are "not used".…
51383 …depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31] are "not used".…
51395 …; 2 - PF WFQ; 3 - VP WFQ; 4 - PF RL; 5 - global VP-QCN RL; 6 - FW stop; 7 - reserved; 8 - PQ Empty.
51436 …- UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM p…
51437 …- UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM p…
51438 …- UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM p…
51439 …- UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM p…
51440 …- UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM p…
51441 …- UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM p…
51442 …- UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM p…
51443 …- UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM p…
51444 …- UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM p…
51445 …- UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM p…
51446 …- UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM p…
51447 …8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM sec; 63-56 YCM pr…
51466 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51467 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51468 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51469 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51470 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51471 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51472 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51473 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51474 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51475 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51476 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51477 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51478 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51479 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51480 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51481 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51482 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51483 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51484 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51485 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51486 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51487 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51488 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51489 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51490 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51491 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51492 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51493 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51494 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51495 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51496 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51497 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51498 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51499 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51500 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51501 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51502 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51503 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51504 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51505 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51506 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51507 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51508 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51509 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51510 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51511 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51512 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51513 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51514 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51515 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51516 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51517 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51518 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51519 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51520 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51521 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51522 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51523 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51524 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51525 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51526 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51527 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51528 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51529 …the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51530 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51531 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51532 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51533 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51534 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51535 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51536 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51537 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51538 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51539 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51540 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51541 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51542 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51543 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51544 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51545 … PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0)…
51568 … // almost full threshold for the xsdm fifo. the value refer fifo size of 8. if the fifo size is…
51569 … // almost full threshold for the ysdm fifo. the value refer fifo size of 8. if the fifo size is…
51570 … // almost full threshold for the psdm fifo. the value refer fifo size of 8. if the fifo size is…
51599 …REG_RLPFINCVAL_SIZE_BB 8
51602 …REG_RLPFUPPERBOUND_SIZE_BB 8
51605 …REG_RLPFCRD_SIZE_BB 8
51608 …depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31] are "not used".…
51614 …REG_WFQPFWEIGHT_SIZE_BB 8
51617 …REG_WFQPFUPPERBOUND_SIZE_BB 8
51619 …epending on the port_mode. Namely : port_mode == 0 (1 port device ) : VOQs [8..15] are "not used" …
51939 …8:1 - RL id; bits 17:9 - VP id (value of all ones is reserved for pure-LB VOQ VP-s. no WFQ is i…
51951 …depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31,33,34,35] are "n…
51957 …8 MSB PF of VOQ0 in K2. Counters 8-15 are associated with 8 MSB PF of VOQ1 in K2. ... Counters 13…
51961 …8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM sec; 63-56 YCM pr…
51962 …8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM sec; 63-56 YCM pr…
51994 …riting to this register (any value) will copy the data in buffer 0 to the debug_buffer_0_data_0..8.
51996 …riting to this register (any value) will copy the data in buffer 0 to the debug_buffer_1_data_0..8.
52009 …ze; [19] eob_flag ; [18] data_is_dix ; [17] set_id ; [16:13] protocol_id; [12:9] type; [8:0] ltid.
52010 … [12] fwrd_app ; [11] fwrd_guard ; [10] validate_ref ; [9] validate_app ; [8] validate_guard ; [7…
52018 …ze; [19] eob_flag ; [18] data_is_dix ; [17] set_id ; [16:13] protocol_id; [12:9] type; [8:0] ltid.
52019 … [12] fwrd_app ; [11] fwrd_guard ; [10] validate_ref ; [9] validate_app ; [8] validate_guard ; [7…
52023 … FWRD ref; [4] FWR app; [5] FWRD guard; [6] vlidate ref; [7] validate app; [8] validate guard; [12…
52044 …_K2_E5 (0x1<<8) // One of the comma…
52045 …DIF_REG_INT_STS_L1_DIRTY_BIT_K2_E5_SHIFT 8
52063 …T_K2_E5 (0x1<<8) // This bit masks, …
52064 …DIF_REG_INT_MASK_L1_DIRTY_BIT_K2_E5_SHIFT 8
52082 …BIT_K2_E5 (0x1<<8) // One of the comma…
52083 …DIF_REG_INT_STS_WR_L1_DIRTY_BIT_K2_E5_SHIFT 8
52101 …_BIT_K2_E5 (0x1<<8) // One of the comma…
52102 …DIF_REG_INT_STS_CLR_L1_DIRTY_BIT_K2_E5_SHIFT 8
52106 … 0x300400UL //Access:R DataWidth:0x20 // Information on the first 8 DIF errors found. On…
52114 …F_REG_DBG_OUT_DATA_SIZE 8
52117 … Address offset-2 bits [5]; Field name-Interval size Address offset-2 bits [8:6]; Field name-Host …
52118 …per task context is as follows: In TDIF - Has 8 QWORDs per task allocated (All are valid). In RDIF…
52128 …riting to this register (any value) will copy the data in buffer 0 to the debug_buffer_0_data_0..8.
52130 …riting to this register (any value) will copy the data in buffer 0 to the debug_buffer_1_data_0..8.
52143 …ze; [19] eob_flag ; [18] data_is_dix ; [17] set_id ; [16:13] protocol_id; [12:9] type; [8:0] ltid.
52144 … [12] fwrd_app ; [11] fwrd_guard ; [10] validate_ref ; [9] validate_app ; [8] validate_guard ; [7…
52152 …ze; [19] eob_flag ; [18] data_is_dix ; [17] set_id ; [16:13] protocol_id; [12:9] type; [8:0] ltid.
52153 … [12] fwrd_app ; [11] fwrd_guard ; [10] validate_ref ; [9] validate_app ; [8] validate_guard ; [7…
52157 … FWRD ref; [4] FWR app; [5] FWRD guard; [6] vlidate ref; [7] validate app; [8] validate guard; [12…
52158 …OB arrived and DIX write pointer != DIX read pointer.); [7:4] protocol ID; [8] buffer inuse; [17:9…
52168 …Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol ID 8.
52194 …_K2_E5 (0x1<<8) // One of the comma…
52195 …DIF_REG_INT_STS_L1_DIRTY_BIT_K2_E5_SHIFT 8
52213 …T_K2_E5 (0x1<<8) // This bit masks, …
52214 …DIF_REG_INT_MASK_L1_DIRTY_BIT_K2_E5_SHIFT 8
52232 …BIT_K2_E5 (0x1<<8) // One of the comma…
52233 …DIF_REG_INT_STS_WR_L1_DIRTY_BIT_K2_E5_SHIFT 8
52251 …_BIT_K2_E5 (0x1<<8) // One of the comma…
52252 …DIF_REG_INT_STS_CLR_L1_DIRTY_BIT_K2_E5_SHIFT 8
52273 …_I_MEM_PRTY (0x1<<8) // This bit masks, …
52274 …DIF_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT 8
52311 … 0x310400UL //Access:R DataWidth:0x20 // Information on the first 8 DIF errors found. On…
52319 …F_REG_DBG_OUT_DATA_SIZE 8
52322 …per task context is as follows: In TDIF - Has 8 QWORDs per task allocated (All are valid). In RDIF…
52331 …RC_REG_DBG_OUT_DATA_SIZE 8
52373 …N*HASH/8 + N*16*RF_GSRC_CTX_SIZE) if HASH is not aligned to 64, set RF_GSRC_TABLE_T1_…
52374 …N*HASH/8 + N*16*RF_GSRC_CTX_SIZE) if HASH is not aligned to 64, set RF_GSRC_TABLE_T2…
52382 … (0x1ff<<8) // Controls PXP Req…
52383 …GSRC_REG_PXP_CTRL_TPH_INDEX_E5_SHIFT 8
52405 …RC_REG_DBG_OUT_DATA_SIZE 8
52447 …N*HASH/8 + N*16*RF_GSRC_CTX_SIZE) if HASH is not aligned to 64, set RF_GSRC_TABLE_T1_…
52448 …N*HASH/8 + N*16*RF_GSRC_CTX_SIZE) if HASH is not aligned to 64, set RF_GSRC_TABLE_T2…
52456 … (0x1ff<<8) // Controls PXP Req…
52457 …GSRC_REG_PXP_CTRL_TPH_INDEX_E5_SHIFT 8
52493 …_ERROR (0x1<<8) // Read packet clie…
52494 …RB_REG_INT_STS_0_RC_PKT1_LEN_ERROR_SHIFT 8
52558 …N_ERROR (0x1<<8) // This bit masks, …
52559 …RB_REG_INT_MASK_0_RC_PKT1_LEN_ERROR_SHIFT 8
52623 …LEN_ERROR (0x1<<8) // Read packet clie…
52624 …RB_REG_INT_STS_WR_0_RC_PKT1_LEN_ERROR_SHIFT 8
52688 …_LEN_ERROR (0x1<<8) // Read packet clie…
52689 …RB_REG_INT_STS_CLR_0_RC_PKT1_LEN_ERROR_SHIFT 8
52749 …INT_FIFO_ERROR (0x1<<8) // Free ointer FIFO…
52750 …RB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT 8
52810 …OINT_FIFO_ERROR (0x1<<8) // This bit masks, …
52811 …RB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT 8
52871 …_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO…
52872 …RB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT 8
52932 …E_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO…
52933 …RB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT 8
52997 …IL_FIFO_ERROR (0x1<<8) // Warning! Check t…
52998 …RB_REG_INT_STS_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT 8
53054 …AIL_FIFO_ERROR (0x1<<8) // This bit masks, …
53055 …RB_REG_INT_MASK_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT 8
53111 …AVAIL_FIFO_ERROR (0x1<<8) // Warning! Check t…
53112 …RB_REG_INT_STS_WR_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT 8
53168 …_AVAIL_FIFO_ERROR (0x1<<8) // Warning! Check t…
53169 …RB_REG_INT_STS_CLR_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT 8
53223 …R_FIFO_ERROR (0x1<<8) // Read packet clie…
53224 …RB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT 8
53286 …CR_FIFO_ERROR (0x1<<8) // This bit masks, …
53287 …RB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT 8
53349 …DSCR_FIFO_ERROR (0x1<<8) // Read packet clie…
53350 …RB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT 8
53412 …_DSCR_FIFO_ERROR (0x1<<8) // Read packet clie…
53413 …RB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT 8
53477 …ETCH_FIFO_ERROR (0x1<<8) // Link list arbite…
53478 …RB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT 8
53532 …FETCH_FIFO_ERROR (0x1<<8) // This bit masks, …
53533 …RB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT 8
53587 …REFETCH_FIFO_ERROR (0x1<<8) // Link list arbite…
53588 …RB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT 8
53642 …PREFETCH_FIFO_ERROR (0x1<<8) // Link list arbite…
53643 …RB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT 8
53777 …NT_ERROR (0x1<<8) // Warning! Check t…
53778 …RB_REG_INT_STS_7_WC4_LL_PA_CNT_ERROR_SHIFT 8
53842 …CNT_ERROR (0x1<<8) // This bit masks, …
53843 …RB_REG_INT_MASK_7_WC4_LL_PA_CNT_ERROR_SHIFT 8
53907 …A_CNT_ERROR (0x1<<8) // Warning! Check t…
53908 …RB_REG_INT_STS_WR_7_WC4_LL_PA_CNT_ERROR_SHIFT 8
53972 …PA_CNT_ERROR (0x1<<8) // Warning! Check t…
53973 …RB_REG_INT_STS_CLR_7_WC4_LL_PA_CNT_ERROR_SHIFT 8
54037 …INT_FIFO_ERROR (0x1<<8) // Warning! Check t…
54038 …RB_REG_INT_STS_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT 8
54072 …OINT_FIFO_ERROR (0x1<<8) // This bit masks, …
54073 …RB_REG_INT_MASK_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT 8
54107 …_POINT_FIFO_ERROR (0x1<<8) // Warning! Check t…
54108 …RB_REG_INT_STS_WR_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT 8
54142 …T_POINT_FIFO_ERROR (0x1<<8) // Warning! Check t…
54143 …RB_REG_INT_STS_CLR_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT 8
54416 …I_ECC_RF_INT (0x1<<8) // This bit masks, …
54417 …RB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_SHIFT 8
54541 …I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
54542 …RB_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_E5_SHIFT 8
54589 …I_MEM_PRTY_BB (0x1<<8) // This bit masks, …
54590 …RB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_BB_SHIFT 8
54641 …I_MEM_PRTY_K2 (0x1<<8) // This bit masks, …
54642 …RB_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2_SHIFT 8
54699 … (0x1<<8) // Enable ECC for memory ecc instance brb.BB_BANK_K…
54700 …RB_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_SHIFT 8
54751 … (0x1<<8) // Set parity only for memory ecc instance brb.BB_BANK…
54752 …RB_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_SHIFT 8
54803 … (0x1<<8) // Record if a correctable error occurred on memory ecc instance …
54804 …RB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_SHIFT 8
54840 …te up to two ECC errors on the next write to memory: brb.BB_BANK_BB_GEN_FOR[8].BB_BANK_BB_GEN_IF.i…
55080 …RC_PRI (0x3<<8) // This is priority…
55081 …RB_REG_RC_PKT_PRIORITY_TMLD_RC_PRI_SHIFT 8
55095 …ient upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.
55112 …_REG_DBG_OUT_DATA_SIZE 8
55141 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55142 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55143 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55144 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55145 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55146 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55147 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55148 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55149 … write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
55150 … write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
55151 … write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
55152 … write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
55153 … write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
55154 … write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
55155 … write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
55156 … write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
55159 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
55160 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
55161 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
55162 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
55163 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
55164 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
55165 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
55166 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
55167 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
55168 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
55169 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
55170 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
55171 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
55172 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
55173 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
55176 …th:0x10 // Debug register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr…
55245 … register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/S…
55246 … register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/S…
55247 … register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/S…
55248 … register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/S…
55253 …g register. Output full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/S…
55254 …g register. Output full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/S…
55255 …g register. Output full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/S…
55256 …g register. Output full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/S…
55261 …er. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55262 …er. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55263 …er. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55264 …er. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55265 …er. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55266 …er. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55267 …er. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55268 …er. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55269 …er. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55270 …er. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55271 …er. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55272 …er. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55273 …er. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55274 …er. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55275 …er. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55276 …er. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55277 …er. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55278 …er. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55279 …er. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55280 …er. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55281 …er. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55282 …er. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55283 …er. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55284 …er. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/B…
55285 …nt lossless counter interrupt for each TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/S…
55286 …nt lossless counter interrupt for each TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/S…
55287 …nt lossless counter interrupt for each TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/S…
55288 …nt lossless counter interrupt for each TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/S…
55298 …8-16 are port 1 (lb 0) TCs 0-8. Similarly for entries 17-24 for port 2 and 25-33 for port 3. In K2…
55301 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55303 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55305 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55307 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55309 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55311 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55313 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55315 …8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: …
55338 …:0x3 // Number of slots at the PCI read response buffer: 3=4/8 slots of 512 bytes;4=8/16 slots …
55392 …h SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.
55393 …ster for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length ou…
55467 …_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
55468 …YLD_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 8
55483 …_I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, …
55484 …YLD_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT 8
55551 …0_OFFSET_01_E5 (0xff<<8) // Offset in 32b un…
55552 …YLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5_SHIFT 8
55560 …1_OFFSET_11_E5 (0xff<<8) // Offset in 32b un…
55561 …YLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5_SHIFT 8
55569 …2_OFFSET_21_E5 (0xff<<8) // Offset in 32b un…
55570 …YLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5_SHIFT 8
55578 …3_OFFSET_31_E5 (0xff<<8) // Offset in 32b un…
55579 …YLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5_SHIFT 8
55589 …1_LEN_02_E5 (0xf<<8) // length in 32b un…
55590 …YLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5_SHIFT 8
55606 …3_LEN_22_E5 (0xf<<8) // length in 32b un…
55607 …YLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5_SHIFT 8
55653 …_DUP_OFFSET_01_E5 (0xff<<8) // Offset in 32b un…
55654 …YLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5_SHIFT 8
55662 …_DUP_OFFSET_11_E5 (0xff<<8) // Offset in 32b un…
55663 …YLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5_SHIFT 8
55671 …_DUP_OFFSET_21_E5 (0xff<<8) // Offset in 32b un…
55672 …YLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5_SHIFT 8
55680 …_DUP_OFFSET_31_E5 (0xff<<8) // Offset in 32b un…
55681 …YLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5_SHIFT 8
55742 …SET_1_E5 (0xff<<8) // offset in 32b un…
55743 …YLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5_SHIFT 8
55753 …MAX_L2MA_2_E5 (0xf<<8) // the maximal numb…
55754 …YLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5_SHIFT 8
55760 …D_INC_EVENT_ID_1_E5 (0xff<<8) // The value by whi…
55761 …YLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5_SHIFT 8
55779 …D_REG_DBG_OUT_DATA_SIZE 8
55832 …h SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.
55833 …ster for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length ou…
55912 …D_REG_DBG_OUT_DATA_SIZE 8
55968 …h SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.
55969 …ster for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length ou…
56045 …_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
56046 …MLD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5_SHIFT 8
56113 …0_OFFSET_01_E5 (0xff<<8) // Offset in 32b un…
56114 …MLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5_SHIFT 8
56122 …1_OFFSET_11_E5 (0xff<<8) // Offset in 32b un…
56123 …MLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5_SHIFT 8
56131 …2_OFFSET_21_E5 (0xff<<8) // Offset in 32b un…
56132 …MLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5_SHIFT 8
56140 …3_OFFSET_31_E5 (0xff<<8) // Offset in 32b un…
56141 …MLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5_SHIFT 8
56151 …1_LEN_02_E5 (0xf<<8) // length in 32b un…
56152 …MLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5_SHIFT 8
56168 …3_LEN_22_E5 (0xf<<8) // length in 32b un…
56169 …MLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5_SHIFT 8
56215 …_DUP_OFFSET_01_E5 (0xff<<8) // Offset in 32b un…
56216 …MLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5_SHIFT 8
56224 …_DUP_OFFSET_11_E5 (0xff<<8) // Offset in 32b un…
56225 …MLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5_SHIFT 8
56233 …_DUP_OFFSET_21_E5 (0xff<<8) // Offset in 32b un…
56234 …MLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5_SHIFT 8
56242 …_DUP_OFFSET_31_E5 (0xff<<8) // Offset in 32b un…
56243 …MLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5_SHIFT 8
56304 …SET_1_E5 (0xff<<8) // offset in 32b un…
56305 …MLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5_SHIFT 8
56315 …MAX_L2MA_2_E5 (0xf<<8) // the maximal numb…
56316 …MLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5_SHIFT 8
56322 …D_INC_EVENT_ID_1_E5 (0xff<<8) // The value by whi…
56323 …MLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5_SHIFT 8
56341 …D_REG_DBG_OUT_DATA_SIZE 8
56353 …0x4 // Log 2 of the BD size in bytes - 2:BD size is 4bytes; 3:BD size is 8bytes; 4:BD size is 1…
56355 … // Log 2 of the SGE size in bytes - 2:SGE size is 4bytes; 3:SGE size is 8bytes; 4:SGE size is …
56359 …:0x3 // Number of slots at the PCI read response buffer: 3=4/8 slots of 512 bytes;4=8/16 slots …
56408 …h SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.
56409 …ster for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length ou…
56483 …_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
56484 …ULD_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_E5_SHIFT 8
56487 …_I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, …
56488 …ULD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT 8
56591 …0_OFFSET_01_E5 (0xff<<8) // Offset in 32b un…
56592 …ULD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5_SHIFT 8
56600 …1_OFFSET_11_E5 (0xff<<8) // Offset in 32b un…
56601 …ULD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5_SHIFT 8
56609 …2_OFFSET_21_E5 (0xff<<8) // Offset in 32b un…
56610 …ULD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5_SHIFT 8
56618 …3_OFFSET_31_E5 (0xff<<8) // Offset in 32b un…
56619 …ULD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5_SHIFT 8
56629 …1_LEN_02_E5 (0xf<<8) // length in 32b un…
56630 …ULD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5_SHIFT 8
56646 …3_LEN_22_E5 (0xf<<8) // length in 32b un…
56647 …ULD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5_SHIFT 8
56693 …_DUP_OFFSET_01_E5 (0xff<<8) // Offset in 32b un…
56694 …ULD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5_SHIFT 8
56702 …_DUP_OFFSET_11_E5 (0xff<<8) // Offset in 32b un…
56703 …ULD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5_SHIFT 8
56711 …_DUP_OFFSET_21_E5 (0xff<<8) // Offset in 32b un…
56712 …ULD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5_SHIFT 8
56720 …_DUP_OFFSET_31_E5 (0xff<<8) // Offset in 32b un…
56721 …ULD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5_SHIFT 8
56782 …SET_1_E5 (0xff<<8) // offset in 32b un…
56783 …ULD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5_SHIFT 8
56793 …MAX_L2MA_2_E5 (0xf<<8) // the maximal numb…
56794 …ULD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5_SHIFT 8
56800 …D_INC_EVENT_ID_1_E5 (0xff<<8) // The value by whi…
56801 …ULD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5_SHIFT 8
56814 …D_REG_DBG_OUT_DATA_SIZE 8
56846 …FO_ERROR_WR (0x1<<8) // FIFO error in TS…
56847 …IG_REG_INT_STS_0_TSDM_SYNCFIFO_ERROR_WR_SHIFT 8
56875 …IFO_ERROR_WR (0x1<<8) // This bit masks, …
56876 …IG_REG_INT_MASK_0_TSDM_SYNCFIFO_ERROR_WR_SHIFT 8
56904 …CFIFO_ERROR_WR (0x1<<8) // FIFO error in TS…
56905 …IG_REG_INT_STS_WR_0_TSDM_SYNCFIFO_ERROR_WR_SHIFT 8
56933 …NCFIFO_ERROR_WR (0x1<<8) // FIFO error in TS…
56934 …IG_REG_INT_STS_CLR_0_TSDM_SYNCFIFO_ERROR_WR_SHIFT 8
56962 …ROR (0x1<<8) // Error in the TX …
56963 …IG_REG_INT_STS_1_TX_SOPQ8_ERROR_SHIFT 8
57027 …RROR (0x1<<8) // This bit masks, …
57028 …IG_REG_INT_MASK_1_TX_SOPQ8_ERROR_SHIFT 8
57092 …_ERROR (0x1<<8) // Error in the TX …
57093 …IG_REG_INT_STS_WR_1_TX_SOPQ8_ERROR_SHIFT 8
57157 …8_ERROR (0x1<<8) // Error in the TX …
57158 …IG_REG_INT_STS_CLR_1_TX_SOPQ8_ERROR_SHIFT 8
57222 …FIFO_ERROR (0x1<<8) // Error in LLH Dat…
57223 …IG_REG_INT_STS_2_P0_TX_LLH_DFIFO_ERROR_SHIFT 8
57267 …DFIFO_ERROR (0x1<<8) // This bit masks, …
57268 …IG_REG_INT_MASK_2_P0_TX_LLH_DFIFO_ERROR_SHIFT 8
57312 …H_DFIFO_ERROR (0x1<<8) // Error in LLH Dat…
57313 …IG_REG_INT_STS_WR_2_P0_TX_LLH_DFIFO_ERROR_SHIFT 8
57357 …LH_DFIFO_ERROR (0x1<<8) // Error in LLH Dat…
57358 …IG_REG_INT_STS_CLR_2_P0_TX_LLH_DFIFO_ERROR_SHIFT 8
57402 …E_TOO_LONG_INT (0x1<<8) // Triggered by TC …
57403 …IG_REG_INT_STS_3_P0_TC7_PAUSE_TOO_LONG_INT_SHIFT 8
57439 …SE_TOO_LONG_INT (0x1<<8) // This bit masks, …
57440 …IG_REG_INT_MASK_3_P0_TC7_PAUSE_TOO_LONG_INT_SHIFT 8
57476 …AUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC …
57477 …IG_REG_INT_STS_WR_3_P0_TC7_PAUSE_TOO_LONG_INT_SHIFT 8
57513 …PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC …
57514 …IG_REG_INT_STS_CLR_3_P0_TC7_PAUSE_TOO_LONG_INT_SHIFT 8
57550 …FIFO_ERROR (0x1<<8) // Error in LLH Dat…
57551 …IG_REG_INT_STS_4_P1_TX_LLH_DFIFO_ERROR_SHIFT 8
57595 …DFIFO_ERROR (0x1<<8) // This bit masks, …
57596 …IG_REG_INT_MASK_4_P1_TX_LLH_DFIFO_ERROR_SHIFT 8
57640 …H_DFIFO_ERROR (0x1<<8) // Error in LLH Dat…
57641 …IG_REG_INT_STS_WR_4_P1_TX_LLH_DFIFO_ERROR_SHIFT 8
57685 …LH_DFIFO_ERROR (0x1<<8) // Error in LLH Dat…
57686 …IG_REG_INT_STS_CLR_4_P1_TX_LLH_DFIFO_ERROR_SHIFT 8
57730 …E_TOO_LONG_INT (0x1<<8) // Triggered by TC …
57731 …IG_REG_INT_STS_5_P1_TC7_PAUSE_TOO_LONG_INT_SHIFT 8
57767 …SE_TOO_LONG_INT (0x1<<8) // This bit masks, …
57768 …IG_REG_INT_MASK_5_P1_TC7_PAUSE_TOO_LONG_INT_SHIFT 8
57804 …AUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC …
57805 …IG_REG_INT_STS_WR_5_P1_TC7_PAUSE_TOO_LONG_INT_SHIFT 8
57841 …PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC …
57842 …IG_REG_INT_STS_CLR_5_P1_TC7_PAUSE_TOO_LONG_INT_SHIFT 8
57878 …FIFO_ERROR_K2_E5 (0x1<<8) // Error in LLH Dat…
57879 …IG_REG_INT_STS_6_P2_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT 8
57923 …DFIFO_ERROR_K2_E5 (0x1<<8) // This bit masks, …
57924 …IG_REG_INT_MASK_6_P2_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT 8
57968 …H_DFIFO_ERROR_K2_E5 (0x1<<8) // Error in LLH Dat…
57969 …IG_REG_INT_STS_WR_6_P2_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT 8
58013 …LH_DFIFO_ERROR_K2_E5 (0x1<<8) // Error in LLH Dat…
58014 …IG_REG_INT_STS_CLR_6_P2_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT 8
58058 …E_TOO_LONG_INT_K2_E5 (0x1<<8) // Triggered by TC …
58059 …IG_REG_INT_STS_7_P2_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 8
58095 …SE_TOO_LONG_INT_K2_E5 (0x1<<8) // This bit masks, …
58096 …IG_REG_INT_MASK_7_P2_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 8
58132 …AUSE_TOO_LONG_INT_K2_E5 (0x1<<8) // Triggered by TC …
58133 …IG_REG_INT_STS_WR_7_P2_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 8
58169 …PAUSE_TOO_LONG_INT_K2_E5 (0x1<<8) // Triggered by TC …
58170 …IG_REG_INT_STS_CLR_7_P2_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 8
58206 …FIFO_ERROR_K2_E5 (0x1<<8) // Error in LLH Dat…
58207 …IG_REG_INT_STS_8_P3_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT 8
58251 …DFIFO_ERROR_K2_E5 (0x1<<8) // This bit masks, …
58252 …IG_REG_INT_MASK_8_P3_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT 8
58296 …H_DFIFO_ERROR_K2_E5 (0x1<<8) // Error in LLH Dat…
58297 …IG_REG_INT_STS_WR_8_P3_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT 8
58341 …LH_DFIFO_ERROR_K2_E5 (0x1<<8) // Error in LLH Dat…
58342 …IG_REG_INT_STS_CLR_8_P3_TX_LLH_DFIFO_ERROR_K2_E5_SHIFT 8
58386 …E_TOO_LONG_INT_K2_E5 (0x1<<8) // Triggered by TC …
58387 …IG_REG_INT_STS_9_P3_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 8
58423 …SE_TOO_LONG_INT_K2_E5 (0x1<<8) // This bit masks, …
58424 …IG_REG_INT_MASK_9_P3_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 8
58460 …AUSE_TOO_LONG_INT_K2_E5 (0x1<<8) // Triggered by TC …
58461 …IG_REG_INT_STS_WR_9_P3_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 8
58497 …PAUSE_TOO_LONG_INT_K2_E5 (0x1<<8) // Triggered by TC …
58498 …IG_REG_INT_STS_CLR_9_P3_TC7_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 8
58538 …ERROR_E5 (0x1<<8) // Error in the LB …
58539 …IG_REG_INT_STS_10_LB_SOPQ16_ERROR_E5_SHIFT 8
58571 …_ERROR_E5 (0x1<<8) // This bit masks, …
58572 …IG_REG_INT_MASK_10_LB_SOPQ16_ERROR_E5_SHIFT 8
58604 …16_ERROR_E5 (0x1<<8) // Error in the LB …
58605 …IG_REG_INT_STS_WR_10_LB_SOPQ16_ERROR_E5_SHIFT 8
58637 …Q16_ERROR_E5 (0x1<<8) // Error in the LB …
58638 …IG_REG_INT_STS_CLR_10_LB_SOPQ16_ERROR_E5_SHIFT 8
58674 …I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
58675 …IG_REG_PRTY_MASK_H_0_MEM090_I_MEM_PRTY_E5_SHIFT 8
58782 …I_MEM_PRTY_K2 (0x1<<8) // This bit masks, …
58783 …IG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_K2_SHIFT 8
58804 …I_MEM_PRTY_BB (0x1<<8) // This bit masks, …
58805 …IG_REG_PRTY_MASK_H_0_MEM109_I_MEM_PRTY_BB_SHIFT 8
58871 …I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
58872 …IG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_E5_SHIFT 8
58897 …I_MEM_PRTY_K2 (0x1<<8) // This bit masks, …
58898 …IG_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_K2_SHIFT 8
58991 …I_MEM_PRTY_BB (0x1<<8) // This bit masks, …
58992 …IG_REG_PRTY_MASK_H_1_MEM077_I_MEM_PRTY_BB_SHIFT 8
59060 …I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
59061 …IG_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_E5_SHIFT 8
59116 …I_MEM_PRTY_K2 (0x1<<8) // This bit masks, …
59117 …IG_REG_PRTY_MASK_H_2_MEM020_I_MEM_PRTY_K2_SHIFT 8
59198 …I_MEM_PRTY_BB (0x1<<8) // This bit masks, …
59199 …IG_REG_PRTY_MASK_H_2_MEM048_I_MEM_PRTY_BB_SHIFT 8
59239 …I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
59240 …IG_REG_PRTY_MASK_H_3_MEM006_I_MEM_PRTY_E5_SHIFT 8
59289 …I_MEM_PRTY_K2 (0x1<<8) // This bit masks, …
59290 …IG_REG_PRTY_MASK_H_3_MEM081_I_MEM_PRTY_K2_SHIFT 8
59305 …I_MEM_PRTY_BB (0x1<<8) // This bit masks, …
59306 …IG_REG_PRTY_MASK_H_3_MEM040_I_MEM_PRTY_BB_SHIFT 8
59343 … (0x1<<8) // T-bit to be used…
59344 …IG_REG_CM_HDR_T_BIT_SHIFT 8
59677 …MAC3 (0x1<<8) // Mask bit for for…
59678 …IG_REG_RX_LLH_NCSI_MCP_MASK_MAC3_SHIFT 8
59754 … (0x1<<3) // Mask bit for forwarding ICMPv4 packets with ICMP type 8 to MCP.
59779 …D_MASK_MAC3 (0x1<<8) // Mask bit for not…
59780 …IG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC3_SHIFT 8
59856 … (0x1<<3) // Mask bit for not forwarding ICMPv4 packets with ICMP type 8 to the host.
60232 … 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6-TC5 traffic; 7-TC6 traffic; 8-TC7 traffic; 9-TC8 t…
60233 … 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6-TC5 traffic; 7-TC6 traffic; 8-TC7 traffic; 9-TC8 t…
60235 … 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6-TC5 traffic; 7-TC6 traffic; 8-TC7 traffic; 9-TC8 t…
60248 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 8 is allowed to reach.
60258 …idth:0x20 // Specify the weight (in bytes) to be added to credit register 8 when it is time to i…
60268 …R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter credit register 8.
60297 …1 of 320. 6-MAC Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 0x01-1B-…
60298 …IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype…
60299 …1 of 320. 6-MAC Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 0x01-1B-…
60300 …IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype…
60317 … translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions …
60318 … translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions …
60319 … translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions …
60320 … translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions …
60321 … translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions …
60322 … translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions …
60323 … translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions …
60324 … translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions …
60327 …1:8 of the outer tag value[15:0]. Bits [23:18] of this register specify the index for bit 11. Bi…
60396 … bits to enable the drain mode for TC0 and TC7. Bit 0 is for TC0 flow. Bit 8 is for TC8 flow. Wh…
60589 …rom other port; 4-TC0 traffic; 5-TC1 traffic; 6-TC2 traffic; 7-TC3 traffic; 8-TC4 traffic; 9-TC5 t…
60590 …rom other port; 4-TC0 traffic; 5-TC1 traffic; 6-TC2 traffic; 7-TC3 traffic; 8-TC4 traffic; 9-TC5 t…
60592 …rom other port; 4-TC0 traffic; 5-TC1 traffic; 6-TC2 traffic; 7-TC3 traffic; 8-TC4 traffic; 9-TC5 t…
60606 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 8 is allowed to reach.
60618 …idth:0x20 // Specify the weight (in bytes) to be added to credit register 8 when it is time to i…
60630 …R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter credit register 8.
60651 …MAC3 (0x1<<8) // Mask bit for for…
60652 …IG_REG_TX_LLH_NCSI_MCP_MASK_MAC3_SHIFT 8
60727 …WD_MASK_MAC3 (0x1<<8) // Mask bit for not…
60728 …IG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC3_SHIFT 8
60792 …_MAC3 (0x1<<8) // Mask bit for for…
60793 …IG_REG_TX_LLH_NCSI_NTWK_MASK_MAC3_SHIFT 8
60918 …_REG_DBG_OUT_DATA_SIZE 8
60957 … DataWidth:0x100 // This is a per-port per-PF register. Byte enable memory for 8 ACPI patterns.
60994 …_REG_WAKE_BUFFER_SIZE 8
60996 …8 functions. Bit 17 - MPKT: This bit is set when a Magic packet is received. This is an OR of the…
60998 …CPI MATCH: Per-function bit-mapped result from ACPI pattern match. Bits 15:8 - MPKT MATCH: Per-…
61049 …TSGEN_OFFSET_T0 register. The drift frequency has a constant added shift of 8 nsec. Bits 30:28 spe…
61058 …_REG_PPF_TO_ENGINE_SEL_SIZE 8
61163 … reisters. This enables credit sharing with one of the BTB TCs. 0: MNG. 1-8: BTB per TC. 9: BT…
61399 …INT_FIFO_ERROR (0x1<<8) // Free ointer FIFO…
61400 …MB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT 8
61456 …OINT_FIFO_ERROR (0x1<<8) // This bit masks, …
61457 …MB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT 8
61513 …_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO…
61514 …MB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT 8
61570 …E_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO…
61571 …MB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT 8
61631 …IL_FIFO_ERROR (0x1<<8) // Warning! Check t…
61632 …MB_REG_INT_STS_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT 8
61684 …AIL_FIFO_ERROR (0x1<<8) // This bit masks, …
61685 …MB_REG_INT_MASK_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT 8
61737 …AVAIL_FIFO_ERROR (0x1<<8) // Warning! Check t…
61738 …MB_REG_INT_STS_WR_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT 8
61790 …_AVAIL_FIFO_ERROR (0x1<<8) // Warning! Check t…
61791 …MB_REG_INT_STS_CLR_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT 8
61843 …R_FIFO_ERROR (0x1<<8) // Read packet clie…
61844 …MB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT 8
61906 …CR_FIFO_ERROR (0x1<<8) // This bit masks, …
61907 …MB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT 8
61969 …DSCR_FIFO_ERROR (0x1<<8) // Read packet clie…
61970 …MB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT 8
62032 …_DSCR_FIFO_ERROR (0x1<<8) // Read packet clie…
62033 …MB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT 8
62093 …ETCH_FIFO_ERROR (0x1<<8) // Link list arbite…
62094 …MB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT 8
62148 …FETCH_FIFO_ERROR (0x1<<8) // This bit masks, …
62149 …MB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT 8
62203 …REFETCH_FIFO_ERROR (0x1<<8) // Link list arbite…
62204 …MB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT 8
62258 …PREFETCH_FIFO_ERROR (0x1<<8) // Link list arbite…
62259 …MB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT 8
62315 …OND_PTR_FIFO_ERROR (0x1<<8) // Read packet clie…
62316 …MB_REG_INT_STS_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT 8
62374 …COND_PTR_FIFO_ERROR (0x1<<8) // This bit masks, …
62375 …MB_REG_INT_MASK_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT 8
62433 …SECOND_PTR_FIFO_ERROR (0x1<<8) // Read packet clie…
62434 …MB_REG_INT_STS_WR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT 8
62492 …_SECOND_PTR_FIFO_ERROR (0x1<<8) // Read packet clie…
62493 …MB_REG_INT_STS_CLR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT 8
62551 …T_PTR_FIFO_ERROR (0x1<<8) // Read packet clie…
62552 …MB_REG_INT_STS_6_RC_PKT8_STRT_PTR_FIFO_ERROR_SHIFT 8
62587 …ction for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 8
62612 …RT_PTR_FIFO_ERROR (0x1<<8) // This bit masks, …
62613 …MB_REG_INT_MASK_6_RC_PKT8_STRT_PTR_FIFO_ERROR_SHIFT 8
62673 …STRT_PTR_FIFO_ERROR (0x1<<8) // Read packet clie…
62674 …MB_REG_INT_STS_WR_6_RC_PKT8_STRT_PTR_FIFO_ERROR_SHIFT 8
62709 …ction for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 8
62734 …_STRT_PTR_FIFO_ERROR (0x1<<8) // Read packet clie…
62735 …MB_REG_INT_STS_CLR_6_RC_PKT8_STRT_PTR_FIFO_ERROR_SHIFT 8
62770 …ction for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 8
62797 …NT_ERROR (0x1<<8) // Warning! Check t…
62798 …MB_REG_INT_STS_7_WC4_LL_PA_CNT_ERROR_SHIFT 8
62862 …CNT_ERROR (0x1<<8) // This bit masks, …
62863 …MB_REG_INT_MASK_7_WC4_LL_PA_CNT_ERROR_SHIFT 8
62927 …A_CNT_ERROR (0x1<<8) // Warning! Check t…
62928 …MB_REG_INT_STS_WR_7_WC4_LL_PA_CNT_ERROR_SHIFT 8
62992 …PA_CNT_ERROR (0x1<<8) // Warning! Check t…
62993 …MB_REG_INT_STS_CLR_7_WC4_LL_PA_CNT_ERROR_SHIFT 8
63057 …INT_FIFO_ERROR (0x1<<8) // Warning! Check t…
63058 …MB_REG_INT_STS_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT 8
63075 …0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 8
63077 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 8
63079 …0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 8
63081 …0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 8
63083 …) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 8
63085 …0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 8
63087 …Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 8
63089 … Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 8
63091 …5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 8
63093 …x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 8
63095 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 8
63097 … in RTL. Packet available counter overflow or underflow for requests to link list in write client 8
63099 …available counter overflow or underflow for requests to big ram of SOP descriptor in write client 8
63122 …OINT_FIFO_ERROR (0x1<<8) // This bit masks, …
63123 …MB_REG_INT_MASK_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT 8
63187 …_POINT_FIFO_ERROR (0x1<<8) // Warning! Check t…
63188 …MB_REG_INT_STS_WR_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT 8
63205 …0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 8
63207 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 8
63209 …0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 8
63211 …0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 8
63213 …) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 8
63215 …0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 8
63217 …Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 8
63219 … Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 8
63221 …5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 8
63223 …x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 8
63225 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 8
63227 … in RTL. Packet available counter overflow or underflow for requests to link list in write client 8
63229 …available counter overflow or underflow for requests to big ram of SOP descriptor in write client 8
63252 …T_POINT_FIFO_ERROR (0x1<<8) // Warning! Check t…
63253 …MB_REG_INT_STS_CLR_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT 8
63270 …0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 8
63272 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 8
63274 …0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 8
63276 …0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 8
63278 …) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 8
63280 …0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 8
63282 …Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 8
63284 … Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 8
63286 …5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 8
63288 …x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 8
63290 … (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 8
63292 … in RTL. Packet available counter overflow or underflow for requests to link list in write client 8
63294 …available counter overflow or underflow for requests to big ram of SOP descriptor in write client 8
63317 …FIFO_ERROR (0x1<<8) // Warning! Check t…
63318 …MB_REG_INT_STS_9_WC9_LL_REQ_FIFO_ERROR_SHIFT 8
63392 …_FIFO_ERROR (0x1<<8) // This bit masks, …
63393 …MB_REG_INT_MASK_9_WC9_LL_REQ_FIFO_ERROR_SHIFT 8
63467 …EQ_FIFO_ERROR (0x1<<8) // Warning! Check t…
63468 …MB_REG_INT_STS_WR_9_WC9_LL_REQ_FIFO_ERROR_SHIFT 8
63542 …REQ_FIFO_ERROR (0x1<<8) // Warning! Check t…
63543 …MB_REG_INT_STS_CLR_9_WC9_LL_REQ_FIFO_ERROR_SHIFT 8
63716 …I_ECC_RF_INT (0x1<<8) // This bit masks, …
63717 …MB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_SHIFT 8
63813 …I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
63814 …MB_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_E5_SHIFT 8
63863 …I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, …
63864 …MB_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB_K2_SHIFT 8
63877 …erate up to two ECC errors on the next write to memory: bmb.BB_BANK_GEN_FOR[8].i_bb_bank.rf_ecc_er…
63902 … (0x1<<8) // Enable ECC for memory ecc instance bmb.BB_BANK_…
63903 …MB_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_SHIFT 8
63935 … (0x1<<8) // Set parity only for memory ecc instance bmb.BB_BA…
63936 …MB_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_SHIFT 8
63968 … (0x1<<8) // Record if a correctable error occurred on memory ecc instanc…
63969 …MB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_SHIFT 8
64043 …RI (0x3<<8) // This is priority…
64044 …MB_REG_RC_PKT_PRIORITY_RC4_PRI_SHIFT 8
64051 … (0x3<<16) // This is priority for read client 8 that is used in link…
64067 …ient upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.
64085 …_REG_DBG_OUT_DATA_SIZE 8
64106 …ifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
64107 …ifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
64108 …ifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
64109 …ifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
64110 …ifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
64111 …ifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
64112 …ifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
64113 …ifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
64114 …ifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
64115 …ifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG…
64128 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
64129 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
64130 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
64131 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
64132 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
64133 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
64134 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
64135 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
64136 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
64137 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
64138 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
64139 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
64140 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
64141 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
64142 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
64143 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
64144 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
64145 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
64146 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
64147 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
64148 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
64149 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
64150 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
64151 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
64152 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
64153 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
64154 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
64155 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
64156 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
64157 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
64160 …th:0x10 // Debug register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr…
64213 …ess:R DataWidth:0x1 // Debug register. This is empty status of SOP SYNC INP FIFO for client 8
64221 …ess:R DataWidth:0x1 // Debug register. This is empty status of SOP SYNC out FIFO for client 8
64239 …Access:R DataWidth:0x8 // Debug register. This is state machine for each read client 8 and 9.
64260 …t_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; …
64262 …t_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; …
64264 …t_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; …
64266 …t_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; …
64268 …t_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; …
64270 …t_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; …
64272 …t_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; …
64274 …t_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; …
64276 …t_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; …
64278 …t_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; …
64294 …h:0xc // TPH fileds of the PXP read requests issued by the PTU logic. [0:8] - ST index; [10:9] …
64333 …_REG_DBG_OUT_DATA_SIZE 8
64433 …I_MEM_PRTY (0x1<<8) // This bit masks, …
64434 …TU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT 8
64641 …13]}; W0 - {par - [12]; NS bit - [11]; W bit - [10]; R bit - [9]; U bit - [8]; Priority bit - [7]…
64651 …[12]}; W1 - { Priority bit - [11]; PLRU - [10]; Err bit - [9]; invpend bit [8]; transpend bit - [7…
64685 …7) // Byte valid Error on PXP Interface. All transactions should be either 8 or 16 bytes, so pxp_…
64702 …7) // Byte valid Error on PXP Interface. All transactions should be either 8 or 16 bytes, so pxp_…
64719 …7) // Byte valid Error on PXP Interface. All transactions should be either 8 or 16 bytes, so pxp_…
64757 …EN1_CCFC (0xff<<8) // CCFC Conxtext Va…
64758 …DU_REG_CCFC_CTX_VALID0_CHECK_EN1_CCFC_SHIFT 8
64766 …EN5_CCFC (0xff<<8) // CCFC Conxtext Va…
64767 …DU_REG_CCFC_CTX_VALID1_CHECK_EN5_CCFC_SHIFT 8
64775 …EN1_TCFC (0xff<<8) // TCFC Conxtext Va…
64776 …DU_REG_TCFC_CTX_VALID0_CHECK_EN1_TCFC_SHIFT 8
64784 …EN5_TCFC (0xff<<8) // TCFC Conxtext Va…
64785 …DU_REG_TCFC_CTX_VALID1_CHECK_EN5_TCFC_SHIFT 8
64790 …ontrols the Full signal to PXP. This register must never be set higher than 8 -- doing so will res…
64855 …_REG_DBG_OUT_DATA_SIZE 8
64863 …/ CCFC Context Validation Error Data. [24:16] LCID of Error Transaction [14:8] Expected Compresse…
64864 …/ TCFC Context Validation Error Data. [24:16] LCID of Error Transaction [14:8] Expected Compresse…
64865 … // Logging of error data in case of a CCFC Load error. [24:16] LCID [11:8] Type [7:0] Reg…
64866 … // Logging of error data in case of a TCFC Load error. [24:16] LCID [11:8] Type [7:0] Reg…
64867 … Logging of error data in case of a CCFC Writeback Error. [24:16] LCID [11:8] Type [7:0] Reg…
64868 … Logging of error data in case of a TCFC Writeback Error. [24:16] LCID [11:8] Type [7:0] Reg…
64936 …h SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.
64937 …ster for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length ou…
65041 …0_OFFSET_01_E5 (0xff<<8) // Offset in 32b un…
65042 …TLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5_SHIFT 8
65050 …1_OFFSET_11_E5 (0xff<<8) // Offset in 32b un…
65051 …TLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5_SHIFT 8
65059 …2_OFFSET_21_E5 (0xff<<8) // Offset in 32b un…
65060 …TLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5_SHIFT 8
65068 …3_OFFSET_31_E5 (0xff<<8) // Offset in 32b un…
65069 …TLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5_SHIFT 8
65079 …1_LEN_02_E5 (0xf<<8) // length in 32b un…
65080 …TLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5_SHIFT 8
65096 …3_LEN_22_E5 (0xf<<8) // length in 32b un…
65097 …TLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5_SHIFT 8
65143 …_DUP_OFFSET_01_E5 (0xff<<8) // Offset in 32b un…
65144 …TLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5_SHIFT 8
65152 …_DUP_OFFSET_11_E5 (0xff<<8) // Offset in 32b un…
65153 …TLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5_SHIFT 8
65161 …_DUP_OFFSET_21_E5 (0xff<<8) // Offset in 32b un…
65162 …TLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5_SHIFT 8
65170 …_DUP_OFFSET_31_E5 (0xff<<8) // Offset in 32b un…
65171 …TLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5_SHIFT 8
65232 …SET_1_E5 (0xff<<8) // offset in 32b un…
65233 …TLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5_SHIFT 8
65243 …MAX_L2MA_2_E5 (0xf<<8) // the maximal numb…
65244 …TLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5_SHIFT 8
65250 …D_INC_EVENT_ID_1_E5 (0xff<<8) // The value by whi…
65251 …TLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5_SHIFT 8
65263 …D_REG_DBG_OUT_DATA_SIZE 8
65288 …h SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.
65289 …ster for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length ou…
65393 …0_OFFSET_01_E5 (0xff<<8) // Offset in 32b un…
65394 …PLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5_SHIFT 8
65402 …1_OFFSET_11_E5 (0xff<<8) // Offset in 32b un…
65403 …PLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5_SHIFT 8
65411 …2_OFFSET_21_E5 (0xff<<8) // Offset in 32b un…
65412 …PLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5_SHIFT 8
65420 …3_OFFSET_31_E5 (0xff<<8) // Offset in 32b un…
65421 …PLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5_SHIFT 8
65431 …1_LEN_02_E5 (0xf<<8) // length in 32b un…
65432 …PLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_02_E5_SHIFT 8
65448 …3_LEN_22_E5 (0xf<<8) // length in 32b un…
65449 …PLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_22_E5_SHIFT 8
65495 …_DUP_OFFSET_01_E5 (0xff<<8) // Offset in 32b un…
65496 …PLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5_SHIFT 8
65504 …_DUP_OFFSET_11_E5 (0xff<<8) // Offset in 32b un…
65505 …PLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5_SHIFT 8
65513 …_DUP_OFFSET_21_E5 (0xff<<8) // Offset in 32b un…
65514 …PLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5_SHIFT 8
65522 …_DUP_OFFSET_31_E5 (0xff<<8) // Offset in 32b un…
65523 …PLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5_SHIFT 8
65584 …SET_1_E5 (0xff<<8) // offset in 32b un…
65585 …PLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5_SHIFT 8
65595 …MAX_L2MA_2_E5 (0xf<<8) // the maximal numb…
65596 …PLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5_SHIFT 8
65602 …D_INC_EVENT_ID_1_E5 (0xff<<8) // The value by whi…
65603 …PLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5_SHIFT 8
65615 …D_REG_DBG_OUT_DATA_SIZE 8
65640 …_REG_DBG_OUT_DATA_SIZE 8
65660 …I_MEM_PRTY_K2_E5 (0x1<<8) // This bit masks, …
65661 …OL_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_E5_SHIFT 8
65695 … DataWidth:0x100 // This is a per-port per-PF register. Byte enable memory for 8 ACPI patterns.
65719 …_REG_WAKE_BUFFER_SIZE 8
65721 …8 functions. Bit 17 - MPKT: This bit is set when a Magic packet is received. This is an OR of the…
65723 …CPI MATCH: Per-function bit-mapped result from ACPI pattern match. Bits 15:8 - MPKT MATCH: Per-…
65757 …N_REG_DBG_OUT_DATA_SIZE 8
65823 …L_CMU_RESETN_I_K2_E5 (0x1<<8) // Firmware must se…
65824 …HY_PCIE_REG_PHY_RESET_CONTROL_CMU_RESETN_I_K2_E5_SHIFT 8
65840 …PCS_CONTROL_2_LNX_RXEII_EXIT_TYPE_I_K2_E5 (0xff<<8) //
65841 …HY_PCIE_REG_PCS_CONTROL_2_LNX_RXEII_EXIT_TYPE_I_K2_E5_SHIFT 8
65873 …_PCIE_REG_DBG_OUT_DATA_SIZE 8
65896 …DQ_I_K2_E5 (0x1<<8) // Turn off CMU mas…
65897 …S_REG_COMMON_CONTROL_CMU1_IDDQ_I_K2_E5_SHIFT 8
65938 …LK_OE_R_I_K2_E5 (0x1<<8) // Output enables f…
65939 …S_REG_CLOCK_SELECT_CMU1_REFCLK_OE_R_I_K2_E5_SHIFT 8
65954 …REG_DBG_OUT_DATA_SIZE 8
66031 …_K2_E5 (0x1<<8) // If set along wit…
66032 …ED_REG_CONTROL_BLINK_TRAFFIC_K2_E5_SHIFT 8
66039 … 1-2 -> PHY1; 3 -> PHY3; 4 -> MAC2; 5-6 -> PHY4; 7 -> PHY6; 8 -> MAC3; 9 -…
66049 … (0x3<<8) // These bits makes…
66050 …ED_REG_MAC_LED_SWAP_P2_K2_E5_SHIFT 8
66180 …_PD_READY_O_K2 (0x1<<8) // 0x0 - PHY is not…
66181 …WS_REG_COMMON_STATUS_LN3_RST_PD_READY_O_K2_SHIFT 8
66196 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) …
66204 …A_RATE_I_K2 (0x3<<8) // 0x0 - Select Rat…
66205 …WS_REG_LN0_CNTL_LN0_CTRL_DATA_RATE_I_K2_SHIFT 8
66258 …0_LINK_STATUS_1G_KX_I_K2 (0x1<<8) // Set to 1 if the …
66259 …WS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_1G_KX_I_K2_SHIFT 8
66276 …N0_LINK_CNTL_25G_CR_O_K2 (0x3<<8) // 0x0 - Link is of…
66277 …WS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_CR_O_K2_SHIFT 8
66314 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) …
66322 …A_RATE_I_K2 (0x3<<8) // 0x0 - Select Rat…
66323 …WS_REG_LN1_CNTL_LN1_CTRL_DATA_RATE_I_K2_SHIFT 8
66372 …1_LINK_STATUS_1G_KX_I_K2 (0x1<<8) // Set to 1 if the …
66373 …WS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_1G_KX_I_K2_SHIFT 8
66394 …N1_LINK_CNTL_25G_CR_O_K2 (0x3<<8) // 0x0 - Link is of…
66395 …WS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_CR_O_K2_SHIFT 8
66432 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) …
66440 …A_RATE_I_K2 (0x3<<8) // 0x0 - Select Rat…
66441 …WS_REG_LN2_CNTL_LN2_CTRL_DATA_RATE_I_K2_SHIFT 8
66490 …2_LINK_STATUS_1G_KX_I_K2 (0x1<<8) // Set to 1 if the …
66491 …WS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_1G_KX_I_K2_SHIFT 8
66508 …N2_LINK_CNTL_25G_CR_O_K2 (0x3<<8) // 0x0 - Link is of…
66509 …WS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_CR_O_K2_SHIFT 8
66546 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) …
66554 …A_RATE_I_K2 (0x3<<8) // 0x0 - Select Rat…
66555 …WS_REG_LN3_CNTL_LN3_CTRL_DATA_RATE_I_K2_SHIFT 8
66608 …3_LINK_STATUS_1G_KX_I_K2 (0x1<<8) // Set to 1 if the …
66609 …WS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_1G_KX_I_K2_SHIFT 8
66626 …N3_LINK_CNTL_25G_CR_O_K2 (0x3<<8) // 0x0 - Link is of…
66627 …WS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_CR_O_K2_SHIFT 8
66757 …ollows: Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6.…
66781 …ollows: Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6.…
66805 …ollows: Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6.…
66829 …ollows: Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6.…
66873 …_REG_DBG_OUT_DATA_SIZE 8
66904 …LVE_10G_KR_K2 (0x1<<8) // Autonegotiation …
66905 …WS_REG_INT_STS_0_LN0_AN_RESOLVE_10G_KR_K2_SHIFT 8
66925 …OLVE_10G_KR_K2 (0x1<<8) // This bit masks, …
66926 …WS_REG_INT_MASK_0_LN0_AN_RESOLVE_10G_KR_K2_SHIFT 8
66946 …ESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation …
66947 …WS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_10G_KR_K2_SHIFT 8
66967 …RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation …
66968 …WS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_10G_KR_K2_SHIFT 8
66986 …LVE_10G_KR_K2 (0x1<<8) // Autonegotiation …
66987 …WS_REG_INT_STS_1_LN1_AN_RESOLVE_10G_KR_K2_SHIFT 8
67005 …OLVE_10G_KR_K2 (0x1<<8) // This bit masks, …
67006 …WS_REG_INT_MASK_1_LN1_AN_RESOLVE_10G_KR_K2_SHIFT 8
67024 …ESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation …
67025 …WS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_10G_KR_K2_SHIFT 8
67043 …RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation …
67044 …WS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_10G_KR_K2_SHIFT 8
67062 …LVE_10G_KR_K2 (0x1<<8) // Autonegotiation …
67063 …WS_REG_INT_STS_2_LN2_AN_RESOLVE_10G_KR_K2_SHIFT 8
67081 …OLVE_10G_KR_K2 (0x1<<8) // This bit masks, …
67082 …WS_REG_INT_MASK_2_LN2_AN_RESOLVE_10G_KR_K2_SHIFT 8
67100 …ESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation …
67101 …WS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_10G_KR_K2_SHIFT 8
67119 …RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation …
67120 …WS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_10G_KR_K2_SHIFT 8
67138 …LVE_10G_KR_K2 (0x1<<8) // Autonegotiation …
67139 …WS_REG_INT_STS_3_LN3_AN_RESOLVE_10G_KR_K2_SHIFT 8
67157 …OLVE_10G_KR_K2 (0x1<<8) // This bit masks, …
67158 …WS_REG_INT_MASK_3_LN3_AN_RESOLVE_10G_KR_K2_SHIFT 8
67176 …ESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation …
67177 …WS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_10G_KR_K2_SHIFT 8
67195 …RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation …
67196 …WS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_10G_KR_K2_SHIFT 8
67215 …15:8] = ram address [2] bits[7:0] = ram address [3] register 0 = ram location [3:0] register 1 …
67217 …15:8] = ram address [2] bits[7:0] = ram address [3] register 0 = ram location [3:0] register 1 …
67236 …3_K2_E5 (0x1<<8) // TX fifo underflow
67237 …WM_REG_INT_STS_TX_UNDERFLOW_3_K2_E5_SHIFT 8
67271 …_3_K2_E5 (0x1<<8) // This bit masks, …
67272 …WM_REG_INT_MASK_TX_UNDERFLOW_3_K2_E5_SHIFT 8
67306 …OW_3_K2_E5 (0x1<<8) // TX fifo underflow
67307 …WM_REG_INT_STS_WR_TX_UNDERFLOW_3_K2_E5_SHIFT 8
67341 …LOW_3_K2_E5 (0x1<<8) // TX fifo underflow
67342 …WM_REG_INT_STS_CLR_TX_UNDERFLOW_3_K2_E5_SHIFT 8
67364 …ocal Fault indicator has transitioned from Low to High since last read. bit 8 - REMOTE_FAULT_LH Re…
67370 …_LINK_INTERRUPT_K2_E5 (0x1<<8) // Live Link Interr…
67371 …WM_REG_LN0_LIVE_STS_LN0_LIVE_LINK_INTERRUPT_K2_E5_SHIFT 8
67380 …ocal Fault indicator has transitioned from Low to High since last read. bit 8 - REMOTE_FAULT_LH Re…
67386 …_LINK_INTERRUPT_K2_E5 (0x1<<8) // Live Link Interr…
67387 …WM_REG_LN1_LIVE_STS_LN1_LIVE_LINK_INTERRUPT_K2_E5_SHIFT 8
67396 …ocal Fault indicator has transitioned from Low to High since last read. bit 8 - REMOTE_FAULT_LH Re…
67402 …_LINK_INTERRUPT_K2_E5 (0x1<<8) // Live Link Interr…
67403 …WM_REG_LN2_LIVE_STS_LN2_LIVE_LINK_INTERRUPT_K2_E5_SHIFT 8
67412 …ocal Fault indicator has transitioned from Low to High since last read. bit 8 - REMOTE_FAULT_LH Re…
67418 …_LINK_INTERRUPT_K2_E5 (0x1<<8) // Live Link Interr…
67419 …WM_REG_LN3_LIVE_STS_LN3_LIVE_LINK_INTERRUPT_K2_E5_SHIFT 8
67459 …S_FEC_ERR_ENA_K2_E5 (0xf<<8) // Set to '1' for a…
67460 …WM_REG_FC_FEC_CONTROL_SIGNALS_FEC_ERR_ENA_K2_E5_SHIFT 8
67556 …E5 (0xf<<8) // High Bit Error R…
67557 …WM_REG_PCS_STATUS_HI_BER_K2_E5_SHIFT 8
67565 …ULT_K2_E5 (0xf<<8) // Asserted when th…
67566 …WM_REG_RX_FAULT_RX_REMOTE_FAULT_K2_E5_SHIFT 8
67584 …AULT_K2_E5 (0x1<<8) // Instructs the XL…
67585 …WM_REG_TX_FAULT_MAC2_TX_LI_FAULT_K2_E5_SHIFT 8
67623 …_REG_DBG_OUT_DATA_SIZE 8
67643 …I_MEM_PRTY_K2_E5 (0x1<<8) // This bit masks, …
67644 …WM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_E5_SHIFT 8
67706 …I_MEM_PRTY_K2_E5 (0x1<<8) // This bit masks, …
67707 …WM_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_K2_E5_SHIFT 8
67769 …I_MEM_PRTY_K2_E5 (0x1<<8) // This bit masks, …
67770 …WM_REG_PRTY_MASK_H_2_MEM069_I_MEM_PRTY_K2_E5_SHIFT 8
67826 …IF_ENABLE (0x1<<8) // Enables the tm_r…
67827 …BF_REG_IF_ENABLE_REG_TM_REQ_IF_ENABLE_SHIFT 8
67862 …_REG_DBG_OUT_DATA_SIZE 8
67872 …_REG_FC_DBG_OUT_DATA_SIZE 8
67886 …_REG_FC_DBG_OUT_DATA_B_SIZE 8
67921 …I_ECC_0_RF_INT_E5 (0x1<<8) // This bit masks, …
67922 …BF_REG_PRTY_MASK_H_0_MEM016_I_ECC_0_RF_INT_E5_SHIFT 8
67985 …I_ECC_1_RF_INT_BB_K2 (0x1<<8) // This bit masks, …
67986 …BF_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT_BB_K2_SHIFT 8
68060 …I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
68061 …BF_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 8
68076 …I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, …
68077 …BF_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_BB_K2_SHIFT 8
68178 …16_I_ECC_0_EN_E5 (0x1<<8) // Enable ECC for m…
68179 …BF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_0_EN_E5_SHIFT 8
68224 …12_I_ECC_1_EN_BB_K2 (0x1<<8) // Enable ECC for m…
68225 …BF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_1_EN_BB_K2_SHIFT 8
68274 …_MEM016_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only …
68275 …BF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_0_PRTY_E5_SHIFT 8
68320 …_MEM012_I_ECC_1_PRTY_BB_K2 (0x1<<8) // Set parity only …
68321 …BF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_1_PRTY_BB_K2_SHIFT 8
68370 …ED_0_MEM016_I_ECC_0_CORRECT_E5 (0x1<<8) // Record if a corr…
68371 …BF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_0_CORRECT_E5_SHIFT 8
68416 …ED_0_MEM012_I_ECC_1_CORRECT_BB_K2 (0x1<<8) // Record if a corr…
68417 …BF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_1_CORRECT_BB_K2_SHIFT 8
68527 …AL_TENANT_ID_EN_E5 (0x1<<8) // Enables inclusio…
68528 …BF_REG_SAME_AS_LAST_CONFIG_SAL_TENANT_ID_EN_E5_SHIFT 8
68536 …or the upper flex field extracted from PBF2TGFS message. A value of 0 indicates a length of 8 bytes
68544 … used only if sal_flex_upper_bytes is not 0, and number of bytes selected = 8 - sal_flex_upper_byt…
68567 …_IPV6_EXT_UNIFORM_HDR_TYPE_1_E5 (0xff<<8) // ipv6 extension u…
68568 …BF_REG_IPV6_EXT_HDR_TYPES_0_3_IPV6_EXT_UNIFORM_HDR_TYPE_1_E5_SHIFT 8
68576 …_IPV6_EXT_UNIFORM_HDR_TYPE_5_E5 (0xff<<8) // ipv6 extension u…
68577 …BF_REG_IPV6_EXT_HDR_TYPES_4_7_IPV6_EXT_UNIFORM_HDR_TYPE_5_E5_SHIFT 8
68583 …HDR_TYPE_8_E5 (0xff<<0) // ipv6 extension uniform header type 8
68585 …1_IPV6_EXT_UNIFORM_HDR_TYPE_9_E5 (0xff<<8) // ipv6 extension u…
68586 …BF_REG_IPV6_EXT_HDR_TYPES_8_11_IPV6_EXT_UNIFORM_HDR_TYPE_9_E5_SHIFT 8
68594 …C_IPV6_EXT_UNIFORM_HDR_TYPE_13_E5 (0xff<<8) // ipv6 extension u…
68595 …BF_REG_IPV6_EXT_HDR_TYPES_MISC_IPV6_EXT_UNIFORM_HDR_TYPE_13_E5_SHIFT 8
68624 …IDS_IPV6_EXT_UNIFORM_HDR_TYPE_8_VALID_E5 (0x1<<8) // If set, validate…
68625 …BF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_8_VALID_E5_SHIFT 8
68660 …_MASK_CONFIG_EVENTID_INNER_L2_TAGS_EXIST_MASK_E5 (0xff<<8) // Mask for Inner L…
68661 …BF_REG_EVENT_ID_L2_TAGS_EXIST_MASK_CONFIG_EVENTID_INNER_L2_TAGS_EXIST_MASK_E5_SHIFT 8
68849 …Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 8.
68850 … 0xd808a4UL //Access:RW DataWidth:0x5 // Almost full threshold for VOQ 8 in the YSTORM comman…
68851 …ess:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 8 (after ending the c…
68852 … 0xd808acUL //Access:RC DataWidth:0x20 // Number of commands received on VOQ 8 from YSTORM.
68853 … 0xd808b0UL //Access:R DataWidth:0xa // Number of commands in the Y command queue of VOQ 8.
68854 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 8. Reset upon init.
68855 …/Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue of VOQ 8.
68856 …0xd808bcUL //Access:RW DataWidth:0xb // The number of BTB 256 byte blocks guaranteed for VOQ 8
68858 …0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 8
68864 …cess:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 8 in both guaranteed a…
68865 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 8. Reset upon init.
68866 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 8. Reset upon init.
69372 …RD_IH (0x1<<8) // TQ read underflo…
69373 …BF_PB1_REG_INT_STS_TQ_ERROR_RD_IH_SHIFT 8
69391 …_RD_IH (0x1<<8) // This bit masks, …
69392 …BF_PB1_REG_INT_MASK_TQ_ERROR_RD_IH_SHIFT 8
69410 …OR_RD_IH (0x1<<8) // TQ read underflo…
69411 …BF_PB1_REG_INT_STS_WR_TQ_ERROR_RD_IH_SHIFT 8
69429 …ROR_RD_IH (0x1<<8) // TQ read underflo…
69430 …BF_PB1_REG_INT_STS_CLR_TQ_ERROR_RD_IH_SHIFT 8
69483 …_PB1_REG_DBG_OUT_DATA_SIZE 8
69512 …RD_IH (0x1<<8) // TQ read underflo…
69513 …BF_PB2_REG_INT_STS_TQ_ERROR_RD_IH_SHIFT 8
69531 …_RD_IH (0x1<<8) // This bit masks, …
69532 …BF_PB2_REG_INT_MASK_TQ_ERROR_RD_IH_SHIFT 8
69550 …OR_RD_IH (0x1<<8) // TQ read underflo…
69551 …BF_PB2_REG_INT_STS_WR_TQ_ERROR_RD_IH_SHIFT 8
69569 …ROR_RD_IH (0x1<<8) // TQ read underflo…
69570 …BF_PB2_REG_INT_STS_CLR_TQ_ERROR_RD_IH_SHIFT 8
69623 …_PB2_REG_DBG_OUT_DATA_SIZE 8
69649 …_ERROR (0x1<<8) // Read packet clie…
69650 …TB_REG_INT_STS_0_RC_PKT1_LEN_ERROR_SHIFT 8
69682 …N_ERROR (0x1<<8) // This bit masks, …
69683 …TB_REG_INT_MASK_0_RC_PKT1_LEN_ERROR_SHIFT 8
69715 …LEN_ERROR (0x1<<8) // Read packet clie…
69716 …TB_REG_INT_STS_WR_0_RC_PKT1_LEN_ERROR_SHIFT 8
69748 …_LEN_ERROR (0x1<<8) // Read packet clie…
69749 …TB_REG_INT_STS_CLR_0_RC_PKT1_LEN_ERROR_SHIFT 8
69785 …INT_FIFO_ERROR (0x1<<8) // Free ointer FIFO…
69786 …TB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT 8
69818 …OINT_FIFO_ERROR (0x1<<8) // This bit masks, …
69819 …TB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT 8
69851 …_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO…
69852 …TB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT 8
69884 …E_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO…
69885 …TB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT 8
69955 …R_FIFO_ERROR (0x1<<8) // Read packet clie…
69956 …TB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT 8
70020 …CR_FIFO_ERROR (0x1<<8) // This bit masks, …
70021 …TB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT 8
70085 …DSCR_FIFO_ERROR (0x1<<8) // Read packet clie…
70086 …TB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT 8
70150 …_DSCR_FIFO_ERROR (0x1<<8) // Read packet clie…
70151 …TB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT 8
70205 …ETCH_FIFO_ERROR (0x1<<8) // Link list arbite…
70206 …TB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT 8
70252 …FETCH_FIFO_ERROR (0x1<<8) // This bit masks, …
70253 …TB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT 8
70299 …REFETCH_FIFO_ERROR (0x1<<8) // Link list arbite…
70300 …TB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT 8
70346 …PREFETCH_FIFO_ERROR (0x1<<8) // Link list arbite…
70347 …TB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT 8
70403 …OND_PTR_FIFO_ERROR (0x1<<8) // Read packet clie…
70404 …TB_REG_INT_STS_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT 8
70468 …COND_PTR_FIFO_ERROR (0x1<<8) // This bit masks, …
70469 …TB_REG_INT_MASK_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT 8
70533 …SECOND_PTR_FIFO_ERROR (0x1<<8) // Read packet clie…
70534 …TB_REG_INT_STS_WR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT 8
70598 …_SECOND_PTR_FIFO_ERROR (0x1<<8) // Read packet clie…
70599 …TB_REG_INT_STS_CLR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT 8
70695 …IFO_PUSH_ERROR (0x1<<8) // Release SYNC FIF…
70696 …TB_REG_INT_STS_11_RLS_SYNC_FIFO_PUSH_ERROR_SHIFT 8
70700 …FIFO_PUSH_ERROR (0x1<<8) // This bit masks, …
70701 …TB_REG_INT_MASK_11_RLS_SYNC_FIFO_PUSH_ERROR_SHIFT 8
70705 …C_FIFO_PUSH_ERROR (0x1<<8) // Release SYNC FIF…
70706 …TB_REG_INT_STS_WR_11_RLS_SYNC_FIFO_PUSH_ERROR_SHIFT 8
70710 …NC_FIFO_PUSH_ERROR (0x1<<8) // Release SYNC FIF…
70711 …TB_REG_INT_STS_CLR_11_RLS_SYNC_FIFO_PUSH_ERROR_SHIFT 8
70742 …I_ECC_RF_INT (0x1<<8) // This bit masks, …
70743 …TB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_SHIFT 8
70872 … (0x1<<8) // Enable ECC for memory ecc instance btb.BB_BANK_K…
70873 …TB_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_SHIFT 8
70924 … (0x1<<8) // Set parity only for memory ecc instance btb.BB_BANK…
70925 …TB_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_SHIFT 8
70976 … (0x1<<8) // Record if a correctable error occurred on memory ecc instance …
70977 …TB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_SHIFT 8
71013 …te up to two ECC errors on the next write to memory: btb.BB_BANK_BB_GEN_FOR[8].BB_BANK_BB_GEN_IF.i…
71042 …AIN2_RC_PRI (0x3<<8) // This is priority…
71043 …TB_REG_RC_PKT_PRIORITY_NIG_MAIN2_RC_PRI_SHIFT 8
71062 …ient upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.
71073 …_REG_DBG_OUT_DATA_SIZE 8
71097 …8 bits spelling of write client status: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_f…
71098 …cess:R DataWidth:0xd // Debug register. Full status of write clients. 8 bits spelling of wri…
71101 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
71102 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
71103 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
71104 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
71105 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
71106 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
71107 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
71108 …acket clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 - - re…
71109 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
71110 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
71111 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
71112 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
71113 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
71114 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
71115 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
71116 …acket clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 - - re…
71117 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
71118 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
71119 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
71120 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
71121 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
71122 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
71123 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
71124 …ls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dsc…
71127 …th:0x10 // Debug register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr…
71145 …_REG_STOPPED_RD_REQ_SIZE_BB 8
71149 …_REG_STOPPED_RLS_REQ_SIZE_BB 8
71151 …8 bits spelling of write client status: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]…
71251 … (0xff<<0) // Register supports up to an 8 bit VFID. For smalle…
71253 …FID_UNUSED0 (0xff<<8) //
71254 …CP_REG_MCP_VFID_UNUSED0_SHIFT 8
71288 …MODE_UNUSED1 (0x3<<8) //
71289 …CP_REG_CPU_MODE_UNUSED1_SHIFT 8
71319 …ALTED (0x1<<8) // This bit is set …
71320 …CP_REG_CPU_STATE_FIO_ABORT_HALTED_SHIFT 8
71356 … (0x1<<8) // This bit enables the attention output when …
71357 …CP_REG_CPU_EVENT_MASK_FIO_ABORT_MASK_SHIFT 8
71435 … (0x1<<8) // If this bit is '…
71436 …CP_REG_MDIO_MODE_BIT_BANG_SHIFT 8
71467 …SWAP (0x1<<8) // This field contr…
71468 …CP_REG_UCINT_WARP_MODE_BYTE_SWAP_SHIFT 8
71489 …BLE_EN_CLR0 (0x1<<8) // Write this bit a…
71490 …CP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR0_SHIFT 8
71512 …SWAP (0x1<<8) // This field contr…
71513 …CP_REG_UCINT_PCIE_MODE_BYTE_SWAP_SHIFT 8
71532 …BLE_EN_CLR0 (0x1<<8) // Write this bit a…
71533 …CP_REG_UCINT_PCIE_TARGET_ENABLE_EN_CLR0_SHIFT 8
71551 …ADDRESS (0xf<<8) // Address of initi…
71552 …CP_REG_IMC_COMMAND_TRANSFER_ADDRESS_SHIFT 8
71568 …AVE_CONTROL_UNUSED0 (0x1ff<<8) //
71569 …CP_REG_IMC_SLAVE_CONTROL_UNUSED0_SHIFT 8
71570 …his is a 7-bit field as defined by the I2C spec, but can be written here as 8-bits -- the LSB is i…
71610 …TA_SM (0x3<<8) // This is the inte…
71611 …CP_REG_M2P_M2P_STATUS_M2P_DATA_SM_SHIFT 8
71682 …G_TAG_FILT_MASK (0xff<<8) // This is the mask…
71683 …CP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_MASK_SHIFT 8
71691 …NFIG_TAG_FILT_MASK (0x7f<<8) // This is the Maxi…
71692 …CP_REG_P2M_P2M_LENGTH_FILT_CONFIG_TAG_FILT_MASK_SHIFT 8
71730 … (0xff<<16) // This is the 8-bit Tag from VDM Hea…
71809 … 0xe0632cUL //Access:RW DataWidth:0x20 // Reflects the status of page 8.
71947 … (0x1<<8) // When this bit is…
71948 …CP_REG_NVM_COMMAND_LAST_SHIFT 8
72013 … (0xff<<8) // Controls the del…
72014 …CP_REG_NVM_CFG2_CSB_W_SHIFT 8
72022 … (0xff<<8) // Command to write…
72023 …CP_REG_NVM_CFG3_WRITE_CMD_SHIFT 8
72024 …memory. This command is similar to the read command, but with an additional 8b of dummy read betwe…
72045 … (0x1<<8) // when REQ0 arbitr…
72046 …CP_REG_NVM_SW_ARB_ARB_ARB0_SHIFT 8
72064 … (0xffff<<8) // Device ID: Memory type = device_id[15:…
72065 …CP_REG_NVM_JEDEC_ID_DEVICE_ID_SHIFT 8
72071 … (0xff<<8) // Flash write disa…
72072 …CP_REG_NVM_CFG5_WRDI_CMD_SHIFT 8
72092 …AXED_TIMING (0x1<<8) // When this bit is…
72093 …CP_REG_NVM_CFG4_SI_INPUT_RELAXED_TIMING_SHIFT 8
72127 … (0x7fffff<<8) // Reserved for fut…
72128 …CP_REG_NVM_RECONFIG_RESERVED_SHIFT 8
72294 … (0x1<<8) // When this bit is…
72295 …CP_REG_SMBUS_CONFIG_ARP_EN0_SHIFT 8
72319 …BUS_IDLE_TIME (0xff<<8) // These bits speci…
72320 …CP_REG_SMBUS_TIMING_CONFIG_SMBUS_IDLE_TIME_SHIFT 8
72332 …ADDR1 (0x7f<<8) // This is the seco…
72333 …CP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR1_SHIFT 8
72347 …ROL_MASTER_RX_FIFO_THRESHOLD (0x7f<<8) // When the Master …
72348 …CP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_THRESHOLD_SHIFT 8
72362 …OL_SLAVE_RX_FIFO_THRESHOLD (0x7f<<8) // When the Slave R…
72363 …CP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_THRESHOLD_SHIFT 8
72404 …PEC (0x1<<8) // PEC should be ch…
72405 …CP_REG_SMBUS_MASTER_COMMAND_PEC_SHIFT 8
72421 …EC (0x1<<8) // PEC should be ca…
72422 …CP_REG_SMBUS_SLAVE_COMMAND_PEC_SHIFT 8
72510 …TER_DATA_WRITE_UNUSED0 (0x7fffff<<8) //
72511 …CP_REG_SMBUS_MASTER_DATA_WRITE_UNUSED0_SHIFT 8
72517 …TER_DATA_READ_UNUSED0 (0x1fffff<<8) //
72518 …CP_REG_SMBUS_MASTER_DATA_READ_UNUSED0_SHIFT 8
72526 …VE_DATA_WRITE_UNUSED0 (0x7fffff<<8) //
72527 …CP_REG_SMBUS_SLAVE_DATA_WRITE_UNUSED0_SHIFT 8
72533 …AVE_DATA_READ_UNUSED0 (0xfffff<<8) //
72534 …CP_REG_SMBUS_SLAVE_DATA_READ_UNUSED0_SHIFT 8
72553 …3 (0xff<<8) // UDID_0 byte 13.
72554 …CP_REG_SMBUS_UDID0_3_BYTE_13_SHIFT 8
72560 …8 (0xff<<0) // UDID_0 byte 8.
72562 …9 (0xff<<8) // UDID_0 byte 9.
72563 …CP_REG_SMBUS_UDID0_2_BYTE_9_SHIFT 8
72571 …5 (0xff<<8) // UDID_0 byte 5.
72572 …CP_REG_SMBUS_UDID0_1_BYTE_5_SHIFT 8
72580 …1 (0xff<<8) // UDID_0 byte 1.
72581 …CP_REG_SMBUS_UDID0_0_BYTE_1_SHIFT 8
72589 …3 (0xff<<8) // UDID_1 byte 13.
72590 …CP_REG_SMBUS_UDID1_3_BYTE_13_SHIFT 8
72596 …8 (0xff<<0) // UDID_1 byte 8.
72598 …9 (0xff<<8) // UDID_1 byte 9.
72599 …CP_REG_SMBUS_UDID1_2_BYTE_9_SHIFT 8
72607 …5 (0xff<<8) // UDID_1 byte 5.
72608 …CP_REG_SMBUS_UDID1_1_BYTE_5_SHIFT 8
72616 …1 (0xff<<8) // UDID_1 byte 1.
72617 …CP_REG_SMBUS_UDID1_0_BYTE_1_SHIFT 8
72632 …B_FIFO_COMMAND_UNUSED1 (0xff<<8) //
72633 …CP_REG_TO_BMB_FIFO_COMMAND_UNUSED1_SHIFT 8
72668 …YTE_VALID (0x3<<8) // These bits indic…
72669 …CP_REG_FRM_BMB_FIFO_STATUS_BYTE_VALID_SHIFT 8
72704 …IN_EN (0x1<<8) // Enable for input…
72705 …SDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT 8
72752 …OUT_EN (0x1<<8) // Enable for outpu…
72753 …SDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT 8
72802 …LE_PRM (0x1<<8) // This bit should …
72803 …SDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT 8
72823 …WAIT_ERROR (0x1<<8) // Passive buffer w…
72824 …SDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
72886 …_WAIT_ERROR (0x1<<8) // This bit masks, …
72887 …SDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
72949 …UF_WAIT_ERROR (0x1<<8) // Passive buffer w…
72950 …SDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
73012 …BUF_WAIT_ERROR (0x1<<8) // Passive buffer w…
73013 …SDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
73083 …_I_MEM_PRTY (0x1<<8) // This bit masks, …
73084 …SDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT 8
73096 … or 8 are not supported by this interface as they require a completion message. If there is an att…
73127 …10] Reserved/Unused. [9] Mode bit where 0=normal and 1=auto-mask-mode. [8] Reserved/Unused…
73196 …M_REG_DBG_OUT_DATA_SIZE 8
73245 …IN_EN (0x1<<8) // Enable for input…
73246 …SDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT 8
73293 …OUT_EN (0x1<<8) // Enable for outpu…
73294 …SDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT 8
73343 …LE_PRM (0x1<<8) // This bit should …
73344 …SDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT 8
73364 …WAIT_ERROR (0x1<<8) // Passive buffer w…
73365 …SDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
73427 …_WAIT_ERROR (0x1<<8) // This bit masks, …
73428 …SDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
73490 …UF_WAIT_ERROR (0x1<<8) // Passive buffer w…
73491 …SDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
73553 …BUF_WAIT_ERROR (0x1<<8) // Passive buffer w…
73554 …SDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
73624 …_I_MEM_PRTY (0x1<<8) // This bit masks, …
73625 …SDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT 8
73633 … or 8 are not supported by this interface as they require a completion message. If there is an att…
73665 …10] Reserved/Unused. [9] Mode bit where 0=normal and 1=auto-mask-mode. [8] Reserved/Unused…
73734 …M_REG_DBG_OUT_DATA_SIZE 8
73783 …IN_EN (0x1<<8) // Enable for input…
73784 …SDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT 8
73831 …OUT_EN (0x1<<8) // Enable for outpu…
73832 …SDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT 8
73881 …LE_PRM (0x1<<8) // This bit should …
73882 …SDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT 8
73902 …WAIT_ERROR (0x1<<8) // Passive buffer w…
73903 …SDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
73965 …_WAIT_ERROR (0x1<<8) // This bit masks, …
73966 …SDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
74028 …UF_WAIT_ERROR (0x1<<8) // Passive buffer w…
74029 …SDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
74091 …BUF_WAIT_ERROR (0x1<<8) // Passive buffer w…
74092 …SDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
74166 …_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
74167 …SDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5_SHIFT 8
74174 …_I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, …
74175 …SDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT 8
74195 … or 8 are not supported by this interface as they require a completion message. If there is an att…
74227 …10] Reserved/Unused. [9] Mode bit where 0=normal and 1=auto-mask-mode. [8] Reserved/Unused…
74296 …M_REG_DBG_OUT_DATA_SIZE 8
74321 …M_REG_TIMERS_SIZE_BB_K2 8
74345 …IN_EN (0x1<<8) // Enable for input…
74346 …SDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT 8
74393 …OUT_EN (0x1<<8) // Enable for outpu…
74394 …SDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT 8
74443 …LE_PRM (0x1<<8) // This bit should …
74444 …SDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT 8
74464 …WAIT_ERROR (0x1<<8) // Passive buffer w…
74465 …SDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
74527 …_WAIT_ERROR (0x1<<8) // This bit masks, …
74528 …SDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
74590 …UF_WAIT_ERROR (0x1<<8) // Passive buffer w…
74591 …SDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
74653 …BUF_WAIT_ERROR (0x1<<8) // Passive buffer w…
74654 …SDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
74726 …_I_MEM_PRTY (0x1<<8) // This bit masks, …
74727 …SDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT 8
74737 … or 8 are not supported by this interface as they require a completion message. If there is an att…
74768 …10] Reserved/Unused. [9] Mode bit where 0=normal and 1=auto-mask-mode. [8] Reserved/Unused…
74837 …M_REG_DBG_OUT_DATA_SIZE 8
74886 …IN_EN (0x1<<8) // Enable for input…
74887 …SDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT 8
74934 …OUT_EN (0x1<<8) // Enable for outpu…
74935 …SDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT 8
74984 …LE_PRM (0x1<<8) // This bit should …
74985 …SDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT 8
75005 …WAIT_ERROR (0x1<<8) // Passive buffer w…
75006 …SDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
75068 …_WAIT_ERROR (0x1<<8) // This bit masks, …
75069 …SDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
75131 …UF_WAIT_ERROR (0x1<<8) // Passive buffer w…
75132 …SDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
75194 …BUF_WAIT_ERROR (0x1<<8) // Passive buffer w…
75195 …SDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
75269 …_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
75270 …SDM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5_SHIFT 8
75283 …_I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, …
75284 …SDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT 8
75306 … or 8 are not supported by this interface as they require a completion message. If there is an att…
75339 …10] Reserved/Unused. [9] Mode bit where 0=normal and 1=auto-mask-mode. [8] Reserved/Unused…
75408 …M_REG_DBG_OUT_DATA_SIZE 8
75457 …IN_EN (0x1<<8) // Enable for input…
75458 …SDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT 8
75505 …OUT_EN (0x1<<8) // Enable for outpu…
75506 …SDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT 8
75555 …LE_PRM (0x1<<8) // This bit should …
75556 …SDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT 8
75576 …WAIT_ERROR (0x1<<8) // Passive buffer w…
75577 …SDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
75639 …_WAIT_ERROR (0x1<<8) // This bit masks, …
75640 …SDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
75702 …UF_WAIT_ERROR (0x1<<8) // Passive buffer w…
75703 …SDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
75765 …BUF_WAIT_ERROR (0x1<<8) // Passive buffer w…
75766 …SDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT 8
75836 …_I_MEM_PRTY (0x1<<8) // This bit masks, …
75837 …SDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT 8
75849 … or 8 are not supported by this interface as they require a completion message. If there is an att…
75881 …10] Reserved/Unused. [9] Mode bit where 0=normal and 1=auto-mask-mode. [8] Reserved/Unused…
75950 …M_REG_DBG_OUT_DATA_SIZE 8
75991 …_REG_DBG_OUT_DATA_SIZE 8
76092 …ER_ERR (0x1<<8) // Read from empty …
76093 …CM_REG_INT_STS_0_IS_YSDM_UNDER_ERR_SHIFT 8
76129 …DER_ERR (0x1<<8) // This bit masks, …
76130 …CM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR_SHIFT 8
76166 …UNDER_ERR (0x1<<8) // Read from empty …
76167 …CM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR_SHIFT 8
76203 …_UNDER_ERR (0x1<<8) // Read from empty …
76204 …CM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR_SHIFT 8
76240 …ER_ERR (0x1<<8) // Read from empty …
76241 …CM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_SHIFT 8
76291 …DER_ERR (0x1<<8) // This bit masks, …
76292 …CM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_SHIFT 8
76342 …UNDER_ERR (0x1<<8) // Read from empty …
76343 …CM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_SHIFT 8
76393 …_UNDER_ERR (0x1<<8) // Read from empty …
76394 …CM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_SHIFT 8
76518 …I_ECC_1_RF_INT_E5 (0x1<<8) // This bit masks, …
76519 …CM_REG_PRTY_MASK_H_0_MEM033_I_ECC_1_RF_INT_E5_SHIFT 8
76608 …I_ECC_RF_INT_K2 (0x1<<8) // This bit masks, …
76609 …CM_REG_PRTY_MASK_H_0_MEM034_I_ECC_RF_INT_K2_SHIFT 8
76618 …I_ECC_RF_INT_BB (0x1<<8) // This bit masks, …
76619 …CM_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_BB_SHIFT 8
76653 …I_MEM_PRTY_K2_E5 (0x1<<8) // This bit masks, …
76654 …CM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2_E5_SHIFT 8
76655 …I_MEM_PRTY_BB (0x1<<8) // This bit masks, …
76656 …CM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_SHIFT 8
76692 …33_I_ECC_1_EN_E5 (0x1<<8) // Enable ECC for m…
76693 …CM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_1_EN_E5_SHIFT 8
76698 …34_I_ECC_EN_K2 (0x1<<8) // Enable ECC for m…
76699 …CM_REG_MEM_ECC_ENABLE_0_MEM034_I_ECC_EN_K2_SHIFT 8
76704 …33_I_ECC_EN_BB (0x1<<8) // Enable ECC for m…
76705 …CM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN_BB_SHIFT 8
76729 …_MEM033_I_ECC_1_PRTY_E5 (0x1<<8) // Set parity only …
76730 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_1_PRTY_E5_SHIFT 8
76735 …_MEM034_I_ECC_PRTY_K2 (0x1<<8) // Set parity only …
76736 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM034_I_ECC_PRTY_K2_SHIFT 8
76741 …_MEM033_I_ECC_PRTY_BB (0x1<<8) // Set parity only …
76742 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY_BB_SHIFT 8
76766 …ED_0_MEM033_I_ECC_1_CORRECT_E5 (0x1<<8) // Record if a corr…
76767 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_1_CORRECT_E5_SHIFT 8
76772 …ED_0_MEM034_I_ECC_CORRECT_K2 (0x1<<8) // Record if a corr…
76773 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM034_I_ECC_CORRECT_K2_SHIFT 8
76778 …ED_0_MEM033_I_ECC_CORRECT_BB (0x1<<8) // Record if a corr…
76779 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_CORRECT_BB_SHIFT 8
76837 …e local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
76838 …t of the input Msem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
76839 …t of the input Usem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
76840 …t of the input Dorq in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
76841 …ht of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
76842 …ht of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
76843 …t of the XSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
76844 …t of the YSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
76845 …t of the input USDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
76846 … QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
76847 …M (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
76848 …of the Timers input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
76855 …lative to usual once in a while. Two values have special meaning: 8'h0 - constant RR; 8'h80 - cons…
76868 … - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg mes…
76943 … 1-TX PQ); if bit[9]=0; then [8:6] reserved; [5:0] Physical queue connection number (queue number …
77042 … 0x1001800UL //Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (L…
77046 …_REG_XX_CBYP_TBL_SIZE 8
77050 …on type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:…
77053 …tion mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client I…
77079 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77080 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77081 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77082 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77083 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77084 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77085 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77086 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77087 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77088 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77089 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77090 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77091 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77092 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77093 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77094 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
77263 …t of the MSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
77264 …t of the input MSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
77275 …t of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
77276 …t of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
77298 …_REG_DBG_OUT_DATA_SIZE 8
77356 …ER_ERR (0x1<<8) // Read from empty …
77357 …CM_REG_INT_STS_0_IS_XYLD_UNDER_ERR_SHIFT 8
77387 …DER_ERR (0x1<<8) // This bit masks, …
77388 …CM_REG_INT_MASK_0_IS_XYLD_UNDER_ERR_SHIFT 8
77418 …UNDER_ERR (0x1<<8) // Read from empty …
77419 …CM_REG_INT_STS_WR_0_IS_XYLD_UNDER_ERR_SHIFT 8
77449 …_UNDER_ERR (0x1<<8) // Read from empty …
77450 …CM_REG_INT_STS_CLR_0_IS_XYLD_UNDER_ERR_SHIFT 8
77480 …_ERR1 (0x1<<8) // Write to full GR…
77481 …CM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_SHIFT 8
77527 …L_ERR1 (0x1<<8) // This bit masks, …
77528 …CM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_SHIFT 8
77574 …VFL_ERR1 (0x1<<8) // Write to full GR…
77575 …CM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_SHIFT 8
77621 …OVFL_ERR1 (0x1<<8) // Write to full GR…
77622 …CM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_SHIFT 8
77684 …I_ECC_0_RF_INT_E5 (0x1<<8) // This bit masks, …
77685 …CM_REG_PRTY_MASK_H_0_MEM029_I_ECC_0_RF_INT_E5_SHIFT 8
77790 …I_ECC_0_RF_INT_K2 (0x1<<8) // This bit masks, …
77791 …CM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT_K2_SHIFT 8
77828 …I_ECC_0_RF_INT_BB (0x1<<8) // This bit masks, …
77829 …CM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_BB_SHIFT 8
77892 …29_I_ECC_0_EN_E5 (0x1<<8) // Enable ECC for m…
77893 …CM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_0_EN_E5_SHIFT 8
77904 …25_I_ECC_0_EN_K2 (0x1<<8) // Enable ECC for m…
77905 …CM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_0_EN_K2_SHIFT 8
77916 …24_I_ECC_0_EN_BB (0x1<<8) // Enable ECC for m…
77917 …CM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN_BB_SHIFT 8
77942 …_MEM029_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only …
77943 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_0_PRTY_E5_SHIFT 8
77954 …_MEM025_I_ECC_0_PRTY_K2 (0x1<<8) // Set parity only …
77955 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_0_PRTY_K2_SHIFT 8
77966 …_MEM024_I_ECC_0_PRTY_BB (0x1<<8) // Set parity only …
77967 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY_BB_SHIFT 8
77992 …ED_0_MEM029_I_ECC_0_CORRECT_E5 (0x1<<8) // Record if a corr…
77993 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_0_CORRECT_E5_SHIFT 8
78004 …ED_0_MEM025_I_ECC_0_CORRECT_K2 (0x1<<8) // Record if a corr…
78005 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_0_CORRECT_K2_SHIFT 8
78016 …ED_0_MEM024_I_ECC_0_CORRECT_BB (0x1<<8) // Record if a corr…
78017 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT_BB_SHIFT 8
78082 …e local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
78083 …t of the input Msem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
78084 …t of the input Usem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
78085 …ht of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
78086 …ht of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
78087 …t of the YSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
78088 …t of the input XYLD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
78089 … QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
78090 …M (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
78097 …lative to usual once in a while. Two values have special meaning: 8'h0 - constant RR; 8'h80 - cons…
78107 … - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg mes…
78108 … - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg mes…
78178 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
78179 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
78180 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
78181 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
78182 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
78183 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
78184 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
78185 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
78320 … 0x1081800UL //Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (L…
78326 …_REG_XX_CBYP_TBL_SIZE 8
78333 …on type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:…
78336 …tion mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client I…
78338 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78339 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78340 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78341 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78342 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78343 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78344 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78345 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78346 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78347 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78348 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78349 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78350 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78351 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78352 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78353 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
78506 …t of the MSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
78507 …t of the input MSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
78546 …_REG_DBG_OUT_DATA_SIZE 8
78566 …ER_ERR_E5 (0x1<<8) // Read from empty …
78567 …CM_REG_INT_STS_0_IS_YPLD_UNDER_ERR_E5_SHIFT 8
78585 …DER_ERR_E5 (0x1<<8) // This bit masks, …
78586 …CM_REG_INT_MASK_0_IS_YPLD_UNDER_ERR_E5_SHIFT 8
78604 …UNDER_ERR_E5 (0x1<<8) // Read from empty …
78605 …CM_REG_INT_STS_WR_0_IS_YPLD_UNDER_ERR_E5_SHIFT 8
78623 …_UNDER_ERR_E5 (0x1<<8) // Read from empty …
78624 …CM_REG_INT_STS_CLR_0_IS_YPLD_UNDER_ERR_E5_SHIFT 8
78650 …_ERR3_BB_K2 (0x1<<8) // Write to full GR…
78651 …CM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_BB_K2_SHIFT 8
78660 …_OVFL_E5 (0x1<<8) // In-process Table…
78661 …CM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_E5_SHIFT 8
78703 …L_ERR3_BB_K2 (0x1<<8) // This bit masks, …
78704 …CM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_BB_K2_SHIFT 8
78713 …L_OVFL_E5 (0x1<<8) // This bit masks, …
78714 …CM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_E5_SHIFT 8
78756 …VFL_ERR3_BB_K2 (0x1<<8) // Write to full GR…
78757 …CM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_BB_K2_SHIFT 8
78766 …TBL_OVFL_E5 (0x1<<8) // In-process Table…
78767 …CM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_E5_SHIFT 8
78809 …OVFL_ERR3_BB_K2 (0x1<<8) // Write to full GR…
78810 …CM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_BB_K2_SHIFT 8
78819 …_TBL_OVFL_E5 (0x1<<8) // In-process Table…
78820 …CM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_E5_SHIFT 8
78886 …I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
78887 …CM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_E5_SHIFT 8
78890 …I_MEM_PRTY_K2 (0x1<<8) // This bit masks, …
78891 …CM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT 8
78894 …I_MEM_PRTY_BB (0x1<<8) // This bit masks, …
78895 …CM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT 8
79000 …e local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
79001 …ht of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
79002 …ht of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
79009 …lative to usual once in a while. Two values have special meaning: 8'h0 - constant RR; 8'h80 - cons…
79015 … - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg mes…
79081 … 0x1101440UL //Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (L…
79085 …on type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:…
79087 …tion mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client I…
79089 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79090 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79091 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79092 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79093 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79094 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79095 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79096 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79097 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79098 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79099 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79100 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79101 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79102 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79103 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79104 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
79113 …t of the input PSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
79114 …t of the input PSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
79126 …t of the input YPLD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
79142 …_REG_DBG_OUT_DATA_SIZE 8
79221 …ER_ERR_E5 (0x1<<8) // Read from empty …
79222 …CM_REG_INT_STS_0_IS_PSDM_UNDER_ERR_E5_SHIFT 8
79260 …DER_ERR_E5 (0x1<<8) // This bit masks, …
79261 …CM_REG_INT_MASK_0_IS_PSDM_UNDER_ERR_E5_SHIFT 8
79299 …UNDER_ERR_E5 (0x1<<8) // Read from empty …
79300 …CM_REG_INT_STS_WR_0_IS_PSDM_UNDER_ERR_E5_SHIFT 8
79338 …_UNDER_ERR_E5 (0x1<<8) // Read from empty …
79339 …CM_REG_INT_STS_CLR_0_IS_PSDM_UNDER_ERR_E5_SHIFT 8
79373 …_ERR (0x1<<8) // Read from empty …
79374 …CM_REG_INT_STS_1_IS_TM_UNDER_ERR_SHIFT 8
79442 …R_ERR (0x1<<8) // This bit masks, …
79443 …CM_REG_INT_MASK_1_IS_TM_UNDER_ERR_SHIFT 8
79511 …DER_ERR (0x1<<8) // Read from empty …
79512 …CM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR_SHIFT 8
79580 …NDER_ERR (0x1<<8) // Read from empty …
79581 …CM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR_SHIFT 8
79661 …I_ECC_0_RF_INT_E5 (0x1<<8) // This bit masks, …
79662 …CM_REG_PRTY_MASK_H_0_MEM030_I_ECC_0_RF_INT_E5_SHIFT 8
79771 …I_ECC_1_RF_INT_K2 (0x1<<8) // This bit masks, …
79772 …CM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT_K2_SHIFT 8
79813 …I_ECC_1_RF_INT_BB (0x1<<8) // This bit masks, …
79814 …CM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_BB_SHIFT 8
79844 …I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
79845 …CM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 8
79863 …30_I_ECC_0_EN_E5 (0x1<<8) // Enable ECC for m…
79864 …CM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_0_EN_E5_SHIFT 8
79879 …24_I_ECC_1_EN_K2 (0x1<<8) // Enable ECC for m…
79880 …CM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_1_EN_K2_SHIFT 8
79889 …23_I_ECC_1_EN_BB (0x1<<8) // Enable ECC for m…
79890 …CM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_1_EN_BB_SHIFT 8
79908 …_MEM030_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only …
79909 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_0_PRTY_E5_SHIFT 8
79924 …_MEM024_I_ECC_1_PRTY_K2 (0x1<<8) // Set parity only …
79925 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_1_PRTY_K2_SHIFT 8
79934 …_MEM023_I_ECC_1_PRTY_BB (0x1<<8) // Set parity only …
79935 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_1_PRTY_BB_SHIFT 8
79953 …ED_0_MEM030_I_ECC_0_CORRECT_E5 (0x1<<8) // Record if a corr…
79954 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_0_CORRECT_E5_SHIFT 8
79969 …ED_0_MEM024_I_ECC_1_CORRECT_K2 (0x1<<8) // Record if a corr…
79970 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_1_CORRECT_K2_SHIFT 8
79979 …ED_0_MEM023_I_ECC_1_CORRECT_BB (0x1<<8) // Record if a corr…
79980 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_1_CORRECT_BB_SHIFT 8
80044 …e local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80045 …t of the input Msem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80046 …t of the input Dorq in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80047 …ht of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80048 …ht of the input PRS in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80049 …ht of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80050 … QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80051 …M (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80052 …of the Timers input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80059 …lative to usual once in a while. Two values have special meaning: 8'h0 - constant RR; 8'h80 - cons…
80068 … - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg mes…
80069 … - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg mes…
80139 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
80140 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
80141 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
80142 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
80143 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
80144 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
80145 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
80146 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
80275 … 0x11814c0UL //Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (L…
80281 …_REG_XX_CBYP_TBL_SIZE 8
80288 …on type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:…
80291 …tion mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client I…
80317 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80318 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80319 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80320 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80321 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80322 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80323 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80324 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80325 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80326 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80327 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80328 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80329 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80330 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80331 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80332 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
80485 …t of the input TSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80486 …t of the input TSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80498 …t of the input PSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80505 …t of the input MSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80512 …t of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80513 …t of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80523 …t of the input PTLD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
80556 …_REG_DBG_OUT_DATA_SIZE 8
80614 …ER_ERR_E5 (0x1<<8) // Read from empty …
80615 …CM_REG_INT_STS_0_IS_TSDM_UNDER_ERR_E5_SHIFT 8
80624 …ER_ERR_BB_K2 (0x1<<8) // Read from empty …
80625 …CM_REG_INT_STS_0_IS_USDM_UNDER_ERR_BB_K2_SHIFT 8
80669 …DER_ERR_E5 (0x1<<8) // This bit masks, …
80670 …CM_REG_INT_MASK_0_IS_TSDM_UNDER_ERR_E5_SHIFT 8
80679 …DER_ERR_BB_K2 (0x1<<8) // This bit masks, …
80680 …CM_REG_INT_MASK_0_IS_USDM_UNDER_ERR_BB_K2_SHIFT 8
80724 …UNDER_ERR_E5 (0x1<<8) // Read from empty …
80725 …CM_REG_INT_STS_WR_0_IS_TSDM_UNDER_ERR_E5_SHIFT 8
80734 …UNDER_ERR_BB_K2 (0x1<<8) // Read from empty …
80735 …CM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR_BB_K2_SHIFT 8
80779 …_UNDER_ERR_E5 (0x1<<8) // Read from empty …
80780 …CM_REG_INT_STS_CLR_0_IS_TSDM_UNDER_ERR_E5_SHIFT 8
80789 …_UNDER_ERR_BB_K2 (0x1<<8) // Read from empty …
80790 …CM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR_BB_K2_SHIFT 8
80834 …R_ERR0 (0x1<<8) // Read from empty …
80835 …CM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_SHIFT 8
80887 …ER_ERR0 (0x1<<8) // This bit masks, …
80888 …CM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_SHIFT 8
80940 …NDER_ERR0 (0x1<<8) // Read from empty …
80941 …CM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_SHIFT 8
80993 …UNDER_ERR0 (0x1<<8) // Read from empty …
80994 …CM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_SHIFT 8
81058 …I_ECC_1_RF_INT_E5 (0x1<<8) // This bit masks, …
81059 …CM_REG_PRTY_MASK_H_0_MEM031_I_ECC_1_RF_INT_E5_SHIFT 8
81142 …I_ECC_RF_INT_BB_K2 (0x1<<8) // This bit masks, …
81143 …CM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_BB_K2_SHIFT 8
81183 …I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
81184 …CM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 8
81206 …31_I_ECC_1_EN_E5 (0x1<<8) // Enable ECC for m…
81207 …CM_REG_MEM_ECC_ENABLE_0_MEM031_I_ECC_1_EN_E5_SHIFT 8
81218 …26_I_ECC_EN_BB_K2 (0x1<<8) // Enable ECC for m…
81219 …CM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_BB_K2_SHIFT 8
81237 …_MEM031_I_ECC_1_PRTY_E5 (0x1<<8) // Set parity only …
81238 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM031_I_ECC_1_PRTY_E5_SHIFT 8
81249 …_MEM026_I_ECC_PRTY_BB_K2 (0x1<<8) // Set parity only …
81250 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_BB_K2_SHIFT 8
81268 …ED_0_MEM031_I_ECC_1_CORRECT_E5 (0x1<<8) // Record if a corr…
81269 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM031_I_ECC_1_CORRECT_E5_SHIFT 8
81280 …ED_0_MEM026_I_ECC_CORRECT_BB_K2 (0x1<<8) // Record if a corr…
81281 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_BB_K2_SHIFT 8
81343 …e local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81344 …t of the input Usem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81345 …ht of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81346 …ht of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81347 …t of the YSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81348 …t of the input USDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81349 …t of the input TMLD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81350 … QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81351 …M (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81358 …lative to usual once in a while. Two values have special meaning: 8'h0 - constant RR; 8'h80 - cons…
81369 … - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg mes…
81370 … - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg mes…
81440 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
81441 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
81442 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
81443 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
81444 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
81445 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
81446 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
81447 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
81579 … 0x1201800UL //Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (L…
81585 …_REG_XX_CBYP_TBL_SIZE 8
81592 …on type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:…
81595 …tion mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client I…
81597 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81598 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81599 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81600 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81601 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81602 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81603 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81604 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81605 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81606 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81607 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81608 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81609 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81610 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81611 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81612 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
81769 …t of the input TSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81776 …t of the input PSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81783 …t of the MSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81784 …t of the input MSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81796 …t of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81797 …t of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
81831 …_REG_DBG_OUT_DATA_SIZE 8
81899 …ER_ERR (0x1<<8) // Read from empty …
81900 …CM_REG_INT_STS_0_IS_USDM_UNDER_ERR_SHIFT 8
81940 …DER_ERR (0x1<<8) // This bit masks, …
81941 …CM_REG_INT_MASK_0_IS_USDM_UNDER_ERR_SHIFT 8
81981 …UNDER_ERR (0x1<<8) // Read from empty …
81982 …CM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR_SHIFT 8
82022 …_UNDER_ERR (0x1<<8) // Read from empty …
82023 …CM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR_SHIFT 8
82079 …ER_ERR_E5 (0x1<<8) // Read from empty …
82080 …CM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_E5_SHIFT 8
82081 …L_ERR_BB_K2 (0x1<<8) // Write to full QM…
82082 …CM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_BB_K2_SHIFT 8
82198 …DER_ERR_E5 (0x1<<8) // This bit masks, …
82199 …CM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_E5_SHIFT 8
82200 …FL_ERR_BB_K2 (0x1<<8) // This bit masks, …
82201 …CM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_BB_K2_SHIFT 8
82317 …UNDER_ERR_E5 (0x1<<8) // Read from empty …
82318 …CM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_E5_SHIFT 8
82319 …OVFL_ERR_BB_K2 (0x1<<8) // Write to full QM…
82320 …CM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_BB_K2_SHIFT 8
82436 …_UNDER_ERR_E5 (0x1<<8) // Read from empty …
82437 …CM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_E5_SHIFT 8
82438 …_OVFL_ERR_BB_K2 (0x1<<8) // Write to full QM…
82439 …CM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_BB_K2_SHIFT 8
82553 …I_ECC_0_RF_INT_E5 (0x1<<8) // This bit masks, …
82554 …CM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT_E5_SHIFT 8
82643 …I_ECC_RF_INT_BB_K2 (0x1<<8) // This bit masks, …
82644 …CM_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2_SHIFT 8
82703 …27_I_ECC_0_EN_E5 (0x1<<8) // Enable ECC for m…
82704 …CM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_0_EN_E5_SHIFT 8
82721 …08_I_ECC_EN_BB_K2 (0x1<<8) // Enable ECC for m…
82722 …CM_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_BB_K2_SHIFT 8
82744 …_MEM027_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only …
82745 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_0_PRTY_E5_SHIFT 8
82762 …_MEM008_I_ECC_PRTY_BB_K2 (0x1<<8) // Set parity only …
82763 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_BB_K2_SHIFT 8
82785 …ED_0_MEM027_I_ECC_0_CORRECT_E5 (0x1<<8) // Record if a corr…
82786 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_0_CORRECT_E5_SHIFT 8
82803 …ED_0_MEM008_I_ECC_CORRECT_BB_K2 (0x1<<8) // Record if a corr…
82804 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_BB_K2_SHIFT 8
82868 …e local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82869 …t of the input Dorq in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82870 …ht of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82871 …ht of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82872 …t of the XSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82873 …t of the YSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82874 …t of the input USDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82875 …t of the input RDIF in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82876 …t of the input RDIF in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82877 …t of the input MULD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82878 …t of the input YULD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82879 … QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82880 …M (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82881 …of the Timers input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
82888 …lative to usual once in a while. Two values have special meaning: 8'h0 - constant RR; 8'h80 - cons…
82902 … - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg mes…
82903 … - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg mes…
82973 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
82974 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
82975 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
82976 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
82977 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
82978 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
82979 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
82980 …ffset of these data in the STORM context is always 0. Index _i stands for the task type (one of 8).
83143 … 0x1281700UL //Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (L…
83149 …_REG_XX_CBYP_TBL_SIZE 8
83156 …on type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:…
83159 …tion mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client I…
83185 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83186 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83187 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83188 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83189 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83190 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83191 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83192 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83193 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83194 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83195 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83196 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83197 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83198 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83199 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83200 …of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).
83359 …t of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritise…
83396 …_ENABLE_IN_BB_K2 (0x1<<8) // Thread ready bus…
83397 …SEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2_SHIFT 8
83420 …_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5 (0xf<<8) // Passive Buffer w…
83421 …SEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5_SHIFT 8
83431 …WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5 (0xf<<8) // Passive Buffer w…
83432 …SEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5_SHIFT 8
83442 …_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
83443 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5_SHIFT 8
83453 …_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
83454 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5_SHIFT 8
83462 …_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
83463 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5_SHIFT 8
83471 …ARBITER3_PB_QUE_ARB3_AFFINITY_A_THRESH_E5 (0x7f<<8) // This register se…
83472 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_AFFINITY_A_THRESH_E5_SHIFT 8
83478 …ARBITER4_PB_QUE_ARB4_AFFINITY_B_THRESH_E5 (0x7f<<8) // This register se…
83479 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_AFFINITY_B_THRESH_E5_SHIFT 8
83506 …OAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
83507 …SEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
83564 …D_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
83565 …SEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
83625 …LOAD_PUSH_ERROR_A_E5 (0x1<<8) // This bit masks, …
83626 …SEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
83683 …RD_PUSH_ERROR_BB_K2 (0x1<<8) // This bit masks, …
83684 …SEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
83744 …T_LOAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
83745 …SEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
83802 …A_RD_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
83803 …SEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
83863 …XT_LOAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
83864 …SEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
83921 …RA_RD_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
83922 …SEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
83982 …D_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
83983 …SEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
84046 …O_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
84047 …SEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
84073 …RD_PUSH_ERROR_B_E5 (0x1<<8) // This bit masks, …
84074 …SEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
84137 …FO_ERROR_BB_K2 (0x1<<8) // This bit masks, …
84138 …SEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
84164 …A_RD_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
84165 …SEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
84228 …FIFO_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
84229 …SEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
84255 …RA_RD_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
84256 …SEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
84319 …_FIFO_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
84320 …SEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
84346 …VLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
84347 …SEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
84409 …NVLD_FOC_ERROR_A_E5 (0x1<<8) // This bit masks, …
84410 …SEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
84472 …_INVLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
84473 …SEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
84535 …C_INVLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
84536 …SEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
84632 …M_REG_VF_ERR_VECTOR_SIZE_K2_E5 8
84646 …M_REG_FIC_FIFO_SIZE 8
84678 …M_REG_ORDER_HEAD_SIZE 8
84680 …M_REG_ORDER_TAIL_SIZE 8
84682 …M_REG_ORDER_EMPTY_SIZE 8
84717 … FIC0_FIFO_X - 5, WAKE_FIFO_PRIO_X - 6, WAKE_FIFO_PRI1_X - 7,FIC0_FIFO_B - 8, WAKE_FIFO_PRIO_B - …
84751 … 0x1401410UL //Access:RW DataWidth:0x8 // This 8-bit vector is used to enable the various 8…
84774 …M_REG_DBG_OUT_DATA_SIZE 8
84788 … state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10 …
84819 …_ENABLE_IN_BB_K2 (0x1<<8) // Thread ready bus…
84820 …SEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2_SHIFT 8
84843 …_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5 (0xf<<8) // Passive Buffer w…
84844 …SEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5_SHIFT 8
84854 …WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5 (0xf<<8) // Passive Buffer w…
84855 …SEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5_SHIFT 8
84865 …_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
84866 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5_SHIFT 8
84876 …_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
84877 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5_SHIFT 8
84885 …_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
84886 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5_SHIFT 8
84894 …ARBITER3_PB_QUE_ARB3_AFFINITY_A_THRESH_E5 (0x7f<<8) // This register se…
84895 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_AFFINITY_A_THRESH_E5_SHIFT 8
84901 …ARBITER4_PB_QUE_ARB4_AFFINITY_B_THRESH_E5 (0x7f<<8) // This register se…
84902 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_AFFINITY_B_THRESH_E5_SHIFT 8
84929 …OAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
84930 …SEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
84987 …D_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
84988 …SEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
85048 …LOAD_PUSH_ERROR_A_E5 (0x1<<8) // This bit masks, …
85049 …SEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
85106 …RD_PUSH_ERROR_BB_K2 (0x1<<8) // This bit masks, …
85107 …SEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
85167 …T_LOAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
85168 …SEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
85225 …A_RD_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
85226 …SEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
85286 …XT_LOAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
85287 …SEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
85344 …RA_RD_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
85345 …SEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
85405 …D_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
85406 …SEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
85469 …O_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
85470 …SEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
85496 …RD_PUSH_ERROR_B_E5 (0x1<<8) // This bit masks, …
85497 …SEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
85560 …FO_ERROR_BB_K2 (0x1<<8) // This bit masks, …
85561 …SEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
85587 …A_RD_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
85588 …SEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
85651 …FIFO_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
85652 …SEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
85678 …RA_RD_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
85679 …SEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
85742 …_FIFO_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
85743 …SEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
85769 …VLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
85770 …SEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
85832 …NVLD_FOC_ERROR_A_E5 (0x1<<8) // This bit masks, …
85833 …SEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
85895 …_INVLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
85896 …SEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
85958 …C_INVLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
85959 …SEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
86055 …M_REG_VF_ERR_VECTOR_SIZE_K2_E5 8
86069 …M_REG_FIC_FIFO_SIZE 8
86140 … FIC0_FIFO_X - 5, WAKE_FIFO_PRIO_X - 6, WAKE_FIFO_PRI1_X - 7,FIC0_FIFO_B - 8, WAKE_FIFO_PRIO_B - …
86174 … 0x1501410UL //Access:RW DataWidth:0x8 // This 8-bit vector is used to enable the various 8…
86197 …M_REG_DBG_OUT_DATA_SIZE 8
86211 … state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10 …
86243 …_ENABLE_IN_BB_K2 (0x1<<8) // Thread ready bus…
86244 …SEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2_SHIFT 8
86267 …_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5 (0xf<<8) // Passive Buffer w…
86268 …SEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5_SHIFT 8
86278 …WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5 (0xf<<8) // Passive Buffer w…
86279 …SEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5_SHIFT 8
86289 …_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
86290 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5_SHIFT 8
86300 …_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
86301 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5_SHIFT 8
86309 …_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
86310 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5_SHIFT 8
86318 …ARBITER3_PB_QUE_ARB3_AFFINITY_A_THRESH_E5 (0x7f<<8) // This register se…
86319 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_AFFINITY_A_THRESH_E5_SHIFT 8
86325 …ARBITER4_PB_QUE_ARB4_AFFINITY_B_THRESH_E5 (0x7f<<8) // This register se…
86326 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_AFFINITY_B_THRESH_E5_SHIFT 8
86353 …OAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
86354 …SEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
86411 …D_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
86412 …SEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
86472 …LOAD_PUSH_ERROR_A_E5 (0x1<<8) // This bit masks, …
86473 …SEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
86530 …RD_PUSH_ERROR_BB_K2 (0x1<<8) // This bit masks, …
86531 …SEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
86591 …T_LOAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
86592 …SEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
86649 …A_RD_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
86650 …SEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
86710 …XT_LOAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
86711 …SEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
86768 …RA_RD_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
86769 …SEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
86829 …D_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
86830 …SEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
86893 …O_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
86894 …SEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
86920 …RD_PUSH_ERROR_B_E5 (0x1<<8) // This bit masks, …
86921 …SEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
86984 …FO_ERROR_BB_K2 (0x1<<8) // This bit masks, …
86985 …SEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
87011 …A_RD_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
87012 …SEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
87075 …FIFO_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
87076 …SEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
87102 …RA_RD_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
87103 …SEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
87166 …_FIFO_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
87167 …SEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
87193 …VLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
87194 …SEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
87256 …NVLD_FOC_ERROR_A_E5 (0x1<<8) // This bit masks, …
87257 …SEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
87319 …_INVLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
87320 …SEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
87382 …C_INVLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
87383 …SEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
87477 …M_REG_VF_ERR_VECTOR_SIZE_K2_E5 8
87560 … FIC0_FIFO_X - 5, WAKE_FIFO_PRIO_X - 6, WAKE_FIFO_PRI1_X - 7,FIC0_FIFO_B - 8, WAKE_FIFO_PRIO_B - …
87593 … 0x1601410UL //Access:RW DataWidth:0x8 // This 8-bit vector is used to enable the various 8…
87616 …M_REG_DBG_OUT_DATA_SIZE 8
87630 … state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10 …
87662 …_ENABLE_IN_BB_K2 (0x1<<8) // Thread ready bus…
87663 …SEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2_SHIFT 8
87686 …_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5 (0xf<<8) // Passive Buffer w…
87687 …SEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5_SHIFT 8
87697 …WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5 (0xf<<8) // Passive Buffer w…
87698 …SEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5_SHIFT 8
87708 …_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
87709 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5_SHIFT 8
87719 …_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
87720 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5_SHIFT 8
87728 …_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
87729 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5_SHIFT 8
87737 …ARBITER3_PB_QUE_ARB3_AFFINITY_A_THRESH_E5 (0x7f<<8) // This register se…
87738 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_AFFINITY_A_THRESH_E5_SHIFT 8
87744 …ARBITER4_PB_QUE_ARB4_AFFINITY_B_THRESH_E5 (0x7f<<8) // This register se…
87745 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_AFFINITY_B_THRESH_E5_SHIFT 8
87772 …OAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
87773 …SEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
87830 …D_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
87831 …SEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
87891 …LOAD_PUSH_ERROR_A_E5 (0x1<<8) // This bit masks, …
87892 …SEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
87949 …RD_PUSH_ERROR_BB_K2 (0x1<<8) // This bit masks, …
87950 …SEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
88010 …T_LOAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
88011 …SEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
88068 …A_RD_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
88069 …SEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
88129 …XT_LOAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
88130 …SEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
88187 …RA_RD_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
88188 …SEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
88248 …D_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
88249 …SEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
88312 …O_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
88313 …SEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
88339 …RD_PUSH_ERROR_B_E5 (0x1<<8) // This bit masks, …
88340 …SEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
88403 …FO_ERROR_BB_K2 (0x1<<8) // This bit masks, …
88404 …SEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
88430 …A_RD_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
88431 …SEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
88494 …FIFO_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
88495 …SEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
88521 …RA_RD_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
88522 …SEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
88585 …_FIFO_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
88586 …SEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
88612 …VLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
88613 …SEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
88675 …NVLD_FOC_ERROR_A_E5 (0x1<<8) // This bit masks, …
88676 …SEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
88738 …_INVLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
88739 …SEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
88801 …C_INVLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
88802 …SEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
88896 …M_REG_VF_ERR_VECTOR_SIZE_K2_E5 8
88979 … FIC0_FIFO_X - 5, WAKE_FIFO_PRIO_X - 6, WAKE_FIFO_PRI1_X - 7,FIC0_FIFO_B - 8, WAKE_FIFO_PRIO_B - …
89012 … 0x1701410UL //Access:RW DataWidth:0x8 // This 8-bit vector is used to enable the various 8…
89035 …M_REG_DBG_OUT_DATA_SIZE 8
89049 … state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10 …
89080 …_ENABLE_IN_BB_K2 (0x1<<8) // Thread ready bus…
89081 …SEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2_SHIFT 8
89104 …_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5 (0xf<<8) // Passive Buffer w…
89105 …SEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5_SHIFT 8
89115 …WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5 (0xf<<8) // Passive Buffer w…
89116 …SEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5_SHIFT 8
89126 …_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
89127 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5_SHIFT 8
89137 …_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
89138 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5_SHIFT 8
89146 …_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
89147 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5_SHIFT 8
89155 …ARBITER3_PB_QUE_ARB3_AFFINITY_A_THRESH_E5 (0x7f<<8) // This register se…
89156 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_AFFINITY_A_THRESH_E5_SHIFT 8
89162 …ARBITER4_PB_QUE_ARB4_AFFINITY_B_THRESH_E5 (0x7f<<8) // This register se…
89163 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_AFFINITY_B_THRESH_E5_SHIFT 8
89190 …OAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
89191 …SEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
89248 …D_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
89249 …SEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
89309 …LOAD_PUSH_ERROR_A_E5 (0x1<<8) // This bit masks, …
89310 …SEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
89367 …RD_PUSH_ERROR_BB_K2 (0x1<<8) // This bit masks, …
89368 …SEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
89428 …T_LOAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
89429 …SEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
89486 …A_RD_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
89487 …SEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
89547 …XT_LOAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
89548 …SEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
89605 …RA_RD_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
89606 …SEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
89666 …D_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
89667 …SEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
89730 …O_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
89731 …SEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
89757 …RD_PUSH_ERROR_B_E5 (0x1<<8) // This bit masks, …
89758 …SEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
89821 …FO_ERROR_BB_K2 (0x1<<8) // This bit masks, …
89822 …SEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
89848 …A_RD_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
89849 …SEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
89912 …FIFO_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
89913 …SEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
89939 …RA_RD_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
89940 …SEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
90003 …_FIFO_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
90004 …SEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
90030 …VLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
90031 …SEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
90093 …NVLD_FOC_ERROR_A_E5 (0x1<<8) // This bit masks, …
90094 …SEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
90156 …_INVLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
90157 …SEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
90219 …C_INVLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
90220 …SEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
90299 …_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, …
90300 …SEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5_SHIFT 8
90378 …M_REG_VF_ERR_VECTOR_SIZE_K2_E5 8
90461 … FIC0_FIFO_X - 5, WAKE_FIFO_PRIO_X - 6, WAKE_FIFO_PRI1_X - 7,FIC0_FIFO_B - 8, WAKE_FIFO_PRIO_B - …
90494 … 0x1801410UL //Access:RW DataWidth:0x8 // This 8-bit vector is used to enable the various 8…
90517 …M_REG_DBG_OUT_DATA_SIZE 8
90531 … state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10 …
90563 …_ENABLE_IN_BB_K2 (0x1<<8) // Thread ready bus…
90564 …SEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_BB_K2_SHIFT 8
90587 …_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5 (0xf<<8) // Passive Buffer w…
90588 …SEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_RR_DRA_B_WEIGHT_E5_SHIFT 8
90598 …WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5 (0xf<<8) // Passive Buffer w…
90599 …SEM_REG_PASSIVE_BUFFER_READ_WRR_ARBITER_PB_RD_RR_DRA_B_WEIGHT_E5_SHIFT 8
90609 …_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
90610 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER0_PB_QUE_ARB0_RR_PRIO0_A_WEIGHT_E5_SHIFT 8
90620 …_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
90621 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER1_PB_QUE_ARB1_RR_PRIO1_X_WEIGHT_E5_SHIFT 8
90629 …_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5 (0xf<<8) // Passive Buffer Q…
90630 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER2_PB_QUE_ARB2_RR_PRIO1_B_WEIGHT_E5_SHIFT 8
90638 …ARBITER3_PB_QUE_ARB3_AFFINITY_A_THRESH_E5 (0x7f<<8) // This register se…
90639 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER3_PB_QUE_ARB3_AFFINITY_A_THRESH_E5_SHIFT 8
90645 …ARBITER4_PB_QUE_ARB4_AFFINITY_B_THRESH_E5 (0x7f<<8) // This register se…
90646 …SEM_REG_PASSIVE_BUFFER_QUEUE_ARBITER4_PB_QUE_ARB4_AFFINITY_B_THRESH_E5_SHIFT 8
90673 …OAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
90674 …SEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
90731 …D_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
90732 …SEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
90792 …LOAD_PUSH_ERROR_A_E5 (0x1<<8) // This bit masks, …
90793 …SEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
90850 …RD_PUSH_ERROR_BB_K2 (0x1<<8) // This bit masks, …
90851 …SEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
90911 …T_LOAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
90912 …SEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
90969 …A_RD_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
90970 …SEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
91030 …XT_LOAD_PUSH_ERROR_A_E5 (0x1<<8) // Error in externa…
91031 …SEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_A_E5_SHIFT 8
91088 …RA_RD_PUSH_ERROR_BB_K2 (0x1<<8) // Error in DRA_RD_…
91089 …SEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_BB_K2_SHIFT 8
91149 …D_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
91150 …SEM_REG_INT_STS_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
91213 …O_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
91214 …SEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
91240 …RD_PUSH_ERROR_B_E5 (0x1<<8) // This bit masks, …
91241 …SEM_REG_INT_MASK_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
91304 …FO_ERROR_BB_K2 (0x1<<8) // This bit masks, …
91305 …SEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
91331 …A_RD_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
91332 …SEM_REG_INT_STS_WR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
91395 …FIFO_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
91396 …SEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
91422 …RA_RD_PUSH_ERROR_B_E5 (0x1<<8) // DRA RD FIFO erro…
91423 …SEM_REG_INT_STS_CLR_1_FAST_DRA_RD_PUSH_ERROR_B_E5_SHIFT 8
91486 …_FIFO_ERROR_BB_K2 (0x1<<8) // Indicates an ove…
91487 …SEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_BB_K2_SHIFT 8
91513 …VLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
91514 …SEM_REG_INT_STS_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
91576 …NVLD_FOC_ERROR_A_E5 (0x1<<8) // This bit masks, …
91577 …SEM_REG_INT_MASK_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
91639 …_INVLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
91640 …SEM_REG_INT_STS_WR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
91702 …C_INVLD_FOC_ERROR_A_E5 (0x1<<8) // Error in FOC err…
91703 …SEM_REG_INT_STS_CLR_2_FIN_RBC_INVLD_FOC_ERROR_A_E5_SHIFT 8
91797 …M_REG_VF_ERR_VECTOR_SIZE_K2_E5 8
91880 … FIC0_FIFO_X - 5, WAKE_FIFO_PRIO_X - 6, WAKE_FIFO_PRI1_X - 7,FIC0_FIFO_B - 8, WAKE_FIFO_PRIO_B - …
91913 … 0x1901410UL //Access:RW DataWidth:0x8 // This 8-bit vector is used to enable the various 8…
91936 …M_REG_DBG_OUT_DATA_SIZE 8
91950 … state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10 …