Lines Matching +full:4000 +full:b000

5866 …Lane0 by the flip operation performed in Detect. Allowed values are:  - 3'b000: Connect logical La…
8200 …PRESCALE_BB                                                   (0x7<<4) // b000 : prescale = 2**2 o…
26523 …          (0x7<<0) // Clock source select for TX path branch 1 clock :  3'b000 - lnX_clk_i 3'b001-…
26527 …           (0x7<<4) // Clock source select for TX path branch 2 clock : 3'b000 - lnX_clk_i 3'b001-…
26532 …           (0x7<<0) // Clock source select for RX path branch 1 clock : 3'b000 - pma_lX_rxb_iRecov…
26536 …           (0x7<<4) // Clock source select for RX path branch 2 clock : 3'b000 - pma_lX_rxb_iRecov…
26541 …           (0x7<<0) // Clock source select for RX path branch 3 clock : 3'b000 - qd_ck_i 3'b001- p…
26545 …           (0x7<<4) // Clock source select for RX path branch 4 clock : 3'b000 - qd_ck_i 3'b001- p…
37061 …:11] - spare RW register reset by por reset; [10:8] : PCIe Device Type: 3'b000 - Endpoint mode; 3'…
38003 …t VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0…
38006 …t VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0…
38036 …t VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0…
38038 …t VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0…
64685 …face.  All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
64702 …face.  All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
64719 …face.  All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.