Lines Matching +full:30 +full:b10000
140 … (0x1<<30) // Signaled system …
141 …IEIP_REG_PCIEEP_CMD_SSE_E5_SHIFT 30
185 …SIGNALED_SYS_ERR_K2 (0x1<<30) // Fatal or Non-Fat…
186 …IEIP_REG_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2_SHIFT 30
236 …SIG_SERR_BB (0x1<<30) // This bit is set …
237 …IEIP_REG_STATUS_COMMAND_PRI_SIG_SERR_BB_SHIFT 30
582 …T_BB (0x1<<30) // This bit indicat…
583 …IEIP_REG_PM_CAP_PME_IN_D3_HOT_BB_SHIFT 30
699 …_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2 (0x1<<30) // Reserved.
700 …IEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2_SHIFT 30
892 …_E5 (0x1<<30) // Link bandwidth m…
893 …IEIP_REG_PCIEEP_LINK_CTL_LBM_E5_SHIFT 30
929 …TATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2 (0x1<<30) // Link Bandwidth M…
930 …IEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2_SHIFT 30
1132 …BB (0x1<<30) // If 1, all of the…
1133 …IEIP_REG_MSIX_CAP_FUNC_MASK_BB_SHIFT 30
1166 …RL_FUNM_E5 (0x1<<30) // Function mask. …
1167 …IEIP_REG_PCIEEP_MSIX_CAP_CNTRL_FUNM_E5_SHIFT 30
1177 …T_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2 (0x1<<30) // Function Mask. …
1178 …IEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2_SHIFT 30
3965 …FORCE_LOCAL_TX_PRESET_ENABLE_K2 (0x1<<30) // Force Local Tran…
3966 …IEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_K2_SHIFT 30
4281 …Timers - Debug mode for PTM Timers. The 100us timer output will go high at 30us and the 10ms timer…
4326 …L2_FORCE_LOC_TXPRE_EN_E5 (0x1<<30) // Force local tran…
4327 …IEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_TXPRE_EN_E5_SHIFT 30
4417 …NT_BB (0x1<<30) // This bit indicat…
4418 …IEIP_REG_CONFIG_3_VAUX_PRESENT_BB_SHIFT 30
4780 …timers. Debug mode for PTM timers. The 100us timer output will go high at 30us and the 10ms timer…
4964 … extended capability structure is defined in bits 31:30 of RC_EXT_CAP_ENA field . AER in bits 31:3…
4978 …_ID_RC_EXT_CAP_ENA_BB (0x3<<30) // Enable for the R…
4979 …IEIP_REG_REG_DEV_SER_NUM_CAP_ID_RC_EXT_CAP_ENA_BB_SHIFT 30
5288 …PML1_E5 (0x1<<30) // Enter ASPM L1 wi…
5289 …IEIP_REG_PCIEEP_ACK_FREQ_EASPML1_E5_SHIFT 30
5301 …_ENTER_ASPM_K2 (0x1<<30) // ASPM L1 Entry Co…
5302 …IEIP_REG_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_K2_SHIFT 30
5440 …_IO_FILT_E5 (0x1<<30) // Mask filtering o…
5441 …IEIP_REG_PCIEEP_SYMB_TIMER_M_IO_FILT_E5_SHIFT 30
5451 …received - 1: For RADM RC filter to allow CFG transaction being received [30]: CX_FLT_MASK_RC_IO_…
5588 …_TYPE_ORDERING_E5 (0x1<<30) // TLP type orderin…
5589 …IEIP_REG_PCIEEP_P_RCV_CREDIT_TYPE_ORDERING_E5_SHIFT 30
5603 …_TLP_TYPE_ORDERING_VC0_K2 (0x1<<30) // TLP Type Orderin…
5604 …IEIP_REG_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_K2_SHIFT 30
5718 …_CONTROL_0_UNUSED_1_BB (0x3<<30) //
5719 …IEIP_REG_TL_CONTROL_0_UNUSED_1_BB_SHIFT 30
5775 …M_LTR_BB (0x1<<30) // This bit instruc…
5776 …IEIP_REG_TL_CONTROL_1_EN_ASPM_LTR_BB_SHIFT 30
5840 …_CONTROL_2_UNUSED_1_BB (0x3<<30) //
5841 …IEIP_REG_TL_CONTROL_2_UNUSED_1_BB_SHIFT 30
5971 …_CTRLSTAT_5_UNUSED_1_BB (0x3<<30) //
5972 …IEIP_REG_TL_CTRLSTAT_5_UNUSED_1_BB_SHIFT 30
6129 …_FUNC345_MASK_UNUSED_1_BB (0x3<<30) //
6130 …IEIP_REG_TL_FUNC345_MASK_UNUSED_1_BB_SHIFT 30
6192 …_FUNC345_STAT_UNUSED_1_BB (0x3<<30) //
6193 …IEIP_REG_TL_FUNC345_STAT_UNUSED_1_BB_SHIFT 30
6255 …_FUNC678_MASK_UNUSED_1_BB (0x3<<30) //
6256 …IEIP_REG_TL_FUNC678_MASK_UNUSED_1_BB_SHIFT 30
6318 …_FUNC678_STAT_UNUSED_1_BB (0x3<<30) //
6319 …IEIP_REG_TL_FUNC678_STAT_UNUSED_1_BB_SHIFT 30
6512 …_FUNC8TO10_MASK_UNUSED_1_BB (0x3<<30) //
6513 …IEIP_REG_TL_FUNC8TO10_MASK_UNUSED_1_BB_SHIFT 30
6575 …_FUNC8TO10_STAT_UNUSED_1_BB (0x3<<30) //
6576 …IEIP_REG_TL_FUNC8TO10_STAT_UNUSED_1_BB_SHIFT 30
6638 …_FUNC11TO13_MASK_UNUSED_1_BB (0x3<<30) //
6639 …IEIP_REG_TL_FUNC11TO13_MASK_UNUSED_1_BB_SHIFT 30
6704 …_FUNC11TO13_STAT_UNUSED_1_BB (0x3<<30) //
6705 …IEIP_REG_TL_FUNC11TO13_STAT_UNUSED_1_BB_SHIFT 30
6875 …_PF15_E5 (0x3<<30) // PF15 hide contro…
6876 …IEIP_REG_PCIEEP_HIDE_PF_HIDE_PF15_E5_SHIFT 30
6908 …5_HIDE_CONTROL_K2 (0x3<<30) // Operates in the …
6909 …IEIP_REG_PF_HIDE_CONTROL_PF15_HIDE_CONTROL_K2_SHIFT 30
7087 …ster is same as tl_status_0, except that it corresponds to split completion table entry for tag 30.
7232 …TN_STAT_BB (0x1<<30) // This field when …
7233 …IEIP_REG_PTM_CTL0_REG_PTM_ATTN_STAT_BB_SHIFT 30
7234 …the PTM req-response handshake completed successfully. This field is valid only when bit 30 is set.
7257 …e TLP type indicated by bits[30:24] Bits[30:24] indicate TLP type. TLP type can be masked using re…
7272 …) // This register contains the mask bits for reg_ttx_det_tlp_type_3. Bits[30:24] are the mask bit…
7290 …e TLP type indicated by bits[30:24] Bits[30:24] indicate TLP type. TLP type can be masked using re…
7305 …) // This register contains the mask bits for reg_trx_det_tlp_type_3. Bits[30:24] are the mask bit…
7384 …L_AF_THRES_SIGN_E5 (0x1<<30) // Almost full thre…
7385 …IEIP_REG_PCIEEP_RX_SER_Q_CTRL_AF_THRES_SIGN_E5_SHIFT 30
7405 …TAT_DBG_FIFO_TRIGGERED_BB (0x1<<30) // Indicates that t…
7406 …IEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_TRIGGERED_BB_SHIFT 30
7424 …_PCIE_DBG_TRIG0_MATCH_MASK - mask bits [319:0] for match trigger0 Register 30 :: IND_PCIE_DBG_TRIG…
7450 …CTL_REG_DBG_FIFO_CTL_30_BB (0x1<<30) // When set, resets…
7451 …IEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_30_BB_SHIFT 30
7504 …_LOCAL_TLDA_TRIGGERED_BB (0x1<<30) // Indicates that t…
7505 …IEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_TLDA_TRIGGERED_BB_SHIFT 30
7554 …_LOCAL_TLDA_TRIGGERED_BB (0x1<<30) // Indicates that t…
7555 …IEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_TLDA_TRIGGERED_BB_SHIFT 30
7598 … this bit is set to '1', DL will not automatically generate UpdateFC every 30us (or 120 us if Ext …
7641 …SPM_L1_ENA_BB (0x1<<30) // Internal ASPM L1…
7642 …IEIP_REG_PDL_CONTROL_1_INT_ASPM_L1_ENA_BB_SHIFT 30
7859 …FIFO_TESTSIZE_SEL_BB (0x1<<30) // Replay FIFO Test…
7860 …IEIP_REG_DL_FIFO_TEST_REPLAYFIFO_TESTSIZE_SEL_BB_SHIFT 30
7935 …30) // This bit must be written as a '1' to initiate read cycle to the pmi_addr value. When the re…
7936 …IEIP_REG_SERDES_PMI_WDATA_RCMD_BB_SHIFT 30
7937 …hen the write has completed, this bit will read as '0'. If both bit 31 and 30 set at the same time…
8021 …NABLE_RIDLE_SPD_CLR_BB (0x1<<30) // Enable the clear…
8022 …IEIP_REG_REG_PHY_CTL_0_REG_ENABLE_RIDLE_SPD_CLR_BB_SHIFT 30
8070 …LR_GEN2_HIST_BB (0x1<<30) // Clear the Gen2 d…
8071 …IEIP_REG_REG_PHY_CTL_1_REG_CLR_GEN2_HIST_BB_SHIFT 30
8083 …IS_SERDES_CLKCOMP_BB (0x1<<30) // When set, the Se…
8084 …IEIP_REG_REG_PHY_CTL_2_REG_DIS_SERDES_CLKCOMP_BB_SHIFT 30
8174 …D_1_BB (0x1<<30) // Reserved - only …
8175 …IEIP_REG_REG_PHY_CTL_5_UNUSED_1_BB_SHIFT 30
8305 …EN3_INGORE_USER_ALLOW_GEN3_BB (0x1<<30) // Ignore the "stra…
8306 …IEIP_REG_REG_PHY_CTL_8_REG_GEN3_INGORE_USER_ALLOW_GEN3_BB_SHIFT 30
8332 …EN3_DIS_PARITY_ERR_BB (0x1<<30) // Disable reportin…
8333 …IEIP_REG_REG_PHY_CTL_9_REG_GEN3_DIS_PARITY_ERR_BB_SHIFT 30
8387 …GEN3_ENA_EC2_EXIT_ON_TXEC3_BB (0x1<<30) // Enable exiting P…
8388 …IEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EC2_EXIT_ON_TXEC3_BB_SHIFT 30
8440 …GEN3_ENA_PHYIEI_EI_BB (0x1<<30) // Enable Serdes IE…
8441 …IEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_EI_BB_SHIFT 30
8465 …G_PHY_CTL_12_UNUSED_1_BB (0x3<<30) //
8466 …IEIP_REG_REG_PHY_CTL_12_UNUSED_1_BB_SHIFT 30
8486 …GEN3_EN_LP_COEFF_MATCH_BB (0x1<<30) // enable LP coeffc…
8487 …IEIP_REG_REG_PHY_CTL_13_REG_GEN3_EN_LP_COEFF_MATCH_BB_SHIFT 30
8539 …GEN3_EC3_EN_COEFFPR_MATCHREJ_TWOTS1_BB (0x1<<30) // [DEBUG_BIT]: Pha…
8540 …IEIP_REG_REG_PHY_CTL_16_REG_GEN3_EC3_EN_COEFFPR_MATCHREJ_TWOTS1_BB_SHIFT 30
8574 …GEN3_SKIP_PH3_RXEVAL_TO_SERDES_BB (0x1<<30) // Phase3: Skips Rx…
8575 …IEIP_REG_REG_PHY_CTL_17_REG_GEN3_SKIP_PH3_RXEVAL_TO_SERDES_BB_SHIFT 30
8649 …Gen3) 5'b01111: Serdes low frequency pattern (with framing for Gen3) 5'b10000: MAC Compliance pa…
9233 … (0xf<<4) // The state of the clock PM state machine and perstb 30 transitions in the p…
9307 …_E5 (0x1<<30) // Signaled system …
9308 …IEIP_VF_REG_PCIEEPVF_CMD_SSE_E5_SHIFT 30
9352 …D_REG_SIGNALED_SYS_ERR_K2 (0x1<<30) // Fatal or Non-Fat…
9353 …IEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2_SHIFT 30
9519 …CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2 (0x1<<30) // Reserved.
9520 …IEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2_SHIFT 30
9712 …L_LBM_E5 (0x1<<30) // Link bandwidth m…
9713 …IEIP_VF_REG_PCIEEPVF_LINK_CTL_LBM_E5_SHIFT 30
9749 …LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2 (0x1<<30) // Link Bandwidth M…
9750 …IEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2_SHIFT 30
9948 …P_CNTRL_FUNM_E5 (0x1<<30) // Function mask. …
9949 …IEIP_VF_REG_PCIEEPVF_MSIX_CAP_CNTRL_FUNM_E5_SHIFT 30
9959 …ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2 (0x1<<30) // Function Mask. …
9960 …IEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2_SHIFT 30
10781 … the instruction. Bit 31 indicates whether the instruction is valid. Bit 30 indicates if the ins…
10868 …RT_PREAMBLE_K2_E5 (0x1<<30) // reserved; write …
10869 …H_MAC_REG_COMMAND_CONFIG_SHORT_PREAMBLE_K2_E5_SHIFT 30
36360 …5] rst_tcfc;[26] reserved; [27] rst_igu; [28] rst_dmae; [29]rst_semi_rtc; [30] rst_rgsrc; [31] rst…
36362 …25] Reserved; [26] rst_rbcv; [27] rst_ypld; [28] rst_ptld; [29] rst_rgfs; [30] rst_tgfs; [31] rst_…
36410 … 0x008478UL //Access:RW DataWidth:0x1 // Set/clr general attention 30; this will set/clr b…
36419 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36420 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36421 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36422 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36423 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36424 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36425 …errupt; [28] Vaux PCI core Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36426 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36428 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36429 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36430 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36431 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36432 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36433 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36434 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36435 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36437 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36438 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36439 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36440 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36441 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36442 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36443 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36444 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36446 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36447 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36448 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36449 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36450 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36451 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36452 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36453 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36455 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36456 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36457 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36458 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36459 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36460 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36461 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36462 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36464 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36465 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36466 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36467 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36468 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36469 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36470 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36471 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36473 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36474 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36475 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36476 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36477 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36478 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36479 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36480 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36482 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36483 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36484 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36485 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36486 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36487 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36488 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36489 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36491 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36492 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36493 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36494 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36495 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36496 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36497 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36498 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36500 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36501 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36502 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36503 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36504 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36505 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36506 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36507 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36509 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36510 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36511 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36512 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36513 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36514 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36515 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36516 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36518 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36519 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36520 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36521 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36522 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36523 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36524 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36525 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36527 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36528 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36529 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36530 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36531 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36532 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36533 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36534 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36536 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36537 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36538 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36539 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36540 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36541 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36542 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36543 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36545 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36546 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36547 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36548 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36549 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36550 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36551 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36552 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36554 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36555 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36556 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36557 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36558 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36559 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36560 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36561 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36563 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36564 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36565 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36566 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36567 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36568 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36569 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36570 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36572 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36573 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36574 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36575 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36576 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36577 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36578 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36579 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36581 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36582 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36583 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36584 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36585 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36586 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36587 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36588 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36590 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36591 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36592 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36593 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36594 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36595 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36596 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36597 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36599 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36600 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36601 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36602 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36603 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36604 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36605 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36606 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36608 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36609 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36610 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36611 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36612 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36613 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36614 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36615 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36617 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36618 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36619 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36620 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36621 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36622 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36623 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36624 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36626 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
36627 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36628 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36629 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36630 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36631 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36632 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36633 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36637 … GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31…
36638 … #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD e…
36639 …al attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31…
36640 …ror; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; […
36641 …r; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; …
36642 …or; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; […
36643 …core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error;…
36644 …P Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; […
36703 …0 - no; 1 - yes); [29] rst_nws_core_assert_on_core_rst (0 - no; 1 - yes); [30] rst_ms_core_assert_…
37113 …7b4UL //Access:RW DataWidth:0x20 // Eco reserved. Global register. [31:30] - used to programm …
37200 … 0x00c0c0UL //Access:RW DataWidth:0x1 // Command 30 go.
37835 …4 // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 MSB…
37878 …PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-…
37909 …PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-…
37965 …PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-…
38003 …sition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO f…
38006 …sition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO f…
38036 …sition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO f…
38038 …sition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO f…
38100 …dco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vc…
38104 …dco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vc…
38108 …dco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vc…
38275 …dco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vc…
38278 …dco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vc…
38281 …dco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vc…
39001 …_0_CNIG_LINK_DOWN_P1_E1_ISIG_STATUS (0x1<<30) // Current status o…
39002 …MU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P1_E1_ISIG_STATUS_SHIFT 30
39097 …_2_TSEM_SEM_IDLE_E1_ISIG_STATUS (0x1<<30) // Current status o…
39098 …MU_REG_CPMU_INPUT_SIG_STATUS_2_TSEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT 30
39669 …ILTER_DIS_BB (0x1<<30) // When set; disabl…
39670 …AC_REG_COMMAND_CONFIG_RUNT_FILTER_DIS_BB_SHIFT 30
41675 …_MEM_PRTY_2_E5 (0x1<<30) // This bit masks, …
41676 …U_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_2_E5_SHIFT 30
41723 …_MEM_PRTY_BB (0x1<<30) // This bit masks, …
41724 …U_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_SHIFT 30
41829 …x20 // [15:0] - function number: opaque fid. [28:16] - PXP BAR address; [30:29] - Reserved; [31]…
42496 …_MEM_PRTY_K2 (0x1<<30) // This bit masks, …
42497 …S_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_SHIFT 30
42568 …_MEM_PRTY_BB (0x1<<30) // This bit masks, …
42569 …S_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_SHIFT 30
42757 …_MEM_PRTY_K2 (0x1<<30) // This bit masks, …
42758 …S_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT 30
43307 …er IP protocol 32.DSCP (extracted form IP TOS) 31.Source port or ICMP type 30.Destination port or …
45173 …FO_COUNTER_E5 (0x3<<30) // number of valid …
45174 …S_REG_COUNTER_STATUS1_RSP_FIFO_COUNTER_E5_SHIFT 30
45310 … the instruction. Bit 31 indicates whether the instruction is valid. Bit 30 indicates if the ins…
45689 … 0x2404ccUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 30 in pswrq memory.
45721 … 0x24054cUL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 30.
46208 …ccess:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b31-30: attributes.
46213 …ccess:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b31-30: attributes.
46489 … 0x240cccUL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 30
47223 …1_I_MEM_PRTY_0_E5 (0x1<<30) // This bit masks, …
47224 …WWR2_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_0_E5_SHIFT 30
47263 …7_I_MEM_PRTY_1_BB_K2 (0x1<<30) // This bit masks, …
47264 …WWR2_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_1_BB_K2_SHIFT 30
47350 …6_I_MEM_PRTY_4_E5 (0x1<<30) // This bit masks, …
47351 …WWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_4_E5_SHIFT 30
47388 …6_I_MEM_PRTY_5_BB_K2 (0x1<<30) // This bit masks, …
47389 …WWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_5_BB_K2_SHIFT 30
47473 …4_I_MEM_PRTY_7_E5 (0x1<<30) // This bit masks, …
47474 …WWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_7_E5_SHIFT 30
47513 …4_I_MEM_PRTY_8_BB_K2 (0x1<<30) // This bit masks, …
47514 …WWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_8_BB_K2_SHIFT 30
47610 …3_I_MEM_PRTY_4_E5 (0x1<<30) // This bit masks, …
47611 …WWR2_REG_PRTY_MASK_H_3_MEM013_I_MEM_PRTY_4_E5_SHIFT 30
47729 …eive side: [15:0] - Echo ID. [28:16] - sub-request length minus 1. [29] - first SR. [30] - last SR.
47924 …4_I_MEM_PRTY_BB_K2 (0x1<<30) // This bit masks, …
47925 …WRD2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT 30
47928 …5_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, …
47929 …WRD2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5_SHIFT 30
48757 …02_I_MEM_PRTY_5_K2_E5 (0x1<<30) // This bit masks, …
48758 …LUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_5_K2_E5_SHIFT 30
49243 …ccess:R DataWidth:0x20 // Indicates there was an error in MCTP BIt 21-30 Message code Bit 7-2…
49244 …ccess:R DataWidth:0x20 // Indicates there was an error in MCTP Bit 21-30 Length Bit 5-20 PCI…
49358 …NVALID_1 (0x1<<30) // Command arrived …
49359 …_REG_INT_STS_0_COMMAND_CID_INVALID_1_SHIFT 30
49423 …INVALID_1 (0x1<<30) // This bit masks, …
49424 …_REG_INT_MASK_0_COMMAND_CID_INVALID_1_SHIFT 30
49488 …D_INVALID_1 (0x1<<30) // Command arrived …
49489 …_REG_INT_STS_WR_0_COMMAND_CID_INVALID_1_SHIFT 30
49553 …ID_INVALID_1 (0x1<<30) // Command arrived …
49554 …_REG_INT_STS_CLR_0_COMMAND_CID_INVALID_1_SHIFT 30
49780 … - client out for type 13. Bits [29:28] - client out for type 14, Bits [31:30] - client out for ty…
49781 … - client out for type 13. Bits [29:28] - client out for type 14, Bits [31:30] - client out for ty…
49782 … - client out for type 13. Bits [29:28] - client out for type 14, Bits [31:30] - client out for ty…
49786 … - client out for type 13. Bits [29:28] - client out for type 14, Bits [31:30] - client out for ty…
49788 …tion for type 13, Bits [29:28] - threshold selection for type 14, Bits [31:30] - threshold selecti…
49789 …tion for type 13, Bits [29:28] - threshold selection for type 14, Bits [31:30] - threshold selecti…
49790 …tion for type 13, Bits [29:28] - threshold selection for type 14, Bits [31:30] - threshold selecti…
49893 …erved. bits [29:26] - the parent PF (applicable if VF, NA if PF). bits [48:30] - the pci base offs…
50851 …MEM_PRTY_E5 (0x1<<30) // This bit masks, …
50852 …_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_E5_SHIFT 30
50889 …MEM_PRTY_BB_K2 (0x1<<30) // This bit masks, …
50890 …_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_BB_K2_SHIFT 30
50978 …MEM_PRTY_E5 (0x1<<30) // This bit masks, …
50979 …_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_E5_SHIFT 30
51014 …MEM_PRTY_2_BB_K2 (0x1<<30) // This bit masks, …
51015 …_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_2_BB_K2_SHIFT 30
51254 …er Table Memory for Other queues 63-0; The mapping is as follow: ptrtbl[53:30] read pointer; ptrtb…
51375 …31] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used" T…
51377 …31] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used". …
51383 …31] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used" W…
51608 …6..31] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used"
51939 …35] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used" N…
51951 …35] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used" N…
51954 …nter Table Memory for TX queues 447-0; The mapping is as follow: ptrtbl[53:30] read pointer; ptrtb…
51958 …16..31,34,35] are "not used". port_mode == 2 (4 port device) : VOQs [22,23,30,31] are "not used" N…
51965 …16..31,34,35] are "not used". port_mode == 2 (4 port device) : VOQs [22,23,30,31] are "not used" N…
51970 …16..31,34,35] are "not used". port_mode == 2 (4 port device) : VOQs [22,23,30,31] are "not used" N…
51975 …16..31,34,35] are "not used". port_mode == 2 (4 port device) : VOQs [22,23,30,31] are "not used" N…
51980 …16..31,34,35] are "not used". port_mode == 2 (4 port device) : VOQs [22,23,30,31] are "not used" N…
52537 …_ERROR (0x1<<30) // Byte counter ove…
52538 …B_REG_INT_STS_0_BYTE_COUNTER_ERROR_SHIFT 30
52602 …R_ERROR (0x1<<30) // This bit masks, …
52603 …B_REG_INT_MASK_0_BYTE_COUNTER_ERROR_SHIFT 30
52667 …TER_ERROR (0x1<<30) // Byte counter ove…
52668 …B_REG_INT_STS_WR_0_BYTE_COUNTER_ERROR_SHIFT 30
52732 …NTER_ERROR (0x1<<30) // Byte counter ove…
52733 …B_REG_INT_STS_CLR_0_BYTE_COUNTER_ERROR_SHIFT 30
52793 …T_ERROR (0x1<<30) // Warning! Check t…
52794 …B_REG_INT_STS_1_WC1_LL_PA_CNT_ERROR_SHIFT 30
52854 …NT_ERROR (0x1<<30) // This bit masks, …
52855 …B_REG_INT_MASK_1_WC1_LL_PA_CNT_ERROR_SHIFT 30
52915 …_CNT_ERROR (0x1<<30) // Warning! Check t…
52916 …B_REG_INT_STS_WR_1_WC1_LL_PA_CNT_ERROR_SHIFT 30
52976 …A_CNT_ERROR (0x1<<30) // Warning! Check t…
52977 …B_REG_INT_STS_CLR_1_WC1_LL_PA_CNT_ERROR_SHIFT 30
53267 …ND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
53268 …B_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT 30
53330 …OND_PTR_FIFO_ERROR (0x1<<30) // This bit masks, …
53331 …B_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT 30
53393 …ECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
53394 …B_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT 30
53456 …SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
53457 …B_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT 30
53511 …FIFO_ERROR (0x1<<30) // Read packet clie…
53512 …B_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT 30
53566 …_FIFO_ERROR (0x1<<30) // This bit masks, …
53567 …B_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT 30
53621 …SP_FIFO_ERROR (0x1<<30) // Read packet clie…
53622 …B_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT 30
53676 …RSP_FIFO_ERROR (0x1<<30) // Read packet clie…
53677 …B_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT 30
53705 …_ERROR (0x1<<30) // Warning! Check t…
53706 …B_REG_INT_STS_6_WC4_SOP_FIFO_ERROR_SHIFT 30
53722 …O_ERROR (0x1<<30) // This bit masks, …
53723 …B_REG_INT_MASK_6_WC4_SOP_FIFO_ERROR_SHIFT 30
53739 …IFO_ERROR (0x1<<30) // Warning! Check t…
53740 …B_REG_INT_STS_WR_6_WC4_SOP_FIFO_ERROR_SHIFT 30
53756 …FIFO_ERROR (0x1<<30) // Warning! Check t…
53757 …B_REG_INT_STS_CLR_6_WC4_SOP_FIFO_ERROR_SHIFT 30
53821 …L_FIFO_ERROR (0x1<<30) // Warning! Check t…
53822 …B_REG_INT_STS_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT 30
53886 …IL_FIFO_ERROR (0x1<<30) // This bit masks, …
53887 …B_REG_INT_MASK_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT 30
53951 …VAIL_FIFO_ERROR (0x1<<30) // Warning! Check t…
53952 …B_REG_INT_STS_WR_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT 30
54016 …AVAIL_FIFO_ERROR (0x1<<30) // Warning! Check t…
54017 …B_REG_INT_STS_CLR_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT 30
54474 …_MEM_PRTY_E5 (0x1<<30) // This bit masks, …
54475 …B_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_E5_SHIFT 30
54504 …_MEM_PRTY_K2 (0x1<<30) // This bit masks, …
54505 …B_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY_K2_SHIFT 30
54520 …_MEM_PRTY_BB (0x1<<30) // This bit masks, …
54521 …B_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_SHIFT 30
54627 …_MEM_PRTY_E5 (0x1<<30) // This bit masks, …
54628 …B_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_E5_SHIFT 30
55610 … (0xf<<16) // length in 32b units from the same 30 .
55714 … (0x3f<<0) // length in 32b units from the dup 30 .
56172 … (0xf<<16) // length in 32b units from the same 30 .
56276 … (0x3f<<0) // length in 32b units from the dup 30 .
56650 … (0xf<<16) // length in 32b units from the same 30 .
56754 … (0x3f<<0) // length in 32b units from the dup 30 .
57006 …ROR (0x1<<30) // Error in the LB …
57007 …G_REG_INT_STS_1_LB_SOPQ14_ERROR_SHIFT 30
57071 …RROR (0x1<<30) // This bit masks, …
57072 …G_REG_INT_MASK_1_LB_SOPQ14_ERROR_SHIFT 30
57136 …_ERROR (0x1<<30) // Error in the LB …
57137 …G_REG_INT_STS_WR_1_LB_SOPQ14_ERROR_SHIFT 30
57201 …4_ERROR (0x1<<30) // Error in the LB …
57202 …G_REG_INT_STS_CLR_1_LB_SOPQ14_ERROR_SHIFT 30
58660 …_MEM_PRTY_BB (0x1<<30) // This bit masks, …
58661 …G_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY_BB_SHIFT 30
58760 …_MEM_PRTY_E5 (0x1<<30) // This bit masks, …
58761 …G_REG_PRTY_MASK_H_0_MEM071_I_MEM_PRTY_E5_SHIFT 30
58794 …_MEM_PRTY_K2 (0x1<<30) // This bit masks, …
58795 …G_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_K2_SHIFT 30
58949 …_MEM_PRTY_E5 (0x1<<30) // This bit masks, …
58950 …G_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_E5_SHIFT 30
58975 …_MEM_PRTY_K2 (0x1<<30) // This bit masks, …
58976 …G_REG_PRTY_MASK_H_1_MEM095_I_MEM_PRTY_K2_SHIFT 30
59025 …_MEM_PRTY_BB (0x1<<30) // This bit masks, …
59026 …G_REG_PRTY_MASK_H_1_MEM100_I_MEM_PRTY_BB_SHIFT 30
59124 …_MEM_PRTY_E5 (0x1<<30) // This bit masks, …
59125 …G_REG_PRTY_MASK_H_2_MEM021_I_MEM_PRTY_E5_SHIFT 30
59134 …_MEM_PRTY_BB (0x1<<30) // This bit masks, …
59135 …G_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_BB_SHIFT 30
59190 …_MEM_PRTY_K2 (0x1<<30) // This bit masks, …
59191 …G_REG_PRTY_MASK_H_2_MEM090_I_MEM_PRTY_K2_SHIFT 30
59721 …CMPV6_RA (0x1<<30) // Mask bit for for…
59722 …G_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6_RA_SHIFT 30
59823 …_MASK_ICMPV6_RA (0x1<<30) // Mask bit for not…
59824 …G_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6_RA_SHIFT 30
60310 …30] of the MAC timestamp value and the current free-running time are different by 2. Bits 1:0 ref…
60311 …30] of the MAC timestamp value and the current free-running time are different by 2. Bits 1:0 ref…
60695 …CMPV6_RA (0x1<<30) // Mask bit for for…
60696 …G_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6_RA_SHIFT 30
60771 …D_MASK_ICMPV6_RA (0x1<<30) // Mask bit for not…
60772 …G_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6_RA_SHIFT 30
60836 …ICMPV6_RA (0x1<<30) // Mask bit for for…
60837 …G_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6_RA_SHIFT 30
61049 …0 register. The drift frequency has a constant added shift of 8 nsec. Bits 30:28 specify how many …
61441 …T_ERROR (0x1<<30) // Warning! Check t…
61442 …B_REG_INT_STS_1_WC1_LL_PA_CNT_ERROR_SHIFT 30
61498 …NT_ERROR (0x1<<30) // This bit masks, …
61499 …B_REG_INT_MASK_1_WC1_LL_PA_CNT_ERROR_SHIFT 30
61555 …_CNT_ERROR (0x1<<30) // Warning! Check t…
61556 …B_REG_INT_STS_WR_1_WC1_LL_PA_CNT_ERROR_SHIFT 30
61612 …A_CNT_ERROR (0x1<<30) // Warning! Check t…
61613 …B_REG_INT_STS_CLR_1_WC1_LL_PA_CNT_ERROR_SHIFT 30
61887 …ND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
61888 …B_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT 30
61950 …OND_PTR_FIFO_ERROR (0x1<<30) // This bit masks, …
61951 …B_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT 30
62013 …ECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
62014 …B_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT 30
62076 …SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
62077 …B_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT 30
62131 …FIFO_ERROR (0x1<<30) // Read packet clie…
62132 …B_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT 30
62186 …_FIFO_ERROR (0x1<<30) // This bit masks, …
62187 …B_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT 30
62241 …SP_FIFO_ERROR (0x1<<30) // Read packet clie…
62242 …B_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT 30
62296 …RSP_FIFO_ERROR (0x1<<30) // Read packet clie…
62297 …B_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT 30
62355 …ND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
62356 …B_REG_INT_STS_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT 30
62414 …OND_PTR_FIFO_ERROR (0x1<<30) // This bit masks, …
62415 …B_REG_INT_MASK_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT 30
62473 …ECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
62474 …B_REG_INT_STS_WR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT 30
62532 …SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
62533 …B_REG_INT_STS_CLR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT 30
62593 …_ERROR (0x1<<30) // Warning! Check t…
62594 …B_REG_INT_STS_6_WC4_SOP_FIFO_ERROR_SHIFT 30
62654 …O_ERROR (0x1<<30) // This bit masks, …
62655 …B_REG_INT_MASK_6_WC4_SOP_FIFO_ERROR_SHIFT 30
62715 …IFO_ERROR (0x1<<30) // Warning! Check t…
62716 …B_REG_INT_STS_WR_6_WC4_SOP_FIFO_ERROR_SHIFT 30
62776 …FIFO_ERROR (0x1<<30) // Warning! Check t…
62777 …B_REG_INT_STS_CLR_6_WC4_SOP_FIFO_ERROR_SHIFT 30
62841 …L_FIFO_ERROR (0x1<<30) // Warning! Check t…
62842 …B_REG_INT_STS_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT 30
62906 …IL_FIFO_ERROR (0x1<<30) // This bit masks, …
62907 …B_REG_INT_MASK_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT 30
62971 …VAIL_FIFO_ERROR (0x1<<30) // Warning! Check t…
62972 …B_REG_INT_STS_WR_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT 30
63036 …AVAIL_FIFO_ERROR (0x1<<30) // Warning! Check t…
63037 …B_REG_INT_STS_CLR_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT 30
63101 …_ERROR (0x1<<30) // Warning! Check t…
63102 …B_REG_INT_STS_8_WC9_INP_FIFO_ERROR_SHIFT 30
63166 …O_ERROR (0x1<<30) // This bit masks, …
63167 …B_REG_INT_MASK_8_WC9_INP_FIFO_ERROR_SHIFT 30
63231 …IFO_ERROR (0x1<<30) // Warning! Check t…
63232 …B_REG_INT_STS_WR_8_WC9_INP_FIFO_ERROR_SHIFT 30
63296 …FIFO_ERROR (0x1<<30) // Warning! Check t…
63297 …B_REG_INT_STS_CLR_8_WC9_INP_FIFO_ERROR_SHIFT 30
63361 …SYNC_FIFO_PUSH_ERROR_E5 (0x1<<30) // SOP input SYNC F…
63362 …B_REG_INT_STS_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5_SHIFT 30
63371 …SYNC_FIFO_PUSH_ERROR_BB_K2 (0x1<<30) // SOP input SYNC F…
63372 …B_REG_INT_STS_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT 30
63436 …_SYNC_FIFO_PUSH_ERROR_E5 (0x1<<30) // This bit masks, …
63437 …B_REG_INT_MASK_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5_SHIFT 30
63446 …_SYNC_FIFO_PUSH_ERROR_BB_K2 (0x1<<30) // This bit masks, …
63447 …B_REG_INT_MASK_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT 30
63511 …NP_SYNC_FIFO_PUSH_ERROR_E5 (0x1<<30) // SOP input SYNC F…
63512 …B_REG_INT_STS_WR_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5_SHIFT 30
63521 …NP_SYNC_FIFO_PUSH_ERROR_BB_K2 (0x1<<30) // SOP input SYNC F…
63522 …B_REG_INT_STS_WR_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT 30
63586 …INP_SYNC_FIFO_PUSH_ERROR_E5 (0x1<<30) // SOP input SYNC F…
63587 …B_REG_INT_STS_CLR_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5_SHIFT 30
63596 …INP_SYNC_FIFO_PUSH_ERROR_BB_K2 (0x1<<30) // SOP input SYNC F…
63597 …B_REG_INT_STS_CLR_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2_SHIFT 30
63760 …_MEM_PRTY_E5 (0x1<<30) // This bit masks, …
63761 …B_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5_SHIFT 30
63790 …_MEM_PRTY_BB_K2 (0x1<<30) // This bit masks, …
63791 …B_REG_PRTY_MASK_H_0_MEM049_I_MEM_PRTY_BB_K2_SHIFT 30
65100 … (0xf<<16) // length in 32b units from the same 30 .
65204 … (0x3f<<0) // length in 32b units from the dup 30 .
65452 … (0xf<<16) // length in 32b units from the same 30 .
65556 … (0x3f<<0) // length in 32b units from the dup 30 .
67687 …_MEM_PRTY_K2_E5 (0x1<<30) // This bit masks, …
67688 …M_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_K2_E5_SHIFT 30
67750 …_MEM_PRTY_K2_E5 (0x1<<30) // This bit masks, …
67751 …M_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_K2_E5_SHIFT 30
67969 …_MEM_PRTY_E5 (0x1<<30) // This bit masks, …
67970 …F_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_E5_SHIFT 30
68025 …_MEM_PRTY_BB_K2 (0x1<<30) // This bit masks, …
68026 …F_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2_SHIFT 30
68130 …_MEM_PRTY_E5 (0x1<<30) // This bit masks, …
68131 …F_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_E5_SHIFT 30
69245 …ccess:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 30.
69246 …0xd80e24UL //Access:RW DataWidth:0x5 // Almost full threshold for VOQ 30 in the YSTORM comman…
69247 …ss:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 30 (after ending the c…
69248 … 0xd80e2cUL //Access:RC DataWidth:0x20 // Number of commands received on VOQ 30 from YSTORM.
69249 … 0xd80e30UL //Access:R DataWidth:0xa // Number of commands in the Y command queue of VOQ 30.
69250 …clic counter for number of 16 byte lines freed from the Y command queue of VOQ 30. Reset upon init.
69251 …Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue of VOQ 30.
69252 …xd80e3cUL //Access:RW DataWidth:0xb // The number of BTB 256 byte blocks guaranteed for VOQ 30
69254 …) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 30
69260 …ess:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 30 in both guaranteed a…
69261 …dth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 30. Reset upon init.
69262 …idth:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 30. Reset upon init.
69477 … the instruction. Bit 31 indicates whether the instruction is valid. Bit 30 indicates if the ins…
69617 … the instruction. Bit 31 indicates whether the instruction is valid. Bit 30 indicates if the ins…
69907 …OINT_FIFO_ERROR (0x1<<30) // Updated pointer …
69908 …B_REG_INT_STS_2_WC_DUP_UPD_POINT_FIFO_ERROR_SHIFT 30
69916 …POINT_FIFO_ERROR (0x1<<30) // This bit masks, …
69917 …B_REG_INT_MASK_2_WC_DUP_UPD_POINT_FIFO_ERROR_SHIFT 30
69925 …D_POINT_FIFO_ERROR (0x1<<30) // Updated pointer …
69926 …B_REG_INT_STS_WR_2_WC_DUP_UPD_POINT_FIFO_ERROR_SHIFT 30
69934 …PD_POINT_FIFO_ERROR (0x1<<30) // Updated pointer …
69935 …B_REG_INT_STS_CLR_2_WC_DUP_UPD_POINT_FIFO_ERROR_SHIFT 30
69999 …ND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
70000 …B_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT 30
70064 …OND_PTR_FIFO_ERROR (0x1<<30) // This bit masks, …
70065 …B_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT 30
70129 …ECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
70130 …B_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT 30
70194 …SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
70195 …B_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT 30
70241 …FIFO_ERROR (0x1<<30) // Read packet clie…
70242 …B_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT 30
70288 …_FIFO_ERROR (0x1<<30) // This bit masks, …
70289 …B_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT 30
70335 …SP_FIFO_ERROR (0x1<<30) // Read packet clie…
70336 …B_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT 30
70382 …RSP_FIFO_ERROR (0x1<<30) // Read packet clie…
70383 …B_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT 30
70447 …ND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
70448 …B_REG_INT_STS_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT 30
70512 …OND_PTR_FIFO_ERROR (0x1<<30) // This bit masks, …
70513 …B_REG_INT_MASK_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT 30
70577 …ECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
70578 …B_REG_INT_STS_WR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT 30
70642 …SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet clie…
70643 …B_REG_INT_STS_CLR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT 30
70683 …FO_PUSH_ERROR (0x1<<30) // WC input SYNC FI…
70684 …B_REG_INT_STS_10_WC0_SYNC_FIFO_PUSH_ERROR_SHIFT 30
70686 …IFO_PUSH_ERROR (0x1<<30) // This bit masks, …
70687 …B_REG_INT_MASK_10_WC0_SYNC_FIFO_PUSH_ERROR_SHIFT 30
70689 …_FIFO_PUSH_ERROR (0x1<<30) // WC input SYNC FI…
70690 …B_REG_INT_STS_WR_10_WC0_SYNC_FIFO_PUSH_ERROR_SHIFT 30
70692 …C_FIFO_PUSH_ERROR (0x1<<30) // WC input SYNC FI…
70693 …B_REG_INT_STS_CLR_10_WC0_SYNC_FIFO_PUSH_ERROR_SHIFT 30
70802 …_MEM_PRTY_E5 (0x1<<30) // This bit masks, …
70803 …B_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 30
70830 …_MEM_PRTY_K2 (0x1<<30) // This bit masks, …
70831 …B_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT 30
71176 …ATCHDOG_TIMEOUT (0x1<<30) // This bit is set …
71177 …P_REG_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT_SHIFT 30
71195 …TBEAT_INC (0x1<<30) // When set this bi…
71196 …P_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_INC_SHIFT 30
71202 …G_2_RESET (0x1<<30) // When set this bi…
71203 …P_REG_WATCHDOG_RESET_WATCHDOG_2_RESET_SHIFT 30
71215 …ST_ENABLE (0x1<<30) // When set this bi…
71216 …P_REG_WATCHDOG_CONTROL_MCP_RST_ENABLE_SHIFT 30
71561 … (0x1<<30) // Setting this bit…
71562 …P_REG_IMC_COMMAND_SOFT_RESET_SHIFT 30
72006 …_EN (0x1<<30) // Legacy strap_con…
72007 …P_REG_NVM_CFG1_FW_FLASH_TYPE_EN_SHIFT 30
72077 … (0x1<<30) // When set to 1, w…
72078 …P_REG_NVM_CFG5_USE_BUFFER_SHIFT 30
72118 …EN (0x1<<30) // Set (=1) to used…
72119 …P_REG_NVM_CFG4_SLOW_CLK_4_WREN_SHIFT 30
72150 …D_TIMEOUT (0x1<<30) // This bit is set …
72151 …P_REG_ERNGN_EXP_ROM_CTRL_READ_TIMEOUT_SHIFT 30
72211 …BUSY (0x1<<30) // This bit indicat…
72212 …P_REG_ERNGN_IMG_LOADER0_CFG_BUSY_SHIFT 30
72248 …BUSY (0x1<<30) // This bit indicat…
72249 …P_REG_ERNGN_IMG_LOADER1_CFG_BUSY_SHIFT 30
72285 …BUSY (0x1<<30) // This bit indicat…
72286 …P_REG_ERNGN_IMG_LOADER2_CFG_BUSY_SHIFT 30
72312 … (0x1<<30) // When this bit is…
72313 …P_REG_SMBUS_CONFIG_SMB_EN_SHIFT 30
72355 …ROL_MASTER_TX_FIFO_FLUSH (0x1<<30) // When this bit is…
72356 …P_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_TX_FIFO_FLUSH_SHIFT 30
72370 …OL_SLAVE_TX_FIFO_FLUSH (0x1<<30) // When this bit is…
72371 …P_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_TX_FIFO_FLUSH_SHIFT 30
72381 …_SMBCLK_OUT_EN (0x1<<30) // When the SM Bus …
72382 …P_REG_SMBUS_BIT_BANG_CONTROL_SMBCLK_OUT_EN_SHIFT 30
72414 …BORT (0x1<<30) // Transaction Abor…
72415 …P_REG_SMBUS_MASTER_COMMAND_ABORT_SHIFT 30
72429 …ORT (0x1<<30) // Transaction Abor…
72430 …P_REG_SMBUS_SLAVE_COMMAND_ABORT_SHIFT 30
72466 …TER_RX_THRESHOLD_HIT_EN (0x1<<30) // When set enables…
72467 …P_REG_SMBUS_EVENT_ENABLE_MASTER_RX_THRESHOLD_HIT_EN_SHIFT 30
72503 …TER_RX_THRESHOLD_HIT (0x1<<30) // This bit is set …
72504 …P_REG_SMBUS_EVENT_STATUS_MASTER_RX_THRESHOLD_HIT_SHIFT 30
72521 …_READ_RD_STATUS (0x3<<30) // Enumeration:
72522 …P_REG_SMBUS_MASTER_DATA_READ_RD_STATUS_SHIFT 30
72537 …READ_RD_STATUS (0x3<<30) // Enumeration:
72538 …P_REG_SMBUS_SLAVE_DATA_READ_RD_STATUS_SHIFT 30
72867 …ST_CYCLE_E5 (0x1<<30) // Unexpected last_…
72868 …DM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
72930 …AST_CYCLE_E5 (0x1<<30) // This bit masks, …
72931 …DM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
72993 …_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_…
72994 …DM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
73056 …D_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_…
73057 …DM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
73408 …ST_CYCLE_E5 (0x1<<30) // Unexpected last_…
73409 …DM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
73471 …AST_CYCLE_E5 (0x1<<30) // This bit masks, …
73472 …DM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
73534 …_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_…
73535 …DM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
73597 …D_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_…
73598 …DM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
73946 …ST_CYCLE_E5 (0x1<<30) // Unexpected last_…
73947 …DM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
74009 …AST_CYCLE_E5 (0x1<<30) // This bit masks, …
74010 …DM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
74072 …_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_…
74073 …DM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
74135 …D_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_…
74136 …DM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
74508 …ST_CYCLE_E5 (0x1<<30) // Unexpected last_…
74509 …DM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
74571 …AST_CYCLE_E5 (0x1<<30) // This bit masks, …
74572 …DM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
74634 …_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_…
74635 …DM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
74697 …D_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_…
74698 …DM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
75049 …ST_CYCLE_E5 (0x1<<30) // Unexpected last_…
75050 …DM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
75112 …AST_CYCLE_E5 (0x1<<30) // This bit masks, …
75113 …DM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
75175 …_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_…
75176 …DM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
75238 …D_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_…
75239 …DM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
75620 …ST_CYCLE_E5 (0x1<<30) // Unexpected last_…
75621 …DM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
75683 …AST_CYCLE_E5 (0x1<<30) // This bit masks, …
75684 …DM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
75746 …_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_…
75747 …DM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
75809 …D_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_…
75810 …DM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30
76602 …_MEM_PRTY_K2_E5 (0x1<<30) // This bit masks, …
76603 …M_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_E5_SHIFT 30
76620 …_MEM_PRTY_BB (0x1<<30) // This bit masks, …
76621 …M_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_SHIFT 30
77048 …REG_XX_LCID_CAM_SIZE_BB_K2 30
77051 …REG_XX_TBL_SIZE_BB_K2 30
77053 …; YCM [29:21]). Task Domain Exist (MCM [30]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - res…
77288 … [19:0]: PQ counter update value. [28:20] PQ number. [29:29] Reserved. [31:30] Command type: 0 - S…
77780 …_MEM_PRTY_E5 (0x1<<30) // This bit masks, …
77781 …M_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5_SHIFT 30
77818 …_MEM_PRTY_K2 (0x1<<30) // This bit masks, …
77819 …M_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT 30
77834 …_MEM_PRTY_BB (0x1<<30) // This bit masks, …
77835 …M_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_SHIFT 30
78336 …; YCM [29:21]). Task Domain Exist (MCM [30]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - res…
79087 …; YCM [29:21]). Task Domain Exist (MCM [30]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - res…
79417 …T_VIOLATE (0x1<<30) // Input message fi…
79418 …M_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_SHIFT 30
79486 …UT_VIOLATE (0x1<<30) // This bit masks, …
79487 …M_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_SHIFT 30
79555 …NPUT_VIOLATE (0x1<<30) // Input message fi…
79556 …M_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_SHIFT 30
79624 …INPUT_VIOLATE (0x1<<30) // Input message fi…
79625 …M_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_SHIFT 30
79757 …_MEM_PRTY_E5 (0x1<<30) // This bit masks, …
79758 …M_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5_SHIFT 30
79803 …_MEM_PRTY_K2 (0x1<<30) // This bit masks, …
79804 …M_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT 30
79815 …_MEM_PRTY_BB (0x1<<30) // This bit masks, …
79816 …M_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_SHIFT 30
80291 …; YCM [29:21]). Task Domain Exist (MCM [30]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - res…
81130 …_MEM_PRTY_E5 (0x1<<30) // This bit masks, …
81131 …M_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 30
81156 …_MEM_PRTY_BB_K2 (0x1<<30) // This bit masks, …
81157 …M_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT 30
81595 …; YCM [29:21]). Task Domain Exist (MCM [30]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - res…
82625 …_MEM_PRTY_0_BB_K2 (0x1<<30) // This bit masks, …
82626 …M_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0_BB_K2_SHIFT 30
82629 …_MEM_PRTY_1_E5 (0x1<<30) // This bit masks, …
82630 …M_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_1_E5_SHIFT 30
83159 …; YCM [29:21]). Task Domain Exist (MCM [30]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - res…
83554 …CH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
83555 …EM_REG_INT_STS_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
83604 …PT_BB_K2 (0x1<<30) // Error interrupt …
83605 …EM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2_SHIFT 30
83673 …TCH_FIFO_ERROR_E5 (0x1<<30) // This bit masks, …
83674 …EM_REG_INT_MASK_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
83723 …UPT_BB_K2 (0x1<<30) // This bit masks, …
83724 …EM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2_SHIFT 30
83792 …FETCH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
83793 …EM_REG_INT_STS_WR_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
83842 …RRUPT_BB_K2 (0x1<<30) // Error interrupt …
83843 …EM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2_SHIFT 30
83911 …_FETCH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
83912 …EM_REG_INT_STS_CLR_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
83961 …ERRUPT_BB_K2 (0x1<<30) // Error interrupt …
83962 …EM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2_SHIFT 30
84026 …T_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
84027 …EM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
84117 …ST_LSB_INP_ERROR_A_E5 (0x1<<30) // This bit masks, …
84118 …EM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
84208 …FAST_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
84209 …EM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
84299 …_FAST_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
84300 …EM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
84390 …ALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
84391 …EM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
84453 …NALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This bit masks, …
84454 …EM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
84516 …_UNALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
84517 …EM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
84579 …M_UNALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
84580 …EM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
84656 …17:12] start_rp_foc1; [23:18] start_rp_foc0; [29:24] end_rp_foc3; [35:30] end_rp_foc2; [41:36…
84977 …CH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
84978 …EM_REG_INT_STS_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
85027 …PT_BB_K2 (0x1<<30) // Error interrupt …
85028 …EM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2_SHIFT 30
85096 …TCH_FIFO_ERROR_E5 (0x1<<30) // This bit masks, …
85097 …EM_REG_INT_MASK_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
85146 …UPT_BB_K2 (0x1<<30) // This bit masks, …
85147 …EM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2_SHIFT 30
85215 …FETCH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
85216 …EM_REG_INT_STS_WR_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
85265 …RRUPT_BB_K2 (0x1<<30) // Error interrupt …
85266 …EM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2_SHIFT 30
85334 …_FETCH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
85335 …EM_REG_INT_STS_CLR_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
85384 …ERRUPT_BB_K2 (0x1<<30) // Error interrupt …
85385 …EM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2_SHIFT 30
85449 …T_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
85450 …EM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
85540 …ST_LSB_INP_ERROR_A_E5 (0x1<<30) // This bit masks, …
85541 …EM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
85631 …FAST_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
85632 …EM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
85722 …_FAST_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
85723 …EM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
85813 …ALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
85814 …EM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
85876 …NALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This bit masks, …
85877 …EM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
85939 …_UNALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
85940 …EM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
86002 …M_UNALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
86003 …EM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
86079 …17:12] start_rp_foc1; [23:18] start_rp_foc0; [29:24] end_rp_foc3; [35:30] end_rp_foc2; [41:36…
86401 …CH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
86402 …EM_REG_INT_STS_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
86451 …PT_BB_K2 (0x1<<30) // Error interrupt …
86452 …EM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2_SHIFT 30
86520 …TCH_FIFO_ERROR_E5 (0x1<<30) // This bit masks, …
86521 …EM_REG_INT_MASK_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
86570 …UPT_BB_K2 (0x1<<30) // This bit masks, …
86571 …EM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2_SHIFT 30
86639 …FETCH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
86640 …EM_REG_INT_STS_WR_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
86689 …RRUPT_BB_K2 (0x1<<30) // Error interrupt …
86690 …EM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2_SHIFT 30
86758 …_FETCH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
86759 …EM_REG_INT_STS_CLR_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
86808 …ERRUPT_BB_K2 (0x1<<30) // Error interrupt …
86809 …EM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2_SHIFT 30
86873 …T_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
86874 …EM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
86964 …ST_LSB_INP_ERROR_A_E5 (0x1<<30) // This bit masks, …
86965 …EM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
87055 …FAST_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
87056 …EM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
87146 …_FAST_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
87147 …EM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
87237 …ALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
87238 …EM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
87300 …NALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This bit masks, …
87301 …EM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
87363 …_UNALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
87364 …EM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
87426 …M_UNALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
87427 …EM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
87500 …17:12] start_rp_foc1; [23:18] start_rp_foc0; [29:24] end_rp_foc3; [35:30] end_rp_foc2; [41:36…
87820 …CH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
87821 …EM_REG_INT_STS_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
87870 …PT_BB_K2 (0x1<<30) // Error interrupt …
87871 …EM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2_SHIFT 30
87939 …TCH_FIFO_ERROR_E5 (0x1<<30) // This bit masks, …
87940 …EM_REG_INT_MASK_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
87989 …UPT_BB_K2 (0x1<<30) // This bit masks, …
87990 …EM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2_SHIFT 30
88058 …FETCH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
88059 …EM_REG_INT_STS_WR_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
88108 …RRUPT_BB_K2 (0x1<<30) // Error interrupt …
88109 …EM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2_SHIFT 30
88177 …_FETCH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
88178 …EM_REG_INT_STS_CLR_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
88227 …ERRUPT_BB_K2 (0x1<<30) // Error interrupt …
88228 …EM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2_SHIFT 30
88292 …T_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
88293 …EM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
88383 …ST_LSB_INP_ERROR_A_E5 (0x1<<30) // This bit masks, …
88384 …EM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
88474 …FAST_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
88475 …EM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
88565 …_FAST_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
88566 …EM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
88656 …ALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
88657 …EM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
88719 …NALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This bit masks, …
88720 …EM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
88782 …_UNALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
88783 …EM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
88845 …M_UNALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
88846 …EM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
88919 …17:12] start_rp_foc1; [23:18] start_rp_foc0; [29:24] end_rp_foc3; [35:30] end_rp_foc2; [41:36…
89238 …CH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
89239 …EM_REG_INT_STS_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
89288 …PT_BB_K2 (0x1<<30) // Error interrupt …
89289 …EM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2_SHIFT 30
89357 …TCH_FIFO_ERROR_E5 (0x1<<30) // This bit masks, …
89358 …EM_REG_INT_MASK_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
89407 …UPT_BB_K2 (0x1<<30) // This bit masks, …
89408 …EM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2_SHIFT 30
89476 …FETCH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
89477 …EM_REG_INT_STS_WR_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
89526 …RRUPT_BB_K2 (0x1<<30) // Error interrupt …
89527 …EM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2_SHIFT 30
89595 …_FETCH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
89596 …EM_REG_INT_STS_CLR_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
89645 …ERRUPT_BB_K2 (0x1<<30) // Error interrupt …
89646 …EM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2_SHIFT 30
89710 …T_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
89711 …EM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
89801 …ST_LSB_INP_ERROR_A_E5 (0x1<<30) // This bit masks, …
89802 …EM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
89892 …FAST_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
89893 …EM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
89983 …_FAST_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
89984 …EM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
90074 …ALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
90075 …EM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
90137 …NALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This bit masks, …
90138 …EM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
90200 …_UNALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
90201 …EM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
90263 …M_UNALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
90264 …EM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
90401 …17:12] start_rp_foc1; [23:18] start_rp_foc0; [29:24] end_rp_foc3; [35:30] end_rp_foc2; [41:36…
90721 …CH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
90722 …EM_REG_INT_STS_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
90771 …PT_BB_K2 (0x1<<30) // Error interrupt …
90772 …EM_REG_INT_STS_0_VFC_INTERRUPT_BB_K2_SHIFT 30
90840 …TCH_FIFO_ERROR_E5 (0x1<<30) // This bit masks, …
90841 …EM_REG_INT_MASK_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
90890 …UPT_BB_K2 (0x1<<30) // This bit masks, …
90891 …EM_REG_INT_MASK_0_VFC_INTERRUPT_BB_K2_SHIFT 30
90959 …FETCH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
90960 …EM_REG_INT_STS_WR_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
91009 …RRUPT_BB_K2 (0x1<<30) // Error interrupt …
91010 …EM_REG_INT_STS_WR_0_VFC_INTERRUPT_BB_K2_SHIFT 30
91078 …_FETCH_FIFO_ERROR_E5 (0x1<<30) // Error indication…
91079 …EM_REG_INT_STS_CLR_0_FIC_PRE_FETCH_FIFO_ERROR_E5_SHIFT 30
91128 …ERRUPT_BB_K2 (0x1<<30) // Error interrupt …
91129 …EM_REG_INT_STS_CLR_0_VFC_INTERRUPT_BB_K2_SHIFT 30
91193 …T_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
91194 …EM_REG_INT_STS_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
91284 …ST_LSB_INP_ERROR_A_E5 (0x1<<30) // This bit masks, …
91285 …EM_REG_INT_MASK_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
91375 …FAST_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
91376 …EM_REG_INT_STS_WR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
91466 …_FAST_LSB_INP_ERROR_A_E5 (0x1<<30) // Error in CAM_LSB…
91467 …EM_REG_INT_STS_CLR_1_CAM_RBC_FAST_LSB_INP_ERROR_A_E5_SHIFT 30
91557 …ALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
91558 …EM_REG_INT_STS_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
91620 …NALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This bit masks, …
91621 …EM_REG_INT_MASK_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
91683 …_UNALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
91684 …EM_REG_INT_STS_WR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
91746 …M_UNALLIGNED_WR_ACCESS_ERROR_E5 (0x1<<30) // This error indic…
91747 …EM_REG_INT_STS_CLR_2_SDM_PRAM_UNALLIGNED_WR_ACCESS_ERROR_E5_SHIFT 30
91820 …17:12] start_rp_foc1; [23:18] start_rp_foc0; [29:24] end_rp_foc3; [35:30] end_rp_foc2; [41:36…