Lines Matching +full:1100 +full:b000

5866 …Lane0 by the flip operation performed in Detect. Allowed values are:  - 3'b000: Connect logical La…
8200 …PRESCALE_BB                                                   (0x7<<4) // b000 : prescale = 2**2 o…
8649 …1100 pattern  5'b00111: Serdes low frequency pattern  5'b01000: reserved  5'b01001: Serdes PRBS7 p…
26523 …          (0x7<<0) // Clock source select for TX path branch 1 clock :  3'b000 - lnX_clk_i 3'b001-…
26527 …           (0x7<<4) // Clock source select for TX path branch 2 clock : 3'b000 - lnX_clk_i 3'b001-…
26532 …           (0x7<<0) // Clock source select for RX path branch 1 clock : 3'b000 - pma_lX_rxb_iRecov…
26536 …           (0x7<<4) // Clock source select for RX path branch 2 clock : 3'b000 - pma_lX_rxb_iRecov…
26541 …           (0x7<<0) // Clock source select for RX path branch 3 clock : 3'b000 - qd_ck_i 3'b001- p…
26545 …           (0x7<<4) // Clock source select for RX path branch 4 clock : 3'b000 - qd_ck_i 3'b001- p…
37061 …:11] - spare RW register reset by por reset; [10:8] : PCIe Device Type: 3'b000 - Endpoint mode; 3'…
38435 …-3% ~ +0% 1000    +0% ~ +3% 1001 +3% ~ +6% 1010 +6% ~ +9% 1011 +9% ~ +12% 1100 +12% ~ +15% 1101 +1…
43309 …UDP Destination Port 2(outer) 1010 � UDP 1011 � User IP Protocol 1(inner) 1100 � User IP Protocol …
64685 …face.  All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
64702 …face.  All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
64719 …face.  All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.