Lines Matching +full:048 +full:mhz
126 … (0x1<<21) // 66 MHz capable. Not applic…
171 …_66MHZ_CAP_K2 (0x1<<21) // PCI 66MHz Capability.
3589 …ale. 0x0 = 1 ns. 0x1 = 32 ns. 0x2 = 1024 ns. 0x3 = 32,768 ns. 0x4 = 1,048,575 ns. 0x5 = 33,…
5445 …MHz core), then the core actually transmits SKP ordered sets once every 1537 symbol times. The val…
7336 … (0x3ff<<0) // The aux_clk frequency in MHz. This value is used…
7339 …MHz. This value is used to provide a 1 us reference for counting time during low-power states with…
8160 … (0x1f<<0) // Counter of 25 MHz clks for the mininu…
8162 … (0xf<<5) // High 4 bits of the 10 bit-counter of 25 MHz clks for the minimu…
8164 … (0x1f<<9) // Counter of 25 MHz clks for the maximu…
8166 … (0x7f<<14) // Counter of 25 MHz clks for the minimu…
8170 …the version.v b00 : lfclk = 25 MHz (default and compatible with older cores) b01 : lfclk = 50 MHz…
8172 … (0x3f<<24) // Low 6 bits of the 10 bit-counter of 25 MHz clks for the minimu…
8179 … (0x3f<<0) // Number of clocks at 25 MHz to delay between th…
8183 … (0x3f<<8) // Number of clocks at 25 MHz to delay between as…
9293 … (0x1<<21) // 66 MHz capable. Not applic…
9338 …G_FAST_66MHZ_CAP_K2 (0x1<<21) // PCI 66MHz Capability.
14398 …ded by the divider setting. For example, the output clock will be 805.66406MHz for the DIV32 setti…
36664 …and main clk are asynchronous and sync FIFOs should be used. (clk_nw = 425 MHz); 0: clk_nw and ma…
37060 … register reset by core reset. Bit[0]: used for VCCMIN control to select 25MHz clock on XMAC; UMAC…
37087 …manual setting has affect when bit 0 = 1: 0-select USPLL clock; 1-select 25Mhz (ref clock); Reset …
37150 … The default value of 0x6C results in 115200 baud operation with CK25 at 25MHz. Baud Rate 2400 …
37152 … The default value of 0xD9 results in 115200 baud operation with CK25 at 25MHz. Baud Rate 2400 …
37878 …ange 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 =…
37884 …aWidth:0x4 // XTAL core current control 4'b0010: 27Mhz 4'b0100: 50Mhz Device will be using 50Mh…
37890 … XTAL core Highpass Filter Corner Frequency control 0: 27Mhz 1: 50Mhz Device will be using 50Mhz c…
37909 …ange 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 =…
37965 …ange 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 =…
38003 …MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or pos…
38006 …MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or pos…
38036 …MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or pos…
38038 …MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or pos…
38069 …Cnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first m…
38077 …Cnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first m…
38084 …Cnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first m…
38454 … of alternate clock. This lowers the overall power consumption. 1: Select 1Mhz Clock 0: Select 500…
38460 …Cnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first m…
38740 …h for every 15 clock pulses. So for a clock rate of 375Mhz, the effective frequency will be 25Mhz.…
38741 …h for every 15 clock pulses. So for a clock rate of 375Mhz, the effective frequency will be 25Mhz.…
38742 …h for every 15 clock pulses. So for a clock rate of 375Mhz, the effective frequency will be 25Mhz.…
38743 …h for every 15 clock pulses. So for a clock rate of 375Mhz, the effective frequency will be 25Mhz.…
41359 … 0x102b68UL //Access:RW DataWidth:0x8 // The number of 25MHz clock cycles per TC…
42255 …RW DataWidth:0x10 // The value of ReleaseTmr in system clock cycles (25MHz). Each expiration w…
42256 …taWidth:0x10 // The number of cycles in each tick of the timer. Clock 25 MHz. value must be bigg…
44270 …default blink period of approximately 16Hz for the 375Mhz clock (used in 10G/40G modes). For 425Mh…
46249 …. Round trip measurement of latest request that was measured. Measured in clk_pci cycles (375 MHz).
46250 …value from the time rmm_enable register was written with '1'. Measured in clk_pci cycles (375 MHz).
46251 …value from the time rmm_enable register was written with '1'. Measured in clk_pci cycles (375 MHz).
49755 …0x2c0448UL //Access:RW DataWidth:0x12 // The number of clock cycles (25MHz clock) for each tim…
51571 … 0x2f2ec8UL //Access:RW DataWidth:0x20 // The RL timeout period in 25Mhz clock cycles for th…
51572 … 0x2f2eccUL //Access:RW DataWidth:0x20 // The RL timeout period in 25Mhz clock cycles for th…
51573 …ed0UL //Access:RW DataWidth:0x20 // The RL timeout period counter in 25Mhz clock cycles for th…
51574 …ed4UL //Access:RW DataWidth:0x20 // The RL timeout period counter in 25Mhz clock cycles for th…
51596 … 0x2f4c1cUL //Access:RW DataWidth:0x20 // The RL timeout period in 25Mhz clock cycles for th…
51597 …c20UL //Access:RW DataWidth:0x20 // The RL timeout period counter in 25Mhz clock cycles for th…
60156 …0 // Increment PERIOD for the BRB interface rate limiter - in term of 25MHz clock cycles. Note…
60200 …dth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note…
60201 …dth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note…
60202 …dth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note…
60203 …dth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note…
60204 …dth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note…
60205 …dth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note…
60206 …dth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note…
60207 …dth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note…
60397 … is set for XOFF time of 0x8000, data rate of 10Gbps, and core clock of 375MHz, with 64 deducted f…
60584 …idth:0x20 // Increment PERIOD for the global rate limiter - in term of 25MHz clock cycles. Note…
66128 … (0x1f<<0) // Sets phy_ctrl_refclk_i used for CMU0 0x09 - refclk is 257.8125Mhz