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2 * Copyright (c) 2017-2018 Cavium, Inc.
60 u32 crc; /* 32-bit CRC */
128 {"TIM1", "-tim1", NVM_TYPE_TIM1},
129 {"TIM2", "-tim2", NVM_TYPE_TIM2},
130 {"MIM1", "-mim1", NVM_TYPE_MIM1},
131 {"MIM2", "-mim2", NVM_TYPE_MIM2},
132 {"MBA", "-mba", NVM_TYPE_MBA},
133 {"OPT_MODULES", "-optm", NVM_TYPE_MODULES_PN},
134 {"VPD", "-vpd", NVM_TYPE_VPD},
135 {"MFW_TRACE1", "-mfwt1", NVM_TYPE_MFW_TRACE1},
136 {"MFW_TRACE2", "-mfwt2", NVM_TYPE_MFW_TRACE2},
137 {"NVM_CFG1", "-cfg", NVM_TYPE_NVM_CFG1},
138 {"L2B", "-l2b", NVM_TYPE_L2B},
139 {"DIR1", "-dir1", NVM_TYPE_DIR1},
140 {"EAGLE_FW1", "-eagle1", NVM_TYPE_EAGLE_FW1},
141 {"FALCON_FW1", "-falcon1", NVM_TYPE_FALCON_FW1},
142 {"PCIE_FW1", "-pcie1", NVM_TYPE_PCIE_FW1},
143 {"HW_SET", "-hw_set", NVM_TYPE_HW_SET},
144 {"LIM", "-lim", NVM_TYPE_LIM},
145 {"AVS_FW1", "-avs1", NVM_TYPE_AVS_FW1},
146 {"DIR2", "-dir2", NVM_TYPE_DIR2},
147 {"CCM", "-ccm", NVM_TYPE_CCM},
148 {"EAGLE_FW2", "-eagle2", NVM_TYPE_EAGLE_FW2},
149 {"FALCON_FW2", "-falcon2", NVM_TYPE_FALCON_FW2},
150 {"PCIE_FW2", "-pcie2", NVM_TYPE_PCIE_FW2},
151 {"AVS_FW2", "-avs2", NVM_TYPE_AVS_FW2},
152 {"INIT_HW", "-init_hw", NVM_TYPE_INIT_HW},
153 {"DEFAULT_CFG", "-def_cfg", NVM_TYPE_DEFAULT_CFG},
154 {"CRASH_DUMP", "-mdump", NVM_TYPE_MDUMP},
155 {"META", "-meta", NVM_TYPE_NVM_META},
156 {"ISCSI_CFG", "-iscsi_cfg", NVM_TYPE_ISCSI_CFG},
157 {"FCOE_CFG", "-fcoe_cfg",NVM_TYPE_FCOE_CFG},
158 {"ETH_PHY_FW1", "-ethphy1", NVM_TYPE_ETH_PHY_FW1},
159 {"ETH_PHY_FW2", "-ethphy2", NVM_TYPE_ETH_PHY_FW2},
160 {"BDN", "-bdn", NVM_TYPE_BDN},
161 {"PK", "-pk", NVM_TYPE_PUB_KEY},
162 {"RECOVERY", "-recovery",NVM_TYPE_RECOVERY},
163 {"PLDM", "-pldm", NVM_TYPE_PLDM},
164 {"UPK1", "-upk1", NVM_TYPE_UPK1},
165 {"UPK2", "-upk2", NVM_TYPE_UPK2},
166 {"ROMTEST", "-romtest" ,NVM_TYPE_ROM_TEST},
167 {"MASTER_KC", "-kc" ,NVM_TYPE_MASTER_KC},
175 /* Note: The has given 150 possible entries since anyway each file captures at least one page. */
199 #define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + (_num_images - 1) * sizeof(struct nvm_c…
221 #define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE) /* 4Kb */
222 #define LEGACY_ASIC_MIM_MAX_SIZE (_KB(1200)) /* 1.2Mb - E4*/
223 #define NG_ASIC_MIM_MAX_SIZE (_MB(2)) /* 2Mb - E5 */
225 #define FPGA_MIM_MAX_SIZE (0x3E000) /* 250Kb */
227 /* Each image must start on its own page. Bootstrap and LIM are bound together, so they can share t…
228 …* The LIM itself should be very small, so limit it to 8Kb, but in order to open a new page, we dec…
230 #define LIM_MAX_SIZE ((2*FLASH_PAGE_SIZE) - sizeof(struct legacy_bootstrap_region) - NVM_RSV_SI…
240 #define E5_BACKUP_KEY_CHAIN_ADDR ((0x20000 << (REG_READ(0, MCP_REG_NVM_CFG4) & 0x7)) - 0x1000)
244 u8 page[FLASH_PAGE_SIZE]; member
248 …* +-------------------+ 0x000000 * +-------------------+ 0x000000 …
255 …* +-------------------+ 0x000014 * | | …
257 …* +-------------------+ 0x000040 * +-------------------+ 0x001000 …
259 …* +-------------------+ 0x002000 * +-------------------+ 0x002000 …
261 …* +-------------------+ 0x003000 * +-------------------+ 0x003000 …
263 …* +-------------------+ 0x004000 * +-------------------+ 0x004000 …
265 …* +-------------------+ 0x130000 * +-------------------+ 0x130000 …
267 …* +-------------------+ 0x25C000 * +-------------------+ 0x25C000 …
275 …* | optic_modules | * +-------------------+ Flash end - 0x1000 …
277 …* +-------------------+ 0x400000 * +-------------------+ Flash end …
291 #define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image*)0)->f))))
297 #define PCI_REG_TYPE 4
305 #define RMW_CLR_OP 4
315 #define PERSET_ASSERT (1 << 4)