Lines Matching +full:0 +full:x00018000

43 #define NVM_CFG_version 0x83306
54 		#define NVM_CFG_MAC_ADDRESS_HI_MASK                             0x0000FFFF
55 		#define NVM_CFG_MAC_ADDRESS_HI_OFFSET                           0
64 	u32 generic_cont0;                                                  /* 0x0 */
65 		#define NVM_CFG1_GLOB_BOARD_SWAP_MASK                           0x0000000F
66 		#define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET                         0
67 		#define NVM_CFG1_GLOB_BOARD_SWAP_NONE                           0x0
68 		#define NVM_CFG1_GLOB_BOARD_SWAP_PATH                           0x1
69 		#define NVM_CFG1_GLOB_BOARD_SWAP_PORT                           0x2
70 		#define NVM_CFG1_GLOB_BOARD_SWAP_BOTH                           0x3
71 		#define NVM_CFG1_GLOB_MF_MODE_MASK                              0x00000FF0
73 		#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED                        0x0
74 		#define NVM_CFG1_GLOB_MF_MODE_DEFAULT                           0x1
75 		#define NVM_CFG1_GLOB_MF_MODE_SPIO4                             0x2
76 		#define NVM_CFG1_GLOB_MF_MODE_NPAR1_0                           0x3
77 		#define NVM_CFG1_GLOB_MF_MODE_NPAR1_5                           0x4
78 		#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0                           0x5
79 		#define NVM_CFG1_GLOB_MF_MODE_BD                                0x6
80 		#define NVM_CFG1_GLOB_MF_MODE_UFP                               0x7
81 		#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK              0x00001000
83 		#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED          0x0
84 		#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED           0x1
85 		#define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK                       0x001FE000
87 		#define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK                      0x1FE00000
89 		#define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK                         0x20000000
91 		#define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED                     0x0
92 		#define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED                      0x1
93 		#define NVM_CFG1_GLOB_ENABLE_ATC_MASK                           0x40000000
95 		#define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED                       0x0
96 		#define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED                        0x1
97 		#define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_MASK       0x80000000
99 		#define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_DISABLED   0x0
100 		#define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_ENABLED    0x1
101 	u32 engineering_change[3];                                          /* 0x4 */
102 	u32 manufacturing_id;                                              /* 0x10 */
103 	u32 serial_number[4];                                              /* 0x14 */
104 	u32 pcie_cfg;                                                      /* 0x24 */
105 		#define NVM_CFG1_GLOB_PCI_GEN_MASK                              0x00000003
106 		#define NVM_CFG1_GLOB_PCI_GEN_OFFSET                            0
107 		#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1                          0x0
108 		#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2                          0x1
109 		#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3                          0x2
110 		#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK                   0x00000004
112 		#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED               0x0
113 		#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED                0x1
114 		#define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK                         0x00000018
116 		#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED               0x0
117 		#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED                 0x1
118 		#define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED                  0x2
119 		#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED              0x3
120 		#define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK     0x00000020
122 		#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK                 0x000003C0
124 		#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK                     0x00001C00
126 		#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW                       0x0
127 		#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB                      0x1
128 		#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB                    0x2
129 		#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB                    0x3
130 		#define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK                     0x001FE000
132 		#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK                     0x1FE00000
134 		#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK                      0x60000000
138 		#define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK        0x80000000
140 	u32 mgmt_traffic;                                                  /* 0x28 */
141 		#define NVM_CFG1_GLOB_RESERVED60_MASK                           0x00000001
142 		#define NVM_CFG1_GLOB_RESERVED60_OFFSET                         0
143 		#define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK                     0x000001FE
145 		#define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK                     0x0001FE00
147 		#define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK                        0x01FE0000
149 		#define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK                        0x06000000
151 		#define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED                    0x0
152 		#define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII                        0x1
153 		#define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII                       0x2
154 		#define NVM_CFG1_GLOB_AUX_MODE_MASK                             0x78000000
156 		#define NVM_CFG1_GLOB_AUX_MODE_DEFAULT                          0x0
157 		#define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY                       0x1
159 		#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK              0x80000000
161 		#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED          0x0
162 		#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED           0x1
163 	u32 core_cfg;                                                      /* 0x2C */
164 		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK                    0x000000FF
165 		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET                  0
166 		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G                0x0
167 		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G                   0x1
168 		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G               0x2
169 		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F                 0x3
170 		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E              0x4
171 		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G                0x5
172 		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G                   0xB
173 		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G                   0xC
174 		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G                   0xD
175 		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G                   0xE
176 		#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G                   0xF
177 		#define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK             0x00000100
179 		#define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED         0x0
180 		#define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED          0x1
181 		#define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK             0x00000200
183 		#define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED         0x0
184 		#define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED          0x1
185 		#define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK                      0x0003FC00
187 		#define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK                      0x03FC0000
189 		#define NVM_CFG1_GLOB_AVS_MODE_MASK                             0x1C000000
191 		#define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP                       0x0
192 		#define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG                    0x1
193 		#define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP                    0x2
194 		#define NVM_CFG1_GLOB_AVS_MODE_DISABLED                         0x3
195 		#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK                 0x60000000
197 		#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED             0x0
198 		#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED              0x1
199 		#define NVM_CFG1_GLOB_DCI_SUPPORT_MASK                          0x80000000
201 		#define NVM_CFG1_GLOB_DCI_SUPPORT_DISABLED                      0x0
202 		#define NVM_CFG1_GLOB_DCI_SUPPORT_ENABLED                       0x1
203 	u32 e_lane_cfg1;                                                   /* 0x30 */
204 		#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK                        0x0000000F
205 		#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET                      0
206 		#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK                        0x000000F0
208 		#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK                        0x00000F00
210 		#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK                        0x0000F000
212 		#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK                        0x000F0000
214 		#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK                        0x00F00000
216 		#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK                        0x0F000000
218 		#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK                        0xF0000000
220 	u32 e_lane_cfg2;                                                   /* 0x34 */
221 		#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK                    0x00000001
222 		#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET                  0
223 		#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK                    0x00000002
225 		#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK                    0x00000004
227 		#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK                    0x00000008
229 		#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK                    0x00000010
231 		#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK                    0x00000020
233 		#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK                    0x00000040
235 		#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK                    0x00000080
237 		#define NVM_CFG1_GLOB_SMBUS_MODE_MASK                           0x00000F00
239 		#define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED                       0x0
240 		#define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ                         0x1
241 		#define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ                         0x2
242 		#define NVM_CFG1_GLOB_NCSI_MASK                                 0x0000F000
244 		#define NVM_CFG1_GLOB_NCSI_DISABLED                             0x0
245 		#define NVM_CFG1_GLOB_NCSI_ENABLED                              0x1
247 		#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK                       0x000F0000
249 		#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES                0x0
250 		#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE                     0x1
251 		#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES                    0x2
252 		#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES                    0x3
253 		#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES                    0x4
255 		#define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK                         0x00300000
257 		#define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED                       0x0
258 		#define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY          0x1
259 		#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK                  0x01C00000
261 		#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED              0x0
262 		#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C           0x1
263 		#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY              0x2
264 		#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS         0x3
265 		#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK          0x06000000
267 		#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE       0x0
268 		#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL      0x1
269 		#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL      0x2
270 		#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH          0x3
272 		#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK                     0x38000000
274 		#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL                 0x0
275 		#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL                 0x1
276 		#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH                     0x2
278 		#define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_MASK                     0x40000000
280 		#define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_DISABLED                 0x0
281 		#define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_ENABLED                  0x1
283 		#define NVM_CFG1_GLOB_RESET_ON_LAN_MASK                         0x80000000
285 		#define NVM_CFG1_GLOB_RESET_ON_LAN_DISABLED                     0x0
286 		#define NVM_CFG1_GLOB_RESET_ON_LAN_ENABLED                      0x1
287 	u32 f_lane_cfg1;                                                   /* 0x38 */
288 		#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK                        0x0000000F
289 		#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET                      0
290 		#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK                        0x000000F0
292 		#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK                        0x00000F00
294 		#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK                        0x0000F000
296 		#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK                        0x000F0000
298 		#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK                        0x00F00000
300 		#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK                        0x0F000000
302 		#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK                        0xF0000000
304 	u32 f_lane_cfg2;                                                   /* 0x3C */
305 		#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK                    0x00000001
306 		#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET                  0
307 		#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK                    0x00000002
309 		#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK                    0x00000004
311 		#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK                    0x00000008
313 		#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK                    0x00000010
315 		#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK                    0x00000020
317 		#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK                    0x00000040
319 		#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK                    0x00000080
322 		#define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK    0x0000FF00
325 		#define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK       0x00FF0000
328 		#define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK             0xFF000000
330 	u32 mps10_preemphasis;                                             /* 0x40 */
331 		#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK                         0x000000FF
332 		#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET                       0
333 		#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK                         0x0000FF00
335 		#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK                         0x00FF0000
337 		#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK                         0xFF000000
339 	u32 mps10_driver_current;                                          /* 0x44 */
340 		#define NVM_CFG1_GLOB_LANE0_AMP_MASK                            0x000000FF
341 		#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET                          0
342 		#define NVM_CFG1_GLOB_LANE1_AMP_MASK                            0x0000FF00
344 		#define NVM_CFG1_GLOB_LANE2_AMP_MASK                            0x00FF0000
346 		#define NVM_CFG1_GLOB_LANE3_AMP_MASK                            0xFF000000
348 	u32 mps25_preemphasis;                                             /* 0x48 */
349 		#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK                         0x000000FF
350 		#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET                       0
351 		#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK                         0x0000FF00
353 		#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK                         0x00FF0000
355 		#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK                         0xFF000000
357 	u32 mps25_driver_current;                                          /* 0x4C */
358 		#define NVM_CFG1_GLOB_LANE0_AMP_MASK                            0x000000FF
359 		#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET                          0
360 		#define NVM_CFG1_GLOB_LANE1_AMP_MASK                            0x0000FF00
362 		#define NVM_CFG1_GLOB_LANE2_AMP_MASK                            0x00FF0000
364 		#define NVM_CFG1_GLOB_LANE3_AMP_MASK                            0xFF000000
366 	u32 pci_id;                                                        /* 0x50 */
367 		#define NVM_CFG1_GLOB_VENDOR_ID_MASK                            0x0000FFFF
368 		#define NVM_CFG1_GLOB_VENDOR_ID_OFFSET                          0
370 		#define NVM_CFG1_GLOB_DEAD_TEMP_TH_TEMPERATURE_MASK             0x00FF0000
373 		#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK      0xFF000000
375 	u32 pci_subsys_id;                                                 /* 0x54 */
376 		#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK                  0x0000FFFF
377 		#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET                0
378 		#define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK                  0xFFFF0000
380 	u32 bar;                                                           /* 0x58 */
381 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK                   0x0000000F
382 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET                 0
383 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED               0x0
384 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K                     0x1
385 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K                     0x2
386 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K                     0x3
387 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K                    0x4
388 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K                    0x5
389 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K                    0x6
390 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K                   0x7
391 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K                   0x8
392 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K                   0x9
393 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M                     0xA
394 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M                     0xB
395 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M                     0xC
396 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M                     0xD
397 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M                    0xE
398 		#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M                    0xF
400 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK                     0x000000F0
402 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED                 0x0
403 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K                       0x1
404 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K                       0x2
405 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K                      0x3
406 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K                      0x4
407 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K                      0x5
408 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K                     0x6
409 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K                     0x7
410 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K                     0x8
411 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M                       0x9
412 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M                       0xA
413 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M                       0xB
414 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M                       0xC
415 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M                      0xD
416 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M                      0xE
417 		#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M                      0xF
419 		#define NVM_CFG1_GLOB_BAR2_SIZE_MASK                            0x00000F00
421 		#define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED                        0x0
422 		#define NVM_CFG1_GLOB_BAR2_SIZE_64K                             0x1
423 		#define NVM_CFG1_GLOB_BAR2_SIZE_128K                            0x2
424 		#define NVM_CFG1_GLOB_BAR2_SIZE_256K                            0x3
425 		#define NVM_CFG1_GLOB_BAR2_SIZE_512K                            0x4
426 		#define NVM_CFG1_GLOB_BAR2_SIZE_1M                              0x5
427 		#define NVM_CFG1_GLOB_BAR2_SIZE_2M                              0x6
428 		#define NVM_CFG1_GLOB_BAR2_SIZE_4M                              0x7
429 		#define NVM_CFG1_GLOB_BAR2_SIZE_8M                              0x8
430 		#define NVM_CFG1_GLOB_BAR2_SIZE_16M                             0x9
431 		#define NVM_CFG1_GLOB_BAR2_SIZE_32M                             0xA
432 		#define NVM_CFG1_GLOB_BAR2_SIZE_64M                             0xB
433 		#define NVM_CFG1_GLOB_BAR2_SIZE_128M                            0xC
434 		#define NVM_CFG1_GLOB_BAR2_SIZE_256M                            0xD
435 		#define NVM_CFG1_GLOB_BAR2_SIZE_512M                            0xE
436 		#define NVM_CFG1_GLOB_BAR2_SIZE_1G                              0xF
439 		#define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK                 0x0000F000
443 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK                    0x00FF0000
445 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED                0x0
446 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K                     0x1
447 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K                    0x2
448 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K                    0x3
449 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K                    0x4
450 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M                      0x5
451 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M                      0x6
452 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M                      0x7
453 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M                      0x8
454 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M                     0x9
455 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M                     0xA
456 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M                     0xB
457 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M                    0xC
458 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M                    0xD
459 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M                    0xE
460 		#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G                      0xF
462 		#define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK            0xFF000000
464 	u32 mps10_txfir_main;                                              /* 0x5C */
465 		#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK                     0x000000FF
466 		#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET                   0
467 		#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK                     0x0000FF00
469 		#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK                     0x00FF0000
471 		#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK                     0xFF000000
473 	u32 mps10_txfir_post;                                              /* 0x60 */
474 		#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK                     0x000000FF
475 		#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET                   0
476 		#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK                     0x0000FF00
478 		#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK                     0x00FF0000
480 		#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK                     0xFF000000
482 	u32 mps25_txfir_main;                                              /* 0x64 */
483 		#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK                     0x000000FF
484 		#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET                   0
485 		#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK                     0x0000FF00
487 		#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK                     0x00FF0000
489 		#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK                     0xFF000000
491 	u32 mps25_txfir_post;                                              /* 0x68 */
492 		#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK                     0x000000FF
493 		#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET                   0
494 		#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK                     0x0000FF00
496 		#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK                     0x00FF0000
498 		#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK                     0xFF000000
500 	u32 manufacture_ver;                                               /* 0x6C */
501 		#define NVM_CFG1_GLOB_MANUF0_VER_MASK                           0x0000003F
502 		#define NVM_CFG1_GLOB_MANUF0_VER_OFFSET                         0
503 		#define NVM_CFG1_GLOB_MANUF1_VER_MASK                           0x00000FC0
505 		#define NVM_CFG1_GLOB_MANUF2_VER_MASK                           0x0003F000
507 		#define NVM_CFG1_GLOB_MANUF3_VER_MASK                           0x00FC0000
509 		#define NVM_CFG1_GLOB_MANUF4_VER_MASK                           0x3F000000
512 		#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_MASK                   0x40000000
514 		#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_NVRAM                  0x0
515 		#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_IO_PINS                0x1
516 		#define NVM_CFG1_GLOB_RECOVERY_MODE_MASK                        0x80000000
518 		#define NVM_CFG1_GLOB_RECOVERY_MODE_DISABLED                    0x0
519 		#define NVM_CFG1_GLOB_RECOVERY_MODE_ENABLED                     0x1
520 	u32 manufacture_time;                                              /* 0x70 */
521 		#define NVM_CFG1_GLOB_MANUF0_TIME_MASK                          0x0000003F
522 		#define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET                        0
523 		#define NVM_CFG1_GLOB_MANUF1_TIME_MASK                          0x00000FC0
525 		#define NVM_CFG1_GLOB_MANUF2_TIME_MASK                          0x0003F000
528 		#define NVM_CFG1_GLOB_MAX_MSIX_MASK                             0x03FC0000
531 		#define NVM_CFG1_GLOB_PF_MAPPING_MASK                           0x0C000000
533 		#define NVM_CFG1_GLOB_PF_MAPPING_CONTINUOUS                     0x0
534 		#define NVM_CFG1_GLOB_PF_MAPPING_FIXED                          0x1
535 		#define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_MASK               0x30000000
537 		#define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_DISABLED           0x0
538 		#define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_TI                 0x1
540 		#define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_MASK                0x40000000
542 		#define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_DISABLED            0x0
543 		#define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_ENABLED             0x1
544 	u32 led_global_settings;                                           /* 0x74 */
545 		#define NVM_CFG1_GLOB_LED_SWAP_0_MASK                           0x0000000F
546 		#define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET                         0
547 		#define NVM_CFG1_GLOB_LED_SWAP_1_MASK                           0x000000F0
549 		#define NVM_CFG1_GLOB_LED_SWAP_2_MASK                           0x00000F00
551 		#define NVM_CFG1_GLOB_LED_SWAP_3_MASK                           0x0000F000
554 		#define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_MASK              0x00FF0000
558 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_MASK               0xFF000000
560 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_NA                 0x0
561 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO0              0x1
562 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO1              0x2
563 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO2              0x3
564 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO3              0x4
565 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO4              0x5
566 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO5              0x6
567 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO6              0x7
568 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO7              0x8
569 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO8              0x9
570 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO9              0xA
571 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO10             0xB
572 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO11             0xC
573 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO12             0xD
574 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO13             0xE
575 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO14             0xF
576 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO15             0x10
577 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO16             0x11
578 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO17             0x12
579 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO18             0x13
580 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO19             0x14
581 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO20             0x15
582 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO21             0x16
583 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO22             0x17
584 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO23             0x18
585 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO24             0x19
586 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO25             0x1A
587 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO26             0x1B
588 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO27             0x1C
589 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO28             0x1D
590 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO29             0x1E
591 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO30             0x1F
592 		#define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO31             0x20
593 	u32 generic_cont1;                                                 /* 0x78 */
594 		#define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK                         0x000003FF
595 		#define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET                       0
596 		#define NVM_CFG1_GLOB_LANE0_SWAP_MASK                           0x00000C00
598 		#define NVM_CFG1_GLOB_LANE1_SWAP_MASK                           0x00003000
600 		#define NVM_CFG1_GLOB_LANE2_SWAP_MASK                           0x0000C000
602 		#define NVM_CFG1_GLOB_LANE3_SWAP_MASK                           0x00030000
605 		#define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_MASK           0x00040000
607 		#define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_DISABLED       0x0
608 		#define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_ENABLED        0x1
610 		#define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_MASK                    0x00780000
614 		#define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_MASK               0x01800000
616 		#define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_MASK               0x06000000
618 		#define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_MASK               0x18000000
620 		#define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_MASK               0x60000000
622 	u32 mbi_version;                                                   /* 0x7C */
623 		#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK                        0x000000FF
624 		#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET                      0
625 		#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK                        0x0000FF00
627 		#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK                        0x00FF0000
629 	/*  If set to other than NA, 0 - Normal operation, 1 - Thermal event
631 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_MASK                   0xFF000000
633 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_NA                     0x0
634 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO0                  0x1
635 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO1                  0x2
636 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO2                  0x3
637 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO3                  0x4
638 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO4                  0x5
639 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO5                  0x6
640 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO6                  0x7
641 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO7                  0x8
642 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO8                  0x9
643 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO9                  0xA
644 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO10                 0xB
645 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO11                 0xC
646 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO12                 0xD
647 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO13                 0xE
648 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO14                 0xF
649 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO15                 0x10
650 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO16                 0x11
651 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO17                 0x12
652 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO18                 0x13
653 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO19                 0x14
654 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO20                 0x15
655 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO21                 0x16
656 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO22                 0x17
657 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO23                 0x18
658 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO24                 0x19
659 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO25                 0x1A
660 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO26                 0x1B
661 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO27                 0x1C
662 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO28                 0x1D
663 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO29                 0x1E
664 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO30                 0x1F
665 		#define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO31                 0x20
666 	u32 mbi_date;                                                      /* 0x80 */
667 	u32 misc_sig;                                                      /* 0x84 */
669 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK                   0x000000FF
670 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET                 0
671 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK                   0x0000FF00
673 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA                      0x0
674 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0                   0x1
675 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1                   0x2
676 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2                   0x3
677 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3                   0x4
678 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4                   0x5
679 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5                   0x6
680 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6                   0x7
681 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7                   0x8
682 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8                   0x9
683 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9                   0xA
684 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10                  0xB
685 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11                  0xC
686 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12                  0xD
687 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13                  0xE
688 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14                  0xF
689 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15                  0x10
690 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16                  0x11
691 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17                  0x12
692 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18                  0x13
693 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19                  0x14
694 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20                  0x15
695 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21                  0x16
696 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22                  0x17
697 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23                  0x18
698 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24                  0x19
699 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25                  0x1A
700 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26                  0x1B
701 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27                  0x1C
702 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28                  0x1D
703 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29                  0x1E
704 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30                  0x1F
705 		#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31                  0x20
708            0 = Interrupt event occurred
711 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_MASK                   0x00FF0000
713 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_NA                     0x0
714 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO0                  0x1
715 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO1                  0x2
716 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO2                  0x3
717 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO3                  0x4
718 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO4                  0x5
719 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO5                  0x6
720 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO6                  0x7
721 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO7                  0x8
722 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO8                  0x9
723 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO9                  0xA
724 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO10                 0xB
725 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO11                 0xC
726 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO12                 0xD
727 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO13                 0xE
728 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO14                 0xF
729 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO15                 0x10
730 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO16                 0x11
731 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO17                 0x12
732 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO18                 0x13
733 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO19                 0x14
734 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO20                 0x15
735 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO21                 0x16
736 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO22                 0x17
737 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO23                 0x18
738 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO24                 0x19
739 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO25                 0x1A
740 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO26                 0x1B
741 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO27                 0x1C
742 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO28                 0x1D
743 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO29                 0x1E
744 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO30                 0x1F
745 		#define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO31                 0x20
747 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_MASK                 0xFF000000
749 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_NA                   0x0
750 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO0                0x1
751 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO1                0x2
752 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO2                0x3
753 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO3                0x4
754 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO4                0x5
755 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO5                0x6
756 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO6                0x7
757 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO7                0x8
758 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO8                0x9
759 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO9                0xA
760 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO10               0xB
761 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO11               0xC
762 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO12               0xD
763 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO13               0xE
764 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO14               0xF
765 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO15               0x10
766 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO16               0x11
767 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO17               0x12
768 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO18               0x13
769 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO19               0x14
770 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO20               0x15
771 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO21               0x16
772 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO22               0x17
773 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO23               0x18
774 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO24               0x19
775 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO25               0x1A
776 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO26               0x1B
777 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO27               0x1C
778 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO28               0x1D
779 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO29               0x1E
780 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO30               0x1F
781 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO31               0x20
782 	u32 device_capabilities;                                           /* 0x88 */
783 		#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET              0x1
784 		#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE                  0x2
785 		#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI                 0x4
786 		#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE                  0x8
787 		#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP                 0x10
788 	u32 power_dissipated;                                              /* 0x8C */
789 		#define NVM_CFG1_GLOB_POWER_DIS_D0_MASK                         0x000000FF
790 		#define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET                       0
791 		#define NVM_CFG1_GLOB_POWER_DIS_D1_MASK                         0x0000FF00
793 		#define NVM_CFG1_GLOB_POWER_DIS_D2_MASK                         0x00FF0000
795 		#define NVM_CFG1_GLOB_POWER_DIS_D3_MASK                         0xFF000000
797 	u32 power_consumed;                                                /* 0x90 */
798 		#define NVM_CFG1_GLOB_POWER_CONS_D0_MASK                        0x000000FF
799 		#define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET                      0
800 		#define NVM_CFG1_GLOB_POWER_CONS_D1_MASK                        0x0000FF00
802 		#define NVM_CFG1_GLOB_POWER_CONS_D2_MASK                        0x00FF0000
804 		#define NVM_CFG1_GLOB_POWER_CONS_D3_MASK                        0xFF000000
806 	u32 efi_version;                                                   /* 0x94 */
807 	u32 multi_network_modes_capability;                                /* 0x98 */
808 		#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G      0x1
809 		#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G      0x2
810 		#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G      0x4
811 		#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G      0x8
812 		#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G      0x10
813 		#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G      0x20
814 		#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G      0x40
815 		#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G  0x80
816 		#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G      0x100
817 	u32 nvm_cfg_version;                                               /* 0x9C */
818 	u32 nvm_cfg_new_option_seq;                                        /* 0xA0 */
819 	u32 nvm_cfg_removed_option_seq;                                    /* 0xA4 */
820 	u32 nvm_cfg_updated_value_seq;                                     /* 0xA8 */
821 	u32 extended_serial_number[8];                                     /* 0xAC */
822 	u32 oem1_number[8];                                                /* 0xCC */
823 	u32 oem2_number[8];                                                /* 0xEC */
824 	u32 mps25_active_txfir_pre;                                       /* 0x10C */
825 		#define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_MASK                  0x000000FF
826 		#define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_OFFSET                0
827 		#define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_MASK                  0x0000FF00
829 		#define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_MASK                  0x00FF0000
831 		#define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_MASK                  0xFF000000
833 	u32 mps25_active_txfir_main;                                      /* 0x110 */
834 		#define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_MASK                 0x000000FF
835 		#define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_OFFSET               0
836 		#define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_MASK                 0x0000FF00
838 		#define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_MASK                 0x00FF0000
840 		#define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_MASK                 0xFF000000
842 	u32 mps25_active_txfir_post;                                      /* 0x114 */
843 		#define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_MASK                 0x000000FF
844 		#define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_OFFSET               0
845 		#define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_MASK                 0x0000FF00
847 		#define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_MASK                 0x00FF0000
849 		#define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_MASK                 0xFF000000
851 	u32 features;                                                     /* 0x118 */
853 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_MASK                0x000000FF
854 		#define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_OFFSET              0
856 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_MASK                         0x0000FF00
858 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_NA                           0x0
859 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO0                        0x1
860 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO1                        0x2
861 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO2                        0x3
862 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO3                        0x4
863 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO4                        0x5
864 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO5                        0x6
865 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO6                        0x7
866 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO7                        0x8
867 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO8                        0x9
868 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO9                        0xA
869 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO10                       0xB
870 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO11                       0xC
871 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO12                       0xD
872 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO13                       0xE
873 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO14                       0xF
874 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO15                       0x10
875 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO16                       0x11
876 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO17                       0x12
877 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO18                       0x13
878 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO19                       0x14
879 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO20                       0x15
880 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO21                       0x16
881 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO22                       0x17
882 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO23                       0x18
883 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO24                       0x19
884 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO25                       0x1A
885 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO26                       0x1B
886 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO27                       0x1C
887 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO28                       0x1D
888 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO29                       0x1E
889 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO30                       0x1F
890 		#define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO31                       0x20
892 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_MASK                       0x00FF0000
894 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_NA                         0x0
895 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO0                      0x1
896 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO1                      0x2
897 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO2                      0x3
898 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO3                      0x4
899 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO4                      0x5
900 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO5                      0x6
901 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO6                      0x7
902 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO7                      0x8
903 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO8                      0x9
904 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO9                      0xA
905 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO10                     0xB
906 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO11                     0xC
907 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO12                     0xD
908 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO13                     0xE
909 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO14                     0xF
910 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO15                     0x10
911 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO16                     0x11
912 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO17                     0x12
913 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO18                     0x13
914 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO19                     0x14
915 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO20                     0x15
916 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO21                     0x16
917 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO22                     0x17
918 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO23                     0x18
919 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO24                     0x19
920 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO25                     0x1A
921 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO26                     0x1B
922 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO27                     0x1C
923 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO28                     0x1D
924 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO29                     0x1E
925 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO30                     0x1F
926 		#define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO31                     0x20
928 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_MASK                       0xFF000000
930 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_NA                         0x0
931 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO0                      0x1
932 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO1                      0x2
933 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO2                      0x3
934 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO3                      0x4
935 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO4                      0x5
936 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO5                      0x6
937 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO6                      0x7
938 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO7                      0x8
939 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO8                      0x9
940 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO9                      0xA
941 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO10                     0xB
942 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO11                     0xC
943 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO12                     0xD
944 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO13                     0xE
945 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO14                     0xF
946 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO15                     0x10
947 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO16                     0x11
948 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO17                     0x12
949 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO18                     0x13
950 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO19                     0x14
951 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO20                     0x15
952 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO21                     0x16
953 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO22                     0x17
954 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO23                     0x18
955 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO24                     0x19
956 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO25                     0x1A
957 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO26                     0x1B
958 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO27                     0x1C
959 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO28                     0x1D
960 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO29                     0x1E
961 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO30                     0x1F
962 		#define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO31                     0x20
963 	u32 tx_rx_eq_25g_hlpc;                                            /* 0x11C */
964 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_MASK             0x000000FF
965 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_OFFSET           0
966 		#define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_MASK             0x0000FF00
968 		#define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_MASK             0x00FF0000
970 		#define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_MASK             0xFF000000
972 	u32 tx_rx_eq_25g_llpc;                                            /* 0x120 */
973 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_MASK             0x000000FF
974 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_OFFSET           0
975 		#define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_MASK             0x0000FF00
977 		#define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_MASK             0x00FF0000
979 		#define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_MASK             0xFF000000
981 	u32 tx_rx_eq_25g_ac;                                              /* 0x124 */
982 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_MASK               0x000000FF
983 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_OFFSET             0
984 		#define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_MASK               0x0000FF00
986 		#define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_MASK               0x00FF0000
988 		#define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_MASK               0xFF000000
990 	u32 tx_rx_eq_10g_pc;                                              /* 0x128 */
991 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_MASK               0x000000FF
992 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_OFFSET             0
993 		#define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_MASK               0x0000FF00
995 		#define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_MASK               0x00FF0000
997 		#define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_MASK               0xFF000000
999 	u32 tx_rx_eq_10g_ac;                                              /* 0x12C */
1000 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_MASK               0x000000FF
1001 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_OFFSET             0
1002 		#define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_MASK               0x0000FF00
1004 		#define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_MASK               0x00FF0000
1006 		#define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_MASK               0xFF000000
1008 	u32 tx_rx_eq_1g;                                                  /* 0x130 */
1009 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_MASK                   0x000000FF
1010 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_OFFSET                 0
1011 		#define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_MASK                   0x0000FF00
1013 		#define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_MASK                   0x00FF0000
1015 		#define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_MASK                   0xFF000000
1017 	u32 tx_rx_eq_25g_bt;                                              /* 0x134 */
1018 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_MASK               0x000000FF
1019 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_OFFSET             0
1020 		#define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_MASK               0x0000FF00
1022 		#define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_MASK               0x00FF0000
1024 		#define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_MASK               0xFF000000
1026 	u32 tx_rx_eq_10g_bt;                                              /* 0x138 */
1027 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_MASK               0x000000FF
1028 		#define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_OFFSET             0
1029 		#define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_MASK               0x0000FF00
1031 		#define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_MASK               0x00FF0000
1033 		#define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_MASK               0xFF000000
1035 	u32 generic_cont4;                                                /* 0x13C */
1036 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_MASK                   0x000000FF
1037 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_OFFSET                 0
1038 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_NA                     0x0
1039 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO0                  0x1
1040 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO1                  0x2
1041 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO2                  0x3
1042 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO3                  0x4
1043 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO4                  0x5
1044 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO5                  0x6
1045 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO6                  0x7
1046 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO7                  0x8
1047 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO8                  0x9
1048 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO9                  0xA
1049 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO10                 0xB
1050 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO11                 0xC
1051 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO12                 0xD
1052 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO13                 0xE
1053 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO14                 0xF
1054 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO15                 0x10
1055 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO16                 0x11
1056 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO17                 0x12
1057 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO18                 0x13
1058 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO19                 0x14
1059 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO20                 0x15
1060 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO21                 0x16
1061 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO22                 0x17
1062 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO23                 0x18
1063 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO24                 0x19
1064 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO25                 0x1A
1065 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO26                 0x1B
1066 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO27                 0x1C
1067 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO28                 0x1D
1068 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29                 0x1E
1069 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30                 0x1F
1070 		#define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31                 0x20
1071 	u32 preboot_debug_mode_std;                                       /* 0x140 */
1072 	u32 preboot_debug_mode_ext;                                       /* 0x144 */
1073 	u32 ext_phy_cfg1;                                                 /* 0x148 */
1075 		#define NVM_CFG1_GLOB_RESERVED_244_MASK                         0x0000FFFF
1076 		#define NVM_CFG1_GLOB_RESERVED_244_OFFSET                       0
1077 	u32 clocks;                                                       /* 0x14C */
1079 		#define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MASK                 0x000000FF
1080 		#define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_OFFSET               0
1081 		#define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_DEFAULT     0x0
1082 		#define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_375         0x1
1083 		#define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_350         0x2
1084 		#define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_325         0x3
1085 		#define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_300         0x4
1086 		#define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_280         0x5
1088 		#define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MASK                  0x0000FF00
1090 		#define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_DEFAULT       0x0
1091 		#define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_782           0x1
1092 		#define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_516           0x2
1094 		#define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_MASK                0x00FF0000
1096 		#define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_DEFAULT   0x0
1097 		#define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1200      0x1
1098 		#define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1000      0x2
1099 		#define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_900       0x3
1100 		#define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1100      0x4
1101 	u32 reserved[54];                                                 /* 0x150 */
1106 	u32 reserved[1];                                                    /* 0x0 */
1111 	u32 reserved__m_relocated_to_option_123;                            /* 0x0 */
1112 	u32 reserved__m_relocated_to_option_124;                            /* 0x4 */
1113 	u32 generic_cont0;                                                  /* 0x8 */
1114 		#define NVM_CFG1_PORT_LED_MODE_MASK                             0x000000FF
1115 		#define NVM_CFG1_PORT_LED_MODE_OFFSET                           0
1116 		#define NVM_CFG1_PORT_LED_MODE_MAC1                             0x0
1117 		#define NVM_CFG1_PORT_LED_MODE_PHY1                             0x1
1118 		#define NVM_CFG1_PORT_LED_MODE_PHY2                             0x2
1119 		#define NVM_CFG1_PORT_LED_MODE_PHY3                             0x3
1120 		#define NVM_CFG1_PORT_LED_MODE_MAC2                             0x4
1121 		#define NVM_CFG1_PORT_LED_MODE_PHY4                             0x5
1122 		#define NVM_CFG1_PORT_LED_MODE_PHY5                             0x6
1123 		#define NVM_CFG1_PORT_LED_MODE_PHY6                             0x7
1124 		#define NVM_CFG1_PORT_LED_MODE_MAC3                             0x8
1125 		#define NVM_CFG1_PORT_LED_MODE_PHY7                             0x9
1126 		#define NVM_CFG1_PORT_LED_MODE_PHY8                             0xA
1127 		#define NVM_CFG1_PORT_LED_MODE_PHY9                             0xB
1128 		#define NVM_CFG1_PORT_LED_MODE_MAC4                             0xC
1129 		#define NVM_CFG1_PORT_LED_MODE_PHY10                            0xD
1130 		#define NVM_CFG1_PORT_LED_MODE_PHY11                            0xE
1131 		#define NVM_CFG1_PORT_LED_MODE_PHY12                            0xF
1132 		#define NVM_CFG1_PORT_LED_MODE_BREAKOUT                         0x10
1133 		#define NVM_CFG1_PORT_ROCE_PRIORITY_MASK                        0x0000FF00
1135 		#define NVM_CFG1_PORT_DCBX_MODE_MASK                            0x000F0000
1137 		#define NVM_CFG1_PORT_DCBX_MODE_DISABLED                        0x0
1138 		#define NVM_CFG1_PORT_DCBX_MODE_IEEE                            0x1
1139 		#define NVM_CFG1_PORT_DCBX_MODE_CEE                             0x2
1140 		#define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC                         0x3
1141 		#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK            0x00F00000
1143 		#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET        0x1
1144 		#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE            0x2
1145 		#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI           0x4
1148 		#define NVM_CFG1_PORT_EXT_PHY_RESET_MASK                        0xFF000000
1150 		#define NVM_CFG1_PORT_EXT_PHY_RESET_NA                          0x0
1151 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO0                       0x1
1152 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO1                       0x2
1153 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO2                       0x3
1154 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO3                       0x4
1155 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO4                       0x5
1156 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO5                       0x6
1157 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO6                       0x7
1158 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO7                       0x8
1159 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO8                       0x9
1160 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO9                       0xA
1161 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO10                      0xB
1162 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO11                      0xC
1163 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO12                      0xD
1164 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO13                      0xE
1165 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO14                      0xF
1166 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO15                      0x10
1167 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO16                      0x11
1168 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO17                      0x12
1169 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO18                      0x13
1170 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO19                      0x14
1171 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO20                      0x15
1172 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO21                      0x16
1173 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO22                      0x17
1174 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO23                      0x18
1175 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO24                      0x19
1176 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO25                      0x1A
1177 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO26                      0x1B
1178 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO27                      0x1C
1179 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO28                      0x1D
1180 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO29                      0x1E
1181 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO30                      0x1F
1182 		#define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO31                      0x20
1183 	u32 pcie_cfg;                                                       /* 0xC */
1184 		#define NVM_CFG1_PORT_RESERVED15_MASK                           0x00000007
1185 		#define NVM_CFG1_PORT_RESERVED15_OFFSET                         0
1186 	u32 features;                                                      /* 0x10 */
1187 		#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK           0x00000001
1188 		#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET         0
1189 		#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED       0x0
1190 		#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED        0x1
1191 		#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK                     0x00000002
1193 		#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED                 0x0
1194 		#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED                  0x1
1195 	u32 speed_cap_mask;                                                /* 0x14 */
1196 		#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK            0x0000FFFF
1197 		#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET          0
1198 		#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G              0x1
1199 		#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G             0x2
1200 		#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G             0x4
1201 		#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G             0x8
1202 		#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G             0x10
1203 		#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G             0x20
1204 		#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G         0x40
1205 		#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK            0xFFFF0000
1207 		#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G              0x1
1208 		#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G             0x2
1209 		#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_20G             0x4
1210 		#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G             0x8
1211 		#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G             0x10
1212 		#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G             0x20
1213 		#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G         0x40
1214 	u32 link_settings;                                                 /* 0x18 */
1215 		#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK                       0x0000000F
1216 		#define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET                     0
1217 		#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG                    0x0
1218 		#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G                         0x1
1219 		#define NVM_CFG1_PORT_DRV_LINK_SPEED_10G                        0x2
1220 		#define NVM_CFG1_PORT_DRV_LINK_SPEED_20G                        0x3
1221 		#define NVM_CFG1_PORT_DRV_LINK_SPEED_25G                        0x4
1222 		#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G                        0x5
1223 		#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G                        0x6
1224 		#define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G                    0x7
1225 		#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK                     0x00000070
1227 		#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG                  0x1
1228 		#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX                       0x2
1229 		#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX                       0x4
1230 		#define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK                       0x00000780
1232 		#define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG                    0x0
1233 		#define NVM_CFG1_PORT_MFW_LINK_SPEED_1G                         0x1
1234 		#define NVM_CFG1_PORT_MFW_LINK_SPEED_10G                        0x2
1235 		#define NVM_CFG1_PORT_MFW_LINK_SPEED_20G                        0x3
1236 		#define NVM_CFG1_PORT_MFW_LINK_SPEED_25G                        0x4
1237 		#define NVM_CFG1_PORT_MFW_LINK_SPEED_40G                        0x5
1238 		#define NVM_CFG1_PORT_MFW_LINK_SPEED_50G                        0x6
1239 		#define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G                    0x7
1240 		#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK                     0x00003800
1242 		#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG                  0x1
1243 		#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX                       0x2
1244 		#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX                       0x4
1245 		#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK      0x00004000
1247 		#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED  0x0
1248 		#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED   0x1
1249 		#define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK                       0x00018000
1251 		#define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM                 0x0
1252 		#define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM                        0x1
1253 		#define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK                       0x000E0000
1255 		#define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE                       0x0
1256 		#define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE                   0x1
1257 		#define NVM_CFG1_PORT_FEC_FORCE_MODE_RS                         0x2
1258 		#define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO                       0x7
1259 		#define NVM_CFG1_PORT_FEC_AN_MODE_MASK                          0x00700000
1261 		#define NVM_CFG1_PORT_FEC_AN_MODE_NONE                          0x0
1262 		#define NVM_CFG1_PORT_FEC_AN_MODE_10G_FIRECODE                  0x1
1263 		#define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE                  0x2
1264 		#define NVM_CFG1_PORT_FEC_AN_MODE_10G_AND_25G_FIRECODE          0x3
1265 		#define NVM_CFG1_PORT_FEC_AN_MODE_25G_RS                        0x4
1266 		#define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE_AND_RS           0x5
1267 		#define NVM_CFG1_PORT_FEC_AN_MODE_ALL                           0x6
1268 		#define NVM_CFG1_PORT_SMARTLINQ_MODE_MASK                       0x00800000
1270 		#define NVM_CFG1_PORT_SMARTLINQ_MODE_DISABLED                   0x0
1271 		#define NVM_CFG1_PORT_SMARTLINQ_MODE_ENABLED                    0x1
1272 		#define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_MASK           0x01000000
1274 		#define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_DISABLED       0x0
1275 		#define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_ENABLED        0x1
1276 	u32 phy_cfg;                                                       /* 0x1C */
1277 		#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK                  0x0000FFFF
1278 		#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET                0
1279 		#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG                 0x1
1280 		#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER             0x2
1281 		#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER                 0x4
1282 		#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN       0x8
1283 		#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN        0x10
1284 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK                 0x00FF0000
1286 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS               0x0
1287 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR                   0x2
1288 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2                  0x3
1289 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4                  0x4
1290 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI                  0x8
1291 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI                  0x9
1292 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X                0xB
1293 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII                0xC
1294 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI                0x11
1295 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI                0x12
1296 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI                 0x21
1297 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI                 0x22
1298 		#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI               0x31
1299 		#define NVM_CFG1_PORT_AN_MODE_MASK                              0xFF000000
1301 		#define NVM_CFG1_PORT_AN_MODE_NONE                              0x0
1302 		#define NVM_CFG1_PORT_AN_MODE_CL73                              0x1
1303 		#define NVM_CFG1_PORT_AN_MODE_CL37                              0x2
1304 		#define NVM_CFG1_PORT_AN_MODE_CL73_BAM                          0x3
1305 		#define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM                       0x4
1306 		#define NVM_CFG1_PORT_AN_MODE_BB_HPAM                           0x5
1307 		#define NVM_CFG1_PORT_AN_MODE_BB_SGMII                          0x6
1308 	u32 mgmt_traffic;                                                  /* 0x20 */
1309 		#define NVM_CFG1_PORT_RESERVED61_MASK                           0x0000000F
1310 		#define NVM_CFG1_PORT_RESERVED61_OFFSET                         0
1311 	u32 ext_phy;                                                       /* 0x24 */
1312 		#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK                    0x000000FF
1313 		#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET                  0
1314 		#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE                    0x0
1315 		#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X                0x1
1316 		#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM5422X                0x2
1317 		#define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK                 0x0000FF00
1320 		#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK                0x00FF0000
1322 		#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED            0x0
1323 		#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED            0x1
1324 		#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE          0x2
1325 		#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY         0x3
1326 	u32 mba_cfg1;                                                      /* 0x28 */
1327 		#define NVM_CFG1_PORT_PREBOOT_OPROM_MASK                        0x00000001
1328 		#define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET                      0
1329 		#define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED                    0x0
1330 		#define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED                     0x1
1331 		#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK            0x00000006
1333 		#define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK                       0x00000078
1335 		#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK                    0x00000080
1337 		#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S                  0x0
1338 		#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B                  0x1
1339 		#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK                0x00000100
1341 		#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED            0x0
1342 		#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED             0x1
1343 		#define NVM_CFG1_PORT_RESERVED5_MASK                            0x0001FE00
1345 		#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK                   0x001E0000
1347 		#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG                0x0
1348 		#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G                     0x1
1349 		#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G                    0x2
1350 		#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_20G                    0x3
1351 		#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G                    0x4
1352 		#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G                    0x5
1353 		#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G                    0x6
1354 		#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G                0x7
1355 		#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK     0x00E00000
1357 		#define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_MASK       0x01000000
1359 		#define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_DISABLED   0x0
1360 		#define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_ENABLED    0x1
1361 	u32 mba_cfg2;                                                      /* 0x2C */
1362 		#define NVM_CFG1_PORT_RESERVED65_MASK                           0x0000FFFF
1363 		#define NVM_CFG1_PORT_RESERVED65_OFFSET                         0
1364 		#define NVM_CFG1_PORT_RESERVED66_MASK                           0x00010000
1366 		#define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_MASK                0x01FE0000
1368 	u32 vf_cfg;                                                        /* 0x30 */
1369 		#define NVM_CFG1_PORT_RESERVED8_MASK                            0x0000FFFF
1370 		#define NVM_CFG1_PORT_RESERVED8_OFFSET                          0
1371 		#define NVM_CFG1_PORT_RESERVED6_MASK                            0x000F0000
1373 	struct nvm_cfg_mac_address lldp_mac_address;                       /* 0x34 */
1374 	u32 led_port_settings;                                             /* 0x3C */
1375 		#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK                   0x000000FF
1376 		#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET                 0
1377 		#define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK                   0x0000FF00
1379 		#define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK                   0x00FF0000
1381 		#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G                      0x1
1382 		#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G                     0x2
1383 		#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_25G                  0x4
1384 		#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_25G                  0x8
1385 		#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_40G                  0x8
1386 		#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_40G                  0x10
1387 		#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_50G                  0x10
1388 		#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_50G                  0x20
1389 		#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G                 0x40
1391 		#define NVM_CFG1_PORT_UID_LED_MODE_MASK_MASK                    0x0F000000
1393 		#define NVM_CFG1_PORT_UID_LED_MODE_MASK_ACTIVITY_LED            0x1
1394 		#define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED0               0x2
1395 		#define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED1               0x4
1396 		#define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED2               0x8
1397 	u32 transceiver_00;                                                /* 0x40 */
1399 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK                     0x000000FF
1400 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET                   0
1401 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA                       0x0
1402 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0                    0x1
1403 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1                    0x2
1404 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2                    0x3
1405 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3                    0x4
1406 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4                    0x5
1407 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5                    0x6
1408 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6                    0x7
1409 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7                    0x8
1410 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8                    0x9
1411 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9                    0xA
1412 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10                   0xB
1413 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11                   0xC
1414 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12                   0xD
1415 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13                   0xE
1416 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14                   0xF
1417 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15                   0x10
1418 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16                   0x11
1419 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17                   0x12
1420 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18                   0x13
1421 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19                   0x14
1422 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20                   0x15
1423 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21                   0x16
1424 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22                   0x17
1425 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23                   0x18
1426 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24                   0x19
1427 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25                   0x1A
1428 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26                   0x1B
1429 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27                   0x1C
1430 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28                   0x1D
1431 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29                   0x1E
1432 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30                   0x1F
1433 		#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31                   0x20
1435 		#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK                  0x00000F00
1437 		#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK                  0x0000F000
1439 	u32 device_ids;                                                    /* 0x44 */
1440 		#define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK                       0x000000FF
1441 		#define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET                     0
1442 		#define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK                      0x0000FF00
1444 		#define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK                     0x00FF0000
1446 		#define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK                  0xFF000000
1448 	u32 board_cfg;                                                     /* 0x48 */
1451 		#define NVM_CFG1_PORT_PORT_TYPE_MASK                            0x000000FF
1452 		#define NVM_CFG1_PORT_PORT_TYPE_OFFSET                          0
1453 		#define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED                       0x0
1454 		#define NVM_CFG1_PORT_PORT_TYPE_MODULE                          0x1
1455 		#define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE                       0x2
1456 		#define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY                         0x3
1457 		#define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE                    0x4
1459 		#define NVM_CFG1_PORT_TX_DISABLE_MASK                           0x0000FF00
1461 		#define NVM_CFG1_PORT_TX_DISABLE_NA                             0x0
1462 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO0                          0x1
1463 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO1                          0x2
1464 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO2                          0x3
1465 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO3                          0x4
1466 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO4                          0x5
1467 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO5                          0x6
1468 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO6                          0x7
1469 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO7                          0x8
1470 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO8                          0x9
1471 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO9                          0xA
1472 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO10                         0xB
1473 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO11                         0xC
1474 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO12                         0xD
1475 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO13                         0xE
1476 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO14                         0xF
1477 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO15                         0x10
1478 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO16                         0x11
1479 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO17                         0x12
1480 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO18                         0x13
1481 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO19                         0x14
1482 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO20                         0x15
1483 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO21                         0x16
1484 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO22                         0x17
1485 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO23                         0x18
1486 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO24                         0x19
1487 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO25                         0x1A
1488 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO26                         0x1B
1489 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO27                         0x1C
1490 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO28                         0x1D
1491 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO29                         0x1E
1492 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO30                         0x1F
1493 		#define NVM_CFG1_PORT_TX_DISABLE_GPIO31                         0x20
1494 	u32 mnm_10g_cap;                                                   /* 0x4C */
1495 		#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK    0x0000FFFF
1496 		#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET  0
1497 		#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G      0x1
1498 		#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G     0x2
1499 		#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_20G     0x4
1500 		#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G     0x8
1501 		#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G     0x10
1502 		#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G     0x20
1503 		#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1504 		#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK    0xFFFF0000
1506 		#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G      0x1
1507 		#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G     0x2
1508 		#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_20G     0x4
1509 		#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G     0x8
1510 		#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G     0x10
1511 		#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G     0x20
1512 		#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1513 	u32 mnm_10g_ctrl;                                                  /* 0x50 */
1514 		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK               0x0000000F
1515 		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET             0
1516 		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG            0x0
1517 		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G                 0x1
1518 		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G                0x2
1519 		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_20G                0x3
1520 		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G                0x4
1521 		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G                0x5
1522 		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G                0x6
1523 		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G            0x7
1524 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK               0x000000F0
1526 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG            0x0
1527 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G                 0x1
1528 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G                0x2
1529 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_20G                0x3
1530 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G                0x4
1531 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G                0x5
1532 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G                0x6
1533 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G            0x7
1536 		#define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK                    0x0000FF00
1538 		#define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED               0x0
1539 		#define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE                  0x1
1540 		#define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE               0x2
1541 		#define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY                 0x3
1542 		#define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE            0x4
1543 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK         0x00FF0000
1545 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS       0x0
1546 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR           0x2
1547 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2          0x3
1548 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4          0x4
1549 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI          0x8
1550 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI          0x9
1551 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X        0xB
1552 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII        0xC
1553 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI        0x11
1554 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI        0x12
1555 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI         0x21
1556 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI         0x22
1557 		#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI       0x31
1558 		#define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK               0xFF000000
1560 	u32 mnm_10g_misc;                                                  /* 0x54 */
1561 		#define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK               0x00000007
1562 		#define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET             0
1563 		#define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE               0x0
1564 		#define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE           0x1
1565 		#define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS                 0x2
1566 		#define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO               0x7
1567 	u32 mnm_25g_cap;                                                   /* 0x58 */
1568 		#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK    0x0000FFFF
1569 		#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET  0
1570 		#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G      0x1
1571 		#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G     0x2
1572 		#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_20G     0x4
1573 		#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G     0x8
1574 		#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G     0x10
1575 		#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G     0x20
1576 		#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1577 		#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK    0xFFFF0000
1579 		#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G      0x1
1580 		#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G     0x2
1581 		#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_20G     0x4
1582 		#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G     0x8
1583 		#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G     0x10
1584 		#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G     0x20
1585 		#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1586 	u32 mnm_25g_ctrl;                                                  /* 0x5C */
1587 		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK               0x0000000F
1588 		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET             0
1589 		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG            0x0
1590 		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G                 0x1
1591 		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G                0x2
1592 		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_20G                0x3
1593 		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G                0x4
1594 		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G                0x5
1595 		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G                0x6
1596 		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G            0x7
1597 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK               0x000000F0
1599 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG            0x0
1600 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G                 0x1
1601 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G                0x2
1602 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_20G                0x3
1603 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G                0x4
1604 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G                0x5
1605 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G                0x6
1606 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G            0x7
1609 		#define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK                    0x0000FF00
1611 		#define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED               0x0
1612 		#define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE                  0x1
1613 		#define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE               0x2
1614 		#define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY                 0x3
1615 		#define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE            0x4
1616 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK         0x00FF0000
1618 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS       0x0
1619 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR           0x2
1620 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2          0x3
1621 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4          0x4
1622 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI          0x8
1623 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI          0x9
1624 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X        0xB
1625 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII        0xC
1626 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI        0x11
1627 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI        0x12
1628 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI         0x21
1629 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI         0x22
1630 		#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI       0x31
1631 		#define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK               0xFF000000
1633 	u32 mnm_25g_misc;                                                  /* 0x60 */
1634 		#define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK               0x00000007
1635 		#define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET             0
1636 		#define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE               0x0
1637 		#define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE           0x1
1638 		#define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS                 0x2
1639 		#define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO               0x7
1640 	u32 mnm_40g_cap;                                                   /* 0x64 */
1641 		#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK    0x0000FFFF
1642 		#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET  0
1643 		#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G      0x1
1644 		#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G     0x2
1645 		#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_20G     0x4
1646 		#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G     0x8
1647 		#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G     0x10
1648 		#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G     0x20
1649 		#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1650 		#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK    0xFFFF0000
1652 		#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G      0x1
1653 		#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G     0x2
1654 		#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_20G     0x4
1655 		#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G     0x8
1656 		#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G     0x10
1657 		#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G     0x20
1658 		#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1659 	u32 mnm_40g_ctrl;                                                  /* 0x68 */
1660 		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK               0x0000000F
1661 		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET             0
1662 		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG            0x0
1663 		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G                 0x1
1664 		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G                0x2
1665 		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_20G                0x3
1666 		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G                0x4
1667 		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G                0x5
1668 		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G                0x6
1669 		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G            0x7
1670 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK               0x000000F0
1672 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG            0x0
1673 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G                 0x1
1674 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G                0x2
1675 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_20G                0x3
1676 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G                0x4
1677 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G                0x5
1678 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G                0x6
1679 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G            0x7
1682 		#define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK                    0x0000FF00
1684 		#define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED               0x0
1685 		#define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE                  0x1
1686 		#define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE               0x2
1687 		#define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY                 0x3
1688 		#define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE            0x4
1689 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK         0x00FF0000
1691 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS       0x0
1692 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR           0x2
1693 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2          0x3
1694 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4          0x4
1695 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI          0x8
1696 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI          0x9
1697 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X        0xB
1698 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII        0xC
1699 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI        0x11
1700 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI        0x12
1701 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI         0x21
1702 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI         0x22
1703 		#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI       0x31
1704 		#define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK               0xFF000000
1706 	u32 mnm_40g_misc;                                                  /* 0x6C */
1707 		#define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK               0x00000007
1708 		#define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET             0
1709 		#define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE               0x0
1710 		#define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE           0x1
1711 		#define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS                 0x2
1712 		#define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO               0x7
1713 	u32 mnm_50g_cap;                                                   /* 0x70 */
1714 		#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK    0x0000FFFF
1715 		#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET  0
1716 		#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G      0x1
1717 		#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G     0x2
1718 		#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_20G     0x4
1719 		#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G     0x8
1720 		#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G     0x10
1721 		#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G     0x20
1722 		#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
1723 		#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK    0xFFFF0000
1725 		#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G      0x1
1726 		#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G     0x2
1727 		#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_20G     0x4
1728 		#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G     0x8
1729 		#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G     0x10
1730 		#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G     0x20
1731 		#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
1732 	u32 mnm_50g_ctrl;                                                  /* 0x74 */
1733 		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK               0x0000000F
1734 		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET             0
1735 		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG            0x0
1736 		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G                 0x1
1737 		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G                0x2
1738 		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_20G                0x3
1739 		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G                0x4
1740 		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G                0x5
1741 		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G                0x6
1742 		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G            0x7
1743 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK               0x000000F0
1745 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG            0x0
1746 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G                 0x1
1747 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G                0x2
1748 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_20G                0x3
1749 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G                0x4
1750 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G                0x5
1751 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G                0x6
1752 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G            0x7
1755 		#define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK                    0x0000FF00
1757 		#define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED               0x0
1758 		#define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE                  0x1
1759 		#define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE               0x2
1760 		#define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY                 0x3
1761 		#define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE            0x4
1762 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK         0x00FF0000
1764 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS       0x0
1765 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR           0x2
1766 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2          0x3
1767 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4          0x4
1768 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI          0x8
1769 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI          0x9
1770 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X        0xB
1771 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII        0xC
1772 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI        0x11
1773 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI        0x12
1774 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI         0x21
1775 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI         0x22
1776 		#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI       0x31
1777 		#define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK               0xFF000000
1779 	u32 mnm_50g_misc;                                                  /* 0x78 */
1780 		#define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK               0x00000007
1781 		#define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET             0
1782 		#define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE               0x0
1783 		#define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE           0x1
1784 		#define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS                 0x2
1785 		#define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO               0x7
1786 	u32 mnm_100g_cap;                                                  /* 0x7C */
1787 		#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK          0x0000FFFF
1788 		#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET        0
1789 		#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G            0x1
1790 		#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G           0x2
1791 		#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_20G           0x4
1792 		#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G           0x8
1793 		#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G           0x10
1794 		#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G           0x20
1795 		#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G       0x40
1796 		#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK          0xFFFF0000
1798 		#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G            0x1
1799 		#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G           0x2
1800 		#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_20G           0x4
1801 		#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G           0x8
1802 		#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G           0x10
1803 		#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G           0x20
1804 		#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G       0x40
1805 	u32 mnm_100g_ctrl;                                                 /* 0x80 */
1806 		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK              0x0000000F
1807 		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET            0
1808 		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG           0x0
1809 		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G                0x1
1810 		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G               0x2
1811 		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_20G               0x3
1812 		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G               0x4
1813 		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G               0x5
1814 		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G               0x6
1815 		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G           0x7
1816 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK              0x000000F0
1818 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG           0x0
1819 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G                0x1
1820 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G               0x2
1821 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_20G               0x3
1822 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G               0x4
1823 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G               0x5
1824 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G               0x6
1825 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G           0x7
1828 		#define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK                   0x0000FF00
1830 		#define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED              0x0
1831 		#define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE                 0x1
1832 		#define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE              0x2
1833 		#define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY                0x3
1834 		#define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE           0x4
1835 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK        0x00FF0000
1837 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS      0x0
1838 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR          0x2
1839 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2         0x3
1840 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4         0x4
1841 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI         0x8
1842 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI         0x9
1843 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X       0xB
1844 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII       0xC
1845 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI       0x11
1846 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI       0x12
1847 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI        0x21
1848 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI        0x22
1849 		#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI      0x31
1850 		#define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK              0xFF000000
1852 	u32 mnm_100g_misc;                                                 /* 0x84 */
1853 		#define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK              0x00000007
1854 		#define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET            0
1855 		#define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE              0x0
1856 		#define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE          0x1
1857 		#define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS                0x2
1858 		#define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO              0x7
1859 	u32 temperature;                                                   /* 0x88 */
1860 		#define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_MASK              0x000000FF
1861 		#define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_OFFSET            0
1862 		#define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK       0x0000FF00
1864 	u32 ext_phy_cfg1;                                                  /* 0x8C */
1866 		#define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_MASK                0x0000FFFF
1867 		#define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_OFFSET              0
1868 	u32 reserved[114];                                                 /* 0x90 */
1873 	struct nvm_cfg_mac_address mac_address;                             /* 0x0 */
1874 	u32 rsrv1;                                                          /* 0x8 */
1875 		#define NVM_CFG1_FUNC_RESERVED1_MASK                            0x0000FFFF
1876 		#define NVM_CFG1_FUNC_RESERVED1_OFFSET                          0
1877 		#define NVM_CFG1_FUNC_RESERVED2_MASK                            0xFFFF0000
1879 	u32 rsrv2;                                                          /* 0xC */
1880 		#define NVM_CFG1_FUNC_RESERVED3_MASK                            0x0000FFFF
1881 		#define NVM_CFG1_FUNC_RESERVED3_OFFSET                          0
1882 		#define NVM_CFG1_FUNC_RESERVED4_MASK                            0xFFFF0000
1884 	u32 device_id;                                                     /* 0x10 */
1885 		#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK                  0x0000FFFF
1886 		#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET                0
1887 		#define NVM_CFG1_FUNC_RESERVED77_MASK                           0xFFFF0000
1889 	u32 cmn_cfg;                                                       /* 0x14 */
1890 		#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK                0x00000007
1891 		#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET              0
1892 		#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE                 0x0
1893 		#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT          0x3
1894 		#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT           0x4
1895 		#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE                0x7
1896 		#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK                     0x0007FFF8
1898 		#define NVM_CFG1_FUNC_PERSONALITY_MASK                          0x00780000
1900 		#define NVM_CFG1_FUNC_PERSONALITY_ETHERNET                      0x0
1901 		#define NVM_CFG1_FUNC_PERSONALITY_ISCSI                         0x1
1902 		#define NVM_CFG1_FUNC_PERSONALITY_FCOE                          0x2
1903 		#define NVM_CFG1_FUNC_PERSONALITY_ROCE                          0x3
1904 		#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK                     0x7F800000
1906 		#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK                   0x80000000
1908 		#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED               0x0
1909 		#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED                0x1
1910 	u32 pci_cfg;                                                       /* 0x18 */
1911 		#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK                 0x0000007F
1912 		#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET               0
1914 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK                     0x00003F80
1916 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED                 0x0
1917 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K                       0x1
1918 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K                       0x2
1919 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K                      0x3
1920 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K                      0x4
1921 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K                      0x5
1922 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K                     0x6
1923 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K                     0x7
1924 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K                     0x8
1925 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M                       0x9
1926 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M                       0xA
1927 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M                       0xB
1928 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M                       0xC
1929 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M                      0xD
1930 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M                      0xE
1931 		#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M                      0xF
1932 		#define NVM_CFG1_FUNC_BAR1_SIZE_MASK                            0x0003C000
1934 		#define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED                        0x0
1935 		#define NVM_CFG1_FUNC_BAR1_SIZE_64K                             0x1
1936 		#define NVM_CFG1_FUNC_BAR1_SIZE_128K                            0x2
1937 		#define NVM_CFG1_FUNC_BAR1_SIZE_256K                            0x3
1938 		#define NVM_CFG1_FUNC_BAR1_SIZE_512K                            0x4
1939 		#define NVM_CFG1_FUNC_BAR1_SIZE_1M                              0x5
1940 		#define NVM_CFG1_FUNC_BAR1_SIZE_2M                              0x6
1941 		#define NVM_CFG1_FUNC_BAR1_SIZE_4M                              0x7
1942 		#define NVM_CFG1_FUNC_BAR1_SIZE_8M                              0x8
1943 		#define NVM_CFG1_FUNC_BAR1_SIZE_16M                             0x9
1944 		#define NVM_CFG1_FUNC_BAR1_SIZE_32M                             0xA
1945 		#define NVM_CFG1_FUNC_BAR1_SIZE_64M                             0xB
1946 		#define NVM_CFG1_FUNC_BAR1_SIZE_128M                            0xC
1947 		#define NVM_CFG1_FUNC_BAR1_SIZE_256M                            0xD
1948 		#define NVM_CFG1_FUNC_BAR1_SIZE_512M                            0xE
1949 		#define NVM_CFG1_FUNC_BAR1_SIZE_1G                              0xF
1950 		#define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK                        0x03FC0000
1953 		#define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK                        0x04000000
1955 		#define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED                    0x0
1956 		#define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED                     0x1
1958 		#define NVM_CFG1_FUNC_BAR2_SIZE_MASK                            0x78000000
1960 		#define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED                        0x0
1961 		#define NVM_CFG1_FUNC_BAR2_SIZE_1M                              0x5
1962 		#define NVM_CFG1_FUNC_BAR2_SIZE_2M                              0x6
1963 		#define NVM_CFG1_FUNC_BAR2_SIZE_4M                              0x7
1964 		#define NVM_CFG1_FUNC_BAR2_SIZE_8M                              0x8
1965 		#define NVM_CFG1_FUNC_BAR2_SIZE_16M                             0x9
1966 		#define NVM_CFG1_FUNC_BAR2_SIZE_32M                             0xA
1967 		#define NVM_CFG1_FUNC_BAR2_SIZE_64M                             0xB
1968 		#define NVM_CFG1_FUNC_BAR2_SIZE_128M                            0xC
1969 		#define NVM_CFG1_FUNC_BAR2_SIZE_256M                            0xD
1970 		#define NVM_CFG1_FUNC_BAR2_SIZE_512M                            0xE
1971 		#define NVM_CFG1_FUNC_BAR2_SIZE_1G                              0xF
1972 	struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;                 /* 0x1C */
1973 	struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;                 /* 0x24 */
1974 	u32 preboot_generic_cfg;                                           /* 0x2C */
1975 		#define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK                   0x0000FFFF
1976 		#define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET                 0
1977 		#define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK                         0x00010000
1979 		#define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_MASK                0x001E0000
1981 		#define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ETHERNET            0x1
1982 		#define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_FCOE                0x2
1983 		#define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ISCSI               0x4
1984 		#define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_RDMA                0x8
1985 	u32 features;                                                      /* 0x30 */
1987 		#define NVM_CFG1_FUNC_RDMA_ENABLEMENT_MASK                      0x00000003
1988 		#define NVM_CFG1_FUNC_RDMA_ENABLEMENT_OFFSET                    0
1989 		#define NVM_CFG1_FUNC_RDMA_ENABLEMENT_NONE                      0x0
1990 		#define NVM_CFG1_FUNC_RDMA_ENABLEMENT_ROCE                      0x1
1991 		#define NVM_CFG1_FUNC_RDMA_ENABLEMENT_IWARP                     0x2
1992 		#define NVM_CFG1_FUNC_RDMA_ENABLEMENT_BOTH                      0x3
1993 	u32 reserved[7];                                                   /* 0x34 */
1998 	struct nvm_cfg1_glob glob;                                          /* 0x0 */
1999 	struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];                     /* 0x228 */
2000 	struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];                     /* 0x230 */
2001 	struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];                     /* 0xB90 */