Lines Matching defs:nvm_cfg1_port
1109 struct nvm_cfg1_port struct
1111 u32 reserved__m_relocated_to_option_123; /* 0x0 */
1112 u32 reserved__m_relocated_to_option_124; /* 0x4 */
1113 u32 generic_cont0; /* 0x8 */
1183 u32 pcie_cfg; /* 0xC */
1186 u32 features; /* 0x10 */
1195 u32 speed_cap_mask; /* 0x14 */
1214 u32 link_settings; /* 0x18 */
1276 u32 phy_cfg; /* 0x1C */
1308 u32 mgmt_traffic; /* 0x20 */
1311 u32 ext_phy; /* 0x24 */
1326 u32 mba_cfg1; /* 0x28 */
1361 u32 mba_cfg2; /* 0x2C */
1368 u32 vf_cfg; /* 0x30 */
1373 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */
1374 u32 led_port_settings; /* 0x3C */
1397 u32 transceiver_00; /* 0x40 */
1439 u32 device_ids; /* 0x44 */
1448 u32 board_cfg; /* 0x48 */
1494 u32 mnm_10g_cap; /* 0x4C */
1513 u32 mnm_10g_ctrl; /* 0x50 */
1560 u32 mnm_10g_misc; /* 0x54 */
1567 u32 mnm_25g_cap; /* 0x58 */
1586 u32 mnm_25g_ctrl; /* 0x5C */
1633 u32 mnm_25g_misc; /* 0x60 */
1640 u32 mnm_40g_cap; /* 0x64 */
1659 u32 mnm_40g_ctrl; /* 0x68 */
1706 u32 mnm_40g_misc; /* 0x6C */
1713 u32 mnm_50g_cap; /* 0x70 */
1732 u32 mnm_50g_ctrl; /* 0x74 */
1779 u32 mnm_50g_misc; /* 0x78 */
1786 u32 mnm_100g_cap; /* 0x7C */
1805 u32 mnm_100g_ctrl; /* 0x80 */
1852 u32 mnm_100g_misc; /* 0x84 */
1859 u32 temperature; /* 0x88 */
1864 u32 ext_phy_cfg1; /* 0x8C */
1868 u32 reserved[114]; /* 0x90 */