Lines Matching +full:0 +full:x37000000
51 #define OFFSIZE_OFFSET_OFFSET 0
52 #define OFFSIZE_OFFSET_MASK 0x0000ffff
55 #define OFFSIZE_SIZE_MASK 0xffff0000
70 u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
71 #define ETH_SPEED_AUTONEG 0
72 #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */
75 #define ETH_PAUSE_NONE 0x0
76 #define ETH_PAUSE_AUTONEG 0x1
77 #define ETH_PAUSE_RX 0x2
78 #define ETH_PAUSE_TX 0x4
82 #define ETH_LOOPBACK_NONE (0)
94 #define EEE_CFG_EEE_ENABLED (1<<0) /* EEE is enabled (configuration). Refer to eee_status->active f…
98 #define EEE_TX_TIMER_USEC_MASK (0xfffffff0)
100 #define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00)
101 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100)
102 #define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000)
105 #define LINK_MODE_SMARTLINQ_ENABLE 0x1 /* XXX Deprecate */
110 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
111 #define PORT_MF_CFG_OV_TAG_OFFSET 0
121 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
122 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
123 u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/
124 u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/
125 u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/
126 u64 r1518; /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */
129 u64 r1522; /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */
130 u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/
131 u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/
132 u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/
133 u64 r16383; /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */
138 u64 r1519_to_max; /* 0x07 (Offset 0x38 ) RX 1519 to max byte frame counter*/
144 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
145 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/
146 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/
147 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
148 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/
149 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */
150 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
151 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */
152 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */
153 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */
154 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
155 u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */
156 u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/
157 u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/
158 u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/
159 u64 t1518; /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */
162 u64 t2047; /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */
163 u64 t4095; /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */
164 u64 t9216; /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */
165 u64 t16383; /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */
168 u64 t1519_to_max; /* 0x47 (Offset 0xd8 ) TX 1519 to max byte frame counter */
174 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */
175 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */
178 u64 tlpiec; /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */
179 u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */
186 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */
187 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */
188 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */
189 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */
190 u64 rxpok; /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */
191 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */
192 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */
193 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */
194 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */
195 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */
215 * BB | 2x10/20Gbps | 0,1 | NA | No | 1 | 1
216 * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1
217 * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1
218 * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional)
219 * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional)
220 * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional)
221 * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1
222 * AH | 2x10/20Gbps | 0,1 | NA | NA | 1 | NA
223 * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA
224 * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA
225 * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA
226 * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA
230 #define CMT_TEAM0 0
236 #define PORT_CMT_IN_TEAM (1<<0)
239 #define PORT_CMT_PORT_INACTIVE (0<<1)
243 #define PORT_CMT_TEAM0 (0<<2)
256 LLDP_NEAREST_BRIDGE = 0,
264 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
265 #define LLDP_CONFIG_TX_INTERVAL_OFFSET 0
266 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
268 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
270 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
272 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
275 If firtst byte is 0, then we will use default chassis ID */
278 If firtst byte is 0, then we will use default port ID */
294 #define DCBX_ETS_ENABLED_MASK 0x00000001
295 #define DCBX_ETS_ENABLED_OFFSET 0
296 #define DCBX_ETS_WILLING_MASK 0x00000002
298 #define DCBX_ETS_ERROR_MASK 0x00000004
300 #define DCBX_ETS_CBS_MASK 0x00000008
302 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
304 #define DCBX_OOO_TC_MASK 0x00000f00
306 /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */
313 #define DCBX_CEE_STRICT_PRIORITY 0xf
314 /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */
316 /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */
318 #define DCBX_ETS_TSA_STRICT 0
325 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
326 #define DCBX_APP_PRI_MAP_OFFSET 0
327 #define DCBX_APP_PRI_0 0x01
328 #define DCBX_APP_PRI_1 0x02
329 #define DCBX_APP_PRI_2 0x04
330 #define DCBX_APP_PRI_3 0x08
331 #define DCBX_APP_PRI_4 0x10
332 #define DCBX_APP_PRI_5 0x20
333 #define DCBX_APP_PRI_6 0x40
334 #define DCBX_APP_PRI_7 0x80
335 #define DCBX_APP_SF_MASK 0x00000300
337 #define DCBX_APP_SF_ETHTYPE 0
339 #define DCBX_APP_SF_IEEE_MASK 0x0000f000
341 #define DCBX_APP_SF_IEEE_RESERVED 0
347 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
354 #define DCBX_APP_ENABLED_MASK 0x00000001
355 #define DCBX_APP_ENABLED_OFFSET 0
356 #define DCBX_APP_WILLING_MASK 0x00000002
358 #define DCBX_APP_ERROR_MASK 0x00000004
361 #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00
364 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
366 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
377 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
378 #define DCBX_PFC_PRI_EN_BITMAP_OFFSET 0
379 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
380 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
381 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
382 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
383 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
384 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
385 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
386 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
388 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
390 #define DCBX_PFC_CAPS_MASK 0x00000f00
392 #define DCBX_PFC_MBC_MASK 0x00004000
394 #define DCBX_PFC_WILLING_MASK 0x00008000
396 #define DCBX_PFC_ENABLED_MASK 0x00010000
398 #define DCBX_PFC_ERROR_MASK 0x00020000
407 #define DCBX_CONFIG_VERSION_MASK 0x00000007
408 #define DCBX_CONFIG_VERSION_OFFSET 0
409 #define DCBX_CONFIG_VERSION_DISABLED 0
423 #define DCBX_CONFIG_VERSION_MASK 0x00000007
424 #define DCBX_CONFIG_VERSION_OFFSET 0
425 #define DCBX_CONFIG_VERSION_DISABLED 0
436 #define LLDP_SYSTEM_TLV_VALID_MASK 0x1
437 #define LLDP_SYSTEM_TLV_VALID_OFFSET 0
441 #define LLDP_SYSTEM_TLV_MANDATORY_MASK 0x2
443 #define LLDP_SYSTEM_TLV_LENGTH_MASK 0xffff0000
460 #define DCB_DSCP_ENABLE_MASK 0x1
461 #define DCB_DSCP_ENABLE_OFFSET 0
467 … 31 28 24 20 16 12 8 4 0
468 …dscp_pri_map[0]: | dscp7 pri | dscp6 pri | dscp5 pri | dscp4 pri | dscp3 pri | dscp2 pri | dscp1 p…
492 ATTRIBUTE_CMD_READ = 0,
519 #define MDUMP_REASON_INTERNAL_ERROR (1 << 0)
523 #define EXT_PHY_FW_UPGRADE_STATUS_MASK (0x0000ffff)
524 #define EXT_PHY_FW_UPGRADE_STATUS_OFFSET (0)
528 #define EXT_PHY_FW_UPGRADE_TYPE_MASK (0xffff0000)
560 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
561 #define ACCUM_ACK_PF_BASE 0
562 #define ACCUM_ACK_PF_SHIFT 0
578 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */
581 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
582 #define PROCESS_KILL_COUNTER_OFFSET 0
583 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
617 u32 validity_map; /* 0x0 (4*2 = 0x8) */
620 #define MCP_VALIDITY_PCI_CFG 0x00100000
621 #define MCP_VALIDITY_MB 0x00200000
622 #define MCP_VALIDITY_DEV_INFO 0x00400000
623 #define MCP_VALIDITY_RESERVED 0x00000007
626 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 /* yaniv - tbd ? license */
627 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
628 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
629 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
632 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
633 #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
634 #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040
635 #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
638 #define LINK_STATUS_LINK_UP 0x00000001
639 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
648 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
649 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
650 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
651 #define LINK_STATUS_PFC_ENABLED 0x00000100
652 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
653 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
654 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
655 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
656 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
657 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
658 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
659 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
660 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
661 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
665 #define LINK_STATUS_SFP_TX_FAULT 0x00100000
666 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
667 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
668 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
669 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
670 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
671 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
672 #define LINK_STATUS_FEC_MODE_MASK 0x38000000
673 #define LINK_STATUS_FEC_MODE_NONE (0<<27)
676 #define LINK_STATUS_EXT_PHY_LINK_UP 0x40000000
679 #define LP_PRESENCE_STATUS_OFFSET 0
680 #define LP_PRESENCE_STATUS_MASK 0x3
681 #define LP_PRESENCE_UNKNOWN 0x0
682 #define LP_PRESENCE_PROBING 0x1
683 #define LP_PRESENT 0x2
684 #define LP_NOT_PRESENT 0x3
697 #define MEDIA_UNSPECIFIED 0x0
698 #define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */
699 #define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */
700 #define MEDIA_DA_TWINAX 0x3
701 #define MEDIA_BASE_T 0x4
702 #define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */
703 #define MEDIA_MODULE_FIBER 0x6
704 #define MEDIA_KR 0xf0
705 #define MEDIA_NOT_PRESENT 0xff
708 #define LFA_LINK_FLAP_REASON_OFFSET 0
709 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
710 #define LFA_NO_REASON (0<<0)
711 #define LFA_LINK_DOWN (1<<0)
720 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
722 #define LINK_FLAP_COUNT_MASK 0x00ff0000
736 /* FC_NPIV table offset & size in NVRAM value of 0 means not present */
738 #define NPIV_TBL_INVALID_ADDR 0xFFFFFFFF
742 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF
743 #define ETH_TRANSCEIVER_STATE_OFFSET 0x0
744 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00
745 #define ETH_TRANSCEIVER_STATE_PRESENT 0x01
746 #define ETH_TRANSCEIVER_STATE_VALID 0x03
747 #define ETH_TRANSCEIVER_STATE_UPDATING 0x08
748 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00
749 #define ETH_TRANSCEIVER_TYPE_OFFSET 0x8
750 #define ETH_TRANSCEIVER_TYPE_NONE 0x00
751 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xFF
752 #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01 /* 1G Passive copper cable */
753 #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02 /* 1G Active copper cable */
754 #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03
755 #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04
756 #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05
757 #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06
758 #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07
759 #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08
760 #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09 /* 10G Passive copper cable */
761 #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a /* 10G Active copper cable */
762 #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b
763 #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c
764 #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d
765 #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e
766 #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f /* Active optical cable */
767 #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10
768 #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11
769 #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12
770 #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13 /* Active copper cable */
771 #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14
772 #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15
773 #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16 /* 25G Passive copper cable - short */
774 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17 /* 25G Active copper cable - short */
775 #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18 /* 25G Passive copper cable - medium */
776 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19 /* 25G Active copper cable - medium */
777 #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a /* 25G Passive copper cable - long */
778 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b /* 25G Active copper cable - long */
779 #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c
780 #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d
781 #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e
782 #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f
783 #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20
784 #define ETH_TRANSCEIVER_TYPE_1000BASET 0x21
785 #define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22
786 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30
787 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
788 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
789 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
790 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
791 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
792 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
799 #define EEE_ACTIVE_BIT (1<<0) /* Set when EEE negotiation is complete. */
801 #define EEE_LD_ADV_STATUS_MASK 0x000000f0 /* Shows the Local Device EEE capabilities */
805 #define EEE_LP_ADV_STATUS_MASK 0x00000f00 /* Same values as in EEE_LD_ADV, but for Link Parter…
808 #define EEE_SUPPORTED_SPEED_MASK 0x0000f000 /* Supported speeds for EEE */
814 #define EEE_REMOTE_TW_TX_MASK 0x0000ffff
815 #define EEE_REMOTE_TW_TX_OFFSET 0
816 #define EEE_REMOTE_TW_RX_MASK 0xffff0000
820 #define ETH_TRANSCEIVER_MONITORING_TYPE_MASK 0x000000FF
821 #define ETH_TRANSCEIVER_MONITORING_TYPE_OFFSET 0
827 #define ETH_TRANSCEIVER_IDENT_MASK 0x0000ff00
831 #define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003
832 #define OEM_CFG_CHANNEL_TYPE_OFFSET 0
833 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1
834 #define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2
836 #define OEM_CFG_SCHED_TYPE_MASK 0x0000000C
838 #define OEM_CFG_SCHED_TYPE_ETS 0x1
839 #define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2
858 /* For PCP values 0-3 use the map lower */
859 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
860 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
864 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
865 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
880 /* function 0 of each port cannot be hidden */
881 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
882 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
883 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_OFFSET 0x00000001
885 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
887 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
888 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
889 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
890 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
891 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
894 /* value range - 0..100, increments in 1 % */
895 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
897 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
898 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
900 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
903 #define FUNC_MF_CFG_RDMA_PROTOCOL_MASK 0x03000000
905 #define FUNC_MF_CFG_RDMA_PROTOCOL_NONE 0x00000000
906 #define FUNC_MF_CFG_RDMA_PROTOCOL_ROCE 0x01000000
907 #define FUNC_MF_CFG_RDMA_PROTOCOL_IWARP 0x02000000
909 #define FUNC_MF_CFG_RDMA_PROTOCOL_BOTH 0x03000000
911 #define FUNC_MF_CFG_BOOT_MODE_MASK 0x0C000000
913 #define FUNC_MF_CFG_BOOT_MODE_BIOS_CTRL 0x00000000
914 #define FUNC_MF_CFG_BOOT_MODE_DISABLED 0x04000000
915 #define FUNC_MF_CFG_BOOT_MODE_ENABLED 0x08000000
918 #define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001
919 #define FUNC_STATUS_LOGICAL_LINK_UP 0x00000002
920 #define FUNC_STATUS_FORCED_LINK 0x00000004
923 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
924 #define FUNC_MF_CFG_UPPERMAC_OFFSET 0
927 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
936 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
937 #define FUNC_MF_CFG_OV_STAG_OFFSET 0
950 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */
953 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
954 #define DRV_ID_PDA_COMP_VER_OFFSET 0
957 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
961 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
963 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_OFFSET)
977 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
982 #define OEM_CFG_FUNC_TC_MASK 0x0000000F
983 #define OEM_CFG_FUNC_TC_OFFSET 0
984 #define OEM_CFG_FUNC_TC_0 0x0
985 #define OEM_CFG_FUNC_TC_1 0x1
986 #define OEM_CFG_FUNC_TC_2 0x2
987 #define OEM_CFG_FUNC_TC_3 0x3
988 #define OEM_CFG_FUNC_TC_4 0x4
989 #define OEM_CFG_FUNC_TC_5 0x5
990 #define OEM_CFG_FUNC_TC_6 0x6
991 #define OEM_CFG_FUNC_TC_7 0x7
993 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030
995 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1
996 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2
1076 #define SENSOR_LOCATION_OFFSET 0
1077 #define SENSOR_LOCATION_MASK 0x000000ff
1079 #define THRESHOLD_HIGH_MASK 0x0000ff00
1081 #define CRITICAL_TEMPERATURE_MASK 0x00ff0000
1083 #define CURRENT_TEMP_MASK 0xff000000
1099 RESOURCE_NUM_SB_E = 0,
1118 RESOURCE_NUM_INVALID = 0xFFFFFFFF
1131 #define RESOURCE_ELEMENT_STRICT (1 << 0)
1139 #define DRV_ROLE_NONE 0
1149 #define LOAD_REQ_ROLE_MASK 0x000000FF
1150 #define LOAD_REQ_ROLE_OFFSET 0
1151 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00
1153 #define LOAD_REQ_LOCK_TO_DEFAULT 0
1155 #define LOAD_REQ_FORCE_MASK 0x000F0000
1157 #define LOAD_REQ_FORCE_NONE 0
1160 #define LOAD_REQ_FLAGS0_MASK 0x00F00000
1162 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0)
1170 #define LOAD_RSP_ROLE_MASK 0x000000FF
1171 #define LOAD_RSP_ROLE_OFFSET 0
1172 #define LOAD_RSP_HSI_MASK 0x0000FF00
1174 #define LOAD_RSP_FLAGS0_MASK 0x000F0000
1176 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0)
1238 #define DRV_MSG_CODE_MASK 0xffff0000
1239 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1240 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1241 #define DRV_MSG_CODE_INIT_HW 0x12000000
1242 #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000
1243 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
1244 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1245 #define DRV_MSG_CODE_INIT_PHY 0x22000000
1248 #define DRV_MSG_CODE_LINK_RESET 0x23000000
1250 #define DRV_MSG_CODE_SET_LLDP 0x24000000
1251 #define DRV_MSG_CODE_REGISTER_LLDP_TLVS_RX 0x24100000
1252 #define DRV_MSG_CODE_SET_DCBX 0x25000000
1254 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
1255 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
1256 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
1257 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
1258 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
1259 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
1260 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
1261 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
1262 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 /* DRV_MB Param: driver version supp, FW_MB para…
1263 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000
1264 #define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000
1265 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000
1266 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000
1267 #define DRV_MSG_CODE_OEM_UPDATE_FCOE_CVID 0x3c000000
1268 #define DRV_MSG_CODE_OEM_UPDATE_FCOE_FABRIC_NAME 0x3d000000
1269 #define DRV_MSG_CODE_OEM_UPDATE_BOOT_CFG 0x3e000000
1270 #define DRV_MSG_CODE_OEM_RESET_TO_DEFAULT 0x3f000000
1271 #define DRV_MSG_CODE_OV_GET_CURR_CFG 0x40000000
1272 #define DRV_MSG_CODE_GET_OEM_UPDATES 0x41000000
1273 #define DRV_MSG_CODE_GET_LLDP_STATS 0x42000000
1274 #define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000 /* params [31:8] - reserved, [7:0] - bitmap */
1276 #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 /*deprecated don't use*/
1277 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000
1278 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1279 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
1280 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000
1281 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BE…
1282 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 /* Param should be set to the transaction size (…
1283 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 /* MFW will place the file offset and len in file…
1284 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 /* Read 32bytes of nvram data. Param is [0:23] ??? …
1285 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 /* Writes up to 32Bytes to nvram. Param is [0:23] …
1286 #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000 /* Delete a file from nvram. Param is image_type. */
1287 #define DRV_MSG_CODE_MCP_RESET 0x00090000 /* Reset MCP when no NVM operation is going on, and no …
1288 #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000 /* Temporary command to set secure mode, where the…
1289 #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 …
1290 #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3…
1291 #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000 /* Param: [0:15] - Address, [30:31] - port */
1292 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 /* Param: [0:15] - Address, [30:31] - port */
1293 #define DRV_MSG_CODE_SET_VERSION 0x000f0000 /* Param: [0:3] - version, [4:15] - name (null termina…
1294 #define DRV_MSG_CODE_MCP_HALT 0x00100000 /* Halts the MCP. To resume MCP, user will need to use M…
1295 …_VMAC 0x00110000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - t…
1296 …_VMAC 0x00120000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - t…
1298 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30
1303 …e DRV_MSG_CODE_GET_STATS 0x00130000 /* Get statistics from pf, params [31:4] - re…
1308 #define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000 /* Host shall provide buffer and size for MFW */
1309 #define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000 /* Host shall provide buffer and size for MFW */
1310 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000 /* Param: [0:1] - Port, [2:7] - read size, [8:15]…
1311 #define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000 /* Param: [0:1] - Port, [2:7] - write size, [8:1…
1312 #define DRV_MSG_CODE_OCBB_DATA 0x00180000 /* indicate OCBB related information */
1313 #define DRV_MSG_CODE_SET_BW 0x00190000 /* Set function BW, params[15:8] - min, params[7:0] - max …
1314 #define BW_MAX_MASK 0x000000ff
1315 #define BW_MAX_OFFSET 0
1316 #define BW_MIN_MASK 0x0000ff00
1319 …V_MSG_CODE_MASK_PARITIES 0x001a0000 /* When param is set to 1, all parities will be masked(disabl…
1320 #define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000 /* param[0] - Simulate fan failure, param[1] - sim…
1321 #define DRV_MSG_FAN_FAILURE_TYPE (1 << 0)
1323 #define DRV_MSG_CODE_GPIO_READ 0x001c0000 /* Param: [0:15] - gpio number */
1324 #define DRV_MSG_CODE_GPIO_WRITE 0x001d0000 /* Param: [0:15] - gpio number, [16:31] - gpio value */
1325 #define DRV_MSG_CODE_BIST_TEST 0x001e0000 /* Param: [0:7] - test enum, [8:15] - image index,…
1326 #define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000
1327 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000 /* Set LED mode params :0 operational, 1 LED turn ON…
1328 #define DRV_MSG_CODE_TIMESTAMP 0x00210000 /* drv_data[7:0] - EPOC in seconds, drv_…
1329 #define DRV_MSG_CODE_EMPTY_MB 0x00220000 /* This is an empty mailbox just return OK*/
1331 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 /* Param[0:4] - resource number (0-31), Param[5:7] - …
1333 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F
1334 #define RESOURCE_CMD_REQ_RESC_OFFSET 0
1335 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0
1342 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00
1345 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF
1346 #define RESOURCE_CMD_RSP_OWNER_OFFSET 0
1347 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700
1350 #define RESOURCE_OPCODE_BUSY 2 /* resource is busy, param[7:0] indicates owner as follow 0-15 = P…
1356 #define RESOURCE_DUMP 0 /* dedicate resource 0 for dump */
1358 #define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */
1359 #define DRV_MSG_CODE_MDUMP_CMD 0x00250000 /* Send crash dump commands with param[3:0] - opcode */
1360 #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f
1361 #define DRV_MSG_CODE_MDUMP_ACK 0x01 /* acknowledge reception of error indication */
1362 #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02 /* set epoc and personality as follow: drv_data[3:0] - …
1363 #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03 /* trigger crash dump procedure */
1364 #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04 /* Request valid logs and config words */
1365 #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 /* Set triggers mask. drv_mb_param should indicate (bit…
1366 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 /* Clear all logs */
1367 #define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07 /* Get retained data */
1368 #define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08 /* Clear retain data */
1369 #define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */
1370 #define DRV_MSG_CODE_GPIO_INFO 0x00270000 /* Param: [0:15] - gpio number */
1371 #define DRV_MSG_CODE_EXT_PHY_READ 0x00280000 /* Value will be placed in union */
1372 #define DRV_MSG_CODE_EXT_PHY_WRITE 0x00290000 /* Value shoud be placed in union */
1373 #define DRV_MB_PARAM_ADDR_OFFSET 0
1374 #define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF
1376 #define DRV_MB_PARAM_DEVAD_MASK 0x001F0000
1378 #define DRV_MB_PARAM_PORT_MASK 0x00600000
1379 #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000
1380 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000
1381 #define DRV_MSG_CODE_SET_LLDP_MAC 0x002c0000
1382 #define DRV_MSG_CODE_GET_LLDP_MAC 0x002d0000
1383 #define DRV_MSG_CODE_OS_WOL 0x002e0000
1385 #define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000 /* Param: None */
1386 #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000 /* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */
1387 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000 /* return FW_MB_PARAM_FEATURE_SUPPORT_* */
1389 #define DRV_MSG_CODE_READ_WOL_REG 0X00320000
1390 #define DRV_MSG_CODE_WRITE_WOL_REG 0X00330000
1391 #define DRV_MSG_CODE_GET_WOL_BUFFER 0X00340000
1392 #define DRV_MSG_CODE_ATTRIBUTE 0x00350000 /* Param: [0:23] Attribute key, [24:31] Attribute sub …
1394 #define DRV_MSG_CODE_ENCRYPT_PASSWORD 0x00360000 /* Param: Password len. Union: Plain Password */
1395 #define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000 /* Param: None */
1398 #define DRV_MSG_CODE_PMBUS_READ 0x00380000 /* Param: [0:7] - Cmd, [8:9] - len */
1399 #define DRV_MSG_CODE_PMBUS_WRITE 0x00390000 /* Param: [0:7] - Cmd, [8:9] - len, [16:31] -data*/
1401 #define DRV_MB_PARAM_PMBUS_CMD_OFFSET 0
1402 #define DRV_MB_PARAM_PMBUS_CMD_MASK 0xFF
1404 #define DRV_MB_PARAM_PMBUS_LEN_MASK 0x300
1406 #define DRV_MB_PARAM_PMBUS_DATA_MASK 0xFFFF0000
1408 #define DRV_MSG_CODE_GENERIC_IDC 0x003a0000
1410 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1414 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
1415 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
1416 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
1417 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
1420 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001
1423 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001
1424 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002
1428 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
1429 #define DRV_MB_PARAM_LLDP_SEND_OFFSET 0
1431 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006
1434 #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_MASK 0x00000001
1435 #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_OFFSET 0
1436 #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_MASK 0x000007f0
1439 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008
1442 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
1443 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_OFFSET 0
1445 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
1446 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
1448 #define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0
1449 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
1451 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
1453 #define DRV_MB_PARAM_PHY_ADDR_OFFSET 0
1454 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF
1456 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000
1458 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000
1460 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000
1462 #define DRV_MB_PARAM_PHYMOD_LANE_OFFSET 0
1463 #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF
1465 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00
1467 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET 0
1468 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
1470 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
1472 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_OFFSET 0
1473 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_MASK 0x000000FF
1476 #define DRV_MB_PARAM_OV_CURR_CFG_OFFSET 0
1477 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
1478 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
1487 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OFFSET 0
1488 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF
1489 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0)
1498 #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0
1500 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_OFFSET 0
1501 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF
1503 #define DRV_MB_PARAM_OV_STORM_FW_VER_OFFSET 0
1504 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
1505 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
1506 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
1507 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
1508 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
1510 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_OFFSET 0
1511 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
1512 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
1513 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 /* Not Installed*/
1514 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
1515 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 /* installed but disabled by user/admin/OS…
1516 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 /* installed and active */
1518 #define DRV_MB_PARAM_OV_MTU_SIZE_OFFSET 0
1519 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
1531 #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0
1532 #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1
1533 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2
1535 #define DRV_MB_PARAM_FCOE_CVID_MASK 0xFFF
1536 #define DRV_MB_PARAM_FCOE_CVID_OFFSET 0
1538 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK 0x1
1539 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET 0
1541 #define DRV_MB_PARAM_LLDP_STATS_AGENT_MASK 0xFF
1542 #define DRV_MB_PARAM_LLDP_STATS_AGENT_OFFSET 0
1544 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
1545 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
1546 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
1548 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0
1549 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
1551 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC
1553 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00
1555 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000
1557 #define DRV_MB_PARAM_GPIO_NUMBER_OFFSET 0
1558 #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF
1560 #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000
1562 #define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000
1564 #define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000
1567 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
1569 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
1570 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0
1572 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0
1578 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
1583 #define DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET 0
1584 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
1586 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00
1588 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF
1589 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
1590 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001 /* driver supports SmartLinQ paramet…
1591 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 /* driver supports EEE parameter */
1592 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK 0xFFFF0000
1594 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000 /* driver supports virtual link para…
1596 #define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0
1597 #define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00FFFFFF
1599 #define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xFF000000
1602 #define FW_MSG_CODE_MASK 0xffff0000
1603 #define FW_MSG_CODE_UNSUPPORTED 0x00000000
1604 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
1605 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1606 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1607 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
1608 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000
1609 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
1610 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000
1611 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
1612 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000
1613 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1614 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
1615 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
1616 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
1617 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1618 #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000
1619 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000
1620 #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000
1621 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000
1622 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000
1623 #define FW_MSG_CODE_REGISTER_LLDP_TLVS_RX_DONE 0x24100000
1624 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000
1625 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000
1626 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000
1627 #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000
1628 #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000
1629 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000
1630 #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000
1631 #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000
1632 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000
1633 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000
1634 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000
1635 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000
1636 #define FW_MSG_CODE_UPDATE_WOL_DONE 0x38000000
1637 #define FW_MSG_CODE_UPDATE_ESWITCH_MODE_DONE 0x39000000
1638 #define FW_MSG_CODE_UPDATE_ERR 0x3a010000
1639 #define FW_MSG_CODE_UPDATE_PARAM_ERR 0x3a020000
1640 #define FW_MSG_CODE_UPDATE_NOT_ALLOWED 0x3a030000
1641 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE 0x3b000000
1642 #define FW_MSG_CODE_UPDATE_FCOE_CVID_DONE 0x3c000000
1643 #define FW_MSG_CODE_UPDATE_FCOE_FABRIC_NAME_DONE 0x3d000000
1644 #define FW_MSG_CODE_UPDATE_BOOT_CFG_DONE 0x3e000000
1645 #define FW_MSG_CODE_RESET_TO_DEFAULT_ACK 0x3f000000
1646 #define FW_MSG_CODE_OV_GET_CURR_CFG_DONE 0x40000000
1647 #define FW_MSG_CODE_GET_OEM_UPDATES_DONE 0x41000000
1648 #define FW_MSG_CODE_GET_LLDP_STATS_DONE 0x42000000
1649 #define FW_MSG_CODE_GET_LLDP_STATS_ERROR 0x42010000
1651 #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000
1652 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1653 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
1654 #define FW_MSG_CODE_FLR_ACK 0x02000000
1655 #define FW_MSG_CODE_FLR_NACK 0x02100000
1656 #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000
1657 #define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000
1658 #define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000
1660 #define FW_MSG_CODE_NVM_OK 0x00010000
1661 #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000
1662 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000
1663 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
1664 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000
1665 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000
1666 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
1667 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
1668 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000
1669 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000
1670 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000
1671 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000
1672 #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000
1673 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000
1674 #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000
1675 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000
1676 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000
1677 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000
1678 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
1679 #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000 /* MFW reject "mcp reset" command if one of the dr…
1680 #define FW_MSG_CODE_NVM_FAILED_CALC_HASH 0x00310000
1681 #define FW_MSG_CODE_NVM_PUBLIC_KEY_MISSING 0x00320000
1682 #define FW_MSG_CODE_NVM_INVALID_PUBLIC_KEY 0x00330000
1684 #define FW_MSG_CODE_PHY_OK 0x00110000
1685 #define FW_MSG_CODE_PHY_ERROR 0x00120000
1686 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000
1687 #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000
1688 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000
1689 #define FW_MSG_CODE_OK 0x00160000
1690 #define FW_MSG_CODE_ERROR 0x00170000
1691 #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000
1692 #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000
1693 #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000
1694 #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000
1695 #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000
1696 #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000
1697 #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000
1698 #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000
1699 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000
1700 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000
1701 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000
1702 #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000
1703 #define FW_MSG_CODE_GPIO_OK 0x00160000
1704 #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000
1705 #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000
1706 #define FW_MSG_CODE_GPIO_INVALID 0x000f0000
1707 #define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000
1708 #define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000
1709 #define FW_MSG_CODE_EXTPHY_INVALID_IMAGE_HEADER 0x00700000
1710 #define FW_MSG_CODE_EXTPHY_INVALID_PHY_TYPE 0x00710000
1711 #define FW_MSG_CODE_EXTPHY_OPERATION_FAILED 0x00720000
1712 #define FW_MSG_CODE_EXTPHY_NO_PHY_DETECTED 0x00730000
1713 #define FW_MSG_CODE_RECOVERY_MODE 0x00740000
1716 #define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000
1717 #define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000
1718 #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000
1719 #define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000
1720 #define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000
1722 #define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000
1723 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000
1725 #define FW_MSG_CODE_WOL_READ_WRITE_OK 0x00820000
1726 #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_VAL 0x00830000
1727 #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_ADDR 0x00840000
1728 #define FW_MSG_CODE_WOL_READ_BUFFER_OK 0x00850000
1729 #define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL 0x00860000
1731 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000
1732 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000
1734 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1736 #define FW_MSG_CODE_ATTRIBUTE_INVALID_KEY 0x00020000
1737 #define FW_MSG_CODE_ATTRIBUTE_INVALID_CMD 0x00030000
1739 #define FW_MSG_CODE_IDC_BUSY 0x00010000
1743 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
1745 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
1746 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0
1749 #define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
1750 #define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
1751 #define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
1752 #define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
1755 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001 /* MFW supports SmartLinQ */
1756 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 /* MFW supports EEE */
1757 #define FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO 0x00000004 /* MFW supports DRV_LOAD Timeout */
1758 #define FW_MB_PARAM_FEATURE_SUPPORT_LP_PRES_DET 0x00000008 /* MFW supports early detection of LP P…
1759 #define FW_MB_PARAM_FEATURE_SUPPORT_RELAXED_ORD 0x00000010 /* MFW supports relaxed ordering settin…
1760 #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000 /* MFW supports virtual link */
1762 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1<<0)
1764 #define FW_MB_PARAM_OEM_UPDATE_MASK 0xFF
1765 #define FW_MB_PARAM_OEM_UPDATE_OFFSET 0
1766 #define FW_MB_PARAM_OEM_UPDATE_BW 0x01
1767 #define FW_MB_PARAM_OEM_UPDATE_S_TAG 0x02
1768 #define FW_MB_PARAM_OEM_UPDATE_CFG 0x04
1770 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001
1771 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_OFFSET 0
1772 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002
1774 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004
1776 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008
1779 #define FW_MB_PARAM_PPFID_BITMAP_MASK 0xFF
1780 #define FW_MB_PARAM_PPFID_BITMAP_OFFSET 0
1783 #define DRV_PULSE_SEQ_MASK 0x00007fff
1784 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1789 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1797 #define MCP_PULSE_SEQ_MASK 0x00007fff
1798 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1801 #define MCP_EVENT_MASK 0xffff0000
1802 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1852 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
1853 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
1910 #define I2C_TRANSCEIVER_ADDR 0xa0
2141 #define I2C_DEV_ADDR_A2 0xa2
2142 #define SFP_EEPROM_A2_TEMPERATURE_ADDR 0x60
2144 #define SFP_EEPROM_A2_VCC_ADDR 0x62
2146 #define SFP_EEPROM_A2_TX_BIAS_ADDR 0x64
2148 #define SFP_EEPROM_A2_TX_POWER_ADDR 0x66
2150 #define SFP_EEPROM_A2_RX_POWER_ADDR 0x68
2153 #define I2C_DEV_ADDR_A0 0xa0
2154 #define QSFP_EEPROM_A0_TEMPERATURE_ADDR 0x16
2156 #define QSFP_EEPROM_A0_VCC_ADDR 0x1a
2158 #define QSFP_EEPROM_A0_TX1_BIAS_ADDR 0x2a
2160 #define QSFP_EEPROM_A0_TX1_POWER_ADDR 0x32
2162 #define QSFP_EEPROM_A0_RX1_POWER_ADDR 0x22
2169 #define ETH_DON_TYPE 0x0911 /* NETWORK Mode for QeDiag */
2170 #define ETH_DON_TRACE_TYPE 0x0912 /* NETWORK Mode Continous Trace */
2172 #define DON_RESP_UNKNOWN_CMD_ID 0x10 /* Response Error */
2176 #define DON_REG_READ_REQ_CMD_ID 0x11
2177 #define DON_REG_WRITE_REQ_CMD_ID 0x22
2178 #define DON_CHALLENGE_REQ_CMD_ID 0x33
2179 #define DON_NVM_READ_REQ_CMD_ID 0x44
2180 #define DON_BLOCK_READ_REQ_CMD_ID 0x55
2182 #define DON_MFW_MODE_TRACE_CONTINUOUS_ID 0x70
2228 #pragma pack(0)