Lines Matching +full:3 +full:x3
43 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3 /* 0=none, 1=DIF, 2=DIX */
48 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
98 __le32 opaque[3] /* The FCP_XFER payload */;
125 #define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3
233 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
235 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
237 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */
251 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
294 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 /* timer0cf */
296 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 /* timer1cf */
298 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */
301 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
303 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf4 */
305 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3 /* cf5 */
307 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3 /* cf6 */
310 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3 /* cf7 */
315 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
332 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
396 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3
401 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3 /* number of additional …
455 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf0 */
457 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
459 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */
473 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
509 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3 /* 0=none, 1=DIF, 2=DIX */
515 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3 /* DIX block size: can be 0:2B, 1:4B…
525 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3
542 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */
545 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */
547 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */
549 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
551 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* cf4 */
561 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
578 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
625 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
627 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
629 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */
643 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
655 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */
657 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */
658 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3
700 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 /* timer0cf */
702 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 /* timer1cf */
704 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */
707 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
709 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf4 */
711 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3 /* cf5 */
713 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3 /* cf6 */
716 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3 /* cf7 */
721 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
738 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
776 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf0 */
778 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
780 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */
794 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
806 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */
808 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */
809 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3
842 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */
845 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */
847 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */
849 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
851 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* dif_error_cf */
861 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
878 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
888 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK 0x3 /* cf5 */
893 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED7_SHIFT 3
990 …u8 max_conc_seqs_c3 /* Maximum concurrent Sequences for Class 3 supported by target, received duri…
1000 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3
1003 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3 /* indication for conn mode: 0=…
1050 __le32 reserved[3];
1060 FCOE_BOTH_OR_NOT_CHOSEN=0x3,
1175 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3 /* If DIF/DIX protection is configured ag…
1187 #define FCOE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */
1189 #define FCOE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */
1195 #define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */