Lines Matching +full:0 +full:x3e00
50 #define ISCSI_CDU_TASK_SEG_TYPE 0
51 #define FCOE_CDU_TASK_SEG_TYPE 0
65 #define YSTORM_QZONE_SIZE 0
66 #define PSTORM_QZONE_SIZE 0
104 #define FW_ENGINEERING_VERSION 0
182 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
185 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
187 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
199 #define DQ_DEMS_LEGACY 0
205 #define DQ_XCM_AGG_VAL_SEL_WORD2 0
235 #define DQ_UCM_AGG_VAL_SEL_WORD0 0
251 #define DQ_TCM_AGG_VAL_SEL_WORD0 0
265 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
290 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0
309 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0
329 #define DQ_PWM_OFFSET_DPM_BASE 0x0
330 #define DQ_PWM_OFFSET_DPM_END 0x27
331 #define DQ_PWM_OFFSET_XCM16_BASE 0x40
332 #define DQ_PWM_OFFSET_XCM32_BASE 0x44
333 #define DQ_PWM_OFFSET_UCM16_BASE 0x48
334 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C
335 #define DQ_PWM_OFFSET_UCM16_4 0x50
336 #define DQ_PWM_OFFSET_TCM16_BASE 0x58
337 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C
338 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68
339 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69
340 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
382 #define CM_TX_PQ_BASE 0x200
401 #define CAU_FSM_ETH_RX 0
411 #define CAU_HC_ENABLE_STATE 0 /* fsm is working with interrupt coalescing for this sb*/
427 #define IGU_MEM_BASE 0x0000
429 #define IGU_MEM_MSIX_BASE 0x0000
430 #define IGU_MEM_MSIX_UPPER 0x0101
431 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
433 #define IGU_MEM_PBA_MSIX_BASE 0x0200
434 #define IGU_MEM_PBA_MSIX_UPPER 0x0202
435 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
437 #define IGU_CMD_INT_ACK_BASE 0x0400
439 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
441 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
442 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1
443 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2
445 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3
446 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4
447 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5
448 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6
450 #define IGU_CMD_PROD_UPD_BASE 0x0600
452 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
459 #define PXP_BAR_GRC 0
460 #define PXP_BAR_TSDM 0
461 #define PXP_BAR_USDM 0
462 #define PXP_BAR_XSDM 0
463 #define PXP_BAR_MSDM 0
464 #define PXP_BAR_YSDM 0
465 #define PXP_BAR_PSDM 0
466 #define PXP_BAR_IGU 0
474 #define PXP_PF_WINDOW_ADMIN_START 0
475 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000
477 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0
480 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200
483 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0
484 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4
485 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8
486 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc
490 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000
492 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000
498 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000
503 #define PXP_BAR0_START_GRC 0x0000
504 #define PXP_BAR0_GRC_LENGTH 0x1C00000
507 #define PXP_BAR0_START_IGU 0x1C00000
508 #define PXP_BAR0_IGU_LENGTH 0x10000
511 #define PXP_BAR0_START_TSDM 0x1C80000
512 #define PXP_BAR0_SDM_LENGTH 0x40000
513 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
516 #define PXP_BAR0_START_MSDM 0x1D00000
519 #define PXP_BAR0_START_USDM 0x1D80000
522 #define PXP_BAR0_START_XSDM 0x1E00000
525 #define PXP_BAR0_START_YSDM 0x1E80000
528 #define PXP_BAR0_START_PSDM 0x1F00000
534 #define PXP_VF_BAR0 0
536 #define PXP_VF_BAR0_START_IGU 0
537 #define PXP_VF_BAR0_IGU_LENGTH 0x3000
540 #define PXP_VF_BAR0_START_DQ 0x3000
541 #define PXP_VF_BAR0_DQ_LENGTH 0x200
542 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
547 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
548 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
551 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
554 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
557 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
560 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
563 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
566 #define PXP_VF_BAR0_START_GRC 0x3E00
567 #define PXP_VF_BAR0_GRC_LENGTH 0x200
570 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
571 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
573 #define PXP_VF_BAR0_START_IGU2 0x10000
574 #define PXP_VF_BAR0_IGU2_LENGTH 0xD000
601 #define SDM_OP_GEN_TRIG_NONE 0
612 #define SDM_COMP_TYPE_NONE 0
646 #define COALESCING_TIMESET_TIMESET_MASK 0x7F /* Interrupt coalescing TimeSet (timeout_ticks = Time…
647 #define COALESCING_TIMESET_TIMESET_SHIFT 0
648 #define COALESCING_TIMESET_VALID_MASK 0x1 /* Only if this flag is set, timeset will take effect …
672 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1
673 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0
674 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F
692 …U_OPCODE_MASK 0x3F /* The processed PDUs opcode on which happened the error - updated for s…
693 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0
694 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 /* Indication for driver is the error_pdu_o…
696 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1
774 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF /* A per protocol indexPROD value. */
775 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
776 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F /* This value determines the TimeSet that the PI is asso…
778 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 /* Select the FSM within the SB */
780 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF /* Select the FSM within the SB */
790 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF /* The SB PROD index which is sent to the IGU. */
791 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0
792 #define CAU_SB_ENTRY_STATE0_MASK 0xF /* RX state */
794 #define CAU_SB_ENTRY_STATE1_MASK 0xF /* TX state */
797 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F /* Indicates the RX TimeSet that this SB is associated …
798 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
799 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F /* Indicates the TX TimeSet that this SB is associated …
801 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 /* This value will determine the RX FSM timer resolution…
803 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 /* This value will determine the TX FSM timer resolution…
805 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
807 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1
809 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
811 #define CAU_SB_ENTRY_TPH_MASK 0x1 /* If set then indicates that the TPH STAG is equal to t…
820 IGU_COMMAND_TYPE_NOP=0,
831 #define CORE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */
832 #define CORE_DB_DATA_DEST_SHIFT 0
833 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */
835 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */
837 #define CORE_DB_DATA_RESERVED_MASK 0x1
839 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */
889 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */
890 #define DB_L2_DPM_DATA_SIZE_SHIFT 0
891 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD)…
893 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */
895 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF /* size of the packet to be transmitted in bytes */
897 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1
899 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 /* In DPM_L2_BD mode: the number of SGE-s */
901 #define DB_L2_DPM_DATA_GFS_SRC_EN_MASK 0x1 /* Flag indicating whether to enable GFS search */
913 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF /* The TPH STAG index value */
914 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
915 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
917 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 /* Indicate if ST hint is requested or not */
919 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
930 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
931 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
932 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 /* doorbell extraction mode specifier- 0 if not used */
934 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF /* internal CID */
944 #define DB_PWM_ADDR_RESERVED0_MASK 0x7
945 #define DB_PWM_ADDR_RESERVED0_SHIFT 0
946 #define DB_PWM_ADDR_OFFSET_MASK 0x7F /* Offset in PWM address space */
948 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */
950 #define DB_PWM_ADDR_DPI_MASK 0xFFFF /* Doorbell page ID */
952 #define DB_PWM_ADDR_RESERVED1_MASK 0xF
962 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */
963 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0
964 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 /* Type of DPM transacation (DPM_RDMA) (use…
966 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF /* opcode for RDMA operation */
968 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF /* the size of the WQE payload in bytes */
970 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1
972 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 /* RoCE completion flag */
974 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */
976 #define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1
978 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 /* Connection type is iWARP */
997 IGU_INT_ENABLE=0,
1010 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
1011 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
1012 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
1014 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 /* interrupt enable/disable/nop (use enum igu…
1016 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 /* (use enum igu_seg_access) */
1018 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
1020 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
1022 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 /* must always be set cleared (use enum comma…
1032 IGU_SEG_ACCESS_REG=0,
1038 …* Enumeration for L3 type field of parsing_and_err_flags. L3Type: 0 - unknown (not ip) ,1 - Ipv4, …
1049 …* Enumeration for l4Protocol field of parsing_and_err_flags. L4-protocol 0 - none, 1 - TCP, 2- UDP…
1065 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 /* L3Type: 0 - unknown (not ip) …
1066 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
1067 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 /* L4-protocol 0 - none, 1 - TCP…
1069 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 /* Set if the packet is IPv4/IPv…
1071 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 /* corresponds to the same 8021q…
1073 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 /* Set if L4 checksum was calcul…
1075 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 /* Set for PTP packet. */
1077 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 /* Set if PTP timestamp recorded…
1079 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 /* Set if either version-mismatc…
1081 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 /* Set if L4 checksum validation…
1083 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 /* Set if GRE/VXLAN/GENEVE tunne…
1085 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 /* This flag should be set if th…
1087 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 /* Set if either tunnel-ipv4-ver…
1089 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 /* taken from the EOP descriptor…
1091 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 /* Set if tunnel L4 checksum val…
1101 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1 /* MAC error indication */
1102 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0
1103 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1 /* truncation error indicatio…
1105 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1 /* packet too small indicatio…
1107 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1 /* Header Missing Tag */
1109 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1 /* from frame cracker output …
1111 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1 /* from frame cracker output …
1113 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1 /* set this error if: 1. tota…
1115 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output …
1117 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1 /* from frame cracker output.…
1119 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1 /* from frame cracker output …
1121 …ASK 0x1 /* cksm calculated and value isnt 0xffff or L4-cksm-wasnt-calculated for any…
1123 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1 /* from frame cracker output …
1125 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1 /* from frame cracker output …
1127 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1 /* set if geneve option size …
1129 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output …
1131 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output …
1149 #define PXP_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */
1150 #define PXP_CONCRETE_FID_PFID_SHIFT 0
1151 #define PXP_CONCRETE_FID_PORT_MASK 0x3 /* port number */
1153 #define PXP_CONCRETE_FID_PATH_MASK 0x1 /* path number */
1155 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1
1157 #define PXP_CONCRETE_FID_VFID_MASK 0xFF
1167 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */
1168 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
1169 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 /* port number. Only when part of ME register. …
1171 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
1173 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
1193 #define PXP_PRETEND_CMD_PATH_MASK 0x1
1194 #define PXP_PRETEND_CMD_PATH_SHIFT 0
1195 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
1197 #define PXP_PRETEND_CMD_PORT_MASK 0x3
1199 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
1201 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
1203 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 /* is pretend mode? */
1205 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 /* is pretend mode? */
1207 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 /* is pretend mode? */
1209 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 /* is fid concrete? */
1219 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
1220 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0
1221 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
1232 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
1233 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
1234 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
1236 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
1238 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
1251 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1252 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1253 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1255 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */
1257 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1259 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 /* 1/2/3 - Protection Type */
1261 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */
1263 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 /* Keep reference tag constant */
1270 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1271 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1272 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1274 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1276 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1278 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1280 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1282 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB…
1284 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */
1286 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 /* DIF tag right at the beginning of …
1288 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
1290 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 /* 0=None, 1=DIF */
1292 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 /* Forward application tag with mask …
1294 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 /* Forward reference tag with mask */
1297 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF
1298 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0
1299 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF
1301 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1
1303 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1
1305 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF /* mask for refernce tag handling */
1307 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
1319 #define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF
1320 #define STATUS_BLOCK_E4_SB_NUM_SHIFT 0
1321 #define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F
1323 #define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF
1326 #define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF
1327 #define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0
1328 #define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF
1339 #define STATUS_BLOCK_E5_SB_NUM_MASK 0x1FF
1340 #define STATUS_BLOCK_E5_SB_NUM_SHIFT 0
1341 #define STATUS_BLOCK_E5_ZERO_PAD_MASK 0x7F
1343 #define STATUS_BLOCK_E5_ZERO_PAD2_MASK 0xFFFF
1346 #define STATUS_BLOCK_E5_PROD_INDEX_MASK 0xFFFFFF
1347 #define STATUS_BLOCK_E5_PROD_INDEX_SHIFT 0
1348 #define STATUS_BLOCK_E5_ZERO_PAD3_MASK 0xFF
1363 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF
1364 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0
1365 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF
1367 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1
1369 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1
1371 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
1375 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1376 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1377 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1379 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */
1381 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1383 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 /* 1/2/3 - Protection Type */
1385 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */
1387 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
1390 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1391 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1392 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1394 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1396 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1398 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1400 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1402 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8…
1404 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */
1406 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 /* DIF tag right at the beginning o…
1408 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 /* reserved */
1410 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 /* 0=None, 1=DIF */
1412 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF
1414 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF
1416 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1
1418 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1
1420 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF /* mask for refernce tag handling */
1422 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 /* Forward application tag with mas…
1424 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 /* Forward reference tag with mask …
1426 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 /* Keep reference tag constant */
1428 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
1444 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF /* Expiration time of logical client 0 …
1445 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
1446 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1
1448 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 /* Valid bit of logical client 0 */
1450 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 /* Active bit of logical client 0 */
1452 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3
1455 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF /* Expiration time of logical client 1 …
1456 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
1457 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1
1459 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 /* Valid bit of logical client 1 */
1461 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 /* Active bit of logical client 1 */
1463 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3
1466 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF /* Expiration time of logical client 2 …
1467 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
1468 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1
1470 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 /* Valid bit of logical client 2 */
1472 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 /* Active bit of logical client 2 */
1474 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3
1477 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF /* Expiration time on host (closest one…
1478 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0
1479 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1
1481 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 /* Valid bit of host expiration */
1483 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7
1492 e_unknown=0,