Lines Matching +full:0 +full:x16000
57 [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
58 [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
59 [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
60 [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
61 [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
62 [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
63 [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
64 [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
65 [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
66 [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
67 [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
68 [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
69 [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
70 [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
71 [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
72 [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
73 [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
74 [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
75 [PCIE_AHB_ARES] = { 0x1d010, 10 },
76 [PCIE_PWR_ARES] = { 0x1d010, 9 },
77 [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
78 [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
79 [PCIE_PHY_ARES] = { 0x1d010, 6 },
80 [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
81 [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
82 [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
83 [PCIE_PIPE_ARES] = { 0x1d010, 2 },
84 [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
85 [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
86 [ESS_RESET] = { 0x12008, 0},
87 [GCC_BLSP1_BCR] = {0x01000, 0},
88 [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
89 [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
90 [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
91 [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
92 [GCC_BIMC_BCR] = {0x04000, 0},
93 [GCC_TLMM_BCR] = {0x05000, 0},
94 [GCC_IMEM_BCR] = {0x0E000, 0},
95 [GCC_ESS_BCR] = {0x12008, 0},
96 [GCC_PRNG_BCR] = {0x13000, 0},
97 [GCC_BOOT_ROM_BCR] = {0x13008, 0},
98 [GCC_CRYPTO_BCR] = {0x16000, 0},
99 [GCC_SDCC1_BCR] = {0x18000, 0},
100 [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
101 [GCC_AUDIO_BCR] = {0x1B008, 0},
102 [GCC_QPIC_BCR] = {0x1C000, 0},
103 [GCC_PCIE_BCR] = {0x1D000, 0},
104 [GCC_USB2_BCR] = {0x1E008, 0},
105 [GCC_USB2_PHY_BCR] = {0x1E018, 0},
106 [GCC_USB3_BCR] = {0x1E024, 0},
107 [GCC_USB3_PHY_BCR] = {0x1E034, 0},
108 [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
109 [GCC_PCNOC_BCR] = {0x2102C, 0},
110 [GCC_DCD_BCR] = {0x21038, 0},
111 [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
112 [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
113 [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
114 [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
115 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
116 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
117 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
118 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
119 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
120 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
121 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
122 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
123 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
124 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
125 [GCC_TCSR_BCR] = {0x22000, 0},
126 [GCC_MPM_BCR] = {0x24000, 0},
127 [GCC_SPDM_BCR] = {0x25000, 0},
151 return (0); in qcom_gcc_ipq4018_hwreset_assert()
175 return (0); in qcom_gcc_ipq4018_hwreset_is_asserted()