Lines Matching +full:0 +full:x12010
71 .clkdef.parent_cnt = 0, \
82 .clkdef.parent_cnt = 0, \
207 F_FEPLL(GCC_FEPLL_VCO, "gcc_fepll_vco", "xo", 0x2f020, 16, 8, 24, 5),
208 F_FEPLL(GCC_APSS_DDRPLL_VCO, "gcc_apps_ddrpll_vco", "xo", 0x2e020,
219 { 384000000, "gcc_apps_ddrpll_vco", 0xd, 0, 0 },
220 { 413000000, "gcc_apps_ddrpll_vco", 0xc, 0, 0 },
221 { 448000000, "gcc_apps_ddrpll_vco", 0xb, 0, 0 },
222 { 488000000, "gcc_apps_ddrpll_vco", 0xa, 0, 0 },
223 { 512000000, "gcc_apps_ddrpll_vco", 0x9, 0, 0 },
224 { 537000000, "gcc_apps_ddrpll_vco", 0x8, 0, 0 },
225 { 565000000, "gcc_apps_ddrpll_vco", 0x7, 0, 0 },
226 { 597000000, "gcc_apps_ddrpll_vco", 0x6, 0, 0 },
227 { 632000000, "gcc_apps_ddrpll_vco", 0x5, 0, 0 },
228 { 672000000, "gcc_apps_ddrpll_vco", 0x4, 0, 0 },
229 { 716000000, "gcc_apps_ddrpll_vco", 0x3, 0, 0 },
230 { 768000000, "gcc_apps_ddrpll_vco", 0x2, 0, 0 },
231 { 823000000, "gcc_apps_ddrpll_vco", 0x1, 0, 0 },
232 { 896000000, "gcc_apps_ddrpll_vco", 0x0, 0, 0 },
233 { 0, }
241 "gcc_apps_ddrpll_vco", 0x2e020,
242 4, 4, 0x2e000, 0, &apss_freq_tbl[0]),
281 { 48000000, "xo", 1, 0, 0 },
282 { 200000000, "fepll200", 1, 0, 0 },
283 { 384000000, "ddrpllapss", 1, 0, 0 },
284 { 413000000, "ddrpllapss", 1, 0, 0 },
285 { 448000000, "ddrpllapss", 1, 0, 0 },
286 { 488000000, "ddrpllapss", 1, 0, 0 },
287 { 500000000, "fepll500", 1, 0, 0 },
288 { 512000000, "ddrpllapss", 1, 0, 0 },
289 { 537000000, "ddrpllapss", 1, 0, 0 },
290 { 565000000, "ddrpllapss", 1, 0, 0 },
291 { 597000000, "ddrpllapss", 1, 0, 0 },
292 { 632000000, "ddrpllapss", 1, 0, 0 },
293 { 672000000, "ddrpllapss", 1, 0, 0 },
294 { 716000000, "ddrpllapss", 1, 0, 0 },
295 { 0,}
300 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 },
301 { 200000000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 },
302 { 0,}
307 { 0,}
317 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 },
318 { 0,}
322 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 },
323 { 100000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(2), 0, 0 },
324 { 0, }
337 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 },
338 { 0, }
342 { 1250000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 16, 0 },
343 { 2500000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 8, 0 },
344 { 5000000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 4, 0 },
345 { 0, }
350 { 400000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 1, 0 },
355 { 192000000, "ddrpllsdcc", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 },
356 { 0, }
360 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 },
361 { 100000000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(2), 0, 0 },
362 { 0, }
366 { 2000000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(10), 0, 0 },
367 { 0, }
371 { 125000000, "fepll125dly", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 },
372 { 0, }
376 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 },
377 { 250000000, "fepllwcss2g", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 },
378 { 0, }
382 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 },
383 { 250000000, "fepllwcss5g", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 },
384 { 0, }
391 { 0, 15 },
395 { 0, 0 }
403 0x2f020, 8, 2, &fepllwcss_clk_div_tbl[0]),
405 0x2f020, 12, 2, &fepllwcss_clk_div_tbl[0]),
413 0x1b000, 5, 0, -1, -1, 0, 0, &audio_clk_src_freq_tbl[0]),
415 gcc_xo_200_parents, 0x200c, 5, 0, -1, -1, 0, 0,
416 &blsp1_qup1_i2c_apps_clk_src_freq_tbl[0]),
418 gcc_xo_200_parents, 0x3000, 5, 0, -1, -1, 0, 0,
419 &blsp1_qup1_i2c_apps_clk_src_freq_tbl[0]),
421 gcc_xo_200_spi_parents, 0x2024, 5, 8, -1, -1, 0, 0,
422 &blsp1_qup1_spi_apps_clk_src_freq_tbl[0]),
424 gcc_xo_200_spi_parents, 0x3014, 5, 8, -1, -1, 0, 0,
425 &blsp1_qup1_spi_apps_clk_src_freq_tbl[0]),
427 gcc_xo_200_spi_parents, 0x2044, 5, 16, -1, -1, 0, 0,
428 &blsp1_uart1_apps_clk_src_freq_tbl[0]),
430 gcc_xo_200_spi_parents, 0x3034, 5, 16, -1, -1, 0, 0,
431 &blsp1_uart1_apps_clk_src_freq_tbl[0]),
432 F_RCG2(GP1_CLK_SRC, "gp1_clk_src", gcc_xo_200_parents, 0x8004,
433 5, 8, -1, -1, 0, 0,
434 &gp1_clk_src_freq_tbl[0]),
435 F_RCG2(GP2_CLK_SRC, "gp2_clk_src", gcc_xo_200_parents, 0x9004,
436 5, 8, -1, -1, 0, 0,
437 &gp1_clk_src_freq_tbl[0]),
438 F_RCG2(GP3_CLK_SRC, "gp3_clk_src", gcc_xo_200_parents, 0xa004,
439 5, 8, -1, -1, 0, 0,
440 &gp1_clk_src_freq_tbl[0]),
442 gcc_xo_sdcc1_500_parents, 0x18004, 5, 0, -1, -1, 0, 0,
443 &sdcc1_apps_clk_src_freq_tbl[0]),
445 0x1900c, 5, 0, -1, 2, 0,
447 &apps_clk_src_freq_tbl[0]),
449 gcc_xo_200_500_parents, 0x19014, 5, 0, -1, -1, 0,
450 0, &apps_ahb_clk_src_freq_tbl[0]),
452 gcc_xo_200_parents, 0x1e000, 5, 0, -1, -1, 0, 0,
453 &usb30_mock_utmi_clk_src_freq_tbl[0]),
455 gcc_xo_125_dly_parents, 0x12000, 5, 0, -1, -1, 0, 0,
456 &fephy_125m_dly_clk_src_freq_tbl[0]),
458 0x1f000, 5, 0, -1, -1, 0, 0,
459 &wcss2g_clk_src_freq_tbl[0]),
461 0x20000, 5, 0, -1, -1, 0, 0,
462 &wcss5g_clk_src_freq_tbl[0]),
464 gcc_xo_200_500_parents, 0x21024, 5, 0, -1, -1, 0, 0,
465 &gcc_pcnoc_ahb_clk_src_freq_tbl[0]),
473 0x1b010, 0, 0, 0, 0x1b010, QCOM_CLK_BRANCH2_BRANCH_HALT,
476 0x1b00c, 0, 0, 0, 0x1b00c, QCOM_CLK_BRANCH2_BRANCH_HALT,
480 0x2008, 0, 0, 0, 0x2008, QCOM_CLK_BRANCH2_BRANCH_HALT,
484 0x3010, 0, 0, 0, 0x3010, QCOM_CLK_BRANCH2_BRANCH_HALT,
488 0x2004, 0, 0, 0, 0x2004, QCOM_CLK_BRANCH2_BRANCH_HALT,
492 0x300c, 0, 0, 0, 0x300c, QCOM_CLK_BRANCH2_BRANCH_HALT,
496 0x203c, 0, 0, 0, 0x203c, QCOM_CLK_BRANCH2_BRANCH_HALT,
500 0x302c, 0, 0, 0, 0x302c, QCOM_CLK_BRANCH2_BRANCH_HALT,
503 0x8000, 0, 0, 0, 0x8000, QCOM_CLK_BRANCH2_BRANCH_HALT,
506 0x9000, 0, 0, 0, 0x9000, QCOM_CLK_BRANCH2_BRANCH_HALT,
509 0xa000, 0, 0, 0, 0xa000, QCOM_CLK_BRANCH2_BRANCH_HALT,
514 0x6000, 14, 0, 0, 0x19004, QCOM_CLK_BRANCH2_BRANCH_HALT,
518 0x6000, 10, 0, 0, 0x1008, QCOM_CLK_BRANCH2_BRANCH_HALT,
519 true, 0), /* BRANCH_HALT_VOTED */
521 0x2103c, 0, 0, 0, 0x2103c, QCOM_CLK_BRANCH2_BRANCH_HALT,
522 false, 0),
524 "pcnoc_clk_src", 0x1300c, 0, 0, 0, 0x1300c,
528 "pcnoc_clk_src", 0x6000, 0, 0, 0, 0x16024,
530 true, 0), /* BRANCH_HALT_VOTED */
532 "fepll125", 0x6000, 1, 0, 0, 0x16020,
534 true, 0), /* BRANCH_HALT_VOTED */
536 0x6000, 2, 0, 0, 0x1601c, QCOM_CLK_BRANCH2_BRANCH_HALT,
537 true, 0), /* BRANCH_HALT_VOTED */
539 0x12010, 0, 0, 0, 0x12010, QCOM_CLK_BRANCH2_BRANCH_HALT,
543 0x6000, 17, 0, 0, 0xe004, QCOM_CLK_BRANCH2_BRANCH_HALT,
547 0xe008, 0, 0, 0, 0xe008, QCOM_CLK_BRANCH2_BRANCH_HALT,
548 false, 0),
550 0x1d00c, 0, 0, 0, 0x1d00c, QCOM_CLK_BRANCH2_BRANCH_HALT,
551 false, 0),
553 0x1d004, 0, 0, 0, 0x1d004, QCOM_CLK_BRANCH2_BRANCH_HALT,
554 false, 0),
556 0x1d008, 0, 0, 0, 0x1d008, QCOM_CLK_BRANCH2_BRANCH_HALT,
557 false, 0),
559 0x6000, 8, 0, 0, 0x13004, QCOM_CLK_BRANCH2_BRANCH_HALT,
560 true, 0), /* BRANCH_HALT_VOTED */
562 0x1c008, 0, 0, 0, 0x1c008, QCOM_CLK_BRANCH2_BRANCH_HALT,
563 false, 0),
565 0x1c004, 0, 0, 0, 0x1c004, QCOM_CLK_BRANCH2_BRANCH_HALT,
566 false, 0),
568 0x18010, 0, 0, 0, 0x18010, QCOM_CLK_BRANCH2_BRANCH_HALT,
569 false, 0),
571 "sdcc1_apps_clk_src", 0x1800c, 0, 0, 0, 0x1800c,
575 0x6000, 5, 0, 0, 0x5004, QCOM_CLK_BRANCH2_BRANCH_HALT,
576 true, 0), /* BRANCH_HALT_VOTED */
578 0x1e00c, 0, 0, 0, 0x1e00c, QCOM_CLK_BRANCH2_BRANCH_HALT,
579 false, 0),
581 "sleep_clk", 0x1e010, 0, 0, 0, 0x1e010,
583 false, 0),
585 "usb30_mock_utmi_clk_src", 0x1e014, 0, 0, 0, 0x1e014,
587 false, 0),
589 0x1e028, 0, 0, 0, 0x1e028, QCOM_CLK_BRANCH2_BRANCH_HALT,
590 false, 0),
592 0x1e02c, 0, 0, 0, 0x1e02c, QCOM_CLK_BRANCH2_BRANCH_HALT,
593 false, 0),
596 0x1e030, 0, 0, 0, 0x1e030, QCOM_CLK_BRANCH2_BRANCH_HALT,
600 0x1f00c, 0, 0, 0, 0x1f00c, QCOM_CLK_BRANCH2_BRANCH_HALT,
603 0x1f00c, 0, 0, 0, 0x1f00c, QCOM_CLK_BRANCH2_BRANCH_HALT,
611 0x1f010, 0, 0, 0, 0x1f010, QCOM_CLK_BRANCH2_BRANCH_HALT,
612 false, 0),
616 0x1f00c, 0, 0, 0, 0x2000c, QCOM_CLK_BRANCH2_BRANCH_HALT,
619 0x1f00c, 0, 0, 0, 0x2000c, QCOM_CLK_BRANCH2_BRANCH_HALT,
622 0x1f010, 0, 0, 0, 0x20010, QCOM_CLK_BRANCH2_BRANCH_HALT,
623 false, 0),
626 0x21030, 0, 0, 0, 0x21030, QCOM_CLK_BRANCH2_BRANCH_HALT, false,
636 for (i = 0; i < nitems(fepll_tbl); i++) { in qcom_gcc_ipq4018_clock_init_fepll()
638 if (rv != 0) in qcom_gcc_ipq4018_clock_init_fepll()
648 for (i = 0; i < nitems(fdiv_tbl); i++) { in qcom_gcc_ipq4018_clock_init_fdiv()
650 if (rv != 0) in qcom_gcc_ipq4018_clock_init_fdiv()
660 for (i = 0; i < nitems(apssdiv_tbl); i++) { in qcom_gcc_ipq4018_clock_init_apssdiv()
662 if (rv != 0) in qcom_gcc_ipq4018_clock_init_apssdiv()
672 for (i = 0; i < nitems(rcg2_tbl); i++) { in qcom_gcc_ipq4018_clock_init_rcg2()
674 if (rv != 0) in qcom_gcc_ipq4018_clock_init_rcg2()
684 for (i = 0; i < nitems(branch2_tbl); i++) { in qcom_gcc_ipq4018_clock_init_branch2()
686 if (rv != 0) in qcom_gcc_ipq4018_clock_init_branch2()
696 for (i = 0; i < nitems(ro_div_tbl); i++) { in qcom_gcc_ipq4018_clock_init_ro_div()
698 if (rv != 0) in qcom_gcc_ipq4018_clock_init_ro_div()