190 	/* Calculate the rate based on the parent rate and config */  in qcom_clk_rcg2_recalc()
197  * configure the mn:d divisor, pre-divisor, and parent.
247 	/* Configure parent clock */  in qcom_clk_rcg2_set_config_locked()
270 	 * Read the mux setting to set the right parent.  in qcom_clk_rcg2_init()
296 	 * If we could be sure our parent clocks existed here in the tree,  in qcom_clk_rcg2_init()
297 	 * we could calculate our current frequency by fetching the parent  in qcom_clk_rcg2_init()
318  * Program the parent index.
342  * fin - the parent frequency, if exists
378 	 * Find the parent index for the given parent clock.  in qcom_clk_rcg2_set_freq()
388 		if (strcmp(parent_names[i], f->parent) == 0)  in qcom_clk_rcg2_set_freq()
393 		    "%s: couldn't find suitable parent?\n",  in qcom_clk_rcg2_set_freq()
399 	 * If we aren't setting the parent clock, then we need  in qcom_clk_rcg2_set_freq()
400 	 * to just program the new parent clock in and update.  in qcom_clk_rcg2_set_freq()
412 			    "%s: setting to safe parent idx %d\n",  in qcom_clk_rcg2_set_freq()
419 			    "%s: safe parent: updating config\n", __func__);  in qcom_clk_rcg2_set_freq()
429 			    "%s: safe parent: done\n", __func__);  in qcom_clk_rcg2_set_freq()
433 		/* Program parent index, then schedule update */  in qcom_clk_rcg2_set_freq()
439 			    "%s: couldn't program in parent idx %u!\n",  in qcom_clk_rcg2_set_freq()
450 	 * If we /are/ setting the parent clock, then we need  in qcom_clk_rcg2_set_freq()
451 	 * to determine what frequency we need the parent to  in qcom_clk_rcg2_set_freq()
452 	 * be, and then reconfigure the parent to the new  in qcom_clk_rcg2_set_freq()
453 	 * frequency, and then change our parent.  in qcom_clk_rcg2_set_freq()
458 	p_clk = clknode_find_by_name(f->parent);  in qcom_clk_rcg2_set_freq()
461 		    "%s: couldn't find parent clk (%s)\n",  in qcom_clk_rcg2_set_freq()
462 		    __func__, f->parent);  in qcom_clk_rcg2_set_freq()
467 	 * Calculate required frequency from said parent clock to  in qcom_clk_rcg2_set_freq()
473 	    "%s: request %llu, parent %s freq %llu, parent freq %llu\n",  in qcom_clk_rcg2_set_freq()
476 	    f->parent,  in qcom_clk_rcg2_set_freq()
482 	 * a safe parent before programming our divisor and the parent  in qcom_clk_rcg2_set_freq()
483 	 * clock configuration.  Then once it's done, flip the parent  in qcom_clk_rcg2_set_freq()
484 	 * to the new parent.  in qcom_clk_rcg2_set_freq()
486 	 * If we're doing a dry-run then we don't need to re-parent the  in qcom_clk_rcg2_set_freq()
492 		    "%s: setting to safe parent idx %d\n",  in qcom_clk_rcg2_set_freq()
499 		    "%s: safe parent: updating config\n", __func__);  in qcom_clk_rcg2_set_freq()
509 		    "%s: safe parent: done\n", __func__);  in qcom_clk_rcg2_set_freq()
515 	 * Set the parent frequency before we change our mux and divisor  in qcom_clk_rcg2_set_freq()
520 		    "%s: couldn't get freq for parent clock %s\n",  in qcom_clk_rcg2_set_freq()
522 		    f->parent);  in qcom_clk_rcg2_set_freq()
546 			    "%s: couldn't set parent clock %s frequency to "  in qcom_clk_rcg2_set_freq()
549 			    f->parent,  in qcom_clk_rcg2_set_freq()
559 				    "%s: couldn't get parent frequency",  in qcom_clk_rcg2_set_freq()
568 	    " parent choice=%s, parent_freq=%llu\n",  in qcom_clk_rcg2_set_freq()
572 	    f->parent,  in qcom_clk_rcg2_set_freq()
576 	 * Set the parent node, the parent programming and the divisor  in qcom_clk_rcg2_set_freq()
582 	 * Program the divisor and parent.  in qcom_clk_rcg2_set_freq()
599 	 * p_freq is now the frequency that the parent /is/ set to.  in qcom_clk_rcg2_set_freq()
634 	 * or limiting it to the lowest parent clock.  But, do set the  in qcom_clk_rcg2_register()