Lines Matching +full:mmp +full:- +full:timer

1 /* SPDX-License-Identifier: BSD-2-Clause AND BSD-3-Clause */
31  *   Copyright(c) 2007-2019 Intel Corporation. All rights reserved.
146 #define QAT_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7)
147 #define QAT_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7)
158 	((((1 << (RING_SIZE - 1)) << 3) >> QAT_SIZE_TO_POW(MSG_SIZE)) - 1)
191 	uint32_t qb_coalescing_time;	/* timer in nano sec, 0: disabled */
234 		((sc)->sc_ae[ae])
238 	u_int qae_ustore_size;		/* free micro-store address */
239 	u_int qae_free_addr;		/* free micro-store address */
240 	u_int qae_free_size;		/* free micro-store size */
242 	u_int qae_ustore_dram_addr;	/* micro-store DRAM address */
248 	u_int qae_reloc_ustore_dram;	/* reloadable ustore-dram address */
295 	u_int qup_num_neigh_reg;	/* num of neigh-reg in array */
297 					/* array of neigh-reg assignments */
500 /* Pad out to 64-byte multiple to ensure optimal alignment of next field */
554 	/* should be 64-byte aligned */
834 	void *sc_fw_mmp;			/* mmp data */
835 	size_t sc_fw_mmp_size;			/* mmp size */
845 	bus_space_write_4(sc->sc_csrt[baroff],  in qat_bar_write_4()
846 	    sc->sc_csrh[baroff], offset, value);  in qat_bar_write_4()
855 	return bus_space_read_4(sc->sc_csrt[baroff],  in qat_bar_read_4()
856 	    sc->sc_csrh[baroff], offset);  in qat_bar_read_4()
863 	qat_bar_write_4(sc, sc->sc_hw.qhw_misc_bar_id, offset, value);  in qat_misc_write_4()
870 	return qat_bar_read_4(sc, sc->sc_hw.qhw_misc_bar_id, offset);  in qat_misc_read_4()
899 	qat_bar_write_4(sc, sc->sc_hw.qhw_etr_bar_id, offset, value);  in qat_etr_write_4()
906 	return qat_bar_read_4(sc, sc->sc_hw.qhw_etr_bar_id, offset);  in qat_etr_read_4()
914 	offset = __SHIFTIN(ae & sc->sc_ae_mask, AE_LOCAL_AE_MASK) |  in qat_ae_local_write_4()
917 	qat_misc_write_4(sc, sc->sc_hw.qhw_ae_local_offset + offset,  in qat_ae_local_write_4()
925 	offset = __SHIFTIN(ae & sc->sc_ae_mask, AE_LOCAL_AE_MASK) |  in qat_ae_local_read_4()
928 	return qat_misc_read_4(sc, sc->sc_hw.qhw_ae_local_offset + offset);  in qat_ae_local_read_4()
935 	offset = __SHIFTIN(ae & sc->sc_ae_mask, AE_XFER_AE_MASK) |  in qat_ae_xfer_write_4()
938 	qat_misc_write_4(sc, sc->sc_hw.qhw_ae_offset + offset, value);  in qat_ae_xfer_write_4()
945 	qat_misc_write_4(sc, sc->sc_hw.qhw_cap_global_offset + offset, value);  in qat_cap_global_write_4()
952 	return qat_misc_read_4(sc, sc->sc_hw.qhw_cap_global_offset + offset);  in qat_cap_global_read_4()
961 	qat_etr_write_4(sc, sc->sc_hw.qhw_etr_bundle_size * bank + offset,  in qat_etr_bank_write_4()
971 	    sc->sc_hw.qhw_etr_bundle_size * bank + offset);  in qat_etr_bank_read_4()