1296 	unsigned int ctxarb_ctl, ctx_enables;  in qat_hal_exec_micro_inst()  local
1346 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_exec_micro_inst()
1347 	ctx_enables &= IGNORE_W1C_MASK;  in qat_hal_exec_micro_inst()
1356 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_exec_micro_inst()
1437 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_exec_micro_inst()
1452 	unsigned int ctxarb_cntl, ustore_addr, ctx_enables;  in qat_hal_rd_rel_reg()  local
1478 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_rd_rel_reg()
1479 	ctx_enables &= IGNORE_W1C_MASK;  in qat_hal_rd_rel_reg()
1486 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_rd_rel_reg()
1516 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_rd_rel_reg()
1700 	unsigned int ctx_enables;  in qat_hal_put_rel_rd_xfer()  local
1704 	status = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_put_rel_rd_xfer()
1705 	if (CE_INUSE_CONTEXTS & ctx_enables) {  in qat_hal_put_rel_rd_xfer()
1742 	unsigned int gprval, ctx_enables;  in qat_hal_put_rel_wr_xfer()  local
1755 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_put_rel_wr_xfer()
1756 	if (CE_INUSE_CONTEXTS & ctx_enables) {  in qat_hal_put_rel_wr_xfer()
1799 	unsigned int ctx_enables;  in qat_hal_put_rel_nn()  local
1802 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_put_rel_nn()
1803 	ctx_enables &= IGNORE_W1C_MASK;  in qat_hal_put_rel_nn()
1804 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables | CE_NN_MODE);  in qat_hal_put_rel_nn()
1807 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_put_rel_nn()
1818 	unsigned int ctx_enables;  in qat_hal_convert_abs_to_rel()  local
1820 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_convert_abs_to_rel()
1821 	if (ctx_enables & CE_INUSE_CONTEXTS) {  in qat_hal_convert_abs_to_rel()