144 #define CAP_CSR_ADDR(csr) (csr + handle->hal_cap_g_ctl_csr_addr_v)
145 #define SET_CAP_CSR(handle, csr, val)                                          \  argument
146 	ADF_CSR_WR(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr), val)
147 #define GET_CAP_CSR(handle, csr)                                               \  argument
148 	ADF_CSR_RD(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr))
149 #define SET_GLB_CSR(handle, csr, val)                                          \  argument
151 		u32 dev_id = pci_get_device(GET_DEV((handle)->accel_dev));     \
153 		    SET_CAP_CSR((handle), (csr), (val)) :                      \
154 		    SET_CAP_CSR((handle), (csr) + GLOBAL_CSR, val);            \
156 #define GET_GLB_CSR(handle, csr)                                               \  argument
158 		u32 dev_id = pci_get_device(GET_DEV((handle)->accel_dev));     \
160 		    GET_CAP_CSR((handle), (csr)) :                             \
161 		    GET_CAP_CSR((handle), (csr) + GLOBAL_CSR);                 \
163 #define SET_FCU_CSR(handle, csr, val)                                          \  argument
165 		typeof(handle) handle_ = (handle);                             \
179 #define GET_FCU_CSR(handle, csr)                                               \  argument
181 		typeof(handle) handle_ = (handle);                             \
190 #define AE_CSR(handle, ae)                                                     \  argument
191 	((handle)->hal_cap_ae_local_csr_addr_v + ((ae) << 12))
192 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr)))  argument
193 #define SET_AE_CSR(handle, ae, csr, val)                                       \  argument
194 	ADF_CSR_WR(handle->hal_misc_addr_v, AE_CSR_ADDR(handle, ae, csr), val)
195 #define GET_AE_CSR(handle, ae, csr)                                            \  argument
196 	ADF_CSR_RD(handle->hal_misc_addr_v, AE_CSR_ADDR(handle, ae, csr))
197 #define AE_XFER(handle, ae)                                                    \  argument
198 	((handle)->hal_cap_ae_xfer_csr_addr_v + ((ae) << 12))
199 #define AE_XFER_ADDR(handle, ae, reg)                                          \  argument
200 	(AE_XFER(handle, ae) + (((reg)&0xff) << 2))
201 #define SET_AE_XFER(handle, ae, reg, val)                                      \  argument
202 	ADF_CSR_WR(handle->hal_misc_addr_v, AE_XFER_ADDR(handle, ae, reg), val)
203 #define SRAM_WRITE(handle, addr, val)                                          \  argument
204 	ADF_CSR_WR((handle)->hal_sram_addr_v, addr, val)