Lines Matching +full:0 +full:x144
9 MISC_CONTROL = 0x04,
10 ICP_RESET = 0x0c,
11 ICP_GLOBAL_CLK_ENABLE = 0x50
14 enum { MISC_CONTROL_C4XXX = 0xAA0,
15 ICP_RESET_CPP0 = 0x938,
16 ICP_RESET_CPP1 = 0x93c,
17 ICP_GLOBAL_CLK_ENABLE_CPP0 = 0x964,
18 ICP_GLOBAL_CLK_ENABLE_CPP1 = 0x968 };
21 USTORE_ADDRESS = 0x000,
22 USTORE_DATA_LOWER = 0x004,
23 USTORE_DATA_UPPER = 0x008,
24 ALU_OUT = 0x010,
25 CTX_ARB_CNTL = 0x014,
26 CTX_ENABLES = 0x018,
27 CC_ENABLE = 0x01c,
28 CSR_CTX_POINTER = 0x020,
29 CTX_STS_INDIRECT = 0x040,
30 ACTIVE_CTX_STATUS = 0x044,
31 CTX_SIG_EVENTS_INDIRECT = 0x048,
32 CTX_SIG_EVENTS_ACTIVE = 0x04c,
33 CTX_WAKEUP_EVENTS_INDIRECT = 0x050,
34 LM_ADDR_0_INDIRECT = 0x060,
35 LM_ADDR_1_INDIRECT = 0x068,
36 LM_ADDR_2_INDIRECT = 0x0cc,
37 LM_ADDR_3_INDIRECT = 0x0d4,
38 INDIRECT_LM_ADDR_0_BYTE_INDEX = 0x0e0,
39 INDIRECT_LM_ADDR_1_BYTE_INDEX = 0x0e8,
40 INDIRECT_LM_ADDR_2_BYTE_INDEX = 0x10c,
41 INDIRECT_LM_ADDR_3_BYTE_INDEX = 0x114,
42 INDIRECT_T_INDEX = 0x0f8,
43 INDIRECT_T_INDEX_BYTE_INDEX = 0x0fc,
44 FUTURE_COUNT_SIGNAL_INDIRECT = 0x078,
45 TIMESTAMP_LOW = 0x0c0,
46 TIMESTAMP_HIGH = 0x0c4,
47 PROFILE_COUNT = 0x144,
48 SIGNATURE_ENABLE = 0x150,
49 AE_MISC_CONTROL = 0x160,
50 LOCAL_CSR_STATUS = 0x180,
54 FCU_CONTROL = 0x00,
55 FCU_STATUS = 0x04,
56 FCU_DRAM_ADDR_LO = 0x0c,
57 FCU_DRAM_ADDR_HI = 0x10,
58 FCU_RAMBASE_ADDR_HI = 0x14,
59 FCU_RAMBASE_ADDR_LO = 0x18
63 FCU_CONTROL_C4XXX = 0x00,
64 FCU_STATUS_C4XXX = 0x04,
65 FCU_STATUS1_C4XXX = 0x0c,
66 FCU_AE_LOADED_C4XXX = 0x10,
67 FCU_DRAM_ADDR_LO_C4XXX = 0x14,
68 FCU_DRAM_ADDR_HI_C4XXX = 0x18,
72 FCU_CONTROL_4XXX = 0x00,
73 FCU_STATUS_4XXX = 0x04,
74 FCU_ME_BROADCAST_MASK_TYPE = 0x08,
75 FCU_AE_LOADED_4XXX = 0x10,
76 FCU_DRAM_ADDR_LO_4XXX = 0x14,
77 FCU_DRAM_ADDR_HI_4XXX = 0x18,
81 FCU_CTRL_CMD_NOOP = 0,
88 FCU_STS_NO_STS = 0,
95 #define UA_ECS (0x1 << 31)
97 #define ACS_ACNO 0x7
98 #define CE_ENABLE_BITPOS 0x8
109 #define CE_NN_MODE (0x1 << CE_NN_MODE_BITPOS)
110 #define CE_INUSE_CONTEXTS (0x1 << CE_INUSE_CONTEXTS_BITPOS)
111 #define XCWE_VOLUNTARY (0x1)
112 #define LCS_STATUS (0x1)
114 #define GLOBAL_CSR 0xA00
115 #define FCU_CTRL_BROADCAST_POS 0x4
116 #define FCU_CTRL_AE_POS 0x8
117 #define FCU_AUTH_STS_MASK 0x7
118 #define FCU_STS_DONE_POS 0x9
119 #define FCU_STS_AUTHFWLD_POS 0X8
120 #define FCU_LOADED_AE_POS 0x16
124 #define FCU_OFFSET 0x8c0
125 #define FCU_OFFSET_C4XXX 0x1000
126 #define FCU_OFFSET_4XXX 0x1000
131 #define ICP_QAT_AE_OFFSET 0x20000
132 #define ICP_QAT_AE_OFFSET_C4XXX 0x40000
133 #define ICP_QAT_AE_OFFSET_4XXX 0x600000
134 #define ICP_QAT_CAP_OFFSET (ICP_QAT_AE_OFFSET + 0x10000)
135 #define ICP_QAT_CAP_OFFSET_C4XXX 0x70000
136 #define ICP_QAT_CAP_OFFSET_4XXX 0x640000
137 #define LOCAL_TO_XFER_REG_OFFSET 0x800
138 #define ICP_QAT_EP_OFFSET 0x3a000
139 #define ICP_QAT_EP_OFFSET_C4XXX 0x60000
140 #define ICP_QAT_EP_OFFSET_4XXX 0x200000 /* HI MMIO CSRs */
141 #define MEM_CFG_ERR_BIT 0x20
192 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr)))
200 (AE_XFER(handle, ae) + (((reg)&0xff) << 2))