Lines Matching +full:e +full:- +full:book
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
78 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
80 PUC_PORT_3S, 0x10, 0, -1,
85 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
87 PUC_PORT_2S, 0x10, 0, -1,
92 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
94 PUC_PORT_4S, 0x10, 0, -1,
99 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
101 PUC_PORT_3S, 0x10, 0, -1,
106 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
108 PUC_PORT_3S, 0x10, 0, -1,
113 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
115 PUC_PORT_3S, 0x10, 0, -1,
120 "VScom PCI-800",
126 "VScom PCI-400",
132 "VScom PCI-200",
139 * Appears to be the same as Chase Research PLC PCI-FAST8
140 * and Perle PCI-FAST8 Multi-Port serial cards.
156 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
168 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
181 PUC_PORT_8S, 0x14, -1, -1,
187 * based on Exar PCI chips, f. e. the 8 port variants on XR17V258IV.
189 * PCIe-PCI-bridge.
195 PUC_PORT_4S, 0x10, 0, -1,
202 PUC_PORT_8S, 0x10, 0, -1,
209 PUC_PORT_8S, 0x10, 0, -1,
216 PUC_PORT_4S, 0x10, 0, -1,
223 PUC_PORT_4S, 0x10, 0, -1,
230 PUC_PORT_8S, 0x10, 0, -1,
435 PUC_PORT_1S2P, 0x10, -1, 0,
442 PUC_PORT_1S2P, 0x10, -1, 0,
449 PUC_PORT_1S2P, 0x10, -1, 0,
492 PUC_PORT_8S, 0x10, -1, -1,
497 "Brainboxes UC-268",
503 "Brainboxes UC-257",
509 "Brainboxes UC-257",
515 "Brainboxes UC-257",
521 "Brainboxes UC-279",
527 "Brainboxes UC-313",
533 "Brainboxes UC-313",
539 "Brainboxes UC-313",
545 "Brainboxes UC-310",
551 "Brainboxes UC-302",
557 "Brainboxes UC-302",
563 "Brainboxes UC-302",
569 "Brainboxes UC-431",
575 "Brainboxes UC-420",
581 "Brainboxes UC-475",
587 "Brainboxes UC-475",
593 "Brainboxes UC-607",
599 "Brainboxes UC-607",
605 "Brainboxes UC-607",
611 "Brainboxes UC-357",
617 "Brainboxes UC-357",
623 "Brainboxes UC-357",
629 "Brainboxes UP-189",
635 "Brainboxes UP-189",
641 "Brainboxes UP-189",
647 "Brainboxes UC-346",
653 "Brainboxes UC-346",
659 "Brainboxes UP-200",
665 "Brainboxes UP-200",
671 "Brainboxes UP-200",
677 "Brainboxes UC-101",
683 "Brainboxes UC-203",
689 "Brainboxes UC-203",
695 "Brainboxes UP-869",
701 "Brainboxes UP-869",
707 "Brainboxes UP-869",
713 "Brainboxes UP-880",
719 "Brainboxes UP-880",
725 "Brainboxes UP-880",
731 "Brainboxes UC-368",
737 "Brainboxes UC-253",
743 "Brainboxes UC-260",
749 "Brainboxes UC-836",
755 "Intashield IS-200",
761 "Intashield IS-400",
767 "Brainboxes PX-279",
773 "Brainboxes UC-414",
779 "Brainboxes PX-260",
781 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
786 "Brainboxes PX-320",
788 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
793 "Brainboxes PX-313",
795 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
800 "Brainboxes PX-310",
802 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
807 "Brainboxes PX-346",
809 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
814 "Brainboxes PX-368",
816 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
821 "Brainboxes PX-420",
823 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
828 "Brainboxes PX-431",
830 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
835 "Brainboxes PX-820",
837 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
842 "Brainboxes PX-831",
844 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
849 "Brainboxes PX-257",
851 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
856 "Brainboxes PX-246",
858 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
863 "Brainboxes PX-846",
865 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
870 "Brainboxes PX-857",
872 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
877 "Brainboxes PX-101",
879 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
884 "Brainboxes PX-475",
886 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
891 "Brainboxes PX-803",
893 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
898 "Intashield IX-100",
900 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
905 "Intashield IX-200",
907 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
912 "Intashield IX-400",
914 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
919 "Quatech QSC-100",
920 -3, /* max 8x clock rate */
926 "Quatech DSC-100",
927 -1, /* max 2x clock rate */
933 "Quatech DSC-200/300",
934 -1, /* max 2x clock rate */
940 "Quatech QSC-200/300",
941 -3, /* max 8x clock rate */
947 "Quatech ESC-100D",
948 -3, /* max 8x clock rate */
954 "Quatech ESC-100M",
955 -3, /* max 8x clock rate */
961 "Quatech QSCLP-100",
962 -1, /* max 2x clock rate */
968 "Quatech DSCLP-100",
969 -1, /* max 3x clock rate */
975 "Quatech DSCLP-200/300",
976 -1, /* max 2x clock rate */
982 "Quatech ESCLP-100",
983 -3, /* max 8x clock rate */
989 "Moxa Technologies, Smartio CP-102E/PCIe",
991 PUC_PORT_2S, 0x14, 0, -1,
996 "Moxa Technologies, Smartio CP-102EL/PCIe",
998 PUC_PORT_2S, 0x14, 0, -1,
1009 "Moxa Technologies, Smartio CP-104UL/PCI",
1015 "Moxa Technologies, Smartio CP-104JU/PCI",
1021 "Moxa Technologies, Smartio CP-104EL/PCIe",
1027 "Moxa Technologies, Smartio CP-104EL-A/PCIe",
1029 PUC_PORT_4S, 0x14, 0, -1,
1034 "Moxa Technologies, CP-112UL",
1040 "Moxa Technologies, Industio CP-114",
1046 "Moxa Technologies, Smartio CP-114EL/PCIe",
1048 PUC_PORT_4S, 0x14, 0, -1,
1053 "Moxa Technologies, Smartio CP-118EL-A/PCIe",
1055 PUC_PORT_8S, 0x14, 0, -1,
1072 "Moxa Technologies, CP-168EL/PCIe",
1078 "Moxa Technologies, Smartio CP-168EL-A/PCIe",
1080 PUC_PORT_8S, 0x14, 0, -1,
1087 PUC_PORT_2S, 0x10, 0, -1,
1094 PUC_PORT_4S, 0x10, 0, -1,
1101 PUC_PORT_8S, 0x10, 0, -1,
1108 PUC_PORT_8S, 0x10, 0, -1,
1115 PUC_PORT_2S, 0x10, 0, -1,
1122 PUC_PORT_4S, 0x10, 0, -1,
1130 PUC_PORT_8S, 0x10, 0, -1,
1135 * The Advantech PCI-1602 Rev. A use the first two ports of an Oxford
1137 * that they drive the RS-422/485 transmitters after power-on until a
1141 "Advantech PCI-1602 Rev. A",
1147 /* Advantech PCI-1602 Rev. B1/PCI-1603 are also based on OXuPCI952. */
1149 "Advantech 2-port PCI (PCI-1602 Rev. B1/PCI-1603)",
1174 "Lava Computers Quattro-PCI A",
1180 "Lava Computers Quattro-PCI B",
1206 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
1217 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
1221 "I-O DATA RSA-PCI2/R",
1245 "Kuroutoshikou SERIAL4P-LPPCI2",
1344 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
1353 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1360 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1367 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1374 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1381 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1388 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1395 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1402 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1407 "VScom PCI-100L",
1413 "VScom PCI-200L",
1425 * VScom (Titan?) PCI-800L. More modern variant of the
1426 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
1434 "Titan VScom PCI-800L",
1436 PUC_PORT_8S, 0x14, -1, -1,
1441 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
1446 "Titan PCI-800H",
1452 "Titan PCI-800H",
1458 "Titan PCI-200H",
1464 "Titan VScom PCI-200HV2",
1470 "Titan VScom PCIex-800H",
1476 "Titan VScom PCIex-800H",
1500 "Syba Tech Ltd. PCI-4S2P-550-ECP",
1502 PUC_PORT_4S1P, 0x10, 0, -1,
1507 "Sunix SER5xxxx 2-port serial",
1513 "Sunix SER5xxxx 4-port serial",
1519 "Sunix SER5xxxx 8-port serial",
1521 PUC_PORT_8S, -1, -1, -1,
1526 "Sunix MIO5xxxx 1-port serial and 1284 Printer port",
1528 PUC_PORT_1S1P, -1, -1, -1,
1533 "Sunix MIO5xxxx 2-port serial and 1284 Printer port",
1535 PUC_PORT_2S1P, -1, -1, -1,
1540 "Sunix MIO5xxxx 4-port serial and 1284 Printer port",
1542 PUC_PORT_4S1P, -1, -1, -1,
1547 "Feasso PCI FPP-02 2S1P",
1559 "Decision Computer Inc, PCCOM 4-port serial",
1565 "Decision Computer Inc, PCCOM 8-port serial",
1589 "NetMos NM9835 based 1-port serial",
1595 "NetMos NM9835 based 2-port serial",
1655 "IC Book Labs Gunboat x4 Lite",
1662 "IC Book Labs Gunboat x4 Pro",
1669 "IC Book Labs Ironclad x8 Lite",
1676 "IC Book Labs Ironclad x8 Pro",
1683 "IC Book Labs Dreadnought x16 Pro",
1690 "IC Book Labs Dreadnought x16 Lite",
1697 "IC Book Labs Gunboat x2 Low Profile",
1703 "IC Book Labs Gunboat x4 Low Profile",
1732 cfg = sc->sc_cfg; in puc_config_advantech()
1733 switch (cfg->subvendor) { in puc_config_advantech()
1735 switch (cfg->device) { in puc_config_advantech()
1748 dev = sc->sc_dev; in puc_config_advantech()
1770 for (i = 0; i < sc->sc_nports; ++i) { in puc_config_advantech()
1772 bar = puc_get_bar(sc, cfg->rid + i * cfg->d_rid); in puc_config_advantech()
1781 printf("RS-232\n"); in puc_config_advantech()
1784 printf("RS-422/RS-485, active-%s auto-DTR\n", in puc_config_advantech()
1789 bus_write_1(bar->b_res, REG_SPR, REG_ACR); in puc_config_advantech()
1790 bus_write_1(bar->b_res, REG_ICR, acr); in puc_config_advantech()
1819 const struct puc_cfg *cfg = sc->sc_cfg; in puc_config_diva()
1822 if (cfg->subdevice == 0x1282) /* Everest SP */ in puc_config_diva()
1824 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ in puc_config_diva()
1872 const struct puc_cfg *cfg = sc->sc_cfg; in puc_config_moxa()
1875 if (port == 3 && (cfg->device == 0x1045 || in puc_config_moxa()
1876 cfg->device == 0x1144)) in puc_config_moxa()
1889 const struct puc_cfg *cfg = sc->sc_cfg; in puc_config_quatech()
1899 bar = puc_get_bar(sc, cfg->rid); in puc_config_quatech()
1902 bus_write_1(bar->b_res, REG_LCR, LCR_DLAB); in puc_config_quatech()
1903 bus_write_1(bar->b_res, REG_SPR, 0); in puc_config_quatech()
1904 v0 = bus_read_1(bar->b_res, REG_SPR); in puc_config_quatech()
1905 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock); in puc_config_quatech()
1906 v1 = bus_read_1(bar->b_res, REG_SPR); in puc_config_quatech()
1907 bus_write_1(bar->b_res, REG_LCR, 0); in puc_config_quatech()
1908 sc->sc_cfg_data = (v0 << 8) | v1; in puc_config_quatech()
1909 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { in puc_config_quatech()
1914 device_printf(sc->sc_dev, "warning: extra features " in puc_config_quatech()
1915 "not usable -- SPAD compatibility enabled\n"); in puc_config_quatech()
1921 * that the SPAD jumper is not set and that a non- in puc_config_quatech()
1925 device_printf(sc->sc_dev, "fixed clock rate " in puc_config_quatech()
1927 if (v0 < -cfg->clock) in puc_config_quatech()
1928 device_printf(sc->sc_dev, "warning: " in puc_config_quatech()
1940 device_printf(sc->sc_dev, "clock rate multiplier of " in puc_config_quatech()
1941 "%d selected\n", 1 << -cfg->clock); in puc_config_quatech()
1944 v0 = (sc->sc_cfg_data >> 8) & 0xff; in puc_config_quatech()
1945 v1 = sc->sc_cfg_data & 0xff; in puc_config_quatech()
1946 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { in puc_config_quatech()
1961 *res = DEFAULT_RCLK << -cfg->clock; in puc_config_quatech()
1966 v0 = (sc->sc_cfg_data >> 8) & 0xff; in puc_config_quatech()
1967 v1 = sc->sc_cfg_data & 0xff; in puc_config_quatech()
1968 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ? in puc_config_quatech()
1982 const struct puc_cfg *cfg = sc->sc_cfg; in puc_config_syba()
1989 bar = puc_get_bar(sc, cfg->rid); in puc_config_syba()
1994 bus_write_1(bar->b_res, 0x250, 0x89); in puc_config_syba()
1995 bus_write_1(bar->b_res, 0x3f0, 0x87); in puc_config_syba()
1996 bus_write_1(bar->b_res, 0x3f0, 0x87); in puc_config_syba()
2000 bus_write_1(bar->b_res, efir, 0x09); in puc_config_syba()
2001 v = bus_read_1(bar->b_res, efir + 1); in puc_config_syba()
2004 bus_write_1(bar->b_res, efir, 0x16); in puc_config_syba()
2005 v = bus_read_1(bar->b_res, efir + 1); in puc_config_syba()
2006 bus_write_1(bar->b_res, efir, 0x16); in puc_config_syba()
2007 bus_write_1(bar->b_res, efir + 1, v | 0x04); in puc_config_syba()
2008 bus_write_1(bar->b_res, efir, 0x16); in puc_config_syba()
2009 bus_write_1(bar->b_res, efir + 1, v & ~0x04); in puc_config_syba()
2011 bus_write_1(bar->b_res, efir, 0x23); in puc_config_syba()
2012 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); in puc_config_syba()
2013 bus_write_1(bar->b_res, efir, 0x24); in puc_config_syba()
2014 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); in puc_config_syba()
2015 bus_write_1(bar->b_res, efir, 0x25); in puc_config_syba()
2016 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); in puc_config_syba()
2017 bus_write_1(bar->b_res, efir, 0x17); in puc_config_syba()
2018 bus_write_1(bar->b_res, efir + 1, 0x03); in puc_config_syba()
2019 bus_write_1(bar->b_res, efir, 0x28); in puc_config_syba()
2020 bus_write_1(bar->b_res, efir + 1, 0x43); in puc_config_syba()
2023 bus_write_1(bar->b_res, 0x250, 0xaa); in puc_config_syba()
2024 bus_write_1(bar->b_res, 0x3f0, 0xaa); in puc_config_syba()
2055 const struct puc_cfg *cfg = sc->sc_cfg; in puc_config_siig()
2059 if (cfg->ports == PUC_PORT_8S) { in puc_config_siig()
2060 *res = (port > 4) ? 8 * (port - 4) : 0; in puc_config_siig()
2065 if (cfg->ports == PUC_PORT_8S) { in puc_config_siig()
2069 if (cfg->ports == PUC_PORT_2S1P) { in puc_config_siig()
2126 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); in puc_config_timedia()
2130 subdev = pci_get_subdevice(sc->sc_dev); in puc_config_timedia()
2136 sc->sc_cfg_data = subdevs[dev].ports; in puc_config_timedia()
2137 *res = sc->sc_cfg_data; in puc_config_timedia()
2149 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; in puc_config_timedia()
2171 if (pci_get_revid(sc->sc_dev) == 1) in puc_config_oxford_pci954()
2186 const struct puc_cfg *cfg = sc->sc_cfg; in puc_config_oxford_pcie()
2193 device_printf(sc->sc_dev, "%d UARTs detected\n", in puc_config_oxford_pcie()
2194 sc->sc_nports); in puc_config_oxford_pcie()
2197 bar = puc_get_bar(sc, cfg->rid); in puc_config_oxford_pcie()
2200 for (idx = 0; idx < sc->sc_nports; idx++) { in puc_config_oxford_pcie()
2201 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + in puc_config_oxford_pcie()
2203 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, in puc_config_oxford_pcie()
2215 * cosmetic side-effects at worst; in PUC_CFG_GET_DESC, in puc_config_oxford_pcie()
2216 * sc->sc_cfg_data will not contain the true number of in puc_config_oxford_pcie()
2220 * The check is for initialization of sc->sc_bar[idx], in puc_config_oxford_pcie()
2225 if (sc->sc_bar[idx++].b_rid != -1) { in puc_config_oxford_pcie()
2226 sc->sc_cfg_data = 16; in puc_config_oxford_pcie()
2227 *res = sc->sc_cfg_data; in puc_config_oxford_pcie()
2232 bar = puc_get_bar(sc, cfg->rid); in puc_config_oxford_pcie()
2236 value = bus_read_1(bar->b_res, 0x04); in puc_config_oxford_pcie()
2240 sc->sc_cfg_data = value; in puc_config_oxford_pcie()
2241 *res = sc->sc_cfg_data; in puc_config_oxford_pcie()
2287 *res = (port < 3) ? 0 : (port - 2) << 3; in puc_config_titan()