Lines Matching +full:pci +full:- +full:x
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 * PCI "universal" communications card driver configuration data (used to
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
79 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
81 PUC_PORT_3S, 0x10, 0, -1,
86 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
88 PUC_PORT_2S, 0x10, 0, -1,
93 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
95 PUC_PORT_4S, 0x10, 0, -1,
100 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
102 PUC_PORT_3S, 0x10, 0, -1,
107 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
109 PUC_PORT_3S, 0x10, 0, -1,
114 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
116 PUC_PORT_3S, 0x10, 0, -1,
121 "VScom PCI-800",
127 "VScom PCI-400",
133 "VScom PCI-200",
140 * Appears to be the same as Chase Research PLC PCI-FAST8
141 * and Perle PCI-FAST8 Multi-Port serial cards.
157 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
169 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
182 PUC_PORT_8S, 0x14, -1, -1,
188 * based on Exar PCI chips, f. e. the 8 port variants on XR17V258IV.
190 * PCIe-PCI-bridge.
194 "Digi Neo PCI 4 Port",
196 PUC_PORT_4S, 0x10, 0, -1,
201 "Digi Neo PCI 8 Port",
203 PUC_PORT_8S, 0x10, 0, -1,
210 PUC_PORT_8S, 0x10, 0, -1,
217 PUC_PORT_4S, 0x10, 0, -1,
224 PUC_PORT_4S, 0x10, 0, -1,
231 PUC_PORT_8S, 0x10, 0, -1,
314 "SIIG Cyber I/O PCI 16C550 (10x family)",
320 "SIIG Cyber I/O PCI 16C650 (10x family)",
326 "SIIG Cyber I/O PCI 16C850 (10x family)",
332 "SIIG Cyber Parallel Dual PCI (10x family)",
338 "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
344 "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
350 "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
356 "SIIG Cyber 2S1P PCI 16C550 (10x family)",
362 "SIIG Cyber 2S1P PCI 16C650 (10x family)",
368 "SIIG Cyber 2S1P PCI 16C850 (10x family)",
374 "SIIG Cyber 4S PCI 16C550 (10x family)",
380 "SIIG Cyber 4S PCI 16C650 (10x family)",
386 "SIIG Cyber 4S PCI 16C850 (10x family)",
392 "SIIG Cyber I/O PCI 16C550 (20x family)",
398 "SIIG Cyber I/O PCI 16C650 (20x family)",
404 "SIIG Cyber I/O PCI 16C850 (20x family)",
410 "SIIG Cyber Parallel Dual PCI (20x family)",
416 "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
422 "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
428 "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
434 "SIIG Cyber 2P1S PCI 16C550 (20x family)",
436 PUC_PORT_1S2P, 0x10, -1, 0,
441 "SIIG Cyber 2P1S PCI 16C650 (20x family)",
443 PUC_PORT_1S2P, 0x10, -1, 0,
448 "SIIG Cyber 2P1S PCI 16C850 (20x family)",
450 PUC_PORT_1S2P, 0x10, -1, 0,
455 "SIIG Cyber 4S PCI 16C550 (20x family)",
461 "SIIG Cyber 4S PCI 16C650 (20x family)",
467 "SIIG Cyber 4S PCI 16C850 (20x family)",
473 "SIIG Cyber 2S1P PCI 16C550 (20x family)",
479 "SIIG Cyber 2S1P PCI 16C650 (20x family)",
485 "SIIG Cyber 2S1P PCI 16C850 (20x family)",
491 "SIIG PS8000 8S PCI 16C650 (20x family)",
493 PUC_PORT_8S, 0x10, -1, -1,
498 "Brainboxes UC-268",
504 "Brainboxes UC-257",
510 "Brainboxes UC-257",
516 "Brainboxes UC-257",
522 "Brainboxes UC-279",
528 "Brainboxes UC-313",
534 "Brainboxes UC-313",
540 "Brainboxes UC-313",
546 "Brainboxes UC-310",
552 "Brainboxes UC-302",
558 "Brainboxes UC-302",
564 "Brainboxes UC-302",
570 "Brainboxes UC-431",
576 "Brainboxes UC-420",
582 "Brainboxes UC-475",
588 "Brainboxes UC-475",
594 "Brainboxes UC-607",
600 "Brainboxes UC-607",
606 "Brainboxes UC-607",
612 "Brainboxes UC-357",
618 "Brainboxes UC-357",
624 "Brainboxes UC-357",
630 "Brainboxes UP-189",
636 "Brainboxes UP-189",
642 "Brainboxes UP-189",
648 "Brainboxes UC-346",
654 "Brainboxes UC-346",
660 "Brainboxes UP-200",
666 "Brainboxes UP-200",
672 "Brainboxes UP-200",
678 "Brainboxes UC-101",
684 "Brainboxes UC-203",
690 "Brainboxes UC-203",
696 "Brainboxes UP-869",
702 "Brainboxes UP-869",
708 "Brainboxes UP-869",
714 "Brainboxes UP-880",
720 "Brainboxes UP-880",
726 "Brainboxes UP-880",
732 "Brainboxes UC-368",
738 "Brainboxes UC-253",
744 "Brainboxes UC-260",
750 "Brainboxes UC-836",
756 "Intashield IS-200",
762 "Intashield IS-400",
768 "Brainboxes PX-279",
774 "Brainboxes UC-414",
780 "Brainboxes PX-260",
782 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
787 "Brainboxes PX-320",
789 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
794 "Brainboxes PX-313",
796 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
801 "Brainboxes PX-310",
803 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
808 "Brainboxes PX-346",
810 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
815 "Brainboxes PX-368",
817 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
822 "Brainboxes PX-420",
824 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
829 "Brainboxes PX-431",
831 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
836 "Brainboxes PX-820",
838 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
843 "Brainboxes PX-831",
845 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
850 "Brainboxes PX-257",
852 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
857 "Brainboxes PX-246",
859 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
864 "Brainboxes PX-846",
866 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
871 "Brainboxes PX-857",
873 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
878 "Brainboxes PX-101",
880 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
885 "Brainboxes PX-475",
887 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
892 "Brainboxes PX-803",
894 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
899 "Intashield IX-100",
901 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
906 "Intashield IX-200",
908 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
913 "Intashield IX-400",
915 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
920 "Quatech QSC-100",
921 -3, /* max 8x clock rate */
927 "Quatech DSC-100",
928 -1, /* max 2x clock rate */
934 "Quatech DSC-200/300",
935 -1, /* max 2x clock rate */
941 "Quatech QSC-200/300",
942 -3, /* max 8x clock rate */
948 "Quatech ESC-100D",
949 -3, /* max 8x clock rate */
955 "Quatech ESC-100M",
956 -3, /* max 8x clock rate */
962 "Quatech QSCLP-100",
963 -1, /* max 2x clock rate */
969 "Quatech DSCLP-100",
970 -1, /* max 3x clock rate */
976 "Quatech DSCLP-200/300",
977 -1, /* max 2x clock rate */
983 "Quatech ESCLP-100",
984 -3, /* max 8x clock rate */
990 "Moxa Technologies, Smartio CP-102E/PCIe",
992 PUC_PORT_2S, 0x14, 0, -1,
997 "Moxa Technologies, Smartio CP-102EL/PCIe",
999 PUC_PORT_2S, 0x14, 0, -1,
1004 "Moxa Technologies, Smartio C104H/PCI",
1010 "Moxa Technologies, Smartio CP-104UL/PCI",
1016 "Moxa Technologies, Smartio CP-104JU/PCI",
1022 "Moxa Technologies, Smartio CP-104EL/PCIe",
1028 "Moxa Technologies, Smartio CP-104EL-A/PCIe",
1030 PUC_PORT_4S, 0x14, 0, -1,
1035 "Moxa Technologies, CP-112UL",
1041 "Moxa Technologies, Industio CP-114",
1047 "Moxa Technologies, Smartio CP-114EL/PCIe",
1049 PUC_PORT_4S, 0x14, 0, -1,
1054 "Moxa Technologies, Smartio CP-118EL-A/PCIe",
1056 PUC_PORT_8S, 0x14, 0, -1,
1061 "Moxa Technologies, C168H/PCI",
1067 "Moxa Technologies, C168U/PCI",
1073 "Moxa Technologies, CP-168EL/PCIe",
1079 "Moxa Technologies, Smartio CP-168EL-A/PCIe",
1081 PUC_PORT_8S, 0x14, 0, -1,
1088 PUC_PORT_2S, 0x10, 0, -1,
1095 PUC_PORT_4S, 0x10, 0, -1,
1102 PUC_PORT_8S, 0x10, 0, -1,
1109 PUC_PORT_8S, 0x10, 0, -1,
1116 PUC_PORT_2S, 0x10, 0, -1,
1123 PUC_PORT_4S, 0x10, 0, -1,
1131 PUC_PORT_8S, 0x10, 0, -1,
1136 * The Advantech PCI-1602 Rev. A use the first two ports of an Oxford
1138 * that they drive the RS-422/485 transmitters after power-on until a
1142 "Advantech PCI-1602 Rev. A",
1148 /* Advantech PCI-1602 Rev. B1/PCI-1603 are also based on OXuPCI952. */
1150 "Advantech 2-port PCI (PCI-1602 Rev. B1/PCI-1603)",
1175 "Lava Computers Quattro-PCI A",
1181 "Lava Computers Quattro-PCI B",
1207 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
1218 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
1222 "I-O DATA RSA-PCI2/R",
1228 "SIIG Cyber 4 PCI 16550",
1234 "SIIG Cyber 4S PCI 16C650 (20x family)",
1246 "Kuroutoshikou SERIAL4P-LPPCI2",
1265 "SIIG Cyber Serial Dual PCI 16C850",
1337 * Oxford Semiconductor PCI Express Expresso family
1339 * Found in many 'native' PCI Express serial boards such as:
1345 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
1354 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1361 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1368 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1375 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1382 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1389 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1396 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1403 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1408 "VScom PCI-100L",
1414 "VScom PCI-200L",
1426 * VScom (Titan?) PCI-800L. More modern variant of the
1427 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
1435 "Titan VScom PCI-800L",
1437 PUC_PORT_8S, 0x14, -1, -1,
1442 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
1443 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
1444 * device ID 3 and PCI device 1 device ID 4.
1447 "Titan PCI-800H",
1453 "Titan PCI-800H",
1459 "Titan PCI-200H",
1465 "Titan VScom PCI-200HV2",
1471 "Titan VScom PCIex-800H",
1477 "Titan VScom PCIex-800H",
1483 "Avlab Technology, PCI IO 2S",
1489 "Avlab Low Profile PCI 4 Serial",
1495 "Avlab Low Profile PCI 4 Serial",
1501 "Syba Tech Ltd. PCI-4S2P-550-ECP",
1503 PUC_PORT_4S1P, 0x10, 0, -1,
1508 "Sunix SER5xxxx 2-port serial",
1514 "Sunix SER5xxxx 4-port serial",
1520 "Sunix SER5xxxx 8-port serial",
1522 PUC_PORT_8S, -1, -1, -1,
1527 "Sunix MIO5xxxx 1-port serial and 1284 Printer port",
1529 PUC_PORT_1S1P, -1, -1, -1,
1534 "Sunix MIO5xxxx 2-port serial and 1284 Printer port",
1536 PUC_PORT_2S1P, -1, -1, -1,
1541 "Sunix MIO5xxxx 4-port serial and 1284 Printer port",
1543 PUC_PORT_4S1P, -1, -1, -1,
1548 "Feasso PCI FPP-02 2S1P",
1554 "Sun 1040 PCI Quad Serial",
1560 "Decision Computer Inc, PCCOM 4-port serial",
1566 "Decision Computer Inc, PCCOM 8-port serial",
1590 "NetMos NM9835 based 1-port serial",
1596 "NetMos NM9835 based 2-port serial",
1750 cfg = sc->sc_cfg; in puc_config_advantech()
1751 switch (cfg->subvendor) { in puc_config_advantech()
1753 switch (cfg->device) { in puc_config_advantech()
1766 dev = sc->sc_dev; in puc_config_advantech()
1788 for (i = 0; i < sc->sc_nports; ++i) { in puc_config_advantech()
1790 bar = puc_get_bar(sc, cfg->rid + i * cfg->d_rid); in puc_config_advantech()
1799 printf("RS-232\n"); in puc_config_advantech()
1802 printf("RS-422/RS-485, active-%s auto-DTR\n", in puc_config_advantech()
1807 bus_write_1(bar->b_res, REG_SPR, REG_ACR); in puc_config_advantech()
1808 bus_write_1(bar->b_res, REG_ICR, acr); in puc_config_advantech()
1837 const struct puc_cfg *cfg = sc->sc_cfg; in puc_config_diva()
1840 if (cfg->subdevice == 0x1282) /* Everest SP */ in puc_config_diva()
1842 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ in puc_config_diva()
1890 const struct puc_cfg *cfg = sc->sc_cfg; in puc_config_moxa()
1893 if (port == 3 && (cfg->device == 0x1045 || in puc_config_moxa()
1894 cfg->device == 0x1144)) in puc_config_moxa()
1907 const struct puc_cfg *cfg = sc->sc_cfg; in puc_config_quatech()
1917 bar = puc_get_bar(sc, cfg->rid); in puc_config_quatech()
1920 bus_write_1(bar->b_res, REG_LCR, LCR_DLAB); in puc_config_quatech()
1921 bus_write_1(bar->b_res, REG_SPR, 0); in puc_config_quatech()
1922 v0 = bus_read_1(bar->b_res, REG_SPR); in puc_config_quatech()
1923 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock); in puc_config_quatech()
1924 v1 = bus_read_1(bar->b_res, REG_SPR); in puc_config_quatech()
1925 bus_write_1(bar->b_res, REG_LCR, 0); in puc_config_quatech()
1926 sc->sc_cfg_data = (v0 << 8) | v1; in puc_config_quatech()
1927 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { in puc_config_quatech()
1932 device_printf(sc->sc_dev, "warning: extra features " in puc_config_quatech()
1933 "not usable -- SPAD compatibility enabled\n"); in puc_config_quatech()
1939 * that the SPAD jumper is not set and that a non- in puc_config_quatech()
1943 device_printf(sc->sc_dev, "fixed clock rate " in puc_config_quatech()
1945 if (v0 < -cfg->clock) in puc_config_quatech()
1946 device_printf(sc->sc_dev, "warning: " in puc_config_quatech()
1958 device_printf(sc->sc_dev, "clock rate multiplier of " in puc_config_quatech()
1959 "%d selected\n", 1 << -cfg->clock); in puc_config_quatech()
1962 v0 = (sc->sc_cfg_data >> 8) & 0xff; in puc_config_quatech()
1963 v1 = sc->sc_cfg_data & 0xff; in puc_config_quatech()
1964 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { in puc_config_quatech()
1979 *res = DEFAULT_RCLK << -cfg->clock; in puc_config_quatech()
1984 v0 = (sc->sc_cfg_data >> 8) & 0xff; in puc_config_quatech()
1985 v1 = sc->sc_cfg_data & 0xff; in puc_config_quatech()
1986 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ? in puc_config_quatech()
2000 const struct puc_cfg *cfg = sc->sc_cfg; in puc_config_syba()
2007 bar = puc_get_bar(sc, cfg->rid); in puc_config_syba()
2012 bus_write_1(bar->b_res, 0x250, 0x89); in puc_config_syba()
2013 bus_write_1(bar->b_res, 0x3f0, 0x87); in puc_config_syba()
2014 bus_write_1(bar->b_res, 0x3f0, 0x87); in puc_config_syba()
2018 bus_write_1(bar->b_res, efir, 0x09); in puc_config_syba()
2019 v = bus_read_1(bar->b_res, efir + 1); in puc_config_syba()
2022 bus_write_1(bar->b_res, efir, 0x16); in puc_config_syba()
2023 v = bus_read_1(bar->b_res, efir + 1); in puc_config_syba()
2024 bus_write_1(bar->b_res, efir, 0x16); in puc_config_syba()
2025 bus_write_1(bar->b_res, efir + 1, v | 0x04); in puc_config_syba()
2026 bus_write_1(bar->b_res, efir, 0x16); in puc_config_syba()
2027 bus_write_1(bar->b_res, efir + 1, v & ~0x04); in puc_config_syba()
2029 bus_write_1(bar->b_res, efir, 0x23); in puc_config_syba()
2030 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); in puc_config_syba()
2031 bus_write_1(bar->b_res, efir, 0x24); in puc_config_syba()
2032 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); in puc_config_syba()
2033 bus_write_1(bar->b_res, efir, 0x25); in puc_config_syba()
2034 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); in puc_config_syba()
2035 bus_write_1(bar->b_res, efir, 0x17); in puc_config_syba()
2036 bus_write_1(bar->b_res, efir + 1, 0x03); in puc_config_syba()
2037 bus_write_1(bar->b_res, efir, 0x28); in puc_config_syba()
2038 bus_write_1(bar->b_res, efir + 1, 0x43); in puc_config_syba()
2041 bus_write_1(bar->b_res, 0x250, 0xaa); in puc_config_syba()
2042 bus_write_1(bar->b_res, 0x3f0, 0xaa); in puc_config_syba()
2073 const struct puc_cfg *cfg = sc->sc_cfg; in puc_config_siig()
2077 if (cfg->ports == PUC_PORT_8S) { in puc_config_siig()
2078 *res = (port > 4) ? 8 * (port - 4) : 0; in puc_config_siig()
2083 if (cfg->ports == PUC_PORT_8S) { in puc_config_siig()
2087 if (cfg->ports == PUC_PORT_2S1P) { in puc_config_siig()
2144 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); in puc_config_timedia()
2148 subdev = pci_get_subdevice(sc->sc_dev); in puc_config_timedia()
2154 sc->sc_cfg_data = subdevs[dev].ports; in puc_config_timedia()
2155 *res = sc->sc_cfg_data; in puc_config_timedia()
2167 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; in puc_config_timedia()
2189 if (pci_get_revid(sc->sc_dev) == 1) in puc_config_oxford_pci954()
2204 const struct puc_cfg *cfg = sc->sc_cfg; in puc_config_oxford_pcie()
2211 device_printf(sc->sc_dev, "%d UARTs detected\n", in puc_config_oxford_pcie()
2212 sc->sc_nports); in puc_config_oxford_pcie()
2215 bar = puc_get_bar(sc, cfg->rid); in puc_config_oxford_pcie()
2218 for (idx = 0; idx < sc->sc_nports; idx++) { in puc_config_oxford_pcie()
2219 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + in puc_config_oxford_pcie()
2221 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, in puc_config_oxford_pcie()
2233 * cosmetic side-effects at worst; in PUC_CFG_GET_DESC, in puc_config_oxford_pcie()
2234 * sc->sc_cfg_data will not contain the true number of in puc_config_oxford_pcie()
2238 * The check is for initialization of sc->sc_bar[idx], in puc_config_oxford_pcie()
2243 if (sc->sc_bar[idx++].b_rid != -1) { in puc_config_oxford_pcie()
2244 sc->sc_cfg_data = 16; in puc_config_oxford_pcie()
2245 *res = sc->sc_cfg_data; in puc_config_oxford_pcie()
2250 bar = puc_get_bar(sc, cfg->rid); in puc_config_oxford_pcie()
2254 value = bus_read_1(bar->b_res, 0x04); in puc_config_oxford_pcie()
2258 sc->sc_cfg_data = value; in puc_config_oxford_pcie()
2259 *res = sc->sc_cfg_data; in puc_config_oxford_pcie()
2305 *res = (port < 3) ? 0 : (port - 2) << 3; in puc_config_titan()
2333 bus_write_1(bar->b_res, /* OPT_IMRREG0 */ 0xc, 0xff); in puc_config_systembase()