Lines Matching +full:0 +full:x8014
72 { 0x0009, 0x7168, 0xffff, 0,
75 PUC_PORT_2S, 0x10, 0, 8,
78 { 0x103c, 0x1048, 0x103c, 0x1049,
81 PUC_PORT_3S, 0x10, 0, -1,
85 { 0x103c, 0x1048, 0x103c, 0x104a,
88 PUC_PORT_2S, 0x10, 0, -1,
92 { 0x103c, 0x1048, 0x103c, 0x104b,
95 PUC_PORT_4S, 0x10, 0, -1,
99 { 0x103c, 0x1048, 0x103c, 0x1223,
102 PUC_PORT_3S, 0x10, 0, -1,
106 { 0x103c, 0x1048, 0x103c, 0x1226,
109 PUC_PORT_3S, 0x10, 0, -1,
113 { 0x103c, 0x1048, 0x103c, 0x1282,
116 PUC_PORT_3S, 0x10, 0, -1,
120 { 0x10b5, 0x1076, 0x10b5, 0x1076,
123 PUC_PORT_8S, 0x18, 0, 8,
126 { 0x10b5, 0x1077, 0x10b5, 0x1077,
129 PUC_PORT_4S, 0x18, 0, 8,
132 { 0x10b5, 0x1103, 0x10b5, 0x1103,
135 PUC_PORT_2S, 0x18, 4, 0,
143 { 0x10b5, 0x9050, 0x12e0, 0x0021,
146 PUC_PORT_8S, 0x18, 0, 8,
149 { 0x10b5, 0x9050, 0x12e0, 0x0031,
152 PUC_PORT_4S, 0x18, 0, 8,
159 * network/misc (0x02/0x80) device.
161 { 0x10b5, 0x9050, 0xd84d, 0x6808,
164 PUC_PORT_2S, 0x18, 4, 0,
171 * network/misc (0x02/0x80) device.
173 { 0x10b5, 0x9050, 0xd84d, 0x6810,
175 0,
176 PUC_PORT_2P, 0x20, 4, 0,
179 { 0x10e8, 0x818e, 0xffff, 0,
182 PUC_PORT_8S, 0x14, -1, -1,
193 { 0x114f, 0x00b0, 0xffff, 0,
196 PUC_PORT_4S, 0x10, 0, -1,
200 { 0x114f, 0x00b1, 0xffff, 0,
203 PUC_PORT_8S, 0x10, 0, -1,
207 { 0x114f, 0x00f0, 0xffff, 0,
210 PUC_PORT_8S, 0x10, 0, -1,
214 { 0x114f, 0x00f1, 0xffff, 0,
217 PUC_PORT_4S, 0x10, 0, -1,
221 { 0x114f, 0x00f2, 0xffff, 0,
224 PUC_PORT_4S, 0x10, 0, -1,
228 { 0x114f, 0x00f3, 0xffff, 0,
231 PUC_PORT_8S, 0x10, 0, -1,
235 { 0x11fe, 0x8010, 0xffff, 0,
238 PUC_PORT_4S, 0x10, 0, 8,
241 { 0x11fe, 0x8011, 0xffff, 0,
244 PUC_PORT_4S, 0x10, 0, 8,
247 { 0x11fe, 0x8012, 0xffff, 0,
250 PUC_PORT_4S, 0x10, 0, 8,
253 { 0x11fe, 0x8013, 0xffff, 0,
256 PUC_PORT_4S, 0x10, 0, 8,
259 { 0x11fe, 0x8014, 0xffff, 0,
262 PUC_PORT_4S, 0x10, 0, 8,
265 { 0x11fe, 0x8015, 0xffff, 0,
268 PUC_PORT_4S, 0x10, 0, 8,
271 { 0x11fe, 0x8016, 0xffff, 0,
274 PUC_PORT_4S, 0x10, 0, 8,
277 { 0x11fe, 0x8017, 0xffff, 0,
280 PUC_PORT_12S, 0x10, 0, 8,
283 { 0x11fe, 0x8018, 0xffff, 0,
286 PUC_PORT_4S, 0x10, 0, 8,
289 { 0x11fe, 0x8019, 0xffff, 0,
292 PUC_PORT_4S, 0x10, 0, 8,
300 { 0x1014, 0x0297, 0xffff, 0,
303 PUC_PORT_4S, 0x10, 4, 0
313 { 0x131f, 0x1010, 0xffff, 0,
316 PUC_PORT_1S1P, 0x18, 4, 0,
319 { 0x131f, 0x1011, 0xffff, 0,
322 PUC_PORT_1S1P, 0x18, 4, 0,
325 { 0x131f, 0x1012, 0xffff, 0,
328 PUC_PORT_1S1P, 0x18, 4, 0,
331 { 0x131f, 0x1021, 0xffff, 0,
333 0,
334 PUC_PORT_2P, 0x18, 8, 0,
337 { 0x131f, 0x1030, 0xffff, 0,
340 PUC_PORT_2S, 0x18, 4, 0,
343 { 0x131f, 0x1031, 0xffff, 0,
346 PUC_PORT_2S, 0x18, 4, 0,
349 { 0x131f, 0x1032, 0xffff, 0,
352 PUC_PORT_2S, 0x18, 4, 0,
355 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
358 PUC_PORT_2S1P, 0x18, 4, 0,
361 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
364 PUC_PORT_2S1P, 0x18, 4, 0,
367 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
370 PUC_PORT_2S1P, 0x18, 4, 0,
373 { 0x131f, 0x1050, 0xffff, 0,
376 PUC_PORT_4S, 0x18, 4, 0,
379 { 0x131f, 0x1051, 0xffff, 0,
382 PUC_PORT_4S, 0x18, 4, 0,
385 { 0x131f, 0x1052, 0xffff, 0,
388 PUC_PORT_4S, 0x18, 4, 0,
391 { 0x131f, 0x2010, 0xffff, 0,
394 PUC_PORT_1S1P, 0x10, 4, 0,
397 { 0x131f, 0x2011, 0xffff, 0,
400 PUC_PORT_1S1P, 0x10, 4, 0,
403 { 0x131f, 0x2012, 0xffff, 0,
406 PUC_PORT_1S1P, 0x10, 4, 0,
409 { 0x131f, 0x2021, 0xffff, 0,
411 0,
412 PUC_PORT_2P, 0x10, 8, 0,
415 { 0x131f, 0x2030, 0xffff, 0,
418 PUC_PORT_2S, 0x10, 4, 0,
421 { 0x131f, 0x2031, 0xffff, 0,
424 PUC_PORT_2S, 0x10, 4, 0,
427 { 0x131f, 0x2032, 0xffff, 0,
430 PUC_PORT_2S, 0x10, 4, 0,
433 { 0x131f, 0x2040, 0xffff, 0,
436 PUC_PORT_1S2P, 0x10, -1, 0,
440 { 0x131f, 0x2041, 0xffff, 0,
443 PUC_PORT_1S2P, 0x10, -1, 0,
447 { 0x131f, 0x2042, 0xffff, 0,
450 PUC_PORT_1S2P, 0x10, -1, 0,
454 { 0x131f, 0x2050, 0xffff, 0,
457 PUC_PORT_4S, 0x10, 4, 0,
460 { 0x131f, 0x2051, 0xffff, 0,
463 PUC_PORT_4S, 0x10, 4, 0,
466 { 0x131f, 0x2052, 0xffff, 0,
469 PUC_PORT_4S, 0x10, 4, 0,
472 { 0x131f, 0x2060, 0xffff, 0,
475 PUC_PORT_2S1P, 0x10, 4, 0,
478 { 0x131f, 0x2061, 0xffff, 0,
481 PUC_PORT_2S1P, 0x10, 4, 0,
484 { 0x131f, 0x2062, 0xffff, 0,
487 PUC_PORT_2S1P, 0x10, 4, 0,
490 { 0x131f, 0x2081, 0xffff, 0,
493 PUC_PORT_8S, 0x10, -1, -1,
497 { 0x135a, 0x0841, 0xffff, 0,
500 PUC_PORT_4S, 0x18, 0, 8,
503 { 0x135a, 0x0861, 0xffff, 0,
506 PUC_PORT_2S, 0x18, 0, 8,
509 { 0x135a, 0x0862, 0xffff, 0,
512 PUC_PORT_2S, 0x18, 0, 8,
515 { 0x135a, 0x0863, 0xffff, 0,
518 PUC_PORT_2S, 0x18, 0, 8,
521 { 0x135a, 0x0881, 0xffff, 0,
524 PUC_PORT_8S, 0x18, 0, 8,
527 { 0x135a, 0x08a1, 0xffff, 0,
530 PUC_PORT_2S, 0x18, 0, 8,
533 { 0x135a, 0x08a2, 0xffff, 0,
536 PUC_PORT_2S, 0x18, 0, 8,
539 { 0x135a, 0x08a3, 0xffff, 0,
542 PUC_PORT_2S, 0x18, 0, 8,
545 { 0x135a, 0x08c1, 0xffff, 0,
548 PUC_PORT_2S, 0x18, 0, 8,
551 { 0x135a, 0x08e1, 0xffff, 0,
554 PUC_PORT_2S, 0x18, 0, 8,
557 { 0x135a, 0x08e2, 0xffff, 0,
560 PUC_PORT_2S, 0x18, 0, 8,
563 { 0x135a, 0x08e3, 0xffff, 0,
566 PUC_PORT_2S, 0x18, 0, 8,
569 { 0x135a, 0x0901, 0xffff, 0,
572 PUC_PORT_3S, 0x18, 0, 8,
575 { 0x135a, 0x0921, 0xffff, 0,
578 PUC_PORT_4S, 0x18, 0, 8,
581 { 0x135a, 0x0981, 0xffff, 0,
584 PUC_PORT_2S, 0x18, 0, 8,
587 { 0x135a, 0x0982, 0xffff, 0,
590 PUC_PORT_2S, 0x18, 0, 8,
593 { 0x135a, 0x09a1, 0xffff, 0,
596 PUC_PORT_2S, 0x18, 0, 8,
599 { 0x135a, 0x09a2, 0xffff, 0,
602 PUC_PORT_2S, 0x18, 0, 8,
605 { 0x135a, 0x09a3, 0xffff, 0,
608 PUC_PORT_2S, 0x18, 0, 8,
611 { 0x135a, 0x0a81, 0xffff, 0,
614 PUC_PORT_2S, 0x18, 0, 8,
617 { 0x135a, 0x0a82, 0xffff, 0,
620 PUC_PORT_2S, 0x18, 0, 8,
623 { 0x135a, 0x0a83, 0xffff, 0,
626 PUC_PORT_2S, 0x18, 0, 8,
629 { 0x135a, 0x0ac1, 0xffff, 0,
632 PUC_PORT_2S, 0x18, 0, 8,
635 { 0x135a, 0x0ac2, 0xffff, 0,
638 PUC_PORT_2S, 0x18, 0, 8,
641 { 0x135a, 0x0ac3, 0xffff, 0,
644 PUC_PORT_2S, 0x18, 0, 8,
647 { 0x135a, 0x0b01, 0xffff, 0,
650 PUC_PORT_4S, 0x18, 0, 8,
653 { 0x135a, 0x0b02, 0xffff, 0,
656 PUC_PORT_4S, 0x18, 0, 8,
659 { 0x135a, 0x0b21, 0xffff, 0,
662 PUC_PORT_2S, 0x18, 0, 8,
665 { 0x135a, 0x0b22, 0xffff, 0,
668 PUC_PORT_2S, 0x18, 0, 8,
671 { 0x135a, 0x0b23, 0xffff, 0,
674 PUC_PORT_2S, 0x18, 0, 8,
677 { 0x135a, 0x0ba1, 0xffff, 0,
680 PUC_PORT_2S, 0x18, 0, 8,
683 { 0x135a, 0x0bc1, 0xffff, 0,
686 PUC_PORT_2S, 0x18, 0, 8,
689 { 0x135a, 0x0bc2, 0xffff, 0,
692 PUC_PORT_2S, 0x18, 0, 8,
695 { 0x135a, 0x0c01, 0xffff, 0,
698 PUC_PORT_2S, 0x18, 0, 8,
701 { 0x135a, 0x0c02, 0xffff, 0,
704 PUC_PORT_2S, 0x18, 0, 8,
707 { 0x135a, 0x0c03, 0xffff, 0,
710 PUC_PORT_2S, 0x18, 0, 8,
713 { 0x135a, 0x0c21, 0xffff, 0,
716 PUC_PORT_2S, 0x18, 0, 8,
719 { 0x135a, 0x0c22, 0xffff, 0,
722 PUC_PORT_2S, 0x18, 0, 8,
725 { 0x135a, 0x0c23, 0xffff, 0,
728 PUC_PORT_2S, 0x18, 0, 8,
731 { 0x135a, 0x0c41, 0xffff, 0,
734 PUC_PORT_4S, 0x18, 0, 8,
737 { 0x135a, 0x0ca1, 0xffff, 0,
740 PUC_PORT_2S, 0x18, 0, 8,
743 { 0x135a, 0x0d21, 0xffff, 0,
746 PUC_PORT_4S, 0x18, 0, 8,
749 { 0x135a, 0x0d41, 0xffff, 0,
752 PUC_PORT_4S, 0x18, 0, 8,
755 { 0x135a, 0x0d80, 0xffff, 0,
758 PUC_PORT_2S, 0x18, 0, 8,
761 { 0x135a, 0x0dc0, 0xffff, 0,
764 PUC_PORT_4S, 0x18, 0, 8,
767 { 0x135a, 0x0e41, 0xffff, 0,
770 PUC_PORT_8S, 0x18, 0, 8,
773 { 0x135a, 0x0e61, 0xffff, 0,
776 PUC_PORT_4S, 0x18, 0, 8,
779 { 0x135a, 0x400a, 0xffff, 0,
781 DEFAULT_RCLK * 0x22,
782 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
786 { 0x135a, 0x400b, 0xffff, 0,
788 DEFAULT_RCLK * 0x22,
789 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
793 { 0x135a, 0x400c, 0xffff, 0,
795 DEFAULT_RCLK * 0x22,
796 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
800 { 0x135a, 0x400e, 0xffff, 0,
802 DEFAULT_RCLK * 0x22,
803 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
807 { 0x135a, 0x400f, 0xffff, 0,
809 DEFAULT_RCLK * 0x22,
810 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
814 { 0x135a, 0x4010, 0xffff, 0,
816 DEFAULT_RCLK * 0x22,
817 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
821 { 0x135a, 0x4011, 0xffff, 0,
823 DEFAULT_RCLK * 0x22,
824 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
828 { 0x135a, 0x4012, 0xffff, 0,
830 DEFAULT_RCLK * 0x22,
831 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
835 { 0x135a, 0x4013, 0xffff, 0,
837 DEFAULT_RCLK * 0x22,
838 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
842 { 0x135a, 0x4014, 0xffff, 0,
844 DEFAULT_RCLK * 0x22,
845 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
849 { 0x135a, 0x4015, 0xffff, 0,
851 DEFAULT_RCLK * 0x22,
852 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
856 { 0x135a, 0x4016, 0xffff, 0,
858 DEFAULT_RCLK * 0x22,
859 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
863 { 0x135a, 0x4017, 0xffff, 0,
865 DEFAULT_RCLK * 0x22,
866 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
870 { 0x135a, 0x4018, 0xffff, 0,
872 DEFAULT_RCLK * 0x22,
873 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
877 { 0x135a, 0x4019, 0xffff, 0,
879 DEFAULT_RCLK * 0x22,
880 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
884 { 0x135a, 0x401d, 0xffff, 0,
886 DEFAULT_RCLK * 0x22,
887 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
891 { 0x135a, 0x401e, 0xffff, 0,
893 DEFAULT_RCLK * 0x22,
894 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
898 { 0x135a, 0x4027, 0xffff, 0,
900 DEFAULT_RCLK * 0x22,
901 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
905 { 0x135a, 0x4028, 0xffff, 0,
907 DEFAULT_RCLK * 0x22,
908 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
912 { 0x135a, 0x4029, 0xffff, 0,
914 DEFAULT_RCLK * 0x22,
915 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
919 { 0x135c, 0x0010, 0xffff, 0,
922 PUC_PORT_4S, 0x14, 0, 8,
926 { 0x135c, 0x0020, 0xffff, 0,
929 PUC_PORT_2S, 0x14, 0, 8,
933 { 0x135c, 0x0030, 0xffff, 0,
936 PUC_PORT_2S, 0x14, 0, 8,
940 { 0x135c, 0x0040, 0xffff, 0,
943 PUC_PORT_4S, 0x14, 0, 8,
947 { 0x135c, 0x0050, 0xffff, 0,
950 PUC_PORT_8S, 0x14, 0, 8,
954 { 0x135c, 0x0060, 0xffff, 0,
957 PUC_PORT_8S, 0x14, 0, 8,
961 { 0x135c, 0x0170, 0xffff, 0,
964 PUC_PORT_4S, 0x18, 0, 8,
968 { 0x135c, 0x0180, 0xffff, 0,
971 PUC_PORT_2S, 0x18, 0, 8,
975 { 0x135c, 0x01b0, 0xffff, 0,
978 PUC_PORT_2S, 0x18, 0, 8,
982 { 0x135c, 0x01e0, 0xffff, 0,
985 PUC_PORT_8S, 0x10, 0, 8,
989 { 0x1393, 0x1024, 0xffff, 0,
992 PUC_PORT_2S, 0x14, 0, -1,
996 { 0x1393, 0x1025, 0xffff, 0,
999 PUC_PORT_2S, 0x14, 0, -1,
1003 { 0x1393, 0x1040, 0xffff, 0,
1006 PUC_PORT_4S, 0x18, 0, 8,
1009 { 0x1393, 0x1041, 0xffff, 0,
1012 PUC_PORT_4S, 0x18, 0, 8,
1015 { 0x1393, 0x1042, 0xffff, 0,
1018 PUC_PORT_4S, 0x18, 0, 8,
1021 { 0x1393, 0x1043, 0xffff, 0,
1024 PUC_PORT_4S, 0x18, 0, 8,
1027 { 0x1393, 0x1045, 0xffff, 0,
1030 PUC_PORT_4S, 0x14, 0, -1,
1034 { 0x1393, 0x1120, 0xffff, 0,
1037 PUC_PORT_2S, 0x18, 0, 8,
1040 { 0x1393, 0x1141, 0xffff, 0,
1043 PUC_PORT_4S, 0x18, 0, 8,
1046 { 0x1393, 0x1144, 0xffff, 0,
1049 PUC_PORT_4S, 0x14, 0, -1,
1053 { 0x1393, 0x1182, 0xffff, 0,
1056 PUC_PORT_8S, 0x14, 0, -1,
1060 { 0x1393, 0x1680, 0xffff, 0,
1063 PUC_PORT_8S, 0x18, 0, 8,
1066 { 0x1393, 0x1681, 0xffff, 0,
1069 PUC_PORT_8S, 0x18, 0, 8,
1072 { 0x1393, 0x1682, 0xffff, 0,
1075 PUC_PORT_8S, 0x18, 0, 8,
1078 { 0x1393, 0x1683, 0xffff, 0,
1081 PUC_PORT_8S, 0x14, 0, -1,
1085 { 0x13a8, 0x0152, 0xffff, 0,
1088 PUC_PORT_2S, 0x10, 0, -1,
1092 { 0x13a8, 0x0154, 0xffff, 0,
1095 PUC_PORT_4S, 0x10, 0, -1,
1099 { 0x13a8, 0x0158, 0xffff, 0,
1102 PUC_PORT_8S, 0x10, 0, -1,
1106 { 0x13a8, 0x0258, 0xffff, 0,
1109 PUC_PORT_8S, 0x10, 0, -1,
1113 { 0x13a8, 0x0352, 0xffff, 0,
1116 PUC_PORT_2S, 0x10, 0, -1,
1120 { 0x13a8, 0x0354, 0xffff, 0,
1123 PUC_PORT_4S, 0x10, 0, -1,
1128 { 0x13a8, 0x0358, 0xffff, 0,
1131 PUC_PORT_8S, 0x10, 0, -1,
1141 { 0x13fe, 0x1600, 0x1602, 0x0002,
1144 PUC_PORT_2S, 0x10, 0, 8,
1149 { 0x13fe, 0xa102, 0x13fe, 0xa102,
1152 PUC_PORT_2S, 0x10, 4, 0,
1156 { 0x1407, 0x0100, 0xffff, 0,
1159 PUC_PORT_2S, 0x10, 4, 0,
1162 { 0x1407, 0x0101, 0xffff, 0,
1165 PUC_PORT_2S, 0x10, 4, 0,
1168 { 0x1407, 0x0102, 0xffff, 0,
1171 PUC_PORT_2S, 0x10, 4, 0,
1174 { 0x1407, 0x0120, 0xffff, 0,
1177 PUC_PORT_2S, 0x10, 4, 0,
1180 { 0x1407, 0x0121, 0xffff, 0,
1183 PUC_PORT_2S, 0x10, 4, 0,
1186 { 0x1407, 0x0180, 0xffff, 0,
1189 PUC_PORT_4S, 0x10, 4, 0,
1192 { 0x1407, 0x0181, 0xffff, 0,
1195 PUC_PORT_4S, 0x10, 4, 0,
1198 { 0x1409, 0x7268, 0xffff, 0,
1200 0,
1201 PUC_PORT_2P, 0x10, 0, 8,
1204 { 0x1409, 0x7168, 0xffff, 0,
1207 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
1221 0x1415, 0x9501, 0x10fc, 0xc070,
1224 PUC_PORT_2S, 0x10, 0, 8,
1227 { 0x1415, 0x9501, 0x131f, 0x2050,
1230 PUC_PORT_4S, 0x10, 0, 8,
1233 { 0x1415, 0x9501, 0x131f, 0x2051,
1236 PUC_PORT_4S, 0x10, 0, 8,
1239 { 0x1415, 0x9501, 0x131f, 0x2052,
1242 PUC_PORT_4S, 0x10, 0, 8,
1245 { 0x1415, 0x9501, 0x14db, 0x2150,
1248 PUC_PORT_4S, 0x10, 0, 8,
1251 { 0x1415, 0x9501, 0xffff, 0,
1253 0,
1254 PUC_PORT_4S, 0x10, 0, 8,
1258 { 0x1415, 0x950a, 0x131f, 0x2030,
1261 PUC_PORT_2S, 0x10, 0, 8,
1264 { 0x1415, 0x950a, 0x131f, 0x2032,
1267 PUC_PORT_4S, 0x10, 0, 8,
1270 { 0x1415, 0x950a, 0x131f, 0x2061,
1273 PUC_PORT_2S, 0x10, 0, 8,
1276 { 0x1415, 0x950a, 0xffff, 0,
1279 PUC_PORT_4S, 0x10, 0, 8,
1282 { 0x1415, 0x9511, 0xffff, 0,
1285 PUC_PORT_4S, 0x10, 0, 8,
1288 { 0x1415, 0x9521, 0xffff, 0,
1291 PUC_PORT_2S, 0x10, 4, 0,
1294 { 0x1415, 0x9538, 0xffff, 0,
1297 PUC_PORT_8S, 0x18, 0, 8,
1306 { 0x155f, 0x0331, 0xffff, 0,
1309 PUC_PORT_4S, 0x10, 0, 8,
1312 { 0x155f, 0xB012, 0xffff, 0,
1315 PUC_PORT_2S, 0x10, 0, 8,
1318 { 0x155f, 0xB022, 0xffff, 0,
1321 PUC_PORT_2S, 0x10, 0, 8,
1324 { 0x155f, 0xB004, 0xffff, 0,
1327 PUC_PORT_4S, 0x10, 0, 8,
1330 { 0x155f, 0xB008, 0xffff, 0,
1333 PUC_PORT_8S, 0x10, 0, 8,
1351 { 0x1415, 0xc11b, 0xffff, 0,
1353 DEFAULT_RCLK * 0x22,
1354 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1358 { 0x1415, 0xc138, 0xffff, 0,
1360 DEFAULT_RCLK * 0x22,
1361 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1365 { 0x1415, 0xc158, 0xffff, 0,
1367 DEFAULT_RCLK * 0x22,
1368 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1372 { 0x1415, 0xc15d, 0xffff, 0,
1374 DEFAULT_RCLK * 0x22,
1375 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1379 { 0x1415, 0xc208, 0xffff, 0,
1381 DEFAULT_RCLK * 0x22,
1382 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1386 { 0x1415, 0xc20d, 0xffff, 0,
1388 DEFAULT_RCLK * 0x22,
1389 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1393 { 0x1415, 0xc308, 0xffff, 0,
1395 DEFAULT_RCLK * 0x22,
1396 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1400 { 0x1415, 0xc30d, 0xffff, 0,
1402 DEFAULT_RCLK * 0x22,
1403 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1407 { 0x14d2, 0x8010, 0xffff, 0,
1410 PUC_PORT_1S, 0x14, 0, 0,
1413 { 0x14d2, 0x8020, 0xffff, 0,
1416 PUC_PORT_2S, 0x14, 4, 0,
1419 { 0x14d2, 0x8028, 0xffff, 0,
1422 PUC_PORT_2S, 0x20, 0, 8,
1434 { 0x14d2, 0x8080, 0xffff, 0,
1437 PUC_PORT_8S, 0x14, -1, -1,
1443 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
1446 { 0x14d2, 0xa003, 0xffff, 0,
1449 PUC_PORT_4S, 0x10, 0, 8,
1452 { 0x14d2, 0xa004, 0xffff, 0,
1455 PUC_PORT_4S, 0x10, 0, 8,
1458 { 0x14d2, 0xa005, 0xffff, 0,
1461 PUC_PORT_2S, 0x10, 0, 8,
1464 { 0x14d2, 0xe020, 0xffff, 0,
1467 PUC_PORT_2S, 0x10, 4, 0,
1470 { 0x14d2, 0xa007, 0xffff, 0,
1473 PUC_PORT_4S, 0x10, 0, 8,
1476 { 0x14d2, 0xa008, 0xffff, 0,
1479 PUC_PORT_4S, 0x10, 0, 8,
1482 { 0x14db, 0x2130, 0xffff, 0,
1485 PUC_PORT_2S, 0x10, 4, 0,
1488 { 0x14db, 0x2150, 0xffff, 0,
1491 PUC_PORT_4S, 0x10, 4, 0,
1494 { 0x14db, 0x2152, 0xffff, 0,
1497 PUC_PORT_4S, 0x10, 4, 0,
1500 { 0x1592, 0x0781, 0xffff, 0,
1503 PUC_PORT_4S1P, 0x10, 0, -1,
1507 { 0x1fd4, 0x1999, 0x1fd4, 0x0002,
1510 PUC_PORT_2S, 0x10, 0, 8,
1513 { 0x1fd4, 0x1999, 0x1fd4, 0x0004,
1516 PUC_PORT_4S, 0x10, 0, 8,
1519 { 0x1fd4, 0x1999, 0x1fd4, 0x0008,
1526 { 0x1fd4, 0x1999, 0x1fd4, 0x0101,
1533 { 0x1fd4, 0x1999, 0x1fd4, 0x0102,
1540 { 0x1fd4, 0x1999, 0x1fd4, 0x0104,
1547 { 0x5372, 0x6872, 0xffff, 0,
1550 PUC_PORT_2S1P, 0x10, 4, 0,
1553 { 0x5372, 0x6873, 0xffff, 0,
1556 PUC_PORT_4S, 0x10, 4, 0,
1559 { 0x6666, 0x0001, 0xffff, 0,
1562 PUC_PORT_4S, 0x1c, 0, 8,
1565 { 0x6666, 0x0002, 0xffff, 0,
1568 PUC_PORT_8S, 0x1c, 0, 8,
1571 { 0x6666, 0x0004, 0xffff, 0,
1574 PUC_PORT_2S, 0x1c, 0, 8,
1577 { 0x9710, 0x9815, 0xffff, 0,
1579 0,
1580 PUC_PORT_2P, 0x10, 8, 0,
1589 { 0x9710, 0x9835, 0x1000, 1,
1592 PUC_PORT_1S, 0x10, 4, 0,
1595 { 0x9710, 0x9835, 0x1000, 2,
1598 PUC_PORT_2S, 0x10, 4, 0,
1601 { 0x9710, 0x9835, 0xffff, 0,
1604 PUC_PORT_2S1P, 0x10, 4, 0,
1607 { 0x9710, 0x9845, 0x1000, 0x0006,
1610 PUC_PORT_6S, 0x10, 4, 0,
1613 { 0x9710, 0x9845, 0xffff, 0,
1616 PUC_PORT_4S1P, 0x10, 4, 0,
1619 { 0x9710, 0x9865, 0xa000, 0x3002,
1622 PUC_PORT_2S, 0x10, 4, 0,
1625 { 0x9710, 0x9865, 0xa000, 0x3003,
1628 PUC_PORT_3S, 0x10, 4, 0,
1631 { 0x9710, 0x9865, 0xa000, 0x3004,
1634 PUC_PORT_4S, 0x10, 4, 0,
1637 { 0x9710, 0x9865, 0xa000, 0x3011,
1640 PUC_PORT_1S1P, 0x10, 4, 0,
1643 { 0x9710, 0x9865, 0xa000, 0x3012,
1646 PUC_PORT_2S1P, 0x10, 4, 0,
1649 { 0x9710, 0x9865, 0xa000, 0x3020,
1652 PUC_PORT_2P, 0x10, 4, 0,
1655 { 0xb00c, 0x021c, 0xffff, 0,
1658 PUC_PORT_4S, 0x10, 0, 8,
1662 { 0xb00c, 0x031c, 0xffff, 0,
1665 PUC_PORT_4S, 0x10, 0, 8,
1669 { 0xb00c, 0x041c, 0xffff, 0,
1672 PUC_PORT_8S, 0x10, 0, 8,
1676 { 0xb00c, 0x051c, 0xffff, 0,
1679 PUC_PORT_8S, 0x10, 0, 8,
1683 { 0xb00c, 0x081c, 0xffff, 0,
1686 PUC_PORT_16S, 0x10, 0, 8,
1690 { 0xb00c, 0x091c, 0xffff, 0,
1693 PUC_PORT_16S, 0x10, 0, 8,
1697 { 0xb00c, 0x0a1c, 0xffff, 0,
1700 PUC_PORT_2S, 0x10, 0, 8,
1703 { 0xb00c, 0x0b1c, 0xffff, 0,
1706 PUC_PORT_4S, 0x10, 0, 8,
1713 { 0x14a1, 0x0008, 0x14a1, 0x0008,
1716 PUC_PORT_8S, 0x10, 0, 8,
1719 { 0x14a1, 0x0004, 0x14a1, 0x0004,
1722 PUC_PORT_4S, 0x10, 0, 8,
1726 { 0xffff, 0, 0xffff, 0, NULL, 0 }
1744 base = fixed = oxpcie = 0; in puc_config_advantech()
1746 acr = mask = 0x0; in puc_config_advantech()
1748 off = 0x60; in puc_config_advantech()
1752 case 0x13fe: in puc_config_advantech()
1754 case 0xa102: in puc_config_advantech()
1755 high = 0; in puc_config_advantech()
1774 i = PCIR_BAR(0); in puc_config_advantech()
1781 if (oxpcie == 0) { in puc_config_advantech()
1788 for (i = 0; i < sc->sc_nports; ++i) { in puc_config_advantech()
1796 if (fixed == 0) { in puc_config_advantech()
1797 if ((mask & (1 << (base + i))) == 0) { in puc_config_advantech()
1798 acr = 0; in puc_config_advantech()
1801 acr = (high == 1 ? 0x18 : 0x10); in puc_config_advantech()
1812 return (0); in puc_config_advantech()
1823 return (0); in puc_config_amc()
1825 *res = 0x14 + (port >> 1) * 4; in puc_config_amc()
1826 return (0); in puc_config_amc()
1840 if (cfg->subdevice == 0x1282) /* Everest SP */ in puc_config_diva()
1842 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ in puc_config_diva()
1844 *res = port * 8 + ((port > 2) ? 0x18 : 0); in puc_config_diva()
1845 return (0); in puc_config_diva()
1856 *res = port * 0x200; in puc_config_exar()
1857 return (0); in puc_config_exar()
1868 *res = port * 0x400; in puc_config_exar_pcie()
1869 return (0); in puc_config_exar_pcie()
1881 return (0); in puc_config_icbook()
1893 if (port == 3 && (cfg->device == 0x1045 || in puc_config_moxa()
1894 cfg->device == 0x1144)) in puc_config_moxa()
1896 *res = port * 0x200; in puc_config_moxa()
1898 return 0; in puc_config_moxa()
1921 bus_write_1(bar->b_res, REG_SPR, 0); in puc_config_quatech()
1923 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock); in puc_config_quatech()
1925 bus_write_1(bar->b_res, REG_LCR, 0); in puc_config_quatech()
1927 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { in puc_config_quatech()
1934 return (0); in puc_config_quatech()
1936 if (v0 != 0) { in puc_config_quatech()
1949 return (0); in puc_config_quatech()
1960 return (0); in puc_config_quatech()
1962 v0 = (sc->sc_cfg_data >> 8) & 0xff; in puc_config_quatech()
1963 v1 = sc->sc_cfg_data & 0xff; in puc_config_quatech()
1964 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { in puc_config_quatech()
1972 } else if (v0 == 0) { in puc_config_quatech()
1982 return (0); in puc_config_quatech()
1984 v0 = (sc->sc_cfg_data >> 8) & 0xff; in puc_config_quatech()
1985 v1 = sc->sc_cfg_data & 0xff; in puc_config_quatech()
1986 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ? in puc_config_quatech()
1988 return (0); in puc_config_quatech()
1999 static int base[] = { 0x251, 0x3f0, 0 }; in puc_config_syba()
2012 bus_write_1(bar->b_res, 0x250, 0x89); in puc_config_syba()
2013 bus_write_1(bar->b_res, 0x3f0, 0x87); in puc_config_syba()
2014 bus_write_1(bar->b_res, 0x3f0, 0x87); in puc_config_syba()
2015 idx = 0; in puc_config_syba()
2016 while (base[idx] != 0) { in puc_config_syba()
2018 bus_write_1(bar->b_res, efir, 0x09); in puc_config_syba()
2020 if ((v & 0x0f) != 0x0c) in puc_config_syba()
2022 bus_write_1(bar->b_res, efir, 0x16); in puc_config_syba()
2024 bus_write_1(bar->b_res, efir, 0x16); in puc_config_syba()
2025 bus_write_1(bar->b_res, efir + 1, v | 0x04); in puc_config_syba()
2026 bus_write_1(bar->b_res, efir, 0x16); in puc_config_syba()
2027 bus_write_1(bar->b_res, efir + 1, v & ~0x04); in puc_config_syba()
2028 ofs = base[idx] & 0x300; in puc_config_syba()
2029 bus_write_1(bar->b_res, efir, 0x23); in puc_config_syba()
2030 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); in puc_config_syba()
2031 bus_write_1(bar->b_res, efir, 0x24); in puc_config_syba()
2032 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); in puc_config_syba()
2033 bus_write_1(bar->b_res, efir, 0x25); in puc_config_syba()
2034 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); in puc_config_syba()
2035 bus_write_1(bar->b_res, efir, 0x17); in puc_config_syba()
2036 bus_write_1(bar->b_res, efir + 1, 0x03); in puc_config_syba()
2037 bus_write_1(bar->b_res, efir, 0x28); in puc_config_syba()
2038 bus_write_1(bar->b_res, efir + 1, 0x43); in puc_config_syba()
2041 bus_write_1(bar->b_res, 0x250, 0xaa); in puc_config_syba()
2042 bus_write_1(bar->b_res, 0x3f0, 0xaa); in puc_config_syba()
2043 return (0); in puc_config_syba()
2046 case 0: in puc_config_syba()
2047 *res = 0x2f8; in puc_config_syba()
2048 return (0); in puc_config_syba()
2050 *res = 0x2e8; in puc_config_syba()
2051 return (0); in puc_config_syba()
2053 *res = 0x3f8; in puc_config_syba()
2054 return (0); in puc_config_syba()
2056 *res = 0x3e8; in puc_config_syba()
2057 return (0); in puc_config_syba()
2059 *res = 0x278; in puc_config_syba()
2060 return (0); in puc_config_syba()
2078 *res = (port > 4) ? 8 * (port - 4) : 0; in puc_config_siig()
2079 return (0); in puc_config_siig()
2084 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); in puc_config_siig()
2085 return (0); in puc_config_siig()
2089 case 0: *res = 0x10; return (0); in puc_config_siig()
2090 case 1: *res = 0x14; return (0); in puc_config_siig()
2091 case 2: *res = 0x1c; return (0); in puc_config_siig()
2106 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, in puc_config_timedia()
2107 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, in puc_config_timedia()
2108 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, in puc_config_timedia()
2109 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, in puc_config_timedia()
2110 0xD079, 0 in puc_config_timedia()
2113 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, in puc_config_timedia()
2114 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, in puc_config_timedia()
2115 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, in puc_config_timedia()
2116 0xB157, 0 in puc_config_timedia()
2119 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, in puc_config_timedia()
2120 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 in puc_config_timedia()
2129 { 0, NULL } in puc_config_timedia()
2141 return (0); in puc_config_timedia()
2146 return (0); in puc_config_timedia()
2149 dev = 0; in puc_config_timedia()
2150 while (subdevs[dev].ports != 0) { in puc_config_timedia()
2151 id = 0; in puc_config_timedia()
2152 while (subdevs[dev].ids[id] != 0) { in puc_config_timedia()
2156 return (0); in puc_config_timedia()
2164 *res = (port == 1 || port == 3) ? 8 : 0; in puc_config_timedia()
2165 return (0); in puc_config_timedia()
2167 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; in puc_config_timedia()
2168 return (0); in puc_config_timedia()
2171 return (0); in puc_config_timedia()
2193 return (0); in puc_config_oxford_pci954()
2218 for (idx = 0; idx < sc->sc_nports; idx++) { in puc_config_oxford_pcie()
2219 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + in puc_config_oxford_pcie()
2220 0x92); in puc_config_oxford_pcie()
2221 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, in puc_config_oxford_pcie()
2222 value | 0x10); in puc_config_oxford_pcie()
2224 return (0); in puc_config_oxford_pcie()
2226 *res = 0x200; in puc_config_oxford_pcie()
2227 return (0); in puc_config_oxford_pcie()
2241 idx = 0; in puc_config_oxford_pcie()
2246 return (0); in puc_config_oxford_pcie()
2254 value = bus_read_1(bar->b_res, 0x04); in puc_config_oxford_pcie()
2255 if (value == 0) in puc_config_oxford_pcie()
2260 return (0); in puc_config_oxford_pcie()
2262 *res = 0x1000 + (port << 9); in puc_config_oxford_pcie()
2263 return (0); in puc_config_oxford_pcie()
2266 return (0); in puc_config_oxford_pcie()
2282 if (error != 0) in puc_config_sunix()
2284 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0; in puc_config_sunix()
2285 return (0); in puc_config_sunix()
2288 if (error != 0) in puc_config_sunix()
2290 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14; in puc_config_sunix()
2291 return (0); in puc_config_sunix()
2305 *res = (port < 3) ? 0 : (port - 2) << 3; in puc_config_titan()
2306 return (0); in puc_config_titan()
2308 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); in puc_config_titan()
2309 return (0); in puc_config_titan()
2324 bar = puc_get_bar(sc, 0x14); in puc_config_systembase()
2333 bus_write_1(bar->b_res, /* OPT_IMRREG0 */ 0xc, 0xff); in puc_config_systembase()
2334 return (0); in puc_config_systembase()