Lines Matching +full:0 +full:x18
71 { 0x0009, 0x7168, 0xffff, 0,
74 PUC_PORT_2S, 0x10, 0, 8,
77 { 0x103c, 0x1048, 0x103c, 0x1049,
80 PUC_PORT_3S, 0x10, 0, -1,
84 { 0x103c, 0x1048, 0x103c, 0x104a,
87 PUC_PORT_2S, 0x10, 0, -1,
91 { 0x103c, 0x1048, 0x103c, 0x104b,
94 PUC_PORT_4S, 0x10, 0, -1,
98 { 0x103c, 0x1048, 0x103c, 0x1223,
101 PUC_PORT_3S, 0x10, 0, -1,
105 { 0x103c, 0x1048, 0x103c, 0x1226,
108 PUC_PORT_3S, 0x10, 0, -1,
112 { 0x103c, 0x1048, 0x103c, 0x1282,
115 PUC_PORT_3S, 0x10, 0, -1,
119 { 0x10b5, 0x1076, 0x10b5, 0x1076,
122 PUC_PORT_8S, 0x18, 0, 8,
125 { 0x10b5, 0x1077, 0x10b5, 0x1077,
128 PUC_PORT_4S, 0x18, 0, 8,
131 { 0x10b5, 0x1103, 0x10b5, 0x1103,
134 PUC_PORT_2S, 0x18, 4, 0,
142 { 0x10b5, 0x9050, 0x12e0, 0x0021,
145 PUC_PORT_8S, 0x18, 0, 8,
148 { 0x10b5, 0x9050, 0x12e0, 0x0031,
151 PUC_PORT_4S, 0x18, 0, 8,
158 * network/misc (0x02/0x80) device.
160 { 0x10b5, 0x9050, 0xd84d, 0x6808,
163 PUC_PORT_2S, 0x18, 4, 0,
170 * network/misc (0x02/0x80) device.
172 { 0x10b5, 0x9050, 0xd84d, 0x6810,
174 0,
175 PUC_PORT_2P, 0x20, 4, 0,
178 { 0x10e8, 0x818e, 0xffff, 0,
181 PUC_PORT_8S, 0x14, -1, -1,
192 { 0x114f, 0x00b0, 0xffff, 0,
195 PUC_PORT_4S, 0x10, 0, -1,
199 { 0x114f, 0x00b1, 0xffff, 0,
202 PUC_PORT_8S, 0x10, 0, -1,
206 { 0x114f, 0x00f0, 0xffff, 0,
209 PUC_PORT_8S, 0x10, 0, -1,
213 { 0x114f, 0x00f1, 0xffff, 0,
216 PUC_PORT_4S, 0x10, 0, -1,
220 { 0x114f, 0x00f2, 0xffff, 0,
223 PUC_PORT_4S, 0x10, 0, -1,
227 { 0x114f, 0x00f3, 0xffff, 0,
230 PUC_PORT_8S, 0x10, 0, -1,
234 { 0x11fe, 0x8010, 0xffff, 0,
237 PUC_PORT_4S, 0x10, 0, 8,
240 { 0x11fe, 0x8011, 0xffff, 0,
243 PUC_PORT_4S, 0x10, 0, 8,
246 { 0x11fe, 0x8012, 0xffff, 0,
249 PUC_PORT_4S, 0x10, 0, 8,
252 { 0x11fe, 0x8013, 0xffff, 0,
255 PUC_PORT_4S, 0x10, 0, 8,
258 { 0x11fe, 0x8014, 0xffff, 0,
261 PUC_PORT_4S, 0x10, 0, 8,
264 { 0x11fe, 0x8015, 0xffff, 0,
267 PUC_PORT_4S, 0x10, 0, 8,
270 { 0x11fe, 0x8016, 0xffff, 0,
273 PUC_PORT_4S, 0x10, 0, 8,
276 { 0x11fe, 0x8017, 0xffff, 0,
279 PUC_PORT_12S, 0x10, 0, 8,
282 { 0x11fe, 0x8018, 0xffff, 0,
285 PUC_PORT_4S, 0x10, 0, 8,
288 { 0x11fe, 0x8019, 0xffff, 0,
291 PUC_PORT_4S, 0x10, 0, 8,
299 { 0x1014, 0x0297, 0xffff, 0,
302 PUC_PORT_4S, 0x10, 4, 0
312 { 0x131f, 0x1010, 0xffff, 0,
315 PUC_PORT_1S1P, 0x18, 4, 0,
318 { 0x131f, 0x1011, 0xffff, 0,
321 PUC_PORT_1S1P, 0x18, 4, 0,
324 { 0x131f, 0x1012, 0xffff, 0,
327 PUC_PORT_1S1P, 0x18, 4, 0,
330 { 0x131f, 0x1021, 0xffff, 0,
332 0,
333 PUC_PORT_2P, 0x18, 8, 0,
336 { 0x131f, 0x1030, 0xffff, 0,
339 PUC_PORT_2S, 0x18, 4, 0,
342 { 0x131f, 0x1031, 0xffff, 0,
345 PUC_PORT_2S, 0x18, 4, 0,
348 { 0x131f, 0x1032, 0xffff, 0,
351 PUC_PORT_2S, 0x18, 4, 0,
354 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
357 PUC_PORT_2S1P, 0x18, 4, 0,
360 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
363 PUC_PORT_2S1P, 0x18, 4, 0,
366 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
369 PUC_PORT_2S1P, 0x18, 4, 0,
372 { 0x131f, 0x1050, 0xffff, 0,
375 PUC_PORT_4S, 0x18, 4, 0,
378 { 0x131f, 0x1051, 0xffff, 0,
381 PUC_PORT_4S, 0x18, 4, 0,
384 { 0x131f, 0x1052, 0xffff, 0,
387 PUC_PORT_4S, 0x18, 4, 0,
390 { 0x131f, 0x2010, 0xffff, 0,
393 PUC_PORT_1S1P, 0x10, 4, 0,
396 { 0x131f, 0x2011, 0xffff, 0,
399 PUC_PORT_1S1P, 0x10, 4, 0,
402 { 0x131f, 0x2012, 0xffff, 0,
405 PUC_PORT_1S1P, 0x10, 4, 0,
408 { 0x131f, 0x2021, 0xffff, 0,
410 0,
411 PUC_PORT_2P, 0x10, 8, 0,
414 { 0x131f, 0x2030, 0xffff, 0,
417 PUC_PORT_2S, 0x10, 4, 0,
420 { 0x131f, 0x2031, 0xffff, 0,
423 PUC_PORT_2S, 0x10, 4, 0,
426 { 0x131f, 0x2032, 0xffff, 0,
429 PUC_PORT_2S, 0x10, 4, 0,
432 { 0x131f, 0x2040, 0xffff, 0,
435 PUC_PORT_1S2P, 0x10, -1, 0,
439 { 0x131f, 0x2041, 0xffff, 0,
442 PUC_PORT_1S2P, 0x10, -1, 0,
446 { 0x131f, 0x2042, 0xffff, 0,
449 PUC_PORT_1S2P, 0x10, -1, 0,
453 { 0x131f, 0x2050, 0xffff, 0,
456 PUC_PORT_4S, 0x10, 4, 0,
459 { 0x131f, 0x2051, 0xffff, 0,
462 PUC_PORT_4S, 0x10, 4, 0,
465 { 0x131f, 0x2052, 0xffff, 0,
468 PUC_PORT_4S, 0x10, 4, 0,
471 { 0x131f, 0x2060, 0xffff, 0,
474 PUC_PORT_2S1P, 0x10, 4, 0,
477 { 0x131f, 0x2061, 0xffff, 0,
480 PUC_PORT_2S1P, 0x10, 4, 0,
483 { 0x131f, 0x2062, 0xffff, 0,
486 PUC_PORT_2S1P, 0x10, 4, 0,
489 { 0x131f, 0x2081, 0xffff, 0,
492 PUC_PORT_8S, 0x10, -1, -1,
496 { 0x135a, 0x0841, 0xffff, 0,
499 PUC_PORT_4S, 0x18, 0, 8,
502 { 0x135a, 0x0861, 0xffff, 0,
505 PUC_PORT_2S, 0x18, 0, 8,
508 { 0x135a, 0x0862, 0xffff, 0,
511 PUC_PORT_2S, 0x18, 0, 8,
514 { 0x135a, 0x0863, 0xffff, 0,
517 PUC_PORT_2S, 0x18, 0, 8,
520 { 0x135a, 0x0881, 0xffff, 0,
523 PUC_PORT_8S, 0x18, 0, 8,
526 { 0x135a, 0x08a1, 0xffff, 0,
529 PUC_PORT_2S, 0x18, 0, 8,
532 { 0x135a, 0x08a2, 0xffff, 0,
535 PUC_PORT_2S, 0x18, 0, 8,
538 { 0x135a, 0x08a3, 0xffff, 0,
541 PUC_PORT_2S, 0x18, 0, 8,
544 { 0x135a, 0x08c1, 0xffff, 0,
547 PUC_PORT_2S, 0x18, 0, 8,
550 { 0x135a, 0x08e1, 0xffff, 0,
553 PUC_PORT_2S, 0x18, 0, 8,
556 { 0x135a, 0x08e2, 0xffff, 0,
559 PUC_PORT_2S, 0x18, 0, 8,
562 { 0x135a, 0x08e3, 0xffff, 0,
565 PUC_PORT_2S, 0x18, 0, 8,
568 { 0x135a, 0x0901, 0xffff, 0,
571 PUC_PORT_3S, 0x18, 0, 8,
574 { 0x135a, 0x0921, 0xffff, 0,
577 PUC_PORT_4S, 0x18, 0, 8,
580 { 0x135a, 0x0981, 0xffff, 0,
583 PUC_PORT_2S, 0x18, 0, 8,
586 { 0x135a, 0x0982, 0xffff, 0,
589 PUC_PORT_2S, 0x18, 0, 8,
592 { 0x135a, 0x09a1, 0xffff, 0,
595 PUC_PORT_2S, 0x18, 0, 8,
598 { 0x135a, 0x09a2, 0xffff, 0,
601 PUC_PORT_2S, 0x18, 0, 8,
604 { 0x135a, 0x09a3, 0xffff, 0,
607 PUC_PORT_2S, 0x18, 0, 8,
610 { 0x135a, 0x0a81, 0xffff, 0,
613 PUC_PORT_2S, 0x18, 0, 8,
616 { 0x135a, 0x0a82, 0xffff, 0,
619 PUC_PORT_2S, 0x18, 0, 8,
622 { 0x135a, 0x0a83, 0xffff, 0,
625 PUC_PORT_2S, 0x18, 0, 8,
628 { 0x135a, 0x0ac1, 0xffff, 0,
631 PUC_PORT_2S, 0x18, 0, 8,
634 { 0x135a, 0x0ac2, 0xffff, 0,
637 PUC_PORT_2S, 0x18, 0, 8,
640 { 0x135a, 0x0ac3, 0xffff, 0,
643 PUC_PORT_2S, 0x18, 0, 8,
646 { 0x135a, 0x0b01, 0xffff, 0,
649 PUC_PORT_4S, 0x18, 0, 8,
652 { 0x135a, 0x0b02, 0xffff, 0,
655 PUC_PORT_4S, 0x18, 0, 8,
658 { 0x135a, 0x0b21, 0xffff, 0,
661 PUC_PORT_2S, 0x18, 0, 8,
664 { 0x135a, 0x0b22, 0xffff, 0,
667 PUC_PORT_2S, 0x18, 0, 8,
670 { 0x135a, 0x0b23, 0xffff, 0,
673 PUC_PORT_2S, 0x18, 0, 8,
676 { 0x135a, 0x0ba1, 0xffff, 0,
679 PUC_PORT_2S, 0x18, 0, 8,
682 { 0x135a, 0x0bc1, 0xffff, 0,
685 PUC_PORT_2S, 0x18, 0, 8,
688 { 0x135a, 0x0bc2, 0xffff, 0,
691 PUC_PORT_2S, 0x18, 0, 8,
694 { 0x135a, 0x0c01, 0xffff, 0,
697 PUC_PORT_2S, 0x18, 0, 8,
700 { 0x135a, 0x0c02, 0xffff, 0,
703 PUC_PORT_2S, 0x18, 0, 8,
706 { 0x135a, 0x0c03, 0xffff, 0,
709 PUC_PORT_2S, 0x18, 0, 8,
712 { 0x135a, 0x0c21, 0xffff, 0,
715 PUC_PORT_2S, 0x18, 0, 8,
718 { 0x135a, 0x0c22, 0xffff, 0,
721 PUC_PORT_2S, 0x18, 0, 8,
724 { 0x135a, 0x0c23, 0xffff, 0,
727 PUC_PORT_2S, 0x18, 0, 8,
730 { 0x135a, 0x0c41, 0xffff, 0,
733 PUC_PORT_4S, 0x18, 0, 8,
736 { 0x135a, 0x0ca1, 0xffff, 0,
739 PUC_PORT_2S, 0x18, 0, 8,
742 { 0x135a, 0x0d21, 0xffff, 0,
745 PUC_PORT_4S, 0x18, 0, 8,
748 { 0x135a, 0x0d41, 0xffff, 0,
751 PUC_PORT_4S, 0x18, 0, 8,
754 { 0x135a, 0x0d80, 0xffff, 0,
757 PUC_PORT_2S, 0x18, 0, 8,
760 { 0x135a, 0x0dc0, 0xffff, 0,
763 PUC_PORT_4S, 0x18, 0, 8,
766 { 0x135a, 0x0e41, 0xffff, 0,
769 PUC_PORT_8S, 0x18, 0, 8,
772 { 0x135a, 0x0e61, 0xffff, 0,
775 PUC_PORT_4S, 0x18, 0, 8,
778 { 0x135a, 0x400a, 0xffff, 0,
780 DEFAULT_RCLK * 0x22,
781 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
785 { 0x135a, 0x400b, 0xffff, 0,
787 DEFAULT_RCLK * 0x22,
788 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
792 { 0x135a, 0x400c, 0xffff, 0,
794 DEFAULT_RCLK * 0x22,
795 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
799 { 0x135a, 0x400e, 0xffff, 0,
801 DEFAULT_RCLK * 0x22,
802 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
806 { 0x135a, 0x400f, 0xffff, 0,
808 DEFAULT_RCLK * 0x22,
809 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
813 { 0x135a, 0x4010, 0xffff, 0,
815 DEFAULT_RCLK * 0x22,
816 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
820 { 0x135a, 0x4011, 0xffff, 0,
822 DEFAULT_RCLK * 0x22,
823 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
827 { 0x135a, 0x4012, 0xffff, 0,
829 DEFAULT_RCLK * 0x22,
830 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
834 { 0x135a, 0x4013, 0xffff, 0,
836 DEFAULT_RCLK * 0x22,
837 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
841 { 0x135a, 0x4014, 0xffff, 0,
843 DEFAULT_RCLK * 0x22,
844 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
848 { 0x135a, 0x4015, 0xffff, 0,
850 DEFAULT_RCLK * 0x22,
851 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
855 { 0x135a, 0x4016, 0xffff, 0,
857 DEFAULT_RCLK * 0x22,
858 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
862 { 0x135a, 0x4017, 0xffff, 0,
864 DEFAULT_RCLK * 0x22,
865 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
869 { 0x135a, 0x4018, 0xffff, 0,
871 DEFAULT_RCLK * 0x22,
872 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
876 { 0x135a, 0x4019, 0xffff, 0,
878 DEFAULT_RCLK * 0x22,
879 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
883 { 0x135a, 0x401d, 0xffff, 0,
885 DEFAULT_RCLK * 0x22,
886 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
890 { 0x135a, 0x401e, 0xffff, 0,
892 DEFAULT_RCLK * 0x22,
893 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
897 { 0x135a, 0x4027, 0xffff, 0,
899 DEFAULT_RCLK * 0x22,
900 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
904 { 0x135a, 0x4028, 0xffff, 0,
906 DEFAULT_RCLK * 0x22,
907 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
911 { 0x135a, 0x4029, 0xffff, 0,
913 DEFAULT_RCLK * 0x22,
914 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
918 { 0x135c, 0x0010, 0xffff, 0,
921 PUC_PORT_4S, 0x14, 0, 8,
925 { 0x135c, 0x0020, 0xffff, 0,
928 PUC_PORT_2S, 0x14, 0, 8,
932 { 0x135c, 0x0030, 0xffff, 0,
935 PUC_PORT_2S, 0x14, 0, 8,
939 { 0x135c, 0x0040, 0xffff, 0,
942 PUC_PORT_4S, 0x14, 0, 8,
946 { 0x135c, 0x0050, 0xffff, 0,
949 PUC_PORT_8S, 0x14, 0, 8,
953 { 0x135c, 0x0060, 0xffff, 0,
956 PUC_PORT_8S, 0x14, 0, 8,
960 { 0x135c, 0x0170, 0xffff, 0,
963 PUC_PORT_4S, 0x18, 0, 8,
967 { 0x135c, 0x0180, 0xffff, 0,
970 PUC_PORT_2S, 0x18, 0, 8,
974 { 0x135c, 0x01b0, 0xffff, 0,
977 PUC_PORT_2S, 0x18, 0, 8,
981 { 0x135c, 0x01e0, 0xffff, 0,
984 PUC_PORT_8S, 0x10, 0, 8,
988 { 0x1393, 0x1024, 0xffff, 0,
991 PUC_PORT_2S, 0x14, 0, -1,
995 { 0x1393, 0x1025, 0xffff, 0,
998 PUC_PORT_2S, 0x14, 0, -1,
1002 { 0x1393, 0x1040, 0xffff, 0,
1005 PUC_PORT_4S, 0x18, 0, 8,
1008 { 0x1393, 0x1041, 0xffff, 0,
1011 PUC_PORT_4S, 0x18, 0, 8,
1014 { 0x1393, 0x1042, 0xffff, 0,
1017 PUC_PORT_4S, 0x18, 0, 8,
1020 { 0x1393, 0x1043, 0xffff, 0,
1023 PUC_PORT_4S, 0x18, 0, 8,
1026 { 0x1393, 0x1045, 0xffff, 0,
1029 PUC_PORT_4S, 0x14, 0, -1,
1033 { 0x1393, 0x1120, 0xffff, 0,
1036 PUC_PORT_2S, 0x18, 0, 8,
1039 { 0x1393, 0x1141, 0xffff, 0,
1042 PUC_PORT_4S, 0x18, 0, 8,
1045 { 0x1393, 0x1144, 0xffff, 0,
1048 PUC_PORT_4S, 0x14, 0, -1,
1052 { 0x1393, 0x1182, 0xffff, 0,
1055 PUC_PORT_8S, 0x14, 0, -1,
1059 { 0x1393, 0x1680, 0xffff, 0,
1062 PUC_PORT_8S, 0x18, 0, 8,
1065 { 0x1393, 0x1681, 0xffff, 0,
1068 PUC_PORT_8S, 0x18, 0, 8,
1071 { 0x1393, 0x1682, 0xffff, 0,
1074 PUC_PORT_8S, 0x18, 0, 8,
1077 { 0x1393, 0x1683, 0xffff, 0,
1080 PUC_PORT_8S, 0x14, 0, -1,
1084 { 0x13a8, 0x0152, 0xffff, 0,
1087 PUC_PORT_2S, 0x10, 0, -1,
1091 { 0x13a8, 0x0154, 0xffff, 0,
1094 PUC_PORT_4S, 0x10, 0, -1,
1098 { 0x13a8, 0x0158, 0xffff, 0,
1101 PUC_PORT_8S, 0x10, 0, -1,
1105 { 0x13a8, 0x0258, 0xffff, 0,
1108 PUC_PORT_8S, 0x10, 0, -1,
1112 { 0x13a8, 0x0352, 0xffff, 0,
1115 PUC_PORT_2S, 0x10, 0, -1,
1119 { 0x13a8, 0x0354, 0xffff, 0,
1122 PUC_PORT_4S, 0x10, 0, -1,
1127 { 0x13a8, 0x0358, 0xffff, 0,
1130 PUC_PORT_8S, 0x10, 0, -1,
1140 { 0x13fe, 0x1600, 0x1602, 0x0002,
1143 PUC_PORT_2S, 0x10, 0, 8,
1148 { 0x13fe, 0xa102, 0x13fe, 0xa102,
1151 PUC_PORT_2S, 0x10, 4, 0,
1155 { 0x1407, 0x0100, 0xffff, 0,
1158 PUC_PORT_2S, 0x10, 4, 0,
1161 { 0x1407, 0x0101, 0xffff, 0,
1164 PUC_PORT_2S, 0x10, 4, 0,
1167 { 0x1407, 0x0102, 0xffff, 0,
1170 PUC_PORT_2S, 0x10, 4, 0,
1173 { 0x1407, 0x0120, 0xffff, 0,
1176 PUC_PORT_2S, 0x10, 4, 0,
1179 { 0x1407, 0x0121, 0xffff, 0,
1182 PUC_PORT_2S, 0x10, 4, 0,
1185 { 0x1407, 0x0180, 0xffff, 0,
1188 PUC_PORT_4S, 0x10, 4, 0,
1191 { 0x1407, 0x0181, 0xffff, 0,
1194 PUC_PORT_4S, 0x10, 4, 0,
1197 { 0x1409, 0x7268, 0xffff, 0,
1199 0,
1200 PUC_PORT_2P, 0x10, 0, 8,
1203 { 0x1409, 0x7168, 0xffff, 0,
1206 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
1220 0x1415, 0x9501, 0x10fc, 0xc070,
1223 PUC_PORT_2S, 0x10, 0, 8,
1226 { 0x1415, 0x9501, 0x131f, 0x2050,
1229 PUC_PORT_4S, 0x10, 0, 8,
1232 { 0x1415, 0x9501, 0x131f, 0x2051,
1235 PUC_PORT_4S, 0x10, 0, 8,
1238 { 0x1415, 0x9501, 0x131f, 0x2052,
1241 PUC_PORT_4S, 0x10, 0, 8,
1244 { 0x1415, 0x9501, 0x14db, 0x2150,
1247 PUC_PORT_4S, 0x10, 0, 8,
1250 { 0x1415, 0x9501, 0xffff, 0,
1252 0,
1253 PUC_PORT_4S, 0x10, 0, 8,
1257 { 0x1415, 0x950a, 0x131f, 0x2030,
1260 PUC_PORT_2S, 0x10, 0, 8,
1263 { 0x1415, 0x950a, 0x131f, 0x2032,
1266 PUC_PORT_4S, 0x10, 0, 8,
1269 { 0x1415, 0x950a, 0x131f, 0x2061,
1272 PUC_PORT_2S, 0x10, 0, 8,
1275 { 0x1415, 0x950a, 0xffff, 0,
1278 PUC_PORT_4S, 0x10, 0, 8,
1281 { 0x1415, 0x9511, 0xffff, 0,
1284 PUC_PORT_4S, 0x10, 0, 8,
1287 { 0x1415, 0x9521, 0xffff, 0,
1290 PUC_PORT_2S, 0x10, 4, 0,
1293 { 0x1415, 0x9538, 0xffff, 0,
1296 PUC_PORT_8S, 0x18, 0, 8,
1305 { 0x155f, 0x0331, 0xffff, 0,
1308 PUC_PORT_4S, 0x10, 0, 8,
1311 { 0x155f, 0xB012, 0xffff, 0,
1314 PUC_PORT_2S, 0x10, 0, 8,
1317 { 0x155f, 0xB022, 0xffff, 0,
1320 PUC_PORT_2S, 0x10, 0, 8,
1323 { 0x155f, 0xB004, 0xffff, 0,
1326 PUC_PORT_4S, 0x10, 0, 8,
1329 { 0x155f, 0xB008, 0xffff, 0,
1332 PUC_PORT_8S, 0x10, 0, 8,
1350 { 0x1415, 0xc11b, 0xffff, 0,
1352 DEFAULT_RCLK * 0x22,
1353 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1357 { 0x1415, 0xc138, 0xffff, 0,
1359 DEFAULT_RCLK * 0x22,
1360 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1364 { 0x1415, 0xc158, 0xffff, 0,
1366 DEFAULT_RCLK * 0x22,
1367 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1371 { 0x1415, 0xc15d, 0xffff, 0,
1373 DEFAULT_RCLK * 0x22,
1374 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1378 { 0x1415, 0xc208, 0xffff, 0,
1380 DEFAULT_RCLK * 0x22,
1381 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1385 { 0x1415, 0xc20d, 0xffff, 0,
1387 DEFAULT_RCLK * 0x22,
1388 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1392 { 0x1415, 0xc308, 0xffff, 0,
1394 DEFAULT_RCLK * 0x22,
1395 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1399 { 0x1415, 0xc30d, 0xffff, 0,
1401 DEFAULT_RCLK * 0x22,
1402 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1406 { 0x14d2, 0x8010, 0xffff, 0,
1409 PUC_PORT_1S, 0x14, 0, 0,
1412 { 0x14d2, 0x8020, 0xffff, 0,
1415 PUC_PORT_2S, 0x14, 4, 0,
1418 { 0x14d2, 0x8028, 0xffff, 0,
1421 PUC_PORT_2S, 0x20, 0, 8,
1433 { 0x14d2, 0x8080, 0xffff, 0,
1436 PUC_PORT_8S, 0x14, -1, -1,
1442 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
1445 { 0x14d2, 0xa003, 0xffff, 0,
1448 PUC_PORT_4S, 0x10, 0, 8,
1451 { 0x14d2, 0xa004, 0xffff, 0,
1454 PUC_PORT_4S, 0x10, 0, 8,
1457 { 0x14d2, 0xa005, 0xffff, 0,
1460 PUC_PORT_2S, 0x10, 0, 8,
1463 { 0x14d2, 0xe020, 0xffff, 0,
1466 PUC_PORT_2S, 0x10, 4, 0,
1469 { 0x14d2, 0xa007, 0xffff, 0,
1472 PUC_PORT_4S, 0x10, 0, 8,
1475 { 0x14d2, 0xa008, 0xffff, 0,
1478 PUC_PORT_4S, 0x10, 0, 8,
1481 { 0x14db, 0x2130, 0xffff, 0,
1484 PUC_PORT_2S, 0x10, 4, 0,
1487 { 0x14db, 0x2150, 0xffff, 0,
1490 PUC_PORT_4S, 0x10, 4, 0,
1493 { 0x14db, 0x2152, 0xffff, 0,
1496 PUC_PORT_4S, 0x10, 4, 0,
1499 { 0x1592, 0x0781, 0xffff, 0,
1502 PUC_PORT_4S1P, 0x10, 0, -1,
1506 { 0x1fd4, 0x1999, 0x1fd4, 0x0002,
1509 PUC_PORT_2S, 0x10, 0, 8,
1512 { 0x1fd4, 0x1999, 0x1fd4, 0x0004,
1515 PUC_PORT_4S, 0x10, 0, 8,
1518 { 0x1fd4, 0x1999, 0x1fd4, 0x0008,
1525 { 0x1fd4, 0x1999, 0x1fd4, 0x0101,
1532 { 0x1fd4, 0x1999, 0x1fd4, 0x0102,
1539 { 0x1fd4, 0x1999, 0x1fd4, 0x0104,
1546 { 0x5372, 0x6872, 0xffff, 0,
1549 PUC_PORT_2S1P, 0x10, 4, 0,
1552 { 0x5372, 0x6873, 0xffff, 0,
1555 PUC_PORT_4S, 0x10, 4, 0,
1558 { 0x6666, 0x0001, 0xffff, 0,
1561 PUC_PORT_4S, 0x1c, 0, 8,
1564 { 0x6666, 0x0002, 0xffff, 0,
1567 PUC_PORT_8S, 0x1c, 0, 8,
1570 { 0x6666, 0x0004, 0xffff, 0,
1573 PUC_PORT_2S, 0x1c, 0, 8,
1576 { 0x9710, 0x9815, 0xffff, 0,
1578 0,
1579 PUC_PORT_2P, 0x10, 8, 0,
1588 { 0x9710, 0x9835, 0x1000, 1,
1591 PUC_PORT_1S, 0x10, 4, 0,
1594 { 0x9710, 0x9835, 0x1000, 2,
1597 PUC_PORT_2S, 0x10, 4, 0,
1600 { 0x9710, 0x9835, 0xffff, 0,
1603 PUC_PORT_2S1P, 0x10, 4, 0,
1606 { 0x9710, 0x9845, 0x1000, 0x0006,
1609 PUC_PORT_6S, 0x10, 4, 0,
1612 { 0x9710, 0x9845, 0xffff, 0,
1615 PUC_PORT_4S1P, 0x10, 4, 0,
1618 { 0x9710, 0x9865, 0xa000, 0x3002,
1621 PUC_PORT_2S, 0x10, 4, 0,
1624 { 0x9710, 0x9865, 0xa000, 0x3003,
1627 PUC_PORT_3S, 0x10, 4, 0,
1630 { 0x9710, 0x9865, 0xa000, 0x3004,
1633 PUC_PORT_4S, 0x10, 4, 0,
1636 { 0x9710, 0x9865, 0xa000, 0x3011,
1639 PUC_PORT_1S1P, 0x10, 4, 0,
1642 { 0x9710, 0x9865, 0xa000, 0x3012,
1645 PUC_PORT_2S1P, 0x10, 4, 0,
1648 { 0x9710, 0x9865, 0xa000, 0x3020,
1651 PUC_PORT_2P, 0x10, 4, 0,
1654 { 0xb00c, 0x021c, 0xffff, 0,
1657 PUC_PORT_4S, 0x10, 0, 8,
1661 { 0xb00c, 0x031c, 0xffff, 0,
1664 PUC_PORT_4S, 0x10, 0, 8,
1668 { 0xb00c, 0x041c, 0xffff, 0,
1671 PUC_PORT_8S, 0x10, 0, 8,
1675 { 0xb00c, 0x051c, 0xffff, 0,
1678 PUC_PORT_8S, 0x10, 0, 8,
1682 { 0xb00c, 0x081c, 0xffff, 0,
1685 PUC_PORT_16S, 0x10, 0, 8,
1689 { 0xb00c, 0x091c, 0xffff, 0,
1692 PUC_PORT_16S, 0x10, 0, 8,
1696 { 0xb00c, 0x0a1c, 0xffff, 0,
1699 PUC_PORT_2S, 0x10, 0, 8,
1702 { 0xb00c, 0x0b1c, 0xffff, 0,
1705 PUC_PORT_4S, 0x10, 0, 8,
1708 { 0xffff, 0, 0xffff, 0, NULL, 0 }
1726 base = fixed = oxpcie = 0; in puc_config_advantech()
1728 acr = mask = 0x0; in puc_config_advantech()
1730 off = 0x60; in puc_config_advantech()
1734 case 0x13fe: in puc_config_advantech()
1736 case 0xa102: in puc_config_advantech()
1737 high = 0; in puc_config_advantech()
1756 i = PCIR_BAR(0); in puc_config_advantech()
1763 if (oxpcie == 0) { in puc_config_advantech()
1770 for (i = 0; i < sc->sc_nports; ++i) { in puc_config_advantech()
1778 if (fixed == 0) { in puc_config_advantech()
1779 if ((mask & (1 << (base + i))) == 0) { in puc_config_advantech()
1780 acr = 0; in puc_config_advantech()
1783 acr = (high == 1 ? 0x18 : 0x10); in puc_config_advantech()
1794 return (0); in puc_config_advantech()
1805 return (0); in puc_config_amc()
1807 *res = 0x14 + (port >> 1) * 4; in puc_config_amc()
1808 return (0); in puc_config_amc()
1822 if (cfg->subdevice == 0x1282) /* Everest SP */ in puc_config_diva()
1824 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ in puc_config_diva()
1826 *res = port * 8 + ((port > 2) ? 0x18 : 0); in puc_config_diva()
1827 return (0); in puc_config_diva()
1838 *res = port * 0x200; in puc_config_exar()
1839 return (0); in puc_config_exar()
1850 *res = port * 0x400; in puc_config_exar_pcie()
1851 return (0); in puc_config_exar_pcie()
1863 return (0); in puc_config_icbook()
1875 if (port == 3 && (cfg->device == 0x1045 || in puc_config_moxa()
1876 cfg->device == 0x1144)) in puc_config_moxa()
1878 *res = port * 0x200; in puc_config_moxa()
1880 return 0; in puc_config_moxa()
1903 bus_write_1(bar->b_res, REG_SPR, 0); in puc_config_quatech()
1905 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock); in puc_config_quatech()
1907 bus_write_1(bar->b_res, REG_LCR, 0); in puc_config_quatech()
1909 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { in puc_config_quatech()
1916 return (0); in puc_config_quatech()
1918 if (v0 != 0) { in puc_config_quatech()
1931 return (0); in puc_config_quatech()
1942 return (0); in puc_config_quatech()
1944 v0 = (sc->sc_cfg_data >> 8) & 0xff; in puc_config_quatech()
1945 v1 = sc->sc_cfg_data & 0xff; in puc_config_quatech()
1946 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { in puc_config_quatech()
1954 } else if (v0 == 0) { in puc_config_quatech()
1964 return (0); in puc_config_quatech()
1966 v0 = (sc->sc_cfg_data >> 8) & 0xff; in puc_config_quatech()
1967 v1 = sc->sc_cfg_data & 0xff; in puc_config_quatech()
1968 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ? in puc_config_quatech()
1970 return (0); in puc_config_quatech()
1981 static int base[] = { 0x251, 0x3f0, 0 }; in puc_config_syba()
1994 bus_write_1(bar->b_res, 0x250, 0x89); in puc_config_syba()
1995 bus_write_1(bar->b_res, 0x3f0, 0x87); in puc_config_syba()
1996 bus_write_1(bar->b_res, 0x3f0, 0x87); in puc_config_syba()
1997 idx = 0; in puc_config_syba()
1998 while (base[idx] != 0) { in puc_config_syba()
2000 bus_write_1(bar->b_res, efir, 0x09); in puc_config_syba()
2002 if ((v & 0x0f) != 0x0c) in puc_config_syba()
2004 bus_write_1(bar->b_res, efir, 0x16); in puc_config_syba()
2006 bus_write_1(bar->b_res, efir, 0x16); in puc_config_syba()
2007 bus_write_1(bar->b_res, efir + 1, v | 0x04); in puc_config_syba()
2008 bus_write_1(bar->b_res, efir, 0x16); in puc_config_syba()
2009 bus_write_1(bar->b_res, efir + 1, v & ~0x04); in puc_config_syba()
2010 ofs = base[idx] & 0x300; in puc_config_syba()
2011 bus_write_1(bar->b_res, efir, 0x23); in puc_config_syba()
2012 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); in puc_config_syba()
2013 bus_write_1(bar->b_res, efir, 0x24); in puc_config_syba()
2014 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); in puc_config_syba()
2015 bus_write_1(bar->b_res, efir, 0x25); in puc_config_syba()
2016 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); in puc_config_syba()
2017 bus_write_1(bar->b_res, efir, 0x17); in puc_config_syba()
2018 bus_write_1(bar->b_res, efir + 1, 0x03); in puc_config_syba()
2019 bus_write_1(bar->b_res, efir, 0x28); in puc_config_syba()
2020 bus_write_1(bar->b_res, efir + 1, 0x43); in puc_config_syba()
2023 bus_write_1(bar->b_res, 0x250, 0xaa); in puc_config_syba()
2024 bus_write_1(bar->b_res, 0x3f0, 0xaa); in puc_config_syba()
2025 return (0); in puc_config_syba()
2028 case 0: in puc_config_syba()
2029 *res = 0x2f8; in puc_config_syba()
2030 return (0); in puc_config_syba()
2032 *res = 0x2e8; in puc_config_syba()
2033 return (0); in puc_config_syba()
2035 *res = 0x3f8; in puc_config_syba()
2036 return (0); in puc_config_syba()
2038 *res = 0x3e8; in puc_config_syba()
2039 return (0); in puc_config_syba()
2041 *res = 0x278; in puc_config_syba()
2042 return (0); in puc_config_syba()
2060 *res = (port > 4) ? 8 * (port - 4) : 0; in puc_config_siig()
2061 return (0); in puc_config_siig()
2066 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); in puc_config_siig()
2067 return (0); in puc_config_siig()
2071 case 0: *res = 0x10; return (0); in puc_config_siig()
2072 case 1: *res = 0x14; return (0); in puc_config_siig()
2073 case 2: *res = 0x1c; return (0); in puc_config_siig()
2088 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, in puc_config_timedia()
2089 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, in puc_config_timedia()
2090 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, in puc_config_timedia()
2091 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, in puc_config_timedia()
2092 0xD079, 0 in puc_config_timedia()
2095 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, in puc_config_timedia()
2096 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, in puc_config_timedia()
2097 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, in puc_config_timedia()
2098 0xB157, 0 in puc_config_timedia()
2101 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, in puc_config_timedia()
2102 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 in puc_config_timedia()
2111 { 0, NULL } in puc_config_timedia()
2123 return (0); in puc_config_timedia()
2128 return (0); in puc_config_timedia()
2131 dev = 0; in puc_config_timedia()
2132 while (subdevs[dev].ports != 0) { in puc_config_timedia()
2133 id = 0; in puc_config_timedia()
2134 while (subdevs[dev].ids[id] != 0) { in puc_config_timedia()
2138 return (0); in puc_config_timedia()
2146 *res = (port == 1 || port == 3) ? 8 : 0; in puc_config_timedia()
2147 return (0); in puc_config_timedia()
2149 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; in puc_config_timedia()
2150 return (0); in puc_config_timedia()
2153 return (0); in puc_config_timedia()
2175 return (0); in puc_config_oxford_pci954()
2200 for (idx = 0; idx < sc->sc_nports; idx++) { in puc_config_oxford_pcie()
2201 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + in puc_config_oxford_pcie()
2202 0x92); in puc_config_oxford_pcie()
2203 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, in puc_config_oxford_pcie()
2204 value | 0x10); in puc_config_oxford_pcie()
2206 return (0); in puc_config_oxford_pcie()
2208 *res = 0x200; in puc_config_oxford_pcie()
2209 return (0); in puc_config_oxford_pcie()
2223 idx = 0; in puc_config_oxford_pcie()
2228 return (0); in puc_config_oxford_pcie()
2236 value = bus_read_1(bar->b_res, 0x04); in puc_config_oxford_pcie()
2237 if (value == 0) in puc_config_oxford_pcie()
2242 return (0); in puc_config_oxford_pcie()
2244 *res = 0x1000 + (port << 9); in puc_config_oxford_pcie()
2245 return (0); in puc_config_oxford_pcie()
2248 return (0); in puc_config_oxford_pcie()
2264 if (error != 0) in puc_config_sunix()
2266 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0; in puc_config_sunix()
2267 return (0); in puc_config_sunix()
2270 if (error != 0) in puc_config_sunix()
2272 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14; in puc_config_sunix()
2273 return (0); in puc_config_sunix()
2287 *res = (port < 3) ? 0 : (port - 2) << 3; in puc_config_titan()
2288 return (0); in puc_config_titan()
2290 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); in puc_config_titan()
2291 return (0); in puc_config_titan()