Lines Matching +full:0 +full:x402
38 #define SMC_LIKE 0
55 #define PPC_TYPE_SMCLIKE 0
70 #define PPC_IRQ_NONE 0x0
71 #define PPC_IRQ_nACK 0x1
72 #define PPC_IRQ_DMA 0x2
73 #define PPC_IRQ_FIFO 0x4
74 #define PPC_IRQ_nFAULT 0x8
77 #define PPC_DMA_INIT 0x01
78 #define PPC_DMA_STARTED 0x02
79 #define PPC_DMA_COMPLETE 0x03
80 #define PPC_DMA_INTERRUPTED 0x04
81 #define PPC_DMA_ERROR 0x05
89 #define PPC_PWORD_MASK 0x30
90 #define PPC_PWORD_16 0x00
91 #define PPC_PWORD_8 0x10
92 #define PPC_PWORD_32 0x20
127 #define PPC_SPP_DTR 0 /* SPP data register */
128 #define PPC_ECP_A_FIFO 0 /* ECP Address fifo register */
133 #define PPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */
134 #define PPC_ECP_CNFGA 0x400 /* Configuration register A */
135 #define PPC_ECP_CNFGB 0x401 /* Configuration register B */
136 #define PPC_ECP_ECR 0x402 /* ECP extended control register */
138 #define PPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */
139 #define PPC_FIFO_FULL 0x2 /* ecr register - bit 1 */
140 #define PPC_SERVICE_INTR 0x4 /* ecr register - bit 2 */
141 #define PPC_ENABLE_DMA 0x8 /* ecr register - bit 3 */
142 #define PPC_nFAULT_INTR 0x10 /* ecr register - bit 4 */
143 #define PPC_ECR_STD 0x0
144 #define PPC_ECR_PS2 0x20
145 #define PPC_ECR_FIFO 0x40
146 #define PPC_ECR_ECP 0x60
147 #define PPC_ECR_EPP 0x80
176 #define PC873_FER 0x00
177 #define PC873_PPENABLE (1<<0)
178 #define PC873_FAR 0x01
179 #define PC873_PTR 0x02
184 #define PC873_FCR 0x03
187 #define PC873_PCR 0x04
188 #define PC873_EPPEN (1<<0)
192 #define PC873_PMC 0x06
193 #define PC873_TUP 0x07
194 #define PC873_SID 0x08
195 #define PC873_PNP0 0x1b
196 #define PC873_PNP1 0x1c
197 #define PC873_LPTBA 0x19
204 #define SMC665_iCODE 0x55
205 #define SMC666_iCODE 0x44
208 #define SMC66x_CSR 0x3F0
209 #define SMC666_CSR 0x370 /* hard-configured value for 666 */
212 #define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */
214 #define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */
218 #define SMC_SPP 0x0 /* SPP */
219 #define SMC_EPPSPP 0x1 /* EPP and SPP */
220 #define SMC_ECP 0x2 /* ECP */
221 #define SMC_ECPEPP 0x3 /* ECP and EPP */
228 #define SMC935_CFG 0x370
229 #define SMC935_IND 0x370
230 #define SMC935_DAT 0x371
233 #define SMC935_LOGDEV 0x7
234 #define SMC935_ID 0x20
235 #define SMC935_PORTHI 0x60
236 #define SMC935_PORTLO 0x61
237 #define SMC935_PPMODE 0xf0
240 #define SMC935_SPP 0x38 + 0
241 #define SMC935_EPP19SPP 0x38 + 1
242 #define SMC935_ECP 0x38 + 2
243 #define SMC935_ECPEPP19 0x38 + 3
244 #define SMC935_CENT 0x38 + 4
245 #define SMC935_EPP17SPP 0x38 + 5
246 #define SMC935_UNUSED 0x38 + 6
247 #define SMC935_ECPEPP17 0x38 + 7
253 #define WINB_W83877F_ID 0xa
254 #define WINB_W83877AF_ID 0xb
258 #define WINB_HEFRAS (1<<0) /* CR16 bit 0 */
261 #define WINB_CHIPID 0xf /* CR9 bits 0-3 */
268 #define WINB_W83757 0x0
269 #define WINB_EXTFDC 0x4
270 #define WINB_EXTADP 0x8
271 #define WINB_EXT2FDD 0xc
272 #define WINB_JOYSTICK 0x80
274 #define WINB_PARALLEL 0x80
275 #define WINB_EPP_SPP 0x4
276 #define WINB_ECP 0x8
277 #define WINB_ECP_EPP 0xc