Lines Matching +full:mode +full:- +full:xxx
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 1997-2000 Nicolas Souchu
5 * Copyright (c) 2001 Alcove - Nicolas Souchu
82 * config mode, but since we only do that to detect the type at startup the
92 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
99 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
100 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
119 * BIOS printer list - used by BIOS probe.
127 * ppc_ecp_sync() XXX
136 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
171 /* enter ECP configuration mode, no interrupt, no DMA */
174 /* read PWord size - transfers in FIFO mode must be PWord aligned */
175 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
177 /* XXX 16 and 32 bits implementations not supported */
178 if (ppc->ppc_pword != PPC_PWORD_8) {
183 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
187 /* enter ECP test mode, no interrupt, no DMA */
210 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
212 ppc->ppc_rthr = i+1;
215 ppc->ppc_fifo = i+1;
225 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
232 for (i=ppc->ppc_fifo; i>0; i--) {
233 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
239 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
281 * PC87332 - reading SPP_STR does it...
282 * SMC - write 1 to EPP timeout bit XXX
283 * Others - (?) write 0 to EPP timeout bit
306 * Configure current operating mode
309 ppc_generic_setmode(struct ppc_data *ppc, int mode)
313 /* check if mode is available */
314 if (mode && !(ppc->ppc_avm & mode))
317 /* if ECP mode, configure ecr register */
318 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
319 /* return to byte mode (keeping direction bit),
326 if (mode & PPB_EPP)
328 else if (mode & PPB_ECP)
329 /* select ECP mode */
331 else if (mode & PPB_PS2)
332 /* select PS2 mode with ECP */
335 /* select COMPATIBLE/NIBBLE mode */
341 ppc->ppc_mode = mode;
348 * if ECP mode is available.
350 * The 'RAW' option allows the upper drivers to force the ppc mode
354 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
358 /* check if mode is available */
359 if (mode && !(ppc->ppc_avm & mode))
362 /* if ECP mode, configure ecr register */
363 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
364 /* return to byte mode (keeping direction bit),
366 * ECP or EPP mode
371 if (mode & PPB_EPP)
372 /* select EPP mode */
374 else if (mode & PPB_ECP)
375 /* select ECP mode */
377 else if (mode & PPB_PS2)
378 /* select PS2 mode with ECP */
381 /* select COMPATIBLE/NIBBLE mode */
387 ppc->ppc_mode = mode;
396 * Probe for a Natsemi PC873xx-family part.
409 PC873_PNP1, PC873_LPTBA, -1
419 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
426 /* XXX should check first to see if this location is already claimed */
429 * Pull the 873xx through the power-on ID cycle (2.2,1.).
439 * 01010xxx PC87334
441 * 01110xxx PC87306
442 * 00110xxx PC87303
447 ppc->ppc_model = NS_PC87332;
449 ppc->ppc_model = NS_PC87306;
451 ppc->ppc_model = NS_PC87334;
455 ppc->ppc_model = NS_PC87303;
465 for (i=0; pc873xx_regstab[i] != -1; i++) {
485 /* XXX we should create a driver instance for every port found */
486 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
489 switch (ppc->ppc_base) {
519 if (pc873xx_porttab[val] != ppc->ppc_base) {
522 pc873xx_porttab[val], ppc->ppc_base);
531 if (ppc->ppc_base == 0x378)
537 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
542 if (irq != ppc->ppc_irq) {
547 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
548 if (ppc->ppc_irq == 7) {
556 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
573 ppc->ppc_avm |= PPB_NIBBLE;
578 ppc->ppc_avm |= PPB_EPP;
584 ppc->ppc_epp = EPP_1_9;
586 ppc->ppc_epp = EPP_1_7;
588 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
592 printf(", Regular mode");
594 printf(", Automatic mode");
597 ppc->ppc_avm |= PPB_ECP;
601 if (pcr & PC873_ECPCLK) { /* XXX */
602 ppc->ppc_avm |= PPB_PS2;
610 ppc->ppc_avm |= PPB_SPP;
624 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
637 ppc->ppc_epp = EPP_1_9; /* XXX */
643 if (ppc->ppc_model == NS_PC87332) {
651 printf(", Automatic mode");
669 /* default to NIBBLE mode */
679 ppc->ppc_avm = chipset_mode;
685 ppc->ppc_type = PPC_TYPE_GENERIC;
690 return(-1);
703 int type = -1;
706 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
711 * Detection: enter configuration mode and read CRD register.
736 /* Another chance, CSR may be hard-configured to be at 0x370 */
744 if (type == -1) {
745 outb(csr, 0xaa); /* end config mode */
746 return (-1);
754 if (port_address[(int)r] != ppc->ppc_base) {
755 outb(csr, 0xaa); /* end config mode */
756 return (-1);
759 ppc->ppc_model = type;
762 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
763 * If SPP mode is detected, try to set ECP+EPP mode
768 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x",
779 /* autodetect mode */
781 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
783 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
790 /* already in extended parallel port mode, read CR4 */
796 ppc->ppc_avm |= PPB_SPP;
802 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
808 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
814 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
820 /* not an extended port mode */
821 ppc->ppc_avm |= PPB_SPP;
827 /* mode forced */
828 ppc->ppc_avm = chipset_mode;
830 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
836 /* do not use ECP when the mode is not forced to */
841 /* an extended mode is selected */
844 /* read CR4 register and reset mode field */
865 ppc->ppc_avm = chipset_mode;
869 if (ppc->ppc_avm & PPB_ECP) {
880 if (ppc->ppc_avm & PPB_EPP) {
889 if (ppc->ppc_epp == EPP_1_9)
895 outb(csr, 0xaa); /* end config mode */
897 ppc->ppc_type = PPC_TYPE_SMCLIKE;
910 int type = -1;
913 outb(SMC935_CFG, 0x55); /* enter config mode */
921 if (type == -1) {
922 outb(SMC935_CFG, 0xaa); /* exit config mode */
923 return (-1);
926 ppc->ppc_model = type;
933 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
935 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
938 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
940 ppc->ppc_avm = chipset_mode;
942 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
947 if (ppc->ppc_epp == EPP_1_9) {
951 if (ppc->ppc_epp == EPP_1_7) {
964 if (ppc->ppc_epp == EPP_1_9) {
968 if (ppc->ppc_epp == EPP_1_7) {
979 outb(SMC935_CFG, 0xaa); /* exit config mode */
981 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1025 * 0 1 write 89h to 250h (power-on default)
1034 return (-1); /* failed */
1037 /* check base port address - read from CR23 */
1039 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1040 return (-1);
1042 /* read CHIP ID from CR9/bits0-3 */
1047 ppc->ppc_model = WINB_W83877F;
1051 ppc->ppc_model = WINB_W83877AF;
1055 ppc->ppc_model = WINB_UNKNOWN;
1060 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]);
1078 ppc->ppc_type = PPC_TYPE_GENERIC;
1081 /* autodetect mode */
1094 device_printf(ppc->ppc_dev,
1095 "W83757 compatible mode\n");
1096 return (-1); /* generic or SMC-like */
1103 device_printf(ppc->ppc_dev,
1104 "not in parallel port mode\n");
1105 return (-1);
1108 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1110 device_printf(ppc->ppc_dev, "EPP SPP\n");
1114 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1116 device_printf(ppc->ppc_dev, "ECP SPP\n");
1120 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1121 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1124 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n");
1131 /* mode forced */
1145 device_printf(ppc->ppc_dev,
1148 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1153 device_printf(ppc->ppc_dev, "ECP\n");
1159 device_printf(ppc->ppc_dev, "EPP SPP\n");
1161 ppc->ppc_avm = chipset_mode;
1164 /* exit configuration mode */
1167 switch (ppc->ppc_type) {
1187 ppc->ppc_type = PPC_TYPE_GENERIC;
1190 device_printf(ppc->ppc_dev, "SPP");
1195 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1199 /* search for SMC style ECP+EPP mode */
1205 ppc->ppc_dtm |= PPB_EPP;
1207 if (ppc->ppc_dtm & PPB_ECP) {
1209 ppc->ppc_model = SMC_LIKE;
1210 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1219 /* restore to standard mode */
1223 /* XXX try to detect NIBBLE and PS2 modes */
1224 ppc->ppc_dtm |= PPB_NIBBLE;
1227 ppc->ppc_avm = chipset_mode;
1229 ppc->ppc_avm = ppc->ppc_dtm;
1234 switch (ppc->ppc_type) {
1249 * mode is the mode suggested at boot
1254 int i, mode;
1267 /* if can't find the port and mode not forced return error */
1271 /* assume centronics compatible mode is supported */
1272 ppc->ppc_avm = PPB_COMPATIBLE;
1276 * chipset running modes and IEEE-1284 operating modes
1278 * after detection, the port must support running in compatible mode
1280 if (ppc->ppc_flags & 0x40) {
1285 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1290 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1291 ppc->ppc_mode = mode;
1299 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1327 /* microsequence registers are equivalent to PC-like port registers */
1329 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg))
1330 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte))
1337 switch (mi->opcode) {
1339 cc = r_reg(mi->arg[0].i, ppc);
1340 cc &= (char)mi->arg[2].i; /* clear mask */
1341 cc |= (char)mi->arg[1].i; /* assert mask */
1342 w_reg(mi->arg[0].i, ppc, cc);
1347 reg = mi->arg[1].i;
1348 ptr = ppc->ppc_ptr;
1350 if ((len = mi->arg[0].i) == MS_ACCUM) {
1351 accum = ppc->ppc_accum;
1352 for (; accum; accum--)
1354 ppc->ppc_accum = accum;
1358 ppc->ppc_ptr = ptr;
1364 reg = mi->arg[1].i;
1365 mask = (char)mi->arg[2].i;
1366 ptr = ppc->ppc_ptr;
1368 if ((len = mi->arg[0].i) == MS_ACCUM) {
1369 accum = ppc->ppc_accum;
1370 for (; accum; accum--)
1372 ppc->ppc_accum = accum;
1376 ppc->ppc_ptr = ptr;
1382 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1383 (char)mi->arg[1].i;
1392 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1393 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1395 if (mi->opcode == MS_OP_DELAY) {
1396 DELAY(mi->arg[0].i);
1403 if (mi->arg[0].i) {
1405 pause("ppbdelay", mi->arg[0].i * (hz/1000));
1412 reg = mi->arg[0].i;
1413 iter = mi->arg[1].i;
1414 p = (char *)mi->arg[2].p;
1416 /* XXX delay limited to 255 us */
1425 ppc->ppc_accum = mi->arg[0].i;
1430 if (--ppc->ppc_accum > 0)
1431 mi += mi->arg[0].i;
1437 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1438 mi += mi->arg[1].i;
1444 if ((cc & (char)mi->arg[0].i) == 0)
1445 mi += mi->arg[1].i;
1451 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1452 (char)mi->arg[0].i)
1453 mi += mi->arg[2].i;
1462 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1469 ppc->ppc_ptr = (char *)mi->arg[0].p;
1477 if (mi->arg[0].p) {
1484 mi = (struct ppb_microseq *)mi->arg[0].p;
1497 /* XXX return code */
1519 __func__, mi->opcode);
1536 * XXX: If DMA is in progress should we just complete that w/o
1540 if (ppc->ppc_intr_hook != NULL &&
1541 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) {
1554 /* don't use ecp mode with IRQENABLE set */
1561 * only in ECP mode */
1562 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1565 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1567 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1569 /* shall be handled by underlying layers XXX */
1575 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1578 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1582 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1590 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1594 ppc->ppc_dmadone(ppc);
1595 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1601 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1603 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1611 ppc_read(device_t dev, char *buf, int len, int mode)
1634 ppc_setmode(device_t dev, int mode)
1639 switch (ppc->ppc_type) {
1641 return (ppc_smclike_setmode(ppc, mode));
1646 return (ppc_generic_setmode(ppc, mode));
1670 ppc->rid_ioport = rid;
1698 ppc->res_ioport = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
1699 &ppc->rid_ioport,
1703 if (ppc->res_ioport != 0) {
1708 ppc->res_ioport = bus_alloc_resource_anywhere(dev,
1710 &ppc->rid_ioport,
1713 if (ppc->res_ioport != 0) {
1723 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1725 ppc->ppc_flags = device_get_flags(dev);
1727 if (!(ppc->ppc_flags & 0x20)) {
1728 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1729 &ppc->rid_irq,
1731 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1732 &ppc->rid_drq,
1736 if (ppc->res_irq)
1737 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1738 if (ppc->res_drq)
1739 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1741 ppc->ppc_dev = dev;
1742 ppc->ppc_model = GENERIC;
1744 ppc->ppc_mode = PPB_COMPATIBLE;
1745 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1747 ppc->ppc_type = PPC_TYPE_GENERIC;
1750 * Try to detect the chipset and its mode.
1752 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1758 if (ppc->res_irq != 0) {
1759 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1760 ppc->res_irq);
1762 if (ppc->res_ioport != 0) {
1763 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1764 ppc->res_ioport);
1766 if (ppc->res_drq != 0) {
1767 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1768 ppc->res_drq);
1779 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF);
1781 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1782 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1783 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1784 ppc_epp_protocol[ppc->ppc_epp] : "");
1786 if (ppc->ppc_fifo)
1788 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1790 if (ppc->res_irq) {
1791 /* default to the tty mask for registration */ /* XXX */
1792 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY |
1793 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie);
1798 mtx_destroy(&ppc->ppc_lock);
1804 ppc->ppbus = device_add_child(dev, "ppbus", DEVICE_UNIT_ANY);
1809 device_probe_and_attach(ppc->ppbus);
1819 if (ppc->res_irq == 0) {
1826 if (ppc->res_irq != 0) {
1827 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
1828 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1829 ppc->res_irq);
1831 if (ppc->res_ioport != 0) {
1832 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1833 ppc->res_ioport);
1835 if (ppc->res_drq != 0) {
1836 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1837 ppc->res_drq);
1840 mtx_destroy(&ppc->ppc_lock);
1853 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1856 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1859 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1862 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1865 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1868 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1921 *val = (u_long)ppc->ppc_epp;
1924 *val = (uintptr_t)&ppc->ppc_lock;
1941 if (dev != ppc->ppbus)
1944 ppc->ppc_intr_hook = NULL;
1947 if (ppc->ppc_intr_hook != NULL)
1949 ppc->ppc_intr_hook = (void *)val;
1950 ppc->ppc_intr_arg = device_get_softc(dev);
1972 return (ppc->res_irq);
1983 if (r == ppc->res_irq)