Lines Matching +full:config +full:- +full:complete +full:- +full:timeout +full:- +full:us
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 1997-2000 Nicolas Souchu
5 * Copyright (c) 2001 Alcove - Nicolas Souchu
74 * We use critical enter/exit for the simple config locking needed to
76 * happen without someone else also writing to those config registers. Since
78 * and critical_enter() then is all that's needed to keep us from being preempted
82 * config mode, but since we only do that to detect the type at startup the
83 * extra overhead isn't needed since Giant protects us from multiple entry
92 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
99 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
100 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
119 * BIOS printer list - used by BIOS probe.
136 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) in ppc_ecp_sync()
174 /* read PWord size - transfers in FIFO mode must be PWord aligned */ in ppc_detect_fifo()
175 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); in ppc_detect_fifo()
178 if (ppc->ppc_pword != PPC_PWORD_8) { in ppc_detect_fifo()
210 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { in ppc_detect_fifo()
212 ppc->ppc_rthr = i+1; in ppc_detect_fifo()
215 ppc->ppc_fifo = i+1; in ppc_detect_fifo()
232 for (i=ppc->ppc_fifo; i>0; i--) { in ppc_detect_fifo()
233 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { in ppc_detect_fifo()
239 ppc->ppc_wthr = ppc->ppc_fifo - i+1; in ppc_detect_fifo()
279 * EPP timeout, according to the PC87332 manual
280 * Semantics of clearing EPP timeout bit.
281 * PC87332 - reading SPP_STR does it...
282 * SMC - write 1 to EPP timeout bit XXX
283 * Others - (?) write 0 to EPP timeout bit
302 return (!(r_str(ppc) & TIMEOUT)); in ppc_check_epp_timeout()
314 if (mode && !(ppc->ppc_avm & mode)) in ppc_generic_setmode()
318 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { in ppc_generic_setmode()
341 ppc->ppc_mode = mode; in ppc_generic_setmode()
359 if (mode && !(ppc->ppc_avm & mode)) in ppc_smclike_setmode()
363 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { in ppc_smclike_setmode()
387 ppc->ppc_mode = mode; in ppc_smclike_setmode()
396 * Probe for a Natsemi PC873xx-family part.
409 PC873_PNP1, PC873_LPTBA, -1
429 * Pull the 873xx through the power-on ID cycle (2.2,1.). in ppc_pc873xx_detect()
447 ppc->ppc_model = NS_PC87332; in ppc_pc873xx_detect()
449 ppc->ppc_model = NS_PC87306; in ppc_pc873xx_detect()
451 ppc->ppc_model = NS_PC87334; in ppc_pc873xx_detect()
455 ppc->ppc_model = NS_PC87303; in ppc_pc873xx_detect()
465 for (i=0; pc873xx_regstab[i] != -1; i++) { in ppc_pc873xx_detect()
486 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) { in ppc_pc873xx_detect()
489 switch (ppc->ppc_base) { in ppc_pc873xx_detect()
519 if (pc873xx_porttab[val] != ppc->ppc_base) { in ppc_pc873xx_detect()
522 pc873xx_porttab[val], ppc->ppc_base); in ppc_pc873xx_detect()
531 if (ppc->ppc_base == 0x378) in ppc_pc873xx_detect()
537 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); in ppc_pc873xx_detect()
542 if (irq != ppc->ppc_irq) { in ppc_pc873xx_detect()
547 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { in ppc_pc873xx_detect()
548 if (ppc->ppc_irq == 7) { in ppc_pc873xx_detect()
556 printf("PC873xx irq set to %d\n", ppc->ppc_irq); in ppc_pc873xx_detect()
573 ppc->ppc_avm |= PPB_NIBBLE; in ppc_pc873xx_detect()
578 ppc->ppc_avm |= PPB_EPP; in ppc_pc873xx_detect()
584 ppc->ppc_epp = EPP_1_9; in ppc_pc873xx_detect()
586 ppc->ppc_epp = EPP_1_7; in ppc_pc873xx_detect()
588 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { in ppc_pc873xx_detect()
597 ppc->ppc_avm |= PPB_ECP; in ppc_pc873xx_detect()
602 ppc->ppc_avm |= PPB_PS2; in ppc_pc873xx_detect()
610 ppc->ppc_avm |= PPB_SPP; in ppc_pc873xx_detect()
637 ppc->ppc_epp = EPP_1_9; /* XXX */ in ppc_pc873xx_detect()
643 if (ppc->ppc_model == NS_PC87332) { in ppc_pc873xx_detect()
679 ppc->ppc_avm = chipset_mode; in ppc_pc873xx_detect()
685 ppc->ppc_type = PPC_TYPE_GENERIC; in ppc_pc873xx_detect()
690 return(-1); in ppc_pc873xx_detect()
703 int type = -1; in ppc_smc37c66xgt_detect()
706 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; in ppc_smc37c66xgt_detect()
708 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ in ppc_smc37c66xgt_detect()
721 goto config; in ppc_smc37c66xgt_detect()
736 /* Another chance, CSR may be hard-configured to be at 0x370 */ in ppc_smc37c66xgt_detect()
740 config: in ppc_smc37c66xgt_detect()
744 if (type == -1) { in ppc_smc37c66xgt_detect()
745 outb(csr, 0xaa); /* end config mode */ in ppc_smc37c66xgt_detect()
746 return (-1); in ppc_smc37c66xgt_detect()
754 if (port_address[(int)r] != ppc->ppc_base) { in ppc_smc37c66xgt_detect()
755 outb(csr, 0xaa); /* end config mode */ in ppc_smc37c66xgt_detect()
756 return (-1); in ppc_smc37c66xgt_detect()
759 ppc->ppc_model = type; in ppc_smc37c66xgt_detect()
768 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x", in ppc_smc37c66xgt_detect()
783 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; in ppc_smc37c66xgt_detect()
796 ppc->ppc_avm |= PPB_SPP; in ppc_smc37c66xgt_detect()
802 ppc->ppc_avm |= PPB_EPP | PPB_SPP; in ppc_smc37c66xgt_detect()
808 ppc->ppc_avm |= PPB_ECP | PPB_SPP; in ppc_smc37c66xgt_detect()
814 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; in ppc_smc37c66xgt_detect()
821 ppc->ppc_avm |= PPB_SPP; in ppc_smc37c66xgt_detect()
828 ppc->ppc_avm = chipset_mode; in ppc_smc37c66xgt_detect()
865 ppc->ppc_avm = chipset_mode; in ppc_smc37c66xgt_detect()
869 if (ppc->ppc_avm & PPB_ECP) { in ppc_smc37c66xgt_detect()
880 if (ppc->ppc_avm & PPB_EPP) { in ppc_smc37c66xgt_detect()
889 if (ppc->ppc_epp == EPP_1_9) in ppc_smc37c66xgt_detect()
895 outb(csr, 0xaa); /* end config mode */ in ppc_smc37c66xgt_detect()
897 ppc->ppc_type = PPC_TYPE_SMCLIKE; in ppc_smc37c66xgt_detect()
910 int type = -1; in ppc_smc37c935_detect()
913 outb(SMC935_CFG, 0x55); /* enter config mode */ in ppc_smc37c935_detect()
921 if (type == -1) { in ppc_smc37c935_detect()
922 outb(SMC935_CFG, 0xaa); /* exit config mode */ in ppc_smc37c935_detect()
923 return (-1); in ppc_smc37c935_detect()
926 ppc->ppc_model = type; in ppc_smc37c935_detect()
933 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); in ppc_smc37c935_detect()
935 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); in ppc_smc37c935_detect()
938 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ in ppc_smc37c935_detect()
940 ppc->ppc_avm = chipset_mode; in ppc_smc37c935_detect()
947 if (ppc->ppc_epp == EPP_1_9) { in ppc_smc37c935_detect()
951 if (ppc->ppc_epp == EPP_1_7) { in ppc_smc37c935_detect()
964 if (ppc->ppc_epp == EPP_1_9) { in ppc_smc37c935_detect()
968 if (ppc->ppc_epp == EPP_1_7) { in ppc_smc37c935_detect()
979 outb(SMC935_CFG, 0xaa); /* exit config mode */ in ppc_smc37c935_detect()
981 ppc->ppc_type = PPC_TYPE_SMCLIKE; in ppc_smc37c935_detect()
1025 * 0 1 write 89h to 250h (power-on default) in ppc_w83877f_detect()
1034 return (-1); /* failed */ in ppc_w83877f_detect()
1037 /* check base port address - read from CR23 */ in ppc_w83877f_detect()
1039 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ in ppc_w83877f_detect()
1040 return (-1); in ppc_w83877f_detect()
1042 /* read CHIP ID from CR9/bits0-3 */ in ppc_w83877f_detect()
1047 ppc->ppc_model = WINB_W83877F; in ppc_w83877f_detect()
1051 ppc->ppc_model = WINB_W83877AF; in ppc_w83877f_detect()
1055 ppc->ppc_model = WINB_UNKNOWN; in ppc_w83877f_detect()
1060 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]); in ppc_w83877f_detect()
1078 ppc->ppc_type = PPC_TYPE_GENERIC; in ppc_w83877f_detect()
1094 device_printf(ppc->ppc_dev, in ppc_w83877f_detect()
1096 return (-1); /* generic or SMC-like */ in ppc_w83877f_detect()
1103 device_printf(ppc->ppc_dev, in ppc_w83877f_detect()
1105 return (-1); in ppc_w83877f_detect()
1108 ppc->ppc_avm |= PPB_EPP | PPB_SPP; in ppc_w83877f_detect()
1110 device_printf(ppc->ppc_dev, "EPP SPP\n"); in ppc_w83877f_detect()
1114 ppc->ppc_avm |= PPB_ECP | PPB_SPP; in ppc_w83877f_detect()
1116 device_printf(ppc->ppc_dev, "ECP SPP\n"); in ppc_w83877f_detect()
1120 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; in ppc_w83877f_detect()
1121 ppc->ppc_type = PPC_TYPE_SMCLIKE; in ppc_w83877f_detect()
1124 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n"); in ppc_w83877f_detect()
1145 device_printf(ppc->ppc_dev, in ppc_w83877f_detect()
1148 ppc->ppc_type = PPC_TYPE_SMCLIKE; in ppc_w83877f_detect()
1153 device_printf(ppc->ppc_dev, "ECP\n"); in ppc_w83877f_detect()
1159 device_printf(ppc->ppc_dev, "EPP SPP\n"); in ppc_w83877f_detect()
1161 ppc->ppc_avm = chipset_mode; in ppc_w83877f_detect()
1167 switch (ppc->ppc_type) { in ppc_w83877f_detect()
1187 ppc->ppc_type = PPC_TYPE_GENERIC; in ppc_generic_detect()
1190 device_printf(ppc->ppc_dev, "SPP"); in ppc_generic_detect()
1195 ppc->ppc_dtm |= PPB_ECP | PPB_SPP; in ppc_generic_detect()
1203 /* try to reset EPP timeout bit */ in ppc_generic_detect()
1205 ppc->ppc_dtm |= PPB_EPP; in ppc_generic_detect()
1207 if (ppc->ppc_dtm & PPB_ECP) { in ppc_generic_detect()
1209 ppc->ppc_model = SMC_LIKE; in ppc_generic_detect()
1210 ppc->ppc_type = PPC_TYPE_SMCLIKE; in ppc_generic_detect()
1224 ppc->ppc_dtm |= PPB_NIBBLE; in ppc_generic_detect()
1227 ppc->ppc_avm = chipset_mode; in ppc_generic_detect()
1229 ppc->ppc_avm = ppc->ppc_dtm; in ppc_generic_detect()
1234 switch (ppc->ppc_type) { in ppc_generic_detect()
1272 ppc->ppc_avm = PPB_COMPATIBLE; in ppc_detect()
1276 * chipset running modes and IEEE-1284 operating modes in ppc_detect()
1280 if (ppc->ppc_flags & 0x40) { in ppc_detect()
1285 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); in ppc_detect()
1290 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { in ppc_detect()
1291 ppc->ppc_mode = mode; in ppc_detect()
1299 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) in ppc_detect()
1327 /* microsequence registers are equivalent to PC-like port registers */ in ppc_exec_microseq()
1329 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg)) in ppc_exec_microseq()
1330 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte)) in ppc_exec_microseq()
1337 switch (mi->opcode) { in ppc_exec_microseq()
1339 cc = r_reg(mi->arg[0].i, ppc); in ppc_exec_microseq()
1340 cc &= (char)mi->arg[2].i; /* clear mask */ in ppc_exec_microseq()
1341 cc |= (char)mi->arg[1].i; /* assert mask */ in ppc_exec_microseq()
1342 w_reg(mi->arg[0].i, ppc, cc); in ppc_exec_microseq()
1347 reg = mi->arg[1].i; in ppc_exec_microseq()
1348 ptr = ppc->ppc_ptr; in ppc_exec_microseq()
1350 if ((len = mi->arg[0].i) == MS_ACCUM) { in ppc_exec_microseq()
1351 accum = ppc->ppc_accum; in ppc_exec_microseq()
1352 for (; accum; accum--) in ppc_exec_microseq()
1354 ppc->ppc_accum = accum; in ppc_exec_microseq()
1358 ppc->ppc_ptr = ptr; in ppc_exec_microseq()
1364 reg = mi->arg[1].i; in ppc_exec_microseq()
1365 mask = (char)mi->arg[2].i; in ppc_exec_microseq()
1366 ptr = ppc->ppc_ptr; in ppc_exec_microseq()
1368 if ((len = mi->arg[0].i) == MS_ACCUM) { in ppc_exec_microseq()
1369 accum = ppc->ppc_accum; in ppc_exec_microseq()
1370 for (; accum; accum--) in ppc_exec_microseq()
1372 ppc->ppc_accum = accum; in ppc_exec_microseq()
1376 ppc->ppc_ptr = ptr; in ppc_exec_microseq()
1382 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & in ppc_exec_microseq()
1383 (char)mi->arg[1].i; in ppc_exec_microseq()
1392 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) in ppc_exec_microseq()
1393 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); in ppc_exec_microseq()
1395 if (mi->opcode == MS_OP_DELAY) { in ppc_exec_microseq()
1396 DELAY(mi->arg[0].i); in ppc_exec_microseq()
1403 if (mi->arg[0].i) { in ppc_exec_microseq()
1405 pause("ppbdelay", mi->arg[0].i * (hz/1000)); in ppc_exec_microseq()
1412 reg = mi->arg[0].i; in ppc_exec_microseq()
1413 iter = mi->arg[1].i; in ppc_exec_microseq()
1414 p = (char *)mi->arg[2].p; in ppc_exec_microseq()
1416 /* XXX delay limited to 255 us */ in ppc_exec_microseq()
1425 ppc->ppc_accum = mi->arg[0].i; in ppc_exec_microseq()
1430 if (--ppc->ppc_accum > 0) in ppc_exec_microseq()
1431 mi += mi->arg[0].i; in ppc_exec_microseq()
1437 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) in ppc_exec_microseq()
1438 mi += mi->arg[1].i; in ppc_exec_microseq()
1444 if ((cc & (char)mi->arg[0].i) == 0) in ppc_exec_microseq()
1445 mi += mi->arg[1].i; in ppc_exec_microseq()
1451 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == in ppc_exec_microseq()
1452 (char)mi->arg[0].i) in ppc_exec_microseq()
1453 mi += mi->arg[2].i; in ppc_exec_microseq()
1462 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) in ppc_exec_microseq()
1469 ppc->ppc_ptr = (char *)mi->arg[0].p; in ppc_exec_microseq()
1477 if (mi->arg[0].p) { in ppc_exec_microseq()
1484 mi = (struct ppb_microseq *)mi->arg[0].p; in ppc_exec_microseq()
1519 __func__, mi->opcode); in ppc_exec_microseq()
1536 * XXX: If DMA is in progress should we just complete that w/o in ppcintr()
1540 if (ppc->ppc_intr_hook != NULL && in ppcintr()
1541 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) { in ppcintr()
1562 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { in ppcintr()
1565 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { in ppcintr()
1567 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; in ppcintr()
1575 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { in ppcintr()
1578 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; in ppcintr()
1582 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { in ppcintr()
1590 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { in ppcintr()
1594 ppc->ppc_dmadone(ppc); in ppcintr()
1595 ppc->ppc_dmastat = PPC_DMA_COMPLETE; in ppcintr()
1601 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { in ppcintr()
1603 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; in ppcintr()
1639 switch (ppc->ppc_type) { in ppc_setmode()
1670 ppc->rid_ioport = rid; in ppc_probe()
1698 ppc->res_ioport = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, in ppc_probe()
1699 &ppc->rid_ioport, in ppc_probe()
1703 if (ppc->res_ioport != 0) { in ppc_probe()
1708 ppc->res_ioport = bus_alloc_resource_anywhere(dev, in ppc_probe()
1710 &ppc->rid_ioport, in ppc_probe()
1713 if (ppc->res_ioport != 0) { in ppc_probe()
1723 ppc->ppc_base = rman_get_start(ppc->res_ioport); in ppc_probe()
1725 ppc->ppc_flags = device_get_flags(dev); in ppc_probe()
1727 if (!(ppc->ppc_flags & 0x20)) { in ppc_probe()
1728 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, in ppc_probe()
1729 &ppc->rid_irq, in ppc_probe()
1731 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ, in ppc_probe()
1732 &ppc->rid_drq, in ppc_probe()
1736 if (ppc->res_irq) in ppc_probe()
1737 ppc->ppc_irq = rman_get_start(ppc->res_irq); in ppc_probe()
1738 if (ppc->res_drq) in ppc_probe()
1739 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); in ppc_probe()
1741 ppc->ppc_dev = dev; in ppc_probe()
1742 ppc->ppc_model = GENERIC; in ppc_probe()
1744 ppc->ppc_mode = PPB_COMPATIBLE; in ppc_probe()
1745 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; in ppc_probe()
1747 ppc->ppc_type = PPC_TYPE_GENERIC; in ppc_probe()
1752 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) in ppc_probe()
1758 if (ppc->res_irq != 0) { in ppc_probe()
1759 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, in ppc_probe()
1760 ppc->res_irq); in ppc_probe()
1762 if (ppc->res_ioport != 0) { in ppc_probe()
1763 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, in ppc_probe()
1764 ppc->res_ioport); in ppc_probe()
1766 if (ppc->res_drq != 0) { in ppc_probe()
1767 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, in ppc_probe()
1768 ppc->res_drq); in ppc_probe()
1779 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF); in ppc_attach()
1782 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], in ppc_attach()
1783 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? in ppc_attach()
1784 ppc_epp_protocol[ppc->ppc_epp] : ""); in ppc_attach()
1786 if (ppc->ppc_fifo) in ppc_attach()
1788 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); in ppc_attach()
1790 if (ppc->res_irq) { in ppc_attach()
1792 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY | in ppc_attach()
1793 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie); in ppc_attach()
1798 mtx_destroy(&ppc->ppc_lock); in ppc_attach()
1804 ppc->ppbus = device_add_child(dev, "ppbus", DEVICE_UNIT_ANY); in ppc_attach()
1809 device_probe_and_attach(ppc->ppbus); in ppc_attach()
1820 if (ppc->res_irq == 0) { in ppc_detach()
1829 if (ppc->res_irq != 0) { in ppc_detach()
1830 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie); in ppc_detach()
1831 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, in ppc_detach()
1832 ppc->res_irq); in ppc_detach()
1834 if (ppc->res_ioport != 0) { in ppc_detach()
1835 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, in ppc_detach()
1836 ppc->res_ioport); in ppc_detach()
1838 if (ppc->res_drq != 0) { in ppc_detach()
1839 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, in ppc_detach()
1840 ppc->res_drq); in ppc_detach()
1843 mtx_destroy(&ppc->ppc_lock); in ppc_detach()
1856 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); in ppc_io()
1859 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); in ppc_io()
1862 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); in ppc_io()
1865 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); in ppc_io()
1868 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); in ppc_io()
1871 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); in ppc_io()
1924 *val = (u_long)ppc->ppc_epp; in ppc_read_ivar()
1927 *val = (uintptr_t)&ppc->ppc_lock; in ppc_read_ivar()
1944 if (dev != ppc->ppbus) in ppc_write_ivar()
1947 ppc->ppc_intr_hook = NULL; in ppc_write_ivar()
1950 if (ppc->ppc_intr_hook != NULL) in ppc_write_ivar()
1952 ppc->ppc_intr_hook = (void *)val; in ppc_write_ivar()
1953 ppc->ppc_intr_arg = device_get_softc(dev); in ppc_write_ivar()
1975 return (ppc->res_irq); in ppc_alloc_resource()
1986 if (r == ppc->res_irq) in ppc_release_resource()