94 	"SMC FDC37C935", "PC87303", 0
102 	"ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
112 	"ECP+EPP", "ECP+EPP", "ECP+EPP", 0
115 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
121 #define	BIOS_PPC_PORTS	0x408
137 		return 0;  in ppc_ecp_sync()
140 	if ((r & 0xe0) != PPC_ECR_EPP)  in ppc_ecp_sync()
141 		return 0;  in ppc_ecp_sync()
143 	for (i = 0; i < 100; i++) {  in ppc_ecp_sync()
145 		if (r & 0x1)  in ppc_ecp_sync()
146 			return 0;  in ppc_ecp_sync()
152 	return 0;  in ppc_ecp_sync()
172 	w_ecr(ppc, 0xf4);  in ppc_detect_fifo()
183 	w_ecr(ppc, 0x34);		/* byte mode, no interrupt, no DMA */  in ppc_detect_fifo()
188 	w_ecr(ppc, 0xd4);  in ppc_detect_fifo()
191 	for (i=0; i<1024; i++) {  in ppc_detect_fifo()
203 	w_ecr(ppc, 0xd0);  in ppc_detect_fifo()
208 	for (i=0; i<1024; i++) {  in ppc_detect_fifo()
225 	w_ecr(ppc, 0xd4);		/* test mode, no interrupt, no DMA */  in ppc_detect_fifo()
226 	w_ctr(ppc, ctr & ~PCD);		/* set direction to 0 */  in ppc_detect_fifo()
227 	w_ecr(ppc, 0xd0);		/* enable interrupts */  in ppc_detect_fifo()
232 	for (i=ppc->ppc_fifo; i>0; i--) {  in ppc_detect_fifo()
257 	return (0);  in ppc_detect_fifo()
270 	w_ctr(ppc, 0x0c);	/* To avoid missing PS2 ports */  in ppc_detect_port()
271 	w_dtr(ppc, 0xaa);  in ppc_detect_port()
272 	if (r_dtr(ppc) != 0xaa)  in ppc_detect_port()
273 		return (0);  in ppc_detect_port()
283  * Others	- (?) write 0 to EPP timeout bit
291 	w_str(ppc, r | 0x1);  in ppc_reset_epp_timeout()
292 	w_str(ppc, r & 0xfe);  in ppc_reset_epp_timeout()
311 	u_char ecr = 0;  in ppc_generic_setmode()
343 	return (0);  in ppc_generic_setmode()
356 	u_char ecr = 0;  in ppc_smclike_setmode()
389 	return (0);  in ppc_smclike_setmode()
401 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
402 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
403 static int pc873xx_irqtab[] = {5, 7, 5, 0};
421     static int	index = 0;  in ppc_pc873xx_detect()
446 	if ((val & 0xf0) == 0x10) {  in ppc_pc873xx_detect()
448 	} else if ((val & 0xf8) == 0x70) {  in ppc_pc873xx_detect()
450 	} else if ((val & 0xf8) == 0x50) {  in ppc_pc873xx_detect()
452 	} else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the  in ppc_pc873xx_detect()
454 					      yielded 0x40... */  in ppc_pc873xx_detect()
457 	    if (bootverbose && (val != 0xff))  in ppc_pc873xx_detect()
458 		printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);  in ppc_pc873xx_detect()
465 		for (i=0; pc873xx_regstab[i] != -1; i++) {  in ppc_pc873xx_detect()
467 			printf(" %s=0x%x", pc873xx_rnametab[i],  in ppc_pc873xx_detect()
468 						inb(idport + 1) & 0xff);  in ppc_pc873xx_detect()
486 	if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {  in ppc_pc873xx_detect()
490 		case 0x378:  in ppc_pc873xx_detect()
491 		val &= 0xfc;  in ppc_pc873xx_detect()
494 		case 0x3bc:  in ppc_pc873xx_detect()
495 		val &= 0xfd;  in ppc_pc873xx_detect()
498 		case 0x278:  in ppc_pc873xx_detect()
499 		val &= 0xfe;  in ppc_pc873xx_detect()
503 		val &= 0xfd;  in ppc_pc873xx_detect()
515 	    val = inb(idport + 1) & 0x3;  in ppc_pc873xx_detect()
521 	  	    printf("PC873xx at 0x%x not for driver at port 0x%x\n",  in ppc_pc873xx_detect()
531 	if (ppc->ppc_base == 0x378)  in ppc_pc873xx_detect()
537 		printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);  in ppc_pc873xx_detect()
544 		 * If the chipset is not locked and base address is 0x378,  in ppc_pc873xx_detect()
547 		if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {  in ppc_pc873xx_detect()
704 	int csr = SMC66x_CSR;	/* initial value is 0x3F0 */  in ppc_smc37c66xgt_detect()
706 	int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };  in ppc_smc37c66xgt_detect()
708 #define cio csr+1	/* config IO port is either 0x3F1 or 0x371 */  in ppc_smc37c66xgt_detect()
718 	outb(csr, 0xd);  in ppc_smc37c66xgt_detect()
719 	if (inb(cio) == 0x65) {  in ppc_smc37c66xgt_detect()
724 	for (i = 0; i < 2; i++) {  in ppc_smc37c66xgt_detect()
730 		outb(csr, 0xd);  in ppc_smc37c66xgt_detect()
731 		if (inb(cio) == 0x66) {  in ppc_smc37c66xgt_detect()
736 		/* Another chance, CSR may be hard-configured to be at 0x370 */  in ppc_smc37c66xgt_detect()
745 		outb(csr, 0xaa);	/* end config mode */  in ppc_smc37c66xgt_detect()
750 	outb(csr, 0x1);  in ppc_smc37c66xgt_detect()
752 	/* read the port's address: bits 0 and 1 of CR1 */  in ppc_smc37c66xgt_detect()
755 		outb(csr, 0xaa);	/* end config mode */  in ppc_smc37c66xgt_detect()
762 	 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration  in ppc_smc37c66xgt_detect()
767 		outb(csr, 0x1);  in ppc_smc37c66xgt_detect()
768 		device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x",  in ppc_smc37c66xgt_detect()
769 		    inb(cio) & 0xff);  in ppc_smc37c66xgt_detect()
771 		outb(csr, 0x4);  in ppc_smc37c66xgt_detect()
772 		printf(" CR4=0x%x", inb(cio) & 0xff);  in ppc_smc37c66xgt_detect()
776 	outb(csr, 0x1);  in ppc_smc37c66xgt_detect()
789 		   if ((inb(cio) & SMC_CR1_MODE) == 0) {  in ppc_smc37c66xgt_detect()
791 			outb(csr, 0x4);  in ppc_smc37c66xgt_detect()
835 		if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {  in ppc_smc37c66xgt_detect()
845 			outb(csr, 0x4);  in ppc_smc37c66xgt_detect()
871 		outb(csr, 0xa);  in ppc_smc37c66xgt_detect()
882 		outb(csr, 0x4);  in ppc_smc37c66xgt_detect()
895 	outb(csr, 0xaa);	/* end config mode */  in ppc_smc37c66xgt_detect()
913 	outb(SMC935_CFG, 0x55); /* enter config mode */  in ppc_smc37c935_detect()
914 	outb(SMC935_CFG, 0x55);  in ppc_smc37c935_detect()
918 	if (inb(SMC935_DAT) == 0x2)  in ppc_smc37c935_detect()
922 		outb(SMC935_CFG, 0xaa); /* exit config mode */  in ppc_smc37c935_detect()
933 	outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));  in ppc_smc37c935_detect()
935 	outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));  in ppc_smc37c935_detect()
979 	outb(SMC935_CFG, 0xaa); /* exit config mode */  in ppc_smc37c935_detect()
994 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
995 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
997 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
998 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1000 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1008 	for (i = 0; i < 4; i ++) {  in ppc_w83877f_detect()
1013 		for (j = 0; j < w83877f_keyiter[i]; j ++)  in ppc_w83877f_detect()
1017 		outb (efir, 0x0c);  in ppc_w83877f_detect()
1020 		outb (efir, 0x16);  in ppc_w83877f_detect()
1025 		 *   0		   1	write 89h to 250h (power-on default)  in ppc_w83877f_detect()
1026 		 *   1		   0	write 86h twice to 3f0h  in ppc_w83877f_detect()
1028 		 *   0		   0	write 88h to 250h  in ppc_w83877f_detect()
1038 	outb(efir, 0x23);  in ppc_w83877f_detect()
1043 	outb(efir, 0x9);  in ppc_w83877f_detect()
1060 		device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]);  in ppc_w83877f_detect()
1061 		for (i = 0; i <= 0xd; i ++) {  in ppc_w83877f_detect()
1063 			printf("0x%x ", inb(efdr));  in ppc_w83877f_detect()
1065 		for (i = 0x10; i <= 0x17; i ++) {  in ppc_w83877f_detect()
1067 			printf("0x%x ", inb(efdr));  in ppc_w83877f_detect()
1069 		outb(efir, 0x1e);  in ppc_w83877f_detect()
1070 		printf("0x%x ", inb(efdr));  in ppc_w83877f_detect()
1071 		for (i = 0x20; i <= 0x29; i ++) {  in ppc_w83877f_detect()
1073 			printf("0x%x ", inb(efdr));  in ppc_w83877f_detect()
1084 		outb(efir, 0x0);  in ppc_w83877f_detect()
1088 		outb(efir, 0x9);  in ppc_w83877f_detect()
1127 			printf("%s: unknown case (0x%x)!\n", __func__, r);  in ppc_w83877f_detect()
1134 		outb(efir, 0x9);  in ppc_w83877f_detect()
1138 		outb(efir, 0x0);  in ppc_w83877f_detect()
1165 	outb(efer, 0xaa);  in ppc_w83877f_detect()
1194 	if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {  in ppc_generic_detect()
1268 	if (!ppc_detect_port(ppc) && chipset_mode == 0)  in ppc_detect()
1280 	if (ppc->ppc_flags & 0x40) {  in ppc_detect()
1289 		for (i=0; chipset_detect[i] != NULL; i++) {  in ppc_detect()
1299 	if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))  in ppc_detect()
1302 	return (0);  in ppc_detect()
1322 	int accum = 0;  in ppc_exec_microseq()
1339 			cc = r_reg(mi->arg[0].i, ppc);  in ppc_exec_microseq()
1342 			w_reg(mi->arg[0].i, ppc, cc);  in ppc_exec_microseq()
1350 			if ((len = mi->arg[0].i) == MS_ACCUM) {  in ppc_exec_microseq()
1356 				for (i=0; i<len; i++)  in ppc_exec_microseq()
1368 			if ((len = mi->arg[0].i) == MS_ACCUM) {  in ppc_exec_microseq()
1374 				for (i=0; i<len; i++)  in ppc_exec_microseq()
1382 			*((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &  in ppc_exec_microseq()
1393 				w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);  in ppc_exec_microseq()
1396 				DELAY(mi->arg[0].i);  in ppc_exec_microseq()
1403 			if (mi->arg[0].i) {  in ppc_exec_microseq()
1405 				pause("ppbdelay", mi->arg[0].i * (hz/1000));  in ppc_exec_microseq()
1412 			reg = mi->arg[0].i;  in ppc_exec_microseq()
1417 			for (i=0; i<iter; i++) {  in ppc_exec_microseq()
1425 			ppc->ppc_accum = mi->arg[0].i;  in ppc_exec_microseq()
1430 			if (--ppc->ppc_accum > 0)  in ppc_exec_microseq()
1431 				mi += mi->arg[0].i;  in ppc_exec_microseq()
1437 			if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)  in ppc_exec_microseq()
1444 			if ((cc & (char)mi->arg[0].i) == 0)  in ppc_exec_microseq()
1451 			if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==  in ppc_exec_microseq()
1452 							(char)mi->arg[0].i)  in ppc_exec_microseq()
1459 			 * If the C call returns !0 then end the microseq.  in ppc_exec_microseq()
1462 			if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))  in ppc_exec_microseq()
1469 			ppc->ppc_ptr = (char *)mi->arg[0].p;  in ppc_exec_microseq()
1477 			if (mi->arg[0].p) {  in ppc_exec_microseq()
1484 				mi = (struct ppb_microseq *)mi->arg[0].p;  in ppc_exec_microseq()
1515 			return (0);  in ppc_exec_microseq()
1518 			panic("%s: unknown microsequence opcode 0x%x",  in ppc_exec_microseq()
1541 	    ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) {  in ppcintr()
1630 	return 0;  in ppc_reset_epp()
1659 	static short next_bios_ppc = 0;  in ppc_probe()
1681 		    (*(BIOS_PORTS + next_bios_ppc) != 0)) {  in ppc_probe()
1685 				    "parallel port found at 0x%jx\n", port);  in ppc_probe()
1703 	if (ppc->res_ioport != 0) {  in ppc_probe()
1713 		if (ppc->res_ioport != 0) {  in ppc_probe()
1727 	if (!(ppc->ppc_flags & 0x20)) {  in ppc_probe()
1745 	ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;  in ppc_probe()
1752 	if (ppc_detect(ppc, ppc->ppc_flags & 0xf))  in ppc_probe()
1755 	return (0);  in ppc_probe()
1758 	if (ppc->res_irq != 0) {  in ppc_probe()
1762 	if (ppc->res_ioport != 0) {  in ppc_probe()
1766 	if (ppc->res_drq != 0) {  in ppc_probe()
1811 	return (0);  in ppc_attach()
1820 	if (ppc->res_irq == 0) {  in ppc_detach()
1826 	if (error != 0)  in ppc_detach()
1829 	if (ppc->res_irq != 0) {  in ppc_detach()
1834 	if (ppc->res_ioport != 0) {  in ppc_detach()
1838 	if (ppc->res_drq != 0) {  in ppc_detach()
1845 	return (0);  in ppc_detach()
1913 	return (0);	/* not significative */  in ppc_io()
1933 	return (0);  in ppc_read_ivar()
1946 		if (val == 0) {  in ppc_write_ivar()
1959 	return (0);  in ppc_write_ivar()
1963  * We allow child devices to allocate an IRQ resource at rid 0 for their
1974 		if (*rid == 0)  in ppc_alloc_resource()
1987 		return (0);  in ppc_release_resource()