Lines Matching +full:0 +full:x720
36 #define OPC_INB_ECHO 0x001 /* */
38 #define OPC_INB_PHYSTART 0x004 /* */
39 #define OPC_INB_PHYSTOP 0x005 /* */
40 #define OPC_INB_SSPINIIOSTART 0x006 /* */
41 #define OPC_INB_SSPINITMSTART 0x007 /* */
42 #define OPC_INB_SSPINIEXTIOSTART 0x008 /* V reserved */
43 #define OPC_INB_DEV_HANDLE_ACCEPT 0x009 /* */
44 #define OPC_INB_SSPTGTIOSTART 0x00a /* */
45 #define OPC_INB_SSPTGTRSPSTART 0x00b /* */
46 #define OPC_INB_SSP_ABORT 0x00f /* */
47 #define OPC_INB_DEREG_DEV_HANDLE 0x010 /* 16 */
48 #define OPC_INB_GET_DEV_HANDLE 0x011 /* 17 */
49 #define OPC_INB_SMP_REQUEST 0x012 /* 18 */
51 #define OPC_INB_SMP_ABORT 0x014 /* 20 */
53 #define OPC_INB_SPC_REG_DEV 0x016 /* 22 V reserved */
54 #define OPC_INB_SATA_HOST_OPSTART 0x017 /* 23 */
55 #define OPC_INB_SATA_ABORT 0x018 /* 24 */
56 #define OPC_INB_LOCAL_PHY_CONTROL 0x019 /* 25 */
57 #define OPC_INB_SPC_GET_DEV_INFO 0x01a /* 26 V reserved */
59 #define OPC_INB_FW_FLASH_UPDATE 0x020 /* 32 */
61 #define OPC_INB_GPIO 0x022 /* 34 */
62 #define OPC_INB_SAS_DIAG_MODE_START_END 0x023 /* 35 */
63 #define OPC_INB_SAS_DIAG_EXECUTE 0x024 /* 36 */
64 #define OPC_INB_SPC_SAS_HW_EVENT_ACK 0x025 /* 37 V reserved */
65 #define OPC_INB_GET_TIME_STAMP 0x026 /* 38 */
66 #define OPC_INB_PORT_CONTROL 0x027 /* 39 */
67 #define OPC_INB_GET_NVMD_DATA 0x028 /* 40 */
68 #define OPC_INB_SET_NVMD_DATA 0x029 /* 41 */
69 #define OPC_INB_SET_DEVICE_STATE 0x02a /* 42 */
70 #define OPC_INB_GET_DEVICE_STATE 0x02b /* 43 */
71 #define OPC_INB_SET_DEV_INFO 0x02c /* 44 */
72 #define OPC_INB_SAS_RE_INITIALIZE 0x02d /* 45 V reserved */
73 #define OPC_INB_SGPIO 0x02e /* 46 */
74 #define OPC_INB_PCIE_DIAG_EXECUTE 0x02f /* 47 */
76 #define OPC_INB_SET_CONTROLLER_CONFIG 0x030 /* 48 */
77 #define OPC_INB_GET_CONTROLLER_CONFIG 0x031 /* 49 */
79 #define OPC_INB_REG_DEV 0x032 /* 50 SPCV */
80 #define OPC_INB_SAS_HW_EVENT_ACK 0x033 /* 51 SPCV */
81 #define OPC_INB_GET_DEV_INFO 0x034 /* 52 SPCV */
82 #define OPC_INB_GET_PHY_PROFILE 0x035 /* 53 SPCV */
83 #define OPC_INB_FLASH_OP_EXT 0x036 /* 54 SPCV */
84 #define OPC_INB_SET_PHY_PROFILE 0x037 /* 55 SPCV */
85 #define OPC_INB_GET_DFE_DATA 0x038 /* 56 SPCV */
86 #define OPC_INB_GET_VHIST_CAP 0x039 /* 57 SPCV12g */
89 #define OPC_INB_KEK_MANAGEMENT 0x100 /* 256 SPCV */
90 #define OPC_INB_DEK_MANAGEMENT 0x101 /* 257 SPCV */
91 #define OPC_INB_SSP_DIF_ENC_OPSTART 0x102 /* 258 SPCV */
92 #define OPC_INB_SATA_DIF_ENC_OPSTART 0x103 /* 259 SPCV */
93 #define OPC_INB_OPR_MGMT 0x104 /* 260 SPCV */
94 #define OPC_INB_ENC_TEST_EXECUTE 0x105 /* 261 SPCV */
95 #define OPC_INB_SET_OPERATOR 0x106 /* 262 SPCV */
96 #define OPC_INB_GET_OPERATOR 0x107 /* 263 SPCV */
97 #define OPC_INB_DIF_ENC_OFFLOAD_CMD 0x110 /* 272 SPCV */
99 #define OPC_INB_FW_PROFILE 0x888 /* 2184 SPCV */
102 #define OPC_OUB_ECHO 0x001 /* 1 */
104 #define OPC_OUB_SPC_HW_EVENT 0x004 /* 4 V reserved Now OPC_OUB_HW_EVENT */
105 #define OPC_OUB_SSP_COMP 0x005 /* 5 */
106 #define OPC_OUB_SMP_COMP 0x006 /* 6 */
107 #define OPC_OUB_LOCAL_PHY_CNTRL 0x007 /* 7 */
109 #define OPC_OUB_SPC_DEV_REGIST 0x00a /* 10 V reserved Now OPC_OUB_DEV_REGIST */
110 #define OPC_OUB_DEREG_DEV 0x00b /* 11 */
111 #define OPC_OUB_GET_DEV_HANDLE 0x00c /* 12 */
112 #define OPC_OUB_SATA_COMP 0x00d /* 13 */
113 #define OPC_OUB_SATA_EVENT 0x00e /* 14 */
114 #define OPC_OUB_SSP_EVENT 0x00f /* 15 */
116 #define OPC_OUB_SPC_DEV_HANDLE_ARRIV 0x010 /* 16 V reserved Now OPC_OUB_DEV_HANDLE_ARRI…
118 #define OPC_OUB_SSP_RECV_EVENT 0x012 /* 18 */
119 #define OPC_OUB_SPC_DEV_INFO 0x013 /* 19 V reserved Now OPC_OUB_DEV_INFO*/
120 #define OPC_OUB_FW_FLASH_UPDATE 0x014 /* 20 */
122 #define OPC_OUB_GPIO_RESPONSE 0x016 /* 22 */
123 #define OPC_OUB_GPIO_EVENT 0x017 /* 23 */
124 #define OPC_OUB_GENERAL_EVENT 0x018 /* 24 */
126 #define OPC_OUB_SSP_ABORT_RSP 0x01a /* 26 */
127 #define OPC_OUB_SATA_ABORT_RSP 0x01b /* 27 */
128 #define OPC_OUB_SAS_DIAG_MODE_START_END 0x01c /* 28 */
129 #define OPC_OUB_SAS_DIAG_EXECUTE 0x01d /* 29 */
130 #define OPC_OUB_GET_TIME_STAMP 0x01e /* 30 */
131 #define OPC_OUB_SPC_SAS_HW_EVENT_ACK 0x01f /* 31 V reserved Now OPC_OUB_SAS_HW_EVENT_AC…
132 #define OPC_OUB_PORT_CONTROL 0x020 /* 32 */
133 #define OPC_OUB_SKIP_ENTRY 0x021 /* 33 */
134 #define OPC_OUB_SMP_ABORT_RSP 0x022 /* 34 */
135 #define OPC_OUB_GET_NVMD_DATA 0x023 /* 35 */
136 #define OPC_OUB_SET_NVMD_DATA 0x024 /* 36 */
137 #define OPC_OUB_DEVICE_HANDLE_REMOVAL 0x025 /* 37 */
138 #define OPC_OUB_SET_DEVICE_STATE 0x026 /* 38 */
139 #define OPC_OUB_GET_DEVICE_STATE 0x027 /* 39 */
140 #define OPC_OUB_SET_DEV_INFO 0x028 /* 40 */
141 #define OPC_OUB_SAS_RE_INITIALIZE 0x029 /* 41 V reserved not replaced */
143 #define OPC_OUB_HW_EVENT 0x700 /* 1792 SPCV Was OPC_OUB_SPC_HW_EVENT*/
144 #define OPC_OUB_DEV_HANDLE_ARRIV 0x720 /* 1824 SPCV Was OPC_OUB_SPC_DEV_HANDLE_ARRI…
146 #define OPC_OUB_PHY_START_RESPONSE 0x804 /* 2052 SPCV */
147 #define OPC_OUB_PHY_STOP_RESPONSE 0x805 /* 2053 SPCV */
148 #define OPC_OUB_SGPIO_RESPONSE 0x82E /* 2094 SPCV */
149 #define OPC_OUB_PCIE_DIAG_EXECUTE 0x82F /* 2095 SPCV */
151 #define OPC_OUB_SET_CONTROLLER_CONFIG 0x830 /* 2096 SPCV */
152 #define OPC_OUB_GET_CONTROLLER_CONFIG 0x831 /* 2097 SPCV */
153 #define OPC_OUB_DEV_REGIST 0x832 /* 2098 SPCV */
154 #define OPC_OUB_SAS_HW_EVENT_ACK 0x833 /* 2099 SPCV */
155 #define OPC_OUB_DEV_INFO 0x834 /* 2100 SPCV */
156 #define OPC_OUB_GET_PHY_PROFILE_RSP 0x835 /* 2101 SPCV */
157 #define OPC_OUB_FLASH_OP_EXT_RSP 0x836 /* 2102 SPCV */
158 #define OPC_OUB_SET_PHY_PROFILE_RSP 0x837 /* 2103 SPCV */
159 #define OPC_OUB_GET_DFE_DATA_RSP 0x838 /* 2104 SPCV */
160 #define OPC_OUB_GET_VIST_CAP_RSP 0x839 /* Can be 2104 for SPCV12g */
162 #define OPC_OUB_FW_PROFILE 0x888 /* 2184 */
164 #define OPC_OUB_KEK_MANAGEMENT 0x900 /* 2304 SPCV */
165 #define OPC_OUB_DEK_MANAGEMENT 0x901 /* 2305 SPCV */
166 #define OPC_OUB_COMBINED_SSP_COMP 0x902 /* 2306 SPCV */
167 #define OPC_OUB_COMBINED_SATA_COMP 0x903 /* 2307 SPCV */
168 #define OPC_OUB_OPR_MGMT 0x904 /* 2308 SPCV */
169 #define OPC_OUB_ENC_TEST_EXECUTE 0x905 /* 2309 SPCV */
170 #define OPC_OUB_SET_OPERATOR 0x906 /* 2310 SPCV */
171 #define OPC_OUB_GET_OPERATOR 0x907 /* 2311 SPCV */
172 #define OPC_OUB_DIF_ENC_OFFLOAD_RSP 0x910 /* 2320 SPCV */
175 #define KEK_MGMT_SUBOP_INVALIDATE 0x1
176 #define KEK_MGMT_SUBOP_UPDATE 0x2
177 #define KEK_MGMT_SUBOP_KEYCARDINVALIDATE 0x3
178 #define KEK_MGMT_SUBOP_KEYCARDUPDATE 0x4
180 #define DEK_MGMT_SUBOP_INVALIDATE 0x1
181 #define DEK_MGMT_SUBOP_UPDATE 0x2
210 #define SPINHOLD_DISABLE (0x00 << 14)
211 #define SPINHOLD_ENABLE (0x01 << 14)
212 #define LINKMODE_SAS (0x01 << 12)
213 #define LINKMODE_DSATA (0x02 << 12)
214 #define LINKMODE_AUTO (0x03 << 12)
215 #define LINKRATE_15 (0x01 << 8)
216 #define LINKRATE_30 (0x02 << 8)
217 #define LINKRATE_60 (0x04 << 8)
218 #define LINKRATE_12 (0x08 << 8)
298 bit32 udt; /* 16 0x10 */
302 bit32 encryptFlagsLo; /* 20 0x14 */
306 bit32 tweakVal_W0; /* 24 0x18 */
310 bit32 AddrLow0; /* 28 0x1C */
379 /* Bits [0] - IR */
392 /* Bits [0] - IR */
568 #define FWFLASH_IOMB_RESERVED_LEN 0x07
582 #define FWPROFILE_IOMB_RESERVED_LEN 0x07
603 #define GPIO_GW_BIT 0x1
604 #define GPIO_GR_BIT 0x2
605 #define GPIO_GS_BIT 0x4
606 #define GPIO_GE_BIT 0x8
783 #define TWI_DEVICE 0x0
784 #define C_SEEPROM 0x1
785 #define VPD_FLASH 0x4
786 #define AAP1_RDUMP 0x5
787 #define IOP_RDUMP 0x6
788 #define EXPAN_ROM 0x7
790 #define DIRECT_MODE 0x0
791 #define INDIRECT_MODE 0x1
793 #define IRMode 0x80000000
794 #define IPMode 0x80000000
795 #define NVMD_TYPE 0x0000000F
796 #define NVMD_STAT 0x0000FFFF
797 #define NVMD_LEN 0xFF000000
799 #define TWI_DEVICE 0x0
800 #define SEEPROM 0x1
814 #define DS_OPERATIONAL 0x01
815 #define DS_IN_RECOVERY 0x03
816 #define DS_IN_ERROR 0x04
817 #define DS_NON_OPERATIONAL 0x07
832 * use to describe MPI OPC_INB_SET_DEV_INFO (0x02c) Command (64 bytes)
843 #define SET_DEV_INFO_V_DW3_MASK 0x0000003F
844 #define SET_DEV_INFO_V_DW4_MASK 0xFF07FFFF
845 #define SET_DEV_INFO_SPC_DW3_MASK 0x7
846 #define SET_DEV_INFO_SPC_DW4_MASK 0x003FFFF
851 #define SET_DEV_INFO_V_DW3_SI_SHIFT 0
856 #define SET_DEV_INFO_V_DW4_ITNEXUS_SHIFT 0
971 #define PHY_ID_BITS 0x000000F0
972 #define LINK_RATE_MASK 0xF0000000
973 #define STATUS_BITS 0x0F000000
974 #define HW_EVENT_BITS 0x00FFFF00
995 #define PHY_ID_V_BITS 0x00FF0000
996 #define NIPP_V_BITS 0x0000FF00
1044 #define SSP_RESCV_BIT 0x00010000 /* Bits [16] */
1045 #define SSP_RESCV_PAD 0x00060000 /* Bits [18:17] */
1084 #define DEVICE_IDC_BITS 0x00FFFF00
1085 #define DEVICE_ID_BITS 0x00000FFF
1099 #define LOCAL_PHY_OP_BITS 0x0000FF00
1100 #define LOCAL_PHY_PHYID 0x000000FF
1115 #define FAILURE_OUT_OF_RESOURCE 0x01 /* The device registration failed because the SPC …
1116 #define FAILURE_DEVICE_ALREADY_REGISTERED 0x02 /* The device registration failed because the SPC …
1117 #define FAILURE_INVALID_PHY_ID 0x03 /* Only for directly-attached SATA registration. T…
1118 #define FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 /* Only for directly-attached SATA registration. T…
1119 …ne FAILURE_PORT_ID_OUT_OF_RANGE 0x05 /* PORT_ID specified in the REGISTER_DEVICE Command is…
1120 #define FAILURE_PORT_NOT_VALID_STATE 0x06 /* The PORT_ID specified in the REGISTER_DEVICE Co…
1121 #define FAILURE_DEVICE_TYPE_NOT_VALID 0x07 /* The device type, specified in the �S field in t…
1123 #define MPI_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020 /* The device registration failed because the SP…
1124 #define MPI_ERR_DEVICE_ALREADY_REGISTERED 0x1021 /* The device registration failed because the SP…
1125 #define MPI_ERR_DEVICE_TYPE_NOT_VALID 0x1022 /* The device type, specified in the �S field in…
1126 #define MPI_ERR_PORT_INVALID_PORT_ID 0x1041 /* specified in the REGISTER_DEVICE_HANDLE Comma…
1127 #define MPI_ERR_PORT_STATE_NOT_VALID 0x1042 /* The PORT_ID specified in the REGISTER_DEVICE_…
1128 #define MPI_ERR_PORT_STATE_NOT_IN_USE 0x1043
1129 #define MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044
1130 #define MPI_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045
1131 #define MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047 /*MPI_ERR_DEVICE_ACCEPT_PENDING*/
1134 #define MPI_ERR_PHY_ID_INVALID 0x1061 /* Only for directly-attached SATA registration.…
1135 #define MPI_ERR_PHY_ID_ALREADY_REGISTERED 0x1062 /* Only for directly-attached SATA registration.…
1190 #define SSPTAG_BITS 0x0000FFFF
1208 #define SMPTO_BITS 0xFFFF
1209 #define NEXUSTO_BITS 0xFFFF
1210 #define FIRST_BURST 0xFFFF
1211 #define FLAG_BITS 0x3
1212 #define LINK_RATE_BITS 0xFF
1213 #define DEV_TYPE_BITS 0x30000000
1231 #define SMPTO_VBITS 0xFFFF
1232 #define NEXUSTO_VBITS 0xFFFF
1233 #define FIRST_BURST_MCN 0xF
1234 #define FLAG_VBITS 0x3
1235 #define LINK_RATE_VBITS 0xFF
1236 #define DEV_TYPE_VBITS 0x10000000
1420 #define OPCODE_BITS 0x00000fff
1426 #define GEN_EVENT_IOMB_V_BIT_NOT_SET 0x01 /* INBOUND_ Inbound IOMB is received with the…
1427 #define GEN_EVENT_INBOUND_IOMB_OPC_NOT_SUPPORTED 0x02 /* Inbound IOMB is received with an unsupport…
1428 #define GEN_EVENT_IOMB_INVALID_OBID 0x03 /* INBOUND Inbound IOMB is received with an i…
1429 #define GEN_EVENT_DS_IN_NON_OPERATIONAL 0x39 /* DEVICE_HANDLE_ACCEPT command failed due to…
1430 #define GEN_EVENT_DS_IN_RECOVERY 0x3A /* DEVICE_HANDLE_ACCEPT command failed due to…
1431 #define GEN_EVENT_DS_INVALID 0x49 /* DEVICE_HANDLE_ACCEPT command failed due to…
1433 #define GEN_EVENT_IO_XFER_READ_COMPL_ERR 0x50 /* Indicates the PCIe Read Request to fetch o…
1437 … Dword 2 bits[15:0] contains the inbound queue number.
1456 #define SSPIUL_BITS 0x0000FFFF
1457 #define INITTAG_BITS 0x0000FFFF
1458 #define FRAME_TYPE 0x000000FF
1459 #define TLR_BITS 0x00000300
1477 #define Conrate_V_MASK 0x0000F000
1479 #define Conrate_SPC_MASK 0x0000F000
1482 #define Protocol_SPC_MASK 0x00000700
1484 #define Protocol_SPC_MASK 0x00000700
1487 #define PortId_V_MASK 0xFF
1488 #define PortId_SPC_MASK 0x0F
1490 #define PROTOCOL_BITS 0x00000700
1493 #define SHIFT_REG_64K_MASK 0xffff0000
1495 #define SPC_GSM_SM_OFFSET 0x400000
1496 #define SPCV_GSM_SM_OFFSET 0x0
1594 #define NDS_BITS 0x0F
1595 #define PDS_BITS 0xF0
1899 * 0x105
1910 * 0x905
1955 * 0x910