Lines Matching +full:0 +full:x00000083
34 /* Message Unit Registers - BAR0(0x10), BAR0(win) */
38 #define MSGU_IBDB_SET 0x20
39 #define MSGU_HOST_INT_STATUS 0x30
40 #define MSGU_HOST_INT_MASK 0x34
41 #define MSGU_IOPIB_INT_STATUS 0x40
42 #define MSGU_IOPIB_INT_MASK 0x44
43 #define MSGU_IBDB_CLEAR 0x70
44 #define MSGU_MSGU_CONTROL 0x74
45 #define MSGU_ODR 0x9C
46 #define MSGU_ODCR 0xA0
47 #define MSGU_SCRATCH_PAD_0 0xB0
48 #define MSGU_SCRATCH_PAD_1 0xB4
49 #define MSGU_SCRATCH_PAD_2 0xB8
50 #define MSGU_SCRATCH_PAD_3 0xBC
52 /* i2o=0 space register offsets - ~MU_I2O_ENABLE */
53 #define MSGU_IBDB_SET 0x04 /* RevA - Write only, RevB - Read/Write */
54 #define MSGU_HOST_INT_STATUS 0x08
55 #define MSGU_HOST_INT_MASK 0x0C
56 #define MSGU_IOPIB_INT_STATUS 0x18
57 #define MSGU_IOPIB_INT_MASK 0x1C
58 #define MSGU_IBDB_CLEAR 0x20 /* RevB - Host not use */
59 #define MSGU_MSGU_CONTROL 0x24
60 #define MSGU_ODR 0x3C /* RevB */
61 #define MSGU_ODCR 0x40 /* RevB */
62 #define MSGU_SCRATCH_PAD_0 0x44
63 #define MSGU_SCRATCH_PAD_1 0x48
64 #define MSGU_SCRATCH_PAD_2 0x4C
65 #define MSGU_SCRATCH_PAD_3 0x50
66 #define MSGU_HOST_SCRATCH_PAD_0 0x54
67 #define MSGU_HOST_SCRATCH_PAD_1 0x58
68 #define MSGU_HOST_SCRATCH_PAD_2 0x5C
69 #define MSGU_HOST_SCRATCH_PAD_3 0x60
70 #define MSGU_HOST_SCRATCH_PAD_4 0x64
71 #define MSGU_HOST_SCRATCH_PAD_5 0x68
72 #define MSGU_HOST_SCRATCH_PAD_6 0x6C
73 #define MSGU_HOST_SCRATCH_PAD_7 0x70
74 #define MSGU_ODMR 0x74 /* RevB */
85 #define V_Inbound_Doorbell_Set_Register 0x00 /* Host R/W Local INT 0x0 MSGU - Inbound D…
86 #define V_Inbound_Doorbell_Set_RegisterU 0x04 /* Host R/W Local INT 0x4 MSGU - Inbound D…
87 #define V_Inbound_Doorbell_Clear_Register 0x08 /* Host No access Local W, R all 0s 0x8 M…
88 #define V_Inbound_Doorbell_Clear_RegisterU 0x0C /* Host No access Local W, R all 0s 0xC M…
89 #define V_Inbound_Doorbell_Mask_Set_Register 0x10 /* Host RO Local R/W 0x10 MSGU - Inbound D…
90 #define V_Inbound_Doorbell_Mask_Set_RegisterU 0x14 /* Host RO Local R/W 0x14 MSGU - Inbound D…
91 #define V_Inbound_Doorbell_Mask_Clear_Register 0x18 /* Host RO Local W, R all 0s 0x18 MSGU - I…
92 #define V_Inbound_Doorbell_Mask_Clear_RegisterU 0x1C /* Host RO Local W, R all 0s 0x1C MSGU - I…
93 #define V_Outbound_Doorbell_Set_Register 0x20 /* Host RO Local R/W 0x20 MSGU - Outbound …
94 #define V_Outbound_Doorbell_Set_RegisterU 0x24 /* Host RO Local R/W 0x24 MSGU - Outbound …
95 #define V_Outbound_Doorbell_Clear_Register 0x28 /* Host W, R all 0s Local RO 0x28 MSGU - …
96 #define V_Outbound_Doorbell_Clear_RegisterU 0x2C /* Host W, R all 0s Local RO 0x2C MSGU - …
97 #define V_Outbound_Doorbell_Mask_Set_Register 0x30 /* Host RW Local RO 0x30 MSGU - Outbound …
98 #define V_Outbound_Doorbell_Mask_Set_RegisterU 0x34 /* Host RW Local RO 0x30 MSGU - Outbound …
99 #define V_Outbound_Doorbell_Mask_Clear_Register 0x38 /* Host W, R all 0s Local RO 0x38 MSGU - O…
100 #define V_Outbound_Doorbell_Mask_Clear_RegisterU 0x3C /* Host W, R all 0s Local RO 0x38 MSGU - O…
101 /* 0x40 Reserved R all 0s */
102 #define V_Scratchpad_0_Register 0x44 /* Host RO Local R/W 0x120 MSGU - Scratchpa…
103 #define V_Scratchpad_1_Register 0x48 /* Host RO Local R/W 0x128 MSGU - Scratchpa…
104 #define V_Scratchpad_2_Register 0x4C /* Host RO Local R/W 0x130 MSGU - Scratchpa…
105 #define V_Scratchpad_3_Register 0x50 /* Host RO Local R/W 0x138 MSGU - Scratchpa…
106 #define V_Host_Scratchpad_0_Register 0x54 /* Host RW Local RO 0x140 MSGU - Scratchpad…
107 #define V_Host_Scratchpad_1_Register 0x58 /* Host RW Local RO 0x148 MSGU - Scratchpad…
108 #define V_Host_Scratchpad_2_Register 0x5C /* Host RW Local RO 0x150 MSGU - Scratchpad…
109 #define V_Host_Scratchpad_3_Register 0x60 /* Host RW Local RO 0x158 MSGU - Scratchpad…
110 #define V_Host_Scratchpad_4_Register 0x64 /* Host RW Local R/W 0x160 MSGU - Scratchpa…
111 #define V_Host_Scratchpad_5_Register 0x68 /* Host RW Local R/W 0x168 MSGU - Scratchpa…
112 #define V_Scratchpad_Rsvd_0_Register 0x6C /* Host RW Local R/W 0x170 MSGU - Scratchpa…
113 #define V_Scratchpad_Rsvd_1_Register 0x70 /* Host RW Local R/W 0x178 MSGU - Scratchpa…
114 /* 0x74 - 0xFF Reserved R all 0s */
115 …_Queue_Consumer_Indices_Base 0x100 /* typical value real offset is read from table to 0x1FF Hos…
116 …Queue_Producer_Indices 0x200 /* typical value real offset is read from table to 0x3FF Hos…
120 PCIBAR0, V_Inbound_Doorbell_Set_Register, 0x00 PCIBAR0, MSGU_IBDB_SET, 0x04
121 PCIBAR0, V_Inbound_Doorbell_Clear_Register, 0x08 NA
122 PCIBAR0, V_Inbound_Doorbell_Mask_Set_Register, 0x10 NA
123 PCIBAR0, V_Inbound_Doorbell_Mask_Clear_Register, 0x18 NA
124 PCIBAR0, V_Outbound_Doorbell_Set_Register, 0x20 PCIBAR0, MSGU_ODR, 0x3C
125 PCIBAR0, V_Outbound_Doorbell_Clear_Register, 0x28 PCIBAR0, MSGU_ODCR, 0x40
126 PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register, 0x30 PCIBAR0, MSGU_ODMR, 0x74
127 PCIBAR0, V_Outbound_Doorbell_Mask_Clear_Register, 0x38 NA
128 PCIBAR0, V_Scratchpad_0_Register, 0x44 PCIBAR0, MSGU_SCRATCH_PAD_0, 0x44
129 PCIBAR0, V_Scratchpad_1_Register, 0x48 PCIBAR0, MSGU_SCRATCH_PAD_1, 0x48
130 PCIBAR0, V_Scratchpad_2_Register, 0x4C PCIBAR0, MSGU_SCRATCH_PAD_2, 0x4C
131 PCIBAR0, V_Scratchpad_3_Register, 0x50 PCIBAR0, MSGU_SCRATCH_PAD_3, 0x50
132 PCIBAR0, V_Host_Scratchpad_0_Register, 0x54 PCIBAR0, MSGU_HOST_SCRATCH_PAD_0, 0x54
133 PCIBAR0, V_Host_Scratchpad_1_Register, 0x58 PCIBAR0, MSGU_HOST_SCRATCH_PAD_1, 0x58
134 PCIBAR0, V_Host_Scratchpad_2_Register, 0x5C PCIBAR0, MSGU_HOST_SCRATCH_PAD_2, 0x5C
135 PCIBAR0, V_Host_Scratchpad_3_Register, 0x60 PCIBAR0, MSGU_HOST_SCRATCH_PAD_3, 0x60
140 #define V_RamEccDbErr 0x00000018
141 #define V_SoftResetRegister 0x1000
142 #define V_MEMBASE_II_ShiftRegister 0x1010
144 #define V_GsmConfigReset 0
145 #define V_GsmReadAddrParityCheck 0x38
146 #define V_GsmWriteAddrParityCheck 0x40
147 #define V_GsmWriteDataParityCheck 0x48
148 #define V_GsmReadAddrParityIndic 0x58
149 #define V_GsmWriteAddrParityIndic 0x60
150 #define V_GsmWriteDataParityIndic 0x68
153 #define SPCv_Reset_Reserved 0xFFFFFF3C
154 #define SPCv_Reset_Read_Mask 0xC0
155 #define SPCv_Reset_Read_NoReset 0x0
156 #define SPCv_Reset_Read_NormalResetOccurred 0x40
157 #define SPCv_Reset_Read_SoftResetHDAOccurred 0x80
158 #define SPCv_Reset_Read_ChipResetOccurred 0xC0
161 #define SPCv_Reset_Write_NormalReset 0x1
162 #define SPCv_Reset_Write_SoftResetHDA 0x2
163 #define SPCv_Reset_Write_ChipReset 0x3
184 [1:0]
193 - BAR2(0x18), BAR1(win) *****/
195 #define SPC_ODAR 0x00335C
196 #define SPC_ICTIMER 0x0033C0
197 #define SPC_ICCONTROL 0x0033C4
199 /* BAR2(0x18), BAR1(win) */
200 #define MSGU_XCBI_IBDB_REG 0x003034 /* PCIE - Message Unit Inbound Doorbell r…
201 #define MSGU_XCBI_OBDB_REG 0x003354 /* PCIE - Message Unit Outbound Doorbell …
202 #define MSGU_XCBI_OBDB_MASK 0x003358 /* PCIE - Message Unit Outbound Doorbell …
203 #define MSGU_XCBI_OBDB_CLEAR 0x00303C /* PCIE - Message Unit Outbound Doorbell …
206 #define SPC_RB6_OFFSET 0x80C0
208 #define RB6_MAGIC_NUMBER_RST 0x1234 /* Magic number of soft reset for RB6 */
223 #define ODMR_MASK_ALL 0xFFFFFFFF /* mask all interrupt vector */
224 #define ODMR_CLEAR_ALL 0 /* clear all interrupt vector */
226 #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all interrupt vector */
229 #define IBDB_IBQ_UNFREEZE 0x08 /* Inbound doorbell bit3 */
230 #define IBDB_IBQ_FREEZE 0x04 /* Inbound doorbell bit2 */
231 #define IBDB_CFG_TABLE_RESET 0x02 /* Inbound doorbell bit1 */
232 #define IBDB_CFG_TABLE_UPDATE 0x01 /* Inbound doorbell bit0 */
234 #define IBDB_MPIIU 0x08 /* Inbound doorbell bit3 - Unfreeze */
235 #define IBDB_MPIIF 0x04 /* Inbound doorbell bit2 - Freeze */
236 #define IBDB_MPICT 0x02 /* Inbound doorbell bit1 - Terminatio…
237 #define IBDB_MPIINI 0x01 /* Inbound doorbell bit0 - Initializa…
240 #define SCRATCH_PAD0_BAR_MASK 0xFC000000 /* bit31-26 - mask bar */
241 #define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF /* bit25-0 - offset mask */
242 #define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF /* if AAP error state */
245 #define SCRATCH_PAD1_POR 0x00 /* power on reset state */
246 #define SCRATCH_PAD1_SFR 0x01 /* soft reset state */
247 #define SCRATCH_PAD1_ERR 0x02 /* error state */
248 #define SCRATCH_PAD1_RDY 0x03 /* ready state */
249 #define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */
250 #define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */
251 …define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1 Mask other bits 31:4, …
252 #define SCRATCH_PAD1_RESERVED 0x000000F0 /* Scratch Pad1 Reserved bit 4 to 7 */
256 #define SCRATCH_PAD1_V_RAAE_MASK 0x00000003 /* 0 1 also ready */
257 #define SCRATCH_PAD1_V_RAAE_ERR 0x00000002 /* 1 */
258 #define SCRATCH_PAD1_V_ILA_MASK 0x0000000C /* 2 3 also ready */
259 #define SCRATCH_PAD1_V_ILA_ERR 0x00000008 /* 3 */
260 #define SCRATCH_PAD1_V_BOOTSTATE_MASK 0x00000070 /* 456 */
261 #define SCRATCH_PAD1_V_BOOTSTATE_SUCESS 0x00000000 /* Load successful */
262 #define SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM 0x00000010 /* HDA Mode SEEPROM Setting */
263 #define SCRATCH_PAD1_V_BOOTSTATE_HDA_BOOTSTRAP 0x00000020 /* HDA Mode BootStrap Setting */
264 #define SCRATCH_PAD1_V_BOOTSTATE_HDA_SOFTRESET 0x00000030 /* HDA Mode Soft Reset */
265 #define SCRATCH_PAD1_V_BOOTSTATE_CRIT_ERROR 0x00000040 /* HDA Mode due to critical error */
266 #define SCRATCH_PAD1_V_BOOTSTATE_R1 0x00000050 /* Reserved */
267 #define SCRATCH_PAD1_V_BOOTSTATE_R2 0x00000060 /* Reserved */
268 #define SCRATCH_PAD1_V_BOOTSTATE_FATAL 0x00000070 /* Fatal Error Boot process halted */
271 #define SCRATCH_PAD1_V_ILA_IMAGE 0x00000080 /* 7 */
272 #define SCRATCH_PAD1_V_FW_IMAGE 0x00000100 /* 8 */
273 #define SCRATCH_PAD1_V_BIT9_RESERVED 0x00000200 /* 9 */
274 #define SCRATCH_PAD1_V_IOP0_MASK 0x00000C00 /* 10 11 also ready */
275 #define SCRATCH_PAD1_V_IOP0_ERR 0x00000800 /* 11 */
276 #define SCRATCH_PAD1_V_IOP1_MASK 0x00003000 /* 12 13 also ready */
277 #define SCRATCH_PAD1_V_IOP1_ERR 0x00002000 /* 13 */
278 #define SCRATCH_PAD1_V_RESERVED 0xFFFFC000 /* 14-31 */
283 …TATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_ILA_MASK ) == SCRATCH_PAD1_V_ILA_MASK) ? 0: \
284 …cratchPad1) & SCRATCH_PAD1_V_ILA_MASK ) == SCRATCH_PAD1_V_ILA_ERR ) ? SCRATCH_PAD1_V_ILA_ERR : 0 )
286 …ATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_RAAE_MASK ) == SCRATCH_PAD1_V_RAAE_MASK) ? 0: \
287 …tchPad1) & SCRATCH_PAD1_V_RAAE_MASK ) == SCRATCH_PAD1_V_RAAE_ERR) ? SCRATCH_PAD1_V_RAAE_ERR : 0 )
289 …ATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_IOP0_MASK ) == SCRATCH_PAD1_V_IOP0_MASK) ? 0: \
290 …tchPad1) & SCRATCH_PAD1_V_IOP0_MASK ) == SCRATCH_PAD1_V_IOP0_ERR) ? SCRATCH_PAD1_V_IOP0_ERR : 0 )
292 …ATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_IOP1_MASK ) == SCRATCH_PAD1_V_IOP1_MASK) ? 0: \
293 …tchPad1) & SCRATCH_PAD1_V_IOP1_MASK ) == SCRATCH_PAD1_V_IOP1_ERR) ? SCRATCH_PAD1_V_IOP1_ERR : 0 )
300 #define SCRATCH_PAD1_V_BOOTLDR_ERROR 0x00000070 /* Scratch Pad1 (6 5 4) */
304 #define SCRATCH_PAD1_BDMA_ERR 0x80000000 /* bit31 */
305 #define SCRATCH_PAD1_GSM_ERR 0x40000000 /* bit30 */
306 #define SCRATCH_PAD1_MBIC1_ERR 0x20000000 /* bit29 */
307 #define SCRATCH_PAD1_MBIC1_SET0_ERR 0x10000000 /* bit28 */
308 #define SCRATCH_PAD1_MBIC1_SET1_ERR 0x08000000 /* bit27 */
309 #define SCRATCH_PAD1_PMIC1_ERR 0x04000000 /* bit26 */
310 #define SCRATCH_PAD1_PMIC2_ERR 0x02000000 /* bit25 */
311 #define SCRATCH_PAD1_PMIC_EVENT_ERR 0x01000000 /* bit24 */
312 #define SCRATCH_PAD1_OSSP_ERR 0x00800000 /* bit23 */
313 #define SCRATCH_PAD1_SSPA_ERR 0x00400000 /* bit22 */
314 #define SCRATCH_PAD1_SSPL_ERR 0x00200000 /* bit21 */
315 #define SCRATCH_PAD1_HSST_ERR 0x00100000 /* bit20 */
316 #define SCRATCH_PAD1_PCS_ERR 0x00080000 /* bit19 */
317 #define SCRATCH_PAD1_FW_INIT_ERR 0x00008000 /* bit15 */
318 #define SCRATCH_PAD1_FW_ASRT_ERR 0x00004000 /* bit14 */
319 #define SCRATCH_PAD1_FW_WDG_ERR 0x00002000 /* bit13 */
320 #define SCRATCH_PAD1_AAP_ERROR_STATE 0x00000002 /* bit1 */
321 #define SCRATCH_PAD1_AAP_READY 0x00000003 /* bit1 & bit0 */
325 #define SCRATCH_PAD2_POR 0x00 /* power on state */
326 #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
327 #define SCRATCH_PAD2_ERR 0x02 /* error state */
328 #define SCRATCH_PAD2_RDY 0x03 /* ready state */
329 #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset rdy flag */
330 #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
331 …fine SCRATCH_PAD2_STATE_MASK 0xFFFFFFF0 /* ScratchPad 2 Mask for other bits 31:…
332 #define SCRATCH_PAD2_RESERVED 0x000000F0 /* Scratch Pad1 Reserved bit 4 to 7 */
335 #define SCRATCH_PAD2_BDMA_ERR 0x80000000 /* bit31 */
336 #define SCRATCH_PAD2_GSM_ERR 0x40000000 /* bit30 */
337 #define SCRATCH_PAD2_MBIC3_ERR 0x20000000 /* bit29 */
338 #define SCRATCH_PAD2_MBIC3_SET0_ERR 0x10000000 /* bit28 */
339 #define SCRATCH_PAD2_MBIC3_SET1_ERR 0x08000000 /* bit27 */
340 #define SCRATCH_PAD2_PMIC1_ERR 0x04000000 /* bit26 */
341 #define SCRATCH_PAD2_PMIC2_ERR 0x02000000 /* bit25 */
342 #define SCRATCH_PAD2_PMIC_EVENT_ERR 0x01000000 /* bit24 */
343 #define SCRATCH_PAD2_OSSP_ERR 0x00800000 /* bit23 */
344 #define SCRATCH_PAD2_SSPA_ERR 0x00400000 /* bit22 */
345 #define SCRATCH_PAD2_SSPL_ERR 0x00200000 /* bit21 */
346 #define SCRATCH_PAD2_HSST_ERR 0x00100000 /* bit20 */
347 #define SCRATCH_PAD2_PCS_ERR 0x00080000 /* bit19 */
349 #define SCRATCH_PAD2_FW_BOOT_ROM_ERROR 0x00010000 /* bit16 */
350 #define SCRATCH_PAD2_FW_ILA_ERR 0x00008000 /* bit15 */
351 #define SCRATCH_PAD2_FW_FLM_ERR 0x00004000 /* bit14 */
352 #define SCRATCH_PAD2_FW_FW_ASRT_ERR 0x00002000 /* bit13 */
353 #define SCRATCH_PAD2_FW_HW_WDG_ERR 0x00001000 /* bit12 */
354 #define SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR 0x00000800 /* bit11 */
355 #define SCRATCH_PAD2_FW_UNDTMN_ERR 0x00000400 /* bit10 */
356 #define SCRATCH_PAD2_FW_HW_FATAL_ERR 0x00000200 /* bit9 */
357 #define SCRATCH_PAD2_FW_HW_NON_FATAL_ERR 0x00000100 /* bit8 */
358 #define SCRATCH_PAD2_FW_HW_MASK 0x000000FF
359 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR 0x00
360 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR 0x01
361 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR 0x02
362 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR 0x03
363 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR 0x04
364 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR 0x05
365 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR 0x06
366 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR 0x08
367 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR 0x0C
368 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR 0x0E
369 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR 0x0F
370 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR 0x10
371 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR 0x13
372 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR 0x14
373 #define SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED 0xFF
377 #define SCRATCH_PAD_ERROR_MASK 0xFFFFFF00 /* Error mask bits 31:8 */
378 #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits 1:0 */
380 #define SPCV_RAAE_STATE_MASK 0x3
383 #define SPCV_ERROR_VALUE 0x2
386 #define SCRATCH_PAD3_FW_IMAGE_MASK 0x0000000F /* SPC 8x6G boots from Image */
387 #define SCRATCH_PAD3_FW_IMAGE_FLAG_VALID 0x00000008 /* Image flag is valid */
388 #define SCRATCH_PAD3_FW_IMAGE_B_VALID 0x00000004 /* Image B is valid */
389 #define SCRATCH_PAD3_FW_IMAGE_A_VALID 0x00000002 /* Image A is valid */
390 #define SCRATCH_PAD3_FW_IMAGE_B_ACTIVE 0x00000001 /* Image B is active */
393 #define SCRATCH_PAD3_V_ 0x00000001 /* Image B is valid */
395 #define SCRATCH_PAD3_V_ENC_DISABLED 0x00000000 /* */
396 #define SCRATCH_PAD3_V_ENC_DIS_ERR 0x00000001 /* */
397 #define SCRATCH_PAD3_V_ENC_ENA_ERR 0x00000002 /* */
398 #define SCRATCH_PAD3_V_ENC_READY 0x00000003 /* */
401 #define SCRATCH_PAD3_V_AUT 0x00000008 /* AUT Operator authentication*/
402 #define SCRATCH_PAD3_V_ARF 0x00000004 /* ARF factory mode. */
407 #define SCRATCH_PAD3_V_SMF_ENABLED 0 /* */
408 #define SCRATCH_PAD3_V_SM_MASK 0x000000F0 /* */
409 #define SCRATCH_PAD3_V_ERR_CODE 0x00FF0000 /* */
412 /* Dynamic map through Bar4 - 0x00700000 */
413 #define GSM_CONFIG_RESET 0x00000000
414 #define RAM_ECC_DB_ERR 0x00000018
415 #define GSM_READ_ADDR_PARITY_INDIC 0x00000058
416 #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
417 #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
418 #define GSM_READ_ADDR_PARITY_CHECK 0x00000038
419 #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
420 #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
423 #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd /* Signature for Soft Reset */
424 #define SPC_HDASOFT_RESET_SIGNATURE 0xa5aa27d7 /* Signature for HDA Soft Reset witho…
428 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
429 #define SPC_REG_RESET 0x000000 /* reset register */
430 #define SPC_REG_DEVICE_LCLK 0x000058 /* Device LCLK generation register */
435 /* NMI register - BAR4(0x20), BAR2(win) 0x060000/0x070000 */
436 //#define MBIC_RAW_NMI_STAT_VPE0_IOP 0x0004C8 not used anymore
437 //#define MBIC_RAW_NMI_STAT_VPE0_AAP1 0x0104C8 not used anymore
438 #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
439 #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
441 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
442 #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
443 #define PCIE_EVENT_INTERRUPT 0x003044
444 #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
445 #define PCIE_ERROR_INTERRUPT 0x00304C
447 /* PCIe Message Unit Configuration Registers offset - BAR2(0x18), BAR1(win) 0x010000 */
448 #define SPC_REG_MSGU_CONFIG 0x003018
449 #define PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE 0x00000010
452 #define SPC_REG_RESET_OSSP 0x00000001
453 #define SPC_REG_RESET_RAAE 0x00000002
454 #define SPC_REG_RESET_PCS_SPBC 0x00000004
455 #define SPC_REG_RESET_PCS_IOP_SS 0x00000008
456 #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
457 #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
458 #define SPC_REG_RESET_PCS_LM 0x00000040
459 #define SPC_REG_RESET_PCS 0x00000080
460 #define SPC_REG_RESET_GSM 0x00000100
461 #define SPC_REG_RESET_DDR2 0x00010000
462 #define SPC_REG_RESET_BDMA_CORE 0x00020000
463 #define SPC_REG_RESET_BDMA_SXCBI 0x00040000
464 #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
465 #define SPC_REG_RESET_PCIE_PWR 0x00100000
466 #define SPC_REG_RESET_PCIE_SFT 0x00200000
467 #define SPC_REG_RESET_PCS_SXCBI 0x00400000
468 #define SPC_REG_RESET_LMS_SXCBI 0x00800000
469 #define SPC_REG_RESET_PMIC_SXCBI 0x01000000
470 #define SPC_REG_RESET_PMIC_CORE 0x02000000
471 #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
472 #define SPC_REG_RESET_DEVICE 0x80000000
475 #define SPC_REG_DEVICE_REV 0x000024
476 #define SPC_REG_DEVICE_REV_MASK 0x0000000F
480 #define SPC_REG_TOP_DEVICE_ID 0x20
481 #define SPC_TOP_DEVICE_ID 0x8001
483 #define SPC_REG_TOP_BOOT_STRAP 0x8
484 #define SPC_TOP_BOOT_STRAP 0x02C0A682
488 #define COUNT_OFFSET 0x4000
489 #define LCLK_CLEAR 0x2
490 #define LCLK 0x1
491 #define CNTL_OFFSET 0x100
492 #define L0_LCLK_CLEAR 0x2
493 #define L0_LCLK 0x1
494 #define DEVICE_LCLK_CLEAR 0x40
497 /* PHY Error Count Registers - BAR4(0x20), BAR2(win) (need dynamic mapping) */
498 #define SPC_SSPL_COUNTER_CNTL 0x001030
499 #define SPC_INVALID_DW_COUNT 0x001034
500 #define SPC_RUN_DISP_ERROR_COUNT 0x001038
501 #define SPC_CODE_VIOLATION_COUNT 0x00103C
502 #define SPC_LOSS_DW_SYNC_COUNT 0x001040
503 #define SPC_PHY_RESET_PROBLEM_COUNT 0x001044
513 /* PHY Error Count Control Registers - BAR2(0x18), BAR1(win) */
514 #define SPC_L0_ERR_CNT_CNTL 0x0041B0
518 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
519 #define SPC_IBW_AXI_TRANSLATION_LOW 0x003258
523 #define HDA_CMD_OFFSET256K 0x0003FFC0
524 #define HDA_RSP_OFFSET256K 0x0003FFE0
527 #define HDA_CMD_OFFSET512K 0x0007FFC0
528 #define HDA_RSP_OFFSET512K 0x0007FFE0
531 #define HDA_CMD_OFFSET768K 0x000BFFC0
532 #define HDA_RSP_OFFSET768K 0x000BFFE0
535 #define HDA_CMD_OFFSET1MB 0x0000FEC0
536 #define HDA_RSP_OFFSET1MB 0x0000FEE0
542 /* Offset Byte 3 Byte 2 Byte 1 Byte 0 */
543 bit32 cmdparm_0; /* 0 Command Parameter 0 */
555 /* Offset Byte 3 Byte 2 Byte 1 Byte 0 */
556 bit32 cmdparm_0; /* 0 Command Parameter 0 */
566 #define SPC_V_HDA_COMMAND_OFFSET 0x000042c0
567 #define SPC_V_HDA_RESPONSE_OFFSET 0x000042e0
570 #define HDA_C_PA_OFFSET 0x1F
571 #define HDA_SEQ_ID_OFFSET 0x1E
572 #define HDA_PAR_LEN_OFFSET 0x04
573 #define HDA_CMD_CODE_OFFSET 0x1C
574 #define HDA_RSP_CODE_OFFSET 0x1C
578 #define SPC_V_HDAC_PA 0xCB
579 #define SPC_V_HDAC_BUF_INFO 0x0001
580 #define SPC_V_HDAC_EXEC 0x0002
581 #define SPC_V_HDAC_RESET 0x0003
582 #define SPC_V_HDAC_DMA 0x0004
584 #define SPC_V_HDAC_PA_MASK 0xFF000000
585 #define SPC_V_HDAC_SEQID_MASK 0x00FF0000
586 #define SPC_V_HDAC_CMDCODE_MASK 0x0000FFFF
589 #define SPC_V_HDAR_PA 0xDB
590 #define SPC_V_HDAR_BUF_INFO 0x8001
591 #define SPC_V_HDAR_IDLE 0x8002
592 #define SPC_V_HDAR_BAD_IMG 0x8003
593 #define SPC_V_HDAR_BAD_CMD 0x8004
594 #define SPC_V_HDAR_INTL_ERR 0x8005
595 #define SPC_V_HDAR_EXEC 0x8006
597 #define SPC_V_HDAR_PA_MASK 0xFF000000
598 #define SPC_V_HDAR_SEQID_MASK 0x00FF0000
599 #define SPC_V_HDAR_RSPCODE_MASK 0x0000FFFF
601 #define ILAHDA_RAAE_IMG_GET 0x11
602 #define ILAHDA_IOP_IMG_GET 0x10
604 #define ILAHDAC_RAAE_IMG_DONE 0x81
607 #define HDA_AES_DIF_FUNC 0xFEDFAE1F
611 #define PMIC_MU_CFG_1_BITMSK_MU_IO_ENABLE 0x00000001
612 #define PMIC_MU_CFG_1_BITMSK_MU_IO_WIR 0x0000000C
613 #define PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE 0x00000010
614 #define PMIC_MU_CFG_1_BITMSK_MU_MEM_OFFSET 0xFFFFFC00
617 #define MU_MEM_OFFSET 0x0
618 #define MSGU_MU_IO_WIR 0x8 /* Window 0 */
620 #define BOOTTLOADERHDA_IDLE 0x8002
621 #define HDAR_BAD_IMG 0x8003
622 #define HDAR_BAD_CMD 0x8004
623 #define HDAR_EXEC 0x8006
625 #define CEILING(X, rem) ((((bit32)X % rem) > 0) ? (bit32)(X/rem+1) : (bit32)(X/rem))
627 #define GSMSM_AXI_LOWERADDR 0x00400000
628 #define SHIFT_MASK 0xFFFF0000
629 #define OFFSET_MASK 0x0000FFFF
630 #define SIZE_64KB 0x00010000
631 #define ILA_ISTR_ADDROFFSETHDA 0x0007E000
632 #define HDA_STATUS_BITS 0x0000FFFF
634 /* Scratchpad Reg: bit[31]: 1-CMDFlag 0-RSPFlag; bit[30,24]:CMD/RSP; bit[23,0]:Offset/Size - Shared…
635 /* ILA: Mandatory response / state codes in MSGU Scratchpad 0 */
636 #define ILAHDA_IOP_IMG_GET 0x10
637 #define ILAHDA_AAP1_IMG_GET 0x11
638 #define ILAHDA_AAP2_IMG_GET 0x12
639 #define ILAHDA_EXITGOOD 0x1F
642 #define ILAHDAC_IOP_IMG_DONE 0x00000080
643 #define ILAHDAC_AAP1_IMG_DONE 0x00000081
644 #define ILAHDAC_AAP2_IMG_DONE 0x00000082
645 #define ILAHDAC_ISTR_IMG_DONE 0x00000083
646 #define ILAHDAC_GOTOHDA 0x000000ff
652 #define RB6_ACCESS_REG 0x6A0000
653 #define HDAC_EXEC_CMD 0x0002
654 #define HDA_C_PA 0xcb
655 #define HDA_SEQ_ID_BITS 0x00ff0000
656 #define HDA_GSM_OFFSET_BITS 0x00FFFFFF
657 #define MBIC_AAP1_ADDR_BASE 0x060000
658 #define MBIC_GSM_SM_BASE 0x04F0000
659 #define MBIC_IOP_ADDR_BASE 0x070000
660 #define GSM_ADDR_BASE 0x0700000
661 #define SPC_TOP_LEVEL_ADDR_BASE 0x000000
662 #define GSM_CONFIG_RESET_VALUE 0x00003b00
663 #define GPIO_ADDR_BASE 0x00090000
664 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
668 #define SA_FATAL_ERROR_SP1_AAP1_ERR_MASK 0x3
669 #define SA_FATAL_ERROR_SP2_IOP_ERR_MASK 0x3
670 #define SA_FATAL_ERROR_FATAL_ERROR 0x2
687 GEN_MSGU_IBDB_SET=0,