Lines Matching +full:0 +full:x0007ffff
43 #define REGISTER_DUMP_BUFF_SIZE 0x4000 /**< Maximum Fatal Error …
55 #define MPI_QUEUE_NORMAL 0
65 #define DIR_NODATA 0x000
66 #define DIR_READ 0x100
67 #define DIR_WRITE 0x200
70 #define TLR_MASK 0x00000003
74 #define PORTID_MASK 0x0000000F
75 #define PORTID_V_MASK 0x000000FF
76 #define PHYID_MASK 0x0000000F
77 #define PHYID_V_MASK 0x000000FF
78 #define PORT_STATE_MASK 0x0000000F
79 #define PHY_IN_PORT_MASK 0x000000F0
85 #define LLROOT_MEM_INDEX 0 /**< the index of root memory */
115 #define MPI_EVENTLOG_INDEX 0
126 #define LL_DEVICE_LOCK 0
158 #define PHY_STOPPED 0x00000000 /**< flag indicates phy s…
159 #define PHY_UP 0x00000001 /**< flag indicates phy u…
160 #define PHY_DOWN 0x00000002 /**< flag indicates phy d…
163 #define PORT_NORMAL 0x0000
164 #define PORT_INVALIDATING 0x0002
167 #define CHIP_NORMAL 0x0000
168 #define CHIP_SHUTDOWN 0x0001
169 #define CHIP_RESETTING 0x0002
170 #define CHIP_RESET_FW 0x0004
171 #define CHIP_FATAL_ERROR 0x0008
174 #define SAS_SATA_UNKNOWN_DEVICE 0xFF /**< SAS SATA unknown device type */
176 #define STP_DEVICE 0x00 /**< SATA device behind an expander */
177 #define SSP_SMP_DEVICE 0x01 /**< SSP or SMP device type */
178 #define DIRECT_SATA_DEVICE 0x02 /**< SATA direct device type */
181 #define SATA_FIS_MASK 0x00000001
184 #define MARK_OFF 0xFFFFFFFF
185 #define PORT_MARK_OFF 0xFFFFFFFF
186 #define NO_FATAL_ERROR_VECTOR 0xFFFFFFFF
188 #define SATA_PROTOCOL_RSRT_ASSERT 0x01
189 #define SATA_PROTOCOL_RSRT_DEASSERT 0x02
190 #define SATA_NON_DATA_PROTOCOL 0x0d
191 #define SATA_PIO_READ_PROTOCOL 0x0e
192 #define SATA_DMA_READ_PROTOCOL 0x0f
193 #define SATA_FPDMA_READ_PROTOCOL 0x10
194 #define SATA_PIO_WRITE_PROTOCOL 0x11
195 #define SATA_DMA_WRITE_PROTOCOL 0x12
196 #define SATA_FPDMA_WRITE_PROTOCOL 0x13
197 #define SATA_DEVICE_RESET_PROTOCOL 0x14
200 #define SHIFT0 0
234 #define ABORT_MASK 0x3
235 #define ABORT_SINGLE 0x0
236 #define ABORT_SCOPE 0x3 /* bits 0-1*/
237 #define ABORT_ALL 0x1
238 #define ABORT_TSDK_QUARANTINE 0x4
239 #define ABORT_QUARANTINE_SPC 0x4
240 #define ABORT_QUARANTINE_SPCV 0x8
243 #define REG_DUMP_NUM0 0x0
244 #define REG_DUMP_NUM1 0x1
245 #define REG_DUMP_NONFLASH 0x0
246 #define REG_DUMP_FLASH 0x1
249 #define MSIX_TABLE_OFFSET 0x2000
250 #define MSIX_TABLE_ELEMENT_SIZE 0x10
251 #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
253 #define MSIX_INTERRUPT_DISABLE 0x1
254 #define MSIX_INTERRUPT_ENABLE 0x0
258 #define NUM_MEM_CHUNKS(Q, rem) ((((bit32)Q % rem) > 0) ? (bit32)(Q/rem+1) : (bit32)(Q/rem))
259 #define NUM_QUEUES_IN_MEM(Q, rem) ((((bit32)Q % rem) > 0) ? (bit32)(Q%rem) : (bit32)(MAX_QUEUE_EACH…
261 #define MAX_DEV_BITS 0xFFFF0000
262 #define PHY_COUNT_BITS 0x01f80000
263 #define Q_SUPPORT_BITS 0x0007ffff
264 #define SAS_SPEC_BITS 0xfe000000
265 #define HP_SUPPORT_BIT 0x00010000
266 #define INT_COL_BIT 0x00040000
267 #define INT_DELAY_BITS 0xFFFF
268 #define INT_THR_BITS 0xFF
269 #define INT_VEC_BITS 0xFF
271 #define AUTO_HARD_RESET_DEREG_FLAG 0x00000001
272 #define AUTO_FW_CLEANUP_DEREG_FLAG 0x00000002
274 #define BYTE_MASK 0xff
276 #define INT_OPTION 0x7FFF
278 #define ITL_TO_DEFAULT 0xFFFF
284 #define HW_CFG_PICI_EFFECTIVE_ADDRESS 0x1
288 #define SUBID_SPC 0x00000000
289 #define SUBID_SPCV 0x56781234
291 #define VEN_DEV_SPC 0x80010000
292 #define VEN_DEV_HIL 0x80810000
294 #define VEN_DEV_SPCV 0x80080000
295 #define VEN_DEV_SPCVE 0x80090000
296 #define VEN_DEV_SPCVP 0x80180000
297 #define VEN_DEV_SPCVEP 0x80190000
299 #define VEN_DEV_SPC12V 0x80700000
300 #define VEN_DEV_SPC12VE 0x80710000
301 #define VEN_DEV_SPC12VP 0x80720000
302 #define VEN_DEV_SPC12VEP 0x80730000
303 #define VEN_DEV_9015 0x90150000
304 #define VEN_DEV_9060 0x90600000
306 #define VEN_DEV_ADAPVEP 0x80890000
307 #define VEN_DEV_ADAPVP 0x80880000
310 #define VEN_DEV_SFC 0x80250000
313 #define VEN_DEV_SPC12ADP 0x80740000 /* 8 ports */
314 #define VEN_DEV_SPC12ADPE 0x80750000 /* 8 ports encrypt */
315 #define VEN_DEV_SPC12ADPP 0x80760000 /* 16 ports */
316 #define VEN_DEV_SPC12ADPEP 0x80770000 /* 16 ports encrypt */
317 #define VEN_DEV_SPC12SATA 0x80060000 /* SATA HBA */