Lines Matching +full:0 +full:xf6000000
39 (bitptr)&(((STRUCT_TYPE *)0)->FEILD)
56 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
57 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF);
60 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
61 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
62 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
63 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF);
82 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
83 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF);
86 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
87 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
88 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
89 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF);
123 OSSA_WRITE_LE_32(agRoot, sglDest, 0, sgLower); \
137 #define AGSA_FLIP_2_BYTES(_x) ((bit16)(((((bit16)(_x))&0x00FF)<<8)| \
138 ((((bit16)(_x))&0xFF00)>>8)))
145 #define AGSA_FLIP_4_BYTES(_x) ((bit32)(((((bit32)(_x))&0x000000FF)<<24)| \
146 ((((bit32)(_x))&0x0000FF00)<<8)| \
147 ((((bit32)(_x))&0x00FF0000)>>8)| \
148 ((((bit32)(_x))&0xFF000000)>>24)))
249 #define BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
253 #define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
257 #define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
261 #define BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
362 #define BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
366 #define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
370 #define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
374 #define BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
544 #define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
548 #define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
552 #define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
556 #define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
712 #define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
716 #define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
720 #define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
724 #define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
752 #define FW_THIS_VERSION_SPC12G 0x03060005
754 #define FW_THIS_VERSION_SPC6G 0x02092400
755 #define FW_THIS_VERSION_SPC 0x01110000
758 #define STSDK_LL_INTERFACE_VERSION 0x20A
759 #define STSDK_LL_OLD_INTERFACE_VERSION 0x1 /* SPC and SPCv before 02…
763 #define MIN_FW_SPCVE_VERSION_SUPPORTED 0x02000000 /**< 2.00 FW */
765 #define STSDK_LL_12G_INTERFACE_VERSION 0x302
769 #define MIN_FW_12G_SPCVE_VERSION_SUPPORTED 0x03000000 /**< 3.00 FW */
771 #define STSDK_LL_SPC_VERSION 0x01100000 /**< current SPC FW version…
773 #define MIN_FW_SPC_VERSION_SUPPORTED 0x01062502 /**< 1.06d FW */
775 #define STSDK_LL_INTERFACE_VERSION_IGNORE_MASK 0xF00
779 #define AGSA_RC_SUCCESS 0x00 /**< Successful function return value …
780 #define AGSA_RC_FAILURE 0x01 /**< Failed function return value */
781 #define AGSA_RC_BUSY 0x02 /**< Busy function return value */
783 #define AGSA_RC_HDA_NO_FW_RUNNING 0x03 /**< HDA mode and no FW running */
784 #define AGSA_RC_FW_NOT_IN_READY_STATE 0x04 /**< FW not in ready state */
786 #define AGSA_RC_VERSION_INCOMPATIBLE 0x05 /**< Version mismatch */
787 #define AGSA_RC_VERSION_UNTESTED 0x06 /**< Version not tested */
788 #define AGSA_RC_NOT_SUPPORTED 0x07 /**< Operation not supported on the cu…
789 #define AGSA_RC_COMPLETE 0x08
794 #define AGSA_CACHED_MEM 0x00 /**< CACHED memory type */
795 #define AGSA_DMA_MEM 0x01 /**< DMA memory type */
796 #define AGSA_CACHED_DMA_MEM 0x02 /**< CACHED DMA memory type */
833 #define AGSA_PHY_LINK_RESET 0x01
834 #define AGSA_PHY_HARD_RESET 0x02
835 #define AGSA_PHY_GET_ERROR_COUNTS 0x03 /* SPC only used in original saLocalPhyCon…
836 #define AGSA_PHY_CLEAR_ERROR_COUNTS 0x04 /* SPC only */
837 #define AGSA_PHY_GET_BW_COUNTS 0x05 /* SPC only */
838 #define AGSA_PHY_NOTIFY_ENABLE_SPINUP 0x10
839 #define AGSA_PHY_BROADCAST_ASYNCH_EVENT 0x12
840 #define AGSA_PHY_COMINIT_OOB 0x20
842 #define AGSA_SAS_PHY_ERR_COUNTERS_PAGE 0x01 /* retrieve the SAS PHY error counters */
843 #define AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE 0x02 /* retrieve the SAS PHY error counters After captu…
844 #define AGSA_SAS_PHY_BW_COUNTERS_PAGE 0x03 /* retrieve the SAS PHY transmit and receive bandw…
845 #define AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE 0x04 /* retrieve the SAS PHY analog settings */
846 #define AGSA_SAS_PHY_GENERAL_STATUS_PAGE 0x05 /* retrieve the SAS PHY general status for the PHY…
847 #define AGSA_PHY_SNW3_PAGE 0x06
848 #define AGSA_PHY_RATE_CONTROL_PAGE 0x07 /* Used to set several rate control parameters. */
849 #define AGSA_SAS_PHY_MISC_PAGE 0x08
850 #define AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE 0x08 /* Used to set retry and bac…
855 #define AGSA_CHIP_RESET 0x00 /**< flag to reset hard reset */
856 #define AGSA_SOFT_RESET 0x01 /**< flag to reset the controller chip…
861 #define AG_SA_DISCOVERY_TYPE_SAS 0x00 /**< flag to discover SAS devices */
862 #define AG_SA_DISCOVERY_TYPE_SATA 0x01 /**< flag to discover SATA devices */
867 #define AG_SA_DISCOVERY_OPTION_FULL_START 0x00 /**< flag to start full discovery */
868 #define AG_SA_DISCOVERY_OPTION_INCREMENTAL_START 0x01 /**< flag to start incremental discove…
869 #define AG_SA_DISCOVERY_OPTION_ABORT 0x02 /**< flag to abort a discovery */
882 bit3-0 - Initiator, target or task mode (1 to 8)
884 #define AGSA_REQTYPE_MASK 0xF0000000 /**< request type mask */
885 #define AGSA_REQ_TYPE_UNKNOWN 0x00000000 /**< unknown request type */
886 #define AGSA_SSP_REQTYPE 0x80000000
887 #define AGSA_SMP_REQTYPE 0x40000000
888 #define AGSA_SATA_REQTYPE 0x20000000
890 #define AGSA_DIR_MASK 0x00000300
891 #define AGSA_AUTO_MASK 0x00000080
892 #define AGSA_SATA_ATAP_MASK 0x0000FC00
894 #define AGSA_DIR_NONE 0x00000000
895 #define AGSA_DIR_CONTROLLER_TO_HOST 0x00000100 /**< used to be called AGSA_DIR_REA…
896 #define AGSA_DIR_HOST_TO_CONTROLLER 0x00000200 /**< used to be called AGSA_DIR_WRI…
899 #define AGSA_AUTO_GOOD_RESPONSE 0x00000080
902 #define AGSA_SSP_INIT 0x00000001
903 #define AGSA_SSP_TGT_MODE 0x00000003
904 #define AGSA_SSP_TASK_MGNT 0x00000005
905 #define AGSA_SSP_TGT_RSP 0x00000006
906 #define AGSA_SMP_INIT 0x00000007
907 #define AGSA_SMP_TGT 0x00000008
916 #define AGSA_MSG 0x00000010
917 #define AGSA_SSP_EXT_BIT 0x00000020
918 #define AGSA_SSP_INDIRECT_BIT 0x00000040
922 #define AGSA_INDIRECT_CDB_BIT 0x00000008
923 #define AGSA_SKIP_MASK_BIT 0x00000010
924 #define AGSA_ENCRYPT_BIT 0x00000020
925 #define AGSA_DIF_BIT 0x00000040
926 #define AGSA_DIF_LA_BIT 0x00000080
927 #define AGSA_DIRECTION_BITS 0x00000300
928 #define AGSA_SKIP_MASK_OFFSET_BITS 0x0F000000
929 #define AGSA_SSP_INFO_LENGTH_BITS 0xF0000000
932 #define AGSA_SSP_TGT_BITS_INI_TAG 0xFFFF0000 /* 16 31 */
933 #define AGSA_SSP_TGT_BITS_ODS 0x00008000 /* 15 */
934 #define AGSA_SSP_TGT_BITS_DEE_DIF 0x00004000 /* 14 */
935 #define AGSA_SSP_TGT_BITS_DEE 0x00002000 /* 13 14 */
936 #define AGSA_SSP_TGT_BITS_R 0x00001000 /* 12 */
937 #define AGSA_SSP_TGT_BITS_DAD 0x00000600 /* 11 10 */
938 #define AGSA_SSP_TGT_BITS_DIR 0x00000300 /* 8 9 */
939 #define AGSA_SSP_TGT_BITS_DIR_IN 0x00000100 /* 8 9 */
940 #define AGSA_SSP_TGT_BITS_DIR_OUT 0x00000200 /* 8 9 */
941 #define AGSA_SSP_TGT_BITS_AGR 0x00000080 /* 7 */
942 #define AGSA_SSP_TGT_BITS_RDF 0x00000040 /* 6 */
943 #define AGSA_SSP_TGT_BITS_RTE 0x00000030 /* 4 5 */
944 #define AGSA_SSP_TGT_BITS_AN 0x00000006 /* 2 3 */
948 #define AGSA_DIF_UPDATE_BITS 0xFC000000
949 #define AGSA_DIF_VERIFY_BITS 0x03F00000
950 #define AGSA_DIF_BLOCK_SIZE_BITS 0x000F0000
951 #define AGSA_DIF_ENABLE_BLOCK_COUNT_BIT 0x00000040
952 #define AGSA_DIF_CRC_SEED_BIT 0x00000020
953 #define AGSA_DIF_CRC_INVERT_BIT 0x00000010
954 #define AGSA_DIF_CRC_VERIFY_BIT 0x00000008
955 #define AGSA_DIF_OP_BITS 0x00000007
957 #define AGSA_DIF_OP_INSERT 0x00000000
958 #define AGSA_DIF_OP_VERIFY_AND_FORWARD 0x00000001
959 #define AGSA_DIF_OP_VERIFY_AND_DELETE 0x00000002
960 #define AGSA_DIF_OP_VERIFY_AND_REPLACE 0x00000003
961 #define AGSA_DIF_OP_RESERVED2 0x00000004
962 #define AGSA_DIF_OP_VERIFY_UDT_REPLACE_CRC 0x00000005
963 #define AGSA_DIF_OP_RESERVED3 0x00000006
964 #define AGSA_DIF_OP_REPLACE_UDT_REPLACE_CRC 0x00000007
968 #define AGSA_ENCRYPT_DEK_BITS 0xFFFFFF000
969 #define AGSA_ENCRYPT_SKIP_DIF_BIT 0x000000010
970 #define AGSA_ENCRYPT_KEY_TABLE_BITS 0x00000000C
971 #define AGSA_ENCRYPT_KEY_TAG_BIT 0x000000002
974 #define AGSA_ENCRYPT_ECB_Mode 0
975 #define AGSA_ENCRYPT_XTS_Mode 0x6
978 #define AGSA_ENCRYPT_KEK_SELECT_BITS 0x0000000E0
979 #define AGSA_ENCRYPT_SECTOR_SIZE_BITS 0x00000001F
1009 #define AGSA_SMP_IOCTL_REQUEST 0xFFFFFFFF
1011 #define AGSA_SATA_ATAP_SRST_ASSERT 0x00000400
1012 #define AGSA_SATA_ATAP_SRST_DEASSERT 0x00000800
1013 #define AGSA_SATA_ATAP_EXECDEVDIAG 0x00000C00
1014 #define AGSA_SATA_ATAP_NON_DATA 0x00001000
1015 #define AGSA_SATA_ATAP_PIO 0x00001400
1016 #define AGSA_SATA_ATAP_DMA 0x00001800
1017 #define AGSA_SATA_ATAP_NCQ 0x00001C00
1018 #define AGSA_SATA_ATAP_PKT_DEVRESET 0x00002000
1019 #define AGSA_SATA_ATAP_PKT 0x00002400
1051 #define AGSA_INTERRUPT_HANDLE_ALL_CHANNELS 0xFFFFFFFF /**< flag indicates handles inter…
1056 #define AGSA_IBQ_PRIORITY_NORMAL 0x0
1057 #define AGSA_IBQ_PRIORITY_HIGH 0x1
1063 #define AGSA_PHY_MAX_LINK_RATE_MASK 0x0000000F /* bits 0-3 */
1064 #define AGSA_PHY_MAX_LINK_RATE_1_5G 0x00000001 /* 0001b */
1065 #define AGSA_PHY_MAX_LINK_RATE_3_0G 0x00000002 /* 0010b */
1066 #define AGSA_PHY_MAX_LINK_RATE_6_0G 0x00000004 /* 0100b */
1067 #define AGSA_PHY_MAX_LINK_RATE_12_0G 0x00000008 /* 1000b */
1070 #define AGSA_PHY_MODE_MASK 0x00000030 /* bits 4-5 */
1071 #define AGSA_PHY_MODE_SAS 0x00000010 /* 01b */
1072 #define AGSA_PHY_MODE_SATA 0x00000020 /* 10b */
1075 #define AGSA_PHY_SPIN_UP_HOLD_MASK 0x00000040 /* bit6 */
1076 #define AGSA_PHY_SPIN_UP_HOLD_ON 0x00000040 /* 1b */
1077 #define AGSA_PHY_SPIN_UP_HOLD_OFF 0x00000000 /* 0b */
1083 #define AGSA_DEV_INFO_SASSATA_MASK 0x00000010 /* bit 4 */
1084 #define AGSA_DEV_INFO_SASSATA_SAS 0x00000010 /* 1b */
1085 #define AGSA_DEV_INFO_SASSATA_SATA 0x00000000 /* 0b */
1088 #define AGSA_DEV_INFO_RATE_MASK 0x0000000F /* bits 0-3 */
1089 #define AGSA_DEV_INFO_RATE_1_5G 0x00000008 /* 8h */
1090 #define AGSA_DEV_INFO_RATE_3_0G 0x00000009 /* 9h */
1091 #define AGSA_DEV_INFO_RATE_6_0G 0x0000000A /* Ah */
1092 #define AGSA_DEV_INFO_RATE_12_0G 0x0000000B /* Bh */
1095 #define AGSA_DEV_INFO_DEV_TYPE_MASK 0x000000E0 /* bits 5-7 */
1096 #define AGSA_DEV_INFO_DEV_TYPE_END_DEVICE 0x00000020 /* 001b */
1097 #define AGSA_DEV_INFO_DEV_TYPE_EDGE_EXP_DEVICE 0x00000040 /* 010b */
1098 #define AGSA_DEV_INFO_DEV_TYPE_FANOUT_EXP_DEVICE 0x00000060 /* 011b */
1103 #define AGSA_ABORT_TASK 0x01
1104 #define AGSA_ABORT_TASK_SET 0x02
1105 #define AGSA_CLEAR_TASK_SET 0x04
1106 #define AGSA_LOGICAL_UNIT_RESET 0x08
1107 #define AGSA_IT_NEXUS_RESET 0x10
1108 #define AGSA_CLEAR_ACA 0x40
1109 #define AGSA_QUERY_TASK 0x80
1110 #define AGSA_QUERY_TASK_SET 0x81
1111 #define AGSA_QUERY_UNIT_ATTENTION 0x82
1116 #define AGSA_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0
1117 #define AGSA_INVALID_FRAME 0x2
1118 #define AGSA_TASK_MANAGEMENT_FUNCTION_NOT_SUPPORTED 0x4
1119 #define AGSA_TASK_MANAGEMENT_FUNCTION_FAILED 0x5
1120 #define AGSA_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8
1121 #define AGSA_INCORRECT_LOGICAL_UNIT_NUMBER 0x9
1123 #define AGSA_OVERLAPPED_TAG_ATTEMPTED 0xA
1125 #define AGSA_SATA_BSY_OVERRIDE 0x00080000
1126 #define AGSA_SATA_CLOSE_CLEAR_AFFILIATION 0x00400000
1132 #define AGSA_RETURN_D2H_FIS_GOOD_COMPLETION 0x000001
1133 #define AGSA_SATA_ENABLE_ENCRYPTION 0x000004
1134 #define AGSA_SATA_ENABLE_DIF 0x000008
1135 #define AGSA_SATA_SKIP_QWORD 0xFFFF00
1138 /* Bits 0,1 use TLR_MASK */
1140 #define AGSA_SAS_ENABLE_ENCRYPTION 0x0004
1141 #define AGSA_SAS_ENABLE_DIF 0x0008
1144 #define AGSA_SAS_USE_DIF_ENC_OPSTART 0x0010
1147 #define AGSA_SAS_ENABLE_SKIP_MASK 0x0010
1148 #define AGSA_SAS_SKIP_MASK_OFFSET 0xFFE0
1153 #define AGSA_PHY_CONTROL_LINK_RESET_OP 0x1
1154 #define AGSA_PHY_CONTROL_HARD_RESET_OP 0x2
1155 #define AGSA_PHY_CONTROL_DISABLE 0x3
1156 #define AGSA_PHY_CONTROL_CLEAR_ERROR_LOG_OP 0x5
1157 #define AGSA_PHY_CONTROL_CLEAR_AFFILIATION 0x6
1158 #define AGSA_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x7
1163 #define AGSA_SAS_DIAG_START 0x1
1164 #define AGSA_SAS_DIAG_END 0x0
1169 #define AGSA_PORT_SET_SMP_PHY_WIDTH 0x1
1170 #define AGSA_PORT_SET_PORT_RECOVERY_TIME 0x2
1171 #define AGSA_PORT_IO_ABORT 0x3
1172 #define AGSA_PORT_SET_PORT_RESET_TIME 0x4
1173 #define AGSA_PORT_HARD_RESET 0x5
1174 #define AGSA_PORT_CLEAN_UP 0x6
1175 #define AGSA_STOP_PORT_RECOVERY_TIMER 0x7
1178 #define SA_DS_OPERATIONAL 0x1
1179 #define SA_DS_PORT_IN_RESET 0x2
1180 #define SA_DS_IN_RECOVERY 0x3
1181 #define SA_DS_IN_ERROR 0x4
1182 #define SA_DS_NON_OPERATIONAL 0x7
1199 #define OSSA_SUCCESS 0x00 /**< flag indicates successful callback …
1200 #define OSSA_FAILURE 0x01 /**< flag indicates failed callback stat…
1203 #define OSSA_RESET_PENDING 0x03 /**< flag indicates reset pending callba…
1204 #define OSSA_CHIP_FAILED 0x04 /**< flag indicates chip failed callback…
1205 #define OSSA_FREEZE_FAILED 0x05 /**< flag indicates freeze failed callba…
1208 #define OSSA_PHY_CONTROL_FAILURE 0x03 /**< flag indicates phy Control operatio…
1211 #define OSSA_FAILURE_OUT_OF_RESOURCE 0x01 /**< flag indicates failed callback stat…
1212 #define OSSA_FAILURE_DEVICE_ALREADY_REGISTERED 0x02 /**< flag indicates failed callback stat…
1213 #define OSSA_FAILURE_INVALID_PHY_ID 0x03 /**< flag indicates failed callback stat…
1214 #define OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 /**< flag indicates failed callback stat…
1215 #define OSSA_FAILURE_PORT_ID_OUT_OF_RANGE 0x05 /**< flag indicates failed callback stat…
1216 #define OSSA_FAILURE_PORT_NOT_VALID_STATE 0x06 /**< flag indicates failed callback stat…
1217 #define OSSA_FAILURE_DEVICE_TYPE_NOT_VALID 0x07 /**< flag indicates failed callback stat…
1218 #define OSSA_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020
1219 #define OSSA_ERR_DEVICE_ALREADY_REGISTERED 0x1021
1220 #define OSSA_ERR_DEVICE_TYPE_NOT_VALID 0x1022
1222 #define OSSA_MPI_ERR_DEVICE_ACCEPT_PENDING 0x1027 /**/
1224 #define OSSA_ERR_PORT_INVALID 0x1041
1225 #define OSSA_ERR_PORT_STATE_NOT_VALID 0x1042
1227 #define OSSA_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045
1229 #define OSSA_ERR_PHY_ID_INVALID 0x1061
1230 #define OSSA_ERR_PHY_ID_ALREADY_REGISTERED 0x1062
1235 #define OSSA_INVALID_HANDLE 0x02 /**< flag indicates failed callback stat…
1236 #define OSSA_ERR_DEVICE_HANDLE_INVALID 0x1023 /* MPI_ERR_DEVICE_HANDLE_INVALID The dev…
1237 #define OSSA_ERR_DEVICE_BUSY 0x1024 /* MPI_ERR_DEVICE_BUSY Device has outsta…
1240 #define OSSA_RC_ACCEPT 0x00 /**< flag indicates the result of the ca…
1241 #define OSSA_RC_REJECT 0x01 /**< flag indicates the result of the ca…
1244 #define OSSA_INVALID_STATE 0x0001
1245 #define OSSA_ERR_DEVICE_NEW_STATE_INVALID 0x1025
1246 #define OSSA_ERR_DEVICE_STATE_CHANGE_NOT_ALLOWED 0x1026
1247 #define OSSA_ERR_DEVICE_STATE_INVALID 0x0049
1250 #define OSSA_DIAG_SUCCESS 0x00 /* Successful SAS diagnostic command. */
1251 #define OSSA_DIAG_INVALID_COMMAND 0x01 /* Invalid SAS diagnostic command. */
1252 #define OSSA_REGISTER_ACCESS_TIMEOUT 0x02 /* Register access has been timed-out. Thi…
1253 #define OSSA_DIAG_FAIL 0x02 /* SAS diagnostic command failed. This is …
1254 #define OSSA_DIAG_NOT_IN_DIAGNOSTIC_MODE 0x03 /* Attempted to execute SAS diagnostic com…
1255 #define OSSA_DIAG_INVALID_PHY 0x04 /* Attempted to execute SAS diagnostic com…
1256 #define OSSA_MEMORY_ALLOC_FAILURE 0x05 /* Memory allocation failed in diagnostic.…
1260 #define OSSA_DIAG_SE_SUCCESS 0x00
1261 #define OSSA_DIAG_SE_INVALID_PHY_ID 0x01
1262 #define OSSA_DIAG_PHY_NOT_DISABLED 0x02
1263 #define OSSA_DIAG_OTHER_FAILURE 0x03 /* SPC */
1264 #define OSSA_DIAG_OPCODE_INVALID 0x03
1267 #define OSSA_PORT_CONTROL_FAILURE 0x03
1269 #define OSSA_MPI_ERR_PORT_IO_RESOURCE_UNAVAILABLE 0x1004
1270 #define OSSA_MPI_ERR_PORT_INVALID 0x1041 /**/
1271 #define OSSA_MPI_ERR_PORT_OP_NOT_IN_USE 0x1043 /**/
1272 #define OSSA_MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044 /**/
1273 #define OSSA_MPI_ERR_PORT_SMP_WIDTH_EXCEEDED 0x1045 /**/
1274 #define OSSA_MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047 /**/
1277 #define GET_GSM_SM_INFO 0x02
1278 #define GET_IOST_RB_INFO 0x03
1283 #define OSSA_HW_EVENT_RESET_START 0x01 /**< flag indicates reset started event …
1284 #define OSSA_HW_EVENT_RESET_COMPLETE 0x02 /**< flag indicates chip reset completed…
1285 #define OSSA_HW_EVENT_PHY_STOP_STATUS 0x03 /**< flag indicates phy stop event statu…
1286 #define OSSA_HW_EVENT_SAS_PHY_UP 0x04 /**< flag indicates SAS link up event */
1287 #define OSSA_HW_EVENT_SATA_PHY_UP 0x05 /**< flag indicates SATA link up event */
1288 #define OSSA_HW_EVENT_SATA_SPINUP_HOLD 0x06 /**< flag indicates SATA spinup hold eve…
1289 #define OSSA_HW_EVENT_PHY_DOWN 0x07 /**< flag indicates link down event */
1291 #define OSSA_HW_EVENT_BROADCAST_CHANGE 0x09 /**< flag indicates broadcast change eve…
1292 /* not used spcv 0x0A*/
1293 #define OSSA_HW_EVENT_PHY_ERROR 0x0A /**< flag indicates link error event */
1294 #define OSSA_HW_EVENT_BROADCAST_SES 0x0B /**< flag indicates broadcast change (SE…
1295 #define OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC 0x0C
1296 #define OSSA_HW_EVENT_HARD_RESET_RECEIVED 0x0D /**< flag indicates hardware reset recei…
1297 /* not used spcv 0x0E*/
1298 #define OSSA_HW_EVENT_MALFUNCTION 0x0E /**< flag indicates unrecoverable Error …
1299 #define OSSA_HW_EVENT_ID_FRAME_TIMEOUT 0x0F /**< flag indicates ID Frame Timeout eve…
1300 #define OSSA_HW_EVENT_BROADCAST_EXP 0x10 /**< flag indicates broadcast (EXPANDER)…
1301 /* not used spcv 0x11*/
1302 #define OSSA_HW_EVENT_PHY_START_STATUS 0x11 /**< flag indicates phy start event stat…
1303 #define OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD 0x12 /**< flag indicates Link error invalid D…
1304 #define OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR 0x13 /**< flag indicates Phy error disparity …
1305 #define OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION 0x14 /**< flag indicates Phy error code viola…
1306 #define OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH 0x15 /**< flag indicates Link error loss of D…
1307 #define OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED 0x16 /**< flag indicates Link error phy reset…
1308 #define OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17 /**< flag indicates Port Recovery timeou…
1309 #define OSSA_HW_EVENT_PORT_RECOVER 0x18 /**< flag indicates Port Recovery */
1310 #define OSSA_HW_EVENT_PORT_RESET_TIMER_TMO 0x19 /**< flag indicates Port Reset Timer out…
1311 #define OSSA_HW_EVENT_PORT_RESET_COMPLETE 0x20 /**< flag indicates Port Reset Complete …
1312 #define OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT 0x21 /**< flag indicates Broadcast Asynch Eve…
1313 #define OSSA_HW_EVENT_IT_NEXUS_LOSS 0x22 /**< Custom: H/W event for IT Nexus Loss…
1315 #define OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED 0x25
1317 #define OSSA_HW_EVENT_ENCRYPTION 0x83 /**< TSDK internal flag indicating that …
1318 #define OSSA_HW_EVENT_MODE 0x84 /**< TSDK internal flag indicating that …
1319 #define OSSA_HW_EVENT_SECURITY_MODE 0x85 /**< TSDK internal flag indicating that …
1323 #define OSSA_PORT_NOT_ESTABLISHED 0x00 /**< flag indicates port is not establis…
1324 #define OSSA_PORT_VALID 0x01 /**< flag indicates port valid */
1325 #define OSSA_PORT_LOSTCOMM 0x02 /**< flag indicates port lost communicat…
1326 #define OSSA_PORT_IN_RESET 0x04 /**< flag indicates port in reset state …
1327 #define OSSA_PORT_3RDPARTY_RESET 0x07 /**< flag indicates port in 3rd party re…
1328 #define OSSA_PORT_INVALID 0x08 /**< flag indicates port invalid */
1331 #define OSSA_CTL_SUCCESS 0x0000
1332 #define OSSA_CTL_INVALID_CONFIG_PAGE 0x1001
1333 #define OSSA_CTL_INVALID_PARAM_IN_CONFIG_PAGE 0x1002
1334 #define OSSA_CTL_INVALID_ENCRYPTION_SECURITY_MODE 0x1003
1335 #define OSSA_CTL_RESOURCE_NOT_AVAILABLE 0x1004
1336 #define OSSA_CTL_CONTROLLER_NOT_IDLE 0x1005
1337 // #define OSSA_CTL_NVM_MEMORY_ACCESS_ERR 0x100B
1338 #define OSSA_CTL_OPERATOR_AUTHENTICATION_FAILURE 0x100XX
1345 #define OSSA_INBOUND_V_BIT_NOT_SET 0x01
1346 #define OSSA_INBOUND_OPC_NOT_SUPPORTED 0x02
1347 #define OSSA_INBOUND_IOMB_INVALID_OBID 0x03
1352 #define OSSA_FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00 /**< flag indicates fw flash update comp…
1353 #define OSSA_FLASH_UPDATE_IN_PROGRESS 0x01 /**< flag indicates fw flash update in p…
1354 #define OSSA_FLASH_UPDATE_HDR_ERR 0x02 /**< flag indicates fw flash header erro…
1355 #define OSSA_FLASH_UPDATE_OFFSET_ERR 0x03 /**< flag indicates fw flash offset erro…
1356 #define OSSA_FLASH_UPDATE_CRC_ERR 0x04 /**< flag indicates fw flash CRC error */
1357 #define OSSA_FLASH_UPDATE_LENGTH_ERR 0x05 /**< flag indicates fw flash length erro…
1358 #define OSSA_FLASH_UPDATE_HW_ERR 0x06 /**< flag indicates fw flash HW error */
1359 #define OSSA_FLASH_UPDATE_HMAC_ERR 0x0E /**< flag indicates fw flash Firmware im…
1361 #define OSSA_FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10 /**< flag indicates fw flash down load n…
1362 #define OSSA_FLASH_UPDATE_DISABLED 0x11 /**< flag indicates fw flash Update disa…
1363 #define OSSA_FLASH_FWDNLD_DEVICE_UNSUPPORT 0x12 /**< flag indicates fw flash Update disa…
1368 #define OSSA_DISCOVER_STARTED 0x00 /**< flag indicates discover started */
1369 #define OSSA_DISCOVER_FOUND_DEVICE 0x01 /**< flag indicates discovery found a ne…
1370 #define OSSA_DISCOVER_REMOVED_DEVICE 0x02 /**< flag indicates discovery found a de…
1371 #define OSSA_DISCOVER_COMPLETE 0x03 /**< flag indicates discover completed */
1372 #define OSSA_DISCOVER_ABORT 0x04 /**< flag indicates discover error12 */
1373 #define OSSA_DISCOVER_ABORT_ERROR_1 0x05 /**< flag indicates discover error1 */
1374 #define OSSA_DISCOVER_ABORT_ERROR_2 0x06 /**< flag indicates discover error2 */
1375 #define OSSA_DISCOVER_ABORT_ERROR_3 0x07 /**< flag indicates discover error3 */
1376 #define OSSA_DISCOVER_ABORT_ERROR_4 0x08 /**< flag indicates discover error4 */
1377 #define OSSA_DISCOVER_ABORT_ERROR_5 0x09 /**< flag indicates discover error5 */
1378 #define OSSA_DISCOVER_ABORT_ERROR_6 0x0A /**< flag indicates discover error6 */
1379 #define OSSA_DISCOVER_ABORT_ERROR_7 0x0B /**< flag indicates discover error7 */
1380 #define OSSA_DISCOVER_ABORT_ERROR_8 0x0C /**< flag indicates discover error8 */
1381 #define OSSA_DISCOVER_ABORT_ERROR_9 0x0D /**< flag indicates discover error9 */
1386 #define OSSA_DEBUG_LEVEL_0 0x00 /**< debug level 0 */
1387 #define OSSA_DEBUG_LEVEL_1 0x01 /**< debug level 1 */
1388 #define OSSA_DEBUG_LEVEL_2 0x02 /**< debug level 2 */
1389 #define OSSA_DEBUG_LEVEL_3 0x03 /**< debug level 3 */
1390 #define OSSA_DEBUG_LEVEL_4 0x04 /**< debug level 4 */
1392 #define OSSA_DEBUG_PRINT_INVALID_NUMBER 0xFFFFFFFF /**< the number won't be printed b…
1394 #define OSSA_FRAME_TYPE_SSP_CMD 0x06 /**< flag indicates received frame is SS…
1395 #define OSSA_FRAME_TYPE_SSP_TASK 0x16 /**< flag indicates received frame is SS…
1398 #define OSSA_EVENT_SOURCE_DEVICE_HANDLE_ADDED 0x00
1399 #define OSSA_EVENT_SOURCE_DEVICE_HANDLE_REMOVED 0x01
1402 #define OSSA_DEV_INFO_INVALID_HANDLE 0x01
1403 #define OSSA_DEV_INFO_NO_EXTENDED_INFO 0x02
1404 #define OSSA_DEV_INFO_SAS_EXTENDED_INFO 0x03
1405 #define OSSA_DEV_INFO_SATA_EXTENDED_INFO 0x04
1408 #define AGSA_CMD_TYPE_DIAG_OPRN_PERFORM 0x00
1409 #define AGSA_CMD_TYPE_DIAG_OPRN_STOP 0x01
1410 #define AGSA_CMD_TYPE_DIAG_THRESHOLD_SPECIFY 0x02
1411 #define AGSA_CMD_TYPE_DIAG_RECEIVE_ENABLE 0x03
1412 #define AGSA_CMD_TYPE_DIAG_REPORT_GET 0x04
1413 #define AGSA_CMD_TYPE_DIAG_ERR_CNT_RESET 0x05
1416 #define AGSA_CMD_DESC_PRBS 0x00
1417 #define AGSA_CMD_DESC_CJTPAT 0x01
1418 #define AGSA_CMD_DESC_USR_PATTERNS 0x02
1419 #define AGSA_CMD_DESC_PRBS_ERR_INSERT 0x08
1420 #define AGSA_CMD_DESC_PRBS_INVERT 0x09
1421 #define AGSA_CMD_DESC_CJTPAT_INVERT 0x0A
1422 #define AGSA_CMD_DESC_CODE_VIOL_INSERT 0x0B
1423 #define AGSA_CMD_DESC_DISP_ERR_INSERT 0x0C
1424 #define AGSA_CMD_DESC_SSPA_PERF_EVENT_1 0x0E
1425 #define AGSA_CMD_DESC_LINE_SIDE_ANA_LPBK 0x10
1426 #define AGSA_CMD_DESC_LINE_SIDE_DIG_LPBK 0x11
1427 #define AGSA_CMD_DESC_SYS_SIDE_ANA_LPBK 0x12
1430 #define AGSA_CMD_DESC_PRBS_ERR_CNT 0x00
1431 #define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT 0x01
1432 #define AGSA_CMD_DESC_DISP_ERR_CNT 0x02
1433 #define AGSA_CMD_DESC_LOST_DWD_SYNC_CNT 0x05
1434 #define AGSA_CMD_DESC_INVALID_DWD_CNT 0x06
1435 #define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT_THHD 0x09
1436 #define AGSA_CMD_DESC_DISP_ERR_CNT_THHD 0x0A
1437 #define AGSA_CMD_DESC_SSPA_PERF_CNT 0x0B
1438 #define AGSA_CMD_DESC_PHY_RST_CNT 0x0C
1439 #define AGSA_CMD_DESC_SSPA_PERF_1_THRESHOLD 0x0E
1441 #define AGSA_CMD_DESC_CODE_VIOL_ERR_THHD 0x19
1442 #define AGSA_CMD_DESC_DISP_ERR_THHD 0x1A
1443 #define AGSA_CMD_DESC_RX_LINK_BANDWIDTH 0x1B
1444 #define AGSA_CMD_DESC_TX_LINK_BANDWIDTH 0x1C
1445 #define AGSA_CMD_DESC_ALL 0x1F
1448 #define AGSA_NVMD_TWI_DEVICES 0x00
1449 #define AGSA_NVMD_CONFIG_SEEPROM 0x01
1450 #define AGSA_NVMD_VPD_FLASH 0x04
1451 #define AGSA_NVMD_AAP1_REG_FLASH 0x05
1452 #define AGSA_NVMD_IOP_REG_FLASH 0x06
1453 #define AGSA_NVMD_EXPANSION_ROM 0x07
1454 #define AGSA_NVMD_REG_FLASH 0x05
1458 #define OSSA_NVMD_SUCCESS 0x0000
1459 #define OSSA_NVMD_MODE_ERROR 0x0001
1460 #define OSSA_NVMD_LENGTH_ERROR 0x0002
1461 #define OSSA_NVMD_TWI_ADDRESS_SIZE_ERROR 0x0005
1462 #define OSSA_NVMD_TWI_NACK_ERROR 0x2001
1463 #define OSSA_NVMD_TWI_LOST_ARB_ERROR 0x2002
1464 #define OSSA_NVMD_TWI_TIMEOUT_ERROR 0x2021
1465 #define OSSA_NVMD_TWI_BUS_NACK_ERROR 0x2081
1466 #define OSSA_NVMD_TWI_ARB_FAILED_ERROR 0x2082
1467 #define OSSA_NVMD_TWI_BUS_TIMEOUT_ERROR 0x20FF
1468 #define OSSA_NVMD_FLASH_PARTITION_NUM_ERROR 0x9001
1469 #define OSSA_NVMD_FLASH_LENGTH_TOOBIG_ERROR 0x9002
1470 #define OSSA_NVMD_FLASH_PROGRAM_ERROR 0x9003
1471 #define OSSA_NVMD_FLASH_DEVICEID_ERROR 0x9004
1472 #define OSSA_NVMD_FLASH_VENDORID_ERROR 0x9005
1473 #define OSSA_NVMD_FLASH_ERASE_TIMEOUT_ERROR 0x9006
1474 #define OSSA_NVMD_FLASH_ERASE_ERROR 0x9007
1475 #define OSSA_NVMD_FLASH_BUSY_ERROR 0x9008
1476 #define OSSA_NVMD_FLASH_NOT_SUPPORT_DEVICE_ERROR 0x9009
1477 #define OSSA_NVMD_FLASH_CFI_INF_ERROR 0x900A
1478 #define OSSA_NVMD_FLASH_MORE_ERASE_BLOCK_ERROR 0x900B
1479 #define OSSA_NVMD_FLASH_READ_ONLY_ERROR 0x900C
1480 #define OSSA_NVMD_FLASH_MAP_TYPE_ERROR 0x900D
1481 #define OSSA_NVMD_FLASH_MAP_DISABLE_ERROR 0x900E
1486 #define OSSA_HW_ENCRYPT_KEK_UPDATE 0x0000
1487 #define OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE 0x0001
1488 #define OSSA_HW_ENCRYPT_KEK_INVALIDTE 0x0002
1489 #define OSSA_HW_ENCRYPT_DEK_UPDATE 0x0003
1490 #define OSSA_HW_ENCRYPT_DEK_INVALIDTE 0x0004
1491 #define OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT 0x0005
1492 #define OSSA_HW_ENCRYPT_TEST_EXECUTE 0x0006
1493 #define OSSA_HW_ENCRYPT_SET_OPERATOR 0x0007
1494 #define OSSA_HW_ENCRYPT_GET_OPERATOR 0x0008
1501 #define OSSA_INVALID_ENCRYPTION_SECURITY_MODE 0x1003
1502 #define OSSA_KEK_MGMT_SUBOP_NOT_SUPPORTED_ 0x2000 /*not in PM 101222*/
1503 #define OSSA_DEK_MGMT_SUBOP_NOT_SUPPORTED 0x2000
1504 #define OSSA_MPI_ENC_ERR_ILLEGAL_DEK_PARAM 0x2001
1505 #define OSSA_MPI_ERR_DEK_MANAGEMENT_DEK_UNWRAP_FAIL 0x2002
1506 #define OSSA_MPI_ENC_ERR_ILLEGAL_KEK_PARAM 0x2021
1507 #define OSSA_MPI_ERR_KEK_MANAGEMENT_KEK_UNWRAP_FAIL 0x2022
1508 #define OSSA_MPI_ERR_KEK_MANAGEMENT_NVRAM_OPERATION_FAIL 0x2023
1511 #define OSSA_OPR_MGMT_OP_NOT_SUPPORTED 0x2060
1512 #define OSSA_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061
1513 #define OSSA_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062
1514 #define OSSA_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063
1515 #define OSSA_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064
1518 #define OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE 0x1005
1519 #define OSSA_MPI_ENC_NVM_MEM_ACCESS_ERR 0x100B
1523 #define agsaEncryptSMF 0x00000000
1524 #define agsaEncryptSMA 0x00000100
1525 #define agsaEncryptSMB 0x00000200
1531 Bit 16: Enable AES ECB. If set to 1, AES ECB is enable. If set to 0, AES ECB is disabled.
1532 Bit 22: Enable AES XTS. If set to 1, AES XTS is enable. If set to 0, AES XTS is disabled.
1534 #define agsaEncryptAcmMask 0x00ff0000
1540 #define agsaEncryptCipherModeECB 0x00000001
1541 #define agsaEncryptCipherModeXTS 0x00000002
1545 #define agsaEncryptStatusNoNVRAM 0x00000001
1546 #define agsaEncryptStatusNVRAMErr 0x00000002
1551 00000 :0x0 512B 512
1552 11000 :0x1 520B 520
1553 00010 :0x2 4K 4096
1554 00011 :0x3 4K+64B 4160
1555 00100 :0x4 4K+128B 4224
1557 11000 :0x18 512+8B 520
1558 11001 :0x19 520+8B 528
1559 11010 :0x1A 4K+8B 4104
1560 11011 :0x1B 4K+64B+8B 4168
1561 11100 :0x1C 4K+128B+8B 4232
1565 #define agsaEncryptSectorSize512 0
1571 #define agsaEncryptDIFSectorSize520 (agsaEncryptSectorSize512 | 0x18)
1572 #define agsaEncryptDIFSectorSize528 ( 0x19)
1573 #define agsaEncryptDIFSectorSize4104 (agsaEncryptSectorSize4096 | 0x18)
1574 #define agsaEncryptDIFSectorSize4168 (agsaEncryptSectorSize4160 | 0x18)
1575 #define agsaEncryptDIFSectorSize4232 (agsaEncryptSectorSize4224 | 0x18)
1589 #define AGSA_READ_SGPIO_REGISTER 0x02
1590 #define AGSA_WRITE_SGPIO_REGISTER 0x82
1592 #define AGSA_SGPIO_CONFIG_REG 0x0
1593 #define AGSA_SGPIO_DRIVE_BY_DRIVE_RECEIVE_REG 0x1
1594 #define AGSA_SGPIO_GENERAL_PURPOSE_RECEIVE_REG 0x2
1595 #define AGSA_SGPIO_DRIVE_BY_DRIVE_TRANSMIT_REG 0x3
1596 #define AGSA_SGPIO_GENERAL_PURPOSE_TRANSMIT_REG 0x4
1601 #define OSSA_SGPIO_COMMAND_SUCCESS 0x00
1602 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE 0x01
1603 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE 0x02
1604 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX 0x03
1605 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_COUNT 0x04
1606 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE 0x05
1607 #define OSSA_SGPIO_CMD_ERROR_WRONG_FUNCTION 0x06
1608 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_INDEX 0x19
1609 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_CNT 0x81
1610 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_INDEX 0x1A
1611 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_COUNT 0x82
1612 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX_REG_COUNT 0x83
1613 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE_REG_INDEX 0x1D
1614 #define OSSA_SGPIO_CMD_ERROR_WRONG_ALL_HEADER_PARAMS 0x9D
1616 #define OSSA_SGPIO_MAX_READ_DATA_COUNT 0x0D
1617 #define OSSA_SGPIO_MAX_WRITE_DATA_COUNT 0x0C
1622 #define OSSA_DFE_MPI_IO_SUCCESS 0x0000
1623 #define OSSA_DFE_DATA_OVERFLOW 0x0002
1624 #define OSSA_DFE_MPI_ERR_RESOURCE_UNAVAILABLE 0x1004
1625 #define OSSA_DFE_CHANNEL_DOWN 0x100E
1626 #define OSSA_DFE_MEASUREMENT_IN_PROGRESS 0x100F
1627 #define OSSA_DFE_CHANNEL_INVALID 0x1010
1628 #define OSSA_DFE_DMA_FAILURE 0x1011
1809 * parameters. The page code for this profile page is 0x07. This page can
1826 * Dword0 Bits 0-11: ALIGN_RATE(ALNR). Align Insertion rate is 2 in every
1829 * connections. The default value is 0x0ff. Other bits are reserved.
1830 * Dword1 Bits 0 -11: STP_ALIGN_RATE(STPALNR) Align Insertion rate is 2 in
1833 * value is 0x0ff. Other bits are reserved.
1834 * Dword2 Bits 0-7: SSP_FRAME_RATE(SSPFRMR) The number of idle DWords
1835 * between each SSP frame. 0 means no idle cycles. The default value is
1836 * 0x0. Other bits are reserved.
1858 7 : SPC GSM register at [MEMBASE-III SHIFT = 0x00_0000]
1859 8 : SPC GSM register at [MEMBASE-III SHIFT = 0x05_0000]
1860 9 : BDMA GSM register at [MEMBASE-III SHIFT = 0x01_0000]
1861 10: PCIe APP GSM register at [MEMBASE-III SHIFT = 0x01_0000]
1862 11: PCIe PHY GSM register at [MEMBASE-III SHIFT = 0x01_0000]
1863 12: PCIe CORE GSM register at [MEMBASE-III SHIFT = 0x01_0000]
1864 13: OSSP GSM register at [MEMBASE-III SHIFT = 0x02_0000]
1865 14: SSPA GSM register at [MEMBASE-III SHIFT = 0x03_0000]
1866 15: SSPA GSM register at [MEMBASE-III SHIFT = 0x04_0000]
1867 16: HSST GSM register at [MEMBASE-III SHIFT = 0x02_0000]
1868 17: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000]
1869 18: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x03_0000]
1870 19: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000]
1871 20: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000]
1872 21: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x04_0000]
1873 22: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000]
1874 23: MBIC IOP GSM register at [MEMBASE-III SHIFT = 0x06_0000]
1875 24: MBIC AAP1 GSM register at [MEMBASE-III SHIFT = 0x07_0000]
1876 25: SPBC GSM register at [MEMBASE-III SHIFT = 0x09_0000]
1877 26: GSM GSM register at [MEMBASE-III SHIFT = 0x70_0000]
1888 #define BAR_SHIFT_GSM_OFFSET 0x400000
1890 #define ONE_MEGABYTE 0x100000
1954 #define OSSA_PCIE_DIAG_SUCCESS 0x0000
1955 #define OSSA_PCIE_DIAG_INVALID_COMMAND 0x0001
1956 #define OSSA_PCIE_DIAG_INTERNAL_FAILURE 0x0002
1957 #define OSSA_PCIE_DIAG_INVALID_CMD_TYPE 0x1006
1958 #define OSSA_PCIE_DIAG_INVALID_CMD_DESC 0x1007
1959 #define OSSA_PCIE_DIAG_INVALID_PCIE_ADDR 0x1008
1960 #define OSSA_PCIE_DIAG_INVALID_BLOCK_SIZE 0x1009
1961 #define OSSA_PCIE_DIAG_LENGTH_NOT_BLOCK_SIZE_ALIGNED 0x100A
1962 #define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_MISMATCH 0x3000
1963 #define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001
1964 #define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002
1965 #define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003
1966 #define OSSA_PCIE_DIAG_MPI_ERR_INVALID_LENGTH 0x0042
1967 #define OSSA_PCIE_DIAG_MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004
1968 #define OSSA_PCIE_DIAG_MPI_ERR_CONTROLLER_NOT_IDLE 0x1005
2085 bit32 tickCount0; /* tick count in second for internal CPU-0 */
2088 bit32 phyStatus[8]; /* status of phy 0 to phy 15 */
2141 bit32 gpioEventLevelChangePart1; /* GPIEVCHANGE (pins 11-0) */
2143 bit32 gpioEventRisingEdgePart1; /* GPIEVRISE (pins 11-0) */
2145 bit32 gpioEventFallingEdgePart1; /* GPIEVALL (pins 11-0) */
2156 bit8 smpFrameType; /* 0x40 for request, 0x41 for response*/
2157 bit8 function; /* 0x02 for read, 0x82 for write */
2330 bit32 fatalErrorInterruptEnable:1; /**< 0 Fatal Error Iterrupt Enable */
2397 is satisfied. Default value is 0.*/
2406 bit32 interruptEnable:1; /* 0b: No interrupt to host (host polling)
2443 #define OQ_SHARE_PATH_BIT 0x00000001
2490 /* Log Option - bit3-0 */
2491 #define DISABLE_LOGGING 0x0
2492 #define CRITICAL_ERROR 0x1
2493 #define WARNING 0x2
2494 #define NOTICE 0x3
2495 #define INFORMATION 0x4
2496 #define DEBUGGING 0x5
2572 Bit 0-3: Connection Rate field when opening the device.
2576 0ah: 6.0 Gbps
2584 Bit 0: Retry flag.
2586 0b: disable SAS TLR (Transport Layer Retry).
2590 0b: Default setting (recommended). Actual AWT value TBD.
2603 0b : The device has no SSP initiator capability.
2606 0b : Device does not support ATAPI protocol.
2613 #define DEV_INFO_MASK 0xFF
2620 #define ATAPI_DEVICE_FLAG 0x200000 /* bit21 */
2624 #define DEV_LINK_RATE 0x3F
2633 (((devInfo)->devType_S_Rate & 0xC0) >> 5)
2652 0: Direct attached.
2768 * entry (i.e. descriptor[0]) in agsaSgl_t structure.
2802 #define AGSA_DIF_INSERT 0
2809 #define agsaDIFSectorSize512 0
2832 #define DIF_FLAG_BITS_ACTION 0x00000007 /* 0-2*/
2833 #define DIF_FLAG_BITS_CRC_VER 0x00000008 /* 3 */
2834 #define DIF_FLAG_BITS_CRC_INV 0x00000010 /* 4 */
2835 #define DIF_FLAG_BITS_CRC_SEED 0x00000020 /* 5 */
2836 #define DIF_FLAG_BITS_UDT_REF_TAG 0x00000040 /* 6 */
2837 #define DIF_FLAG_BITS_UDT_APP_TAG 0x00000080 /* 7 */
2838 #define DIF_FLAG_BITS_UDTR_REF_BLKCOUNT 0x00000100 /* 8 */
2839 #define DIF_FLAG_BITS_UDTR_APP_BLKCOUNT 0x00000200 /* 9 */
2840 #define DIF_FLAG_BITS_CUST_APP_TAG 0x00000C00 /* 10 11*/
2841 #define DIF_FLAG_BITS_EPRC 0x00001000 /* 12 */
2842 #define DIF_FLAG_BITS_Reserved 0x0000E000 /* 13 14 15*/
2843 #define DIF_FLAG_BITS_BLOCKSIZE_MASK 0x00070000 /* 16 17 18 */
2845 #define DIF_FLAG_BITS_BLOCKSIZE_512 0x00000000 /* */
2846 #define DIF_FLAG_BITS_BLOCKSIZE_520 0x00010000 /* 16 */
2847 #define DIF_FLAG_BITS_BLOCKSIZE_4096 0x00020000 /* 17 */
2848 #define DIF_FLAG_BITS_BLOCKSIZE_4160 0x00030000 /* 16 17 */
2849 #define DIF_FLAG_BITS_UDTVMASK 0x03F00000 /* 20 21 22 23 24 25 */
2851 #define DIF_FLAG_BITS_UDTUPMASK 0xF6000000 /* 26 27 28 29 30 31 */
2898 bit16 flag; /**< bit1-0 TLR as SAS specification
2966 Bit 0-1: Transport Layer Retry setting for other phase:
2978 0b: disabled
2981 0b: Disabled
2996 #define SSP_OPTION_BITS 0x3F /**< bit5-AGR, bit4-RDF bit3,2-RTE, bit1,0-AN */
2997 #define SSP_OPTION_ODS 0x8000 /**< bit15-ODS */
2999 #define SSP_OPTION_OTHR_NO_RETRY 0
3004 #define SSP_OPTION_DATA_NO_RETRY 0
3036 bit32 respOption; /**< Bit 0-1: ACK and NAK retry option:
3043 #define RESP_OPTION_BITS 0x3 /** bit0-1 */
3044 #define RESP_OPTION_ODS 0x8000 /** bit15 */
3075 Bit 0: Indirect Response (IR). This indicates
3078 0b: Direct mode
3084 0b: Direct mode
3093 #define smpFrameFlagDirectResponse 0
3095 #define smpFrameFlagDirectPayload 0
3151 #define AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04
3152 #define AGSA_INTERRUPT_CONFIGURATION_PAGE 0x05
3153 #define AGSA_IO_GENERAL_CONFIG_PAGE 0x06
3154 #define AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE 0x20
3155 #define AGSA_ENCRYPTION_DEK_CONFIG_PAGE 0x21
3156 #define AGSA_ENCRYPTION_CONTROL_PARM_PAGE 0x22
3157 #define AGSA_ENCRYPTION_HMAC_CONFIG_PAGE 0x23
3161 bit32 numberOfKeksPageCode; /* 0x20 */
3169 bit32 pageCode; /* 0x20 */
3174 #define AGSA_ENC_CONFIG_PAGE_KEK_NUMBER 0x0000FF00
3190 #define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_NUMBER 0xF0000000
3192 #define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_WAY 0x0F000000
3199 bit32 pageCode; /* 0x22 */
3266 #define AGSA_BIST_TEST 0x1
3267 #define AGSA_HMAC_TEST 0x2
3268 #define AGSA_SHA_TEST 0x3
3296 #define SA_OPR_MGMNT_FLAG_MASK 0x00003000
3339 bit32 pageCode; /* 0x06 */
3373 bit32 pageCode; /* 0 */
3605 #define PCIBAR0 0 /**< PCI Base Address 0 */
3763 #define COUNTER_SSP_START 0x000001
3764 #define COUNTER_SSP_ABORT 0x000002
3765 #define COUNTER_SSPABORT_CB 0x000004
3766 #define COUNTER_SSP_COMPLETEED 0x000008
3767 #define COUNTER_SMP_START 0x000010
3768 #define COUNTER_SMP_ABORT 0x000020
3769 #define COUNTER_SMPABORT_CB 0x000040
3770 #define COUNTER_SMP_COMPLETEED 0x000080
3771 #define COUNTER_SATA_START 0x000100
3772 #define COUNTER_SATA_ABORT 0x000200
3773 #define COUNTER_SATAABORT_CB 0x000400
3774 #define COUNTER_SATA_COMPLETEED 0x000800
3775 #define COUNTER_ECHO_SENT 0x001000
3776 #define COUNTER_ECHO_CB 0x002000
3777 #define COUNTER_UNKWN_IOMB 0x004000
3778 #define COUNTER_OUR_INT 0x008000
3779 #define COUNTER_SPUR_INT 0x010000
3780 #define ALL_COUNTERS 0xFFFFFF
3796 #define SA_PTNFE_POISION_TLP 0 /* Disable if zero default setting */
3802 #define SA_MDFD_MULTI_DATA_FETCH 0 /* Enable if zero default setting */
3808 #define SA_ARBTE 0 /* Disable if zero default setting */
3812 #define SA_OUTBOUND_COALESCE 0 /* Disable if zero */
3873 #define EnableFPGA_TEST_ICCcontrol 0x01
3874 #define EnableFPGA_TEST_ReadDEV 0x02
3875 #define EnableFPGA_TEST_WriteCALAll 0x04
3876 #define EnableFPGA_TEST_ReconfigSASParams 0x08
3877 #define EnableFPGA_TEST_LocalPhyControl 0x10
3878 #define EnableFPGA_TEST_PortControl 0x20
3897 #define OSSA_ENCRYPT_ENGINE_FAILURE_MASK 0x00FF0000 /* Encrypt Engine failed the BIST Tes…
3898 #define OSSA_ENCRYPT_SEEPROM_NOT_FOUND 0x01 /* SEEPROM is not installed. This condition i…
3899 #define OSSA_ENCRYPT_SEEPROM_IPW_RD_ACCESS_TMO 0x02 /* SEEPROM access timeout detected while read…
3900 #define OSSA_ENCRYPT_SEEPROM_IPW_RD_CRC_ERR 0x03 /* CRC Error detected when reading initializa…
3901 #define OSSA_ENCRYPT_SEEPROM_IPW_INVALID 0x04 /* Initialization password read from SEEPROM …
3902 #define OSSA_ENCRYPT_SEEPROM_WR_ACCESS_TMO 0x05 /* access timeout detected while writing init…
3903 #define OSSA_ENCRYPT_FLASH_ACCESS_TMO 0x20 /* Timeout while reading flash memory. */
3904 #define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_TMO 0x21 /* Flash sector erase timeout while writing t…
3905 #define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_ERR 0x22 /* Flash sector erase failure while writing t…
3906 #define OSSA_ENCRYPT_FLASH_ECC_CHECK_ERR 0x23 /* Flash ECC check failure. */
3907 #define OSSA_ENCRYPT_FLASH_NOT_INSTALLED 0x24 /* Flash memory not installed, this error is …
3908 #define OSSA_ENCRYPT_INITIAL_KEK_NOT_FOUND 0x40 /* Initial KEK is not found in the flash memo…
3909 #define OSSA_ENCRYPT_AES_BIST_ERR 0x41 /* Built-In Test Failure */
3910 #define OSSA_ENCRYPT_KWP_BIST_FAILURE 0x42 /* Built-In Test Failed on Key Wrap Engine */
3912 /* 0x01:ENC_ERR_SEEPROM_NOT_INSTALLED */
3913 /* 0x02:ENC_ERR_SEEPROM_IPW_RD_ACCESS_TMO */
3914 /* 0x03:ENC_ERR_SEEPROM_IPW_RD_CRC_ERR */
3915 /* 0x04:ENC_ERR_SEEPROM_IPW_INVALID */
3916 /* 0x05:ENC_ERR_SEEPROM_WR_ACCESS_TMO */
3917 /* 0x20:ENC_ERR_FLASH_ACCESS_TMO */
3918 /* 0x21:ENC_ERR_FLASH_SECTOR_ERASE_TMO */
3919 /* 0x22:ENC_ERR_FLASH_SECTOR_ERASE_FAILURE */
3920 /* 0x23:ENC_ERR_FLASH_ECC_CHECK_FAILURE */
3921 /* 0x24:ENC_ERR_FLASH_NOT_INSTALLED */
3922 /* 0x40:ENC_ERR_INITIAL_KEK_NOT_FOUND */
3923 /* 0x41:ENC_ERR_AES_BIST_FAILURE */
3924 /* 0x42:ENC_ERR_KWP_BIST_FAILURE */
3930 #define OSSA_DIF_ENGINE_FAILURE_MASK 0x0F000000 /* DIF Engine failed the BIST Test */
3932 #define OSSA_DIF_ENGINE_0_BIST_FAILURE 0x1 /* DIF Engine 0 failed the BIST Test */
3933 #define OSSA_DIF_ENGINE_1_BIST_FAILURE 0x2 /* DIF Engine 1 failed the BIST Test */
3934 #define OSSA_DIF_ENGINE_2_BIST_FAILURE 0x4 /* DIF Engine 2 failed the BIST Test */
3935 #define OSSA_DIF_ENGINE_3_BIST_FAILURE 0x8 /* DIF Engine 3 failed the BIST Test */
3937 #define SA_ROLE_CAPABILITIES_CSP 0x001
3938 #define SA_ROLE_CAPABILITIES_OPR 0x002
3939 #define SA_ROLE_CAPABILITIES_SCO 0x004
3940 #define SA_ROLE_CAPABILITIES_STS 0x008
3941 #define SA_ROLE_CAPABILITIES_TST 0x010
3942 #define SA_ROLE_CAPABILITIES_KEK 0x020
3943 #define SA_ROLE_CAPABILITIES_DEK 0x040
3944 #define SA_ROLE_CAPABILITIES_IOS 0x080
3945 #define SA_ROLE_CAPABILITIES_FWU 0x100
3946 #define SA_ROLE_CAPABILITIES_PRM 0x200