Lines Matching +full:device +full:- +full:id +full:- +full:base
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
42 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */
78 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
97 /* Interesting values for PCI MSI-X */
105 u_int mte_vector; /* 1-based index into msix_vectors array. */
111 uint8_t msix_location; /* Offset of MSI-X capability registers. */
126 uint32_t id; member
131 uint8_t ht_slave; /* Non-zero if device is an HT slave. */
134 uint64_t ht_msiaddr; /* MSI mapping base address */
137 /* Interesting values for PCI-express */
139 uint8_t pcie_location; /* Offset of PCI-e capability registers. */
140 uint8_t pcie_type; /* Device type. */
141 uint16_t pcie_flags; /* Device capabilities register. */
142 uint16_t pcie_device_ctl; /* Device control register. */
146 uint16_t pcie_device_ctl2; /* Second device control register. */
153 uint8_t pcix_location; /* Offset of PCI-X capability registers. */
174 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */
178 device_t dev; /* device which owns this */
182 uint16_t subvendor; /* card vendor ID */
183 uint16_t subdevice; /* card device ID, assigned by card vendor */
184 uint16_t vendor; /* chip vendor ID */
185 uint16_t device; /* chip device ID, assigned by chip vendor */ member
193 uint8_t revid; /* chip revision ID */
204 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
218 struct pcicfg_msix msix; /* PCI MSI-X */
221 struct pcicfg_pcix pcix; /* PCI-X */
222 struct pcicfg_iov *iov; /* SR-IOV */
223 struct pcicfg_vf vf; /* SR-IOV Virtual Function */
227 /* additional type 1 device config header information (PCI to PCI bridge) */
230 pci_addr_t pmembase; /* base address of prefetchable memory */
232 uint32_t membase; /* base address of memory window */
234 uint32_t iobase; /* base address of port window */
241 /* additional type 2 device config header information (CardBus bridge) */
244 uint32_t membase0; /* base address of memory window */
246 uint32_t membase1; /* base address of memory window */
248 uint32_t iobase0; /* base address of port window */
250 uint32_t iobase1; /* base address of port window */
252 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
291 uint16_t device; member
304 .match_flag_device = 1, .device = (d)
317 "M16:mask;U16:vendor;U16:device;U16:subvendor;U16:subdevice;" \
324 const struct pci_device_table *id, size_t nelt);
375 PCI_ACCESSOR(device, DEVICE, uint16_t) in PCI_ACCESSOR()
500 * D0 State in which device is on and running. It is receiving full
502 * D1 Class-specific low-power state in which device context may or may not
505 * D2 Class-specific low-power state in which device context may or may
509 * D3hot State in which the device is off and not running. Device context is
510 * lost. Power can be removed from the device.
511 * D3cold Same as D3hot, but power has been removed from the device.
521 #define PCI_POWERSTATE_UNKNOWN -1
651 pci_get_id(device_t dev, enum pci_id_type type, uintptr_t *id) in pci_get_id() argument
653 return (PCI_GET_ID(device_get_parent(dev), dev, type, id)); in pci_get_id()
686 /* Can be used by drivers to manage the MSI-X table. */
720 * cdev switch for control device, initialised in generic PCI code