1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
38  * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
44 /* some PCI bus constants */
81 /* PCI config header registers for all devices */
125 /* PCI Spec rev 2.2: 0FFFFh is an invalid value for Vendor ID. */
135 #define	PCIY_PMG	0x01	/* PCI Power Management */
141 #define	PCIY_PCIX	0x07	/* PCI-X */
146 #define	PCIY_HOTPLUG	0x0c	/* PCI Hot-Plug */
147 #define	PCIY_SUBVENDOR	0x0d	/* PCI-PCI bridge subvendor ID */
148 #define	PCIY_AGP8X	0x0e	/* AGP 8x */
150 #define	PCIY_EXPRESS	0x10	/* PCI Express */
151 #define	PCIY_MSIX	0x11	/* MSI-X */
153 #define	PCIY_PCIAF	0x13	/* PCI Advanced Features */
154 #define	PCIY_EA		0x14	/* PCI Extended Allocation */
176 #define	PCIZ_MFVC	0x0008	/* Multi-Function Virtual Channel */
180 #define	PCIZ_CAC	0x000c	/* Configuration Access Correction -- obsolete */
182 #define	PCIZ_ARI	0x000e	/* Alternative Routing-ID Interpretation */
193 #define	PCIZ_SEC_PCIE	0x0019	/* Secondary PCI Express */
200 #define	PCIZ_M_PCIE	0x0020	/* PCIe over M-PHY */
203 #define	PCIZ_DVSEC	0x0023	/* Designated Vendor-Specific */
217 #define	PCIR_BAR(x)		(PCIR_BARS + (x) * 4)  argument
219 #define	PCI_RID2BAR(rid)	(((rid) - PCIR_BARS) / 4)
220 #define	PCI_BAR_IO(x)		(((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)  argument
221 #define	PCI_BAR_MEM(x)		(((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)  argument
227 #define	PCIM_BAR_MEM_1MB	2	/* Locate below 1MB in PCI <= 2.1 */
257 /* config registers for header type 1 (PCI-to-PCI bridge) devices */
329 /* PCI device class, subclass and programming interface definitions */
543 /* PCI power manangement */
600 /* PCI Message Signalled Interrupts (MSI) */
628 /* PCI Enhanced Allocation registers */
636 /* 0-5 map to BARs 0-5 respectively */
639 #define	PCIM_EA_BEI_BAR(x)	(((x) >> PCIM_EA_BEI_OFFSET) & 0xf)  argument
643 /* 9-14 map to VF BARs 0-5 respectively */
646 #define	PCIM_EA_BEI_RESERVED	0xf	/* Reserved - Treat like ENI */
651 #define	PCIM_EA_P_MEM		0x00	/* Non-Prefetch Memory */
655 #define	PCIM_EA_P_VF_MEM	0x04	/* VF Non-Prefetch Memory */
656 #define	PCIM_EA_P_BRIDGE_MEM	0x05	/* Bridge Non-Prefetch Memory */
659 /* 0x08-0xfc reserved */
668 #define	PCIM_EA_IS_64		0x00000002	/* 64-bit field flag */
674 /* PCI-X definitions */
722 /* For header type 1 devices (PCI-X bridges) */
774 /* PCI Vendor capability definitions */
778 /* PCI Device capability definitions */
781 /* PCI EHCI Debug Port definitions */
786 /* PCI-PCI Bridge Subvendor definitions */
789 /* PCI Express definitions */
826 #define	PCIEM_CTL_BRDG_CFG_RETRY	0x8000	/* PCI-E - PCI/PCI-X bridges */
965 /* MSI-X definitions */
982 /* PCI Advanced Features definitions */
1064 /* SR-IOV definitions */
1080 #define	PCIR_SRIOV_BAR(x)	(PCIR_SRIOV_BARS + (x) * 4)  argument
1082 /* Extended Capability Vendor-Specific definitions */
1090  * PCI Express Firmware Interface definitions
1094 #define	PCIM_OSC_SUPPORT_EXT_PCI_CONF	0x01	/* Extended PCI Config Space */
1097 #define	PCIM_OSC_SUPPORT_SEG_GROUP	0x08	/* PCI Segment Groups supported */
1134  * Publication # 48882 Revision: 3.09-PUB Date: October 2023