Lines Matching +full:hot +full:- +full:plug

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
140 #define	PCIY_CHSWP	0x06	/* CompactPCI Hot Swap */
141 #define	PCIY_PCIX	0x07	/* PCI-X */
146 #define	PCIY_HOTPLUG	0x0c	/* PCI Hot-Plug */
147 #define	PCIY_SUBVENDOR	0x0d	/* PCI-PCI bridge subvendor ID */
151 #define	PCIY_MSIX	0x11	/* MSI-X */
176 #define	PCIZ_MFVC	0x0008	/* Multi-Function Virtual Channel */
180 #define	PCIZ_CAC	0x000c	/* Configuration Access Correction -- obsolete */
182 #define	PCIZ_ARI	0x000e	/* Alternative Routing-ID Interpretation */
200 #define	PCIZ_M_PCIE	0x0020	/* PCIe over M-PHY */
203 #define	PCIZ_DVSEC	0x0023	/* Designated Vendor-Specific */
219 #define	PCI_RID2BAR(rid)	(((rid) - PCIR_BARS) / 4)
257 /* config registers for header type 1 (PCI-to-PCI bridge) devices */
636 /* 0-5 map to BARs 0-5 respectively */
643 /* 9-14 map to VF BARs 0-5 respectively */
646 #define	PCIM_EA_BEI_RESERVED	0xf	/* Reserved - Treat like ENI */
651 #define	PCIM_EA_P_MEM		0x00	/* Non-Prefetch Memory */
655 #define	PCIM_EA_P_VF_MEM	0x04	/* VF Non-Prefetch Memory */
656 #define	PCIM_EA_P_BRIDGE_MEM	0x05	/* Bridge Non-Prefetch Memory */
659 /* 0x08-0xfc reserved */
668 #define	PCIM_EA_IS_64		0x00000002	/* 64-bit field flag */
674 /* PCI-X definitions */
722 /* For header type 1 devices (PCI-X bridges) */
786 /* PCI-PCI Bridge Subvendor definitions */
826 #define	PCIEM_CTL_BRDG_CFG_RETRY	0x8000	/* PCI-E - PCI/PCI-X bridges */
965 /* MSI-X definitions */
1064 /* SR-IOV definitions */
1082 /* Extended Capability Vendor-Specific definitions */
1100 #define	PCIM_OSC_CTL_PCIE_HP		0x01	/* PCIe Native Hot Plug */
1101 #define	PCIM_OSC_CTL_SHPC_HP		0x02	/* SHPC Native Hot Plug */
1134  * Publication # 48882 Revision: 3.09-PUB Date: October 2023