Lines Matching +full:num +full:- +full:irqs
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
64 #define DBI_WR1(sc, reg, val) pci_dw_dbi_wr1((sc)->dev, reg, val)
65 #define DBI_WR2(sc, reg, val) pci_dw_dbi_wr2((sc)->dev, reg, val)
66 #define DBI_WR4(sc, reg, val) pci_dw_dbi_wr4((sc)->dev, reg, val)
67 #define DBI_RD1(sc, reg) pci_dw_dbi_rd1((sc)->dev, reg)
68 #define DBI_RD2(sc, reg) pci_dw_dbi_rd2((sc)->dev, reg)
69 #define DBI_RD4(sc, reg) pci_dw_dbi_rd4((sc)->dev, reg)
72 bus_write_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg), (val))
74 bus_read_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg))
94 MPASS(sc->dbi_res != NULL); in pci_dw_dbi_read()
98 return (bus_read_4(sc->dbi_res, reg)); in pci_dw_dbi_read()
100 return (bus_read_2(sc->dbi_res, reg)); in pci_dw_dbi_read()
102 return (bus_read_1(sc->dbi_res, reg)); in pci_dw_dbi_read()
104 device_printf(sc->dev, "Unsupported width: %d\n", width); in pci_dw_dbi_read()
115 MPASS(sc->dbi_res != NULL); in pci_dw_dbi_write()
119 bus_write_4(sc->dbi_res, reg, val); in pci_dw_dbi_write()
122 bus_write_2(sc->dbi_res, reg, val); in pci_dw_dbi_write()
125 bus_write_1(sc->dbi_res, reg, val); in pci_dw_dbi_write()
128 device_printf(sc->dev, "Unsupported width: %d\n", width); in pci_dw_dbi_write()
153 if (bus < sc->bus_start || bus > sc->bus_end || slot > PCI_SLOTMAX || in pci_dw_check_dev()
157 /* link is needed for access to all non-root busses */ in pci_dw_check_dev()
158 if (bus != sc->root_bus) { in pci_dw_check_dev()
159 rv = PCI_DW_GET_LINK(sc->dev, &status); in pci_dw_check_dev()
183 num_regions = sc->iatu_ur_size / DW_IATU_UR_STEP; in pci_dw_detect_out_atu_regions_unroll()
193 sc->num_out_regions = i; in pci_dw_detect_out_atu_regions_unroll()
208 device_printf(sc->dev, in pci_dw_detect_out_atu_regions_legacy()
218 * page-aligned address sticks. in pci_dw_detect_out_atu_regions_legacy()
228 sc->num_out_regions = i; in pci_dw_detect_out_atu_regions_legacy()
236 if (sc->iatu_ur_res) in pci_dw_detect_out_atu_regions()
257 (pa + size - 1) & 0xFFFFFFFF); in pci_dw_map_out_atu_unroll()
268 for (i = 10; i > 0; i--) { in pci_dw_map_out_atu_unroll()
275 device_printf(sc->dev, in pci_dw_map_out_atu_unroll()
293 DBI_WR4(sc, DW_IATU_LIMIT_ADDR, (pa + size - 1) & 0xFFFFFFFF); in pci_dw_map_out_atu_legacy()
300 for (i = 10; i > 0; i--) { in pci_dw_map_out_atu_legacy()
307 device_printf(sc->dev, in pci_dw_map_out_atu_legacy()
317 if (sc->iatu_ur_res) in pci_dw_map_out_atu()
339 DBI_WR1(sc, PCIR_PRIBUS_1, sc->root_bus); in pci_dw_setup_hw()
340 DBI_WR1(sc, PCIR_SECBUS_1, sc->sub_bus); in pci_dw_setup_hw()
341 DBI_WR1(sc, PCIR_SUBBUS_1, sc->bus_end); in pci_dw_setup_hw()
348 for (i = 0; i < min(sc->num_mem_ranges, sc->num_out_regions - 1); ++i) { in pci_dw_setup_hw()
350 sc->mem_ranges[i].host, sc->mem_ranges[i].pci, in pci_dw_setup_hw()
351 sc->mem_ranges[i].size); in pci_dw_setup_hw()
357 if (sc->num_mem_ranges + 1 < sc->num_out_regions && in pci_dw_setup_hw()
358 sc->io_range.size != 0) { in pci_dw_setup_hw()
360 rv = pci_dw_map_out_atu(sc, sc->num_mem_ranges + 1, in pci_dw_setup_hw()
361 IATU_CTRL1_TYPE_IO, sc->io_range.host, sc->io_range.pci, in pci_dw_setup_hw()
362 sc->io_range.size); in pci_dw_setup_hw()
370 switch (sc->num_lanes) { in pci_dw_setup_hw()
390 device_printf(sc->dev, in pci_dw_setup_hw()
391 "'num-lanes' property have invalid value: %d\n", in pci_dw_setup_hw()
392 sc->num_lanes); in pci_dw_setup_hw()
400 switch (sc->num_lanes) { in pci_dw_setup_hw()
442 sc->mem_ranges = malloc(nmem * sizeof(*sc->mem_ranges), M_DEVBUF, in pci_dw_decode_ranges()
444 sc->num_mem_ranges = nmem; in pci_dw_decode_ranges()
450 if (sc->io_range.size != 0) { in pci_dw_decode_ranges()
451 device_printf(sc->dev, in pci_dw_decode_ranges()
457 sc->io_range = ranges[i]; in pci_dw_decode_ranges()
458 if (sc->io_range.size > UINT32_MAX) { in pci_dw_decode_ranges()
459 device_printf(sc->dev, in pci_dw_decode_ranges()
463 sc->io_range.size = UINT32_MAX; in pci_dw_decode_ranges()
468 MPASS(nmem < sc->num_mem_ranges); in pci_dw_decode_ranges()
469 sc->mem_ranges[nmem] = ranges[i]; in pci_dw_decode_ranges()
470 if (sc->mem_ranges[nmem].size > UINT32_MAX) { in pci_dw_decode_ranges()
471 device_printf(sc->dev, in pci_dw_decode_ranges()
475 sc->mem_ranges[nmem].size = UINT32_MAX; in pci_dw_decode_ranges()
481 MPASS(nmem == sc->num_mem_ranges); in pci_dw_decode_ranges()
484 device_printf(sc->dev, in pci_dw_decode_ranges()
492 free(sc->mem_ranges, M_DEVBUF); in pci_dw_decode_ranges()
496 /*-----------------------------------------------------------------------------
516 if (bus == sc->root_bus) { in pci_dw_read_config()
517 res = (sc->dbi_res); in pci_dw_read_config()
521 if (bus == sc->sub_bus) in pci_dw_read_config()
526 sc->cfg_pa, addr, sc->cfg_size); in pci_dw_read_config()
529 res = sc->cfg_res; in pci_dw_read_config()
563 if (bus == sc->root_bus) { in pci_dw_write_config()
564 res = (sc->dbi_res); in pci_dw_write_config()
568 if (bus == sc->sub_bus) in pci_dw_write_config()
573 sc->cfg_pa, addr, sc->cfg_size); in pci_dw_write_config()
576 res = sc->cfg_res; in pci_dw_write_config()
596 int maxcount, int *irqs) in pci_dw_alloc_msi() argument
607 irqs)); in pci_dw_alloc_msi()
611 pci_dw_release_msi(device_t pci, device_t child, int count, int *irqs) in pci_dw_release_msi() argument
620 return (intr_release_msi(pci, child, msi_parent, count, irqs)); in pci_dw_release_msi()
687 /*-----------------------------------------------------------------------------
697 return (sc->dmat); in pci_dw_get_dma_tag()
708 sc->dev = dev; in pci_dw_init()
709 sc->node = ofw_bus_get_node(dev); in pci_dw_init()
711 mtx_init(&sc->mtx, "pci_dw_mtx", NULL, MTX_DEF); in pci_dw_init()
714 sc->bus_start = 0; in pci_dw_init()
715 sc->bus_end = 255; in pci_dw_init()
716 sc->root_bus = 0; in pci_dw_init()
717 sc->sub_bus = 1; in pci_dw_init()
720 if (!sc->coherent) in pci_dw_init()
721 sc->coherent = OF_hasprop(sc->node, "dma-coherent"); in pci_dw_init()
723 rv = OF_getencprop(sc->node, "num-lanes", &sc->num_lanes, in pci_dw_init()
724 sizeof(sc->num_lanes)); in pci_dw_init()
725 if (rv != sizeof(sc->num_lanes)) in pci_dw_init()
726 sc->num_lanes = 1; in pci_dw_init()
727 if (sc->num_lanes != 1 && sc->num_lanes != 2 && in pci_dw_init()
728 sc->num_lanes != 4 && sc->num_lanes != 8) { in pci_dw_init()
730 "invalid number of lanes: %d\n",sc->num_lanes); in pci_dw_init()
731 sc->num_lanes = 0; in pci_dw_init()
737 rv = ofw_bus_find_string_index(sc->node, "reg-names", "config", &rid); in pci_dw_init()
743 sc->cfg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in pci_dw_init()
745 if (sc->cfg_res == NULL) { in pci_dw_init()
753 sc->cfg_size = rman_get_size(sc->cfg_res); in pci_dw_init()
754 sc->cfg_pa = rman_get_start(sc->cfg_res) ; in pci_dw_init()
757 device_printf(dev, "Bus is%s cache-coherent\n", in pci_dw_init()
758 sc->coherent ? "" : " not"); in pci_dw_init()
767 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ in pci_dw_init()
769 &sc->dmat); in pci_dw_init()
776 rv = pci_dw_decode_ranges(sc, sc->ofw_pci.sc_range, in pci_dw_init()
777 sc->ofw_pci.sc_nrange); in pci_dw_init()
787 rv = ofw_bus_find_string_index(sc->node, "reg-names", "atu", &rid); in pci_dw_init()
789 sc->iatu_ur_res = bus_alloc_resource_any(dev, in pci_dw_init()
791 if (sc->iatu_ur_res == NULL) { in pci_dw_init()
798 sc->iatu_ur_offset = 0; in pci_dw_init()
799 sc->iatu_ur_size = rman_get_size(sc->iatu_ur_res); in pci_dw_init()
801 sc->iatu_ur_res = sc->dbi_res; in pci_dw_init()
802 sc->iatu_ur_offset = DW_DEFAULT_IATU_UR_DBI_OFFSET; in pci_dw_init()
803 sc->iatu_ur_size = DW_DEFAULT_IATU_UR_DBI_SIZE; in pci_dw_init()
816 device_printf(sc->dev, "Detected outbound iATU regions: %d\n", in pci_dw_init()
817 sc->num_out_regions); in pci_dw_init()