Lines Matching +full:irqs +full:- +full:map +full:- +full:range
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
65 #define DBI_WR1(sc, reg, val) pci_dw_dbi_wr1((sc)->dev, reg, val)
66 #define DBI_WR2(sc, reg, val) pci_dw_dbi_wr2((sc)->dev, reg, val)
67 #define DBI_WR4(sc, reg, val) pci_dw_dbi_wr4((sc)->dev, reg, val)
68 #define DBI_RD1(sc, reg) pci_dw_dbi_rd1((sc)->dev, reg)
69 #define DBI_RD2(sc, reg) pci_dw_dbi_rd2((sc)->dev, reg)
70 #define DBI_RD4(sc, reg) pci_dw_dbi_rd4((sc)->dev, reg)
73 bus_write_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg), (val))
75 bus_read_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg))
95 MPASS(sc->dbi_res != NULL);
99 return (bus_read_4(sc->dbi_res, reg));
101 return (bus_read_2(sc->dbi_res, reg));
103 return (bus_read_1(sc->dbi_res, reg));
105 device_printf(sc->dev, "Unsupported width: %d\n", width);
116 MPASS(sc->dbi_res != NULL);
120 bus_write_4(sc->dbi_res, reg, val);
123 bus_write_2(sc->dbi_res, reg, val);
126 bus_write_1(sc->dbi_res, reg, val);
129 device_printf(sc->dev, "Unsupported width: %d\n", width);
154 if (bus < sc->bus_start || bus > sc->bus_end || slot > PCI_SLOTMAX ||
158 /* link is needed for access to all non-root busses */
159 if (bus != sc->root_bus) {
160 rv = PCI_DW_GET_LINK(sc->dev, &status);
184 num_regions = sc->iatu_ur_size / DW_IATU_UR_STEP;
194 sc->num_out_regions = i;
209 device_printf(sc->dev,
219 * page-aligned address sticks.
229 sc->num_out_regions = i;
237 if (sc->iatu_ur_res)
258 (pa + size - 1) & 0xFFFFFFFF);
269 for (i = 10; i > 0; i--) {
276 device_printf(sc->dev,
277 "Cannot map outbound region %d in unroll mode iATU\n", idx);
294 DBI_WR4(sc, DW_IATU_LIMIT_ADDR, (pa + size - 1) & 0xFFFFFFFF);
301 for (i = 10; i > 0; i--) {
308 device_printf(sc->dev,
309 "Cannot map outbound region %d in legacy mode iATU\n", idx);
313 /* Map one outbound ATU region */
318 if (sc->iatu_ur_res)
340 DBI_WR1(sc, PCIR_PRIBUS_1, sc->root_bus);
341 DBI_WR1(sc, PCIR_SECBUS_1, sc->sub_bus);
342 DBI_WR1(sc, PCIR_SUBBUS_1, sc->bus_end);
349 for (i = 0; i < min(sc->num_mem_ranges, sc->num_out_regions - 1); ++i) {
351 sc->mem_ranges[i].host, sc->mem_ranges[i].pci,
352 sc->mem_ranges[i].size);
358 if (sc->num_mem_ranges + 1 < sc->num_out_regions &&
359 sc->io_range.size != 0) {
361 rv = pci_dw_map_out_atu(sc, sc->num_mem_ranges + 1,
362 IATU_CTRL1_TYPE_IO, sc->io_range.host, sc->io_range.pci,
363 sc->io_range.size);
371 switch (sc->num_lanes) {
391 device_printf(sc->dev,
392 "'num-lanes' property have invalid value: %d\n",
393 sc->num_lanes);
401 switch (sc->num_lanes) {
443 sc->mem_ranges = malloc(nmem * sizeof(*sc->mem_ranges), M_DEVBUF,
445 sc->num_mem_ranges = nmem;
451 if (sc->io_range.size != 0) {
452 device_printf(sc->dev,
453 "Duplicated IO range found in DT\n");
458 sc->io_range = ranges[i];
459 if (sc->io_range.size > UINT32_MAX) {
460 device_printf(sc->dev,
464 sc->io_range.size = UINT32_MAX;
469 MPASS(nmem < sc->num_mem_ranges);
470 sc->mem_ranges[nmem] = ranges[i];
471 if (sc->mem_ranges[nmem].size > UINT32_MAX) {
472 device_printf(sc->dev,
476 sc->mem_ranges[nmem].size = UINT32_MAX;
482 MPASS(nmem == sc->num_mem_ranges);
485 device_printf(sc->dev,
486 "Missing required memory range in DT\n");
493 free(sc->mem_ranges, M_DEVBUF);
497 /*-----------------------------------------------------------------------------
517 if (bus == sc->root_bus) {
518 res = (sc->dbi_res);
522 if (bus == sc->sub_bus)
527 sc->cfg_pa, addr, sc->cfg_size);
530 res = sc->cfg_res;
564 if (bus == sc->root_bus) {
565 res = (sc->dbi_res);
569 if (bus == sc->sub_bus)
574 sc->cfg_pa, addr, sc->cfg_size);
577 res = sc->cfg_res;
597 int maxcount, int *irqs)
608 irqs));
612 pci_dw_release_msi(device_t pci, device_t child, int count, int *irqs)
621 return (intr_release_msi(pci, child, msi_parent, count, irqs));
688 /*-----------------------------------------------------------------------------
698 return (sc->dmat);
709 sc->dev = dev;
710 sc->node = ofw_bus_get_node(dev);
712 mtx_init(&sc->mtx, "pci_dw_mtx", NULL, MTX_DEF);
715 sc->bus_start = 0;
716 sc->bus_end = 255;
717 sc->root_bus = 0;
718 sc->sub_bus = 1;
721 if (!sc->coherent)
722 sc->coherent = OF_hasprop(sc->node, "dma-coherent");
724 rv = OF_getencprop(sc->node, "num-lanes", &sc->num_lanes,
725 sizeof(sc->num_lanes));
726 if (rv != sizeof(sc->num_lanes))
727 sc->num_lanes = 1;
728 if (sc->num_lanes != 1 && sc->num_lanes != 2 &&
729 sc->num_lanes != 4 && sc->num_lanes != 8) {
731 "invalid number of lanes: %d\n",sc->num_lanes);
732 sc->num_lanes = 0;
738 rv = ofw_bus_find_string_index(sc->node, "reg-names", "config", &rid);
744 sc->cfg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
746 if (sc->cfg_res == NULL) {
754 sc->cfg_size = rman_get_size(sc->cfg_res);
755 sc->cfg_pa = rman_get_start(sc->cfg_res) ;
758 device_printf(dev, "Bus is%s cache-coherent\n",
759 sc->coherent ? "" : " not");
768 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */
770 &sc->dmat);
777 rv = pci_dw_decode_ranges(sc, sc->ofw_pci.sc_range,
778 sc->ofw_pci.sc_nrange);
788 rv = ofw_bus_find_string_index(sc->node, "reg-names", "atu", &rid);
790 sc->iatu_ur_res = bus_alloc_resource_any(dev,
792 if (sc->iatu_ur_res == NULL) {
799 sc->iatu_ur_offset = 0;
800 sc->iatu_ur_size = rman_get_size(sc->iatu_ur_res);
802 sc->iatu_ur_res = sc->dbi_res;
803 sc->iatu_ur_offset = DW_DEFAULT_IATU_UR_DBI_OFFSET;
804 sc->iatu_ur_size = DW_DEFAULT_IATU_UR_DBI_SIZE;
817 device_printf(sc->dev, "Detected outbound iATU regions: %d\n",
818 sc->num_out_regions);