Lines Matching +full:0 +full:x12340000
60 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
80 #define PCI_BUS_MASK 0xFF
81 #define PCI_SLOT_MASK 0x1F
82 #define PCI_FUNC_MASK 0x07
83 #define PCI_REG_MASK 0xFFF
85 #define IATU_CFG_BUS(bus) ((uint64_t)((bus) & 0xff) << 24)
86 #define IATU_CFG_SLOT(slot) ((uint64_t)((slot) & 0x1f) << 19)
87 #define IATU_CFG_FUNC(func) ((uint64_t)((func) & 0x07) << 16)
106 return (0xFFFFFFFF);
161 if (rv != 0 || !status)
167 if (slot > 0 || func > 0)
175 return (DBI_RD4(sc, DW_IATU_VIEWPORT) == 0xFFFFFFFFU);
186 for (i = 0; i < num_regions; ++i) {
188 0x12340000);
190 if (reg != 0x12340000)
196 return (0);
206 DBI_WR4(sc, DW_IATU_VIEWPORT, IATU_REGION_INDEX(~0U));
208 if (reg > IATU_REGION_INDEX(~0U)) {
221 for (i = 0; i < num_viewports; ++i) {
223 DBI_WR4(sc, DW_IATU_LWR_TARGET_ADDR, 0x12340000);
225 if (reg != 0x12340000)
231 return (0);
250 if (size == 0)
251 return (0);
254 pa & 0xFFFFFFFF);
256 (pa >> 32) & 0xFFFFFFFF);
258 (pa + size - 1) & 0xFFFFFFFF);
260 pci_addr & 0xFFFFFFFF);
262 (pci_addr >> 32) & 0xFFFFFFFF);
269 for (i = 10; i > 0; i--) {
272 return (0);
288 if (size == 0)
289 return (0);
292 DBI_WR4(sc, DW_IATU_LWR_BASE_ADDR, pa & 0xFFFFFFFF);
293 DBI_WR4(sc, DW_IATU_UPPER_BASE_ADDR, (pa >> 32) & 0xFFFFFFFF);
294 DBI_WR4(sc, DW_IATU_LIMIT_ADDR, (pa + size - 1) & 0xFFFFFFFF);
295 DBI_WR4(sc, DW_IATU_LWR_TARGET_ADDR, pci_addr & 0xFFFFFFFF);
296 DBI_WR4(sc, DW_IATU_UPPER_TARGET_ADDR, (pci_addr >> 32) & 0xFFFFFFFF);
301 for (i = 10; i > 0; i--) {
304 return (0);
337 DBI_WR4(sc, PCIR_BAR(0), 4);
338 DBI_WR4(sc, PCIR_BAR(1), 0);
349 for (i = 0; i < min(sc->num_mem_ranges, sc->num_out_regions - 1); ++i) {
353 if (rv != 0)
359 sc->io_range.size != 0) {
364 if (rv != 0)
370 reg &= ~PORT_LINK_CAPABLE(~0);
400 reg &= ~GEN2_CTRL_NUM_OF_LANES(~0);
427 return (0);
436 nmem = 0;
437 for (i = 0; i < nranges; i++) {
447 nmem = 0;
448 for (i = 0; i < nranges; i++) {
451 if (sc->io_range.size != 0) {
484 if (nmem == 0) {
490 return (0);
515 return (0xFFFFFFFFU);
526 rv = pci_dw_map_out_atu(sc, 0, type,
528 if (rv != 0)
529 return (0xFFFFFFFFU);
544 data = 0xFFFFFFFFU;
573 rv = pci_dw_map_out_atu(sc, 0, type,
575 if (rv != 0)
604 if (rv != 0)
619 if (rv != 0)
633 if (rv != 0)
647 if (rv != 0)
660 if (rv != 0)
681 if (rv != 0)
685 return (0);
715 sc->bus_start = 0;
717 sc->root_bus = 0;
732 sc->num_lanes = 0;
737 rid = 0;
739 if (rv != 0) {
761 1, 0, /* alignment, bounds */
768 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */
771 if (rv != 0)
775 if (rv != 0)
779 if (rv != 0)
787 rid = 0;
789 if (rv == 0) {
799 sc->iatu_ur_offset = 0;
813 if (rv != 0)
821 if (rv != 0)
826 return (0);