675 #define	REG(n, w)	PCIB_READ_CONFIG(pcib, b, s, f, n, w)  in pci_hdrtypedata()  macro
678 		cfg->subvendor      = REG(PCIR_SUBVEND_0, 2);  in pci_hdrtypedata()
679 		cfg->subdevice      = REG(PCIR_SUBDEV_0, 2);  in pci_hdrtypedata()
680 		cfg->mingnt         = REG(PCIR_MINGNT, 1);  in pci_hdrtypedata()
681 		cfg->maxlat         = REG(PCIR_MAXLAT, 1);  in pci_hdrtypedata()
685 		cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1);  in pci_hdrtypedata()
686 		cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1);  in pci_hdrtypedata()
687 		cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1);  in pci_hdrtypedata()
688 		cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1);  in pci_hdrtypedata()
689 		cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2);  in pci_hdrtypedata()
693 		cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1);  in pci_hdrtypedata()
694 		cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1);  in pci_hdrtypedata()
695 		cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1);  in pci_hdrtypedata()
696 		cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1);  in pci_hdrtypedata()
697 		cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2);  in pci_hdrtypedata()
698 		cfg->subvendor      = REG(PCIR_SUBVEND_2, 2);  in pci_hdrtypedata()
699 		cfg->subdevice      = REG(PCIR_SUBDEV_2, 2);  in pci_hdrtypedata()
703 #undef REG  in pci_hdrtypedata()
710 #define	REG(n, w)	PCIB_READ_CONFIG(pcib, b, s, f, n, w)  in pci_read_device()  macro
713 	vid = REG(PCIR_VENDOR, 2);  in pci_read_device()
717 	did = REG(PCIR_DEVICE, 2);  in pci_read_device()
747 	cfg->cmdreg		= REG(PCIR_COMMAND, 2);  in pci_fill_devinfo()
748 	cfg->statreg		= REG(PCIR_STATUS, 2);  in pci_fill_devinfo()
749 	cfg->baseclass		= REG(PCIR_CLASS, 1);  in pci_fill_devinfo()
750 	cfg->subclass		= REG(PCIR_SUBCLASS, 1);  in pci_fill_devinfo()
751 	cfg->progif		= REG(PCIR_PROGIF, 1);  in pci_fill_devinfo()
752 	cfg->revid		= REG(PCIR_REVID, 1);  in pci_fill_devinfo()
753 	cfg->hdrtype		= REG(PCIR_HDRTYPE, 1);  in pci_fill_devinfo()
754 	cfg->cachelnsz		= REG(PCIR_CACHELNSZ, 1);  in pci_fill_devinfo()
755 	cfg->lattimer		= REG(PCIR_LATTIMER, 1);  in pci_fill_devinfo()
756 	cfg->intpin		= REG(PCIR_INTPIN, 1);  in pci_fill_devinfo()
757 	cfg->intline		= REG(PCIR_INTLINE, 1);  in pci_fill_devinfo()
768 	if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)  in pci_fill_devinfo()
794 #undef REG
799 #define	REG(n, w)	PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \  in pci_ea_fill_info()  macro
816 	num_ent = REG(PCIR_EA_NUM_ENT, 2);  in pci_ea_fill_info()
831 		val = REG(ptr, 4);  in pci_ea_fill_info()
836 			dw[b] = REG(ptr, 4);  in pci_ea_fill_info()
868 #undef REG
873 #define	REG(n, w)	PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)  in pci_read_cap()  macro
892 	nextptr = REG(ptrptr, 1);	/* sanity check? */  in pci_read_cap()
906 		nextptr = REG(ptr + PCICAP_NEXTPTR, 1);  in pci_read_cap()
909 		switch (REG(ptr + PCICAP_ID, 1)) {  in pci_read_cap()
912 			cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);  in pci_read_cap()
916 			val = REG(ptr + PCIR_HT_COMMAND, 2);  in pci_read_cap()
926 					addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,  in pci_read_cap()
929 					addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,  in pci_read_cap()
949 			cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);  in pci_read_cap()
953 			cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);  in pci_read_cap()
954 			val = REG(ptr + PCIR_MSIX_TABLE, 4);  in pci_read_cap()
958 			val = REG(ptr + PCIR_MSIX_PBA, 4);  in pci_read_cap()
970 				val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);  in pci_read_cap()
995 			val = REG(ptr + PCIER_FLAGS, 2);  in pci_read_cap()
1041 	while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {  in pci_read_vpd_reg()
1046 	*data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));  in pci_read_vpd_reg()
1061 	while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
1386 #undef REG  in pci_read_vpd()
4225 #define	REG(n, w)	PCIB_READ_CONFIG(pcib, busno, s, f, n, w)  in pci_add_children()  macro
4256 		if (REG(PCIR_VENDOR, 2) == PCIV_INVALID)  in pci_add_children()
4258 		hdrtype = REG(PCIR_HDRTYPE, 1);  in pci_add_children()
4266 #undef REG  in pci_add_children()
4272 #define	REG(n, w)	PCIB_READ_CONFIG(pcib, busno, s, f, n, w)  in pci_rescan_method()  macro
4299 		if (REG(PCIR_VENDOR, 2) == PCIV_INVALID)  in pci_rescan_method()
4302 		hdrtype = REG(PCIR_HDRTYPE, 1);  in pci_rescan_method()
4308 			if (REG(PCIR_VENDOR, 2) == PCIV_INVALID)  in pci_rescan_method()
4361 #undef REG  in pci_rescan_method()